MXIC MX29F400TTA-90, MX29F400TTC-12, MX29F400TTC-55, MX29F400TTC-70, MX29F400TTC-90 Datasheet

FEA TURES

MX29F400T/B

4M-BIT [512Kx8/256Kx16] CMOS FLASH MEMORY

• 524,288 x 8/262,144 x 16 switchable

• Single power supply operation

- 5.0V only operation for read, erase and program
operation

• Fast access time: 55/70/90/120ns

• Low power consumption

- 40mA maximum active current(5MHz)

- 1uA typical standby current

• Command register architecture

- Byte/word Programming (7us/12us typical)

- Sector Erase (Sector structure 16K-Bytex1, 8K­Bytex2, 32K-Bytex1, and 64K-Byte x7)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with
Erase Suspend capability.

- Automatically program and verify data at specified
address

• Erase suspend/Erase Resume

- Suspends an erase operation to read data from, or
program data to, another sector that is not being
erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program and

erase cycle completion.

• Ready/Busy pin (RY/BY)

- Provides a hardware method of detecting program or
erase cycle completion.

- Sector protect/unprotect for 5V only system or 5V/
12V system.

• Sector protection

- Hardware method to disable any combination of
sectors from program or erase operations

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 44-pin SOP

- 48-pin TSOP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

• 20 years data retention

GENERAL DESCRIPTION

The MX29F400T/B is a 4-mega bit Flash memory orga­nized as 512K bytes of 8 bits or 256K words of 16 bits.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memory . The MX29F400T/B is packaged in 44-pin SOP,
48-pin TSOP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.

The standard MX29F400T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces­sors without wait states. To eliminate bus contention,
the MX29F400T/B has separate chip enable (CE) and
output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F400T/B uses a command register to manage this
functionality. The command register allows for 100%

P/N:PM0439 REV. 1.6 , NOV. 12, 2001

TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi­mum EPROM compatibility.

MXIC Flash technology reliably stores memory contents
even after 100,000 erase and prog ram cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy­cling. The MX29F400T/B uses a 5.0V±10% VCC sup-
ply to perform the High Reliability Erase and auto Pro­gram/Erase algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro­tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.

1

MX29F400T/B

PIN CONFIGURATIONS

44 SOP(500 mil)

RESET

NC

RY/BY

A17

CE

GND

OE
Q0
Q8
Q1
Q9
Q2

Q10

Q3

Q11

2
3
4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12
13
14
15
16
17
18
19
20
21
22

44

WE

43

A8

42

A9

41

A10

40

A11

39

A12

38

A13

37

A14

36

A15

35

A16

34

BYTE

33

GND

32

Q15/A-1

31

MX29F400T/B

Q7

30

Q14

29

Q6

28

Q13

27

Q5

26

Q12

25

Q4

24

VCC

23

48 TSOP (Standard Type) (12mm x 20mm)

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A17 Address Input
Q0~Q14 Data Input/Output
Q15/A-1 Q15(Word mode)/LSB addr(Byte mode)
CE Chip Enable Input
WE Write Enable Input
BYTE Word/Byte Selction input
RESET Hardware Reset Pin/Sector Protect Unlock
OE Output Enable Input
RY/BY Ready/Busy Output
VCC Power Supply Pin (+5V)
GND Ground Pin

A15
A14
A13
A12
A11
A10

RESET

RY/BY

A17

1
2
3
4
5
6
7

A9

8

A8

9

NC

10

NC

11

WE

12
13

NC

14

NC

15
16

NC

17
18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

MX29F400T/B

48

A16

47

BYTE

46

GND

45

Q15/A-1

44

Q7

43

Q14

42

Q6

41

Q13

40

Q5

39

Q12

38

Q4

37

VCC

36

Q11

35

Q3

34

Q10

33

Q2

32

Q9

31

Q1

30

Q8

29

Q0

28

OE

27

GND

26

CE

25

A0

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2

MX29F400T/B

SECTOR STRUCTURE

MX29F400T TOP BOOT SECTOR ADDRESS TABLE

Sector Size Address Range (in hexadecimal)
(Kbytes/ (x8) (x16)

Sector A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA0 0 0 0 X X X 64/32 00000h-0FFFFh 00000h-07FFFh
SA1 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh
SA2 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh
SA3 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh
SA4 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh
SA5 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh
SA6 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh
SA7 1 1 1 0 X X 32/16 70000h-77FFFh 38000h-3BFFFh
SA81111008/4 78000h-79FFFh 3C000h-3CFFFh
SA91111018/4 7A000h-7BFFFh 3D000h-3DFFFh
SA10 1 1111X16/8 7C000h-7FFFFh 3E000h-3FFFFh

MX29F400B BOTTOM BOOT SECTOR ADDRESS TABLE

Sector Size Address Range (in hexadecimal)
(Kbytes/ (x8) (x16)

Sector A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA000000X16/8 00000h-03FFFh 00000h-01FFFh
SA10000108/4 04000h-05FFFh 02000h-02FFFh
SA20000118/4 06000h-07FFFh 03000h-03FFFh
SA3 0 0 0 1 X X 32/16 08000h-0FFFFh 04000h-07FFFh
SA4 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh
SA5 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh
SA6 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh
SA7 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh
SA8 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh
SA9 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh
SA10 1 1 1 X X X 64/32 70000h-7FFFFh 38000h-3FFFFh

Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode.

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3

BLOCK DIAGRAM

MX29F400T/B

CE
OE

WE

A0-A17

CONTROL
INPUT

LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLTA GE

X-DECODER

MX29F400T/B

FLASH
ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

PGM

DATA

HV

ARRAY

SOURCE

HV

WRITE

STATE

MACHINE

(WSM)

STATE

REGISTER

COMMAND

DATA
DECODER

COMMAND

DATA LATCH

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Q0-Q15/A-1

PROGRAM

DATA LATCH

I/O BUFFER

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4

MX29F400T/B

AUTOMATIC PROGRAMMING

The MX29F400T/B is byte programmable using the Au­tomatic Programming algorithm. The Automatic Pro­gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29F400T/B is less than 4 sec­onds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
T ypical erasure at room temper ature is accomplished in
less than 4 second. The A utomatic Erase algorithm au­tomatically programs the entire array prior to electrical
erase. The timing and v erification of electrical erase are
controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F400T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle.
The Automatic Sector Erase algorithm automatically pro­grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are con­trolled internally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The de vice automatically
times the programming pulse width, provides the pro­gram verification, and counts the number of sequences.
A status bit similar to DAT A polling and a status bit tog­gling between consecutive read cycles, provide feed­back to the user as to the status of the programming
operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan­dard microprocessor write timings. The device will auto­matically pre-program and verify the entire arra y. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu­tive read cycles provides feedback to the user as to the
status of the programming operation.

Register contents serve as inputs to an internal state­machine which controls the erase and programming cir­cuitry . During write cycles, the command register inter­nally latches address and data needed for the program­ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichev er hap­pens first .

MXIC's Flash technology combines years of EPROM
experience to produce the highest lev els of quality , reli­ability , and cost eff ectiveness. The MX29F400T/B elec­trically erases all bits simultaneously using Fowler­Nordheim tunneling. The bytes are programmed b y us­ing the EPROM programming mechanism of hot elec­tron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis­ter to respond to its full command set.

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5

MX29F400T/B

T ABLE1. SOFTW ARE COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI
Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H
Verify x02H XX01H

Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H

x04H 01H

Porgram Word 4 555H AAH 2AAH 55H 555H A0H PA PD

Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD
Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55 H 555H 10H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H
Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55 H SA 30H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 3 0H
Sector Erase Suspend 1 XXXH B0H
Sector Erase Resume 1 XXXH 30H
Unlock for sector 6 555H AAH 2AAH 55 H 555H 8 0H 555H AAH 2AAH 55H 555H 20H
protect/unprotect

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code, A2~A17=do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, 23H/ABH (x8) and 2223H/22ABH (x16) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or
555H to Address A10~A-1 in byte mode.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A17 in either state.

4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00 H, it
means the sector is still not being protected.

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6

COMMAND DEFINITIONS

MX29F400T/B

Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read mode.

Note that the Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Sector Erase
operation is in progress. Either of the two reset com­mand sequences will reset the device(when applicable).

Table 1 defines the valid register command sequences.

T ABLE 2. MX29F400T/B BUS OPERATION

Pins CE OE WE A0 A1 A6 A9 Q0 ~ Q1 5
Mode
Read Silicon ID L L H L L X VID(2) C2H (Byte mode)
Manfacturer Code(1) 00C2H (Word mode)
Read Silicon ID L L H H L X VID(2) 23H/ABH (Byte mode)
Device Code(1) 2223H/22ABH (Word mode)
Read L L H A0 A1 A6 A9 D
Standby H XXXXXX HIGH Z
Output Disable L H H XXXX HIGH Z
Write L H L A0 A1 A6 A9 DIN(3)
Sector Protect with 12V L VID(2) L X X L VID(2) X
system(6)
Chip Unprotect with 12V L VID(2) L X X H VID(2) X
system(6)
Verify Sector Protect L L H X H X VID(2) Code(5)
with 12V system
Sector Protect without 12V L H L X X L H X
system (6)
Chip Unprotect without 12V L H L X X H H X
system (6)
Verify Sector Protect/Unprotect L L H X H X H Code(5)
without 12V system (7)
Reset X XXXXXX HIGH Z

OUT

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/XX00H means unprotected.
Code=01H/XX01H means protected.
A17~A12=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.
Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V system"
command.

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REV. 1.6, NOV. 12, 2001

MX29F400T/B

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg­ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com­mand must then be written to place the device in the
desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu­facturer and device codes must be accessible while the
device resides in the target system. PROM program­mers typically access signature codes by raising A9 to
a high voltage. Howe ver , multiplexing high v oltage onto
address lines is not generally desired system design
practice.

The MX29F400T/B contains a Silicon-ID-Read opera­tion to supplement traditional PROM programming meth­odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis­ter. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of 23H/2223H for MX29F400T, ABH/22ABH
for MX29F400B.

SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS

Chip erase is a six-bus cycle operation. There are tw o
"unlock" write cycles. These are followed b y writing the
"set-up" command 80H. Two more "unlock" write cy­cles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au­tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to pro vide any
control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).

If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE or CE, whichever happens later, pulse in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two con­secutive read cycles, at which time the device returns
to the Read mode.

T ABLE 3. EXP ANDED SILICON ID CODE

Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code Word VIL VIL 0 0H 1 1 0 0 0 0 1 0 00C2H

Byte VIL VIL X 1 1 0 0 0 0 1 0 C2H
Device code Word VIH VIL 22H 0 0 1 0 0 0 1 1 2223H
for MX29F400T Byte VIH VIL X 0 0 1 0 0 0 1 1 2 3 H
Device code Word VIH VIL 22H 1 0 1 0 1 0 1 1 22ABH
for MX29F400B Byte VIH VIL X 1 0 1 0 1 0 1 1 A BH
Sector Protection X VIH X 0 0 0 0 0 0 0 1 01H (Protected)
Verification X VIH X 0 0 0 0 0 0 0 0 00H (Unprotected)

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REV. 1.6, NOV. 12, 2001

SECTOR ERASE COMMANDS

MX29F400T/B

The Automatic Sector Erase does not require the de­vice to be entirely pre-programmed prior to executing
the Automatic Set-up Sector Erase command and Auto­matic Sector Erase command. Upon executing the Au­tomatic Sector Erase command, the device will auto­matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.

When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate

T able 4. Write Operation Status

Status Q7 Q6 Q 5 Q3 Q2 RY/BY

erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un­lock" write cycles. These are f ollowed by writing the set­up command 80H. Two more "unlock" write cycles are
then followed by the sector erase command 30H. The
sector address is latched on the falling edge of WEor
CE, whichever happens later , while the command(data)
is latched on the rising edge of WE or CE, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE or
CE, whichever happens later. Each successive sector
load cycle started by the falling edge of WE or CE, which­ever happens later, must begin within 30us from the
rising edge of the preceding WE or CE, whichev er hap­pens First, otherwise, the loading period ends and inter­nal auto sector erase cycle starts. (Monitor Q3 to deter­mine if the sector erase timer window is still open, see
section Q3, Sector Erase Timer.) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.

Note1 Note2

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No 0

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 No 0 N/A Toggle 1
(Erase Suspended Sector) Toggle

In Progress

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector)
Erase Suspend Program Q7 Toggle 0 N/A N/A 0

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No 0

Exceeded
Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

Erase Suspend Program Q7 Toggle 1 N/A N/A 0

Toggle

Toggle

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.

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9

MX29F400T/B

ERASE SUSPEND

This command only has meaning while the state ma­chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend com­mand is written during a sector erase operation, the de­vice requires a maximum of 100us to suspend the erase
operations. However , When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex­ecuted, the command register will initiate erase suspend
mode. The state machine will return to read mode auto­matically after suspend is ready . At this time, state ma­chine only allows the command register to respond to
the Read Memory Array, Erase Resume and program
commands.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro­gram operation is complete, the system can once again
read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM

tem is not required to provide further controls or timings.
The device will automatically provide an adequate inter­nally generated program pulse and verify margin.

If the program opetation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data
on Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read mode(no
program verify command is required).

DATA POLLING-Q7

The MX29F400T/B also features Data Polling as a
method to indicate to the host system that the Auto­matic Program or Erase algorithms are either in progress
or completed.

While the Automatic Programming algorithm is in opera­tion, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an at­tempt to read the device will produce the true data last
written to Q7. The Data P olling f eature is valid after the
rising edge of the fourth WEor CE, whichever happens
first, pulse of the four write pulse sequences for auto­matic program.

While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data P olling feature is valid after the rising
edge of the sixth WE or CE, whichever happens first
pulse of six write pulse sequences for automatic chip/
sector erase.

COMMANDS

T o initiate Automatic Progr am mode, A three-cycle com­mand sequence is required. There are two "unlock" write
cycles. These are f ollowed by writing the Automatic Pro­gram command A0H.

Once the Automatic Program command is initiated, the
next WEor CE, pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the
rising edge of the WE or CE, whichever happens first,
pulse. The rising edge of WE or CE, whiche ver happens
first, also begins the programming operation. The sys-

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The Data Polling f eature is active during Automatic Pro­gram/Erase algorithm or sector erase time-out.(see sec­tion Q3 Sector Erase Timer)

RY/BY :Read y/Busy

The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid
after the rising edge of the final WE or CE, whichever
happens first, pulse in the command sequence. Since
RY/BY is an open-dr ain output, several R Y/BY pins can
be tied together in parallel with a pull-up resistor to Vcc.

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MX29F400T/B

If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.)If the output is high (Ready), the device
is ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.

Table 4 sho ws the outputs f or R Y/BY.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an A utomatic Pro­gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE or CE, whichever
happens first, pulse in the command sequence(prior to
the program or erase operation), and during the sector
time-out.

During an Automatic Program or Erase algorithm opera­tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to con­trol the read cycles. When the operation is complete , Q6
stops toggling.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus­pended. When the de vice is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. Ho wever , the system m ust also use Q2
to determine which sectors are erasing or erase-sus­pended. Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program com­mand sequence is written, then returns to reading array
data.

Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo­rithm is complete.

Table 4 sho ws the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid af­ter the rising edge of the final WE or CE, whichev er hap­pens first, pulse in the command sequence.

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com­parison, indicates whether the device is actively eras­ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus , both status bits
are required for sectors and mode information. Refer to
Table 4 to compare outputs f or Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. T ypically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.

Howe v e r, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys­tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfuly completed the program or erase opera­tion. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta­tus as described in the previous paragraph. Alterna­tively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation.

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MX29F400T/B

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex­ceeded the specified limits(internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data Polling and Toggle Bit
are the only operating functions of the device under this
condition.

If this time-out condition occurs during sector erase op­eration, it specifies that a particular sector is bad and it
may not be reused. Howe ver , other sectors are still func­tional and may be used for the program or erase opera­tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute prog ram or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com­bination of sectors are bad.

If this time-out condition occurs during the byte program­ming operation, it specifies that the entire sector con­taining that byte is bad and this sector maynot be re­used, (other sectors are still functional and can be re­used).

The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Au­tomatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops tog­gling. Once the Device has exceeded timing limits, the
Q5 bit will indicate a "1". Please note that this is not a
device failure condition since the device was incorrectly
used.

DATA PROTECTION

resulting from VCC pow er-up and power-down transition
or system noise.

TEMPORARY SECT OR UNPROTECT

This feature allows temporary unprotection of previously
protected sector to change data in-system. The T empo­rary Sector Unprotect mode is activated by setting the
RESET pin to VID(11.5V-12.5V). During this mode, for­merly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin,all the previously protected sectors are pro­tected again.

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase com­mand sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com­mand has been accepted, the system software should
check the status of Q3 prior to and following each sub­sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.

The MX29F400T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi­tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of spe­cific command sequences. The device also incorpo­rates sever al features to prev ent inadvertent write cycles

P/N:PM0439

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. T o initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be­tween its VCC and GND .

REV. 1.6, NOV. 12, 2001

12

Temporary Sector Unprotect Operation

RESET = VID (Note 1)

Perform Erase or Program Operation

Temporary Sector Unprotect Completed(Note 2)

MX29F400T/B

Start

Operation Completed

RESET = VIH

Note :

1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V

2. All previously protected sectors are protected again.

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MX29F400T/B

TEMPORARY SECTOR UNPROTECT

Parameter Std. Description T est Setup AllSpeed Options Unit
tVIDR VID Rise and Fall Time (See Note) Min 50 0 ns
tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 us

Note:
Not 100% tested

Temporary Sector Unprotect Timing Diagram

12V

RESET

CE

WE

RY/BY

0 or 5V

tVIDR

tRSP

Program or Erase Command Sequence

0 or 5V

tVIDR

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