MXIC MX29F1615 Datasheet

FEATURES

PRELIMINARY

MX29F1615

16M-BIT [2M x8/1M x16] CMOS

SINGLE VOLTAGE FLASH EEPROM

• 5V ± 10% write and erase

• JEDEC-standard EEPROM commands

• Endurance:100 cycles

• Fast access time: 90/100/120ns

• Auto Erase and Auto Program Algorithms

- Automatically erases the whole chip

- Automatically programs and verifies data at specified addresses

• Status Register feature for detection of

program or erase cycle completion

• Low VCC write inhibit is equal to or less than 3.2V

GENERAL DESCRIPTION

The MX29F1615 is a 16-mega bit Flash memory organized as either 1M wordx16 or 2M bytex8. MXIC's Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memory. The MX29F1615 is packaged in 42-pin PDIP. It is designed to be reprogrammed and in standard EPROM programmers.

The standard MX29F1615 offers access times as fast as 90ns,allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29F1615 has separate chip enables(CE) and output enable (OE) control.

• Software and hardware data protection

• Page program operation

- Internal address and data latches for 64 words per page

- Page programming time: 0.9ms typical

• Low power dissipation

- 30mA typical active current

- 1uA typical standby current

• CMOS and TTL compatible inputs and outputs

• Package Type:

- 42 lead PDIP

To allow for simple in-system reprogrammability, the MX29F1615 requires high input voltages (10V) on BYTE/ VPP pin for programming. Reading data out of the device is similar to reading from an EPROM.

MXIC Flash technology reliably stores memory contents even after 100 cycles. The MXIC's cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F1615 uses a 5V ± 10% VCC supply to perform the Auto Erase and Auto Program algorithms.

MXIC's Flash memories augment EPROM functionality with electrical erasure and programming. The MX29F1615 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.

P/N: PM0615

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.

REV.1.1, JUN. 15, 2001

MX29F1615

PIN CONFIGURATIONS

42 PDIP(600mil)

A18

A17

GND

13 14 15 16 17 18 19 20 21

MX29F1615

Q0 Q8 Q1 Q9 Q2

Q10

Q11

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE/VPP GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC

PIN DESCRIPTION

SYMBOL PIN NAME

A0 - A19 Address Input Q0 - Q14 Data Input/Output Q15/A - 1 Q15(Word mode)/LSB addr.(Byte mode) CE Chip Enable Input OE Output Enable Input BYTE/VPP Word/Byte Selection Input/Write Enable

Input VCC Power Supply GND Ground Pin

P/N: PM0615

REV. 1.1, JUN. 15, 2001

BLOCK DIAGRAM

MX29F1615

CE OE

BYTE/VPP

Q15/A-1

A0-A19

CONTROL INPUT

LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLT A GE

X-DECODER

MX29F1615

FLASH ARRAY

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

PGM

DATA

ARRAY

SOURCE

WRITE

STATE

MACHINE

(WSM)

COMMAND INTERFACE

(CIR)

COMMAND

DATA DECODER

COMMAND

DATA LATCH

P/N: PM0615

Q0-Q15/A-1

PAGE PROGRAM

DATA LATCH

I/O BUFFER

REV. 1.1, JUN. 15, 2001

MX29F1615

Table1.PIN DESCRIPTIONS

SYMBOL TYPE NAME AND FUNCTION

A0 - A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally latched

during a write cycle.

Q0 - Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface

Register(CIR) write cycles. Outputs array,status and identifier data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled.

Q8 - Q14 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs

array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled

Q15/A -1 INPUT/OUTPUT Selects between high-byte data INPUT/OUTPUT(BYTE/VPP = HIGH) and LSB

ADDRESS(BYTE/VPP = LOW) for read operation.

CE INPUT CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,

decoders and sense amplifiers. With CE high, the device is de-selected and power consumption reduces to Standby level upon completion of any current program or erase operations. CE must be low to select the device. Device selection occurs with the latter falling edge of CE. The first rising edge of CE disables the device.

OE INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during a

read cycle OE is active low.

BYTE/VPP INPUT BYTE ENABLE: While operating read mode, BYTE/VPP Low places device in x8

mode. All data is then input or output on Q0-7 and Q8-14 float. AddressQ15/A1 selects between the high and low byte. While operating read mode, BYTE/VPP high places the device in x16 mode, and turns off the Q15/A-1 input buffer. Address A0, then becomes the lowest order address. Write Enable is active while

apply 10V on the BYTE/VPP pin. VC C DEVICE POWER SUPPLY(5V±10%) GND GROUND

P/N: PM0615

REV. 1.1, JUN. 15, 2001

MX29F1615

BUS OPERATION

Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

Table2.1 Bus Operations

Mode Notes CE OE BYTE/VPP A0 A 1 A9 Q0-Q7 Q8-Q14 Q15/A-1

Read 1,5 VIL VIL VIH/VIL X X X DOUT HighZ/DOUT VIL/VIH/DOUT Output Disable 1 VIL VIH VIH/VIL X X X High Z HIghZ High Z/X Standby 1 VIH X X X X X X X X Manufacturer ID 2,4 VIL VIL VIH/VIL VIL VIL VID C2H High Z/00H VIL/OB Device ID 2,4 VIL VIL VIH/VIL VIH VIL VID 6BH High Z/00H VIL/OB

MX29F1615 Write 1,3,6 VIL VIH VHH X X X DIN DIN DIN

NOTES :

1. X can be VIH or VIL for address or control pins.

2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes.

3. Commands for different Erase operations or Data program operations can only be successfully completed through proper command sequence.

4. VID = 11.5V- 12.5V.

5. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.

6.VHH=9.5V~10.5V

P/N: PM0615

REV. 1.1, JUN. 15, 2001

MX29F1615

WRITE OPERATIONS

Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon ID, Erase and Program command. In the event of a read command, the CIR simply points the read path at either the array or the silicon ID, depending on the specific read command given. For a program or erase cycle, the CIR informs the write state machine that a program or erase has been requested. During a program cycle, the write state machine will control the program sequences and the CIR

TABLE 3. COMMAND DEFINITIONS(Word-Wide Mode, BYTE/VPP=VHH)

Command Read/ Silicon Page Chip Read Clear Sequence Reset ID Read Program Erase Status Reg. Status Reg. Bus Write 4 4 4 6 4 3 Cycles Req'd First Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Data AAH AAH AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Data 55H 55H 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Data F0H 90H A0 H 80H 70H 50H Fourth Bus Addr RA 00H/01H PA 5555H X Read/Write Cycle Data RD C2H/6BH PD AAH SRD Fifth Bus Addr 2AAAH Write Cycle Data 55H Sixth Bus Addr 5555H Write Cycle Data 10H

will only respond to status reads. During a sector/chip erase cycle, the CIR will respond to status reads and erase suspend. After the write state machine has completed its task, it will allow the CIR to respond to its full command set. The CIR stays at read status register mode until the microprocessor issues another valid command sequence.

Device operations are selected by writing commands into the CIR. Table 3 below defines 16 Mbit flash command.

Notes:

1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA).

5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.

2. Bus operations are defined in Table 2.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the CE pulse.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of CE. SRD = Data read from status register.

5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.

P/N: PM0615

REV. 1.1, JUN. 15, 2001

DEVICE OPERATION

SILICON ID READ

MX29F1615

The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding

The manufacturer and device codes may also be read via the command register, for instances when the MX29F1615 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is

illustrated in Table 3. programming algorithm. This mode is functional over the entire temperature range of the device.

Byte 0 (A0=VIL) represents the manfacturer's code

(MXIC=C2H) and byte 1 (A0=VIH) the device identifier To activate this mode, the programming equipment must

code (MX29F1615=6BH). force VID (11.5V~12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0 and A1.

The Silicon ID Read mode will be terminated after the

following write command cycle.

Table 4. MX29F1615 Silion ID Codes

Type A19 A18 A17A16A1A0Code(HEX) Q7Q

Manufacturer Code X X X X VIL VIL C2H* 1 1 0 0 0 0 1 0 MX29F1615 Device Code X X X X VIL VIH 6BH 0 1 1 0 1 0 1 1

Q5Q4Q3Q2Q1Q

* MX29F1615 Manufacturer Code = C2H, Device Code = 6BH when BYTE/VPP = VIL MX29F1615 Manufacturer Code = 00C2H, Device Code = 006BH when BYTE/VPP= VIH

P/N: PM0615

REV. 1.1, JUN. 15, 2001

MX29F1615

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the CIR contents are altered by a valid command sequence.

The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

The MX29F1615 is accessed like an EPROM. When CE and OE are low and BYTE/VPP is high or low the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention.

Note that the read/reset command is not valid when program or erase is in progress.

PROGRAM

Any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed.

The device is programmed on a page basis. If a word of data within a page is to be changed, data for the entire page can be loaded into the device. Any word that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the words of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data word has been loaded into the device, successive words are entered in the same manner. The time between word loads must be less than 30us otherwise the load period could be teminated. A6 to A19 specify the page address, i.e., the device is page-aligned on 64 words boundary. The page address must be valid during each high to low transition of CE. A0 to A5 specify the byte address within the page. The word may be loaded in any order; sequential loading is not required. If a high to low transition of CE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The Auto page program terminates when status on Q7 is '1' at which time the device stays at read status register mode until the CIR contents are altered by a valid command sequence.

PAGE PROGRAM

To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock" write cycles. These are followed by writing the page program commandA0H.

Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine(WSM), no data will be written to the device.

After three-cycle command sequence is given, a word load is performed by applying a low pulse on the CE input with CE low (respectively) and OE high. The address is latched on the falling edge of CE, whichever occurs last. The data is latched by the first rising edge of CE. Maximum of 64 words of data may be loaded into each page by the same procedure as outlined in the page program section below.

P/N: PM0615

CHIP ERASE

Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command-80H. Two more "unlock" write cycles are then followed by the chip erase command-10H.

Chip erase does not require the user to program the device prior to erase.

The automatic erase begins on the rising edge of the last CE pulse in the command sequence and terminates when the status on Q7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.

REV. 1.1, JUN. 15, 2001

+ 18 hidden pages