MXIC MX29F1610A Datasheet

FEATURES

PRELIMINARY

MX29F1610A

16M-BIT [2M x8/1M x16] CMOS

SINGLE VOLTAGE FLASH EEPROM

• 5V ± 10% write and erase

• JEDEC-standard EEPROM commands

• Endurance:100,000 cycles

• Fast access time: 90/100/120ns

• Sector erase architecture

- 16 equal sectors of 128k bytes each

- Sector erase time: 1.3 s typical

• Auto Erase and Auto Program Algorithms

- Automatically erases any one of the sectors
or the whole chip with Erase Suspend capability

- Automatically programs and verifies data at
specified addresses

• Status Register feature for detection of

program or erase cycle completion

• Low VCC write inhibit is equal to or less than 3.2V

• Software and hardware data protection

GENERAL DESCRIPTION

The MX29F1610A is a 16-mega bit Flash memory
organized as either 1M wordx16 or 2M bytex8. The
MX29F1610A includes 16-128KB(131,072) blocks or 16­64KW(65,536) blocks. MXIC's Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX29F1610A is packaged
in 48-pin TSOP or 44-pin SOP. For 48-pin TSOP, CE2 and
RY/BY are extra pins compared with 44-pin SOP package.
This is to optimize the products (such as solid-state disk
drives or flash memory cards) control pin budget. All the
above three pins(CE2,RY/BY and PWD) plus one extra
VCC pin are not provided in 44-pin SOP. It is designed to
be reprogrammed and erased in-system or in-standard
EPROM programmers.

The standard MX29F1610A offers access times as fast as
90ns,allowing operation of high-speed microprocessors
without wait. To eliminate bus contention, the
MX29F1610A has separate chip enables(CE1 and CE2),
output enable (OE), and write enable (WE) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F1610A uses a command register to manage this

• Page program operation

- Internal address and data latches for
128 bytes/64 words per page

- Page programming time: 0.9ms typical

- Byte programming time: 7us in average

• Low power dissipation

- 30mA typical active current

- 1uA typical standby current

• CMOS and TTL compatible inputs and outputs

• Sector Protection

- Hardware method that can protect any combination
of sectors from write or erase operations.

• Deep Power-Down Input

- 1uA ICC typical

• Industry standard surface mount packaging

- 48 lead TSOP, TYPE I

- 44 lead SOP

functionality. The command register allows for 100% TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.

To allow for simple in-system reprogrammability, the
MX29F1610A does not require high input voltages for
programming. Five-volt-only commands determine the
operation of the device. Reading data out of the device
is similar to reading from an EPROM.

MXIC Flash technology reliably stores memory contents
even after 100,000 cycles. The MXIC's cell is designed
to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29F1610A uses a 5V ± 10% VCC supply to perform the
Auto Erase and Auto Program algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.

P/N: PM0506

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REV.1.7,JUN. 15, 2001

PIN CONFIGURATIONS

48 TSOP(TYPE I) (12mm x 20mm)

1

RY/BY

2

A16

3

A15

4

A14

5

A13

6

A12

7

A11

8

A10

9

A9

10

A8

11

A19

WP

WE
A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

VCC

12
13
14
15
16
17
18
19
20
21
22
23
24

(NORMAL TYPE)

MX29F1610A

MX29F1610A

48

PWD

47

BYTE

46

GND

45

Q15/A-1

44

Q7

43

Q14

42

Q6

41

Q13

40

Q5

39

Q12

38

Q4

37

VCC

36

Q11

35

Q3

34

Q10

33

Q2

32

Q9

31

Q1

30

Q8

29

Q0

28

OE

27

GND

26

CE1

25

CE2

PWD

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

Q11

Q3

Q10

Q2
Q9
Q1
Q8
Q0
OE

GND

CE1
CE2

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX29F1610A

(REVERSE TYPE)

1

RY/BY

2

A16

3

A15

4

A14

5

A13

6

A12

7

A11

8

A10

9

A9

10

A8

11

A19

12

WP

13

WE

14

A18

15

A17

16

A7

17

A6

18

A5

19

A4

20

A3

21

A2

22

A1

23

A0

24

VCC

44 SOP(500mil)

WE
A18
A17

CE1

GND

Q10

Q11

OE
Q0
Q8
Q1
Q9
Q2

Q3

PIN DESCRIPTION

WP

44

A19

2
3
4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12
13
14
15
16
17
18
19
20
21
22

43

A8

42

A9

41

A10

40

A11

39

A12

38

A13

37

A14

36

A15

35

A16

34

BYTE

33

GND

32

MX29F1610A

Q15/A-1

31

Q7

30

Q14

29

Q6

28

Q13

27

Q5

26

Q12

25

Q4

24

VCC

23

SYMBOL PIN NAME

A0 - A19 Address Input
Q0 - Q14 Data Input/Output
Q15/A - 1 Q15(Word mode)/LSB addr.(Byte mode)
CE1/CE2 Chip Enable Input
PWD Deep Power- Down Input
OE Output Enable Input
WE Write Enable Input
RY/BY Ready/Busy Output
WP Sector Write Protect Input
BYTE Word/Byte Selection Input
VCC Power Supply
GND Ground Pin

P/N: PM0506

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REV.1.7, JUN. 15, 2001

BLOCK DIAGRAM

MX29F1610A

WE

CE1/CE2

WP

PWD

BYTE

Q15/A-1

A0-A19

OE

CONTROL
INPUT

LOGIC

ADDRESS

LATCH

AND

BUFFER

PROGRAM/ERASE

HIGH VOLTAGE

X-DECODER

MX29F1610A

FLASH
ARRAY

Y-DECODER

Y-PASS GATE

ARRAY

SOURCE

HV

WRITE

STATE

RY/BY

MACHINE

(WSM)

COMMAND INTERFACE

REGISTER

(CIR)

COMMAND
DATA

DECODER

P/N: PM0506

Q0-Q15/A-1

SENSE

AMPLIFIER

I/O BUFFER

PGM

DATA

HV

PAGE
PROGRAM

DATA LATCH

3

COMMAND

DATA LATCH

REV.1.7, JUN. 15, 2001

MX29F1610A

Table1.PIN DESCRIPTIONS

SYMBOL TYPE NAME AND FUNCTION

A0 - A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally latched

during a write cycle.

Q0 - Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface

Register(CIR) write cycles. Outputs array,status and identifier data in the
appropriate read mode. Floated when the chip is de-selected or the outputs are
disabled.

Q8 - Q14 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs

array, identifier data in the appropriate read mode; not used for status register
reads. Floated when the chip is de-selected or the outputs are disabled

.Q15/A -1 INPUT/OUTPUT Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB

ADDRESS(BYTE = LOW)

CE1/CE2 INPUT CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,

decoders and sense amplifiers. With either CE1 or CE2 high, the device is de­selected and power consumption reduces to Standby level upon completion of
any current program or erase operations. Both CE1,CE2 must be low to
select the device. CE2 is not provided in 44-pin SOP package.
All timing specifications are the same for both signals. Device selection occurs
with the latter falling edge of CE1 or CE2. The first rising edge of CE1 or CE2
disables the device.

PWD INPUT POWER-DOWN: Puts the device in deep power-down mode. PWD is active low;

PWD high gates normal operation. PWD also locks out erase or program
operation when active low providing data protection during power transitions.

OE INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during

a read cycle OE is active low.

WE INPUT WRITE ENABLE: Controls writes to the Command Interface Register(CIR).

WE is active low.

RY/BY OPEN DRAIN READY/BUSY: Indicates the status of the internal Write State Machine(WSM).

OUTPUT When low it indicates that the WSM is performing a erase or program operation.

RY/BY high indicate that the WSM is ready for new commands, sector erase is
suspended or the device is in deep power-down mode. RY/BY is always active
and does not float to tristate off when the chip is deselected or data output are
disabled.

WP INPUT WRITE PROTECT: All sectors can be protected by writing a non-volatile protect-

bit for each sector. When WP is low, all prottect-bits status can not be changed,
i.e., the user can not execute Sector Protection and Sector Unprotect. The WP
input buffer is disabled when PWD transitions low(deep power-down mode).

BYTE INPUT BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or

output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high
and low byte. BYTE high places the device in x16 mode, and turns off the Q15/

A-1 input buffer. Address A0, then becomes the lowest order address.
VCC DEVICE POWER SUPPLY(5V±10%)
GND GROUND

P/N: PM0506

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REV.1.7, JUN. 15, 2001

MX29F1610A

BUS OPERATION

Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.

Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)

Mode Notes PWD CE1 CE2 OE WE A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1 RY/BY

Read 1,2,7 VIH VIL VIL VIL VIH X X X DOUT DOUT DOUT X
Output Disable 1,6,7 VIH VIL VIL VIH VIH X X X High Z High Z HighZ X
Standby 1,6,7 VIH VIL VIH X X X X X High Z HIgh Z HighZ X

VIH VIL

VIH VIH

Deep Power-Down 1,3 VIL X X X X X X X High Z High Z HighZ VOH

Manufacturer ID 4,8 VIH VIL VIL VIL VIH VIL VIL VID C2H 00H 0B VOH
Device ID 4,8 VIH VIL VIL VIL VIH VIH VIL VID FAH/FBH 00H 0B VOH

MX29F1610A
Write 1,5,6 VIH VIL VIL VIH VIL X X X DIN DIN DIN X

Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)

Mode Notes PWD CE1 CE2 OE WE A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1 RY/BY

Read 1,2,7,9 VIH VIL VIL VIL VIH X X X DOUT HighZ VIL/VIH X
Output Disable 1,6,7 VIH VIL VIL VIH VIH X X X High Z HIghZ X X
Standby 1,6,7 VIH VIL VIH X X X X X High Z HighZ X X

VIH VIL

VIH VIH

Deep Power-Down 1,3 VIL X X X X X X X High Z HIghZ X VOH

Manufacturer ID 4,8 VIH VIL VIL VIL VIH VIL VIL VID C2H High Z VIL VOH
Device ID 4,8 VIH VIL VIL VIL VIH VIH VIL VID FAH/FBH High Z VIL VOH

MX29F1610A
Write 1,5,6 VIH VIL VIL VIH VIL X X X DIN HIghZ VIL/VIH X

NOTES :

1.X can be VIH or VIL for address or control pins except for RY/BY which is either VOL or VOH.

2.RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH
if it is tied to VCC through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress.

3.PWD at GND ± 0.2V ensures the lowest deep power-down current.

4. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate
sector addresses provide Sector Protect Code.(Refer to Table 4)

5. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through
proper command sequence.

6.While the WSM is running. RY/BY in Level-Mode stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not
busy or in erase suspend mode.

7. RY/BY may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation.

8. VID = 11.5V- 12.5V.

9. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.

P/N: PM0506

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REV.1.7, JUN. 15, 2001

MX29F1610A

WRITE OPERATIONS

Commands are written to the COMMAND INTERFACE
REGISTER (CIR) using standard microprocessor write
timings. The CIR serves as the interface between the
microprocessor and the internal chip operation. The CIR
can decipher Read Array, Read Silicon ID, Erase and
Program command. In the event of a read command, the
CIR simply points the read path at either the array or the
silicon ID, depending on the specific read command
given. For a program or erase cycle, the CIR informs the
write state machine that a program or erase has been
requested. During a program cycle, the write state
machine will control the program sequences and the CIR

TABLE 3. COMMAND DEFINITIONS

Command Read/ Silicon Page/Byte Chip Sector Erase Erase Read Clear
Sequence Reset ID Read Program Erase Erase Suspend Resume Status Reg. Status Reg.

Bus Write 4 4 4 6 6 1 1 4 3
Cycles Req'd

will only respond to status reads. During a sector/chip
erase cycle, the CIR will respond to status reads and
erase suspend. After the write state machine has
completed its task, it will allow the CIR to respond to its full
command set. The CIR stays at read status register
mode until the microprocessor issues another valid
command sequence.

Device operations are selected by writing commands into
the CIR. Table 3 below defines 16 Mbit flash family
command.

First Bus Addr 5555H 5555H 5555H 5555H 5555H XXXX XXXX 5555H 5555H
Write Cycle Data AAH AAH AAH AAH AAH B0H D0H AAH AAH

Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
Write Cycle Data 55H 55H 55H 55H 55H 55H 55H

Third Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H
Write Cycle Data F0H 90H A0H 80H 80H 70H 50H

Fourth Bus Addr RA 00H/01H PA 5555H 5555H X
Read/Write Cycle Data RD C2H/FAH PD AAH AAH SRD

(FBH)

Fifth Bus Addr 2AAAH 2AAAH
Write Cycle Data 55H 55H

Sixth Bus Addr 5555H SA
Write Cycle Data 10H 30H

P/N: PM0506

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REV.1.7, JUN. 15, 2001

COMMAND DEFINITIONS(continue Table 3.)

Command Sector Sector Verify Sector
Sequence Protection Unprotect Protect

.
Bus Write 6 6 4
Cycles Req'd

First Bus Addr 5555H 5555H 5555H
Write Cycle Data AAH AAH AAH

Second Bus Addr 2AAAH 2AAAH 2AAAH
Write Cycle Data 55H 55H 55H

Third Bus Addr 5555H 5555H 5555H
Write Cycle Data 60H 60H 90H

Fourth Bus Addr 5555H 5555H *
Read/Write Cycle Data AAH AAH C2H*

Fifth Bus Addr 2AAAH 2AAAH
Write Cycle Data 55H 55H

MX29F1610A

Sixth Bus Addr SA** SA**
Write Cycle Data 20H 40H

Notes:

1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector
Address(SA).
5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.

2. Bus operations are defined in Table 2.

3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A16 -- A19 will uniquely select any sector.

4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
SRD = Data read from status register.

5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.

* Refer to Table 4, Figure 12.

6. The details of sector protection/unprotect algorithm are shown in Fig.10 and Fig.11.

P/N: PM0506

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REV.1.7, JUN. 15, 2001

DEVICE OPERATION

SILICON ID READ

MX29F1610A

The Silicon ID Read mode allows the reading out of a binary
code from the device and will identify its manufacturer and
type. This mode is intended for use by programming
equipment for the purpose of automatically matching the
device to be programmed with its corresponding

The manufacturer and device codes may also be read via
the command register, for instances when the
MX29F1610A is erased or programmed in a system
without access to high voltage on the A9 pin. The

command sequence is illustrated in Table 3.
programming algorithm. This mode is functional over the
entire temperature range of the device.

Byte 0 (A0=VIL) represents the manfacturer's code

(MXIC=C2H) and byte 1 (A0=VIH) the device identifier
To activate this mode, the programming equipment must

code (MX29F1610A=FAH).
force VID (11.5V~12.5V) on address pin A9. Two
identifier bytes may then be sequenced from the device
outputs by toggling address A0 from VIL to VIH. All

The Silicon ID Read mode will be terminated after the

following write command cycle.
addresses are don't cares except A0 and A1.

Table 4. MX29F1610 Silion ID Codes and Verify Sector Protect Code

Type A19 A18 A17A16A1A0Code(HEX) DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

Manufacturer Code X X X X VIL VIL C2H* 1 1 0 0 0 0 1 0

0

MX29F1610A Device Code X X X X VIL VIH FAH 1 1 1 1 1 0 1 0/1
Verify Sector Protect Sector Address*** VIH VIL C2H** 1 1 0 0 0 0 1 0

* MX29F1610A Manufacturer Code = C2H, Device Code = FAH when BYTE = VIL
MX29F1610A Manufacturer Code = 00C2H, Device Code = 00FAH when BYTE = VIH
** Outputs C2H at protected sector address, 00H at unprotected scetor address.
***All sectors have protect-bit feature. Sector address = (A19, A18,A17,A16)

P/N: PM0506

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REV.1.7, JUN. 15, 2001

MX29F1610A

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the
memory. The device remains enabled for reads until the
CIR contents are altered by a valid command sequence.

The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during
the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing
parameters.

The MX29F1610A is accessed like an EPROM. When CE
and OE are low and WE is high the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual
line control gives designers flexibility in preventing bus
contention.

CE stands for the combination of CE1 and CE2 in
MX29F1610A 48-pin TSOP package. CE and stands for
CE in 44-pin SOP package.

Note that the read/reset command is not valid when
program or erase is in progress.

PAGE PROGRAM

To initiate Page program mode, a three-cycle command
sequence is required. There are two " unlock" write
cycles. These are followed by writing the page program
command-A0H.

Any attempt to write to the device without the three-cycle
command sequence will not start the internal Write State
Machine(WSM), no data will be written to the device.

After three-cycle command sequence is given, a
byte(word) load is performed by applying a low pulse on
the WE or CE input with CE or WE low (respectively) and
OE high. The address is latched on the falling edge of CE
or WE, whichever occurs last. The data is latched by the
first rising edge of CE or WE. Maximum of 128 bytes of
data may be loaded into each page by the same
procedure as outlined in the page program section below.

BYTE-WIDE LOAD/WORD-WIDE LOAD

Byte(word) loads are used to enter the 128 bytes(64

words) of a page to be programmed or the software codes

for data protection. A byte load(word load) is performed

by applying a low pulse on the WE or CE input with CE or

WE low (respectively) and OE high. The address is

latched on the falling edge of CE or WE, whichever occurs

last. The data is latched by the first rising edge of CE or

WE.

Either byte-wide load or word-wide load is

determined(Byte = VIL or VIH is latched) on the falling

edge of the WE(or CE) during the 3rd command write

cycle.

PROGRAM

Any page to be programmed should have the page in the
erased state first, i.e. performing sector erase is
suggested before page programming can be performed.

The device is programmed on a page basis. If a
byte(word) of data within a page is to be changed, data for
the entire page can be loaded into the device. Any
byte(word) that is not loaded during the programming of
its page will be still in the erased state (i.e. FFH). Once
the bytes of a page are loaded into the device, they are
simultaneously programmed during the internal
programming period. After the first data byte(word) has
been loaded into the device, successive bytes(words)
are entered in the same manner. The time between byte
(word) loads must be less than 30us otherwise the load
period could be teminated. A6 to A19 specify the page
address, i.e., the device is page-aligned on 128 bytes(64
words)boundary. The page address must be valid during
each high to low transition of WE or CE. A-1 to A5 specify
the byte address within the page, A0 to A5 specify the
word address withih the page. The byte(word) may be
loaded in any order; sequential loading is not required. If
a high to low transition of CE or WE is not detected whithin
100us of the last low to high transition, the load period will
end and the internal programming period will start. The
Auto page program terminates when status on DQ7 is '1'
at which time the device stays at read status register
mode until the CIR contents are altered by a valid
command sequence.(Refer to table 3,6 and Figure 1,7,8)

P/N: PM0506

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REV.1.7, JUN. 15, 2001

MX29F1610A

CHIP ERASE

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command-80H. Two more "unlock" write cycles
are then followed by the chip erase command-10H.

Chip erase does not require the user to program the
device prior to erase.

The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the status on DQ7 is "1" at which time the device
stays at read status register mode. The device remains
enabled for read status register mode until the CIR
contents are altered by a valid command
sequence.(Refer to table 3,6 and Figure 2,7,9)

Table 5. MX29F1610 Sector Address Table

(Byte-Wide Mode)

A19 A18 A17 A16 Address Range[A19, -1]

SA0 0 0 0 0 000000H--01FFFFH
SA1 0 0 0 1 020000H--03FFFFH
SA2 0 0 1 0 040000H--05FFFFH
SA3 0 0 1 1 060000H--07FFFFH
SA4 0 1 0 0 080000H--09FFFFH

Sector erase does not require the user to program the
device prior to erase. The system is not required to
provide any controls or timings during these operations.

The automatic sector erase begins on the rising edge of
the last WE pulse in the command sequence and
terminates when the status on DQ7 is "1" at which time
the device stays at read status register mode. The device
remains enabled for read status register mode until the
CIR contents are altered by a valid command
sequence.(Refer to table 3,6 and Figure 3,4,7,9))

ERASE SUSPEND

This command only has meaning while the the WSM is
executing SECTOR erase operation, and therefore will
only be responded to during SECTOR erase operation.
After this command has been executed, the CIR will
initiate the WSM to suspend erase operations, and then
return to Read Status Register mode. The WSM will set
the DQ6 bit to a "1". Once the WSM has reached the
Suspend state,the WSM will set the DQ7 bit to a "1", At
this time, WSM allows the CIR to respond to the Read
Array, Read Status Register and Erase Resume
commands only. In this mode, the CIR will not resopnd to
any other comands. The WSM will continue to run, idling
in the SUSPEND state, regardless of the state of all input
control pins, with the exclusion of PWD. PWD low will
immediately shut down the WSM and the remainder of the
chip.

... .... ... ... ................

SA15 1 1 1 1 1E0000H--1FFFFFH

SECTOR ERASE

Sector erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
set-up command-80H. Two more "unlock" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of WE,
while the command (data) is latched on the rising edge of
WE.

P/N: PM0506

ERASE RESUME

This command will cause the CIR to clear the suspend
state and set the DQ6 to a '0', but only if an Erase Suspend
command was previously issued. Erase Resume will not
have any effect in all other conditions.

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REV.1.7, JUN. 15, 2001

MX29F1610A

READ STATUS REGISTER

The MXIC's16 Mbit flash family contains a status register
which may be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The status register may be read
at any time by writing the Read Status command to the
CIR. After writing this command, all subsequent read
operations output data from the status register until
another valid command sequence is written to the CIR.
A Read Array command must be written to the CIR to
return to the Read Array mode.

The status register bits are output on DQ2 - DQ7(table 6)
whether the device is in the byte-wide (x8) or word-wide
(x16) mode for the MX29F1610A. In the word-wide mode
the upper byte, DQ(8:15) is set to 00H during a Read
Status command. In the byte-wide mode, DQ(8:14) are
tri-stated and DQ15/A-1 retains the low order address
function. DQ0-DQ1 is set to 0H in either x8 or x16 mode.

It should be noted that the contents of the status register
are latched on the falling edge of OE or CE whichever
occurs last in the read cycle. This prevents possible bus
errors which might occur if the contents of the status
register change while reading the status register. CE or
OE must be toggled with each subsequent status read, or
the completion of a program or erase operation will not be
evident.

CLEAR STATUS REGISTER

The Eraes fail status bit (DQ5) and Program fail status bit
(DQ4) are set by the write state machine, and can only be
reset by the system software. These bits can indicate
various failure conditions(see Table 6). By allowing the
system software to control the resetting of these bits,
several operations may be performed (such as
cumulatively programming several pages or erasing
multiple blocks in squence). The status register may then
be read to determine if an error occurred during that
programming or erasure series. This adds flexibility to the
way the device may be programmed or erased.
Additionally, once the program(erase) fail bit happens,
the program (erase) operation can not be performed
further. The program(erase) fail bit must be reset by
system software before further page program or sector
(chip) erase are attempted. To clear the status register,
the Clear Status Register command is written to the CIR.
Then, any other command may be issued to the CIR.
Note again that before a read cycle can be initiated, a
Read command must be written to the CIR to specify
whether the read data is to come from the Array, Status
Register or Silicon ID.

The Status Register is the interface between the
microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate the
status of the WSM, and will also hold the bits indicating
whether or not the WSM was successful in performing the
desired operation. The WSM sets status bits four through
seven and clears bits six and seven, but cannot clear
status bits four and five. If Erase fail or Program fail status
bit is detected, the Status Register is not cleared until the
Clear Status Register command is written. The
MX29F1610A automatically outputs Status Register data
when read after Chip Erase, Sector Erase, Page Program
or Read Status Command write cycle. The internal state
machine is set for reading array data upon device power­up, or after deep power-down mode.

P/N: PM0506

11

REV.1.7, JUN. 15, 2001

MX29F1610A

TABLE 6. MX29F1610 STATUS REGISTER

STATUS NOTES DQ7 DQ6 DQ5 DQ4 DQ3

IN PROGRESS PROGRAM 1,2 0 0 0 0 0

ERASE 1,3 0 0 0 0 0
SUSPEND (NOT COMPLETE) 1,4 0 0 0 0 0
(COMPLETE) 1 1 0 0 0

COMPLETE PROGRAM 1,2 1 0 0 0 0

ERASE 1,3 1 0 0 0 0

FAIL PROGRAM 1,5 1 0 0 1 0

ERASE 1,5 1 0 1 0 0

AFTER CLEARING STATUS REGISTER 1000 0

NOTES:

1. DQ7 : WRITE STATE MACHINE STATUS
1 = READY, 0 = BUSY
DQ6 : ERASE SUSPEND STATUS
1 = SUSPEND, 0 = NO SUSPEND
DQ5 : ERASE FAIL STATUS
1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE
DQ4 : PROGRAM FAIL STATUS
1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM
DQ3=0 = RESERVED FOR FUTURE ENHANCEMENTS.
These bits are reserved for future use ; mask them out when polling the Status Register.

2. PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode.

3. ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode.

4. SUSPEND STATUS is for Sector Erase mode .

5. FAIL STATUS bit(DQ4 or DQ5) is provided during Page Program or Sector/Chip Erase modes respectively.

6. DQ3 = 0 all the time.

P/N: PM0506

12

REV.1.7, JUN. 15, 2001