MXIC MX29F100TTC-55, MX29F100TTC-70, MX29F100TTC-90, MX29F100TMC-12, MX29F100TMC-55 Datasheet

FEATURES

MX29F100T/B

1M-BIT [128Kx8/64Kx16] CMOS FLASH MEMORY

•5V±10% for read, erase and write operation

• 131072x8/ 65536x16 switchable

• Fast access time:55/70/90/120ns

• Low power consumption

- 40mA maximum active current(5MHz)

- 1uA typical standby current

• Command register architecture

- Byte/ Word Programming (7us/ 12us typical)

- Erase (16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and
64K-Byte x1)

• Auto Erase (chip) and Auto Program

- Automatically erase any combination of sectors or
with Erase Suspend capability.

- Automatically program and verify data at specified
address

• Status Reply

- Data polling & Toggle bit for detection of program
and erase cycle completion.

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

- Superior inadvertent write protection

• Sector protection

- Hardware method to disable any combination of
sectors from program or erase operations

- Sector protect/unprotect for 5V only system or 5V/
12V system

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1 to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 44-pin SOP

- 48-pin TSOP

• Ready/Busy pin(RY/BY)

- Provides a hardware method or detecting program
or erase cycle completion

• Erase suspend/ Erase Resume

- Suspend an erase operation to read data from, or
program data to a sector that is not being erased,
then resume the erase operation.

• Hardware RESET pin

- Hardware method of resetting the device to reading
the device to reading array data.

• 20 years data retention

GENERAL DESCRIPTION

The MX29F100T/B is a 1-mega bit Flash memory
organized as 131,072 bytes or 65,536 words.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memory. The MX29F100T/B is packaged in 44-pin
SOP and 48-pin TSOP. It is designed to be repro­grammed and erased in-system or in-standard
EPROM programmers.

The standard MX29F100T/B offers access time as
fast as 55ns, allowing operation of high-speed micro­processors without wait states. To eliminate bus
contention, the MX29F100T/B has separate chip
enable (CE) and output enable (OE) controls.

MXIC's Flash memories augment EPROM function­ality with in-circuit electrical erasure and
programming. The MX29F100T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs and

P/N:PM0548 REV. 1.2, NOV. 12, 2001

fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.

MXIC Flash technology reliably stores memory con­tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi­nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The
MX29F100T/B uses a 5.0V±10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.

The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.

1

PIN CONFIGURATIONS

MX29F100T/B

44SOP(500mil)

NC

RY/BY

NC

A7
A6
A5
A4
A3
A2
A1
A0

CE

GND

OE
Q0
Q8
Q1
Q9
Q2

Q10

Q3

Q11

PIN DESCRIPTION:

SYMBOL PIN NAME

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

RESET

44

WE

43

A8

42

A9

41

A10

40

A11

39

A12

38

A13

37

A14

36

A15

35

NC

34

BYTE

33

GND

32

MX29F100T/B

Q15/A-1

31

Q7

30

Q14

29

Q6

28

Q13

27

Q5

26

Q12

25

Q4

24

VCC

23

48 TSOP(TYPE I) (12mm x 20mm)

1

A15

2

A14

3

A13

4

A12

5

A11

6

A10

7

A9

8

A8

9

NC

10

NC

11

WE

RESET

RY/BY

12
13

NC

14

NC

15
16

NC

17

NC

18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

MX29F100T/B

(NORMAL TYPE)

48

NC

47

BYTE

46

GND

45

Q15/A-1

44

Q7

43

Q14

42

Q6

41

Q13

40

Q5

39

Q12

38

Q4

37

VCC

36

Q11

35

Q3

34

Q10

33

Q2

32

Q9

31

Q1

30

Q8

29

Q0

28

OE

27

GND

26

CE

25

A0

A0-A15 Address Input
Q0-Q14 Data Input/Output
Q15/A-1 Q15(Word mode)/LSB addr.(Byte mode)
CE Chip Enable Input
OE Output Enable Input
RESET Hardware Reset Pin, Active low
WE Write Enable Input
RY/BY Ready/Busy Output
BYTE Word/Byte Selection Input
VCC Power Supply Pin (+5V)
GND Ground Pin
NC Pin Not Connected Internally

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MX29F100T/B

SECTOR STRUCTURE

MX29F100T Top Boot Sector Addresses Tables

A15 A14 A13 A12 (x8)Address Range (x16) Address Range

SA0 0 X X X 00000h-0FFFFh 64KB 00000h-07FFFh 32KW
SA1 1 0 X X 10000h-17FFFh 32KB 08000h-0BFFFh 16KW
SA2 1 1 0 0 18000h-19FFFh 8KB 0C000h-0CFFFh 4KW
SA3 1 1 0 1 1A000h-1BFFFh 8KB 0D000h-0DFFFh 4KW
SA4 1 1 1 X 1C000h-1FFFFh 16KB 0E000h-0FFFFh 8KW

MX29F100B Bottom Boot Sector Addresses Tables

A15 A14 A13 A12 (x8)Address Range (x16) Address Range

SA0 0 0 0 X 00000h-03FFFh 16KB 00000h-01FFFh 8KW
SA1 0 0 1 0 04000h-05FFFh 8KB 02000h-02FFFh 4KW
SA2 0 0 1 1 06000h-07FFFh 8KB 03000h-03FFFh 4KW
SA3 0 1 X X 08000h-0FFFFh 32KB 04000h-07FFFh 16KW
SA4 1 X X X 10000h-1FFFFh 64KB 08000h-0FFFFh 32KW

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3

SECTOR DIAGRAM

CE
OE

WE

CONTROL
INPUT

LOGIC

PROGRAM/ERASE

HIGH VOLTAGE

MX29F100T/B

WRITE

STATE

MACHINE

(WSM)

A0-A15

A-1/Q15

ADDRESS

LATCH

AND

BUFFER

X-DECODER

MX29F100T/B

FLASH
ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

STATE

REGISTER

ARRAY

SOURCE

HV

COMMAND

DATA
DECODER

PGM

DATA

HV

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

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Q0~Q14

I/O BUFFER

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4

MX29F100T/B

AUTOMATIC PROGRAMMING

The MX29F100T/B is byte/ word programmable using
the Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out sequence or verify the data programmed. The
typical chip programming time of the MX29F100T/B at
room temperature is less than 3.5 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase
pulses according to MXIC's Automatic Chip Erase
algorithm. Typical erasure at room temperature is
accomplished in less than 3 seconds. The Automatic
Erase algorithm automatically programs the entire
array prior to electrical erase. The timing and
verification of electrical erase are internally controlled
by the device.

AUTOMATIC SECTOR ERASE

The MX29F100T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro­grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter­nally controlled by the device.

AUTOMATIC PROGRAMMING ALGORITHM

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand­ard microprocessor write timings. The device will
automatically pre-program and verify the entire array.
Then the device automatically times the erase pulse
width, verifies the erase and counts the number of
sequences. A status bit toggling between consecutive
read cycles provides feedback to the user as to the
status of the programming operation.

Register contents serve as inputs to an internal state­machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches address and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE.

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia­bility, and cost effectiveness. The MX29F100T/B electri­cally erases all bits simultaneously using Fowler-Nord­heim tunneling. The bytes are programmed by using the
EPROM programming mechanism of hot electron
injection.

During a program cycle, the state-machine will control the
program sequences and command register will not re­spond to any command set. During a Sector Erase cycle,
the command register will only respond to Erase Sus­pend command. After Erase Suspend is complete, the
device stays in read mode. After the state machine has
completed its task, it will allow the command register to
respond to its full command set.

MXIC's Automatic Programming algorithm requires
the user to only write program set-up commands
(include 2 unlock write cycle and A0H) and a program
command (program data and address). The device
automatically times the programming pulse width,
verifies the program and counts the number of
sequences. A status bit similar to DATA polling and a
status bit toggling between consecutive read cycles,
provides feedback to the user as to the status of the
programming operation.

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MX29F100T/B

TABLE1. SOFTWARE COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI
Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA)
Verify x02H XX01H

Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H

Porgram Word 4 555H AAH 2AAH 55H 555H A0H PA PD

Byte 4 AAAH AAH 555H 55 H AAAH A 0H PA PD
Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H
Sector Erase Word 6 555H AAH 2AAH 55 H 555H 8 0H 555H AAH 2AAH 55H SA 30H

Byte 6 AAAH AAH 555H 55 H AAAH 80H AAAH AAH 555H 55H SA 30H
Sector Erase Suspend 1 XXXH B 0H
Sector Erase Resume 1 XXXH 30 H
Unlock for sector 6 555H AAH 2AAH 5 5H 555H 80H 555H AAH 2AAH 5 5H 555H 20H
protect/unprotect

XX00H

x04H 01H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code.
(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, D9H/DFH(x8) and 22D9H/22DFH(x16) for device
code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/
AAAH or 555H to Address A10~A-1 in byte mode.
Address bit A11~A15=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A15 in either state.

4. For Sector Protect Verify Operation : If read out data is 01H, it means the sector has been protected. If read out
data is 00H, it means the sector is still not being protected.

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6

COMMAND DEFINITIONS

Device operations are selected by writing specific ad­dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
the read mode. Table 1 defines the valid register com­mand sequences. Note that the Erase Suspend (B0H)
and Erase Resume (30H) commands are valid only
while the Sector Erase operation is in progress. Either
of the two reset command sequences will reset the
device(when applicable).

MX29F100T/B

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TABLE 2. MX29F100T/B BUS OPERATION

Pins CE OE WE A0 A1 A6 A9 D0 ~ Q15
Mode

MX29F100T/B

Read Silicon ID L L H L L X V

(2) C2H(Byte mode)

ID

Manfacturer Code(1) 00C2H(Word mode)
Read Silicon ID L L H H L X VID(2) D9H/DFH(Byte mode)
Device Code(1) 22D9H/22DFH

(Word mode)

Read L L H A0 A1 A6 A9 D

OUT

Standby H X X X X X X HIGH Z
Output Disable L H H X X X X HIGH Z
Write L H L A0 A1 A6 A9 DIN(3)
Sector Protect with 12V L VID(2) L X X L VID(2) X
system(6)
Chip Unprotect with 12V L VID(2) L X X H VID(2) X
system(6)
Verify Sector Protect L L H X H X VID(2) Code(5)
with 12V system
Sector Protect without 12V L H L X X L H X
system (6)
Chip Unprotect without 12V L H L X X H H X
system (6)
Verify Sector Protect/Unprotect L L H X H X H Code(5)
without 12V system (7)
Reset X X X X X X X HIGH Z

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/0000H means unprotected.

Code=01H/0001H means protected.
A15~A12=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.

Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V system"

command.

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MX29F100T/B

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array
data. The device remains enabled for reads until the
command register contents are altered.

If program-fail or erase-fail happen, the write of F0H
will reset the device to abort the operation. A valid
command must then be written to place the device in
the desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by rais­ing A9 to a high voltage. However, multiplexing high
voltage onto address lines is not generally desired
system design practice.

The MX29F100T/B contains a Silicon-ID-Read opera­tion to supplement traditional PROM programming
methodology. The operation is initiated by writing the
read silicon ID command sequence into the command
register. Following the command write, a read cycle
with A1=VIL, A0=VIL retrieves the manufacturer code
of C2H/00C2H. A read cycle with A1=VIL, A0=VIH
returns the device code of D9H/22D9H for
MX29F100T, DFH/22DFH for MX29F100B.

SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing
the "set-up" command 80H. Two more "unlock" write
cycles are then followed by the chip erase command
10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify
begin. The erase and verify operations are completed
when the data on Q7 is "1" at which time the device
returns to the Read mode. The system is not required
to provide any control or timing during these
operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when
adequate erase margin has been achieved for the
memory array(no erase verified command is required).

If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and
terminates when the data on Q7 is "1" and the data on
Q6 stops toggling for two consecutive read cycles, at
which time the device returns to the Read mode.

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MX29F100T/B

TABLE 3. EXPANDED SILICON ID CODE

Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code Word VIL VIL 00H 1 1 0 0 0 0 1 0 00C2H

Byte VIL VIL X 1 1 0 0 0 0 1 0 C2H
Device code Word VIH VIL 22H 1 1 0 1 1 0 0 1 22D9H
for MX29F100T Byte VIH VIL X 1 1 0 1 1 0 0 1 D 9H
Device code Word VIH VIL 22H 1 1 0 1 1 1 1 1 22DFH
for MX29F100B Byte VIH VIL X 1 1 0 1 1 1 1 1 DFH

Sector Protection X VIH X 0 0 0 0 0 0 0 1 01H(Protected)
Verification X VIH X 0 0 0 0 0 0 0 0 00H(Unprotected)

ERASE COMMANDS

The Automatic Sector Erase does not require the
device to be entirely pre-programmed prior to executing
the Automatic Set-up Sector Erase command and
Automatic Sector Erase command. Upon executing the
Automatic Sector Erase command, the device will
automatically program and verify the sector(s) memory
for an all-zero data pattern. The system does not
require to provide any control or timing during these
operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and
verification begin. The erase and verification
operations are complete when the data on Q7 is "1"
and the data on Q6 stops toggling for two consecutive
read cycles, at which time the device returns to the
Read mode. The system does not require to provide
any control or timing during these operations.

When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when
adequate erase margin has been achieved for the
memory array (no erase verified command is
required). Sector erase is a six-bus cycle operation.
There are two "unlock" write cycles. These are
followed by writing the set-up command 80H. Two
more "unlock" write cycles are then followed by the
sector erase command 30H. The sector address is
latched on the falling edge of WE, while the
command(data) is latched on the rising edge of WE.
Sector addresses selected are loaded into internal

register on the sixth falling edge of WE. Each succes­sive sector load cycle started by the falling edge of WE
must begin within 30us from the rising edge of the
preceding WE. Otherwise, the loading period ends and
internal auto sector erase cycle starts. (Monitor Q3 to
determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command
other than Sector Erase (30H) or Erase Suspend (B0H)
during the time-out period resets the derice to read
mode.

ERASE SUSPEND

This command is only valid while the state machine is
executing Automatic Sector Erase operation, and there­fore will only be responded to period during Automatic
Sector Erase operation. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out immediately terminates the
time-out period and suspends the erase operation.
After this command has been executed, the command
register will initiate erase suspend mode. The state
machine will return to read mode automatically after
suspend is ready. At this time, state machine only
allows the command register to respond to the Read
Memory Array, Erase Resume and Program com­mands.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend
program operation is complete, the system can once
again read array data within non-suspended sectors.

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Table 4. Write Operation Status

Status Q7 Q6 Q5 Q3 Q2 RY/BY

MX29F100T/B

Note1 Note2

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No 0

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 No 0 N/A Toggle 1
(Erase Suspended Sector) Toggle

In Progress

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector)
Erase Suspend Program Q7 Toggle 0 N/A N/A 0

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No 0

Exceeded
Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

Erase Suspend Program Q7 Toggle 1 N/A N/A 0

Toggle

Toggle

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.

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MX29F100T/B

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all other
conditions.Another Erase Suspend command can be
written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, a three-cycle
command sequence is required. There are two "un­lock" write cycles. These are followed by writing the
Automatic Program command A0H.

Once the Automatic Program command is initiated,
the next WE pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the
rising edge of the WE pulse. The rising edge of WE
also begins the programming operation. The system
is not required to provide further controls or timings.
The device will automatically provide an adequate
internally generated program pulse and verify margin.

If the program opetation was unsuccessful, the data
on Q5 is "1"(see Table 4), indicating the program
operation exceed internal timing limit. The automatic
programming operation is completed when the data
read on Q6 stops toggling for two consecutive read
cycles and the data on Q7 and Q6 are equivalent to
data written to these two bits, at which time the device
returns to the Read mode(no program verify command
is required).

WRITE OPERATION STATUS

DATA POLLING-Q7

The MX29F100T/B also features Data Polling as a method
to indicate to the host system that the Automatic Program
or Erase algorithms are either in progress or completed.

While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an attempt
to read the device will produce the true data last written

to Q7. The Data Polling feature is valid after the rising edge
of the fourth WE pulse of the four write pulse sequences
for automatic program.

While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will read
"1". The Data Polling feature is valid after the rising edge
of the sixth WE pulse of six write pulse sequences for
automatic chip/sector erase.

The Data Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)

RY/BY:Ready/Busy

The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid after
the rising edge of the final WE pulse in the command
sequence. Since RY/BY is an open-drain output, several
RY/BY pins can be tied together in parallel with a pull-up
resistor to Vcc.

If the outputs is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the
device is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.

TOGGLE BIT-Q6

The MX29F100T/B features a "Toggle Bit" as a method to
indicate to the host system that the Auto Program/Erase
algorithms are either in progress or completed.

While the Automatic Program or Erase algorithm is in
progress, successive attempts to read data from the
device will result in Q6 toggling between one and zero.
Once the Automatic Program or Erase algorithm is
completed, Q6 will stop toggling and valid data will be
read. The toggle bit is valid after the rising edge of the
sixth WE pulse of the six write pulse sequences for chip/
sector erase.

The Toggle Bit feature is active during Automatic Program/
Erase algorithms or sector erase time-out.(see section
Q3 Sector Erase Timer)

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MX29F100T/B

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
condition.

If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence.
This allows the system to continue to use the other active
sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.

If this time-out condition occurs during the byte
programming operation, it specifies that the entire sector
containing that byte is bad and this sector maynot be
reused, (other sectors are still functional and can be
reused).

The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this case
the device locks out and never completes the Automatic
Algorithm operation. Hence, the system never reads a
valid data on Q7 bit and Q6 never stops toggling. Once
the Device has exceeded timing limits, the Q5 bit will
indicate a "1". Please note that this is not a device failure
condition since the device was incorrectly used.

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequenc the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.

used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent commands
to the device will be ignored until the erase operation is
completed as indicated by Data Polling or Toggle Bit. If
Q3 is low ("0"), the device will accept additional sector
erase commands. To insure the command has been
accepted, the system software should check the status of
Q3 prior to and following each subsequent sector erase
command. If Q3 were high on the second status check,
the command may not have been accepted.

Reading Toggle Bits Q6

Whenever the system initally begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of Q5 is high (see the
section on Q5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as Q5 went high. If the
toggle bit is no longer toggling, the device has successfully
completed the program ot erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset command
to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and Q5
through successive read cycles, determining the status
as described in the previous paragraph. Alternatively, it
may choose to perform other system tasks. In this case,
the system must start at the beginning of the algorithm
when it returns to determine the status of the operation.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be

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13

MX29F100T/B

DATA PROTECTION

The MX29F100T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transition.
During power up the device automatically resets the state
machine in the Read mode. In addition, with its control
register architecture, alteration of the memory contents
only occurs after successful completion of specific
command sequences. The device also incorporates
several features to prevent inadvertent write cycles
resulting from VCC power-up and power-down transition
or system noise.

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously
protected sector to change data in-system. The Temporary
Sector Unprotect mode is activated by setting the RESET
pin to VID(11.5V-12.5V). During this mode, formerly
protected sectors can be programmed or erased as un­protected sector. Once VID is remove from the RESET
pin, all the previously protected sectors are protected
again.

WRITE PULSE "GLITCH" PROTECTION

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F100T/B features hardware sector protection.
This feature will disable both program and erase operations
for these sectors protected. To activate this mode, the
programming equipment must force VID on address pin
A9 and control pin OE, (suggest VID = 12V) A6 = VIL and
CE = VIL.(see Table 2) Programming of the protection
circuitry begins on the falling edge of the WE pulse and is
terminated on the rising edge. Please refer to sector
protect algorithm and waveform.

To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for a
protected sector. Otherwise the device will produce 00H
for the unprotected sector. In this mode, the
address,except for A1, are in "don't care" state. Address
locations with A1 = VIL are reserved to read manufacturer
and device codes.(Read Silicon ID)

It is also possible to determine if the sector is protected in
the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.

Noise pulses of less than 5ns(typical) on CE or WE will not
initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibite by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE must
be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduced power switching effect, each device
should have a 0.1uF ceramic capacitor connected between
its VCC and GND.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F100T/B also features the chip unprotect mode,
so that all sectors are unprotected after chip unprotect is
completed to incorporate any changes in the code. It is
recommended to protect all sectors before activating chip
unprotect mode.

To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and waveform
for the chip unprotect algorithm. The unprotection
mechanism begins on the falling edge of the WE pulse
and is terminated on the rising.

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.

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14

MX29F100T/B

SECTOR PROTECTION WITHOUT 12V SYSTEM

The MX29F100T/B also feature a hardware sector
protection method in a system without 12V power suppply.
The programming equipment do not need to supply 12
volts to protect sectors. The details are shown in sector
protect algorithm and waveform.

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature -40oC to 125oC
Ambient Temperature with Power -55oC to 125oC
Applied
Storage Temperature -65oC to 125oC
Applied Input Voltage -0.5V to 7.0V
Applied Output Voltage -0.5V to 7.0V
VCC to Ground Potential -0.5V to 7.0V
A9 & OE & RESET -0.5V to 13.5V

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F100T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and waveform.

POWER-UP SEQUENCE

The MX29F100T/B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command
sequences.

NOTICE:

Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended period may affect reliability.

NOTICE:

Specifications contained within the following tables are
subject to change.

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V
CIN2 Control Pin Capacitance 1 2 pF VIN = 0V
COUT Output Capacitance 12 pF VOUT = 0V

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REV. 1.2, NOV. 12, 2001