MXIC MX29F080TC-12, MX29F080TC-70, MX29F080TC-90, MX29F080MC-12, MX29F080MC-70 Datasheet

FEA TURES

PRELIMINARY

MX29F080

8M-BIT [1024K x 8] CMOS EQUAL SECTOR FLASH MEMORY

• 1,048,576 x 8 byte mode only stuction

• Single power supply operation

- 5.0V only operation for read, erase and program
operation

• Fast access time: 70/90/120ns

• Low power consumption

- 30mA maximum active current

- 0.2uA typical standby current

• Command register architecture

- Byte Programming (7us typical)

- Sector Erase of 16 equal sector with 64K-Byte each

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with
Erase Suspend capability .

- Automatically program and verify data at specified
address

• Erase suspend/Erase Resume

- Suspends sector erase operation to read data from,
or program data to, another sector that is not being
erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program

and erase operation completion.

• Ready/Busy (RY/BY)

- Provides a hardware methed of detecting program
and erase operation complation.

• Sector Group protect/chip unprotect for 5V/12V sys­tem.

• Sector Group protection

- Hardware protect method for each group which con­sists of two adjacent sectors

- Temporary sector group unprotect allows code
changes in previously locked sectors

• 10,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 40-pin TSOP or 44-pin SOP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

GENERAL DESCRIPTION

The MX29F080 is a 8-mega bit Flash memory organized
as 1024K bytes of 8 bits. MXIC's Flash memories offer
the most cost-effective and reliable read/write non-vola­tile random access memory. The MX29F080 is pack­aged in 40-pin TSOP or 44-pin SOP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.

The standard MX29F080 offers access time as fast as
70ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F080 has separate chip enable (CE) and output
enable (OE ) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F080 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels

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during erase and programming, while maintaining maxi­mum EPROM compatibility.

MXIC Flash technology reliably stores memory
contents even after 10,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29F080 uses a 5.0V±10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.

The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.

1

PIN CONFIGURATIONS

MX29F080

40 TSOP (Standard Type) (10mm x 20mm)

1

A19

2

A18

3

A17

4

A16

5

A15

6

A14

7

A13

8

A12

9

CE

10

VCC

RESET

A11
A10

11

NC

12
13
14
15

A9

16

A8

17

A7

18

A6

19

A5

20

A4

MX29F080

44 SOP

VCC

NC

RESET

A11
A10

NC
NC

Q0
Q1
Q2

Q3
VSS
VSS

2
3
4
5

A9

6

A8

7

A7

8

A6

9

A5

10

A4

11
12
13

A3

14

A2

15

A1

16

A0

17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32

MX29F080

31
30
29
28
27
26
25
24
23

CE
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE
OE
RY/BY
Q7
Q6
Q5
Q4
VCC

LOGIC SYMBOL

NC

40

NC

39

WE

38

OE

37

RY/BY

36

Q7

35

Q6

34

Q5

33

Q4

32

VCC

31

VSS

30

VSS

29

Q3

28

Q2

27

Q1

26

Q0

25

A0

24

A1

23

A2

22

A3

21

20

A0-A19

CE
OE
WE
RESET

8

Q0-Q7

RY/BY

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A19 Address Input
Q0~Q7 8 Data Inputs/Outputs
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
RESET Hardware Reset Pin, Active Low
RY/BY Read/Busy Output
VC C +5.0V single power supply
VSS Device Ground
N C Pin Not Connected Internally

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MX29F080

SECTOR STRUCTURE

MX29F080 SECTOR ADDRESS T ABLE

Sector Group Sector A1 9 A1 8 A17 A16 Address Range

SGA0 SA0 0000 000000h-00FFFFh
SGA0 SA1 0001 010000h-01FFFFh
SGA1 SA2 0010 020000h-02FFFFh
SGA1 SA3 0011 030000h-03FFFFh
SGA2 SA4 0100 040000h-04FFFFh
SGA2 SA5 0101 050000h-05FFFFh
SGA3 SA6 0110 060000h-06FFFFh
SGA3 SA7 0111 070000h-07FFFFh
SGA4 SA8 1000 080000h-08FFFFh
SGA4 SA9 1001 090000h-09FFFFh
SGA5 SA10 1010 0A0000h-0AFFFFh
SGA5 SA11 1011 0B0000h-0BFFFFh
SGA6 SA12 1100 0C0000h-0CFFFFh
SGA6 SA13 1101 0D0000h-0DFFFFh
SGA7 SA14 1110 0E0000h-0EFFFFh
SGA7 SA15 1111 0F0000h-0FFFFFh

Legend:SA=Sector Address ; SGA=Sector Group Addres
Note:All sectors are 64 Kbytes in size.

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3

BLOCK DIAGRAM

CE
OE
WE

CONTROL
INPUT

LOGIC

PROGRAM/ERASE

HIGH VOLT A GE

MX29F080

WRITE

STATE

MACHINE

(WSM)

A0-A19

ADDRESS

LA TCH

AND

BUFFER

X-DECODER

MX29F080

FLASH
ARRA Y

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

STATE

REGISTER

ARRAY

SOURCE

HV

COMMAND

DATA
DECODER

PGM

DATA

HV

COMMAND
DATA LATCH

PROGRAM

DATA LATCH

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Q0-Q7

I/O BUFFER

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4

MX29F080

AUTOMATIC PROGRAMMING

The MX29F080 is byte programmable using the Auto­matic Programming algorithm. The Automatic Progr am­ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro­grammed. The typical chip programming time at room
temperature of the MX29F080 is less than 8 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
T ypical erasure at room temper ature is accomplished in
less than 8 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electri­cal erase. The timing and v erification of electrical erase
are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F080 is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes
allow sectors of the array to be erased in one erase
cycle. The Automatic Sector Erase algorithm
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The de vice automatically
times the programming pulse width, provides the pro­gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog­gling between consecutive read cycles, provide feed­back to the user as to the status of the programming
operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand­ard microprocessor write timings. The de vice will auto­matically pre-program and verify the entire arra y. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu­tive read cycles provides feedback to the user as to the
status of the programming operation.

Register contents serve as inputs to an internal state­machine which controls the erase and programming cir­cuitry . During write cycles, the command register inter­nally latches address and data needed for the program­ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichev er hap­pens first .

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, re­liability, and cost effectiveness. The MX29F080 electri­cally erases all bits simultaneously using Fowler-Nord­heim tunneling. The bytes are programmed by using
the EPROM programming mechanism of hot electron
injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis­ter to respond to its full command set.

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MX29F080

T ABLE1. SOFTW ARE COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Silicon ID 4 555H AAH 2AAH 55H 555H 90H ADI DDI
Sector Group 4 555H AAH 2AAH 55H 555H 90H SGAx02 0 0 H
Protect Verify 01H
Porgram 4 555H AAH 2AAH 55H 555H A0H PA PD
Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Sector Erase Suspend 1 XXXH B 0H
Sector Erase Resume 1 XXXH 30 H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code. A2-A19=do
not care. (Refer to Table 3)

DDI = Data of Device identifier : C2H for manufacture code, D5H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.
SA = Address of the sector to be erased. Address A16-A19 select a unigue sector.

SGA=Address of the sector group. Address A17~A19 select a unigue sector group.

3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .
Address bit A11~A19=X=Don't care for all address commands except f or Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A19 in either state .

4.For Sector Group Protect V erify Operation : If read out data is 01H, it means the sector has been protected.If read
out data is 00H,it means the sector is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read mode.
Table 1 defines the valid register command sequences.
Note that the Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Sector Erase
operation is in progress. Either of the two reset command
sequences will reset the device(when applicable).

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MX29F080

T ABLE 2. MX29F080 BUS OPERATION

Pins
Mode CE OE WE A0 A1 A6 A9 Q0 ~ Q 7
Read Silicon ID L L H L L X VID(2) C2H
Manfacturer Code(1)
Read Silicon ID L L H H L X VID(2) D5H
Device Code(1)
Read L L H A0 A1 A6 A9 D
Standby H X X X X X X HIGH Z
Output Disable L H H X X X X HIGH Z
Write L H L A0 A1 A 6 A9 DIN(3)
Sector Group Protect (6) L VID(2) L X X L VID(2) X
Chip Unprotect(6) L VID(2) L X X H VID(2) X
Verify Sector Protect L L H X H X VID(2) Code(5)
Reset X X X X X X X HIGH Z

OUT

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 13V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

6. A19~A17=Sector group address for sector group protect.

Refer to sector group protect/chip unprotect algorithm and waveform.

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MX29F080

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg­ister. Microprocessor read cycles retr ieve array data.
The device remains enabled for reads until the command
register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com­mand must then be written to place the device in the
desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu­facturer and device codes must be accessible while the
device resides in the target system. PROM program­mers typically access signature codes by raising A9 to
a high voltage. Howe ver , multiplexing high voltage onto
address lines is not generally desired system design
practice.

The MX29F080 contains a Silicon-ID-Read operation to
supplement traditional PROM programming methodol­ogy . The operation is initiated b y writing the read silicon
ID command sequence into the command register. Fol­lowing the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of D5H for MX29F080.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are f ollowed b y writing the
"set-up" command 80H. Two more "unlock" write cy­cles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au­tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide an y
control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).

If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.

T ABLE 3. EXPANDED SILICON ID CODE

Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code VIL VIL 11000010C2H
Device code for MX29F080 VIH VIL 11010101D5H

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SECTOR ERASE COMMANDS

MX29F080

The Automatic Sector Erase does not require the
device to be entirely pre-programmed prior to
executing the Automatic Set-up Sector Erase
command and Automatic Sector Erase command.
Upon executing the Automatic Sector Erase
command, the device will automatically program and
verify the sector(s) memory for an all-zero data
pattern. The system is not required to provide any
control or timing during these operations.

When the sector(s) is automatically verified to
contain an all-zero pattern, a self-timed sector erase
and verify begin. The erase and verify operations
are complete when the data on Q7 is "1" and the data
on Q6 stops toggling for two consecutive read
cycles, at which time the device returns to the Read
mode. The system is not required to provide any
control or timing during these operations.

When using the Automatic Sector Erase algorithm,
note that the erase automatically terminates when
adequate erase margin has been achieved for the

memory array (no erase verification command is
required). Sector erase is a six-bus cycle operation.
There are two "unlock" write cycles. These are
followed by writing the set-up command 80H. Two
more "unlock" write cycles are then followed by the
sector erase command 30H. The sector address is
latched on the falling edge of WE or CE, whichever
happens later , while the command(data) is latched on
the rising edge of WE o r CE, whichever happens first.
Sector addresses selected are loaded into internal
register on the sixth falling edge of WE or CE,
whichever happens later. Each successive sector
load cycle started by the falling edge of WE or CE,
whichever happens later must begin within 80us from
the rising edge of the preceding WE or CE, whichever
happens first. Otherwise, the loading period ends and
internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still
open, see section Q3, Sector Erase Timer.) Any
command other than Sector Erase(30H) or Erase
Suspend(B0H) during the time-out period resets the
device to read mode.

T able 4. Write Operation Status

Status Q7 Q6 Q5 Q3 Q2

Byte Program in Auto Program Algorithm Q7 Toggle 0 0 1
Auto Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspend Read 1 1 0 0 Toggle

In Progress (Erase Suspended Sector) (Note1)

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data

(Non-Erase Suspended Sector)
Erase Suspend Program Q7 Toggle 0 0 1
(Non-Erase Suspended Sector) (Note2) (Note3)

Byte Program in Auto Program Algorithm Q7 Toggle 1 0 1
Exceeded Program/Erase in Auto Erase Algorithm 0 Toggle 1 1 N/A
Time Limits Erase Suspended Mode Erase Suspend Program Q7 Toggle 1 0 N/A

(Non-Erase Suspended Sector)

Notes:

1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.

2.Performing successive read operations from any address will cause Q6 to toggle.

3.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.

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MX29F080

ERASE SUSPEND

This command only has meaning while the state ma­chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend com­mand is written during a sector erase operation, the de­vice requires a maximum of 100us to suspend the erase
operations. However , When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex­ecuted, the command register will initiate erase suspend
mode. The state machine will return to read mode auto­matically after suspend is ready . At this time, state ma­chine only allows the command register to respond to
the Read Memory Array, Erase Resume and program
commands.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro­gram operation is complete, the system can once again
read array data within non-suspended sector .

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM

COMMANDS

required to provide further controls or timings. The de­vice will automatically provide an adequate internally gen­erated program pulse and verify margin.

If the program opetation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data
on Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read mode(no
program verify command is required).

DATA POLLING-Q7

The MX29F080 also features Data P olling as a method
to indicate to the host system that the Automatic Pro­gram or Erase algorithms are either in progress or com­pleted.

While the Automatic Programming algorithm is in opera­tion, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an at­tempt to read the device will produce the true data last
written to Q7. The Data P olling f eature is valid after the
rising edge of the fourth WE or CE, whichever happens
first, of the four write pulse sequences for automatic
program.

While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data P olling feature is valid after the rising
edge of the sixth WE or CE, whiche ver happens first, of
six write pulse sequences for automatic chip/sector
erase.

T o initiate Automatic Progr am mode, A three-cycle com­mand sequence is required. There are two "unlock" write
cycles. These are follow ed by writing the Automatic Pro­gram command A0H.

Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active program­ming operation. Addresses are latched on the falling
edge, and data are internally latched on the rising edge
of the WE or CE, whichever happens first pulse. The
rising edge of WE or CE, whichever happens first also
begins the programming operation. The system is not

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The Data Polling feature is activ e during Automatic Pro­gram/Erase algorithm or sector erase time-out.(see sec­tion Q3 Sector Erase Timer)

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10

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro­gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE or CE, whichever
happens first pulse in the command sequence(prior to
the program or erase operation), and during the sector
time-out.

During an Automatic Program or Erase algorithm opera­tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to con­trol the read cycles. When the operation is complete, Q6
stops toggling.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

MX29F080

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com­parison, indicates whether the device is actively eras­ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 4 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. T ypically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus­pended. When the de vice is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus­pended. Alternatively, the system can use Q7.

If a program address falls within a protected sector , Q6
toggles for approximately 2us after the program com­mand sequence is written, then returns to reading array
data.

Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo­rithm is complete.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. T oggle Bit I is v alid af­ter the rising edge of the final WE or CE, whichev er hap­pens first pulse in the command sequence.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys­tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfuly completed the program or erase opera­tion. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta­tus as described in the previous paragraph. Alternatively ,
it may choose to perform other system tasks. In this
case, the system must start at the beginning of the al­gorithm when it returns to determine the status of the
operation.

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MX29F080

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not suc­cessfully completed. Data P olling and T oggle Bit are the
only operating functions of the device under this condi­tion.

If this time-out condition occurs during sector erase op­eration, it specifies that a particular sector is bad and it
may not be reused. Howe ver , other sectors are still func­tional and may be used for the program or erase opera­tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute prog ram or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com­bination of sectors are bad.

If this time-out condition occurs during the byte program­ming operation, it specifies that the entire sector con­taining that byte is bad and this sector maynot be re­used, (other sectors are still functional and can be re­used).

The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Au­tomatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops toggling.
Once the Device has exceeded timing limits, the Q5 bit
will indicate a "1". Please note that this is not a device
failure condition since the device was incorrectly used.

TEMPORARY SECT OR GROUP UNPRO TECT

This feature allows temporary unprotection of previously
protected sector group to change data in-system. The
T emporary Sector group Unprotect mode is activated b y
setting the RESET pin to VID(11.5V -12.5V). During this
mode, formerly protected sectors can be programmed or
erased as un-protected sector . Once VID is remove from
the RESET pin,all the previously protected sector groups
are protected again.

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase com­mand sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
T oggle Bit. If Q3 is low ("0"), the de vice will accept addi­tional sector erase commands. To insure the command
has been accepted, the system software should check
the status of Q3 prior to and following each subsequent
sector erase command. If Q3 were high on the second
status check, the command may not have been accepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.

DATA PROTECTION

The MX29F080 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi­tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory
contents only occurs after successful completion of spe­cific command sequences. The de vice also incorporates
several features to prevent inadvertent write cycles re­sulting from VCC pow er-up and power-down transition or
system noise.

P/N:PM0579

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a wr ite cycle CE and WE
must be a logical zero while OE is a logical one.

REV. 1.4, JAN. 16, 2002

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