MXIC MX29F040 Technical data

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FEATURES

MX29F040

4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY

• 524,288 x 8 only

• Single power supply operation

- 5.0V only operation for read, erase and program op­eration

• Fast access time: 55/70/90/120ns

• Low power consumption

- 30mA maximum active current(5MHz)

- 1uA typical standby current

• Command register architecture

- Byte Programming (7us typical)

- Sector Erase
8 equal sectors of 64K-Byte each

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with
Erase Suspend capability .

- Automatically program and verify data at specified
address

• Erase suspend/Erase Resume

- Suspends an erase operation to read data from, or

program data to, another sector that is not being
erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program
and erase cycle completion.

• Sector protect/unprotect for 5V only system or 5V/
12V system.

• Sector protection

- Hardware method to disable any combination of
sectors from program or erase operations

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA fro m -1V to VCC+1V

• Low VCC write inhibit is equal to o r less than 3.2V

• Package type:

- 32-pin PLCC, TSOP o r PDIP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

• 20 years data retention

GENERAL DESCRIPTION

The MX29F040 is a 4-mega bit Flash memory organized
as 512K bytes of 8 bits. MXIC's Flash memories offer
the most cost-effective and reliable read/write non-vola­tile random access memory. The MX29F040 is pack­aged in 32-pin PLCC, TSOP, PDIP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.

The standard MX29F040 offers access time as fast as
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F040 has separate chip enable (CE) and output
enable (OE) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and progr amming. The
MX29F040 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels

P/N:PM0538 REV. 2.3, DEC. 10, 2004

during erase and programming, while maintaining maxi­mum EPROM compatibility.

MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29F040 uses a 5.0V±10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.

The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.

1

PIN CONFIGURATIONS

MX29F040

32 PDIP

A18
A16
A15
A12

GND

A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

MX29F040

VCC

32

WE

31

A17

30

A14

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23

CE

22

Q7

21

Q6

20

Q5

19

Q4

18

Q3

17

32 TSOP (Standard T ype) (8mm x 20mm)

1

A11

2

A9

3

A8

4

A13

5

A14

6

A17

7

WE

A18
A16
A15
A12

8
9
10
11
12
13

A7

14

A6

15

A5

16

A4

MX29F040

VCC

32 PLCC

A12

A15

A16

A18

VCCWEA17

4

5

A7
A6
A5
A4

9

A3
A2
A1
A0

13

Q0

14 17 20

Q1

32

OE

31

A10

30

CE

29

Q7

28

Q6

27

Q5

26

Q4

25

Q3

24

GND

23

Q2

22

Q1

21

Q0

20

A0

19

A1

18

A2

17

A3

1

MX29F040

Q2

Q3Q4Q5

GND

32

30

29

A14
A13
A8
A9

25

A11
OE
A10
CE

21

Q7

Q6

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A18 Address Input
Q0~Q7 Data Input/Output
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
GN D Ground Pin
VC C +5.0V single power supply

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SECTOR STRUCTURE

MX29F040 SECTOR ADDRESS TABLE

Sector A18 A17 A16 Address Range

SA0 0 0 0 00000h-0FFFFh
SA1 0 0 1 10000h-1FFFFh
SA2 0 1 0 20000h-2FFFFh
SA3 0 1 1 30000h-3FFFFh
SA4 1 0 0 40000h-4FFFFh
SA5 1 0 1 50000h-5FFFFh
SA6 1 1 0 60000h-6FFFFh
SA7 1 1 1 70000h-7FFFFh

Note: All sectors are 64 Kbytes in size.

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2

BLOCK DIAGRAM

CE

OE

WE

CONTROL
INPUT

LOGIC

PROGRAM/ERASE

HIGH VOLT A GE

MX29F040

WRITE

STATE

MACHINE

(WSM)

A0-A18

ADDRESS

LATCH

AND

BUFFER

X-DECODER

MX29F040

FLASH
ARRAY

Y-DECODER

Y-PASS GATE

SENSE

AMPLIFIER

DATA LATCH

STATE

REGISTER

ARRAY

SOURCE

HV

COMMAND

DATA
DECODER

PGM

DATA

HV

COMMAND

DATA LATCH

PROGRAM

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Q0-Q7

I/O BUFFER

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3

MX29F040

AUTOMATIC PROGRAMMING

The MX29F040 is byte programmable using the Auto­matic Programming algo rithm. The Auto matic Pro gram­ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro­grammed. The typical chip programming time at room
temperature of the MX29F040 is less than 4 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
T ypical er asure at room temperature is accomplished in
less than 4 second. The A uto matic Erase algorithm au­tomatically programs the entire array prior to electrical
erase. The timing and v erification o f electrical erase are
controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F040 is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes
allow sectors of the array to be erased in one erase
cycle. The Automatic Sector Erase algorithm
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un­lock write cycle and A0H) and a program command (pro­gram data and address). The de vice automatically times
the programming pulse width, provides the program veri­fication, and counts the number of sequences. A status
bit similar to DATA polling and a status bit toggling be­tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand­ard microprocessor write timings. The device will auto­matically pre-progr am and v erify the entire arra y. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu­tive read cycles provides feedback to the user as to the
status of the programming operation.

Register contents serve as inputs to an internal state­machine which controls the erase and programming cir­cuitry . During write cycles, the co mmand register inter­nally latches address and data needed for the program­ming and erase operations. During a system write cycle,
addresses are latched on the f alling edge o f WE o r CE,
whichever happens later, and data are latched on the
rising edge of WE or CE, whichever happens first.

MXIC's Flash technology combines years of EPROM
experience to pro duce the highest levels o f quality, relia­bility , and co st effectiveness. The MX29F040 electrically
erases all bits simultaneously using Fowler-Nordheim
tunneling. The bytes are programmed by using the
EPROM programming mechanism of hot electron injec­tion.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis­ter to respond to its full command set.

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MX29F040

TABLE 1. SOFTWARE COMMAND DEFINITIONS

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Silicon ID 4 555H AAH 2AAH 55H 555H 90H ADI DDI
Sector Protect Verify 4 555H AAH 2AAH 55H 555H 90H (SA)X 00H

02 01H
Program 4 555H AAH 2AAH 55H 555H A0H PA PD
Chip Erase 6 555H AAH 2AAH 55H 555H 8 0H 555H AAH 2AAH 55H 555H 10H
Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30 H
Sector Erase Suspend 1 XXXH B0H
Sector Erase Resume 1 XXXH 30H
Unlock for sector 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H
protect/unprotect

Note:
1 . ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code A2-A18=Do

not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, A4H for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be progr ammed at location PA.

SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .

Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence ma y be initiated with A11~A18 in either state.

4. For Sector Protect Verify Operation : If read out data is 01H, it means the sector has been protected. If read ou t

data is 00H, it means the sector is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad­dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mod e. Table 1 defines the valid register co mmand
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Either of the two
reset command sequences will reset the device (when
applicable).

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MX29F040

TABLE 2. MX29F040 BUS OPERATION

Mode Pins

CE O E W E A0 A1 A6 A9 Q0 ~ Q7

Read Silicon ID L L H L L X VID(2) C 2H
Manufacturer Code(1)
Read Silicon ID L L H H L X VID(2) A4 H
Device Code(1)
Read L L H A0 A1 A6 A9 D
Standby H X X X X X X HIGH Z
Output Disable L H H X X X X HIGH Z
Write L H L A0 A1 A6 A9 DIN(3)
Sector Protect with 12V L VID(2) L X X L VID(2) X
system(6)
Chip Unprotect with 12V L VID(2) L X X H VID(2) X
system(6)
Verify Sector Protect L L H X H X VID(2) Code(5)
with 12V system
Sector Protect without 12V L H L X X L H X
system (6)
Chip Unprotect without 12V L H L X X H H X
system (6)
Verify Sector Protect/Unprotect L L H X H X H Code(5)
without 12V system (7)
Reset X X X X X X X HIGH Z

OUT

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.
Code=01H means protected.
A18~A16=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.
Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V system"

command.

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MX29F040

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg­ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com­mand must then be written to place the device in the
desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu­facturer and device codes must be accessible while the
device resides in the target system. PROM program­mers typically access signature codes by raising A9 to
a high vo ltage. Howe ver , multiplexing high v o ltage o nto
address lines is not generally desired system design
practice.

The MX29F040 contains a Silicon-ID-Read operation to
supplement traditional PROM programming methodol­ogy. The o peratio n is initiated by writing the read silico n
ID command sequence into the co mmand register . F o l­lowing the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of A4H for MX29F040.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two
"unloc k" write cycles. These are f o llo wed by writing the
"set-up" command 80H. Two more "unlock" write cy­cles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au­tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory fo r an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mod e. The system is not required to provide any
control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).

If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE o r CE, whichev er happens first pulse in the com­mand sequence and terminates when the data on Q7 is
"1" and the data on Q6 stops toggling for two consecu­tive read cycles, at which time the device returns to the
Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins A0 A 1 Q 7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)

Manufacture code VIL VIL 1 1 0 0 0 0 1 0 C2 H
Device code for MX29F040 VIH VIL 1 0 1 0 0 1 0 0 A4 H
Sector Protection Verification X VIH 0 0 0 0 0 0 0 1 01H (Protected)

X VIH 0 0 0 0 0 0 0 0 00H(Unprotected)

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SECTOR ERASE COMMANDS

MX29F040

The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the Au­tomatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system is no t required to provide any
control or timing during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mod e. The system is no t
required to provide any control or timing during these
operations.

When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array

(no erase verification command is required). Sector erase
is a six-bus cycle operation. There are two "unlock"
write cycles. These are followed by writing the set-up
command 80H. T w o more "unlo ck" write cycles are then
fo llowed b y the sector er ase command 30H. The secto r
address is latched on the f alling edge of WE or CE, which­ever happens later , while the co mmand (data) is latched
on the rising edge o f WE o r CE, whichev er happens first.
Sector addresses selected are loaded into internal reg­ister on the sixth falling edge of WE or CE, whichever
happens later. Each successive sector load cycle
started by the falling edge of WE o r CE, whichev er hap­pens later must begin within 30us from the rising edge
of the preceding WE or CE, whichever happens first.
Otherwise, the loading period ends and internal auto
sector erase cycle starts. (Monitor Q3 to determine if
the sector erase timer window is still open, see section
Q3, Secto r Erase Timer .) Any co mmand other than Sec­tor Erase (30H) or Erase Suspend (B0H) during the time­out period resets the device to read mode.

TABLE 4. Write Operation Status

Status Q7 Q6 Q5 Q3 Q2

Note1 Note2

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No Toggle
Auto Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspend Read 1 N o 0 N/A Toggle

In Progress (Erase Suspended Sector) Toggle

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data

(Non-Erase Suspended Sector)
Erase Suspend Program Q7 Toggle 0 N/A N/A

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No Toggle
Exceeded Auto Erase Algorithm 0 Toggle 1 1 Toggle
Time Limits Erase Suspend Program Q7 Toggle 1 N/A N/A

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.

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8

MX29F040

ERASE SUSPEND

This command only has meaning while the state ma­chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase o peratio n. When the Erase Suspend co m­mand is written during a sector erase operation, the de­vice requires a maximum of 100us to suspend the erase
operatio ns. Howev er, When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex­ecuted, the command register will initiate erase suspend
mod e. The state machine will return to read mo de auto­matically after suspend is ready . At this time, state ma­chine only allows the command register to respond to
the Read Memory Array, Erase Resume and program
commands.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro­gram operation is complete, the system can once again
read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

T o initiate A utomatic Pro gram mo de, A three-cycle co m­mand sequence is required. There are two "unlo ck" write
cycles. These are f ollow ed by writing the Auto matic Pro­gram command A0H.

tem is not required to pro vide further contro ls o r timings.
The device will automatically provide an adequate inter­nally generated program pulse and verify margin.

If the program operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program o peratio n
exceed internal timing limit. The auto matic pro gramming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data
on Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read mode
(no program verify command is required).

DATA POLLING-Q7

The MX29F040 also features Data P o lling as a metho d
to indicate to the host system that the Automatic Pro­gram or Erase algorithms are either in progress or com­pleted.

While the Automatic Programming algorithm is in opera­tion, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an at­tempt to read the device will produce the true data last
written to Q7. The Data P o lling f eature is valid after the
rising edge of the fo urth WE o r CE, whichev er happens
first pulse of the four write pulse sequences for auto­matic program.

While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data P olling f eature is valid after the rising
edge of the sixth WE or CE, whichever happens first
pulse of six write pulse sequences for automatic chip/
sector erase.

The Data Po lling feature is activ e during Auto matic Pro­gram/Erase algorithm or sector erase time-out. (see sec­tion Q3 Sector Erase Timer)

Once the Automatic Program command is initiated, the
next WE or CE pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the
rising edge of the WE or CE, whichever happens first
pulse. The rising edge of WE o r CE, whichever happens
first also begins the programming operation. The sys-

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9

MX29F040

Q6:Toggle BIT I

Toggle Bit I o n Q6 indicates whether an A uto matic Pro­gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE or CE, whichever
happens first pulse in the command sequence (prior to
the program or erase operation), and during the sector
time-out.

During an Automatic Program or Erase algorithm opera­tion, successive read cycles to any address cause Q6
to toggle . The system may use either OE o r CE to con­trol the read cycles . When the o peratio n is complete , Q6
stops toggling.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus­pended. When the de vice is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus­pended. Alternatively, the system can use Q7.

If a progr am address falls within a protected sector, Q6
toggles for approximately 2us after the program com­mand sequence is written, then returns to reading array
data.

Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo­rithm is complete.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "T oggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether

that sector is er ase-suspended. Toggle Bit I is valid af­ter the rising edge of the final WE o r CE, whichever hap­pens first pulse in the command sequence.

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com­parison, indicates whether the device is actively eras­ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected f or erasure. Thus , both status bits
are required for sectors and mode information. Refer to
Table 4 to compare o utputs f or Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is to ggling. T ypically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the pro gr am o r erase o peratio n. The system
can read array data on Q7-Q0 on the following read cycle.

Howe v e r, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys­tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase op­eration. If it is still toggling, the device did not complete
the operation successfully, and the system must write
the reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta­tus as described in the previous paragraph. Alterna­tively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation.

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MX29F040

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex­ceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully co mpleted. Data Po lling and Toggle Bit
are the only operating functions of the device under this
condition.

If this time-out condition occurs during sector erase op­eration, it specifies that a particular secto r is bad and it
may no t be reused. Ho wev er, o ther secto rs are still func­tional and may be used for the program or erase opera­tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute pro gram o r erase co mmand sequence. This
allows the system to continue to use the other active
sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com­bination of sectors are bad.

If this time-out condition occurs during the byte program­ming operation, it specifies that the entire sector con­taining that byte is bad and this sector may not be re­used, (other sectors are still functional and can be re­used).

specific command sequences. The device also incor­porates several features to prevent inadvertent write
cycles resulting fro m VCC power-up and pow er-down tran­sition or system noise.

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are v alid after the initial sector er ase com­mand sequence.

If Data Po lling o r the Toggle Bit indicates the de vice has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com­mand has been accepted, the system software should
check the status of Q3 prior to and following each sub­sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.

The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Au­tomatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops tog­gling. Once the Device has exceeded timing limits, the
Q5 bit will indicate a "1". Please note that this is not a
device failure condition since the device was incorrectly
used.

DATA PROTECTION

The MX29F040 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi­tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of

P/N:PM0538

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on CE or WE will
not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding an y one of OE = VIL, CE
= VIH o r WE = VIH. T o initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be­tween its VCC and GND .

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11

MX29F040

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F040 features secto r pro tection. This f eature
will disable both program and erase operations for these
sectors protected. To activate this mode, the program­ming equipment must force VID on address pin A9 and
control pin OE, (suggest VID = 12V) A6 = VIL and CE =
VIL. (see Table 2) Programming of the protection cir­cuitry begins on the falling edge o f the WE or CE, which­ever happens later pulse and is terminated on the rising
edge. Please refer to sector protect algorithm and wave­form.

T o v erify programming o f the pro tectio n circuitry , the pro­gramming equipment must fo rce VID o n address pin A9
( with CE and OE at VIL and WE at VIH). When A1=1, it
will produce a logical "1" code at device output Q0 for a
protected secto r . Otherwise the device will pro duce 00H
fo r the unpro tected secto r . In this mo de, the addresses,
except for A1, are don't care. Address locations with A1
= VIL are reserved to read manuf acturer and device co des.
(Read Silicon ID)

It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Perf orming a read o peratio n with A1=VIH, it will pro duce
a logical "1" at Q0 for the protected sector.

CHIP UNPROTECT WITH 12V SYSTEM

is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.

POWER-UP SEQUENCE

The MX29F040 powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command se­quences.

SECTOR PROTECTION WITHOUT 12V SYS­TEM

The MX29F040 also feature a sector protection method
in a system without 12V po wer supply . The programming
equipment do not need to supply 12 volts to protect sec­tors. The details are shown in sector protect algorithm
and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F040 also feature a chip unprotection method
in a system without 12V po wer supply . The programming
equipment do not need to supply 12 volts to unprotect all
sectors. The details are shown in chip unprotect algo­rithm and waveform.

The MX29F040 also features the chip unprotect mode,
so that all sectors are unprotected after chip unprotect
is completed to incorporate any changes in the code. It
is recommended to protect all sectors before activating
chip unprotect mode.

T o activ ate this mode , the prog ramming equipment must
fo rce VID on co ntro l pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algor ithm and wave­fo rm for the chip unprotect algorithm. The unprotectio n
mechanism begins on the f alling edge o f the WE o r CE,
whichever happens later , pulse and is terminated on the
rising edge.

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Perf orming a read o peratio n with A1=VIH, it will pro duce
00H at data o utputs(Q0-Q7) fo r an unpro tected sector . It

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REV. 2.3, DEC. 10, 2004

12