MXIC MX29F022BPC-12, MX29F022BPC-55, MX29F022BPC-70, MX29F022BPC-90, MX29F022BQC-12 Datasheet

...
FEATURES
MX29F022/022N
2M-BIT[256K x 8]CMOS FLASH MEMORY
262,144x 8 only
Fast access time: 55/70/90/120ns
Low power consumption
-1uA typical standby current@5MHz
Programming and erasing voltage 5V ±10%
Command register architecture
-Byte Programming (7us typical)
-Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte x1, and 64K-Byte x 3)
Auto Erase (chip & sector) and Auto Program
-Automatically erase any combination of sectors or the whole chip with Erase Suspend capability.
-Automatically programs and verifies data atspecified address
Erase Suspend/Erase Resume
-Suspends an erase operation to read data from, or program data to, a sector that is not being er ased, then resumes the erase operation.
GENERAL DESCRIPTION
Status Reply
-Data polling & Toggle bit f or detection of program and erase cycle completion.
Chip protect/unprotect for 5V only system or 5V/12V
system
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1 to VCC+1V
Boot Code Sector Architecture
-T = Top Boot Sector
-B = Bottom Boot Sector
Hardware RESET pin
-Resets internal state machine to read mode
Low VCC write inhibit is equal to or less than 3.2V
Pac kage type:
-32-pin PDIP
-32-pin PLCC
-32-pin TSOP (Type 1)
20 years data retention
The MX29F022T/B is a 2-mega bit Flash memory organized as 256K bytes of 8 bits only. MXIC's Flash memories offer the most cost-effectiv e and reliable read/ write non-volatile random access memory.The MX29F022T/B is packaged in 32-pin PDIP, PLCC and 32-pin TSOP(I). It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers.
The standard MX29F022T/B offers access time as fast as 55ns, allowing operation of high-speed microproc essors without wait states. T o eliminate b us contention, the MX29F022T/B has separate chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F022T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
P/N:PM0556 REV. 1.1, JUN. 14, 2001
MXIC's Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combina­tion of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F022T/ B uses a 5.0V ± 10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved f or stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
1
MX29F022/022N
PIN CONFIGURATIONS
32 PDIP
NC on MX29F022NT/B
RESET
A16 A15 A12
GND
A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCC
32
WE
31
A17
30
A14
29
A13
28
A8
27
A9
26
A11
25
OE
24
A10
23
CE
22
MX29F022T/B
Q7
21
Q6
20
Q5
19
Q4
18
Q3
17
(NC on
MX29F022NT/B)
32 PLCC
NC on MX29F022NT/B
A12
A15
A16
RESET
VCCWEA17
4
5
A7 A6 A5 A4
9
A3 A2 A1 A0
13
Q0
14 17 20
Q1
1
32
MX29F022T/B
Q2
Q3Q4Q5
VSS
30
29
A14 A13 A8 A9
25
A11 OE A10 CE
21
Q7
Q6
PIN DESCRIPTION:
SYMBOL PIN NAME
A0~A17 Address Input Q0~Q7 Data Input/Output CE Chip Enable Input WE Write Enable Input RESET Hardware Reset Pin/Sector Protect Unlock OE Output Enable Input VCC Power Supply Pin (+5V) GND Ground Pin
32 TSOP (TYPE 1)
WE
1 2
A9
3
A8
4 5 6 7 8 9 10 11 12 13
A7
14
A6
15
A5
16
A4
A11
A13 A14 A17
VCC
RESET
A16 A15 A12
SECTOR STRUCTURE
A17~A0
3FFFFH
3BFFFH
39FFFH
37FFFH 2FFFFH 1FFFFH
0FFFFH
00000H
A17~A0
3FFFFH 2FFFFH
1FFFFH
0FFFFH
07FFFH 05FFFH 03FFFH
00000H
MX29F022T/B
(NORMAL TYPE)
16 K-BYTE
(BOOT SECTOR)
8 K-BYTE
8 K-BYTE
32 K-BYTE 64 K-BYTE
64 K-BYTE 64 K-BYTE
MX29F022T Sector Architecture
64 K-BYTE
64 K-BYTE 64 K-BYTE
32 K-BYTE
8 K-BYTE 8 K-BYTE
16 K-BYTE
(BOOT SECTOR)
32
OE
31
A10
30
CE
29
Q7
28
Q6
27
Q5
26
Q4
25
Q3
24
GND
23
Q2
22
Q1
21
Q0
20
A0
19
A1
18
A2
17
A3
P/N:PM0556
MX29F022B Sector Architecture
REV. 1.1, JUN. 14, 2001
2
Block Diagram
MX29F022/022N
CE OE
WE
RESET
A0-A17
CONTROL
INPUT LOGIC
ADDRESS
LATCH
AND
BUFFER
PROGRAM/ERASE
HIGH VOLT AGE
X-DECODER
FLASH ARRA Y
Y-DECODER
Y-PASS GATE
ARRAY
SOURCE
HV
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTERMX29F022T/B
COMMAND
DATA
DECODER
P/N:PM0556
Q0-Q7
SENSE
AMPLIFIER
I/O BUFFER
3
PGM DATA
HV
PROGRAM
DATA LATCH
COMMAND
DATA LATCH
REV. 1.1, JUN. 14, 2001
MX29F022/022N
AUTOMATIC PROGRAMMING
The MX29F022T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical chip programming time of the MX29F022T/B at room tem­perature is less than 2 seconds.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10ms erase pulses according to MXIC's High Reliability Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than two second. The device is erased using the Automatic Erase algorithm. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are internally controlled within the device.
AUTOMATIC SECTOR ERASE
The MX29F022T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle . The Automatic Sector Erase algorithm automatically pro­grams the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are inter­nally controlled by the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to write commands to the command register using stan­dard microprocessor write timings. The device will au­tomatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, verifily the erase, and counts the number of sequences . A status bit similar to DATA polling and status bit tog­gling between consecutive read cycles prodvides feed­back to the user as to the status of the programming operation.
Commands are written to the command register using standard microprocessor write timings. Register con­tents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle addresses are latched on the falling edge, and data are latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM experience to produce the highest lev els of quality, reli­ability , and cost eff ectiv eness. The MX29F022T/B elec­trically erases all bits simultaneously using Fowler­Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mecha­nism of hot electron injection.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the user to only write a program set-up commands (include 2 unlock arite cycle and A0H) include 2 unlock arite cycle and A0H and a program command (program data and address). The de vice automatically times the program­ming pulse width, verifies the program verification, and counts the number of sequences. A status bit similar to DAT A polling and a status bit toggling between consecu­tive read cycles, provides f eedback to the user as to the status of the programming operation.
P/N:PM0556
During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode . After the state machine has completed its task, it will allow the command regis­ter to respond to its full command set.
REV. 1.1, JUN. 14, 2001
4
MX29F022/022N
T able 1 Software Command Definitions
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Command Bus Cycle Cycle Cycle Cycle Cycle Cycle
Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA RD Read Silicon ID 4 555H AAH 2AAH 5 5H 555H 90H ADI DDI Chip Protect Verify 4 555H AAH 2AAH 55H 555H 90H (SA) 00 H
X02H 01H Porgram 4 555H AAH 2AAH 55H 555H A0H PA PD Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Sector Erase Suspend 1 XXXH B0H Sector Erase Resume 1 XXXH 30H Unlock for chip 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H protect/unprotect
Note:
1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3). DDI = Data of Device identifier : C2H for manufacture code, 36H/37H for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased.
3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10. Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A17 in either state.
4. For Chip Protect Verify operation:If read out data is 01H, it means the chip has been protected. If read out data is 00H, it means the chip is still not being protected.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
5
MX29F022/022N
TABLE 2. MX29F022T/B BUS OPERATION
Pins CE OE WE A0 A1 A6 A9 Q0~Q7 Mode Read Silicon ID L L H L L X VID(2) C2H Manfacturer Code(1) Read Silicon ID L L H H L X VID(2) 36H/37H Device Code(1) Read L L H A0 A1 A6 A9 Standby H X X X X X X HIGH Z Output Disable L H H X X X X HIGH Z Write L H L A0A1 A6A9 Chip Protect with 12V L VID(2) L X X L VID(2) X system(6) Chip Unprotect with 12V L VID(2) L X X H VID(2) X system(6) V erify chip Protect L L H X H X VID(2) Code(5) with 12V system Chip Protect without 12V L H L X X L H X system (6) Chip Unprotect without 12V L H L X X H H X system (6) V erify Chip Protect/Unprotect L L H X H X H Code(5) without 12V system (7) Reset X X X X X X X HIGH Z
D
OUT
DIN(3)
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected. Code=01H means protected.
6. Refer to chip protect/unprotect algorithm and waveform.
Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command.
7. The "verify chip protect/unprotect without 12V sysytem" is only following "chip protect/unprotect without 12V system" command.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
6
MX29F022/022N
READ/RESET COMMAND
The read or reset operation is initiated by writing the read/reset command sequence into the command reg­ister. Microprocessor read cycles retrieve array data. The device remains enabled f or reads until the command register contents are altered.
If program-fail or er ase-fail happen, the write of F0H will reset the device to abort the operation. A valid com­mand must then be written to place the device in the desired state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and de vice codes must be accessible while the device resides in the target system. PROM pro­grammers typically access signature codes by raising A9 to a high voltage. However, multiplexing high volt­age onto address lines is not generally desired system design practice.
SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are f ollow ed by writing the "set-up" command 80H. Two more "unlock" write cy­cles are then followed b y the chip erase command 10H.
The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the A u­tomatic Chip Erase. Upon ex ecuting the Automatic Chip Erase, the device will automatically progr am and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-z ero pattern, a self-timed chip erase and verification begin. The erase and verification operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.
When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved f or the memory array(no erase verify command is required).
The MX29F022T/B contains a Silicon-ID-Read opera­tion to supplement traditional PROM programming meth­odology. The operation is initiated by writing the read silicon ID command sequence into the command regis­ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manuf acturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 36H for MX29F022T,37H for MX29F022B.
TABLE 3. EXPANDED SILICON ID CODE
Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code VIL VIL 1 1 0 0 0 0 1 0 C2H Device code VIHVIL0011011036H
for MX29F022T Device code VIHVIL0011011137H for MX29F022B Chip Protection Verification X VIH 0 0 0 0 0 0 0 1 01H (Protected)
X VIH 0 0 0 0 0 0 0 0 00H (Unprotected)
If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation of exceed internal timing limit.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles , at which time the device returns to the Read mode.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
7
MX29F022/022N
SET-UP AUTOMATIC SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system does not require to provide any control or timing during these operations.
When the sector(s) is automatically verified to contain an all-zero pattern,a self-timed sector erase and verifi­cation begin. The erase and v erification operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutiv e read cycles, at which time the device returns to the Read mode. The system does not required to provide any control or timing during these operations.
When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achiev ed for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are f ollow ed by writing the set-up command-80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command(data) is latched on the rising edge
of WE. Sector addresses selected are loaded into internal register on the sixth falling edge of WE. Each successive sector load cycle started by the falling edge of WE must begin within 30us from the rising edge of the preceding WE. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase (30H) or Erase Suspend (B0H) during the time-out period resets the device to read mode.
ERASE SUSPEND
This command is only valid while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic/Sec­tor Erase operation. Writing the Erase Suspend com­mand during the Sector Erase time-out immediately ter­minates the time-out period and suspends the erase op­eration. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically af­ter suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array , Erase Resume and Progr am commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspendend program operation is complete, the system can once again read array data within non-suspended sectors.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
8
MX29F022/022N
T able 4. Write Operation Status
Status Q7 Q6 Q5 Q3 Q2
Note1 Note2
Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No Toggle Auto Erase Algorithm 0 Toggle 0 1 Toggle
Erase Suspend Read 1 N o 0 N/A Toggle
In Progress (Erase Suspended Sector) Toggle
Erase Suspended Mode Erase Suspend Read Data Data Data Data Data
(Non-Erase Suspended Sector) Erase Suspend Program Q7 Toggle 0 N/A N/A
Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No Toggle Exceeded Auto Erase Algorithm 0 Toggle 1 1 Toggle Time Limits Erase Suspend Program Q7 Toggle 1 N/A N/A
Note:
1.Q7 and Q2 require a valid address when reading status inf ormation. Refer to the appropriate subsection f or further details.
2.Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " f or more information.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
9
MX29F022/022N
ERASE RESUME
This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was pre viously issued. Erase Resume will not have any effect in all other conditions.Another Erase Suspend command can be written after the chip has resumed erasing.
SET-UP AUTOMATIC PROGRAM COMMANDS
T o initiate A utomatic Program mode, A three-cycle com­mand sequence is required. There are two "unlock" write cycles. These are f ollowed by writing the Automatic Pro­gram command A0H.
Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active program­ming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE pulse. The rising edge of WE also be­gins the programming operation. The system does not require to provide further controls or timings. The de­vice will automatically provide an adequate internally generated program pulse and v erify margin.
If the program opetation was unsuccessful, the data on Q5 is "1", indicating the program operation of internally exceed timing limit. The automatic programming opera­tion is complete when the data read on Q6 stops tog­gling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required).
WRITE OPERA TION STATUS D ATA POLLING-Q7
While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is compete. Upon completion of the erase operation, the data on Q7 will read "1". The Data P olling feature is valid after the rising edge of the secone WE pulse of two write pulse se­quences.
The Data Polling f eature is active during Automatic Pro­gram/Erase algorithm or sector erase time-out.(see sec­tion Q3 Sector Erase Timer)
Q6:Toggle BIT I
The MX29F022T/B features a "Toggle Bit" as a method to indicate to the host system that the Auto Program/ Erase algorithms are either in progress or complete.
During an Automatic Program or Erase algorithm op­eration, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling.
After an erase command sequence is written, if the chip is protected, Q6 toggles and returns to reading array data.
The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus­pended. When the de vice is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-sus­pended. Alternatively, the system can use Q7(see the subsection on Q7:Data Polling).
The MX29F022T/B also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed.
While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data Polling f eature is v alid after the rising edge of the second WE pulse of the two write pulse sequences.
P/N:PM0556
If a program address falls within a protected sector, Q6 toggles for approximately 2us after the progr am com­mand sequence is written, then returns to reading array data.
Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete.
The Write Operation Status table shows the outputs f or Toggle Bit I on Q6. Ref er to the toggle bit algorithmg.
REV. 1.1, JUN. 14, 2001
10
MX29F022/022N
Q2:Toggle Bit II
The "T oggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. T oggle Bit I is v alid after the rising edge of the final WE pulse in the command sequence.
Q2 toggles when the system reads at addresses within those sectors that have been selected f or erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Ref er to Table 4 to compare outputs f or Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Refer to the toggle bit algorithm for the following discussion. Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system w ould note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle.
Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation(top of the toggle bit algorithm flow chart).
Q5
Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions not of the device under this condition.
If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device .
If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is , the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfuly completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and
P/N:PM0556
If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused).
The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system nev er reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.
REV. 1.1, JUN. 14, 2001
11
MX29F022/022N
Q3
Sector Erase Timer
After the completion of the initial sector erase command sequence th sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the inter nally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not ha ve been accepted.
DATA PROTECTION
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be­tween its VCC and GND.
CHIP PROTECTION WITH 12V SYSTEM
The MX29F022T/B features hardware chip protection, which will disable both program and erase operations. T o activate this mode , the programming equipment must force VID on address pin A9 and control pin OE, (sug­gest VID = 12V) A6 = VIL and CE = VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please refer to chip protect algorithm and waveform.
To verify programming of the protection circuitry, the programming equipment must f orce VID on address pin A9 ( with CE and OE at VIL and WE at VIH. When A1=1, it will produce a logical "1" code at device output Q0 for the protected status. Otherwise the device will produce 00H for the unprotected status. In this mode, the addresses,except for A1, are in "don't care" state. Address locations with A1 = VIL are reserved to read manufacturer and device codes .(Read Silicon ID)
The MX29F022T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that ma y exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise .
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
It is also possible to determine if the chip is protected in the system by writing a Read Silicon ID command. Perf orming a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected status.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F022T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code.
T o activate this mode , the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated on the rising edge.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
12
MX29F022/022N
It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Perf orming a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected chip. It is noted that all sectors are unprotected after the chip unprotect algorithm is complete.
CHIP PROTECTION WITHOUT 12V SYSTEM
The MX29F022T/B also feature a hardware chip protection method in a system without 12V power suppply. The programming equipment do not need to supply 12 volts to protect all sectors. The details are shown in chip protect algorithm and wavef orm.
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F022T/B also feature a hardware chip unprotection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and wavef orm.
POWER-UP SEQUENCE
ABSOLUTE MAXIMUM RATINGS
RATING VALUE Ambient Operating Temperature 0oC to 70oC Storage T emperature -65oC to 125oC Applied Input V oltage -0.5V to 7.0V Applied Output V oltage -0.5V to 7.0V VCC to Ground Potential -0.5V to 7.0V A9 -0.5V to 13.5V
NOTICE:
Stresses greater than those listed under ABSOLUTE MAXI­MUM RATINGS may cause permanent damage to the de­vice. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to ab­solute maximum rating conditions for extended period may affect reliability.
NOTICE:
Specifications contained within the following tables are sub­ject to change.
The MX29F022T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of a two-step command sequence. Vpp and Vcc power up sequence is not required.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
13
MX29F022/022N
Temporary Sector Unprotect Operation (only for 29F022T/B)
Start
RESET = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET = VIH
Temporary Sector Unprotect Completed(Note 2)
Note :
1. All protected sectors are temporary unprotected. VID=11.5V~12.5V
2. All previously protected sectors are protected again.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
14
Loading...
+ 32 hidden pages