• Single power supply 5V operation for read, erase and
program
• Fast access time: 90/120ns
• Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase:32 equal sector with of 64KByte each
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends an erase operation to read data from,
or program data to, another sector that is not being
erased, then resumes the erase.
GENERAL DESCRIPTION
The MX29F016 is a 16-mega bit Flash memory organized
as 2M bytes of 8 bits. MXIC's Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX29F016 is packaged in
40-pin TSOP or 44-pin SOP, 48-pin TSOP. It is designed
to be reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29F016 offers access time as fast as
90ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F016 has separate chip enable (CE) and output
enable (OE ) controls.
• Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
• Group Sector protect/unprotect for 5V/12V system.
• Group Sector protection
- Hardware sector protect/unprotect method for each
group which consists of two adjacent sectors
- Temporary group sector unprotect allows code
changes in previously locked sectors
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 40-pin TSOP, 44-pin SOP, 48-pin TSOP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29F016 uses a 5.0V±10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F016 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
P/N:PM0590REV. 1.3, JUN. 13, 2001
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to
100 milliamps on address and data pin from -1V to
VCC + 1V.
Legend:SA=Sector Address ; SGA=Sector Group Address
Note:All sectors are 64 Kbytes in size.
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3
BLOCK DIAGRAM
CE
OE
WE
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLT A GE
MX29F016
WRITE
STATE
MACHINE
(WSM)
A0-A20
ADDRESS
LA TCH
AND
BUFFER
X-DECODER
MX29F016
FLASH
ARRA Y
Y-DECODER
Y-PASS GATE
SENSE
AMPLIFIER
STATE
REGISTER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
P/N:PM0590
Q0-Q7
I/O BUFFER
REV. 1.3, JUN. 13, 2001
4
MX29F016
AUTOMATIC PROGRAMMING
The MX29F016 is byte programmable using the Automatic
Programming algorithm. The Automatic Programming
algorithm makes the external system do not need to have
time out sequence nor to verify the data programmed.
The typical chip programming time at room temperature
of the MX29F016 is less than 15 seconds.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 19 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29F016 is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes
allow sectors of the array to be erased in one erase
cycle. The Automatic Sector Erase algorithm
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.
automatically pre-program and verify the entire array.
Then the device automatically times the erase pulse
width, provides the erase verification, and counts the
number of sequences. A status bit toggling between
consecutive read cycles provides feedback to the user
as to the status of the programming operation.
Register contents serve as inputs to an internal statemachine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches address and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality,
reliability, and cost effectiveness. The MX29F016
electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by
using the EPROM programming mechanism of hot
electron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register
to respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the program
verification, and counts the number of sequences. A
status bit similar to DATA polling and a status bit toggling
between consecutive read cycles, provide feedback to
the user as to the status of the programming operation.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard
microprocessor write timings. The device will
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5
MX29F016
TABLE1. SOFTWARE COMMAND DEFINITIONS
First BusSecond BusThird BusFourth BusFifth BusSixth Bus
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code.
(Refer to Table 3)
DDI = Data of Device identifier : C2H for manufacture code, ADH for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector to be erased.
SGA = Address of the Sector Group Address bits A18-A20 select a uniqul sector group.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .
Address bit A11~A20=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A20 in either state.
4.For Sector Group Protect Verify Operation : If read out data is 01H, it means the sector has been protected.If read
out data is 00H,it means the sector is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read mode.
Table 1 defines the valid register command sequences.
Note that the Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Sector Erase
operation is in progress.
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MX29F016
TABLE 2. MX29F016 BUS OPERATION
ModePins
CEOEWEA0A1A6A9Q0 ~ Q7
Read Silicon IDLLHLLXVID(2)C2H
Manfacturer Code(1)
Read Silicon IDLLHHLXVID(2)ADH
Device Code(1)
ReadLLHA0A1A6A9D
StandbyHXXXXXXHIGH Z
Output DisableLHHXXXXHIGH Z
WriteLHLA0A1A6A9DIN(3)
Sector Protect with 12VLVID(2)LXXLVID(2)X
system(6)
Chip Unprotect with 12VLVID(2)LXXHVID(2)X
system(6)
Verify Sector Group ProtectLLHXHXVID(2)Code(5)
with 12V system
ResetXXXXXXXHIGH Z
OUT
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 13V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected.
Code=01H means protected.
A20~A18=Sector Group address for protect.
6. Refer to sector protect/unprotect algorithm and waveform.
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MX29F016
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array
data. The device remains enabled for reads until the
command register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid command
must then be written to place the device in the desired
state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by raising
A9 to a high voltage. However, multiplexing high voltage
onto address lines is not generally desired system
design practice.
The MX29F016 contains a Silicon-ID-Read operation to
supplement traditional PROM programming
methodology. The operation is initiated by writing the
read silicon ID command sequence into the command
register. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of ADH for MX29F016.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify begin.
The erase and verify operations are completed when the
data on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).
If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 4), indicating the erase operation exceed
internal timing limit.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
TABLE 3. SILICON ID CODE
PinsA0A1Q7Q6Q5Q4Q3Q2Q1Q0Code(Hex)
Manufacture codeVILVIL11000010C2H
Device code for MX29F016VIHVIL10101101ADH
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REV. 1.3, JUN. 13, 2001
SECTOR ERASE COMMANDS
MX29F016
The Automatic Sector Erase does not require the
device to be entirely pre-programmed prior to
executing the Automatic Set-up Sector Erase
command and Automatic Sector Erase command.
Upon executing the Automatic Sector Erase
command, the device will automatically program and
verify the sector(s) memory for an all-zero data
pattern. The system is not required to provide any
control or timing during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and
verify begin. The erase and verify operations are
complete when the data on Q7 is "1" and the data on
Q6 stops toggling for two consecutive read cycles, at
which time the device returns to the Read mode. The
system is not required to provide any control or timing
during these operations.
Table 4. Write Operation Status
When using the Automatic Sector Erase algorithm,
note that the erase automatically terminates when
adequate erase margin has been achieved for the
memory array (no erase verification command is
required). Sector erase is a six-bus cycle operation.
There are two "unlock" write cycles. These are
followed by writing the set-up command 80H. Two
more "unlock" write cycles are then followed by the
sector erase command 30H. The sector address is
latched on the falling edge of WE, while the
command(data) is latched on the rising edge of WE.
Sector addresses selected are loaded into internal
register on the sixth falling edge of WE. Each
successive sector load cycle started by the falling
edge of WE must begin within 80ms from the rising
edge of the preceding WE. Otherwise, the loading
period ends and internal auto sector erase cycle
starts. (Monitor Q3 to determine if the sector erase
timer window is still open, see section Q3, Sector
Erase Timer.) Any command other than Sector
Erase(30H) or Erase Suspend(B0H) during the timeout period resets the device to read mode.
StatusQ7Q6Q5Q3Q2
Byte Program in Auto Program AlgorithmQ7Toggle001
Auto Erase Algorithm0Toggle01Toggle
Byte Program in Auto Program AlgorithmQ7Toggle101
ExceededProgram/Erase in Auto Erase Algorithm0Toggle11N/A
Time Limits Erase Suspended ModeErase Suspend ProgramQ7Toggle10N/A
(Non-Erase Suspended Sector)
Notes:
1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.
2.Performing successive read operations from any address will cause Q6 to toggle.
3.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.
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9
MX29F016
ERASE SUSPEND
This command only has meaning while the state machine
is executing Automatic Sector Erase operation, and
therefore will only be responded during Automatic Sector
Erase operation. However, When the Erase Suspend
command is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation. After this command has
been executed, the command register will initiate erase
suspend mode. The state machine will return to read
mode automatically after suspend is ready. At this time,
state machine only allows the command register to
respond to the Read Memory Array, Erase Resume and
program commands.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend
program operation is complete, the system can once
again read array data within non-suspended blocks.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.
If the program opetation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read
mode(no program verify command is required).
DATA POLLING-Q7
The MX29F016 also features Data Polling as a method
to indicate to the host system that the Automatic Program
or Erase algorithms are either in progress or completed.
While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an
attempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the fourth WE pulse of the four write pulse
sequences for automatic program.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the sixth WE pulse of six write pulse sequences
for automatic chip/sector erase.
SET-UP AUTOMATIC PROGRAM
COMMANDS
To initiate Automatic Program mode, A three-cycle
command sequence is required. There are two "unlock"
write cycles. These are followed by writing the Automatic
Program command A0H.
Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on therising
edge of the WE pulse. The rising edge of WE also begins
the programming operation. The system is not required
to provide further controls or timings. The device will
automatically provide an adequate internally generated
program pulse and verify margin.
P/N:PM0590
The Data Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)
REV. 1.3, JUN. 13, 2001
10
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE pulse in the
command sequence(prior to the program or erase
operation), and during the sector time-out.
During an Automatic Program or Erase algorithm
operation, successive read cycles to any address cause
Q6 to toggle. The system may use either OE or CE to
control the read cycles. When the operation is complete,
Q6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Q6 toggles
and returns to reading array data. If not all selected
sectors are protected, the Automatic Erase algorithm
erases the unprotected sectors, and ignores the selected
sectors that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Automatic
Erase algorithm is in progress), Q6 toggling. When the
device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to
determine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program command
sequence is written, then returns to reading array data.
Q6 also toggles during the erase-suspend-program
mode, and stops toggling once the Automatic Program
algorithm is complete.
Table 4 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid after
the rising edge of the final WE pulse in the command
sequence.
MX29F016
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. Q6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sectors and mode information.
Refer to Table 4 to compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of Q5 is high (see the
section on Q5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as Q5 went high. If
the toggle bit is no longer toggling, the device has
successfuly completed the program or erase operation.
If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the
status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status
of the operation.
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MX29F016
Q5
Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
condition.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use the
other active sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
cycles resulting from VCC power-up and power-down
transition or system noise.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
protected sector to change data in-system. The Temporary
Sector Unprotect mode is activated by setting the RESET
pin to VID(11.5V-12.5V). During this mode, formerly
protected sectors can be programmed or erased as unprotected sector. Once VID is remove from the RESET
pin,all the previously protected sectors are protected
again.
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
If this time-out condition occurs during the byte
programming operation, it specifies that the entire sector
containing that byte is bad and this sector maynot be
reused, (other sectors are still functional and can be
reused).
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system
never reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was incorrectly
used.
DATA PROTECTION
The MX29F016 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically
resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specific command sequences. The device also
incorporates several features to prevent inadvertent write
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
P/N:PM0590
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