MXIC MX27C8111MC-10, MX27C8111MC-12, MX27C8111MC-15, MX27C8111MC-90, MX27C8111PC-10 Datasheet
...
FEATURES
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
NC
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
MX27C8111
PRELIMINARY
MX27C8111
8M-BIT [1M x8/512K x16] CMOS OTP ROM
WITH PAGE MODE
• With Page Mode function, 8-word/16-byte page
• 1M x 8 or 512K x 16 organization
• +12.5V programming voltage
• Fast access time:90/100/120/150 ns
• Page mode access time 50/60/75 ns
• Totally static operation
• Completely TTL compatible
• Operating current: 60mA
• Standby current: 100uA
• Package type:
- 42 pin plastic DIP
- 44 pin SOP
GENERAL DESCRIPTION
The MX27C8111 is a 8M-bit, One Time Programmable
Read Only Memory with page mode. It is organized as
1M x 8 or 512K x 16, operates from a single + 5 volt
supply, has a static standby mode, and features fast
single address location programming. All programming
signals are TTL levels, requiring a single pulse. For
programming outside from the system, existing
EPROM programmers may be used. The MX27C8111
supports a intelligent fast programming algorithm which
can result in programming time of less than two minutes.
MX27C8111 provides Page Read Access Mode which
can greatly reduce the read access time. Normal read
access time and Page Mode read access time is as fast
as 90/50ns. It is designed to be compatible with all
microprocessors and similar applications in which high
perofmrance, large bit storage and simple interfacing
are important design considerations.
This One Time Programmable Read Only Memory is
packaged in industry standard 42 pin dual-in-line plastic
package and 44 pin SOP packages.
PIN CONFIGURATIONS
PDIP
A18
1
A17
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
CE
11
GND
12
13
14
15
16
17
18
19
20
21
MX27C8111
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
1
SOP
REV. 2.6, AUG. 22, 2001P/N: PM0329
MX27C8111
CONTROL
LOGIC
OUTPUT
BUFFERS
Q0~Q14
Q15/A-1
CE
OE
BYTE/VPP
A0~A18
ADDRESS
INPUTS
Y-DECODER
X-DECODER
Y-SELECT
8M BIT
CELL
MAXTRIX
VCC
GND
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
PIN DESCRIPTION
BLOCK DIAGRAM
SYMBOL PIN NAME
A0~A18 Address Input
Q0~Q14 Data Input/Output
CE Chip Enable Input
OE Output Enable Input
BYTE/VPP Word/Byte Selection
/Program Supply Voltage
Q15/A-1 Q15(Word mode)/
LSB addr. (Byte mode)
VCC Power Supply Pin (+5V)
GND Ground Pin
TRUTH TABLE OF BYTE FUNCTION
BYTE MODE(BYTE = GND)
CE OE Q15/A-1 MODE Q0-Q7 SUPPLY CURRENT
H X X Non selected High Z Standby(ICC2)
L H X Non selected High Z Operating(ICC1)
L L A-1 input Selected DOUT Operating(ICC1)
WORD MODE(BYTE = VCC)
CE OE Q15/A-1 MODE Q0-Q14 SUPPLY CURRENT
H X High Z Non selected High Z Standby(ICC2)
L H High Z Non selected High Z Operating(ICC1)
L L DOUT Selected DOUT Operating(ICC1)
NOTE : X = H or L
P/N: PM0329
2
REV. 2.6, AUG. 22, 2001
MX27C8111
FUNCTIONAL DESCRIPTION
THE PROGRAMMING OF THE MX27C8111
When the MX27C8111 is delivered, the chip has all
8M bits in the "ONE" or HIGH state. "ZEROs" are loaded
into the MX27C8111 through the procedure of
programming.
For programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.
Vcc must be applied simultaneously or before Vpp, and
removed simultaneously or after Vpp. When
programming an MXIC One Time Programmable Read
Only Memory, a 0.1uF capacitor is required across Vpp
and ground to suppress spurious voltage transients
which may damage the device.
FAST PROGRAMMING
The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and OE = VIH (Algorithm is shown in
Figure 1). The programming is achieved by applying a
single TTL low level 50us pulse to the CE input after
addresses and data line are stable. If the data is not
verified, an additional pulse is applied for a maximum of
25 pulses. This process is repeated while sequencing
through each address of the device. When the
programming mode is completed, the data in all address
is verified at VCC = VPP = 5V ± 10%.
PROGRAM INHIBIT MODE
Programming of multiple MX27C8111's in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C8111 may be common. A
TTL low-level program pulse applied to an MX27C8111
CE input with VPP = 12.5 ± 0.5 V will program the
MX27C8111. A high-level CE input inhibits the other
MX27C8111s from being programmed.
at VIH, VPP at its programming voltage.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from an One Time Programmable Read Only
Memory that will identify its manufacturer and device
type. This mode is intended for use by programming
equipment for the purpose of automatically matching the
device to be programmed with its corresponding
programming algorithm. This mode is functional in the
25°C± 5°C ambient temperature range that is required
when programming the MX27C8111.
To activate this mode, the programming equipment
must force 12.0 ± 0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C8111, these two identifier bytes are given in the
Mode Select Table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB
(Q15) defined as the parity bit.
READ MODE
The MX27C8111 provides page mode with 8 words/16
bytes per page. In order to get the benefit of fast page
read, the user should keep chip enable(CE) low and
toggle address A0~A2 in word mode or A-1~A2 in byte
mode. Page Read access time(tPA) is equal to the delay
from address stable to data output. It is twice as fast as
normal tACC and is highly recommended.
WORD-WIDE MODE
With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.
PROGRAM VERIFY MODE
Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE at VIL, CE
P/N: PM0329
BYTE-WIDE MODE
With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits
3
REV. 2.6, AUG. 22, 2001
MX27C8111
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.
STANDBY MODE
The MX27C8111 has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX27C8111 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a twoline control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on One Time
Programmable Read Only Memory arrays, a 4.7 uF bulk
electrolytic capacitor should be used between VCC and
GND for each eight devices. The location of the
capacitor should be close to where the power supply is
connected to the array.
MODE SELECT TABLE
BYTE/
MODE CE OE A9 A0 Q15/A-1 VPP(5) Q8-14 Q0-7
Read (Word) VIL VIL X X Q15 Out VCC Q8-14 Out Q0-7 Out
Read (Upper Byte) VIL VIL X X VIH GND High Z Q8-15 Out
Read (Lower Byte) VIL VIL X X VIL GND High Z Q0-7 Out
Output Disable VIL VIH X X High Z X High Z High Z
Standby VIH X X X High Z X High Z High Z
Program VIL VIH X X Q15 In VPP Q8-14 In Q0-7 In
Program Verify VIH VIL X X Q15 Out VPP Q8-14 Out Q0-7 Out
Program Inhibit VIH VIH X X High Z VPP High Z High Z
Manufacturer Code(3) VIL VIL VH VIL 0B VCC 00H C2H
Device Code(3) VIL VIL VH VIH 1B VCC 38H 16H
NOTES: 1. VH = 12.0V ± 0.5V
2. X = Either VIH or VIL.
3. A1-A8, A10-A18 = VIL(for auto select)
P/N: PM0329
4. See DC Programming Characteristics for VPP voltages.
5. BYTE/VPP is intended for operation under DC Voltage conditions
only.
6. Manufacture code = 00C2H
Device code = B816H
4
REV. 2.6, AUG. 22, 2001
FIGURE 1. FAST PROGRAMMING FLOW CHART
MX27C8111
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
VPP = 12.75V
X = 0
PROGRAM ONE 50us PULSE
INTERACTIVE
SECTION
VERIFY SECTION
INCREMENT ADDRESS
FAIL
NO
INCREMENT X
X = 25?
NO
VERIFY WORD
?
PASS
LAST ADDRESS
YES
VCC = VPP = 5.25V
VERIFY ALL WORDS
?
PASS
DEVICE PASSED
YES
FAIL
FAIL
DEVICE FAILED
P/N: PM0329
5
REV. 2.6, AUG. 22, 2001
Loading...