MXIC MX10E8050I Technical data

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Major Difference

PRELIMINARY

MX10E8050I /

MX10E8050IA

Feature

Product Default ISP IAP Package

Clock mode MX10E8050IPC 44 Pin PDIP MX10E8050IQC 6 UART YES 44 Pin PLCC MX10E8050IUC 44 Pin LQFP

MX10E8050IAQC 6 I2C YES 44 Pin PLCC

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

FEATURES

PRELIMINARY

MX10E8050I / MX10E8050IA

- 80C51 CPU core

- 3.0 ~ 3.6V voltage range

- On-chip Flash program memory with in-system programming ( ISP )

- Operating frequency up to 40MHz (12x), 20MHz(6x)

- 64K bytes Flash memory for code memory

- 1280 bytes internal data RAM

- Low power consumption

- Code and data memory expandable to 64K Bytes

- Four 8 bit and one 4 bit general purpose I/O ports

PIN Configurations

6140

- Three standard 16-bit Timers

- In - Application Programming( IAP ) capability

- On-chip Watch Dog Timer

- Four channel PWM outputs/4bit general purpose I/O ports ( PLCC & LQFP only )

- UART

- 7 interrupt sources with four priority level

- 5 volt tolerant input

- 400kb/s I2C

- 6x / 12x clock mode

PLCC44

Pin Function

1 P4.2/PWM2 2 P1.0/T2 3 P1.1/T2EX 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6/SCL

9 P1.7/SDA 10 RST 11 P3.0/RxD 12 P4.3/PWM3 13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1

18 28

Pin Function

16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD 20 XTAL2 21 XTAL1 22 V 23 P4.0/PWM0 24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14

Pin Function

31 P2.7/A15 32 PSEN 33 ALE 34 P4.1/PWM1 35 EA 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

44 34

PRELIMINARY

MX10E8050I / MX10E8050IA

Pin Function

1 P1.5 2 P1.6/SCL 3 P1.7/SDA 4 RST 5 P3.0/RxD 6 P4.3/PWM3 7 P3.1/TxD 8 P3.2/INT0

9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD 14 XTAL2 15 XTAL1

(T2) P1.0

(T2EX) P1.1

LQFP44

P1.2 P1.3 P1.4

P1.5 (SCL)P1.6 (SDA)P1.7

12 22

Pin Function

16 V

17 P4.0/PWM0 18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15 26 PSEN 27 ALE 28 P4.1/PWM1 29 EA 30 P0.7/AD7

Pin Function

31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V

39 P4.2/PWM2 40 P1.0/T2 41 P1.1/T2EX 42 P1.2 43 P1.3 44 P1.4

RESET

(RXD) P3.0

(TXD)P3.1

(INT0) P3.2 (INT1) P3.3

(T0) P3.4 (T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2 XTAL1

VSS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

PDIP 40

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)

Table. 1 Pin Description

Package Type PDIP PLCC LQFP

I/O SYMBOL PIN PIN PIN DESCRIPTION I/O P0.0-P0.7 39-32 43-36 37-30 Port:8-bit open drain bidirectional I/O Port I/O P2.0-P2.7 21-28 24-31 18-25 Port: 8-bit quasi-bidirectional I/O Port with internal pull-up I/O P1.0-P1.7 1-8 2-9 40-44,1-3 Port: 8-bit quasi-bidirectional I/O Port with internal pull-up

, except P1.6 and P1.7 I/O P3.0-P3.7 10-17 11,13-19 5,7-13 Port: 8-bit quasi-bidirectional I/O Port with internal pull-up I/O P4.0~P4.3/ NA 23,34,1,12 17,28,39,6 4bit Quasi-bidirectional I/O port or PWM PWM0~PWM3 I RESET 9 10 4 reset input I VCC 40 44 38 Positive power supply I VSS 20 22 16 Ground I XTAL1 19 21 15 XTAL connection input O XTAL2 18 20 14 XTAL connection output O PSEN 29 32 26 Program store enable output O ALE 30 33 27 Address latch enable output I EA 31 35 29 External access input

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Mnemonic Pin Number Type Name and Function

PDIP PLCC LQFP

P0.0 ~ 0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open drain, bi-directional I/O port. Port 0

P1.0~1.7 1-8 2-9 40-44 I/O Port1: Port 1 is an 8-bit bi-directional I/O port with internal

P2.0~2.7 21-28 24-31 18-25 I/O Port 2 : Port 2 is an 8-bit bi-directional I/O port with internal

P3.0~3.7 10-17 11, 5, I/O Port 3: Port 3 is an 8-bit bi-directional I/O port with internal

20 22 16 I Ground: 0 volt reference 40 44 38 I Power Supply: This is the power supply voltage for normal,

idle and power-down operation

pins have 1s written to them float and can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accessed to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s.

1-3 pull-ups. Port 1 pins that have 1s written to them are pulled

high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Note that P1.6 and P1.7 are open drain pins for I2C function.

Alternate functions for port 1 include: 1 2 40 I/O T2(P1.0): Timer/Counter 2 external count input/clock out 2 3 41 I T2EX(P1.1): Timer/Counter 2 Reload / Capture / Direction

control 3 4 42 I SDA (P1.7): Data line for I2C 4 5 43 I/O SCL (P1.6): Clock line for I2C 5 6 44 I/O 6 7 1 I/O 7 8 2 I/O 8 9 3 I/O

pull-ups. Port2 pins that have 1s written to them are pulled

high by the internal pull-ups and can be used as inputs. As

inputs, Port 2 pins that are externally pulled low will source

current because of the internal pull-ups. Port 2 emits the high

ordered address byte during fetches from external program

memory and during accesses to external data memory that

use 16-bit addresses (MOVX @DPTR). In this application, it

uses strong internal pull-ups when emitting 1s. During

accesses to external data memory using 8-bit addresses

(MOVX@RI), port 2 emits the contents of P2 special

`function register.

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

13-19 7-13 pull-ups. Port 3 pins that have 1s written to them are pulled

high with the internal pull-ups and can be used as inputs. As

inputs, Port 3 pins that are externally pulled low will source

current because of the internal pull-ups. Port 3 also serves

the special features of MX10E8050I family, as listed below: 10 11 5 I RxD (P3.0) : Serial input port 11 13 7 O TxD (P3.1) : Serial output port 12 14 8 I INT0 (P3.2) : External interrupt 0 13 15 9 I INT1 (P3.3) : External interrupt 1 14 16 10 I T0 (P3.4) : Timer 0 external input 15 17 11 I T1 (P3.5) : Timer 1 external input 16 18 12 O WR (P3.6) : External data memory write strobe 17 19 14 O RD (P3.7) : External data memory read strobe

P4.0~P4.3 I/O Port 4: Port 4 is an 4-bit bi-directional I/O port with internal

pull-ups. Port 4 pins that have 1s written to them are pulled

high with the internal pull-ups and can be used as inputs. As

inputs, Port 4 pins that are externally pulled low will source

current because of the internal pull-ups. Port 4 also serves

the special features of MX10E8050I family, as listed below:

P4.0 23 17 I PWM0 (P4.0) : PWM module output 0 P4.1 34 28 I PWM1 (P4.1) : PWM module output 1 P4.2 1 39 I PWM2 (P4.2) : PWM module output 2 P4.3 12 6 I PWM3 (P4.3) : PWM module output 3 RST 9 10 4 I Reset : A high on this pin for eight machine cycles while the

oscillator is running, reset the devices.

ALE 30 33 27 O Address Latch Enable: Output pulse for latching the low byte

of the address during an access to external memory. In

normal operation, ALE is emitted at constant rate of 1/6 the

oscillator frequency in 12x clock mode. 1/3 the oscillator

frequency in 6x clock mode, and can be used for external

timing or clocking. Note that one ALE pulse is skipped during

each access to external data memory.

PSEN 29 32 26 O Program Strobe Enable: The read strobe to external program

memory. When executing code from external program

memory, PSEN is activated twice each machine cycle.,

except the two PSEN activation are skipped during each

access to external data memory. PSEN is not activated

during fetch from internal program memory.

EA 31 35 15 I External Access Enable/ Programming Supply Voltage: EA

must be external held low to enable the device to fetch code

from external program memory locations 0000H and FFFFH

for 64 K devices.

XTAL 1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input

to the internal clock generator circuits.

XTAL 2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

BLOCK DIAGRAM

Vcc Vss

PORT 4

DRIVERS

PORT 4

LATCH

P0.0-P0.7P4.0-P4.3 P2.0-P2.7

PORT 0

DRIVERS

PORT 2

DRIVERS

PRELIMINARY

MX10E8050I / MX10E8050IA

PSEN

ALE

RST

TIMING

AND

CONTROL

RAM ADDR.

INSTRUCTION

RAM PWM

ACC

TMP2

PSW

PORT 1

LATCH

ALU

PORT 0

LATCH

TMP1

STACK

POINTER

T0/T1/T2

SFRs

TIMERS

I2C

PORT 2

LATCH

WATCHDOG

TIMER

ROM

PROGRAM

ADDR.

BUFFER

INCREMENTER

PROGRAM

COUNTER

DPTR

PORT 3

LATCH

P/N:PM0887

OSC.

XTAL1

Specifications subject to change without notice, contact your sales representatives for the most update information.

XTAL2

PORT 1

DRIVERS

P1.0-P1.7

Input Filter

Output Stage

PORT 3

DRIVERS

P3.0-P3.7

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

FUNCTIONAL DESCRIPTION

General

The MX10E8050I Serial is a stand-alone high-performance and low power microcontroller designed for use in many applications which need code programmability. The Flash EPROM offers customers to program the device themselves. This feature increases the flexibility in many applications, not only in development stage, but also in mass production stage. In addition to the 80C51 standard functions, the MX10E8050I Serial provides a number of dedicated hardware functions. MX10E8050I Serial is a control-oriented CPU with on-chip program and data memory. It can execute program with internal memory up to 64k bytes. MX10E8050I Serial has two software selectable modes of reduced activity for power reduction Idle, and Power-down. The idle mode freezes the CPU while allowing the RAM, Timers, serial ports, interrupt system and other peripherals to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. Power-down mode can be terminated by an external reset ,and in addition , by either of the two external interrupts can be terminated as the power down mode does.

MEMORY ORGANIZATION

The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 256 bytes internal data memory (RAM), 1k byte auxiliary data memory (AUX-RAM) and 64k byte internal MTP program memory ( FLASH ROM ).

Program Memory

The program memory address space of the MX10E8050I Serial comprises an internal and an external memory space. The MX10E8050I Serial has 64k byte of program memory on-chip.

Program Protection

If the user choose to set security lock in MTP memory, the program content is protected from reading out of chip.

Internal Data Memory

The internal data memory is divided into three physically separated parts: 256 byte of RAM, 1k bytes of AUX-RAM, and 128 bytes special function register area (SFR). These parts can be addressed as follows (see Fig.1 and Table. 2)

- RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank.

- RAM 128 to 255 can only be addressed indirectly . Address pointers are R0 and R1 of the selected register bank.

- AUX-RAM 0 to 1023 is indirectly addressable as the external data memory locations 0 to 1023 by the MOVX instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. SFRs can only be addressed directly in the address range from 128 to 255.

P/N:PM0887

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REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Table. 2 Internal data memory access

LOCATION ADDRESSED RAM 0 to 127 DIRECT and INDIRECT RAM 128 to 255 INDIRECT only AUX-RAM 0 to 1023 INDIRECT only with MOVX Special Function Register (SFR) 128 to 255 DIRECT only

Fig. 1 shows the internal memory address space. Table 3 shows the Special Function Register (SFR) memory map. Location 0 to 31 at the lower RAM area can be devided into four 8-bit register banks. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations.

The stack can be located anywhere in the internal 256 byte RAM. The stack depth is only limited by the available internal RAM space of 256 bytes. All registers except the Program Counter and the four 8-byte register banks reside in the SFR address space.

Five methods to access memory space are as floww :

- Register

- Direct

- Register-Indirect

- Immediate

- Base-Register plus Index-Register-Indirect. The first three methods can be used for addressing destination operands. Most instructions have a 'destination / source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand.

Access to memory addresses is as follows:

- Register in one of the four 8-byte register banks through Direct or Register-Indirect addressing.

- 256 bytes of internal RAM through Direct or Register-Indirect addressing. Bytes 0-127 of internal RAM may be only be addressed indirectly as data RAM.

- SFR through direct addressing at address location 128-255.

OVERLAPPED SPACE with different access schemes

64k

FLASH memory

INTERNAL PROGRAM MEMORY

255

127

Indirect Only

Direct and Indirect

MAIN RAM SFRs AUX-RAM

SFRs direct only

INTERNAL DATA MEMORY

AUXILIARY RAM through MOVX access

1023

Fig.1 Internal program and data memory address space

P/N:PM0887

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REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Table. 3 SFR Register Map

HIGH NIBBLE OF SFR ADDRESS

LOW 8 9 A B C D E F 0 P0% P1% P2% P3% P4% PSW% ACC% B%

11111111 11111111 11111111 11111111 11111111 00000000 00000000 00000000

1SP PWMC

00000111 10000000

2 DPL AUXR1

00000000 00000000

3 DPH PWMP3

00000000 00000000

4 FMCON PWM2

00000001 00000000

5 FMDATA PWM3

00000000 00000000

6 PWMP2

7 PCON IPH

00000000 00000000

8 TCON% SCON% IE% IP% T2CON% S1CON PDCON

00000000 00000000 00000000 00000000 00000000 00000000 00000000

9 TMOD SBUF SADDR SADEN T2MOD S1STA

00000000 XXXXXXXX 00000000 00000000 11111110 11111000

A TL0 RCAP2L S1DAT

00000000 00000000 00000000

B TL1 RCAP2H S1ADR EBTCON PWMP1

00000000 00000000 00000000 XXXXXX1X 00000000

C TH0 TL2 PWM0

00000000 00000000 00000000

D TH1 TH2 PWM1

00000000 00000000 00000000

E AUXR PWMP0

00000000 00000000

F T3

00000000

11111111

NOTES :

P/N:PM0887

% = Bit addressable register x = Undefined

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Special Function Registers

Symbol Description Direct Bit Address, Symbol, or Alternative Port Function Reset

Address MSB LSB Function

ACC Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H AUXR Auxiliary 8EH - - - - - - EXTRAM AO 00000000B AUXR1 Auxiliary1 A2H - - ENBOOT - - 0 - DPS 00000000B B B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H DPTR Data pointer(2-byte)

Data pointer high DPH Data pointer low 83H 00H DPL 82H 00H EBTCON Enable T3 EBH EB xxxxxx1xB FMCON Flash control E4H PPARAM PALE PCEB POEB PWEB - - PREADYB 00000001B FMDATA Flash data E5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000B

AF AE AD AC AB AA A9 A8

IE Interrupt Enable A8H EA ET2 ES1 ES ET1 EX1 ET0 EX0 00000000B

BF BE BD BC BB BA B9 B8

IP Interrupt priority B8H - PT2 PS1 PS PT1 PX1 PT0 PX0 x0000000B

B7 B6 B5 B4 B3 B2 B1 B0

IPH Interrupt priority B7H - PT2H PS1H PSH PT1H PX1H PT0H PX0H x0000000B

high

87 86 85 84 83 82 81 80

P0 Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

97 96 95 94 93 92 91 90

P1 Port 1 90H P17 P16 P15 P14 P13 P12 P11 P10 FFH

A7 A6 A5 A4 A3 A2 A1 A0

P2 Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 FFH

B7 B6 B5 B4 B3 B2 B1 B0

P3 Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH

C3 C2 C1 C0 P4 Port4 C0H - - - - PWM3 PWM2 PWM1 PWM0 FH PCON Power Control 87H SMOD1 SMOD0 - WLE GF1 GF2 PD IDL 00xx0000B PDCON ROM enable code F8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000B

D7 D6 D5 D4 D3 D2 D1 D0 PSW Program Status Word D0H CY AC F0 RS1 RS0 OV - P 000000x0B PWMC PWM control F1H PWMD DSCB PWM3E PWM2E DSCA PWM1E PWM0E 1000x000B PWMP0 Prescaler vector 0 FEH PWMP PWMP PWMP PWMP PWMP PWMP PWMP PWMP 00000000B

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0

PWMP1 Prescaler vector 1 FBH PWMP PWMP PWMP PWMP PWMP PWMP PWMP PWMP 00000000B

1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0

PWMP2 Prescaler vector 2 F6H PWMP PWMP PWMP PWMP PWMP PWMP PWMP PWMP 00000000B

2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0

PWMP3 Prescaler vector 3 F3H PWMP PWMP PWMP PWMP PWMP PWMP PWMP PWMP 00000000B

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0

PWM0 PWM0 ratio FCH PWM PWM PWM PWM PWM PWM PWM PWM 00000000B

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0

PWM1 PWM1 ratio FDH PWM PWM PWM PWM PWM PWM PWM PWM 00000000B

1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0

PWM2 PWM2 ratio F4H PWM PWM PWM PWM PWM PWM PWM PWM 00000000B

2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0

PWM3 PWM3 ratio F5H PWM PWM PWM PWM PWM PWM PWM PWM 00000000B

3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0

RACAP2H Timer 2 Capture High CBH 00H RACAP2L Timer 2 Capture Low CAH 00H

SADDR Slave Address A9H 00H SADEN Slave address Mask B9H 00H SBUF Serial Data Buffer 99H xxxxxxxxB

9F 9E 9D 9C 9B 9A 99 98 SCON Serial Control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00H SP Stack Pointer 81H 07H

DF DE DD DC DB DA D9 D8 S1CON I2C Control D8H CR2 ENS1 STA STO SI AA CR1 CR0 00H S1STA I2C Status D9H S1STA.7 S1STA.6 S1STA.5 S1STA.4 S1STA.3 00H S1DAT I2C data DAH S1DAT.7 S1DAT.6 S1DAT.5 S1DAT.4 S1DAT.3 S1DAT.2 S1DAT.1 S1DAT.0 00H S1ADR I2C address DBH S1ADR.7 S1ADR.6 S1ADR.5 S1ADR.4 S1ADR.3 S1ADR.2 S1ADR.1 GC 00H TCON Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H

CF CE CD CC CB CA C9 C8 T2CON Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL 00H T2MOD Timer 2 Mode ControlC9H ------T2OEDCEN xxxxxx00B TH0 Timer High 0 8CH 00H TH1 Timer High 1 8DH 00H TH2 Timer High 2 CDH 00H TL0 Timer Low 0 8AH 00H TL1 Timer Low 1 8BH 00H TL2 Timer Low 2 CCH 00H TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H T3 Timer 3 FFH FFH

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

AUXR (8EH)

EXTRAM A0

- EXTRAM : External RAM Select Switch. Set 1 to select (MOVX) the external RAM directly. Default is 0 to switch (MOVX) to external RAM only when the address is larger than 1k.

- AO : Turn off ALE output in internal execution mode.

( 1 : Turn off ) ( 0 : Turn on )

Watchdog Timer/WDT/T3 (FFH)

- WDT consists of an 11-bit prescaler and an 8-bit timer formed by SFR T3.

EBTCON (EBH)

/EW

- /EW: After reset, /EW bit is set, and WDT is disable.

POWER CONTROL Register/PCON (87H)

SMOD1 SMOD0 X WLE GF1 GF0 PD IDL

- SMOD1: Double baud rate bit for UART.

- SMOD0: Frame error detection bit.

- WLE: Watchdog load enable. This flag must be set prior to loading WDT and is cleared when WDT is loaded.

- GF1/GF0: general-purpose flag bit.

- PD: Power-down bit. Setting it activates power-down mode.

- IDL: Idle mode bit. Setting it activates idle mode.

- The CPU & Peripheral status during 2 power saving mode:

Idle mode Power-down mode CPU OFF OFF Int,Timer. ON OFF Oscillator ckt ON OFF

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

I/O facilities

MX10E8050I serial has one 8 bits port, port 0, which is open drain, three 8 bits ports, port1/2/3 and a four-bits port port 4 . They are quasi bi-directional ports except P1.6 and P1.7. These five ports are fully compatible to standard 80C51's port 0/1/2/3/4.

- Port3: pins can be configured individually to provide: external interrupt inputs (external interrupt 0/1); external inputs for Timer/ counter 0 and Timer /counter1, and UART receive / transmit.

- Port 1.6, Port 1.7 : pins are used to be I2C clock and data I/O, which are open drain

Port pins which are not used for alternate functions may be used as normal bidirectional I/O pins. The generation or use of a Port 1 or Port 3 pin as an alternate function is carried out automatically by writing the associated SFR bit with proper value.

+3V

from port latch

input data

read port pin

2 oscillator

penods

INPUT

BUFFER

strong pull-up

I/O PORT

1,2,3,4

exclude P1.6,P1.7

I/O buffers in the MX10E8050I (Ports 1,2,3,4)

P/N:PM0887

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REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Timer/Counter

MX10E8050I Serial Timer/Counter 0 and 1 are fully compatible to standard 80C51's.

The MX10E8050I Serial contains two 16-bit Timer/counters, Timer 0 and Timer 1. Timer 0 and Timer 1 may be programmed to carry out the following functions:

- measure time intervals and pulse durations

- count events

- generate interrupt requests.

Timer 0 and Timer 1 Timers 0 and 1 each have a control bit in TMOD SFR that selects the Timer or counter function of the corresponding Timer. In the Timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding samples, when the transition shows a HIGH in one cycle and a LOW in the next cycle, the counter is incremented. Thus, it takes two machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.

Timer 0 and Timer 1 can be programmed independently to operate in one of four modes (refer to table 5) :

- Mode 0 : 8-bit Timer/counter with devided-by-32 prescaler

- Mode 1 : 16-bit Timer/counter

- Mode 2 : 8-bit Timer/counter with automatic reload

- Mode 3 : Timer 0 :one 8-bit Timer/counter and one 8-bits Timer. Timer 1 :stopped. When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port transmission-rgate generator. With a 16 MHz crystal, the counting frequency of these Timer/counters is as follows:

- in the Timer function, the Timer is incremented at a frequency of 1.33 MHz (oscillator frequency divided by 12).

- in the counter function, the frequency handling range for external inputs is 0 Hz to 0.66 MHz (oscillator frequency divided by 24). Both internal and external inputs can be gated to the Timer by a second external source for directly measuring pulse duration. The Timers are started and stopped under software control. Each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of Mode 3 as previously described.

TMOD : TIMER/COUNTER MODE CONTROL REGISTER This register is located at address 89H.

Table. 4 TMOD SFR (89H)

765 43210 GATE C/ T M1 M0 GATE C/ T M1 M0 (MSB) (LSB) TIMER 1 TIMER 0

keep the above table with the following table

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Table. 5 Description of TMOD bits

MNEMONIC POSITION FUNCTION TIMER 1 GATE TMOD.7 Timer 1 gating control : when set, Timer/counter '1' is enabled only while 'Int1'

pin is high and 'tr1' control bit is set. when cleared, Timer/counter '1' is enabled whenever 'tr1' control bit is set.

C/T TMOD.6 Timer or counter selector: cleared for Timer operation (input from internal

system clock). set for counter operation (input from 'T1' input pin). M1 TMOD.5 Operation mode: see table 6. M0 TMOD.4 Operation mode: see table 6. TIMER 0 GATE TMOD.3 Timer 0 gating control: when set, Timer/Counter '0' is enabled only while 'Int0'

pin is high and 'tr0' control bit is set. when cleared, Timer/counter '0' is enabled

whenever 'tr0' control bit is set. C/T TMOD.2 Timer or counter selector: cleared for Timer operation (input from internal

system clock). set for counter operation (input from 'T0' input pin). M1 TMOD.1 Operation mode: see table 6. M0 TMOD.0 Operation mode: see table 6.

Table. 6 TMOD M1 and M0 operating modes

M1 M0 FUNCTION 0 0 8-bit Timer/counter : 'THx' with 5-bit prescaler. 0 1 16-bit Timer/counter : 'THx' and 'TLx' are cascaded, there is no prescaler. 1 0 8-bit autoload Timer/counter : 'THx' holds a value which is to be reloaded into 'TLx' each time it

overflows.

1 1 Timer 0: TL0 is an 8-bit Timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-

bit Timer controlled by Timer 1 control bits.

1 1 Timer 1 : Timer/counter 1 stopped.

TCON : TIMER/COUNTER CONTROL REGISTER This register is located at address 88H. Notes :

Symbol Description Direct Bit Address, Symbol, or Alternative Port Function Reset

Address MSB LSB Function

TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

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Table. 7 TCON SFR (88H)

76543210 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 (MSB) (LSB)

keep the above table with the following table

Table. 8 Description of TCON bits

MNEMONIC POSITION FUNCTION TF1 TCON.7 Timer 1 overflow flag : set by hardware on Timer/Counter overflow. Cleared when

interrupt is processed. TR1 TCON.6 Timer 1 control bit : set/cleared by software to turn Timer/counter ON/OFF. TF0 TCON.5 Timer 0 overflow flag: set by hardware on Timer/Counter overflow. Cleared when

interrupt is processed. TR0 TCON.4 Timer 0 control bit : set/cleared by software to turn Timer/counter ON/OFF. IE1 TCON.3 Interrupt 1 edge flag: set by hardware when external interrupt is detected. Cleared

when interrupt is processed. IT1 TCON.2 Interrupt 1 type control bit : set/cleared by software to specify falling edge/LOW

level triggered external interrupt. IE0 TOCN.1 Interrupt 0 edge flag: set by hardware when external interrupt is detected. Cleared

when interrupt is processed. IT0 TOCN.0 Interrupt 0 type control bit: set/cleared by software tospecify falling edge/LOW

level triggered external interrupt.

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TIMER 2 OPERATION

Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/ T2* in the special function register T2CON (see Figure 2). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 9.

Capture Mode

In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure B (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/6 pulses (osc/12 in 12 clock mode).).

Auto-Reload Mode ( Up or Down Counter )

In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2* in T2CON]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Figure 4). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin.

Figure 5 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means.

If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1.

In Figure 6 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.

When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2.

The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.

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(MSB) (LSB)

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

Symbol Position Name and Significance TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set

EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and

RCLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock

TCLK T2CON.4 Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock

EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative

TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. C/T2

CP/RL2

T2CON.1 Timer or counter select. (Timer 2)

T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When

when either RCLK or TCLK = 1.

EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

0 = Internal timer (OSC/6 in 6 clock mode or OSC/12 in 12 clock mode) 1 = External event counter (falling edge triggered).

cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow .

CP/RL2

Figure 2. Timer / Counter 2 (T2CON) Control Register

Table 9 : Timer 2 Operation Modes

RCLK + TCLK CP / RL2 TR2 MODE

0 0 1 16-bit Auto-reload

0 1 1 16-bit Capture

1 X 1 Baud rate generator

X X 0 ( off )

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OSC

T2 Pin

T2EX Pin

Transition

Detector

C/T2

= 0

= 1

EXEN2

Control

TR2

Control

Capture

TL2

(8-bits)

RCAP2L RCAP2H

TH2

(8-bits)

TF2

EXF2

* n = 12 in 12 clock mode.

n = 6 in 6 clock mode.

Figure 3 : Timer 2 in Capture Mode

T2MOD Address = 0C9H Reset Value = XXXX XX00B

Not Bit Addressable

Timer 2

Interrupt

DCENT2OE

Bit

76543210

Symbol Function

- Not implemented, reserved for future use.* T2OE Timer 2 Output Enable bit.

DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter .

* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

Figure 4 : Timer 2 Mode (T2MOD) Control Register

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OSC

T2 PIN

T2EX PIN

TRANSITION

DETECTOR

* n = 12 in 12 clock mode.

n = 6 in 6 clock mode.

C/T2 = 0

C/T2

= 1

EXEN2

CONTROL

TR2

CONTROL

RELOAD

TL2

(8-BITS)

RCAP2L RCAP2H

TH2

(8-BITS)

Figure 5 : Timer 2 in Auto-Reload Mode (DCEN = 0)

(DOWN COUNTING RELOAD VALUE)

FFH FFH

TF2

EXF2

TOGGLE

TIMER 2

INTERRUPT

OSC

T2 PIN

* n = 12 in 12 clock mode.

n = 6 in 6 clock mode.

C/T2 = 0

C/T2

= 1

TL2 TH2

OVERFLOW

CONTROL

TR2

RCAP2L RCAP2H

(UP COUNTING RELOAD VALUE) T2EX PIN

Figure 6 : Timer 2 Auto-Reload Mode (DCEN = 1)

COUNT DIRECTION 1 = UP 0 = DOWN

TF2

EXF2

INTERRUPT

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OSC

T2 Pin

÷ n*

Transition

Detector

C/T2 = 0

C/T2

= 1

TR2

Control

TL2

(8-bits)

RCAP2L RCAP2H

TH2

(8-bits)

PRELIMINARY

MX10E8050I / MX10E8050IA

Timer 1

Overflow

÷ 2

"0"

"1"

"0"

"1"

÷ 16

Reload

"1"

"0"

SMOD

RCLK

RX Clock

TCLK

TX Clock

T2EX Pin

* n = 2 in 12 clock mode.

n = 1 in 6 clock mode.

EXF2

Control

EXEN2

Note availability of additional external interrupt.

Timer 2

Interrupt

Figure 7. Timer 2 in Baud Rate Generator Mode

Table 10 : Timer 2 Generated Commonly Used Baud Rates

Baud Rate Timer 2

12 clock

mode

Osc Freq

RCAP2H RCAP2L

375 k 12 MHz FF FF

9.6 k 12 MHz FF D9

2.8 k 12 MHz FF B2

2.4 k 12 MHz FF 64

1.2 k 12 MHz FE C8 300 12 MHz FB 1E 110 12 MHz F2 AF 300 6 MHz FD 8F 110 6 MHz F9 57

Baud Rate Generator Mode

Bits TCLK and / or RCLK in T2CON (Table 10) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK = 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK = 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With there two bits, the serial port can have different receive and transmit baud rates - one generated by Timer1, the other by Timer2.

Figure 7 shows the Timer2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.

The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate given below :

Timer 2 Overflow Rate

Modes 1 and 3 Baud Rates =

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The Timer can be configured for either "timer" or "counter" operation. In many applications, it is configured for "timer" operation ( C/T 2* = 0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle ( i.e., 1/6 the oscillator frequency in 6 clock mode, 1/ 12 the oscillator frequency in 12 clock mode). As a baud rate generator, it increments at the oscillator frequency in 6 clock mode (OSC/2 in 12 clock mode). Thus the baud rate formula is as follows :

Oscillator Frequency

Modes 1 and 3 Baud Rates =

Where : (RCAP2h, RCAP2L) = The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

The Timer 2 as a baud rate generator mode shown in Figure7, is valid only if RCLK and / or TCLK = 1in T2CON register. Note that a rollover in TH2 does not set TF2, and Will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baudrate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer / counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.

[ n * x [65536 - (RCAP2H, RCAP2L) ] ]

*n = 32 in 12 clock mode or 16 in 6 clock mode

When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and / or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.

Table 10 shows commonly used baud rates and how they can be obtained from Timer 2.

Summary Of Baud Rate Equations

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is :

Timer 2 Overflow Rate

Baud Rate =

If Timer 2 is being clocked internally, The baud rate is :

Baud Rate =

OSC

[ n * x [65536 - (RCAP2H, RCAP2L) ] ]

*n = 32 in 12 clock mode or 16 in 6 clock mode

Where f

= Oscillator Frequency

OSC

To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as :

RCAP2H, RCAP2L = 65536 - ( )

OSC

n * x Baud Rate

Timer / Counter 2 Set-up

Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 11 for set-up of Timer 2 as a timer. Also see Table 12 for set-up of Timer 2 as a counter.

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Table 11 : Timer 2 as a Timer

T2CON

MODE INTERNAL CONTROL EXTERNAL CONTROL

(Note 1) (Note 2) 16-bit Auto-Reload 00H 08H 16-bit Capture 01H 09H Baud rate generator receive and transmit same baud rate 34H 36H Receive only 24H 26H Transmit only 14H 16H

Table 12 : Timer 2 as a Counter

T2CON

MODE INTERNAL CONTROL EXTERNAL CONTROL

(Note 1) (Note 2) 16-bit 02H 0AH Auto-Reload 03H 0BH

NOTES :

1. Capture / reload occurs only on timer / counter overflow.

2. Capture / reload occurs on timer / counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generatior mode.

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Interrupt system

The MX10E8050I Serial contains a 7-source (2 external interrupts, Timer 0, Timer1, Timer2, I2C and UART) with four priority levels interrupt structure.

Each External interrupts INT0 and INT1, can be either level-activated or transition-activated depending on bits IT0 and IT1 in TCON SFR. The flags that actually generate these interrupts are bits IE0, IE1 in TCON. When an external interrupt is generated, the corresponding request flag is cleared by the hardware where the service routine is vectored to, if the interrupt is transition-activated. If the interrupt is level-activated the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactive the request before the interrupt service routine is completed, otherwise another interrupt will be generated.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a Timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.

IE : INTERRUPT ENABLE REGISTER This register is located at address A8H.

Table. 13 IE SFR (A8H)

76543210 EA ET2 ES1 ES ET1 EX1 ET0 EX0 (MSB) (LSB)

keep the above table with the following table

Table. 14 Description of IE bits

MNEMONIC POSITION FUNCTION EA IE.7 Disable all interrupt

- Low, all disabled.

- High, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.

ET2 IE.6 Enable / Disable Timer2 interrupt.

- Low, disabled

- High, enabled

ES1 IE.5 Enable / Disable l2C Interrupt.

- Low, disabled

- High, enabled

ES IE.4 Enable / Disable UART interrupt.

- Low, disabled

- High, enabled ET1 IE.3 Enable / Disable Timer1 overflow interrupt. EX1 IE.2 Enable / Disable External interrupt 1.

- Low, disabled

- High, enabled ET0 IE.1 Enable / disable Timer0 overflow interrupt. EX0 IE.0 Enable / Disable External interrupt 0.

- Low, disabled

- High, enabled

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IP : INTERRUPT PRIORITY REGISTER This register is located at address B8H.

Table. 15 IP SFR (B8H)

76543210

- PT2 PS1 PS PT1 PX1 PT0 PX0 ( LSB )

keep the above table with the following table

Table. 16 Description of IP bits

MNEMONIC POSITION FUNCTION

- IP.7 RESERVED PT2 IP.6 Define Timer2 interrupt priority level.

- High, assign a high priority level.

PS1 IP.5 Define I2C interrupt priority level.

- High, assign a high priority level.

PS IP.4 Define interrupt priority level of UART. PT1 IP.3 Define Timer1 overflow interrupt priority level. PX1 IP.2 Define External interrupt 1 interrupt priority level.

- High, assign a high priority level.

PT0 IP.1 Define Timer0 overflow interrupt priority level. PX0 IP.0 Define External interrupt 0 interrupt priority level.

- High, assign a high priority level.

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IPH : INTERRUPT HIGH PRIORITY REGISTER This register is located at address B7H.

Table. 17 IPH SFR (B7H)

76543210

- PT2H PS1H PSH PT1H PX1H PT0H PX0H ( LSB )

keep the above table with the following table

Table. 18 Description of IPH bits

MNEMONIC POSITION FUNCTION

- IPH.7 RESERVED PT2H IPH.6 Define Timer2 interrupt priority level.

- High, assign a high priority level.

PS1H IPH.5 Define I2C interrupt priority level.

- High, assign a high priority level.

PSH IPH.4 Define interrupt priority level of UART. PT1H IPH.3 Define Timer1 overflow interrupt priority level. PX1H IPH.2 Define External interrupt 1 interrupt priority level.

- High, assign a high priority level.

PT0H IPH.1 Define Timer0 overflow interrupt priority level. PX0H IPH.0 Define External interrupt 0 interrupt priority level.

- High, assign a high priority level.

PRELIMINARY

MX10E8050I / MX10E8050IA

NAME PRIORITY WITHIN LEVEL VECTOR ADDRESS IE0 (HIGHEST) 1 0003H I2C 2 002BH TF0 3 000BH IE1 4 0013H TF1 5 001BH RI + TI 6 0023H TF2 + EXF2 (LOWEST) 7 0033H

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OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the datasheet must be observed.

RESET

A reset is accomplished by holding the RST pin high for at least two and half machine cycles (15 oscillator periods in 6-clock mode, or 30 oscillator periods in 12-clock mode), while the oscillator is running. To ensure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up.

Ports 1,2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH (min.) is applied to RST.

IDLE MODE

In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.

POWER_DOWN MODE

In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. The power-down mode can be terminated by a RESET in the same way as in the 80C51 or in addition by one of two external interrupts, INT0 or INT1. A termination with an external interrupt does ont affect the internal data memory and does not affect the internal data memory and does not affect the special function registers. This makes it possible to exit power-down without changing the port output levels. To terminate the power-down mode with any external interrupt INT0 or INT1 must be switched to level-sensitive and must be enabled. The external interrupt input signal INT0 and INT1 must be kept low until the oscillator has restarted and stabilized. An instruction following the instruction that puts the device in the power-down mode will be executed. A reset generated by the watchdog timer terminates the power-down mode in the same way as an external RESET, and only the contents of the on-chip RAM are preserved. The control bits for the reduced power modes are in the special function register PCON.

DESIGN CONSIDERATIONS

At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up.

When the idle mode is terminated by a hardware reset, the device normally resumes program exectution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory.

Table 19 shows the state of I/O ports during low current operation modes.

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Table 19. External Pin Status During Idle and Power-Down Modes

MODE PROGRAM MEMORY ALE PSEN PORT0 PORT1 PORT2 PORT3

IDLE Internal 1 1 Data Data Data Data

IDLE External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data FF Data

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Watchdog Timer

The Watchdog Timer (WDT) see Fig.8 , consists of an 11-bit prescaler and an 8-bit Timer formed by SFR T3. The Timer is incremented every 1.5 ms, derived from the system clock frequency of 16 MHz by the following formula : f

= f

Timer

overflow occurs, the microcontroller is reset. The internal RESET signal is not inhibited when the external RST pin is kept 0 into high impedance, no matter if the XTAL-clock is running or not.

To prevent a system reset the Timer must be reloaded in time by the application software. If the processor suffers a hardware / software malfunction, the software will fail to reload the Timer. This failure will result in an overflow thus prevent the processor from running out of control. This time interval is determined by the 8-bit reload value that is written into register T3.

Watchdog time interval = [ 100 - T3 ] x 12 x 2048 / oscillator frequency (12x mode)

The watch-dog Timer can only be reloaded if the condition flag WLE (SFR PCON bit 4) has been previously set high by software. At the moment the counter is loaded WLE is automatically cleared.

In the idle state the watchdog Timer and reset circuitry remain active.

/ (12 x (2048)). The 8-bit Timer increments every 12 x 2048 cycles of the on-chip oscillator. When a Timer

clk

[ 100 - T3 ] x 6 x 2048 / oscillator frequency ( 6x mode)

The watchdog Timer is controlled by the watchdog enable signal EW (SFR EBTCON bit 1). A LOW level enables the watchdog Timer. A HIGH level disable the watchdog Timer.

Internal Bus

CLK

/12

Prescaler

(11-bit)

Clear

Write T3

Timer T3

(8-bit)

LOAD LOADEN

Clear

WLE

PCON. 4 PCON. 1

to reset circuitry

LOADEN

P/N:PM0887

Internal Bus

Fig. 8 Watchdog Timer T3

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Pulse Width Modulated Outputs

The MX10E8050I contains four pulse width modulated output channels. These channels generate pulses of programmable length and interval. Two kinds of user modes are available. One is to use two channels as a pair of PWM output with one prescaler and four channels as two pairs of PWM outputs with each own single prescaler. The operation thus is like two set of independently PWM modules. The repetition frequency is defined by an 8-bit prescaler, which supplies the clock for the counter. The prescaler and counter are common to the both PWM channels in each set. The 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two registers: PWM0 and PWM1 or PWM2 and PWM3. Provided the contents of either of these registers is greater than the counter value, the corresponding PWM0 or PWM1 or PWM2 or PWM3 output is set LOW. If the contents of these registers are equal to, or less than the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the registers PWM0 and PWM1 or PWM2 and PWM3. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. The other one operation is that to use four channels as four independently PWM outputs with each own prescaler.

PWM

2 x (1 + PWMP) x 255

OSC

This gives a repetition frequency range of 123Hz to 31.4KHz (f

= 16MHz). At f

OSC

= 24MHz, the frequency range

OSC

is 184Hz to 47.1KHz. By loading the PWM registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH.

When a compare register (PWM0 or PWM1 or PWM2 or PWM3) is loaded with a new value, the associated output is updated immediately. It does not have to wait until the end of the current counter period. Every PWMn output pins are driven by push-pull drivers. These pins are not used for any other purpose.

The PWM function is enabled by setting SFR PWMC. SFR PWMC also controls operational mode and enable out. After reset, P4.0 to P4.3 are used to as the PWM output.

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

PWM Module Prescaler frequency control Register / PWMPX

PWMPX.7 PWMPX.6 PWMPX.5 PWMPX.4 PWMPX.3 PWMPX.2 PWMPX.1 WMPX.0

PWMPX X = 0, 1, 2, or 3

PWMP0 0FEH PWMP1 0FBH PWMP2 0F6H PWMP3 0F3H

BIT SYMBOL FUCTION PWMPX.7-0 PWMPX.7-0 Prescaler division factor = (PWMPX) + 1

PWM Module Pulse width Register / PWMX

PWMX.7 PWMX.6 PWMX.5 PWMX.4 PWMX.3 PWMX.2 PWMX.1 PWMX.0

PWMX X = 0, 1, 2, or 3

PWM0 0FCH PWM1 0FDH PWM2 0F4H PWM3 0F5H

BIT SYMBOL FUCTION PWMX.7-0 PWMX.7-0 LOW/HIGH ration of PWMX signal = (PWMX) / [255 - (PWMX)]

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PWM0/2

PRELIMINARY

MX10E8050I / MX10E8050IA

DSCA/DSCB = 1

Internal Bus

fCKL

1/2

PRESCALE (PWMP 0/2)

PRESCALE (PWMP 1/3)

8-BIT COMPARATOR

8-BIT COUNTER

8-BIT COMPARATOR

PWM1/3

OUTPUT BUFFER

DSCA/DSCB = 0

PWM 0/2

PWM 1/3

Internal Bus

P/N:PM0887

PWM0/2

OUTPUT BUFFER

CKL

1/2

PRESCALE (PWMP 0,1)

(PWMP 2,3)

8-BIT COMPARATOR

8-BIT COUNTER

8-BIT COMPARATOR

PWM1/3

Fig. 9 Functional Diagram of Pulse Width Modulated Outputs

Specifications subject to change without notice, contact your sales representatives for the most update information.

PWM 0/2

PWM 1/3

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

UART

Enhanced UART

In addition to the standard operation the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 10). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recogintion is shown in figure 12.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address.

Mode 0 is the Shift Register mode and SM2 is ignored.

Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme:

Slave 0 SADDR = 1100 0000

SADEN = 1111 1101 Given = 1100 00X0

Slave 1 SADDR = 1100 0000

SADEN = 1111 1110 Given = 1100 000X

In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave

0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:

P/N:PM0887

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REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Slave 0 SADDR = 1100 0000

SADEN = 1111 1001 Given = 1100 0XX0

Slave 1 SADDR = 1110 0000

SADEN = 1111 1010 Given = 1110 0X0X

Slave 2 SADDR = 1110 0000

SADEN = 1111 1100 Given = 1110 00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

SCON Address = 98H

Reset Value = 0000 0000B

Bit Addressable

SM0/FE SM1 SM2 REN TB8 RB8 Tl Rl

Bit: 76543210

(SMOD0 = 0/1)*

Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) SM1 Serial Port Mode Bit 1

SM0 SM1 Mode Description Baud Rate**

0 0 0 shift register f

/6 (6-clock mode) or f

OSC

/12 (12-clock mode)

OSC

0 1 1 8-bit UART variable 1 0 2 9-bit UART f

OSC

/32 or f /64 or f

/16 (6-clock mode) or

OSC

/32 (12-clock mode)

OSC

1 1 3 9-bit UART variable

SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0 is located at PCON6. **f

= oscillator frequency

OSC

P/N:PM0887

Figure 10. SCON : Serial Port Control Register

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

MX10E8050I / MX10E8050IA

D0 D1 D2 D3 D4 D5 D6 D7 D8

PRELIMINARY

START

BIT

SM0 / FE SM1 SM2 REN TB8 RB8 TI RI

SMOD1 SMOD0 ± POF LVF GF0 GF1 IDL

0 : SCON.7 = SM0 1 : SCON.7 = FE

DATA BYTE

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

Figure 11. UART Framing Error Detection

D0 D1 D2 D3 D4 D5 D6 D7 D8

SM0 SM1 SM2 REN TB8 RB8 TI RI

1 1

1 0

11 X

ONLY IN

MODE 2, 3

SCON

(98H)

PCON

(87H)

STOP

BIT

SCON

(98H)

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND ªRECEIVED ADDRESSº = ªPROGRAMMED ADDRESSº ± WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES ± WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

COMPARATOR

Figure 12. UART Multiprocessor Communication, Automatic Address Recognition

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Serial I/O

The MX10E8050I Serial is equipped with two independent serial ports : SIO0 and SIO1. SIO0 is a full duplex UART port and is identical to the 80C51 serial port.

SIO0 : SIO0 is a full duplex serial I/O port identical to that on the 80C51. It's operation is the same, including the use of timer 1 as a baud rate generator.

SIO1, I2C Serial I/O : The I2C bus uses two wires ( SDA and SCL ) to transfer information between devices connected to the bus. The main features of the bus are :

- Bidirectional data transfer between masters and slaves

- Multimaster bus ( no central master )

- Arbitration between simultaneously transmitting masters without corruption of serial data on the bus

- Serial clock synchronization allows devices with different bit rates to communicate via one serial bus

- Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer

- The I2C bus may be used for test and diagnostic purposes

The output latches of P1.6 and P1.7 must be set to logic 1 in order to enable SIO1.

The MX10E8050I Serial on-chip I2C logic provides a serial interface that meets the I2C bus specification and supports all transfer modes ( other than the low-speed mode ) from and to the I2C bus. The SIO1 logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register ( S1STA ) reflects the status of SIO1 and the I2C bus.

The CPU interfaces to the I2C logic via the following four special function register : S1CON ( SIO1 control register ), S1STA ( SIO1 status register ), S1DAT ( SIO1 data register ), and S1ADR ( SIO1 slave address register ). The SIO1 logic interfaces to the external I2C bus via two port 1 pins : P1.6/SCL ( serial clock line ) and P1.7/SDA ( serial data line ).

A typical I2C bus configuration is shown in Figure 13, and Figure 14 shows how a data transfer is accomplished on the bus. Depending on the state of the direction bit ( R/W ), two types of data transfers are possible on the I2C bus:

1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte.

2. Data transfer from a slave transmitter to a master receiver. The first byte ( the slave address ) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released.

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Modes of Operation: The on-chip SIO1 logic may operate in the following four modes:

1. Master Transmitter Mode:

Serial data output through P1.7/SDA while P1.6/SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 0, and we say that a “W” is transmitted. Thus the first byte transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer.

2. Master Receiver Mode:

The first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 1, and we say that an “R” is transmitted. Thus the first byte transmitted is SLA+R. Serial data is received via P1.7/SDA while P1.6/SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are output to indicate the beginning and end of a serial transfer.

3. Slave Receiver Mode:

Serial data and the serial clock are received through P1.7/SDA and P1.6/SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit.

4. Slave Transmitter Mode:

The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via P1.7/SDA while the serial clock is input through P1.6/SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.

In a given application, SIO1 may operate as a master and as a slave. In the slave mode, the SIO1 hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, SIO1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer.

SIO1 Implementation and Operation: Figure 15 shows how the on-chip I2C bus interface is implemented, and the following text describes the individual blocks.

INPUT FILTERS AND OUTPUT STAGES

The input filters have I2C compatible input levels. If the input voltage is less than 1.5V, the input logic level is interpreted as 0; if the input voltage is greater than 3.0V, the input logic level is interpreted as 1. Input signals are synchronized with the internal clock (f

/4), and spikes shorter than three oscillator periods are filtered out.

OSC

The output stages consist of open drain transistors that can sink 3mA at V

< 0.4V. These open drain outputs do not

OUT

have clamping diodes to VDD. Thus, if the device is connected to the I2C bus and VDD is switched off, the I2C bus is not

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

affected.

ADDRESS REGISTER, S1ADR

This 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which SIO1 will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (00H) recognition.

COMPARATOR

The comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in S1ADR). It also compares the first received 8-bit byte with the general call address (00H). If an equality is found, the appropriate status bits are set and an interrupt is requested.

SHIFT REGISTER, S1DAT

This 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been received. Data in S1DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT.

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

SDA

C bus

MSB

P1.7/SDA P1.6/SCL

MX10E8050I / IA

Slave Address

Other Device with

C Interface

Figure 13. Typical I2C Bus Configuration

R/W

Direction

Bit

Acknowledgment

Signal from Receiver

Clock Line Held Low While

Interrupts Are Serviced

Other Device with

C Interface

Acknowledgment

Signal from Receiver

SDA

SCL

Stop

Condition

Repeated

Start

Condition

SCL

Start

Condition

1 2 7 8 9 1 2 3±8

ACK

Repeated if more bytes

are transferred

Figure 14. Data Transfer on the I2C Bus

ACK

P/S

P/N:PM0887

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

P1.7/SDA

P1.6/SCL

P1.7

Input Filter

Output

Stage

Input Filter

Output

Stage

Timer 1

Overflow

S1ADR

S1DAT

Address Register

Arbitration &

Sync Logic

Serial Clock

Generator

Comparator

Shift Register

Timing

Control

Logic

ACK

OSC

Interrupt

Internal Bus

P1.6

S1CON

Status Bits

S1STA

Control Register

Status

Decoder

Status Register

Figure 15. I2C Bus Serial Interface Block Diagram

P/N:PM0887

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REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

(3)

ACK

SDA

SCL

(1) (1) (2)

234 89

1. Another device transmits identical serial data.

2. Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is lost, and SIO1 enters the slave receiver mode.

3. SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.

Figure 16. Arbitration Procedure

SDA

(1)

SCL

(2)

(3) (1)

Mark

Duration

Space Duration

1. Another service pulls the SCL line low before the SIO1"mark" duration is complete. The serial clock generator is immediately reset and commences with the "space" duration by pulling SCL low.

2. Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into the wait state until the SCL line is released.

3. The SCL line is released, and the serial clock generator commences with the mark duration.

Figure 17. Serial Clock Synchronization

P/N:PM0887

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REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

ARBITRATION AND SYNCHRONIZATION LOGIC

In the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus. If another device on the bus overrules a logic 1 and pulls the SDA line low, arbitration is lost, and SIO1 immediately changes from master transmitter to slave receiver. SIO1 will continue to output clock pulses (on SCL) until transmission of the current serial byte is complete.

Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode can only occur while SIO1 is returning a “not acknowledge: (logic 1) to the bus. Arbitration is lost when another device on the bus pulls this signal LOW. Since this can occur only at the end of a serial byte, SIO1 generates no further clock pulses. Figure 16 shows the arbitration procedure.

The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the “mark” duration is determined by the device that generates the shortest “marks,” and the “space” duration is determined by the device that generates the longest “spaces.” Figure 17 shows the synchronization procedure.

A slave may stretch the space duration to slow down the bus master. The space duration may also be stretched for handshaking purposes. This can be done after each bit or after a complete byte transfer. SIO1 will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared.

SERIAL CLOCK GENERATOR

This programmable clock pulse generator provides the SCL clock pulses when SIO1 is in the master transmitter or master receiver mode. It is switched off when SIO1 is in a slave mode. The programmable output clock frequencies are: f

OSC

/120, f

/9600, and the Timer 1 overflow rate divided by eight. The output clock pulses have a 50% duty

OSC

cycle unless the clock generator is synchronized with other SCL clock sources as described above.

TIMING AND CONTROL

The timing and control logic generates the timing and control signals for serial byte handling. This logic block provides the shift pulses for S1DAT, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the I2C bus status.

CONTROL REGISTER, S1CON

This 7-bit special function register is used by the microcontroller to control the following SIO1 functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment.

STATUS DECODER AND STATUS REGISTER

The status decoder takes all of the internal status bits and compresses them into a 5-bit code. This code is unique for each I2C bus status. The 5-bit code may be used to generate vector addresses for fast processing of the various service routines. Each service routine processes a particular bus status. There are 26 possible bus states if all four modes of SIO1 are used. The 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. The three least significant bits of the status register are always zero. If the status code is used as a vector to service routines, then the routines are displaced by eight address locations. Eight bytes of code is sufficient for most of the service routines (see the software example in this section).

The Four SIO1 Special Function Registers: The microcontroller interfaces to SIO1 via four special function registers. These four SFRs (S1ADR, S1DAT, S1CON, and S1STA) are described individually in the following sections.

P/N:PM0887

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REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

The Address Register, S1ADR: The CPU can read from and write to this 8-bit, directly addressable SFR. S1ADR is

not affected by the SIO1 hardware. The contents of this register are irrelevant when SIO1 is in a master mode. In the slave modes, the seven most significant bits must be loaded with the microcontroller’s own slave address, and, if the least significant bit is set, the general call address (00H) is recognized; otherwise it is ignored.

76543210

S1ADR (DBH)

The most significant bit corresponds to the first bit received from the I2C bus after a start condition. A logic 1 in S1ADR corresponds to a high level on the I2C bus, and a logic 0 corresponds to a low level on the bus.

The Data Register, S1DAT: S1DAT contains a byte of serial data to be transmitted or a byte which has just been received. The CPU can read from and write to this 8-bit, directly addressable SFR while it is not in the process of shifting a byte. This occurs when SIO1 is in a defined state and the serial interrupt flag is set. Data in S1DAT remains stable as long as SI is set. Data in S1DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and, after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT.

S1ADR (DAH)

SD7 - SD0:

Eight bits to be transmitted or just received. A logic 1 in S1DAT corresponds to a high level on the I2C bus, and a logic 0 corresponds to a low level on the bus. Serial data shifts through S1DAT from right to left. Figure 18 shows how data in S1DAT is serially transferred to and from the SDA line.

XXXXXXX GC

own slave address

76543210

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

shift direction

S1DAT and the ACK flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. The ACK flag is controlled by the SIO1 hardware and cannot be accessed by the CPU. Serial data is shifted through the ACK flag into S1DAT on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into S1DAT, the serial data is available in S1DAT, and the acknowledge bit is returned by the control logic during the ninth clock pulse. Serial data is shifted out from S1DAT via a buffer (BSD7) on the falling edges of clock pulses on the SCL line.

When the CPU writes to S1DAT, BSD7 is loaded with the content of S1DAT.7, which is the first bit to be transmitted to the SDA line (see Figure 19). After nine serial clock pulses, the eight bits in S1DAT will have been transmitted to the SDA line, and the acknowledge bit will be present in ACK. Note that the eight transmitted bits are shifted back into S1DAT.

P/N:PM0887

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REV. 1.6, MAR. 28, 2005

Internal Bus

PRELIMINARY

MX10E8050I / MX10E8050IA

SDA

BSD7 S1DAT ACK

SCL

Shift Pulses

Figure 18. Serial Input/Output Configuration

The Control Register, S1CON: The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are

affected by the SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I

C bus. The STO bit is also cleared when ENS1 = “0”.

76543210

S1CON (D8H)

CR2 ENS1 STA STO SI A A CR1 CR0

ENS1, THE SIO1 ENABLE BIT

ENS1 = “0”: When ENS1 is “0”, the SDA and SCL outputs are in a high impedance state. SDA and SCL input signals are ignored, SIO1 is in the “not addressed” slave state, and the STO bit in S1CON is forced to “0”. No other bits are affected. P1.6 and P1.7 may be used as open drain I/O ports.

ENS1 = “1”: When ENS1 is “1”, SIO1 is enabled. The P1.6 and P1.7 port latches must be set to logic 1.

ENS1 should not be used to temporarily release SIO1 from the I2C bus since, when ENS1 is reset, the I2C bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text).

In the following text, it is assumed that ENS1 = “1”.

STA, THE START FLAG

STA = “1”: When the STA bit is set to enter a master mode, the SIO1 hardware checks the status of the I2C bus and generates a START condition if the bus is free. If the bus is not free, then SIO1 waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal serial clock generator.

If STA is set while SIO1 is already in a master mode and one or more bytes are transmitted or received, SIO1 transmits a repeated START condition. STA may be set at any time. STA may also be set when SIO1 is an addressed slave. STA = “0”: When the STA bit is reset, no START condition or repeated START condition will be generated.

STO, THE STOP FLAG

STO = “1”: When the STO bit is set while SIO1 is in a master mode, a STOP condition is transmitted to the I2C bus. When the STOP condition is detected on the bus, the SIO1 hardware clears the STO flag. In a slave mode, the STO flag may be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C bus. However, the SIO1 hardware behaves as if a STOP condition has been received and switches to the defined “not addressed” slave receiver mode. The STO flag is automatically cleared by hardware.

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If the STA and STO bits are both set, the a STOP condition is transmitted to the I2C bus if SIO1 is in a master mode (in a slave mode, SIO1 generates an internal STOP condition which is not transmitted). SIO1 then transmits a START condition. STO = “0”: When the STO bit is reset, no STOP condition will be generated.

SI, THE SERIAL INTERRUPT FLAG

SI = “1”: When the SI flag is set, then, if the EA and ES1 (interrupt enable register) bits are also set, a serial interrupt is requested. SI is set by hardware when one of 25 of the 26 possible SIO1 states is entered. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available.

While SI is set, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A high level on the SCL line is unaffected by the serial interrupt flag. SI must be reset by software.

SI = “0”: When the SI flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the SCL line.

AA, THE ASSERT ACKNOWLEDGE FLAG

AA = “1”: If the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when:

- The “own slave address” has been received

- The general call address has been received while the general call bit (GC) in S1ADR is set

- A data byte has been received while SIO1 is in the master receiver mode

- A data byte has been received while SIO1 is in the addressed slave receiver mode

AA = “0”: if the AA flag is reset, a not acknowledge (high level to SDA) will be returned during the acknowledge clock pulse on SCL when:

- A data has been received while SIO1 is in the master receiver mode

- A data byte has been received while SIO1 is in the addressed slave receiver mode

When SIO1 is in the addressed slave transmitter mode, state C8H will be entered after the last serial is transmitted (see Figure 23). When SI is cleared, SIO1 leaves state C8H, enters the not addressed slave receiver mode, and the SDA line remains at a high level. In state C8H, the AA flag can be set again for future address recognition.

When SIO1 is in the not addressed slave mode, its own slave address and the general call address are ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, SIO1 can be temporarily released from the I2C bus while the bus status is monitored. While SIO1 is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag. If the AA flag is set when the part’s own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission.

CR0, CR1, AND CR2, THE CLOCK RATE BITS These three bits determine the serial clock frequency when SIO1 is in a master mode. The various serial rates are shown in Table 19.

A 12.5kHz bit rate may be used by devices that interface to the I2C bus via standard I/O port lines which are software driven and slow. 100kHz is usually the maximum bit rate and can be derived from a 16MHz, 12MHz, or a 6MHz oscillator. A variable bit rate (0.5kHz to 62.5kHz) may also be used if Timer 1 is not required for any other purpose while SIO1 is in a master mode.

The frequencies shown in Table 19 are unimportant when SIO1 is in a slave mode. In the slave modes, SIO1 will automatically synchronize with any clock frequency up to 100kHz.

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REV. 1.6, MAR. 28, 2005

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The Status Register, S1STA:

S1STA is an 8-bit read-only special function register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 26 possible status codes. When S1STA contains F8H, no relevant state information is available and no serial interrupt is requested. All other S1STA values correspond to defined SIO1 states. When each of these states is entered, a serial interrupt is requested (SI = “1”). A valid status code is present in S1STA one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software.

More Information on SIO1 Operating Modes: The four operating modes are:

- Master Transmitter

- Master Receiver

- Slave Receiver

- Slave Transmitter

Data transfers in each mode of operation are shown in Figures 20~28. These figures contain the following abbreviations:

Abbreviation Explanation

S Start condition SLA 7-bit slave address R Read bit (high level at SDA) W Write bit (low level at SDA) A Acknowledge bit (low level at SDA) A Not acknowledge bit (high level at SDA) Data 8-bit data byte P Stop condition

In Figures 20~28, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in the S1STA register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software.

When a serial interrupt routine is entered, the status code in S1STA is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Table 21~25.

Master Transmitter Mode:

In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 20). Before the master transmitter mode can be entered, S1CON must be initialized as follows:

76543210

S1CON (D8H)

CR0, CR1, and CR2 define the serial bit rate. ENS1 must be set to logic 1 to enable SIO1. If the AA bit is reset, SIO1 will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. In other words, if AA is reset, SIO0 cannot enter a slave mode. STA, STO, and SI must be reset.

The master transmitter mode may now be entered by setting the STA bit using the SETB instruction. The SIO1 logic will now test the I2C bus and generate a start condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (S1STA) will be 08H. This status code must be used to vector to an interrupt service routine that loads S1DAT with the slave address and the data direction bit (SLA+W). The SI bit in S1CON must then be reset before the serial transfer can continue.

P/N:PM0887

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CR2 ENS1 STA STO SI A A CR1 CR0

bit rate

1000x

bit rate

REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are possible. There are 18H, 20H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 21. After a repeated start condition (state 10H). SIO1 may switch to the master receiver mode by loading S1DAT with SLA+R).

SDA

SCL

Shift ACK & S1DAT

ACK

Shift BSD7

BSD7

Loaded by the CPU

(1) Valid data in S1DAT (2) Shifting data in S1DAT and ACK (3) High level on SDA

D7 D6 D5 D4 D3 D2 D1 D0 A

Shift In

(2) (2) (2) (2) (2) (2) (2) (2) A

(2) (2) (2) (2) (2) (2) (2) (2) (1)(1)S1DAT

Shift Out

D7 D6 D5 D4 D3 D2 D1 D0 (3)

Figure 19. Shift-in and Shift-out Timing

Table 20 : Serial Clock Rates

BIT FREQUENCY (kHz) AT f

CR2 CR1 CR0 6MHz 12MHz 16MHz f

OSC

DIVIDED BY

OSC

0 0 0 23 47 63 256 0 0 1 27 54 71 224 0 1 0 31 63 83 192 0 1 1 37 75 100 160 1 0 0 6.25 12.5 17 960 1 0 1 50 100 - 120 1 1 0 100 - - 60 1 1 1 0.25<62.5 0.5<62.5 0.67<56 96x(256-reload value Timer1)

(Reload value range:0-254 in mode2)

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REV. 1.6, MAR. 28, 2005

PRELIMINARY

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Successful Transmission to a Slave Receiver

Next Transfer Started with a Repeated Start Condition

Not Acknowledge Received after the Slave Address

Not Acknowledge Received after a Data Byte

Arbitration Lost in Slave Address or Data Byte

S SLA WA AData P

08H

18H

A P

20H

A or A

Other MST Continues

28H

S SLA W

10H

A P

30H

A or A

Other MST Continues

To MST/REC Mode Entry = MR

Arbitration Lost and Addressed as Slave

From Master to Slave

From Slave to Master

Data

Any Number of Data Bytes and Their Associated Acknowledge Bits

This Number (Contained in S1STA) Corresponds to a Defined State of the I

Figure 20. Format and States in the Master Transmitter Mode

38H

Other MST

Continues

68H 78H 80H

C Bus. See Table 21.

38H

To Corresponding States in Slave Mode

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MX10E8050I / MX10E8050IA

Data

Successful Reception from a Slave Transmitter

Next Transfer Started with a Repeated Start Condition

Not Acknowledge Received after the Slave Address

Arbitration Lost in Slave Address or Acknowledge Bit

Arbitration Lost and Addressed as Slave

S SLA DataR A Data P

08H

40H

A P

48H

A or A

38H

Other MST Continues

50H

58H

38H

S SLA R

10H

Other MST

Continues

To MST/TRX Mode Entry = MT

P/N:PM0887

To Corresponding States in Slave Mode

From Master to Slave

From Slave to Master

Data

This Number (Contained in S1STA) Corresponds to a Defined State of the I

Any Number of Data Bytes and Their Associated Acknowledge Bits

68H 78H 80H

C Bus. See Table 22.

Figure 21. Format and States in the Master Receiver Mode

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REV. 1.6, MAR. 28, 2005

Reception of the Own Slave Address and One or More Data Bytes All Are Acknowledged.

PRELIMINARY

MX10E8050I / MX10E8050IA

S SLA WA AData P or S

A SLAData

Last Data Byte Received Is Not Acknowledged

Arbitration Lost as MST and Addressed as Slave

Reception of the General Call Address and One or More Data Bytes

Last Data Byte Is Not Acknowledged

Arbitration Lost as MST and Addressed as Slave by General Call

General

Call

60H

70H

68H

80H

Data P or S

90H

Data

80H A0H

P or S

88H

90H A0H

P or S

98H

P/N:PM0887

78H

From Master to Slave

From Slave to Master

Data

Any Number of Data Bytes and Their Associated Acknowledge Bits

This Number (Contained in S1STA) Corresponds to a Defined State of the I

C Bus. See Table 23.

Figure 22. Format and States in the Slave Receiver Mode

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REV. 1.6, MAR. 28, 2005

Reception of the Own Slave Address and Transmission of One or More Data Bytes

PRELIMINARY

MX10E8050I / MX10E8050IA

S SLA R A Data P or S

ADataA

C0H

C8H

All "1"sA

P or S

From Master to Slave

From Slave to Master

Data

Any Number of Data Bytes and Their Associated Acknowledge Bits

This Number (Contained in S1STA) Corresponds to a Defined State of the I

A8H

B0H

B8H

Arbitration Loast as MST and Addressed as Slave

Last Data Byte Transmitted. Switched to Not Addressed Slave (AA Bit in S1CON = "0"

C Bus. See Table 24.

Figure 23. Format and States of the Slave Transmitter Mode

Master Receiver Mode:

In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 21). The transfer is initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service routine must load S1DAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in S1CON must then be cleared before the serial transfer can continue.

When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are possible. These are 40H, 48H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 22. ENS1, CR1, and CR0 are not affected by the serial transfer and are not referred to in Table 22. After a repeated start condition (state 10H), SIO1 may switch to the master transmitter mode by loading S1DAT with SLA+W.

Slave Receiver Mode:

In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 22). To initiate the slave receiver mode, S1ADR and S1CON must be loaded as follows:

76543210

S1ADR (DBH)

XXXXXXX GC

own slave address

The upper 7 bits are the address to which SIO1 will respond when addressed by a master. If the LSB (GC) is set, SIO1 will respond to the general call address (00H); otherwise it ignores the general call address.

76543210

S1CON (D8H)

CR2 ENS1 STA STO S I AA CR1 CR0

X10001XX

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REV. 1.6, MAR. 28, 2005

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CR0, CR1, and CR2 do not affect SIO1 in the slave mode. ENS1 must be set to logic 1 to enable SIO1. The AA bit must be set to enable SIO1 to acknowledge its own slave address or the general call address. STA, STO, and SI must be reset.

When S1ADR and S1CON have been initialized, SIO1 waits until it is addressed by its own slave address followed by the data direction bit which must be “0” (W) for SIO1 to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (I) is set and a valid status code can be read from S1STA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 23. The slave receiver mode may also be entered if arbitration is lost while SIO1 is in the master mode (see status 68H and 78H).

If the AA bit is reset during a transfer, SIO1 will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, SIO1 does not respond to its own slave address or a general call address. However, the I2C bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO1 from the I2C bus.

P/N:PM0887

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REV. 1.6, MAR. 28, 2005

Table 21 : Master Transmitter Mode

PRELIMINARY

MX10E8050I / MX10E8050IA

STATUS

CODE

(S1STA) SIO1 HARDWARE

08H A START condition has

10H A repeated START

18H SLA+W has been

20H SLA+W has been

STATUS OF THE

C BUS AND

been transmitted

condition has been transmitted

transmitted; ACK has been received

transmitted; NOT ACK has been received

APPLICATION SOFTWARE RESPONSE

TO/FROM S1DAT

Load SLA+W X 0 0 X SLA+W will be transmitted;

Load SLA+W or Load SLA+R

Load data byte or no S1DAT action or

no S1DAT action or no S1DAT action

Load data byte or no S1DAT action or

no S1DAT action or no S1DAT action

TO S1CON

STA STO SI AA

0 1

NEXT ACTION TAKEN BY SIO1 HARDWARE

ACK bit will be received

XXAs above

SLA+W will be transmitted; SIO1 will be switched to MST/REC mode

Data byte will be transmitted; ACK bit will be received

Repeated START will be transmitted;

STOP condition will be transmitted; STO flag will be reset

STOP condition followed by a STAR T condition will be transmitted; STO flag will be reset

Data byte will be transmitted; ACK bit will be received

Repeated START will be transmitted;

STOP condition will be transmitted; STO flag will be reset

STOP condition followed by a STAR T condition will be transmitted; STO flag will be reset

28H Data byte in S1DAT has

been transmitted; ACK has been received

30H Data byte in S1DAT has

been transmitted; NOT ACK has been received

38H Arbitration lost in

SLA+R/W or Data bytes

Load data byte or no S1DAT action or

no S1DAT action or no S1DAT action

Load data byte or no S1DAT action or

no S1DAT action or no S1DAT action

No S1DAT action or No S1DAT action

Data byte will be transmitted;

0 1

ACK bit will be received

Repeated START will be transmitted;

STOP condition will be transmitted; STO flag will be reset

STOP condition followed by a STAR T condition will be transmitted; STO flag will be reset

Data byte will be transmitted; ACK bit will be received

Repeated START will be transmitted;

STOP condition will be transmitted; STO flag will be reset

STOP condition followed by a STAR T condition will be transmitted; STO flag will be reset

XXI2C bus will be released;

not addressed slave will be entered A START condition will be transmitted when the bus becomes free

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MX10E8050I / MX10E8050IA

Table 22 : Master Receiver Mode

STATUS STATUS OF THE APPLICATION SOFTWARE RESPONSE

CODE I2C BUS AND TO/FROM S1DAT TO S1CON NEXT ACTION TAKEN BY SIO1 HARDWARE

(S1STA) SIO1 HARDWARE STA STO SI AA

08H A START condition has

been transmitted

Load SLA+R X 0 0 X SLA+R will be transmitted;

ACK bit will be received

10H A repeated START

condition has been transmitted

38H Arbitration lost in

NOT ACK bit

40H SLA+R has been

transmitted; ACK has been received

48H SLA+R has been

transmitted; NOT ACK has been received

50H Data byte has been

received; ACK has been returned

58H Data byte has been

received; NOT ACK has been returned

Load SLA+R or Load SLA+W

No S1DAT action or No S1DAT action

No S1DAT action or no S1DAT action

No S1DAT action or no S1DAT action or no S1DAT action

Read data byte or read data byte

Read data byte or read data byte or read data byte

XXAs above

0 0

0 0 0

0 0

0 0 0

SLA+W will be transmitted; SIO1 will be switched to MST/TRX mode

XXI2C bus will be released;

SIO1 will enter a slave mode A START condition will be transmitted when the bus becomes free

01Data byte will be received;

NOT ACK bit will be returned Data byte will be received; ACK bit will be returned

Repeated START condition will be transmitted

STOP condition will be transmitted; STO flag will be reset

STOP condition followed by a STAR T condition will be transmitted; STO flag will be reset

01Data byte will be received;

NOT ACK bit will be returned Data byte will be received; ACK bit will be returned

Repeated START condition will be transmitted

STOP condition will be transmitted; STO flag will be reset

STOP condition followed by a STAR T condition will be transmitted; STO flag will be reset

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REV. 1.6, MAR. 28, 2005

PRELIMINARY

MX10E8050I / MX10E8050IA

Table 23 : Slave Receiver Mode

STATUS STATUS OF THE APPLICATION SOFTWARE RESPONSE

CODE I2C BUS AND TO/FROM S1DAT TO S1CON NEXT ACTION TAKEN BY SIO1 HARDWARE

(S1STA) SIO1 HARDWARE STA STO SI AA

60H Own SLA+W has

68H Arbitration lost in

70H General call address

78H Arbitration lost in

80H Previously addressed

88H Previously addressed

90H Previously addressed

98H Previously addressed

been received; ACK has been returned

SLA+R/W Own SLA+W has been received, ACK returned

(00H) has been received; ACK has been returned

SLA+R/W General call address has been received, ACK has been returned

with own SLV address; DATA has been received; ACK has been returned

with own SLA; DATA byte has been received; NOT ACK has been returned

with General Call; DATA byte has been received; ACK has been returned

with General Call; DATA byte has been received; NOT ACK has been returned

as master;

No S1DAT action or no S1DAT action

Read data byte or read data byte

Read data byte or read data byte or

read data byte or

read data byte

Read data byte or read data byte

Read data byte or read data byte or

read data byte or

read data byte

01Data byte will be received and NOT ACK will be

returned Data byte will be received and ACK will be returned

01Data byte will be received and NOT ACK will be

returned Data byte will be received and ACK will be returned

01Data byte will be received and NOT ACK will be

returned Data byte will be received and ACK will be returned

01Data byte will be received and NOT ACK will be

returned Data byte will be received and ACK will be returned

01Data byte will be received and NOT ACK will be

returned Data byte will be received and ACK will be returned

Switched to not addressed SLV mode; no recognition of own SLA or General call address

Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1

Switched to not addressed SLV mode; no recognition of own SLA or General call address. A STAR T condition will be transmitted when the bus becomes free

Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A STAR T condition will be transmitted when the bus becomes free.

01Data byte will be received and NOT ACK will be

returned Data byte will be received and ACK will be returned

Switched to not addressed SLV mode; no recognition of own SLA or General call address

Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1

Switched to not addressed SLV mode; no recognition of own SLA or General call address. A STAR T condition will be transmitted when the bus becomes free

Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A STAR T condition will be transmitted when the bus becomes free.

P/N:PM0887

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MX10E8050I / MX10E8050IA

Table 23 : Slave Receiver Mode (Continued)

STATUS STATUS OF THE APPLICATION SOFTWARE RESPONSE

CODE I2C BUS AND TO/FROM S1DAT TO S1CON NEXT ACTION TAKEN BY SIO1 HARDWARE

(S1STA) SIO1 HARDWARE STA STO SI AA

A0H A STOP condition or

repeated STAR T condition has been received while still addressed as SLV/REC or SLV/TRX

Table 24 : Slave Transmitter Mode

STATUS STATUS OF THE APPLICATION SOFTWARE RESPONSE

CODE I2C BUS AND TO/FROM S1DAT TO S1CON NEXT ACTION TAKEN BY SIO1 HARDWARE

(S1STA) SIO1 HARDWARE STA STO SI AA

A8H Own SLA+R has been

B0H Arbitration lost in

B8H Data byte in S1DAT

C0H Data byte in S1DAT

C8H Last data byte in

received; ACK has been returned

SLA+R/W Own SLA+R has been received, ACK has been returned

has been transmitted; ACK has been received

has been transmitted; NOT ACK has been received

S1DAT has been transmitted (AA = 0); ACK has been received

as master;

No STDAT action or No STDAT action or

No STDAT action or

No STDAT action

Load data byte or load data byte

No S1DAT action or no S1DAT action or

no S1DAT action or

no S1DAT action

No S1DAT action or no S1DAT action or

no S1DAT action or

no S1DAT action

Switched to not addressed SLV mode; no

recognition of own SLA or General call address

Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1

Switched to not addressed SLV mode; no recognition of own SLA or General call address. A STAR T condition will be transmitted when the bus becomes free

Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A STAR T condition will be transmitted when the bus becomes free.

01Last data byte will be transmitted and

ACK bit will be received Data byte will be transmitted; ACK will be received

01Last data byte will be transmitted and ACK bit will

be received Data byte will be transmitted; ACK bit will be received

01Last data byte will be transmitted and

ACK bit will be received Data byte will be transmitted; ACK bit will be received