MX COM Inc MX929BDS, MX929BDW, MX929BP Datasheet

DATA BULLETIN

MX929B

4-Level FSK Modem Data Pump

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

PRELIMINARY INFORMATION

Features Applications

 4-Level Root Raised Cosine FSK

Modulation

 Half Duplex, 4800 to 19.2kbps  Increase Channel Bit Rate/Hz  Full Data Packet Framing  Impulse and NRZ Signal Modes  Enhanced Performance in Noisy

Conditions

 Error Detection and Error Correction  Low Power 3.3V/5.0V Operation

 RD-LAP Systems  RCR STD-47 Systems  Two Way Paging Systems  Mobile Data Systems  Wireless Telemetry  DataTAC Terminals  Portable Wireless Data

Equipment

MODEM

DAT A

PUMP

MX929B

ANALOG TX

DA TA AND

CONTROL BUS

ANALOG RX

RADIO

DISCRIMINATOR

MODULATOR

SYSTEM

APPLICATION

PROCESSING

HOST Cµ

The MX929B is a low voltage CMOS device containing all of the baseband signal processing and Medium Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data Modem. It interfaces with the modem host C and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data over a wireless link.

The MX929B assembles application data received from the host C, adds forward error correction (FEC) and error detection (CRC) information, and interleaves the result for burst-error protection. After automatically adding symbol and frame sync codewords, the data packet is converted into filtered 4-level analog signals for modulating the radio transmitter.

In receive mode, the MX929B performs the reverse function using the analog signals from the receiver discriminator. After error correction and removal of the packet overhead, the recovered application data is supplied to the host C. CRC detected residual uncorrected data errors will be flagged. Readout of the SNR value during receipt of a packet is also provided.

The MX929B uses data block sizes and FEC/CRC Algorithms that are compatible with RD-LAP and RCR STD-47 over-air-standards. The device is programmable to operate at standard bit rates from a wide range of Xtal/clock frequencies.

The MX929B may be used with a 3.0V to 5.5V power supply and is available in the following package styles: 24-pin SSOP (MX929BDS), 24-pin SOIC (MX929BDW), and 24-pin PDIP (MX929BP).

4-Level FSK Modem Data Pump 2 MX929B PRELIMINARY INFORMATION

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CONTENTS

Section Page

1 Block Diagram................................................................................................................6

2 Signal List.......................................................................................................................7

3 External Components....................................................................................................8

4 General Description.......................................................................................................9

4.1 Description of Blocks.............................................................................................................. 9

4.1.1 Data Bus Buffers....................................................................................................................... 9

4.1.2 Address and R/W Decode ........................................................................................................9

4.1.3 Status and Data Quality Registers............................................................................................9

4.1.4 Command, Mode, and Control Registers..................................................................................9

4.1.5 Data Buffer................................................................................................................................ 9

4.1.6 CRC Generator/Checker...........................................................................................................9

4.1.7 FEC Generator/Checker...........................................................................................................9

4.1.8 Interleave/De-Interleave Buffer...............................................................................................10

4.1.9 Frame Sync Detect.................................................................................................................10

4.1.10 Rx Input Amp..........................................................................................................................10

4.1.11 RRC Low Pass Filter...............................................................................................................10

4.1.12 Tx Output Buffer......................................................................................................................11

4.1.13 Rx Level/Clock Extraction.......................................................................................................12

4.1.14 Clock Oscillator and Dividers..................................................................................................12

4.2 Modem - µC Interaction........................................................................................................ 12

4.3 Binary to Symbol Translation................................................................................................ 13

4.4 Frame Structure.................................................................................................................... 14

4.5 The Programmer's View....................................................................................................... 15

4.5.1 Data Block Buffer....................................................................................................................15

4.5.2 Command Register.................................................................................................................16

4.5.2.1 Command Register B7: AQSC - Acquire Symbol Clock............................................16

4.5.2.2 Command Register B6: AQLEV - Acquire Receive Signal Levels.............................16

4.5.2.3 Command Register B5: CRC....................................................................................16

4.5.2.4 Command Register B4: TXIMP - Tx Level/Impulse Shape........................................16

4.5.2.5 Command Register B3 - Reserved............................................................................ 16

4.5.2.6 Command Register B2, B1, B0: TASK.......................................................................17

4.5.2.7 NULL: No effect .........................................................................................................18

4.5.2.8 SFP: Search for Frame Preamble..............................................................................18

4.5.2.9 RHB: Read Header Block..........................................................................................19

4.5.2.10 RILB: Read 'Intermediate' or 'Last' Block...................................................................19

4.5.2.11 SFS: Search for Frame Sync.....................................................................................19

4.5.2.12 R4S: Read 4 Symbols................................................................................................19

4.5.2.13 RSID: Read Station ID...............................................................................................19

4.5.2.14 T24S: Transmit 24 Symbols.......................................................................................20

4.5.2.15 THB: Transmit Header Block .....................................................................................20

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4.5.2.16 TIB: Transmit Intermediate Block...............................................................................20

4.5.2.17 TLB: Transmit Last Block...........................................................................................20

4.5.2.18 T4S: Transmit 4 Symbols...........................................................................................20

4.5.2.19 TSID: Transmit Station ID..........................................................................................21

4.5.2.20 RESET: Stop any current action................................................................................21

4.5.2.21 Task Timing ...............................................................................................................21

4.5.2.22 RRC Filter Delay........................................................................................................22

4.5.3 Control Register......................................................................................................................23

4.5.3.1 Control Register B7, B6: CKDIV - Clock Division Ratio.............................................23

4.5.3.2 Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches.........23

4.5.3.3 Control Register B3, B2: LEVRES - Level Measurement Modes...............................23

4.5.3.4 Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes ..............24

4.5.4 Mode Register.........................................................................................................................25

4.5.4.1 Mode Register B7: IRQEN -

IRQ

Output Enable......................................................25

4.5.4.2 Mode Register B6: INVSYM - Invert Symbols............................................................25

4.5.4.3 Mode Register B5:

RXTX/ - Tx/Rx Mode..................................................................25

4.5.4.4 Mode Register B4: RXEYE - Show Rx Eye ...............................................................25

4.5.4.5 Mode Register B3: PSAVE - Powersave ...................................................................26

4.5.4.6 Mode Register B2: SSIEN - 'S' Symbol IRQ Enable..................................................26

4.5.4.7 Mode Register B1, B0: SSYM - 'S' Symbol To Be Transmitted................................26

4.5.5 Status Register .......................................................................................................................26

4.5.5.1 Status Register B7: IRQ - Interrupt Request..............................................................27

4.5.5.2 Status Register B6: BFREE - Data Block Buffer Free................................................27

4.5.5.3 Status Register B5: IBEMPTY - Interleave Buffer Empty...........................................27

4.5.5.4 Status Register B4: DIBOVF - De-Interleave Buffer Overflow...................................27

4.5.5.5 Status Register B3: CRCERR - CRC Checksum Error..............................................27

4.5.5.6 Status Register B2: 'S' Symbol Ready.......................................................................28

4.5.5.7 Status Register B1, B0: SVAL - Received 'S' Symbol Value ..................................... 28

4.5.6 Data Quality Register..............................................................................................................28

4.6 CRC, FEC and Interleaving.................................................................................................. 29

4.6.1 Cyclic Redundancy Codes......................................................................................................29

4.6.1.1 CRC0.........................................................................................................................29

4.6.1.2 CRC1.........................................................................................................................29

4.6.1.3 CRC2.........................................................................................................................29

4.6.1.4 Forward Error Correction...........................................................................................29

4.6.1.5 Interleaving ................................................................................................................29

4.7 Transmitted Symbol Shape.................................................................................................. 30

5 Application ...................................................................................................................32

5.1 Transmit Frame Example..................................................................................................... 32

5.2 Receive Frame Example...................................................................................................... 35

5.3 Clock Extraction and Level Measurement Systems............................................................. 38

5.3.1 Supported Types of Systems..................................................................................................38

5.3.2 Clock and Level Acquisition Procedures with RF Carrier Detect............................................38

5.3.3 Clock and Level Acquisition Procedure without RF Carrier Detect.........................................38

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5.3.4 Automatic Acquisition Functions.............................................................................................39

5.4 AC Coupling ......................................................................................................................... 39

5.5 Radio Performance............................................................................................................... 40

5.6 Received Signal Quality Monitor .......................................................................................... 42

6 Performance Specification..........................................................................................43

6.1 Electrical Performance ......................................................................................................... 43

6.1.1 Absolute Maximum Ratings....................................................................................................43

6.1.2 Operating Limits......................................................................................................................43

6.1.3 Operating Characteristics .......................................................................................................44

6.1.4 Operating Characteristics Notes:............................................................................................45

6.1.5 Timing.....................................................................................................................................45

6.1.6 Typical Bit Error Rate..............................................................................................................47

6.2 Packaging............................................................................................................................. 48

MX-COM, Inc. Reserves the right to change specifications at any time and without notice

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Figures

Figure Page

Figure 1: Block Diagram ....................................................................................................................................6

Figure 2: Recommended External Components................................................................................................8

Figure 3: Typical Modem • C connections.........................................................................................................9

Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode.................................................10

Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5)....................11

Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5)............11

Figure 7: Over-Air Signal Format.....................................................................................................................14

Figure 8: Alternative Frame Structures............................................................................................................15

Figure 9: Transmit Task Overlapping...............................................................................................................17

Figure 10: Receive Task Overlapping..............................................................................................................18

Figure 11: Transmit Task Timing Diagram.......................................................................................................22

Figure 12: Receive Task Timing Diagram........................................................................................................22

Figure 13: RRC Low Pass Filter Delay............................................................................................................22

Figure 14: Ideal 'RXEYE' Signal ......................................................................................................................26

Figure 15: Typical Data Quality Reading vs S/N..............................................................................................28

Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 1...........................................................30

Figure 17: Tx Signal Eye TXIMP = 0................................................................................................................30

Figure 18: Tx Signal Eye TXIMP = 1................................................................................................................31

Figure 19: Transmit Frame Example Flowchart, Main Program......................................................................33

Figure 20: Tx Interrupt Service Routine...........................................................................................................34

Figure 21: Receive Frame Example Flowchart, Main Program........................................................................36

Figure 22: Rx Interrupt Service routine............................................................................................................37

Figure 23: Acquisition Sequence Timing .........................................................................................................38

Figure 24: Effect of AC Coupling on BER (without FEC).................................................................................39

Figure 25: Decay Time - AC Coupling.............................................................................................................40

Figure 26: Typical Connections between Radio and MX929B.........................................................................41

Figure 27: Received Signal Quality Monitor Flowchart....................................................................................42

Figure 28: C Parallel Interface Timings .........................................................................................................46

Figure 29: Typical Bit Error Rate With and Without FEC.................................................................................47

Figure 30: 24-pin SOIC Mechanical Outline:

Order as part no. MX929BDW

.................................................48

Figure 31: 24-pin SSOP Mechanical Outline:

Order as part no. MX929BDS

.................................................48

Figure 32: 24-pin PDIP Mechanical Outline:

Order as part no. MX929BP

.....................................................49

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1 Block Diagram

BIAS

XTAL /

CLOCK

TXOUT

RXIN

Rx Input Amp

Tx Output Buffer

DOC1 DOC2

D1 D2 D3 D4 D5 D6 D7

Tx Symbols Rx Symbols

Tx Rx

RxEye

BIAS

µCONTROLLER

INTERFACE

DATA

BUS

BUFFERS

ADDRESS

AND

R/W

DECODE

CRC

GENERATOR/

CHECKER

FRAME

SYNC DETECT

Rx LEVEL/CLOCK

EXTRACTION

FEC

ENCODER/

DECODER

INTERLEAVE/

DE-INTERLEAVE

CONTROL

MODE

COMMAND

DA T A

BUFFER

STATUS

DATA

QUALITY

RRC

LOW P ASS

FIL TER

CLOCK

OSCILLATOR

AND

DIVIDERS

RXAMPOUT

XTAL

IRQ

BIAS

Figure 1: Block Diagram

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2 Signal List

Pin No. Signal Type Description

IRQ

output

A 'wire-ORable' output for connection to the host C's Interrupt Request input. When active, this output has a low impedance pull down to V

. It has high impedance when inactive.

2D7BUS 3D6BUS 4D5BUS 5 D4 BUS Pins 2-9 (D7-D0) are 8-bit, bi-directional, 3-state 6D3BUS



C interface data lines 7D2BUS 8D1BUS 9D0BUS

input Read. An active low logic level input used to control the reading

of data from the modem into the host C.

input Write. An active low logic level input used to control the writing

of data into the modem from the host C.

12 V

power Negative supply (ground).

input Chip Select. An active low logic level input to the modem used

to enable a data read or write operation. 14 A0 input Logic level modem register select input 15 A1 input Logic level modem register select input 16

XTAL

output Output of the on-chip oscillator.

17 XTAL/CLOCK input Input to the on-chip oscillator, for an external Xtal circuit or

clock. 18 DOC 2 output Connection to the Rx level measurement circuitry. Should be

capacitive coupled to V

19 DOC 1 output Connection to the Rx level measurement circuitry. Should be

capacitive coupled to V

20 TXOUT output Tx signal output from the modem. 21 V

BIAS

output A bias line for the internal circuitry held at VDD /2. This pin must

be bypassed to V

by a capacitor mounted close to the device

pins. 22 RXIN input Input to the Rx input amplifier. 23 RXAMPOUT output Output of the Rx input amplifier. 24 V

power Positive supply. Levels and voltages are dependent upon this

supply. This pin should be bypassed to V

by a capacitor

mounted close to the device pins.

Note: Internal protection diodes are connected from each signal pin to VDD and VSS.

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3 External Components

DOC1 DOC2

BIAS

RXIN

From Rx FM Discriminator

To Tx F requency Modulator

RXAMPOUT

µCONTROLLER INTERFACE

MX929B

TXOUT

D7 D6 D5 D4 D3 D2 D1 D0

XTAL/CLOCK

2 3 4

5 6

9 10 11 12

24 23 22 21 20 19 18 17

IRQ

XTAL

Figure 2: Recommended External Components

Component Notes Value Tolerance Component Notes Value Tolerance

R1 1



20%

C4 3



20%

100k



C5 4





20%

C6 5



20%

100k



C7 5



20%

C1 0.1 µF



20%

C8 4



C2 0.1 µF



20%

C3 3



20%

X1 2

Recommended External Component Notes:

1. See Section 4.1.10 Rx Input Amp.

2. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of V

, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain

crystal oscillator design assistance, consult your crystal manufacturer.

3. The values used for C3 and C4 should be suitable for the frequency of the crystal X1. As a guide, values (including stray capacitance) of 33pF at 1MHz falling to 18pF at 10MHz will generally prove suitable. Crystal frequency tolerances are discussed in Section 4.5.3.4 Control Register B1, B0: PLLBW - PhaseLocked Loop Bandwidth Modes.

4. Values C5 and C8 should be equal to 750,000 / symbol rate, e.g.

Symbol Rate C5 and C8

2400 symbols/second 330pF 4800 symbols/second 150pF 9600 symbols/second 82pF

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5. Values C6 and C7 should be equal to 50,000 / symbol rate, e.g.

Symbol Rate C6 and C7

2400 symbols/second

0.022F

4800 symbols/second

0.01F

9600 symbols/second 4700pF

4 General Description

4.1 Description of Blocks

4.1.1 Data Bus Buffers

Eight bi-directional 3-state logic level buffers between the modem's internal registers and the host µC's data bus lines.

4.1.2 Address and R/W Decode

This block controls the transfer of data bytes between the µC and the modem's internal registers according to the state of the Write and Read Enable inputs (

WR and RD ), the Chip Select input (CS), and the Register

Address inputs A0 and A1. The Data Bus Buffers, Address, and R/W Decode blocks provide a byte-wide parallel µC interface, which can

be memory-mapped, as shown in Figure 3.

Address Bus

µC

MODEM

Address Decode

Circuit

Data Bus

IRQ

D0:7 A0:1

IRQ pull up

resistor

D0:7

IRQ

A2:7

A0:1

Figure 3: Typical Modem C connections

4.1.3 Status and Data Quality Registers

Two 8-bit registers which the µC can read to determine the status of the modem and received data quality.

4.1.4 Command, Mode, and Control Registers

The values written by the µC to these 8-bit registers control the operation of the modem.

4.1.5 Data Buffer

A 12-byte buffer used to hold, receive or transmit data to or from the µC.

4.1.6 CRC Generator/Checker

A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum bits, which may be included in the transmitted data blocks so the receive modem can detect transmission errors.

4.1.7 FEC Generator/Checker

In transmit mode, this circuit adds Forward Error Correction bits to the transmitted data, resulting in the conversion of binary data to 4-level symbols. In receive mode, this circuit translates received 4-level symbols to binary data, using the FEC information to correct a large proportion of transmission errors.

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4.1.8 Interleave/De-Interleave Buffer

This circuit interleaves data symbols within a block before transmission and de-interleaves the received data so that the FEC system is best able to handle short noise bursts or fades.

4.1.9 Frame Sync Detect

This circuit, which is only active in receive mode, is used to look for the 24-symbol Frame Synchronization pattern that is transmitted to mark the start of every frame.

4.1.10 Rx Input Amp

This amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the external components R1 and R2. The value of R1 should be calculated to give 0.2 x V

volts

P-P

at the RXAMPOUT pin for a received '...+3 +3 -3 -3 ...' sequence.

A capacitor may be placed in series with R1 if ac coupling of the received signal is desired (see Section

5.4AC Coupling), otherwise the DC level of the received signal should be adjusted so that the signal at the

modem's RXAMPOUT pin is centered around V

BIAS

(VDD/2).

4.1.11 RRC Low Pass Filter

This filter, which is used in both transmit and receive modes, is a linear-phase lowpass filter with a 'Root Raised Cosine' frequency response defined by:

rate symbol

= T 0.2, = b Where

b+1

> f for 0 = )f(H

b+1

< f <

b-1

for

)2-Tf(

sin

=)f(H

b-1

< f < 0 for 1 = )f(H



This frequency response is illustrated in Figure 5 and Figure 6. In transmit mode, the 4-level symbols are passed through this filter to eliminate the high frequency

components which would otherwise cause interference into adjacent radio channels. The input applied to the RRC Tx filter may be impulses or full-width symbols depending on the setting of the Command Register TXIMP bit. See Section 4.7 Transmitted Symbol Shape.

Data

Encoding

binary -

symbol

Transmit

filter

Frequency

modulator

Bit

pairs

MX929B

Symbols

-1

-3

Modem

Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode

In receive mode, the filter is used to reject HF noise and to equalize the received signal to a form suitable for extracting the 4-level symbols. The equalization characteristics are determined by the setting of the Command Register TXIMP bit.

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-5

-10

-15

-20

-25

-30 0 0.1 0.2 0.3 0.4 0.5

Frequency / Bit Rate

Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5)

-5

-10

-15

-20

-25

-30 0 0.2 0.4 0.6 0.8 1.0

Frequency / Symbol Rate

Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5)

4.1.12 Tx Output Buffer

This is a unity gain amplifier used in the transmit mode to buffer the output of the Tx low pass filter. In receive mode, the input of this buffer is connected to V

BIAS

, unless the RXEYE bit of the Control Register is '1', in

which case it is connected to the received signal. When changing from Rx to Tx mode, the input to this buffer will be connected to V

BIAS

for 8 symbol times while the RRC filter settles.

Note: The RC low pass filter formed by the external components R4 and C5 between the TXOUT pin and the

input to the radio's frequency modulator forms an important part of the transmit signal filtering. These components may form part of any DC level-shifting and gain adjustment circuitry. The value used for C5 should take into account stray circuit capacitance, and its ground connection should be positioned to give maximum attenuation of high frequency noise into the modulator.

The signal at the TXOUT pin is centered around V

BIAS

. It is approximately 0.2 x V

volts

P-P

for a

continuous ’+3 +3 -3 -3...' pattern with TXIMP = 0. For typical Tx Eye Diagrams refer to Section

4.7Transmitted Symbol Shape, Figure 17 and Figure 18. For typical Rx Eye Diagrams refer to Section

4.5.4.4 Mode Register B4: RXEYE - Show Rx Eye, Figure 14. A capacitor may be placed in series with the input to the frequency modulator if AC coupling is desired.

See Section 5.4AC Coupling.

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4.1.13 Rx Level/Clock Extraction

These circuits, which operate only in receive mode, derive a symbol rate clock from the received signal and measure the received signal amplitude and DC offset. This information is then used to extract the received 4level symbols and also to provide an input to the received Data Quality measuring circuit. The external capacitors C6 and C7 form part of the received signal level measuring circuit.

The capacitors C6 and C7 are driven from a very high impedance source so any measurement of the voltages on the DOC pins must be made via high input impedance (MOS input) voltage followers to avoid disturbance of the level measurement circuits.

Further details of the level and clock extraction functions are given in Section 5.3 Clock Extraction and Level Measurement Systems.

4.1.14 Clock Oscillator and Dividers

These circuits derive the transmit symbol rate (and the nominal receive symbol rate) by frequency division of a reference frequency which may be generated by the on-chip Xtal oscillator or applied from an external source.

Note: If the on-chip Xtal oscillator is to be used, then the external components X1, C3, C4, and R3 are

required. If an external clock source is to be used, then it should be connected to the XTAL/CLOCK input pin, the

XTAL pin should be left unconnected, and X1, C3, C4, and R3 should not be installed.

4.2 Modem - µC Interaction

In general, data is transmitted over-air in the form of messages, or 'Frames', consisting of a 'Frame Preamble' followed by one or more formatted data blocks. The Frame Preamble includes a Frame Synchronization pattern designed to allow the receiving modem to identify the start of a frame. The following data blocks are constructed from the 'raw' data using a combination of CRC (Cyclic Redundancy Checksum) generation, Forward Error Correction coding, and Interleaving. Details of the message formats handled by the modem are provided in Section 4.3 Binary to Symbol Translation, Figure 7, and Figure 8.

To reduce the processing load on the associated C, the MX929B modem has been designed to perform as much of the computationally intensive work involved in Frame formatting and de-formatting and (when in receive mode) searching for and synchronizing onto the Frame Preamble. In normal operation, the modem will only require servicing by the µC once per received or transmitted block.

Therefore, to transmit a block, the controlling µC needs only to load the unformatted 'raw' binary data into the modem's Data Block Buffer, then instruct the modem to format and transmit that data. The modem will then calculate and add the CRC bits as required, encode the result as 4-level symbols (with Forward Error Correction coding), and interleave the symbols before transmission.

In receive mode, the modem can be instructed to assemble a block's worth of received symbols, de-interleave the symbols, translate them to binary, perform Forward Error Correction, and check the resulting CRC before placing the received binary data into the Data Block Buffer for the µC to read.

The modem can also handle the transmission and reception of unformatted data using the T4S, T24S, and R4S tasks as described in Sections 4.3 Binary to Symbol Translation and 4.5.2Command Register. These tasks are normally used for the transmission of Symbol and Frame Synchronization sequences. These tasks may also be used for the transmission and reception of special test patterns or special data formats. In such a case, care should be taken to ensure that the transmitted TXOUT signal contains enough level and timing information for the receiving modem's level and clock extraction circuits to function correctly. See Section

5.3Clock Extraction and Level Measurement Systems.

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4.3 Binary to Symbol Translation

Although the over-air signal, and therefore the signals at the modem TXOUT and RXIN pins, consists of 4level symbols, the raw data passing between the modem and the µC is in binary form. Translation between binary data and the 4-level symbols is done in one of two ways, depending on the task being performed.

1. Direct way: (simplest form) - converts between two binary bits and a single symbol, such as the 'S' Channel Status symbol.

SYMBOL MSB LSB

+3 1 1 +1 1 0

-1 0 0

-3 0 1

Accordingly, 1 byte = 4 symbols = 8 bits, and one byte translates to four symbols for the T4S and R4S tasks and six bytes translates to twenty-four symbols for the T24S task described in Section 4.5.2 Command Register.

MSB LSB

Bits:

76543210

Symbols:

abcd

sent first sent last

2. FEC way: (more complicated) - essentially translates groups of 3 binary bits to pairs of 4-level symbols using a Forward Error Correcting coding scheme for the block oriented tasks THB, TIB, TLB, RHB, RILB, and RSID described in Section 4.5.2 Command Register.

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4.4 Frame Structure

The MX929B Frame Structure as used in a RD-LAP system is illustrated in Figure 7, and consists of a Frame Preamble (comprising a 24-symbol Frame Synchronization pattern and Station ID block), followed by a 'Header Block', one or more 'Intermediate Blocks', and a 'Last Block'. Channel Status (S) symbols are included at regular intervals. The first Frame of any transmission is preceded by a Symbol Synchronization pattern.

354670

35467

FEC TRELLIS CODING / DECODING

(ERROR CORRECTION)

INTERLEAVING / DE-INTERLEAVING

345 29303132

64 65

Byte 11

22 Symbols 22 Symbols22 Symbols

SSS

Byte 0

Byte 1

'000'

777

Symbol

Sync

Frame

Sync

Station

'Header'

Block

24 24 1 22 1

Frame

Preamble

Intermediate Blocks

Packet (1 to 44 Blocks)

69 6969

'Last' Block

Frame

Sync

Next Frame

(Optional)

Frame

-1 +1 -1 +1 -1 +3 -3 +3 -3 -1 +1 -3 +3 +3 -1 +1-3-3 +1 +3 -1 -3 +1 +3

+3 +3 -3 -3 +3 +3 -3 -3 +3 +3 -3 -3 +3 +3 -3 -3 -3+3+3 -3 -3 -3 +3 +3

S: Channel Status Symbol: +3 = Busy, +1 = Unknown, -1 = Unknown, -3 = Idle

Frame Sync:

Symbol Sync:

sent first last

Over-air Signal

(symbols)

Block:

35467

Last BlockIntermediate BlocksHeader Block

4 5 6 7 8

9 10 11

1 2 3

µC binary data stored in MX929B data block memory configured as header, intermediate, or last block by MX929B task being executed.

Byte

FEC TRELLIS CODING / DECODING

(ERROR CORRECTION)

8910

Byte 0 Byte 1 Byte 2 Byte 3

Data Bytes

(0-8)

-------------Pad Bytes

(0-8)

Address

Control

(10 bytes)

Data Bytes

(12 bytes)

CRC2

(4 bytes)

CRC1

(2 bytes)

707070

'000'

211

tri-bits

4-level

symbols

35467

1 2 3

Station ID

lsbmsb

CRC0

System ID Domain ID

Base ID

Byte

Figure 7: Over-Air Signal Format

4-Level FSK Modem Data Pump 15 MX929B PRELIMINARY INFORMATION

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The 'Header' block is self-contained and includes its own checksum (CRC1). It would normally carry information such as the address of the calling and called parties, the number of following blocks in the frame (if any), and miscellaneous control information. The number of following blocks (if any) is required to allow the Rx device software to expect the Last Block and interpret it as a Last Block rather than an Intermediate Block. There is no other indicator to differentiate a Last Block and an Intermediate Block.

The 'Intermediate' block(s) contain only data, the checksum at the end of the 'Last' block (CRC2) also checks the data in any preceding 'Intermediate' blocks.

Proprietary systems that do not use RD-LAP format may use the block structures provided by the MX929B to build alternative frame formats more suited to the particular application. Some examples are shown in Figure 7.

SYMBOL

SYNC

SYMBOL

SYNC

SYMBOL

SYNC

FRAME

SYNC

FRAME

SYNC

FRAME

SYNC

'LAST'

BLOCK

'HEADER' BLOCKS

'INTERMEDIATE' BLOCKS

Figure 8: Alternative Frame Structures

The MX929B performs the entire block formatting and de-formatting required to convert data between the C binary form and the Over-Air form as shown in Figure 7.

4.5 The Programmer's View

To the programmer, the modem appears as 4 write only 8-bit registers, shadowed by 3 read only registers. The individual registers are selected by the A0 and A1 chip inputs:

A1 A0 Write to Modem Read from Modem

0 0 Data Buffer Data Buffer 0 1 Command Register Status Register 1 0 Control Register Data Quality Register 1 1 Mode Register not used

Note: There is a minimum time allowance between accesses of the modem's registers, see Section

6.1.5 Timing.

4.5.1 Data Block Buffer

This is a 12-byte read/write buffer used to transfer data (as opposed to command, status, mode, and data quality or control information) between the modem and the host µC.

To the µC, the Data Block Buffer appears as a single 8-bit register. The modem ensures that sequential µC reads or writes to the buffer are routed to the correct locations within the buffer.

The µC should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'. The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in receive

mode, the modem will function correctly even if the received data is not read from the Data Buffer by the C.

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