x Detects 12 or 16kHz SPM Frequencies
x ‘Controlled’ (PC) & ‘Fixed’ Signal Sensitivity
Modes
x Selectable Tone Follower or Packet Mode
Outputs
x High Speech-Band Rejection Properties
x ‘Output Enable’ Multiplexing Facility
XTAL/CLOCK
XTAL
Ch1AMPOUT
Ch1 AMP IN (-)
Ch1 AMP IN (+)
PRESET LEVEL
CHIP SELECT
SERIAL
DATA
SERIAL
CLOCK
SYSTEM SELECT
Ch2 AM PIN (-)
Ch2 AMP IN (+)
Ch2AMPOUT
+
Ch 1
INPUT
AMPLIFIER
SERIAL
INPUT
LOGIC
Ch 2
INPUT
AMPLIFIER
+
XTAL/CLOCK
GENERATOR
Ch 1
BANDPASS
FILTER
GAIN
ADJUST
LEVEL/
SYSTEM
SETTING
GAIN
ADJUST
Ch 2
BANDPASS
FILTER
COMPARATOR
THRESHOLD
COMPARATOR
THRESHOLD
CLOCK OUTCLOCK IN
BUFFER
Ch 1
COMPARATOR
+
INTERNAL
12kHz/16kHz
SYSTEM
INTERNAL
+
-
Ch 2
COMPARATOR
x Call Charge Applications on PABX Line
Cards
x Remote Telephone Applications
CLOCK
DIVIDERS
12kHz/16kHz
PULSE
GENERATOR
AND
DIVIDER
CHANNEL 1
CHANNEL 2
PULSE
GENERATOR
AND
DIVIDER
SYSTEM
PULSE
MEASUREMENT
LOGIC
PULSE
MEASUREMENT
LOGIC
TONE FOLLOWER
PULSE
LENGTH
LOGIC
PULSE
LENGTH
LOGIC
TONE FOLLOWER
PRELIMINARY INFORMATION
V
DD
V
OUTPUT
SELECT
CIRCUITS
OUTPUT
SELECT
CIRCUITS
V
Ch 1
OUTPUT
OUTPUT
ENABLE
OUTPUT
SELECT
Ch 2
OUTPUT
BIAS
SS
MODE
MODE
INTERNAL
CLOCKS
PACKET
MODE
12kHz/16kHz
SYSTEM
PACKET
MODE
The MX641 is a low-power, system-selectable Dual Subscriber Pulse Metering (SPM) Detector designed to indicate the
presence, on a telephone line, of either 12kHz or 16kHz telephone call-charge frequencies. It is designed for PBX and
PABX line-card and remote telephone installations. Under PProcessor control via a common serial interface, each
channel of the MX641 will detect call-charge pulses from a telephone line and provide a digital output for recording, billing
or security purposes. A common set of external components and a stable 3.579545MHz Xtal/clock input ensures that the
MX641 adheres accurately to most national “Must and Must-Not” decode band-edges and threshold levels. For nonPProcessor systems a preset sensitivity/system input allows external channel level and system setting
The digital output is pin-selectable to one of three modes:
(1) Tone Follower mode: logic level for the period of a correct decode.
(2) Packet mode: respond/de-respond after a cumulative period of tone or notone in a fixed (intrinsic hardwired period
that is not user controlled) period.
(3) High-impedance output: for device multiplexing.
The MX641 requires a 5V supply and is available in the following packages: 24-pin SOIC (MX641DW) and 24-pin PDIP
(MX641P).
2. Signal List......................................................................................................................................... 4
5.1.2 Protection Against High Voltages .....................................................................................................................12
6.1.1 Absolute Maximum Ratings..............................................................................................................................13
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Dual SPM Detector4MX641 PRELIMINARY INFORMATION
2. Signal List
Pin No.NameTypeDescription
1Xtal/ClockinputThe input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in
conjunction with the Xtal output; circuit components are on-chip. When using a
Xtal input, the Clock Out pin should be connected directly to the Clock In pin. If
a clock pulse input is used at the Clock In pin, this (Xtal/Clock) pin must be
connected directly to V
frequency distribution.
2
XTAL
outputThe output of the on-chip clock oscillator inverter.
3Clock OutoutputThe buffered output of the on-chip-clock oscillator inverter. If a Xtal input is
used, this output should be connected directly to the Clock In pin. This output
can support up to 3 additional MX641 ICs. See Figure 3 for details of clock
frequency distribution.
4Clock IninputThe 3.579545 clock pulse input to the internal clock dividers. If an externally
generated clock pulse input is used, the Xtal/Clock input pin should be
connected to V
5
Output Enable
inputFor multi-chip output multiplexing; controls the state of both Ch1 and Ch2
DD
.
outputs. When this input is placed high (logic '1') both outputs are set to a high
impedance. When placed low (logic '0') both outputs are enabled.
6Ch 2 OutputoutputThe digital output of the Channel 2 SPM detector when enabled. The format of
the signal at this pin, in common with Ch 1, is selectable to either
'Tone Follower' or 'Packet' mode via the Output Select input.
7Ch 1 OutputoutputThe digital output of the Channel 1 SPM detector when enabled. The format of
the signal at this pin, in common with Ch 2, is selectable to either
'Tone Follower' or 'Packet' mode via the Output Select input.
8V
BIAS
powerThe output of the on-chip analog bias circuitry. Held internally at VDD/2, this
pin should be decoupled to V
9Ch 1 Amp OutoutputThe output of the Channel 1 Input Amplifier. See Figure 2 and Figure 8.
10Ch 1 Amp In (-):inputThe negative input to the Channel 1 Input Amplifier. See Figure 2 and Figure
8.
11Ch 1 Amp In (+):inputThe positive input to the Channel 1 Input Amplifier. See Figure 2 and Figure 8.
12V
SS
powerNegative supply (GND).
13N/CNo internal connection; leave open circuit.
14Ch 2 Amp In (+):inputThe positive input to the Channel 2 Input Amplifier. See Figure 2 and Figure 8.
15Ch 2 Amp In (-):inputThe negative input to the Channel 2 Input Amplifier. See Figure 2 and Figure
8.
16Ch 2 Amp OutoutputThe output of the Channel 2 Input Amplifier. See Figure 2 and Figure 8.
17Output SelectinputA logic input to set the Channel 1 and Channel 2 output modes. When high
(logic '1'), the outputs are in the Tone Follower mode; when low (logic '0'), the
outputs are in the Packet mode.
18Preset LevelinputA logic input to set the sensitivity mode of the MX641. When high (logic '1'),
both channels are in the Fixed Sensitivity mode. The external components
govern the input sensitivity; the System Select input selects 12kHz or 16kHz
operation. When low (logic '0'), both channels are in the Controlled Sensitivity
mode. Device sensitivities and system selection are via the Chip Select/Serial
Data/Serial Clock inputs. This input has an internal pullup resistor on chip
(Fixed Sensitivity Mode).
19
Chip Select
inputThe Chip Select input for use in data loading when using the MX641 in the
Controlled Sensitivity mode (see Figure 9). The device is selected when this
input is set low (logic '0'). When the MX641 is in the Fixed Sensitivity mode
this input should be connected to either V
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
Dual SPM Detector5MX641 PRELIMINARY INFORMATION
Pin No.NameTypeDescription
20Serial ClockinputThe Serial Clock input for use in data loading when using the MX641 in the
Controlled Sensitivity mode (see Figure 9). Data is loaded to the MX641 on
this clock's rising edge. When the MX641 is in the Fixed Sensitivity mode this
input should be connected to either V
or VDD.
SS
21Serial DatainputThe Serial Data input for use in data loading when using the MX641 in the
Controlled Sensitivity mode (see Figure 9 and Table 4). When the device is in
the Fixed Sensitivity mode this input should be connected to either V
or VDD.
SS
22System SelectinputIn the Fixed Sensitivity mode this pin selects the system frequency. High (logic
‘1’) = 12kHz; Low (logic ‘0’) = 16kHz. In the Controlled Sensitivity mode this pin
is inactive and may be left unconnected. This pin has an internal pullup
resistor on chip.
23N/CNo internal connection; leave open circuit.
24V
DD
powerPositive supply rail; a single, stable power supply is required. Critical levels
and voltages within the MX641 are dependent upon this supply. This pin