Delta Modulation CODEC 4 MX629
1998 MX-COM, Inc. www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480190.001
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.
2 Signal List
J/P LH Name Signal Description
1 1 Xtal/Clock input Input to the clock oscillator inverter. A 1.024MHz Xtal input or
externally derived clock is injected here. See Clock Mode pins and
Figure 2.
2 N/C No Connection
23
Xtal
output The 1.024 MHz output of the clock oscillator inverter.
3 4 N/C No Connection
4 5 Encoder Data
Clock
input/
output
A logic I/O port. External encode clock input or internal data clock
output. Clock frequency is dependent upon Clock Mode 1, 2 inputs
and Xtal frequency (see Clock Mode pins).
5 6 Encoder Output output The encoder digital output. This is a three-state output whose
condition is set by the Data Enable and
Powersave inputs. See
Table 2.
67
Idle Force Encoder
When this pin is at a logical “0” the encoder is forced to an idle
state and the encoder digital output is 0101, a perfect idle pattern.
When this pin is a logical “1” the encoder encodes as normal.
Internal 1M pullup.
7 8 Data Enable input Data is made available at the encoder output pin by control of this
input. See Encoder Output pin. Internal 1 M pullup.
8 9 N/C No Connection
910V
BIAS
Normally at VDD/2 bias, this pin should be externally decoupled by
capacitor C4. Internally pulled to V
SS
when “
Powersave
” is a
logical “0”.
10 11 Encoder Input input The analog signal input. Internally biased at VDD/2, this input
requires an external coupling capacitor. The source impedance
should be less than 100. Output channel noise levels will
improve with an even lower source impedance. See Figure 2.
11 12 V
SS
power Negative Supply
12 13 N/C No Connection
13 14 Decoder Output output The recovered analog signal is output at this pin. It is the buffered
output of a lowpass filter and requires external components.
During “Powersave” this output is open circuit.
14 15 N/C No Connection
15 16
Powersave
A logic “0” at this pin puts most parts of the codec into a quiescent
non-operational state. When at a logical “1”, the codec operates
normally. Internal 1 M pullup.
17 N/C No Connection
16 18
Idle Force Decoder
A logic “0” at this pin gates a 0101... pattern internally to the
decoder so that the Decoder Output goes to V
DD
/2. When this pin
is a logical “1” the decoder operates as normal. Internal 1M
pullup.
17 19 Decoder Input
The received digital signal input. Internal 1 M pullup.
18 20 Decoder Data
Clock
input/
output
A logic I/O port. External decode clock input or internal data clock
output, dependent upon clock mode 1,2 inputs. See Clock Mode
pins.
19 21 Algorithm A logic “1” at this pin sets this device for a 3-bit companding
algorithm. A logical “0” sets a 4-bit companding algorithm. Internal
1 M pullup.