Bell 202 Compatible Modem 4 MX614 PRELIMINARY INFORMATION
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2. Signal List
Pin No. Signal Description
P, DW TN Name Type
11
XTAL
output Output of the on-chip Xtal oscillator inverter.
2 2 XTAL/CLOCK input Input to the on-chip Xtal oscillator inverter.
3 5 M0 input A logic level input for setting the mode of the device. See
section 4.2
4 6 M1 input A logic level input for setting the mode of the device. See
section 4.2
5 7 RXIN input Input to the Rx input amplifier.
6 8 RXAMPOUT output Output of the Rx input amplifier
7 11 TXOUT output Output of the FSK generator.
812 VSSPower Negative supply (ground).
913 V
BIAS
output Internally generated bias voltage, held at VDD/2 when the
device is not in 'Zero-Power' mode. Should be bypassed to
V
SS
by a capacitor mounted close to the device pins.
10 14 RXEQ input A logic level input for enabling/disabling the equalizer in the
receive filter. See section 4.4
11 17 TXD input A logic level input for either the raw input to the FSK
Modulator or data to be re-timed depending on the state of
the M0, M1 and CLK inputs. See section 4.9
12 18 CLK input A logic level input which may be used to clock data bits in or
out of the FSK Data Retiming block.
13 19 RXD output A logic level output carrying either the raw output of the FSK
Demodulator or re-timed characters depending on the state of
the M0, M1 and CLK inputs. See section 4.8
14 20 DET output A logic level output of the on-chip Energy Detect circuit.
15 23
RDY
output "Ready for data transfer" output of the on-chip data retiming
circuit. This open-drain active low output may be used as an
Interrupt Request/Wake-up input to the associated µC. An
external pull-up resistor should be connected between this
output and V
DD
.
16 24 V
DD
Power Positive supply. Levels and thresholds within the device are
proportional to this voltage. Should be bypassed to V
SS
by a
capacitor mounted close to the device pins.
3, 4,
9, 10,
15,
16,
21,
22
N/C No internal connection