MX COM Inc MX609DW, MX609J, MX609LH, MX609P Datasheet
DATA BULLETIN
MX609
1998 MX-COM, Inc. www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480069.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.
PCN/PCS DELTA
MODULATION CODEC
Features Applications
Single Chip full Duplex CVSD CODEC
On-chip Input and Output Filters
Programmable Sampling Clocks
3- or 4-bit Companding Algorithm
Powersave Capabilities
Low Power, 5.0V Operation
Digital PCN/PCS Systems
Digital Cordless Phones
Digital Delay Lines
Digital Voice Storage
Multiplexers, Switches, and
Phones
Time Domain Scramblers
ENCODER DATA CLOCK
DECODER DATA CLOCK
MOD
DEMOD
CLOCK RATE
GENERAT ORS
CLOCK MODE
LOGIC
f
f
f
f
f
1
1
3
0
2
ENCODER INPUT
ENCODER FORCE IDLE*
DECODER FORCE IDLE*
DATA ENABLE
V
DD
V
SS
POWERSAVE
V
BIAS
XTAL/CLOCK
MODE 1
MODE 2
XTAL
ALGORITHM
DECODER INPUT
SAMPLING RATE
CONTROL
3or4BIT
DECODER
OUTPUT
ENCODER
OUTPUT
*Available on J,P & LH
package styles only
The MX609 is a Continuously Variable Slope Delta Modulation (CVSD) Codec designed for use in cordless
telephones. The device is suitable for applications in delta multiplexers, switches and phones. Encoder input
and decoder output switched capacitor filters are incorporated on-chip.
Sampling clock rates can be programmed to 16, 32 or 64K bits/second from an internal clock generator or
externally injected in the 8 to 64K bits/second range. The internal clocks are derived from an on-chip
reference oscillator driven by an externally connected crystal. The sampling clock frequency is output for the
synchronization of external circuits.
The encoder has an enable function for use in multiplexer applications. When not enabled the encoder output
remains in a high-impedance “tri-state” mode.
Companding circuits may be operated with an externally selectable 3- or 4-bit algorithm. The device may be
put in standby mode when Powersave is selected.
The MX609 operates with a supply voltage of 5.0V and is available in the following packages: 24-pin PLCC
(MX609LH), 16-pin SOIC (MX609DW), 22-pin CERDIP (MX609J), and 22-pin PDIP (MX609P).
PCN/PCS Delta Modulation CODEC 2 MX609
1998 MX-COM, Inc. www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 204800069.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.
CONTENTS
Section Page
1 Block Diagram................................................................................................................3
2 Signal List.......................................................................................................................4
3 External Components....................................................................................................6
4 General Description.......................................................................................................6
5 Application .....................................................................................................................7
5.1 CODEC Integration.............................................................................................................. 7
5.2 CODEC Performance.......................................................................................................... 7
6 Performance Specification............................................................................................9
6.1 Electrical Performance ........................................................................................................ 9
6.1.1 Absolute Maximum Ratings....................................................................................................9
6.1.2 Operating Limits.....................................................................................................................9
6.1.3 Operating Characteristics.....................................................................................................10
6.1.4 TIMING.................................................................................................................................11
6.2 Packaging.......................................................................................................................... 12
MX-COM, Inc. reserves the right to change specifications at any time and without notice.
PCN/PCS Delta Modulation CODEC 3 MX609
1998 MX-COM, Inc. www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 204800069.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.
1 Block Diagram
ENCODER DATA CLOCK
DECODER DATA CLOCK
MOD
DEMOD
CLOCK RATE
GENERATORS
CLOCK MODE
LOGIC
f
f
f
f
f
1
1
3
0
2
ENCODER INPUT
ENCODER FORCE IDLE*
DECODER FORCE IDLE*
DATA ENABLE
V
DD
V
SS
POWERSAVE
V
BIAS
XT AL/CLOCK
MODE 1
MODE 2
XT AL
ALGORITHM
DECODER INPUT
SAMPLING RATE
CONTROL
3or4BIT
DECODER
OUTPUT
ENCODER
OUTPUT
*Available on J,P & LH
package styles only
Figure 1: Block Diagram
PCN/PCS Delta Modulation CODEC 4 MX609
1998 MX-COM, Inc. www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 204800069.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.
2 Signal List
1 1 1 Xtal/Clock input Input to the clock oscillator inverter. A 1.024MHz Xtal input
or externally derived clock is injected here. See Clock Mode
pins and figure 3.
2 N/C
232
Xtal
output The 1.024 MHz output of the clock oscillator inverter.
3 4 N/C No Connection
4 5 3 Encoder Data
Clock
input/
output
A logic I/O port. External encode clock input or internal data
clock output. Clock frequency is dependent upon Clock
Mode 1, 2 inputs and Xtal frequency (see Clock Mode pins).
5 6 4 Encoder Output output The encoder digital output. This is a three-state output
whose condition is set by the Data Enable and
Powersave
inputs. See Table 2:
67-
Idle Force Encoder
When this pin is at a logical “0” the encoder is forced to an
idle state and the encoder digital output is 0101, a perfect
idle pattern. When this pin is a logical “1” the encoder
encodes as normal. Internal 1M pullup.
7 8 5 Data Enable input Data is made available at the encoder output pin by control
of this input. See Encoder Output pin. Internal 1 M pullup.
8 9 N/C No Connection
9 10 6 Bias Normally at VDD/2 bias, this pin should be externally
decoupled by capacitor C4. Internally pulled to V
SS
when
“
Powersave ” is a logical “0”.
10 11 7 Encoder Input input The analog signal input. Internally biased at VDD/2, this
input requires an external coupling capacitor. The source
impedance should be less than 100. Output channel noise
levels will improve with an even lower source impedance.
See Figure 3.
11 12 8 V
SS
power Negative Supply
12 13 - N/C No Connection
13 14 9 Decoder Output output The recovered analog signal is output at this pin. It is the
buffered output of a lowpass filter and requires external
components. During “Powersave” this output is open circuit.
14 15 N/C No Connection
15 16 10
Powersave
A logic “0” at this pin puts most parts of the codec into a
quiescent non-operational state. When at a logical “1”, the
codec operates normally. Internal 1 M pullup.
17 No Connection
16 18 -
Idle Force Decoder
A logic “0” at this pin gates a 0101... pattern internally to the
decoder so that the Decoder Output goes to V
DD
/2. When
this pin is a logical “1” the decoder operates as normal.
Internal 1M pullup.
17 19 11 Decoder Input
The received digital signal input. Internal 1 M pullup.
18 20 12 Decoder Data
Clock
input/
output
A logic I/O port. External decode clock input or internal data
clock output, dependent upon clock mode 1,2 inputs. See
Clock Mode pins.
19 21 13 Algorithm A logic “1” at this pin sets this device for a 3-bit companding
algorithm. A logical “0” sets a 4-bit companding algorithm.
Internal 1 M pullup.
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