MX COM Inc CMX639P6, CMX639E2, CMX639D4 Datasheet

COMMUNICATION ICs

DATA BULLETIN

CMX639

Consumer / Commercial

CVSD Digital Voice CODEC

2000 MX-COM, Inc. www.mxcom.com Tel: [phone] 744 5050 Fax: [phone] Doc. # 20480209.006

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.

PRELIMINARY INFORMATION

Features Applications

•

Single Chip Full Duplex CVSD CODEC

Integrated Input and Output Filters
Robust Coding for Wireless Links
Programmable Sampling Clocks
3 and 4 bit Companding Algorithms

•

Low Power / Small Size for Portable
Devices

1.9mA/2.75mA typ. @ 3V/5V

3.0V to 5.5V Operation
Powersave Mode

•

Consumer & Business Handheld
Devices

•

Digital Voice Appliances

Spread Spectrum Wireless
Cordless Phones
Voice Recording & Storage
Delay Lines

•

Time Domain Scramblers

•

Multiplexers and Switches

COMPAND
REGISTER

PRINCIPAL

INTEGRATOR

SYLLABIC

INTEGRATOR

PULSE

GENERATOR

X

IDLE

CHANNEL

STABILIZER

+

ENCODE

TIMING

ENCODE DATA OUT

COMPAND
REGISTER

PULSE

GENERATOR

SYLLABIC

INTEGRATOR

X

PRINCIPAL

INTEGRATOR

DECODE

TIMING

COMMON

TIMING

DECODE

DATA IN

ENCODE

ANALOG IN

DECODE
ANALOG

OUT

-

+

-

The CMX639 is a Continuously Variable Slope Delta Modulation (CVSD) full duplex CODEC for use in
consumer and commercial digital voice communication systems. With its robust and selectable coding
algorithms, low cost, very low power, and small size, the CMX639 is ideal for use in a wide variety of
consumer and business digital voice applications. Its completely integrated CODEC simplifies design and
eliminates the costs, complexity and risk of external filters and software algorithms.

8kbps to 128kbps data/sampling clock rates are supported both via external clock signals or internally
generated, programmable clocks. Internal data/sampling clocks are derived from an on-chip reference
oscillator that uses an external clock crystal. An internal data/sampling clock output signal is provided to
synchronize external circuits, if desired. Multiplexer applications are also well supported by the encoder
output’s tri-state enable feature.

The CMX639 operates from 3.0V to 5.5V and is available in the following packages: 24-pin TSSOP
(CMX639E2), 16-pin SOIC (CMX639D4) and 22-pin PDIP (CMX639P6).

Consumer/Commercial CVSD Digital Voice CODEC 2 CMX639 Preliminary Information

2000 MX-COM, Inc. www.mxcom.com Tel: [phone] 744 5050 Fax: [phone] Doc. # 20480209.006

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.

CONTENTS

Section Page

1 Block Diagram................................................................................................................3

2 Signal List.......................................................................................................................4

3 External Components....................................................................................................5

4 Application .....................................................................................................................6

4.1 CODEC Integration.............................................................................................................. 6

5 Performance Specification............................................................................................6

5.1 Electrical Performance ........................................................................................................ 6

5.1.1 Absolute Maximum Ratings....................................................................................................6

5.1.2 Operating Limits.....................................................................................................................6

5.1.3 Operating Characteristics.......................................................................................................7

5.1.4 Timing.....................................................................................................................................9

5.1.5 Typical Performance ............................................................................................................10

5.2 Packaging.......................................................................................................................... 11

MX-COM, Inc. reserves the right to change specifications at any time and without notice.

Consumer/Commercial CVSD Digital Voice CODEC 3 CMX639 Preliminary Information

2000 MX-COM, Inc. www.mxcom.com Tel: [phone] 744 5050 Fax: [phone] Doc. # 20480209.006

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.

1 Block Diagram

ENCODER DATA CLOCK
DECODER DATA CLOCK

MOD

DEMOD

CLOCK RATE

GENERATORS

CLOCK MODE

LOGIC

f

f

f

f

f

1

1

3

0

2

ENCODER INPUT

ENCODER FORCE IDLE*

DECODER FORCE IDLE*

DATA ENABLE

V

DD

V

SS

POWERSAVE

V

BIAS

XTAL/CLOCK

MODE 1
MODE 2

XTAL

ALGORITHM

DECODER INPUT

SAMPLING RATE

CONTROL

3or4BIT

DECODER
OUTPUT

ENCODER
OUTPUT

*Available on E2 & P6

package styles only

Figure 1: Block Diagram

Consumer/Commercial CVSD Digital Voice CODEC 4 CMX639 Preliminary Information

2000 MX-COM, Inc. www.mxcom.com Tel: [phone] 744 5050 Fax: [phone] Doc. # 20480209.006

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.

2 Signal List

P6

22-pin

PDIP

E2

24-pin

TSSOP

D4

16-pin

SOIC

Signal Name Type Description

1 1 1 Xtal/Clock input

Input to the clock oscillator inverter. A 1.024MHz Xtal input or
externally derived clock is injected here. See Table 3 and Figure 3.

2 N/C No Connection

2 3 2

Xtal

output The 1.024 MHz output of the clock oscillator inverter.

3 4 N/C No Connection

4 5 3

Encoder Data
Clock

input/

output

A logic I/O port. External encode clock input or internal data clock
output. Clock frequency is dependent upon Clock Mode 1, 2 inputs
and Xtal frequency (see Table 3). Note: No internal pull-up is
provided.

5 6 4 Encoder Output output

The encoder digital output. This is a three-state output whose
condition is set by the Data Enable and

Powersave

inputs. See

Table 2.

6 7

Not

present

Idle Force Encoder

input

When this pin is at a logical '0' the encoder is forced to an idle
state and the encoder digital output is 0101…, a perfect idle
pattern. When this pin is a logical '1' the encoder encodes as
normal. Internal 1MΩ pull-up.

7 8 5 Data Enable input

Data is made available at the encoder output pin by control of this
input. See Encoder Output pin. Internal 1 MΩ pull-up.

8 9 N/C No Connection

9 10 6 Bias

Normally at V

DD

/2 bias, this pin should be externally decoupled b y

capacitor C4. Internally pulled to V

SS

when Powersave is a logical

'0'.

10 11 7 Encoder Input input

The analog signal input. Internally biased at V

DD

/2, this input
requires an external coupling capacitor. The source impedance
driving the coupling capacitor should be less than 1kΩ. A lower
driving source impedance will reduce encoder output channel
noise levels. See Figure 2.

11 12 8 VSS power Negative Supply
12 13 N/C No Connection

13 14 9 Decoder Output output

The recovered analog signal is output at this pin. It is the buffered
output of a lowpass filter and requires external components. During
'Powersave' this output is open circuit.

14 15 N/C No Connection

15 16 10

Powersave

input

A logic '0' at this pin puts most parts of the codec into a quiescent
non-operational state. When at a logical '1', the codec operates
normally. Internal 1 MΩ pull-up.

17 N/C No Connection

16 18

Not

present

Idle Force Decoder

input

A logic '0' at this pin gates a 0101... pattern internally to the
decoder so that the Decoder Output goes to V

DD

/2. When this pin
is a logical '1' the decoder operates as normal. Internal 1MΩ pull­up.

17 19 11 Decoder Input input

The received digital signal input. Internal 1 MΩ pull-up.

18 20 12

Decoder Data
Clock

input/

output

A logic I/O port. External decode clock input or internal data clock
output, dependent upon Clock Mode 1 and 2 inputs. See Table 3.
Note: No internal pull-up is provided.

19 21 13 Algorithm input

A logic '1' at this pin sets this device for a 3-bit companding
algorithm. A logical '0' sets a 4-bit companding algorithm. Internal 1
MΩ pull-up.

20 22 14 Clock Mode 2 input

21 23 15 Clock Mode 1 input

Clock rates refer to f = 1024MHz Xtal/Clock input. During internal
operation the data clock frequencies are available at the ports for
external circuit synchronization. Independent or common data rate
inputs to Encode and Decode data clock ports may be employed in
the External Clocks mode. Internal 1MΩ pull-ups. See Table 3.

22 24 16 VDD power Positive Supply. A single 3.0V to 5.5V supply is required.

Table 1: Signal List