Low Voltage SPM Detector 4 CMX631A PRELIMINARY INFORMATION
© 1999 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480177.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
2 Signal List
Packages Signal
D5 D4/P3 Name Type
Description
1 1 Xtal/Clock input The input to the on-chip clock oscillator; for use with a
3.579545MHz Xtal in conjunction with the Xtal output; circuit
components are on-chip. When using a Xtal input, the Clock
Out pin should be connected directly to the Clock In pin. If a
clock pulse input is used at the Clock In pin, this (Xtal/Clock)
pin must be connected directly to V
DD
See Figure 2 and
Section 3.
42
XTAL
output The output of the on-chip clock oscillator inverter.
5 3 Clock Out output The buffered output of the on-chip-clock oscillator inverter. If a
Xtal input is used, this output should be connected directly to
the Clock In pin.
6 4 Clock In input The 3.579545MHz clock pulse input to the internal clock
dividers. If an externally generated clock pulse is used, the
Xtal/Clock input pin should be connected to V
DD
. Reference
Section 3.
87V
BIAS
power The output of the on-chip analog bias circuitry. Held internally
at V
DD
/2, this pin should be bypassed to VSS. See Figure 2.
12 8 V
SS
power Negative supply (GND).
13 9 Signal In + input The positive input to the input gain adjusting signal amplifier.
Reference Section 4.3 and 4.4.
17 10 Signal In - input The negative input to the input gain adjusting signal amplifier.
Reference Section 4.3 and 4.4.
18 11 Amp Out input The output of the input gain adjusting signal amplifier.
Reference Section 4.3 and 4.4.
19 13 Tone
Follower
Mode
output This output provides a logic 0 for the period of a detected tone
and a logic 1 for a NOTONE detection. See Section 4.1 and
Figure 3.
20 14 Packet Mode output This output provides a logic 0 for a detected tone and a logic 1
for NOTONE detection and will ignore a small fluctuation or
fade during the tone signal. See Section 4.2 and Figure 3.
21 15 System input This logic input selects the device operation to either 12kHz
(logic 1) or 16kHz (logic 0) SPM systems. This input has an
internal 1MΩ pull-up resistor (12kHz).
24 16 V
DD
power Positive supply. A single, stable power supply is required.
Critical levels and voltages within the CMX631A are dependent
upon this supply. This pin should be bypassed to V
SS
by a
capacitor mounted close to the pin. Note: If this device is line
powered, the resulting power supply must be stable. See
Section 5.1.1.
2, 3, 7,
9, 10,
11, 14,
15, 16,
22, 23
5,6,12 N/C No internal connection; leave open circuit.
Table 1: Signal List