1200/2400/4800bps MSK Modem 4 CMX469A PRELIMINARY INFORMATION
1999 MX-COM, Inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 Doc. # 20480191.002
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2. Signal List
Pin No. Signal
E2 P6 D3 Name Type
Description
1 1 1 Xtal/Clock input
The input to the on-chip inverter, for use with either a
1.008MHz or a 4.032MHz Xtal or external clock.
Clock frequency selection is by the “Clock Rate”
input pin. The selection of this frequency will affect
the operational Data Rate of this device. Refer to
Table 3.
As specified in the Performance Specifications, this
input signal should be actively clocked (either driven
from an external source or via an XTAL circuit).
222
XTAL
output Output of the on-chip inverter.
3 3 3 TX Sync Out output
A squarewave, produced on-chip, to synchronize the
input of logic data and transmission of the MSK
signal. See Figure 8 and Section 4.1.
5 5 4 TX Signal Out output
When the transmitter is enabled, this pin outputs the
(140-step pseudo sinewave) MSK signal. See
Figure 8. With the transmitter disabled, this output is
set to a high-impedance state.
7 6 5 TX Data In input Serial logic data to be transmitted is input to this pin.
876
ENABLE TX
input
A logic ‘0’ will enable the transmitter. See Figure 8.
A logic ‘1’ at this input will put the transmitter into
powersave while forcing “TX Sync Out” to a logic ‘1’
and “TX Signal Out” to a high-impedance state. This
pin is internally pulled to V
DD
.
9 8 7 Bandpass Out output
The output of the RX Bandpass Filter. This output
impedance is typically 10kΩ and may require
buffering prior to use.
10 9 8 RX Enable input
The control of the RX function. The control of other
outputs is provided in Table 2
11 10 9
V
BIAS
power
The output of the on-chip analog bias circuitry. Held
internally at V
DD
/2, this pin should be bypassed to
V
SS
by a capacitor (C2). See Figure 2 and RX
Enable notes. This bias voltage is maintained under
all powersave conditions.
12 11 10 V
SS
power Negative supply (GND).
13 12 11
Unclocked
Data Out
output
The recovered asynchronous serial data output from
the receiver.
14 13 12
Clocked
Data Out
output
The recovered synchronous serial data output from
the receiver. Data is latched out by the recovered
clock, available at the “RX Sync Out”. See Figure 9
and Figure 11.
15 14 13 Carrier Detect output
When an MSK signal is being received this output is
a logic ‘1’.
16 15 14 RX Signal In input
The MSK signal input for the receiver. This input
should be coupled via a capacitor, C3.
18 17 15 RX Sync Out output
A flywheel squarewave output. This clock will
synchronize to incoming RX MSK data.
See Figure 9 and Figure 11.