The CMX208 is an ISDN telephony protocol engine which implements the lower level ISDN interface and
communicates with the CMX605 and other standard devices to form a fully integrated ISDN chipset for voice
communications. The CMX208 puts all the main data processing elements in a single device. No ISDN
software has to be written and simple ‘Plug and Play’ design results. This reduces development time and
provides a highly cost-effective hardware solution. By using proven circuit designs, the designer can move
quickly from initial concept through design in to manufacture.
The CMX208 supports two voice ports over the ISDN Line, which can be used to provide ISDN telephony
services or POTS line interfaces, and has independent keypad-configuration of these services for each port.
The CMX208’s feature set and architecture allow most analog systems to be converted to an ISDN equivalent
with enhanced features.
The CMX208 is designed to work with the AMD 79C30 S/T bus interface, the Siemens PSB-21525 HDLC
formatter, the Motorola MC145480 PCM codec and the MX-COM CMX605 POTS interface circuit, and also
comes complete with embedded applications software. To support the CMX208, MX-COM can also provide
licensed reference designs on user request. A flexible Applications Program Interface (API) allows users to
customize the features and operation of their own design. The CMX208 is available in an 80-pin QFP
(CMX208S1) package.
1
The CMX208 is a data processor integrated circuit that supports the protocol layers 1, 2 and 3 of the ISDN protocol stack in accordance
with the specifications of CCITT (now ITU). These specifications, which are widely used around the world, might not be supported withi n
the U.S.
All trademarks and service marks are held by their respective companies
ISDN Dual Telephony Protocol Engine 4 CMX208 Advance Information
2. Signal List
S1 Package Signal
Pin No. Name Type
1 SCL output EEPROM - Serial Clock
2 SDA bi-directional EEPROM - Serial Data
3 ISDNRST output ISDN S-interface Chip Reset
4 N/C output Do not make any connection to this pin
5 N/C output Do not make any connection to this pin
6 N/C output Do not make any connection to this pin
7
8
RST
DV
DD1
input CMX208 Chip Reset (active low)
power
The digital positive supply rail. Levels and voltages are
dependent upon this supply. This pin should be decoupled to
DV
by a capacitor
SS
9
XTAL
output The output of the on-chip Xtal oscillator inverter
10 XTAL input The input to the oscillator inverter from the Xtal circuit
DV
11
SS1
power The digital negative supply rail (ground)
12 LED1 output POTS Port 1 Off-Hook Indicator (HK1)
13 LED2 output POTS Port 2 Off-Hook Indicator (HK2)
14 N/C output Do not make any connection to this pin
15 LED4 output POTS Port 2 Call Connected Indicator (CN2)
16 N/C output Do not make any connection to this pin
17 N/C output Do not make any connection to this pin
18 N/C output Do not make any connection to this pin
19 LED8 output ISDN Line Activated Indicator (AR)
20
24 A19 output Memory and Peripheral Address Bus
25 A18 output Memory and Peripheral Address Bus
26 A17 output Memory and Peripheral Address Bus
27 A16 output Memory and Peripheral Address Bus
28 A15 output Memory and Peripheral Address Bus
29 A14 output Memory and Peripheral Address Bus
30 A13 output Memory and Peripheral Address Bus
31 A12 output Memory and Peripheral Address Bus
32 A11 output Memory and Peripheral Address Bus
33 A10 output Memory and Peripheral Address Bus
34 A9 output Memory and Peripheral Address Bus
35 A8 output Memory and Peripheral Address Bus
36 A/D7 bi-directional Memory and Peripheral Address and Data Bus
37 A/D6 bi-directional Memory and Peripheral Address and Data Bus
38 A/D5 bi-directional Memory and Peripheral Address and Data Bus
All trademarks and service marks are held by their respective companies
ISDN Dual Telephony Protocol Engine 5 CMX208 Advance Information
S1 Package Signal
Description
Pin No. Name Type
39 A/D4 bi-directional Memory and Peripheral Address and Data Bus
40 A/D3 bi-directional Memory and Peripheral Address and Data Bus
41 A/D2 bi-directional Memory and Peripheral Address and Data Bus
42 A/D1 bi-directional Memory and Peripheral Address and Data Bus
43 A/D0 bi-directional Memory and Peripheral Address and Data Bus
44 ASTB output Address/Data Bus Strobe (data bus selected if low)
DV
45
46 ~ input
SS0
power The digital negative supply rail (ground)
For manufacturer's use only. Connect to DV
directly
SS
47 PSBRES output HDLC Chip Reset
48 RING2 output POTS Port 2 Ringing Generator (low when not ringing)
49
2RING
output POTS Port 2 Ringing Generator (high when not ringing)
50 API-RXD input API/RS232 Port Rx Data (inactive = high)
51 API-TXD output API/RS232 Port Tx Data (high when inactive)
52 CLIP2 output
POTS Port 2 Line Voltage Adjustment (low when sending FSK
to a Caller Display unit. If low, it makes the SLIC present a
high impedance to the POTS line)
The digital positive supply rail. Levels and voltages are
dependent upon this supply. This pin should be decoupled to
DV
by a capacitor
SS
56 RING1 output POTS Port 1 Ringing Generator (low when not ringing)
57
1RING
58 CLIP1 output
output POTS Port 1 Ringing Generator (high when not ringing)
POTS Port 1 Line Voltage Adjustment (low when sending FSK
to a Caller Display unit. If low, it makes the SLIC present a
high impedance to the POTS line)
59 ILINE1 input
POTS Port 1 Hook Switch Status Detector
(on-hook = low)