MUSIC MU9C8338-TFC, MU9C8338-TFI Datasheet
Data Sheet
MU9C8338 10/100Mb Ethernet Filter Interface
MU9C8338 10/100Mb Ethernet Filter Interface
MU9C8338 10/100Mb Ethernet Filter InterfaceMU9C8338 10/100Mb Ethernet Filter Interface
APPLICATION BENEFITS
• 10/100Mb Ethernet wire speed switching and
bridging for remote access and wireless networks
• Glueless connection to MUSIC LANCAM and most
10/100Mb Ethernet chip sets
• Offloads all DA/SA processing and management
functions from host processor
• Support station lists from 256 up to 32K
• Full support of Unicast, Multicast, and Broadcast
frames
• Built-in generic Processor port
MUSIC
10/100
PHY
10/100
MAC
MII
REJECT
FR_ERR
TAG
MU9C8338
MII and
TAG Port
Packet
Parser
DISTINCTIVE CHARACTERISTICS
• Industry-standard 10/100Mb MII port
• Supports station list up to 32K addresses
• Port ID and MAC Frame Reject signal based on DA
search results
• Read search results from the Result port or CPU port
• Hardware support for Tag switching
• Optional automatic learning of new SAs
• Optional automatic Aging and Purging
• 144–pin LQFP packages
• 3.3 Volt operation with 5 Volt tolerant I/O
Processor
Interface
Controller
Result
Port
Processor
ASIC
LANCAM
Interface
MUSIC
LANCAM
Figure 1: System Application Diagram
MUSIC Semiconductors, th e MUSIC logo, and the phrase "MUSIC Semiconductors" are March 27, 2001 Rev. 1a
Registered trademarks of MUSIC Semiconductors. MUSIC and Epoch are a trademarks of
MUSIC Semiconductors.
Registers
MU9C8338 10/100Mb Ethernet Filter Interface General Description
GENERAL DESCRIPTION
The MU9C8338, when configured with the MUSIC
Semiconductors MU9Cx480B family of LANCAMs
provides a high performance, large capacity Ethernet
address processing subsystem for use in Ethernet bridge,
OPERATIONAL OVERVIEW
Because of the flexibility of the MU9C8338, the best way
to approach the feature set of the device is to first look at a
typical 10/100Mb Ethernet application. The MU9C8338
captures the Destination address (DA) and the Source
address (SA) of an incoming Ethernet frame on the MII
port. After checking for a frame error or collision, the DA
is processed and the result (associated data, usually a port
ID) is made available. The SA then is checked, and either
learned if new, or aged if already in the list.
Typ ical MU9C8338 Application
The MU9C8338 plays an integral role in the example of
an Ethernet bridge system, shown in Figure 1.
This system can handle up to 32,768 addresses on a
bidirectional 100Mb Ethernet port by utilizing the
MU9C8338 device and four LANCAMs connected as
shown in Figure 1. The MII bus is "tapped" to collect
packet data as it passes from the Ethernet PHY to the
MAC. That data is processed automatically by the
MU9C8338/LANCAM combination. The MU9C8338
transfers the DA and SA to the CAMs for comparison. The
results of MU9C8338/LANCAM data processing are
available through the Result bus or through the Processor
bus. In addition to the Result bus, there is a serial Tag port
switch, or remote access products. The device is designed
to work in single-port system supporting a 100Mb/s
Ethernet port at wire speed.
for the MII port to relay the Tag ID to the system for
systems that support Tag switching.
When the DA is processed, the MU9C8338 first checks if
the frame is Unicast, Multicast, or Broadcast. Unicast
frames destined for the same collision domain (visible on
the same switch port as it came in on) are rejected. If the
DA is found in the CAM database, the port ID associated
with it is stored in the Result register. Multicast and
Broadcast frames are not processed by the system. Instead
they are identified and their classification is stored in the
Result register. Once processing completes, the Result
register is accessed through the Result port or Processor
port.
Provided the frame length is correct, and no errors are
detected, the SA is processed. If the SA exists in the CAM
database, the time stamp and Port ID are updated. If the
SA is not found in the CAM database, the address is
learned automatically, along with its Port ID and the
current time stamp information.
Address processing always has priority over management
routines, such as purging aged entries, inserting permanent
entries, deleting entries, or reading from the CAM
database.
2Rev. 1a
Pin Descriptions MU9C8338 10/100Mb Ethernet Filter Interface
PIN DESCRIPTIONS
Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.
Inputs should never be left floating. Refer to the Electrical Characteristics section for more information.
/WRITE
/PCSS
PROC_RDY
/ INTR
GND
/RESET
INCR
VDD
/PCS
VDD
D1
D0
GND
A7
A6
A5
A4
A3
A2A1A0
VDD
D6
D4
D5
D3
D2
D7
D12
D13
D11
D10
D9
D8
D14
GND
VDD
RP0
RP1
RP2
RP3
GND
RP4
RP5
RP6
VDD
RP7
RP8
RP9
RP10
RP11
RP12
GND
RP13
RP14
RP15
RP_DV
VDD
SC_ENB
TST_HLD
GND
TST_HLD2
VDD
RP_NXT
RP_SEL
GND
GND
1
144
6
12
18
NC
NC
NC
NC
NC
24
30
36
138
42
132
48
126
54
120
60
114
66
108
102
VDD
D15
NC
/RESET_LC
/W
/E
/CM
/EC
GND
/MI
/FI
96
90
84
78
72
VDD
DQ0
DQ1
GND
DQ2
DQ3
DQ4
DQ5
VDD
DQ6
NC
DQ7
DQ8
DQ9
DQ10
GND
DQ11
DQ12
DQ13
NC
DQ14
DQ15
GND
SYSCLK
NC
NCNCNCNCNCNCNCNCNC
TP_SD
FRX_ER
GND
TP_DV
NC
VDD
REJ
Figure 2: Pinout
MII Interface
RXD[3:0] (Receive Data, Input, TTL)
RXD[3:0] is the 4-bit MII Receive Data nibble (see
Timing Diagrams: Timing Data for RXD, RX_DV, and
RX_ER).
RX_DV (Receive Data Valid, Input, TTL)
Data Valid is on RX_DV; RX_DV is asserted by the PHY
at the beginning of the first nibble of the data frame and
deasserted at the end of the last nibble of the frame. It
indicates that the data is synchronous to RX_CLK and is
itself synchronous to the clock (see Timing Diagrams:
Timing Data for RXD, RX_DV, and RX_ER).
RX_ER (Receive Error, Input, TTL)
RX_ER indicates a data symbol error in 100Mb/s mode or
Rev. 1a
3
NC
GND
RXD3
RXD0
RXD1
RXD2
VDD
RX_DV
RX_CLK
COL
RX_ER
CRS
GND
TDO
GND
TDI
TCK
VDD
TMS
/TRST
any other error that the PHY can detect, even if the MAC
is not capable of detecting that error (see Timing
Diagrams: Timing Data for RXD, RX_DV, and RX_ER).
RX_CLK (Receive Clock, Input, TTL)
RX_CLK is the receive clock recovered from the data by
the PHY. It is equal to 25MHz in 100Base-X mode or
2.5MHz in 10Base-X mode.
CRS (Carrier Sense, Input, TTL)
Carrier sense CRS indicates that the medium is active
(non-idle) and remains asserted during a collision. For Rx
or Tx: CRS is HIGH in 10/100Base-X half-duplex mode;
for Rx it is HIGH in repeater, full-duplex, and loopback
modes. CRS is not synchronized to RX_CLK.
MU9C8338 10/100Mb Ethernet Filter Interface Pin Descriptions
COL (Collision, Input, TTL)
Collision detect COL is asserted by the PHY upon
detection of a collision on the medium and remains
asserted as long as the collision persists. It is HIGH in
half-duplex modes and remains HIGH for 1 microsecond
following the end of transmission; it is LOW in
full-duplex mode. It is asserted in response to
signal_quality_error message from the PMA in 10Base-X
Heartbeat mode.
Tag Port Interface
REJ (Reject, Output, TTL)
REJ is the reject packet command issued by the
MU9C8338. REJ is driven HIGH to reject a data frame,
and can be detected by and responded to by the MAC
device from 2 bit times after SFD to 512 bit times (64 byte
times) after SFD. The REJ signal can be made active
LOW by setting Bit 0 in the SSCFG register. (See Timing
Diagrams: REJ Timing Data.
FRX_ER (Frame Error, Output, TTL)
The Forced Receive Error pins provide the logical OR of
the RX_ER and REJ lines for the MII port (see Timing
Diagrams: Timing Data for FRX_ER in Relation to REJ
and RX_ER).
TP_SD (Ta g Port Data, Output, TTL)
The Tag Port Serial Data pin carries the destination Port
ID to external circuitry as soon as it is collected from the
CAM (see Timing Diagrams: Timing Data for Tag Ports
TP_DV and TP_SD).
TP_DV (Tag Port Data Valid, Output, TTL)
The Tag Port Data Valid pin is driven HIGH for as long as
unread data exists for the Destination Port ID. Pin TP_SD
carries the Destination Port ID (6 bits) to external circuitry
as soon as it is collected from the CAM (see Timing
Diagrams: Timing Data for Tag Ports TP_DV and
TP_SD).
Result Port Interface
See Timing Diagrams: Timing Data for Result Port
Interface. Table 1 shows the Result Port bit descriptions.
Note: Although the result data register can also be read through
the processor port, it is important to note that the means of
retrieving the data must be unique. Therefore, if the user is not
using the Result Port Interface, but is reading result data through
the processor port, RP_NXT and RP_SEL should be pulled low.
This ensures that all result data remains in the Result Data
register until read through the processor port. RP_NXT and
RP_SEL should be pulled low to 0 volts through a pull-down
resistor (typically 10k ohms).
RP[15:0] (Result Port Data, Output, Tri-state, TTL)
The Result Port Data carries the results of recently
processed packets detected on the MII port. See Table 1
for details of the Result Port Data bit descriptions. These
are identical to the Result Data register bits.
RP_DV (Result Port Data Valid, Output TTL)
The Result Port Data Valid indicates that the RP port
carries valid packet data. As long as there is valid packet
data, RP_DV will stay HIGH.
RP_NXT (Result Port Next Data, Input, TTL)
The Result Port Next pin brings the next result to the RP
bus if RP_SEL is asserted. If there are no additional results
available, the RP_DV will drop LOW after the time
interval specified in the Result Port Timing specification.
RP_SEL (Result Port Select, Input, TTL)
The Result Port Select pin controls RP[15:0] and
RP_NXT. RP_NXT and RP_SEL are connected by a
logical AND. Therefore, RP_SEL must be HIGH in order
for RP_NXT to bring the next result to the RP bus.
RP_SEL can stay continuously HIGH as long as there is
valid packet data, RP_DV will stay HIGH.
Table 1: Result Port Bit Descriptions
Bit(s) Description
15:10 6-Bit Source Port ID
9:8 Packet Type: Broadcast = 00, Multicast = 01,
Unicast = 10
7 (if Unicast) Match Found
6:1 6-Bit (if CAM Match Found) Destination Port ID
0 (If Match Found) Destination Port = Source Port
Control Interfaces
See Timing Diagrams: Timing Data for Control Interfaces.
SYSCLK (System Clock, Input, TTL)
CLK is the user-supplied system clock for synchronous
chip operation; its frequency must be 25-50 MHz with
duty cycle between 45 to 55 percent.
/RESET (Reset, Input, TTL)
When system Reset is taken LOW, all internal
state-machines are reset to their initial state and any data is
cleared. All registers are returned to default values.
/RESET is synchronous and should be held LOW for a
minimum of two SYSCLK cycles. The user must set the
LANCAM Segment Control register after asserting
/RESET.
4Rev. 1a
Pin Descriptions MU9C8338 10/100Mb Ethernet Filter Interface
INCR (Increment Time Stamp Counters, Input, TTL)
INCR is a user command to invoke the built-in purge
routine. Both STCURR and STPURG 8-bit counters are
advanced one count on the rising edge of INCR, and the
time stamp stored with each LANCAM entry is compared
with STPURG. Matching entries subsequently are purged
or deleted. This pin must be configured, if it is required, by
setting bit 2 and bit 3 in the System Target (STARG)
register. Each counter can be incremented individually
through the Processor Port. (see Operational
Characteristics: STARG System Target Register
Mapping).
Host Processor Interface
The Host Processor interface is asynchronous to the
System Clock. This interface is controlled by the /PCS or
/PCSS (whichever is appropriate) and PROC_RDY
signals, which form the handshaking between the
processor and the MU9C8338. This allows the end system
to use a processor that runs at a different clock speed than
the clock required by the MU9C8338. (see Timing
Diagrams: Timing Data for Host Processor Interface).
/PCS (Processor Port Chip Select, Input, TTL)
Processor Chip Select is taken LOW by the host processor
to gain access to the MU9C8338 Port or Chip registers.
/PCSS (Processor Port Chip Select System, Input, TTL)
Processor Chip Select System is taken LOW by the host
processor to gain access to the MU9C8338 System
registers or to access the LANCAM.
/WRITE (Processor Port Read/Write, Input, TTL)
Read/Write determines the direction of data flow into or
out of the MU9C8338 host processor interface. If /WRITE
is LOW, the data is written into the register selected by
A[7:0] and /PCS or /PCSS; if HIGH, the data is read from
the register selected by A[7:0] and /PCS or /PCSS.
A[7:0] (Processor Port Address, Input, TTL)
Processor Address bus A[7:0] selects the MU9C8338
register accessed by the host processor.
D[15:0] (Processor Port Data, Input/Output, Tri-state, TTL)
Processor Data bus D[15:0] is the tri-state processor data
bus for the MU9C8338.
PROC_RDY (Processor Port Ready, Output, Tri-state, TTL)
When reading from or writing to any MU9C8338 internal
register, the PROC_RDY tri-state output goes LOW on the
falling edge of /PCS or /PCSS. If it is a read cycle,
PROC_RDY goes HIGH on the rising edge of SYSCLK
once data is available. If it is a write cycle, PROC_RDY
goes HIGH on the rising edge of SYSCLK when the
internal register is ready to accept data.
/INTR (Processor Interrupt, Output, TTL)
/INTR goes LOW to signal that one of the four
configurable interrupt conditions have been satisfied. The
four separate conditions are configured by setting bits in
the appropriate register. /INTR returns HIGH when the
appropriate register is read. See Table 2 for details of
which interrupt conditions are possible and which register
must be read to reset the /INTR pin to HIGH.
Table 2: /INTR Settings
Register R equired to
Select Interrupt
Condition
PTARG RSTAT. Please note that /INTR will only return
STARG SSTAT. Please note that /INTR will only return
Rev. 1a
5
To clear /INTR, Read Interrupt Condition
HIGH when all possible result data has been read.
HIGH when the LANCAM has become not full.
Therefore, after the SSTA T register read has
confirm e d th e status of the in te r r u pt c on d ition, an
entry should be removed from the LANCAM by
using the PURGE sequence.
The MII port ha s parsed an incoming packet. The DA lookup
has been performed and the result data is available to be
read from RDAT register.
The /FF output from the LANCAM (s) has indicated that the
LANCAM is full. When reading the SSTAT register, a full
condition is indicated by bit 0 = 0.
MU9C8338 10/100Mb Ethernet Filter Interface Pin Descriptions
LANCAM Interface
See Timing Diagrams: Timing Data for LANCAM
Interface.
DQ[15:0] (LANCAM Bus, Input/Output, Tri-state, TTL)
DQ[15: 0] tri-state 16- bit bus transfers data or instructions
between the MU9C8338 and the LANCAM. When no
data or instructions are present on the bus, the bus goes
HIGH-Z.
/E (LANCAM Bus Enable, Output, Tri-state, TTL)
The /E chip enable is taken LOW to initiate LANCAM
activity. On LANCAM read cycles, /E is taken HIGH after
the MU9C8338 registers the data.
/W (LANCAM Bus Write, Output, Tri-state, TTL)
The MU9C8338 outputs /W (read/write select) to control
the direction of data flow between the MU9C8338 and the
LANCAM. If /W is LOW at the falling edge of /E, the
MU9C8338 outputs data on the DQ[15:0] bus for the
LANCAM as input. When /W is HIGH at the falling edge
of /E, the LANCAM outputs data on the DQ[15:0] bus to
the MU9C8338 as input.
/CM (LANCAM Bus Command Mode, Output, Tri-state, TTL)
The MU9C8338 outputs /CM Data/Command Select to
control whether the LANCAM interprets the DQ[15:0]
bus contents as command information or data. If both /CM
and /W are LOW at the falling edge of /E, the MU9C8338
outputs an instruction for the LANCAM to execute or a
value for one of the LANCAM configuration registers. If
/CM is LOW while /W is HIGH, then the LANCAM will
output data from one of its configuration registers to the
MU9C8338. If /CM is HIGH while /W is LOW, the
MU9C8338 will output data for the LANCAM to place in
one of its data registers or memory. If /CM is HIGH while
/W is HIGH, the LANCAM outputs data from one of its
data registers or memory to the MU9C8338.
/EC (LANCAM Bus Enable Chain, Output, Tri-state, TTL)
The Daisy Chain Enable signal performs two functions.
The /EC signal enables the LANCAMs /MF output to
show the results of a comparison. If /EC is LOW at the
falling edge of /E in a cycle, the /MF flag output is
enabled; otherwise, /MF is held HIGH. The /EC signal
also enables the /MF-/MI daisy chain that serves to select
the device with the highest-priority match in a string of
LANCAMs.
/MI (LANCAM Bus Match Flag, Input, TTL)
The /MI LANCAM Match flag input is used to indicate to
the MU9C8338 the conditions of the LANCAM Match
flag. The /MF output from the LANCAM should be
connected to this pin. If more than one LANCAM is used,
/MI should be connected to the /MF pin of the last
LANCAM in the daisy chain.
/FI (LANCAM Bus Full Flag, Input, TTL)
The /FI LANCAM Full flag input is used to indicate to the
MU9C8338 the condition of the LANCAM Full flag. The
/FF output from the LANCAM should be connected to this
pin. If more than one LANCAM is used, /FI should be
connected to the /FF of the last device in the daisy chain.
/RESET_LC (Reset LANCAM, Output, TTL)
/RESET_LC is LOW whenever /RESET is LOW. It is
taken HIGH only by writing to bit 0 in the System
Dynamic Configuration (SDCFG) register. See SDCFG
register information.
Test
SC_ENB (Scan Enable)
Enables scan chain for testing. Pin may be left
unconnected or tied to GND for normal operation
TST_HLD, TST_HLD2 (Test Hold)
Enables test mechanism. Pins may be left unconnected or
tied to GND for normal operation.
JTAG
Note: Please refer to IEEE Standard 1149.1 for information on
using the mandatory JTAG functions. The optional HIGH-Z
function is implemented and may be activated by writing 0011 to
the JTAG Instruction register.
/TRST (JTAG Reset, Input)
The /TRST is the Test Reset pin. It is internally pulled up
with a 3k minimum resistor. It must be tied to /RESET or
tied LOW when the JTAG port is not used.
TMS (JTAG Test Mode Select, Input)
The TMS input is the Test Mode Select input. This pin is
internally pulled up with a 3k minimum resistor.
TCK (JTAG Test Clock, Input)
The TCK input is the Test Clock input. It can be tied at a
valid logic level 1 when not in use. This pin is internally
pulled up with a 3k minimum resistor.
TDI (JTAG Test Data Input, Input)
The TDI input is the Test Data input. This pin is internally
pulled up with a 3k minimum resistor.
TDO (JTAG Test Data Output, Output)
The TDO output is the Test Data output.
Po wer and Ground
VDD, GND (Positive Power Supply, Ground)
These pins are the power supply connections to the
MU9C8338. VDD must meet the voltage supply
requirements in the Operating Conditions section relative
to the GND pins, which are at 0 Volts (system reference
potential), for correct operation of the device.
6Rev. 1a
Functional Description MU9C8338 10/100Mb Ethernet Filter Interface
FUNCTIONAL DESCRIPTION
Internal Functions
MU9C8338 internal functions are shown in Figure 3.
Before discussing the individual blocks, the underlying
principles are presented. The network interface is
monitored for network and data symbol errors. Receive
data [RXD] is clocked into a register using the 25MHz
recovered clock for 100Base-X or 2.5MHz clock for
10Base-X. The Preamble and Start Frame delimiter (SFD)
are scanned to locate the Destination address (DA) and the
Source address (SA).
The LANCTL block generates the command cycles and
operational codes to complete CPU-requested actions and
network-generated requests. The CPU must initialize the
CAM, write the permanent station list, and initiate other
housekeeping functions. Network traffic initiates DA
filtering, SA learning, and time stamp updates. All
state-machines required for real-time operations are
implemented in the ASIC hardware; the host CPU runs the
non-time-critical initialization routine.
The MU9C8338 schedules communication with the host
processor and the CAM through an arbitration process.
Once the system is initialized and configured,
highest-priority is given to network traffic.
FRX_ER
RX_DV
RX_ER
RXD[3:0]
RX_CLK
CRS
COL
CPU Bus
REJ
TP_SD
TP_DV
MII
Interface
Host CPU
Interface
Tag Port
Interface
MAC
Receiver
Configuration,
Control and Status
Registers
Information on the LANCAM operation and instruction
set can be found in the appropriate LANCAM data sheet
for each device.
LANCAM Bus
LANCAM
Interface
TCK
LANCTL
JTAG
Controller
TMS
TDI
TDO
/TRST
Result Bus
Rev. 1a
Result Bus
Interface
FIFO
Figure 3: Functional Block Diagram
7
MU9C8338 10/100Mb Ethernet Filter Interface Functional Description
Destination Address Processing
Once configured, the MU9C8338 will extract the DA from
the frames that are received through the MII port. An
automatic address processing function is subsequently
triggered. Once the DA processing function is triggered,
the frame is monitored to detect whether it is a broadcast,
multicast, or unicast frame and the appropriate actions are
taken. DA processing consists of the following actions:
• Packets are characterized as Broadcast, Multicast, or
Unicast types.
• Unicast packets initiate a search of the CAM for
existing entries.
• If a DA match is found, the Port ID read from the
CAM is compared to the Source Port ID. If the Source
Port ID and Destination Port ID match, the frame is
rejected. If the Port IDs are different, the Tag
information is made available for MACs that support
Tag switching, through the Tag port.
• If the MU9C8338 rejects the frame, it asserts the
Reject output pin (REJ) and forces the MII RX_ER
output (FRX_ER) HIGH for the MII Port. This causes
the MAC to discard the frame.
• Once the DA processing function is complete, the
MU9C8338 stores the result. This result indicates the
characterization of the processed frame. (Broadcast,
Multicast, or Unicast) and the Source Port ID.
Additionally, if a unicast frame was processed, the
result of the search and the port ID of the DA is also
stored. Finally, the detail of whether the Destination
port and the Source port are identical is also stored.
• The result of DA processing may be read in two ways.
1. An interrupt may be sent to the host processor
indicating that there is a result available. The host
processor would read the result from an internal
Result Data register.
2. External circuitry can monitor the status of the
Result Port Data valid (RP_DV) output pin. This
output indicates that there is a result available in the
internal register which can be read through the Result
port. The external circuitry can read the data by
asserting the Result Port Select (RP_SEL) pin.
Assertion of Result Port Next (RP_NXT) clears the
value and advances the next entry if there is one
available.
Source Address Processing
Once configured, the MU9C8338 also will perform SA
processing functions after the address information has
been extracted from a received frame. The SA of each
arriving frame is stored by the MU9C8338 for further
processing, along with the port ID and the current time
stamp. Note that at start-up, permanent addresses and their
Port ID are loaded into the LANCAM through the CPU
port; as message traffic proceeds, new addresses are
learned and added to the LANCAM database, and aged
addresses are purged. SA processing consists of the
following actions:
• The SA field is collected and temporarily stored. Note
the SA cannot be a Broadcast or Multicast address by
definition.
• When the complete packet has arrived, the CRC field
is checked and the length of the packet is checked.
Any errors result in no further SA processing.
• If the packet did not contain any errors, (or the CRC
check facility is disabled), the SA field is compared
with the address fields that are stored in the
LANCAM.
• If a match is found, the Port ID and time stamp for
that entry are updated. If no match is found, the SA is
added to the CAM, along with the current time stamp
and the Port ID assigned to that particular Source port.
Functional Blocks
The building blocks that make up the MU9C8338 are
shown in Figure 3, and their functions are described by the
following.
MII Interface (MII Port)
The incoming asynchronous receive data is registered for
subsequent processing. MU9C8338 internal processing is
synchronous with the system clock.
Tag Port Interface (Tag P ort)
Rejection of a packet is indicated by the assertion of REJ.
The FRX_ER line, which otherwise reflects the state of
the RX_ER pin, is forced to HIGH at the same time. If the
DA is matched in the LANCAM, the TP_DV pin is
asserted and the destination port ID, high-order bit first, is
clocked out through the TP_SD pin transitioning after the
RX_CLK rising edge.
MAC Receiver
This block performs tasks that are a subset of the Ethernet
MAC. It detects errors, (CRS, COL, RX_ER, and Runt
Frame), determines the start of frame, parses addresses,
computes the CRC for 10Base-X packets, and formats the
4-bit nibbles into 48-bit SA and DA registers.
8Rev. 1a
Functional Description MU9C8338 10/100Mb Ethernet Filter Interface
MAC Address Storage
When the MU9C8338 performs an SA processing
function, it automatically extracts the MAC address from
the packet. The database is searched and the MAC address
is added to the LANCAM database if necessary. Similarly,
when a DA processing function is performed, the
MU9C8338 automatically searches the database for the
extracted DA MAC address.
It is important that the user is aware of the byte ordering of
the 48-bit MAC address when it is stored in the LANCAM
database. This is because the user must byte-order MAC
addresses identically when a database entry is to be
manually added or deleted. Similarly, if the user wishes to
read out a MAC address, they should also be aware of the
byte ordering when the relevant data registers are read.
Throughout this data sheet MAC addresses are shown as
bit 47 being the most significant bit, which is placed on the
left. Similarly, bit 0 is shown as the least significant bit and
placed on the right. Using this notation, the
Individual/Group (I/G) bit subfield would be shown as bit
40. This bit would be the first bit of an address transmitted
If the MAC address shown in Figure 4 is added to the
database by the MU9C8338, it is stored as follows:
• Segment 3 = 6002h
• Segment 2 = 128Ch
• Segment 1 = 5634h
• Segment 0 = Associated data (permanent bit, time
stamp and port ID)
If the user wishes to use the built-in routines to manually
add, delete, or read MAC addresses from the database, the
System CAM Word registers (SCDW) are used as shown
in Figure 5. It shows how the MAC address, used as an
example in Figure 4, would be transferred using the
SCDW registers.
If the user intended to delete the MAC address, the SCDW
registers would be written as shown in item 1 and the
SDO_DELETE routine would be invoked.
If the user intended to add the address manually, the
SCDW registers would be written as shown in item 2 and
the SDO_ADD routine would be invoked.
onto the serial network and also the first bit received. The
IEEE 802.3 refers to the I/G bit subfield as bit 0. If the bit
is set to 1, it indicates that the address is a group address.
Conversely, if the bit is set to 0, it indicates it is an
individual address. Figure 4 shows a typical 48-bit MAC
address used in Ethernet or IEEE 802.3 networks.
47 40 162324313239 070815 00
:::::
02 5634128C60
MAC Address
Finally, if the user intended to read an entry, the
SDO_READ routine would be invoked and the address
would be read from the SCDW registers as shown in item
3. The built-in routines are explained more fully later in
this document.
1
SDO_DELETE
SCDW3 SCDW2 SCDW1 SCDW0
6002not used 5634128C
IEEE bit 0
Rev. 1a
0000 0010
I/G bit
LANCAM Database Entry
seg 3 seg 2 seg 1 seg 0
6002 assoc. data5634128C
Figure 4: MAC Address Byte Order
9
2
SDO_ADD
3
SDO_READ
SCDW3 SCDW2 SCDW1 SCDW0
6002 assoc. data5634128C
SCDW3 SCDW2 SCDW1 SCDW0
6002 assoc. data5634128C
Figure 5: SCDW Register Order
Loading...