MUSIC MU9C448L-10DC, MU9C4481L-10DC, MU9C8481L-10DC, MU9C2481L-10DC, MU9C248L-10DC Datasheet

LANCAM® 1ST Family

MUSIC Semiconductors, the MUSIC logo, LANCAM, and the phrase “MUSIC Semiconductors” are
registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC
Semiconductors. Certain features of this device are patented under U.S. Patent 5,383,146.

1 October 1998 Rev. 1a

Block Diagram

DISTINCTIVE CHARACTERISTICS

Preliminary Data Sheet

Ø High density content-addressable memory

(CAM) family

Ø 2K (2481L), 4K (4481L), and 8K (8481L) words
Ø 64-bit per word memory organization

Ø Fast 100 ns compare speed
Ø MUSIC’s patented CAM/RAM partitioning
Ø Powerful LANCAM instruction set
Ø 16-bit I/O
Ø 3.3 volt operation
Ø 44 pin PLCC

FEATURES AND BENEFITS

Ø Full compatibility among all LANCAM 1

ST

devices, allowing CAM density variations
within any application

Ø Full CAM technology for simplicity and

speed: one single cycle to find, learn, or
delete an entry

Ø 3.3 volt operation for low power dissipation
Ø Powerful LANCAM instruction set for

application flexibility

Ø Partionable CAM/RAM array for associated

data storage

Ø Low cost per entry for cost sensitive

applications

ADDRESS/W

/E

/CM

DQ (15–0)

(16 )

I/O BUFFER

S

CONTROL

CAM ARRAY

2N WORDS

X 64 BIT S

COMPARAND

MASK 1
MASK 2

2

N

x

2 VALIDITY BITS

PRIORITY ENCODER

COMMANDS & STATUS

N

MUX

DAT A (16)

DEMUX

SOURCE AND
DESTINATION

SEGMENT

COUNTERS

VCC

GND

INSTRUCTION (W/O)*

NEXT FR EE A D D R ESS (R /O )

CONTROL

SEGMENT CONTROL

ADDRESS

STATUS (15–0) (R/O)*

STAT U S (3 1–16) (R/ O )

REG I ST ER S ET

2

MATCH ADDR, /MF

/MM, /FF

DAT A (16)

(16 )

DAT A (64)

DAT A (64)

AD DR ESS D EC O D ER

/RESET

/MF
/FF

N+1

LANCAM 1ST Family

Rev. 1a 2

OPERA TIONAL OVER VIEW

To use the LANCAM 1ST, the user loads the data into the
Comparand register, which is automatically compared to all
valid CAM locations. The device then indicates whether
or not one or more of the valid CAM locations contains
data that match the target data. The status of each CAM
location is determined by two validity bits at each memory
location. The two bits are encoded to render four validity
conditions: Valid, Skip, Empty, and Random Access, as
shown in Table 1. The memory can be partitioned into CAM
and associated RAM segments on 16-bit boundaries, but
by using one of the two available mask registers, the
CAM/RAM partitioning can be set at any arbitrary size
between zero and 64 bits.

The LANCAM 1ST’s internal data path is 64 bits wide for
rapid internal comparison and data movement. Loading data
to the Control, Comparand, and mask registers

automatically triggers a compare. Compares may also be
initiated by a command to the device. Associated RAM
data is available immediately after a successful compare
operation. The Status register reports the results of
compares including all flags and addresses. Two Mask
registers are available and can be used in two different
ways: to mask comparisons or to mask data writes. The
random access validity type allows additional masks to
be stored in the CAM array where they may be retrieved rapidly.

A simple three-wire control interface and commands
loaded into the Instruction decoder control the device.
A powerful instruction set increases the control flexibility
and minimizes software overhead. These and other
features make the LANCAM 1ST a powerful associative
memory that drastically reduces search delays.

Skip Bit

0
0
1
1

Empty Bit

0
1
0
1

Entry Type

Valid

Empty

Skip

RAM

Table 1: Entry Types vs. Validity Bits

Pinout Diagram

Table 2: I/O Cycles

/W

LOW

LOW
HIGH
HIGH

/CM

LOW

HIGH

LOW

HIGH

Cycle Typ e

Command Write Cycle
Data Write Cycle
Command Read Cycle
Data Read Cycle

GENERAL DESCRIPTION

The LANCAM 1

ST

family consists of high density content­addressable memories (CAMs) in a variety of depths. Like the
other LANCAM series from MUSIC Semiconductors, the
LANCAM 1ST is ideal for time critical applications requiring
intensive list processing.

Content-addressable memories, also known as associative
memories, operate in the converse way to random access
memories (RAM). In RAM, the input to the device is an address
and the output is the data stored at that address. In CAM, the
input is a data sample and the output is a flag to indicate a
match and the address of the matching data. As a result, CAM

searches large databases for matching data in a short, constant
time period, no matter how many entries are in the database.
The ability to search data words up to 64 bits wide allows large
address spaces to be searched rapidly and efficiently. A
patented architecture links each CAM entry to associated data
and makes this data available for use after a successful
compare operation.

The MUSIC LANCAM 1ST is ideal for address filtering and
translation applications in LAN switches and routers. The
LANCAM 1ST is also well suited to encryption, data caches,
and branch tables.

GND
DQ4

DQ5

VCC

VCC

TES T 2

GND
GND
DQ6
DQ7

VCC

GND
/R
VCC
VCC
TES T 1
/E
/W
GND

NC

/FF

/CM

GND

DQ 0

DQ 1

DQ2

DQ 3

VCC

GND

DQ15

DQ14

DQ13

DQ12

GND

DQ11

DQ10

DQ9

DQ8

GND

44-pin PLCC

(Top View)

40

41

42

43

44

12345

6

7
8
9
10
11
12
13
14
15
16
17

39
38
37
36
35
34
33
32
31
30
29

28

27

26

25

24

23

22

21

20

19

18

NC
/MF
VCC

GND

VCC

LANCAM 1ST Family

Rev . 1a3

/E (Chip Enable, Input, TTL)

The /E input enables the device while LOW. The falling
edge registers the control signals /W and /CM. The rising
edge turns off the DQ pins and clocks the Destination and
Source Segment counters. The four cycle types enabled
by /E are shown in Table 2 on page 2.

/W (Write Enable, Input, TTL)

The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle and /W HIGH
selects a Read cycle.

/CM (Data/Command Select, Input, TTL)

The /CM input selects whether the input signals on
DQ15–0 are data or commands. /CM LOW selects Command
cycles and /CM HIGH selects Data cycles.

DQ15–0 (Data Bus, I/O, TTL)

The DQ15–0 lines convey data, commands, and status to
and from the LANCAM 1ST. /W and /CM control the
direction and nature of the information that flows to or
from the device. When /E is HIGH, DQ15–0 go to Hi-Z.

/MF (Match Flag, Output, TTL)

The /MF output goes LOW when one or more valid
matches occur during a compare cycle. /MF is HIGH if
there is no match. /MF will be reset when the active
configuration register set is changed.

/FF (Full Flag, Output, TTL)

The /FF output goes LOW when no empty memory
locations exist within the device.

/RESET (Reset, Input, TTL)

/RESET must be driven LOW to place the device in a known
state before operation, which will reset the device to the
conditions shown in Table 4 on page 8. The /RESET pin
should be driven by TTL levels, not directly by an RC time­out. /E must be kept HIGH during /RESET .

TEST1, TEST2 (T est, Input, TTL)

These pins enable MUSIC production test modes that are
not usable in an application. They should be connected to
ground, either directly or through a pull-down resistor, or
they may be left unconnected. These pins may not be
implemented on all versions of these products.

VCC, GND (Positive Power Supply , Ground)

These pins are the power supply connections to the
LANCAM 1ST. VCC must meet the voltage supply
requirements in the Operating Conditions section relative
to the GND pins, which are at 0 Volts (system reference
potential), for correct operation of the device. All the
ground and power pins must be connected to their
respective planes with adequate bulk and high frequency
bypassing capacitors in close proximity to the device.

PIN DESCRIPTIONS

All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs
should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout
and bypassing techniques. Refer to the Electrical Characteristics section for more information.

LANCAM 1ST Family

Rev. 1a 4

FUNCTIONAL DESCRIPTION

The LANCAM 1ST is a content-addressable memory
(CAM) with 16-bit I/O for network address filtering and
translation, virtual memory, data compression, caching,
and table lookup applications. The memory consists of
static CAM, organized in 64-bit data fields. Each data
field can be partitioned into a CAM and a RAM subfield
on 16-bit boundaries. The contents of the memory can
be randomly accessed or associatively accessed by the
use of a compare. During automatic comparison cycles,
data in the Comparand register is automatically compared
with the “V alid” entries in the memory array. The Device
ID can be read using a TCO PS instruction (see T able 11
on page 16).

The data inputs and outputs of the LANCAM 1ST are
multiplexed for data and instructions over a 16-bit
I/O bus. Internally, data is handled on a 64-bit basis,
since the Comparand register, the mask registers, and
each memory entry are 64 bits wide. Memory entries are
globally configurable into CAM and RAM segments on
16-bit boundaries, as described in US Patent 5,383,146
assigned to MUSIC Semiconductors. Seven different
CAM/RAM splits are possible, with the CAM width
going from one to four segments, and the remaining RAM
width going from three to zero segments. Finer resolution
on compare width is possible by invoking a mask register
during a compare, which does global masking on a bit
basis. The CAM subfield contains the associative data,
which enters into compares, while the RAM subfield
contains the associated data, which is not compared. In
LAN bridges, the RAM subfield could hold, for example,
port-address and aging information related to the
destination or source address information held in the
CAM subfield of a given location. In a translation
application, the CAM field could hold the dictionary
entries, while the RAM field holds the translations, with
almost instantaneous response.

Each entry has two validity bits (known as Skip bit and
Empty bit) associated with it to define its particular type:
empty, valid, skip, or RAM. When data is written to the
active Comparand register, and the active Segment
Control register reaches its terminal count, the contents
of the Comparand register are automatically compared
with the CAM portion of all the valid entries in the
memory array. For added versatility, the Comparand
register can be barrel-shifted right or left one bit at a
time. A Compare instruction can then be used to force
another compare between the Comparand register and
the CAM portion of memory entries of any one of the
four validity types. After a Read or Move from Memory

operation, the validity bits of the location read or moved
will be copied into the Status register, where they can be
read using Command Read cycles.

Data can be moved from one of the data registers (CR,
MR1, or MR2) to a memory location that is based on the
results of the last comparison (Highest-Priority Match
or Next Free), or to an absolute address, or to the location
pointed to by the active Address register. Data can also
be written directly to the memory from the DQ bus using
any of the above addressing modes. The Address
register may be directly loaded and may be set to
increment or decrement, allowing DMA-type reading or
writing from memory.

Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background
activities. The currently active set of configuration
registers control writes, reads, moves, and compares.
The foreground set would typically be pre-loaded with
values useful for comparing input data, often called
filtering, while the background set would be pre-loaded
with values useful for housekeeping activities such as
purging old entries. Moving from the foreground task of
filtering to the background task of purging can be done
by issuing a single instruction to change the current set
of configuration registers. The match condition of the
device is reset whenever the active register set is
changed.

The active Control register determines the operating
conditions within the device. Conditions set by this
register’s contents are reset, CAM/RAM partitioning,
disable or select masking conditions, and disable or select
auto-incrementing or -decrementing the Address register.
The active Segment Control register contains separate
counters to control the writing of 16-bit data segments
to the selected persistent destination, and to control the
reading of 16-bit data segments from the selected
persistent source.

There are two active mask registers at any one time,
which can be selected to mask comparisons or data
writes. Mask Register 1 has both a foreground and
background mode to support rapid context switching.
Mask Register 2 does not have this mode, but can be
shifted left or right one bit at a time. For masking
comparisons, data stored in the active selected mask
register determines which bits of the comparand are

LANCAM 1ST Family

Rev . 1a5

compared against the valid contents of the memory. If a
bit is set HIGH in the mask register, the same bit position
in the Comparand register becomes a “don’t care” for
the purpose of the comparison with all the memory
locations. During a Data Write cycle or a MOV instruction,
data in the specified active mask register can also
determine which bits in the destination will be updated.
If a bit is HIGH in the mask register, the corresponding
bit of the destination is unchanged.

The match line associated with each memory address is
fed into a priority encoder where multiple responses are
resolved, and the address of the highest-priority
responder (the lowest numerical match address) is
generated. In LAN applications, a multiple response might
indicate an error. In other applications the existence of
multiple responders may be valid.

Three input control signals and commands loaded into an
instruction decoder control the LANCAM 1ST. T wo of the
three input control signals determine the cycle type. The
control signals tell the device whether the data on the I/O
bus represents data or a command, and is input or output.
Commands are decoded by instruction logic and control
moves, forced compares, validity bit manipulations, and
the data path within the device. Registers (Control, Segment
Control, Address, Next Free Address, etc.) are accessed
using Temporary Command Override instructions. The data
path from the DQ bus to/from data resources (comparand,
masks, and memory) within the device are set until changed
by Select Persistent Source and Destination instructions.

After a Compare cycle (caused by either a data write to the
Comparand or mask registers, a write to the Control register,
or a forced compare), the status register contains the address
of the Highest-Priority Matching location, along with flags
indicating match, multiple match, and full. The /MF and /FF
flags are also available directly on output pins.

FUNCTIONAL DESCRIPTION

Continued

OPERATIONAL CHARACTERISTICS

Throughout the following, “aaaH” represents a three-digit
hexadecimal number “aaa,” while “bbB” represents a
two-digit binary number “bb.” All memory locations are
written to or read from in 16-bit segments. Segment 0
corresponds to the lowest order bits (bits 15–0) and
Segment 3 corresponds to the highest order bits (bits
63–48).

THE CONTROL BUS

Refer to the Block Diagram on page 1 for the following
discussion. The inputs Chip Enable (/E), Write Enable (/W),
and Command Enable (/CM) are the primary control
mechanism for the LANCAM 1ST. Instructions are the
secondary control mechanism. Logical combinations of the
Control Bus inputs, coupled with the execution of Select
Persistent Source (SPS), Select Persistent Destination (SPD),
and Temporary Command Override (TCO) instructions
allow the I/O operations to and from the DQ15–0 lines to
the internal resources, as shown in Table 3 on page 7.

The Comparand register is the default source and
destination for Data Read and Write cycles. This default
state can be overridden independently by executing a Select
Persistent Source or Select Persistent Destination
instruction, selecting a different source or destination for
data. Subsequent Data Read or Data Write cycles will
access that source or destination until another SPS or SPD

instruction is executed. The currently selected persistent
source or destination can be read back through a TCO PS
or PD instruction. The sources and destinations available
for persistent access are those resources on the 64-bit bus:
Comparand register, Mask Register 1, Mask Register 2, and
the Memory array.

The default destination for Command Write cycles is the
Instruction decoder, while the default source for Command
Read cycles is the Status register.

Temporary Command Override (TCO) instructions provide
access to the Control register, the Segment Control register ,
the Address register, and the Next Free Address register.
TCO instructions are only active for one Command Read or
Write cycle after being loaded into the Instruction decoder .

The data and control interfaces to the LANCAM 1ST are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When writing
to the persistently selected data destination, the Destination
Segment counter is clocked by the rising edge of /E. During
a Read cycle, the Control inputs are registered by the falling
edge of /E, and the Data outputs are enabled while /E is
LOW. When reading from the persistently selected data
source, the Source Segment counter is clocked by the rising
edge of /E.

LANCAM 1ST Family

Rev. 1a 6

THE REGISTER SET

The Control, Segment Control, Address, Mask Register 1,
and the Persistent Source and Destination registers are
duplicated, with one set termed the Foreground set, and
the other the Background set. The active set is chosen by
issuing Select Foreground Registers or Select Background
Registers instructions. By default, the Foreground set is
active after a reset. Having two alternate sets of registers
that determine the device configuration allows for a rapid
return to a foreground network filtering task from a
background housekeeping task.

Writing a value to the Control register or writing data to the
last segment of the Comparand or either mask register will
cause an automatic comparison to occur between the
contents of the Comparand register and the words in the
CAM segments of the memory marked valid, masked by
MR1 or MR2 if selected in the Control register.

Instruction Decoder

The Instruction decoder is the write-only decode logic for
instructions and is the default destination for Command
Write cycles. If an instruction’ s Address Field flag (bit 1 1)
is set to a 1, it is a two-cycle instruction that is not executed
immediately. For the next cycle only, the data from a
Command Write cycle is loaded into the Address register
and the instruction then completes at that address. The
Address register will then increment, decrement, or stay at
the same value depending on the setting of Control Register
bits CT3 and CT2. If the Address Field flag is not set, the
memory access occurs at the address currently contained
in the Address register.

Control Register (CT)

The Control register is composed of a number of switches
that configure the LANCAM 1ST, as shown in Table 7 on
page 15. It is written or read using a TCO CT instruction. If
bit 15 of the value written during a TCO CT is a 0, the
device is reset (and all other bits are ignored). See Table 4
for the Reset states. Bit 15 always reads back as a 0. A write
to the Control register causes an automatic compare to
occur (except in the case of a reset). Either the Foreground
or Background Control register will be active, depending
on which register set has been selected, and only the active
Control register will be written to or read from.

Control Register bits 8–6 control the CAM/RAM
partitioning. The CAM portion of each word may be sized
from a full 64 bits down to 16 bits in 16-bit increments. The
RAM portion can be at either end of the 64-bit word.

Compare masks may be selected by bits 5 and 4. Mask
Register 1, Mask Register 2, or neither may be selected to
mask compare operations. The address register behavior is
controlled by bits 3 and 2, and may be set to increment,
decrement, or neither after a memory access.

Segment Control Register (SC)

The Segment Control register, as shown in T able 8 on page
16, is accessed using a TCO SC instruction. On read cycles,
D15, D10, D5, and D2 will always read back as 0s. Either the
Foreground or Background Segment Control register will
be active, depending on which register set has been
selected, and only the active Segment Control register will
be written to or read from.

The Segment Control register contains dual independent
incrementing counters with limits, one for data reads and
one for data writes. These counters control which 16-bit
segment of the 64-bit internal resource is accessed during
a particular data cycle on the 16-bit data bus. The actual
destination for data writes and source for data reads (called
the persistent destination and source) are set independently
with SPD and SPS instructions, respectively.

Each of the two counters consists of a start limit, an end
limit, and the current count value that points to the segment
to be accessed on the next data cycle. The current count
value can be set to any segment, even if it is outside the
range set by the start and end limits. The counters count
up from the current count value to the end limit and then
jump back to the start limit. If the current count is greater
than the end limit, the current count value will increment to 3,
then roll over to 0 and continue incrementing until the end
limit is reached; it then jumps back to the start limit.

If a sequence of data writes or reads is interrupted, the Segment
Control register can be reset to its initial start limit values by
using an RSC instruction. After the LANCAM 1ST is reset,
both Source and Destination counters are set to count from
Segment 0 to Segment 3 with an initial value of 0.

Address Register (AR)

The Address register points to the CAM memory location
to be operated upon when M@[AR] or M@aaaH is part of
the instruction. It can be loaded directly by using a TCO
AR instruction or indirectly by using an instruction requiring
an absolute address, such as MOV aaaH, CR,V. After being
loaded, the Address register value will then be used for the
next memory access referencing the Address register. A
reset sets the Address register to zero.

OPERATIONAL CHARACTERISTICS

Continued