MUSIC MU9C1480A-70DC, MU9C1480A-70DI, MU9C1480A-12DC, MU9C1480L-12DI, MU9C1480L-70DC Datasheet

Data Sheet Draft

MU9C1480A/L LANCAMs

APPLICATION BENEFITS

The 1024 x 64-bit LANCAM facilitates numerous
operations:

Ø New package saves space
Ø New speed grade allows processing of both

DA and SA within 560 ns, equivalent to 111,
10 Base-T or 11, 100 Base-T Ethernet ports

Ø Full CAM features allow all operations to

be masked on a bit-by-bit basis

Ø Expanded powerful instruction set for any

list processing needs

Ø Shiftable Comparand and mask registers

assist in proximate matching algorithms

Ø Fully compatible with all MUSIC LANCAM

series, cascadable to any practical length
without performance penalties

®

DISTINCTIVE CHARACTERISTICS

Ø 1024 x 64-bit CMOS content-addressable

memory (CAM)

Ø 16-bit I/O
Ø Fast 90 ns compare speed
Ø Dual configuration register set for rapid context

switching

Ø 16-bit CAM/RAM segments with MUSIC’s patented

partitioning

Ø /MA and /MM output flags to enable faster system

performance

Ø Readable Device ID
Ø Selectable faster operating mode with no wait

states after a no-match

Ø Validity bit setting accessible from the

Status register

Ø Single cycle reset for Segment Control register
Ø 44-Pin PLCC package / 44-Pin TQFP package
Ø 5 Volt (1480A) or 3.3 Volt (1480L) operation

SEGMENT

COUNTER S

DATA (64 )

DEM UX

11

2

DATA (64 )

ODER

ADDRES S DE C

COMPARAND*

MASK 1
MASK 2

CAM ARRAY

1024 WORDS

X 64 BITS

DQ ( 15—0) (16)

/E

CONTROL

/CM

/RESET

/EC

S
R
E
E
F
F
U

B
I/O

16

DATA (16 )

DATA (16 )

COM M ANDS & S TATUS

(16)

INSTRUC TION (W /O )*

ADDRES S/W

ADDRES S

NEX T FREE ADDRESS (R/O)

CONTRO L

SEGM E NT CONTROL

PAG E ADDR ESS (LOCAL)

DEVICE SELECT (GLOBAL)

STATUS (15-0) (R/O)*
STATUS (31-16) (R/O)

REGISTER SET

MUX

TRANS LA TE

802.3/802.5

DATA (16 )

SOU RCE AN D
DES TINATION

10

MATCH ADDR

& /MA FLAG

/MM, /FL

Block Diagram

LANCAM, the MUSIC logo, and the phrase “MUSIC Semiconductors” are registered trademarks of MUSIC Semiconductors. MUSIC is
a trademark of MUSIC Semiconductors. Certain features of this device are patented under US Patent 5,383,146.

Note: This document version has not completed MUSIC’s internal approval process, therefore it should
be rechecked with a released version or with factory personnel.

VCC

GND

/MA

ITY BITS

1K X 2 VALID

PRIORITY ENCODE R

/M M

2

MATCH

AND

FLAG

LOG IC

21 May 1999 Rev. 3.0 Draft

/FF

/FI

/M F

/MI

MU9C1480A/L Draft

GENERAL DESCRIPTION

The MU9C1480A and MU9C1480L LANCAMs are 1024 x
64-bit content-addressable memories (CAMs), with a 16-bit
wide interface. They are pin compatible with all devices in the
MUSIC LANCAM family .

Content-addressable memories, also known as associative
memories, operate in the converse way to random access
memories (RAM). In RAM, the input to the device is an
address and the output is the data stored at that address.
In CAM, the input is a data sample and the output is a flag
to indicate a match and the address of the matching data.
As a result, CAM searches large databases for matching

OPERA TIONAL OVER VIEW

To use the LANCAM, the user loads the data into the
Comparand register, which is automatically compared to all
valid CAM locations. The device then indicates whether
or not one or more of the valid CAM locations contains
data that matches the target data. The status of each CAM
location is determined by two validity bits at each memory
location. The two bits are encoded to render four validity
conditions: Valid, Empty, Skip, and RAM, shown in
Table 1. The memory can be partitioned into CAM and
associated RAM segments on 16-bit boundaries, but by
using one of the two available mask registers, the CAM/RAM
partitioning can be set at any arbitrary size between zero
and 64 bits.

The LANCAM’s internal data path is 64 bits wide for rapid
internal comparison and data movement. V ertical cascading
of additional LANCAMs in a daisy chain fashion extends
the CAM memory depth for large databases. Cascading
requires no external logic. Loading data to the Control,

data in a short, constant time period, no matter how many
entries are in the database. The ability to search data words
up to 64 bits wide allows large address spaces to be
searched rapidly and efficiently. A patented architecture
links each CAM entry to associated data and makes this
data available for use after a successful compare operation.

The MUSIC LANCAMs are ideal for address filtering and
translation applications in LAN switches and routers. The
LANCAMs are also well suited to encryption, database
accelerators, and image processing.

Comparand, and mask registers automatically triggers a
compare. Compares also may be initiated by a command
to the device. Associated RAM data is available
immediately after a successful compare operation. The
Status register reports the results of compares including
all flags and addresses. T wo mask registers are available
and can be used in two different ways: to mask
comparisons or to mask data writes. The RAM validity
type allows additional masks to be stored in the CAM
array where they may be retrieved rapidly.

A simple four-wire control interface and commands
loaded into the Instruction decoder control the device.
A powerful instruction set increases the control flexibility
and minimizes software overhead. Additionally,
dedicated pins for match and multiple-match flags
enhance performance when the device is controlled by a
state machine. These and other features make the
LANCAM a powerful associative memory that drastically
reduces search delays.

Skip Bit

0
0
1
1

Table 1: Entry Types vs. Validity Bits

Rev. 3.0 Draft 2

Empty Bit

0
1
0
1

Entry Type

Valid

Empty

Skip

RAM

/W

LOW

LOW
HIGH
HIGH

/CM

LOW

HIGH

LOW

HIGH

Table 2: I/O Cycles

Cycle Type

Command Write cycle
Data Write cycle
Command Read cycle
Data Read cycle

MU9C1480A/L Draft

PIN DESCRIPTIONS

All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs
should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout
and bypassing techniques. Refer to the Electrical Characteristics section for more information.

/E (Chip Enable, Input, TTL)

The /E input enables the device while LOW. The falling
edge registers the control signals /W, /CM, and /EC. The
rising edge locks the daisy chain, turns off the DQ pins,
and clocks the Destination and Source Segment counters.
The four cycle types enabled by /E are shown in Table 2.

/W (Write Enable, Input, TTL)

The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle and /W HIGH
selects a Read cycle.

/CM (Data/Command Select, Input, TTL)

The /CM input selects whether the input signals on
DQ15–0 are data or commands. /CM LOW selects Command
cycles and /CM HIGH selects Data cycles.

/EC (Enable Daisy Chain, Input, TTL)

The /EC signal performs two functions. The /EC input enables
the /MF output to show the results of a comparison, as shown
in Figure 6 on page 14. If /EC is LOW at the falling edge of /E
in a given cycle, the /MF output is enabled. Otherwise, the
/MF output is held HIGH. The /EC signal also enables the
/MF– /MI daisy chain, which serves to select the device with
the highest-priority match in a string of LANCAMs. Tables 5a

and 5b on page 12 explain the effect of the /EC signal on a
device with or without a match in both Standard and Enhanced
modes. /EC must be HIGH during initialization.

DQ15–0 (Data Bus, I/O, TTL)

The DQ15–0 lines convey data, commands, and status to
and from the LANCAM. /W and /CM control the direction
and nature of the information that flows to or from the
device. When /E is HIGH, DQ15–0 go to HIGH-Z.

/MF (Match Flag, Output, TTL)

The /MF output goes LOW when one or more valid matches
occur during a compare cycle. /MF becomes valid after /E
goes HIGH on the cycle that enables the daisy chain (on
the first cycle that /EC is registered LOW by the previous
falling edge of /E; see Figure 6 on page 14). In a daisy
chain, valid match(es) in higher priority devices are passed
from the /MI input to /MF . If the daisy chain is enabled but
the match flag is disabled in the Control register, the /MF
output only depends on the /MI input of the device
(/MF=/MI). /MF is HIGH if there is no match or when the
daisy chain is disabled (/E goes HIGH when /EC was HIGH
on the previous falling edge of /E). The System Match flag
is the /MF pin of the last device in the daisy chain. /MF will
be reset when the active configuration register set is changed.

GND
DQ4
DQ5
VCC
VCC

TEST2

GND
GND
DQ6
DQ7
VCC

DQ3

VCC

5

6

7
8
9
10
11
12
13
14
15
16
17

19

18

DQ8

GND

PLCC Pinout Diagram

GND

DQ0

DQ2

DQ1

3

4

/CM

/EC

43

44

1

2

44-pin PLCC

(Top View)

25

24

23

22

21

20

DQ13

DQ12

GND

DQ11

DQ10

DQ9

DQ3

7
8
9
10
11
12
13
14
15
16
17

VCC

5

6

19

18

DQ8

GND

/MM

/FF

/FI

40

41

42

/MA

39

/MI

38

/MF

37

GND

36

/RESET

35
34

VCC

33

VCC

32

TES T1

31

/E

30

/W

29

28

27

26

GND

DQ15

DQ14

GND

GND

DQ4
DQ5
VCC
VCC

TEST2

GND
GND

DQ6
DQ7
VCC

GND

DQ0

DQ2

DQ1

3

4

44-pin PLCC

2

/EC

44

1

TQFP

/CM

43

(Top View)

25

24

23

22

21

20

DQ13

DQ12

GND

DQ11

DQ10

DQ9

/MM

/FF

/FI

40

41

42

/MA

39

/MI

38

/MF

37

GND

36

/RESET

35
34

VCC

33

VCC

32

TES T1

31

/E

30

/W

29

28

27

26

GND

DQ15

DQ14

GND

TQFP Pinout Diagram

Rev. 3.0 Draft3

MU9C1480A/L Draft

PIN DESCRIPTIONS

/MI (Match Input, Input, TTL)

The /MI input prioritizes devices in vertically cascaded
systems. It is connected to the /MF output of the previous
device in the daisy chain. The /MI pin on the first device in
the chain must be tied HIGH.

/MA (Device Match Flag, Output, TTL)

The /MA output is LOW when one or more valid matches
occur during the current or the last previous compare cycle.
The /MA output is not qualified by /EC or /MI, and reflects
the match flag from that specific device’s Status register.
/MA will be reset when the active register set is changed.

Continued

/RESET (Reset, Input, TTL)

/RESET must be driven LOW to place the device in a known
state before operation, which will reset the device to the
conditions shown in Table 4 on page 10. LANCAM ‘A’
devices have a hardware reset that operates in parallel with
the internal Power-on-reset circuitry, and sets the device to
the same condition. For compatibility with the MU9C1480,
the /RESET pin has an internal pull-up resistor and may be
left unconnected. The /RESET pin should be driven by
TTL levels, not directly by an RC timeout. /E must be kept
HIGH during /RESET .

/MM (Device Multiple Match Flag, Output, TTL)

The /MM output is LOW when more than one valid match
occurs during the current or the last previous compare cycle.
The /MM output is not qualified by /EC or /MI, and reflects
the multiple match flag from that specific device’s Status
register. /MM will be reset when the active register set is changed.

/FF (Full Flag, Output, TTL)

If enabled in the Control register, the /FF output goes LOW
when no empty memory locations exist within the device
(and in the daisy chain above the device as indicated by
the /FI pin). The System Full flag is the /FF pin of the last
device in the daisy chain, and the Next Free address resides
in the device with /FI LOW and /FF HIGH. If disabled in the
Control register, the /FF output only depends on the /FI
input (/FF = /FI).

/FI (Full Input, Input, TTL)

The /FI input generates a CAM-Memory-System-Full
indication in vertically cascaded systems. It is connected
to the /FF output of the previous device in the daisy chain.
The /FI pin on the first device in a chain must be tied LOW .

FUNCTIONAL DESCRIPTION

TEST1, TEST2 (T est, Input, TTL)

These pins enable MUSIC production test modes that are
not usable in an application. They should be connected to
ground, either directly or through a pull-down resistor, or
they may be left unconnected. These pins may not be
implemented on all versions of these products.

VCC, GND (Positive Power Supply , Ground)

These pins are the power supply connections to the
LANCAM. VCC must meet the voltage supply requirements
in the Operating Conditions section relative to the GND
pins, which are at 0 volts (system reference potential), for
correct operation of the device. All the ground and power
pins must be connected to their respective planes with
adequate bulk and high frequency bypassing capacitors in
close proximity to the device. The MU9C1480A and
MU9C1480L are compatible with the original MU9C1480
connections, and may be operated at -90 or slower
switching characteristics without the GND connections on
pins 1, 7, 18, 23, and 29; and the VCC connections on pins
6, 10, and 17.

The LANCAM is a content-addressable memory (CAM)
with 16-bit I/O for network address filtering and translation,
virtual memory, data compression, caching, and table lookup
applications. The memory consists of static CAM,
organized in 64-bit data fields. Each data field can be
partitioned into a CAM and a RAM subfield on 16-bit
boundaries. The contents of the memory can be randomly
accessed or associatively accessed by the use of a compare.
During automatic comparison cycles, data in the
Comparand register is automatically compared with the
“V alid” entries in the memory array . The Device ID can be
read using a TCO PS instruction (see T able 12 on page 22).

The data inputs and outputs of the LANCAM are
multiplexed for data and instructions over a 16-bit

Rev. 3.0 Draft 4

I/O bus. Internally, data is handled on a 64-bit basis, since
the Comparand register, the mask registers, and each
memory entry are 64 bits wide. Memory entries are globally
configurable into CAM and RAM segments on 16-bit
boundaries, as described in US Patent 5,383,146 assigned
to MUSIC Semiconductors. Seven different CAM/RAM
splits are possible, with the CAM width going from one to
four segments, and the remaining RAM width going from
three to zero segments. Finer resolution on compare width
is possible by invoking a mask register during a compare,
which does global masking on a bit basis. The CAM subfield
contains the associative data, which enters into compares,
while the RAM subfield contains the associated data, which
is not compared. In LAN bridges, the RAM subfield could
hold, for example, port-address and aging information

MU9C1480A/L Draft

FUNCTIONAL DESCRIPTION

related to the destination or source address information
held in the CAM subfield of a given location. In a translation
application, the CAM field could hold the dictionary entries,
while the RAM field holds the translations, with almost
instantaneous response.

Each entry has two validity bits (known as Skip bit and
Empty bit) associated with it to define its particular type:
Empty, Valid, Skip, or RAM. When data is written to the
active Comparand register, and the active Segment Control
register reaches its terminal count, the contents of the
Comparand register are automatically compared with the
CAM portion of all the valid entries in the memory array.
For added versatility, the Comparand register can be
barrel-shifted right or left one bit at a time. A Compare
instruction then can be used to force another compare
between the Comparand register and the CAM portion of
memory entries of any one of the four validity types. After
a Read or Move from Memory operation, the validity bits
of the location read or moved will be copied into the Status
register, where they can be read using Command
Read cycles.
Data can be moved from one of the data registers (CR,
MR1, or MR2) to a memory location that is based on the
results of the last comparison (Highest-Priority Match or
Next Free), or to an absolute address, or to the location
pointed to by the active Address register. Data can also be
written directly to the memory from the DQ bus using any
of the above addressing modes. The Address register may
be directly loaded and may be set to increment or
decrement, allowing DMA-type reading or writing from
memory.

Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background activities.
The currently active set of configuration registers controls
writes, reads, moves, and compares. The foreground set
typically would be pre-loaded with values useful for
comparing input data, often called filtering, while the
background set would be pre-loaded with values useful for
housekeeping activities such as purging old entries.
Moving from the foreground task of filtering to the
background task of purging can be done by issuing a single
instruction to change the current set of configuration
registers. The match condition of the device is reset
whenever the active register set is changed.

Continued

register’s contents are reset, enable or disable Match flag,
enable or disable Full flag, CAM/RAM partitioning, disable
or select masking conditions, disable or select
auto-incrementing or auto-decrementing the Address
register, and select Standard or Enhanced mode. The active
Segment Control register contains separate counters to
control the writing of 16-bit data segments to the selected
persistent destination, and to control the reading of 16-bit
data segments from the selected persistent source.

There are two active mask registers at any one time, which
can be selected to mask comparisons or data writes. Mask
Register 1 has both a foreground and background mode to
support rapid context switching. Mask Register 2 does not
have this mode, but can be shifted left or right one bit at a
time. For masking comparisons, data stored in the active
selected mask register determines which bits of the
comparand are compared against the valid contents of the
memory. If a bit is set HIGH in the mask register , the same
bit position in the Comparand register becomes a “don’t
care” for the purpose of the comparison with all the memory
locations. During a Data Write cycle or a MOV instruction,
data in the specified active mask register can also determine
which bits in the destination will be updated. If a bit is
HIGH in the mask register, the corresponding bit of the
destination is unchanged.

The match line associated with each memory address is fed
into a priority encoder where multiple responses are
resolved, and the address of the highest-priority responder
(the lowest numerical match address) is generated. In LAN
applications, a multiple response might indicate an error. In
other applications the existence of multiple responders may
be valid.

Four input control signals and commands loaded into an
instruction decoder control the LANCAM. T wo of the four
input control signals determine the cycle type. The control
signals tell the device whether the data on the I/O bus
represents data or a command, and is input or output.
Commands are decoded by instruction logic and control
moves, forced compares, validity bit manipulations, and
the data path within the device. Registers (Control, Segment
Control, Address, Next Free Address, etc.) are accessed
using Temporary Command Override instructions. The data
path from the DQ bus to/from data resources (comparand,
masks, and memory) within the device are set until changed
by Select Persistent Source and Destination instructions.

The active Control register determines the operating
conditions within the device. Conditions set by this

After a Compare cycle (caused by either a data write to the
Comparand or mask registers, a write to the Control register,

Rev. 3.0 Draft5

MU9C1480A/L Draft

FUNCTIONAL DESCRIPTION

or a forced compare), the Status register contains the
address of the Highest-Priority Matching location in that
device, concatenated with its page address, along with
flags indicating internal match, multiple match, and full.
When the Status register is read with a Command Read
cycle, the device with the Highest-Priority Match will
respond, outputting the System Match address to the DQ
bus. The internal Match (/MA) and Multiple Match (/MM)
flags are also output on pins. Another set of flags (/MF
and /FF) that are qualified by the match and full flags of
previous devices in the system also are available directly
on output pins, and are independently daisy-chained to
provide System Match and Full flags in vertically cascaded
LANCAM arrays. In such arrays, if no match occurs during
a comparison, read access to the memory and all the
registers except the Next Free register is denied to prevent
device contention. In a daisy chain, all devices will respond
to Command and Data Write cycles, depending on the
conditions shown in Tables 5a and 5b on page 12, unless
the operation involves the Highest-Priority Match address
or the Next Free address; in which case, only the specific
device having the Highest-Priority match or the Next Free
address will respond.

Continued

A Page Address register in each device simplifies vertical
expansion in systems using more than one LANCAM. This
register is loaded with a specific device address during
system initialization, which then serves as the higher-order
address bits. A Device Select register allows the user to
target a specific device within a vertically cascaded system
by setting it equal to the Page Address Register value, or
to address all the devices in a string at the same time by
setting the Device Select value to FFFFH.

Figure 1a shows expansion using a daisy chain. Note that
system flags are generated without the need for external
logic. The Page Address register allows each device in the
vertically cascaded chain to supply its own address in the
event of a match, eliminating the need for an external priority
encoder to calculate the complete Match address at the
expense of the ripple-through time to resolve the Highest­Priority match. The Full flag daisy-chaining allows
Associative writes using a Move to Next Free Address
instruction, which does not need a supplied address.

Figure 1b shows an external PLD implementation of a simple
priority encoder that eliminates the daisy chain ripple­through delays for systems requiring maximum performance
from many CAMs.

OPERATIONAL CHARACTERISTICS

Throughout the following, “aaaH” represents a three-digit
hexadecimal number “aaa,” while “bbB” represents a two­digit binary number “bb.” All memory locations are written
to or read from in 16-bit segments. Segment 0 corresponds to
the lowest order bits (bits 15–0) and Segment 3 corresponds
to the highest order bits (bits 63–48).

THE CONTROL BUS

Refer to the Block Diagram on page 1 for the following
discussion. The inputs Chip Enable (/E), Write Enable (/W),
Command Enable (/CM), and Enable Daisy Chain (/EC) are
the primary control mechanism for the LANCAM. The /EC
input of the Control bus enables the /MF Match flag output
when LOW and controls the daisy chain operation.
Instructions are the secondary control mechanism. Logical
combinations of the Control Bus inputs, coupled with the
execution of Select Persistent Source (SPS), Select Persistent
Destination (SPD), and Temporary Command Override
(TCO) instructions allow the I/O operations to and from
the DQ15–0 lines to the internal resources, as shown in
T able 3 on page 9.

The Comparand register is the default source and
destination for Data Read and Write cycles. This default
state can be overridden independently by executing a Select
Persistent Source or Select Persistent Destination
instruction, selecting a different source or destination for
data. Subsequent Data Read or Data Write cycles will
access that source or destination until another SPS or SPD
instruction is executed. The currently selected persistent
source or destination can be read back through a TCO PS
or PD instruction. The sources and destinations available
for persistent access are those resources on the 64-bit bus:
Comparand register, Mask Register 1, Mask Register 2, and
the Memory array.

The default destination for Command Write cycles is the
Instruction decoder, while the default source for Command
Read cycles is the Status register.

T emporary Command Override (TCO) instructions provide
access to the Control register, the Page Address register,
the Segment Control register, the Address register , the Next
Free Address register, and Device Select register. TCO

Rev. 3.0 Draft 6

MU9C1480A/L Draft

OPERATIONAL CHARACTERISTICS

instructions are active only for one Command Read or
Write cycle after being loaded into the Instruction decoder .

The data and control interfaces to the LANCAM are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When writing
to the persistently selected data destination, the
Destination Segment counter is clocked by the rising edge
of /E. During a Read cycle, the Control inputs are registered
by the falling edge of /E, and the Data outputs are enabled
while /E is LOW. When reading from the persistently
selected data source, the Source Segment counter is
clocked by the rising edge of /E.

THE REGISTER SET

The Control, Segment Control, Address, Mask Register 1,
and the Persistent Source and Destination registers are
duplicated, with one set termed the Foreground set and
the other the Background set. The active set is chosen by
issuing Select Foreground Registers or Select Background
Registers instructions. By default, the Foreground set is
active after a reset. Having two alternate sets of registers
that determine the device configuration allows for a rapid

Continued

return to a foreground network filtering task from a
background housekeeping task.

Writing a value to the Control register or writing data to the
last segment of the Comparand or either mask register will
cause an automatic comparison to occur between the
contents of the Comparand register and the words in the
CAM segments of the memory marked valid, masked by
MR1 or MR2 if selected in the Control register.

Instruction Decoder

The Instruction decoder is the write-only decode logic for
instructions and is the default destination for Command
Write cycles. If an instruction’ s Address Field flag (bit 1 1)
is set to a 1, it is a two-cycle instruction that is not executed
immediately. For the next cycle only, the data from a
Command Write cycle is loaded into the Address register
and the instruction then completes at that address. The
Address register will then increment, decrement, or stay at
the same value depending on the setting of Control Register
bits CT3 and CT2. If the Address Field flag is not set, the
memory access occurs at the address currently contained
in the Address register.

DQ 15–0

/E

/W
/CM
/EC

Vcc

16

DQ 15–0
/E
/W
/CM
/EC

DQ 15–0
/E
/W
/CM
/EC

DQ 15–0
/E
/W
/CM
/EC

LANC AM

LANC AM

LANC AM

/MI

/FI

/FF

/MF

/MI

/FI

/FF

/MF

/MI

/FI

/FF

/MF

Vcc

SYSTEM FU LL

SYSTE M MATCH

LANCAM

LANCAM

LANCAM

LANCAM

/MA

/MA

/MA

/MA

/MI

/MI

/MI

/MI

PLD

Figure 1a: Vertical Cascading Figure 1b: External Prioritizing

SYSTEM

MATCH

Rev. 3.0 Draft7

MU9C1480A/L Draft

OPERATIONAL CHARACTERISTICS

Control Register (CT)

The Control register contains a number of switches that
configure the LANCAM, as shown in T able 8 on page 21. It
is written or read using a TCO CT instruction. If bit 15 of
the value written during a TCO CT is a 0, the device is reset
(and all other bits are ignored). See Table 4 on page 10 for
the Reset states. Bit 15 always reads back as a 0. A write to
the Control register causes an automatic compare to occur
(except in the case of a reset). Either the Foreground or
Background Control register will be active, depending on
which register set has been selected, and only the active
Control register will be written to or read from.

If the Match Flag is disabled through bit 14 and bit 13, the
internal match condition, /MA(int), used to determine a
daisy-chained device’s response is forced HIGH as shown
in Tables 5a and 5b on page 12, so that Case 6 is not
possible, effectively removing the device from the daisy
chain. With the Match Flag disabled, /MF=/MI and
operations directed to Highest-Priority Match locations are
ignored. Normal operation of the device is with the /MF
enabled. The Match Flag Enable field has no effect on the
/MA or /MM output pins or Status Register bits. These
bits always reflect the true state of the device.

If the Full Flag is disabled through bit 12 and bit 11, the
device behaves as if it is full and ignores instructions to
Next Free address. Also, writes to the Page Address register
are disabled. All other instructions operate normally.
Additionally, with the /FF disabled, /FF=/FI. Normal
operation of the device is with the /FF enabled. The Full
Flag Enable field has no effect on the /FL Status Register
bit. This bit always reflects the true state of the device.

The IEEE Translation control at bit 10 and bit 9 can be used
to enable the translation hardware for writes to 64-bit
resources in the device. When translation is enabled, the
bits are reordered as shown in Figure 2.

DQ15 DQ8 DQ7 DQ0

DQ15 DQ8 DQ7 DQ0

Continued

Control Register bits 8–6 control the CAM/RAM
partitioning. The CAM portion of each word may be sized
from a full 64 bits down to 16 bits in 16-bit increments. The
RAM portion can be at either end of the 64-bit word.

Compare masks may be selected by bit 5 and bit 4. Mask
Register 1, Mask Register 2, or neither may be selected to
mask compare operations. The address register behavior is
controlled by bit 3 and bit 2, and may be set to increment,
decrement, or neither after a memory access. Bit 1 and bit 0
set the operating mode: Standard as shown in Table 5a on
page 12, or Enhanced as shown in T able 5b on page 12. The
device will reset to the Standard mode, and follow the
operating responses of the original MU9C1480 in T able 5a.
When operating in Enhanced mode, it is not necessary to
unlock the daisy chain with a NOP instruction before
command or data writes after a non-matching compare, as
required in Standard mode.

Segment Control Register (SC)

The Segment Control register, as shown in T able 9 on page
22, is accessed using a TCO SC instruction. On read cycles,
D15, D10, D5, and D2 always will read back as 0s. Either the
Foreground or Background Segment Control register will
be active, depending on which register set has been
selected, and only the active Segment Control register will
be written to or read from.

The Segment Control register contains dual independent
incrementing counters with limits, one for data reads and
one for data writes. These counters control which 16-bit
segment of the 64-bit internal resource is accessed during
a particular data cycle on the 16-bit data bus. The actual
destination for data writes and source for data reads (called
the persistent destination and source) are set independently
with SPD and SPS instructions, respectively.

Each of the two counters consists of a start limit, an end
limit, and the current count value that points to the segment
to be accessed on the next data cycle. The current count
value can be set to any segment, even if it is outside the
range set by the start and end limits. The counters count
up from the current count value to the end limit and then
jump back to the start limit. If the current count is
greater than the end limit, the current count value will
increment to three, then roll over to zero and continue
incrementing until the end limit is reached; it then jumps
back to the start limit.

Figure 2: IEEE 802.3/802.5 Format Mapping

Rev. 3.0 Draft 8

If a sequence of data writes or reads is interrupted, the
Segment Control register can be reset to its initial start limit

MU9C1480A/L Draft

values by using an RSC instruction. After the
LANCAM is reset, both Source and Destination counters
are set to count from Segment 0 to Segment 3 with an initial
value of 0.

Page Address Register (PA)

The Page Address register is loaded using a TCO PA
instruction followed by a Command Write cycle of a user
selected 16-bit value (not FFFFH). The entry in the PA
register is used to give a unique address to the different
devices in a daisy chain. In a daisy chain, the PA value of
each device is loaded using the SFF instruction to advance
to the next device, shown in the “Setting Page Address
Register Values” section on page 15. A software reset
(using the Control register) does not affect the Page
Address register.

Device Select Register (DS)

The Device Select register is used to select a specific (target)
device. The TCO DS instruction sets the 16-bit DS register
to the value of the following Command Write cycle. The DS
register can be read. A device is selected when its DS is
equal to its P A value. In a daisy chain, setting DS = FFFFH
will select all devices. However, in this case, the ability to
read information out of the device is restricted as shown in
Tables 5a and 5b on page 12. A software reset (using the
Control register) does not affect the Device Select register .

Address Register (AR)

The Address register points to the CAM memory location
to be operated upon when M@[AR] or M@aaaH is part of
the instruction. It can be loaded directly by using a TCO
AR instruction or indirectly by using an instruction requiring
an absolute address, such as MOV aaaH,CR,V . After being
loaded, the Address register value will then be used for the
next memory access referencing the Address register. A
reset sets the Address register to zero.

Control Register bits CT3 and CT2 set the Address register
to automatically increment or decrement (or not change)
during sequences of Command or Data cycles. The Address
register will change after executing an instruction that
includes M@[AR] or M@aaaH, or after a data access to
the end limit segment (as set in the Segment Control
register) when the persistent source or destination is
M@[AR] or M@aaaH.

Either the Foreground or Background Address register will
be active, depending on which register set has been
selected, and only the active Address register will be written
to or read from.

Next Free Address Register (NF)

The LANCAM automatically stores the address of the first
empty memory location in the Next Free Address register,
which is then used as a memory address pointer for M@NF
operations. The Next Free Address register, shown in T able
10 on page 22, can be read using a TCO NF instruction. By
taking /EC LOW during the TCO NF instruction cycle, only
the device with /FI LOW and /FF HIGH will output the
contents of its Next Free Address register, which gives the
Next Free address in a system of daisy-chained devices.
The Next Free address may be read from a specific device
in the chain by setting the Device Select register to the
value of the desired device’s Page address and leaving
/EC HIGH.

The Full Flag daisy chain causes only the device whose /FI
input is LOW and /FF output HIGH to respond to an
instruction using the Next Free address. After a reset, the
Next Free Address register is set to zero.

Status Register

The 32-bit Status register, shown in T able 1 1 on page 22, is
the default source for Command Read cycles. Bit 31 is the
internal Full flag, which will go LOW if the particular device
has no empty memory locations. Bit 30 is the internal
Multiple Match flag, which will go LOW if a Multiple match
was detected. Bit 29 and Bit 28 are the Skip and Empty
Validity bits, which reflect the validity of the last memory
location read. After a reset, the Skip and Empty bits will
read 11 until a read or move from memory has occurred.
The rest of the Status register down to bit 1 contains the
Page address of the device and the address of the Highest­Priority match. After a reset or a no-match condition, the
match address bits will be all 1s. Bit 0 is the internal Match
flag, which will go LOW if a match was found in this
particular device.

Comparand Register (CR)

The 64-bit Comparand register is the default destination
for data writes and reads, using the Segment Control register
to select which 16-bit segment of the Comparand register is
to be loaded or read out. The persistent source and
destination for data writes and reads can be changed to the
mask registers or memory by SPS and SPD instructions.
During an automatic or forced compare, the Comparand
register is simultaneously compared against the CAM
portion of all memory locations with the correct validity
condition. Automatic compares always compare against
valid memory locations, while forced compares, using CMP
instructions, can compare against memory locations tagged
with any specific validity condition.

Rev. 3.0 Draft9