Murata Electronics North America DRWLS1271L User Manual

Preliminary and RFM Confidential

DR-WLS1271L-102

FCC/IC Certified

WLAN/Bluetooth

Multifunction Module

Data Sheet

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Scope

This specification applies to the IEEE802.11b/g/n WLAN and Bluetooth 4.0 standards.

Interfaces

WLAN: SDIO Bluetooth: UART and PCM

IC and Firmware

WLAN/BT BB/MAC IC: TI WL1271L (PG 3.1) Front-end IC for WL1271L: TriQuint TQM679002A (E 2.6)

Clocks and Compliance

Sleep Clock: External 32.768 kHz oscillator required RoHS: This module is compliant with the RoHS directive Bluetooth: Qualified Design Listing: B017989 Certifications: FCC, and Industry Canada (IC)

For mobile operating conditions (greater than 20 cm to the body) - This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator and your body. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.

For portable operating conditions (less than 20 cm to the body) - This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment may operate in direct contact with the body of the user under normal operating conditions. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.

Certification testing conducted with Antenna Factor ANT-RAF-RPS 2.4/5 GHz antenna, RSMA connector.

Part Numbers

Module: DR-WLS1271L-102

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Block Diagram

Preliminary and RFM Confidential

3 8 . 4 M H z F a s t C L K

S l o w C L K

S D I O

2 . 4 G H z W L A N / B T

F r o n t E n d I C a n d R F

W L 1 2 7 1 L

P C M

U A R T

V I O

F i l t e r i n g

D C - D C

C o n v e r t e r

D u a l

R e g

V I N

DR-WLS1271L-102 WLAN Features

• WLAN MAC baseband processor and RF transceiver which are IEEE802.11b/g and IEEE802.11n PICS compliant

• Optimized for ultra-low current consumption in all operating modes

• Accepts 19.2, 26, 38.4, 52 MHz reference clock inputs for easy integration into cellular handsets, etc.

• IEEE Standard 802.11d, e, h, i, k, r, PICS compliant

• Support for Cisco Client eXtensions (CCX) standard

• Serial debug interface

• Secure Digital Input/Output (SDIO) host interface

• Medium Access Controller (MAC) – Embedded ARM™ central processing unit (CPU) – Hardware-based encryption/decryption using 64-, 128- or 256-bit WEP, TKIP or AES keys – Supports Wi-Fi protected access (WPA and WPA2.0) and IEEE Standard 802.11i, including hardware accelerated Advanced Encryption Standard (AES)] – Designed to work with IEEE Std 802.1x for Virtual Private Network (VPN) solutions

• Baseband Processor – IEEE Std 802.11n single-stream data rates (MCS0-7) and SGI support

• 2.4 GHz Radio – Digital Radio Processor (DRP) implementation – Integrated LNA – Supports IEEE Std 802.11b, g, b/g and 802.11n

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DR-WLS1271L-102 Bluetooth Features

• V4.0 + EDR, Power Class 1.5 + BLE

• Bluetooth Qualified Design Listing: B017988

• BT Enhanced Data Rates - 2 and 3 Mbps

• Enhanced UART host interface

• Very low power consumption

• On-chip Embedded radio – Integrated 2.4 GHz RF transceiver – All digital PLL transmitter with digitally controlled oscillator – Near-zero IF architecture – On-chip TX/RX switch – Support for Class-1.5 applications

• Embedded ARM microprocessor system – High rate four wire UART HCI (H4) and three wire UART HCI (H5) – Automatic clock-detection mechanism

• Flexible PCM interface - full flexibility for data order, sampling and positioning

• Temperature detection and compensation mechanism ensures minimal variation in the RF performance over the entire operating temperature range

• Low-power scan achieves paging and inquiry scans at 1/3 normal power

• Digital Radio Processor (DRP) single-ended 50 ohm I/O for easy RF interfacing

• Patch trap mechanism and reserved RAM enables easy bug fixes

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• Advance Audio Interfaces and capabilities – A2DP support – A2DP internal loopback – Wide-band speech support – On board SBC encoder/decoder - offloads host for A2DP and wide-band speech processing – Full support for Bluetooth low energy (BLE) standard. BLE can operate in parallel with standard Bluetooth function.

WLAN Functional Blocks

The DR-WLS1271L-102 WLAN architecture includes a digital radio processor and a point-to-multipoint baseband core function. The architecture is based on a single-processor ARM core. The device includes on-chip peripherals to enable easy communication between a host system and the WLAN core function.

WLAN SDIO Transport Layer

SDIO is the WLAN host interface in the DR-WLS1271L-102. This interface is a standard SDIO interface (SDIO Version 2.0), supporting a maximum clock rate of 26 MHz. The DR-WLS1271L-102 SDIO also supports the following features:

• 4-bit data bus

• Functions number 0 and 2

• Multi-Block data transfer

• The SDIO interface is used for WLAN. The WLAN block uses function 2. Function 0 is used for the common I/O area.

WLAN MAC

The DR-WLS1271L-102 MAC implements the IEEE standard 802.11 MAC sub-layer using both dedicated hardware and embedded firmware. The MAC hardware implements real-time functions, including access protocol management, encryption and decryption.

WLAN Baseband Processor

The DR-WLS1271L-102 baseband processor sits between the on-chip MAC and the radio. The DRWLS1271L-102 baseband processor implements the IEEE 802.11b/g/n PHY sub-layers and has been optimized to perform well in conditions of high multipath and noise.

WLAN RF Radio

The DR-WLS1271L-102 radio is a highly integrated Digital Radio Processor (DRP) designed for

802.11b/g/n applications. The DR-WLS1271L-102 RF interface is a single-band RF front end for 2.4 GHz

802.11b/g/n applications.

BT Functional Blocks

The DR-WLS1271L-102 BT architecture comprises a digital radio processor and a point-to-multipoint baseband core function. The architecture is based on a single-processor ARM core. The device includes on-chip peripherals to enable easy communication between a host system and the Bluetooth core function.

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Preliminary and RFM Confidential

BT HCI UART Transport Layers

The DR-WLS1271L-102 incorporates one UART module dedicated to the Host Controller Interface (HCI) transport layer. The HCI interface is used to transport commands, events, ACL and data between the Bluetooth device and its host using HCI data packets. The DR-WLS1271L-102 supports the following HCI transport layers, detected automatically when communication starts:

• UART transport layer - HCI four-wire (H4) and HCI three-wire (H5)

• HCI interface has a 256 byte receive buffer

The HCI UART supports most baud rates (including all PC rates) up to a maximum of 4 Mbps. After power-up, the baud rate is set for 115.2 kbps. The maximum baud rate deviation supported is -2.5%, +1.5%. The baud rate can thereafter be changed with a VS command. The DR-WLS1271L-102 responds with a Command Complete Event (still at 115.2 kbps), after which the baud rate change takes place. The only parameter needed is the desired baud rate. HCI hardware includes the following features:

• Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions

• Transmitter underflow detection

• CTR/RTS hardware flow control

BT UART 4-Wire Interface - H4

The interface includes four signals: TXD, RXD, CTS and RTS. Flow control between the host and the DR-WLS1271L-102 is byte-wise by hardware. Flow control is obtained by the following:

H O S T _ R X

H o s t

P r o c e s s o r

H O S T T X

H O S T _ C T S

H O S T _ R T S

When the UART RX buffer of the DR-WLS1271L-102 passes the “flow control” threshold, it sets the UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high, the DR-WLS1271L-102 stops transmitting on the interface. In case HCI_CTS is set high in the middle of transmitting a byte, the DR-WLS1271L-102 finishes transmitting the byte and stops the transmission.

H C I _ R X

H C I _ T X

H C I _ C T S

H C I _ R T S

D R - W L S 1 2 7 1 L - 1 0 2

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BT UART 3-Wire Interface - H5

This interface consists of three signals: TXD, RXD and GND:

HCI_RX Receive Data on the UART Interface HCI_TX Transmit Data on the UART Interface GND Ground

XON/XOFF software flow control is normally used.

The DR-WLS1271L-102 also supports a four-wire mode for H5, with RTS/CTS hardware flow control. Since the same UART module is used for the 3- and 4-wire HCI UART interface, all features supported by the 4-wire interface are also supported for the 3-wire interface. H5 features:

• Flow control configured with HCI_VS command, software XON/XOFF, hardware (RTS/CTS), or none

• Power management

• Configurable timers for re-transmission management

• CRC

BT Audio CODEC Interface

The CODEC interface is a fully dedicated programmable serial port that provides the logic to interface to several kinds of PCM codecs. The interface supports:

• Two voice channels

• Master/slave modes

• Coding schemes: μ-Law, A-Law, Linear, Transparent

• Long & short frames

• Different data widths, orders and positions

• UDI profile

• High rate PCM interface for EDR

• Enlarged interface options to support a wider variety of codecs

• PCM bus sharing

PCM Hardware Interface

The PCM interface is one implementation of the codec interface. It contains the following four lines:

• Clock - configurable direction (input or output)

• Frame Sync - configurable direction (input or output)

• Data In - Input

• Data Out - Output/Hi-Z

The DR-WLS1271L-102 device can be either the master of the interface where it generates the clock and the frame-sync signals, or slave where it receives these two signals. The PCM interface is fully configured by means of a VS command. For slave mode, clock input frequencies of up to 16 MHz are supported. At clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the DR-WLS1271L102 can generate any clock frequency between 64 kHz and 4.096 MHz.

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Data Format

The data format is fully configurable:

• The data length can be from 8 to 320 bits, in 1-bit increments, when working with two channels, or up to 640 bits when using 1 channel. The data length can be set independently for each channel.

• The data position within a frame is also configurable with 1-clock (bit) resolution, and can be set independently (relative to the edge of the Frame Sync signal) for each channel.

• The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start with MSB while Data_Out starts with LSB. Each channel is separately configurable. The inverse bit order (i.e. LSB first) is supported only for sample sizes up to 24 bits.

• The data in and data out size do not necessarily have to be the same length.

• The Data_Out line is configured as a ‘high-Z’ output between data words. Data_Out can also be set for permanent high-Z, irrespective of data out. This allows the DR-WLS1271L-102 to be a bus slave in a multi-slave PCM environment. At power up, Data_Out is configured as high-Z.

Frame-Idle Period

The CODEC interface has the capability for frame-idle periods, where the PCM clock can “take a break” and become ‘0’ at the end of the PCM frame, after all data has been transferred. The DR-WLS1271L-102 supports frame-idle periods both as master and slave of the PCM bus. When DR-WLS1271L-102 is the master of the interface, the frame-idle period is configurable. There are 2 configurable parameters:

• Clk_Idle_Start - indicates the number of PCM clock cycles from the beginning of the frame till the beginning of the idle period. After Clk_Idle_Start clock cycles, the clock becomes ‘0’.

• Clk_Idle_End - indicates the time from the beginning of the frame till the end of the idle period. This time is given in multiples of PCM clock periods. The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period, e.g., for PCM clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90. Between each two-frame sync there are 70 clock cycles (instead of 100). The clock idle period starts 60 clock cycles after the beginning of the frame and lasts 90-60=30 clock cycles. This means that the idle period ends 100-90=10 clock cycles before the end of the frame. The data transmission must end prior to the beginning of the idle period.

Audio Encoding

The DR-WLS1271L-102 CODEC interface can use one of four audio coding patterns:

• A-Law (8-bit)

• m-Law (8-bit)

• Linear (8 or 16-bit)

• Transparent

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Mechanical

Preliminary and RFM Confidential

D R - W L S 1 2 7 1 L - 1 0 2 P a c k a g e D r a w i n g

2 . 4 G H z

0 . 5 0 ( 1 . 3 )

0 . 2 6 9

( 6 . 8 )

0 . 1 0 4

( 2 . 7 )

0 . 3 8 0

( 9 . 7 )

0 . 0 8 0

( 2 . 0 )

0 . 1 2 0

( 3 . 0 )

0 . 7 3 2 ( 1 8 . 6 )

T o p

0 . 0 8 0

( 2 . 0 )

0 . 1 6 0

( 4 . 1 )

0 . 0 3 0

0 . 0 4 0

( 1 . 0 )

( 0 . 8 )

S i d e

0 . 1 5 ( 3 . 8 )

M a x i m u m H e i g h t

0 . 0 4 0

( 1 . 0 )

0 . 5 5 6 ( 1 4 . 1 )

0 . 0 3 0

( 0 . 8 )

V i e w f r o m T o p

D i m e n s i o n s i n i n c h e s ( m m )

0 . 5 2 9 ( 1 3 . 4 )

0 . 4 6 9 ( 1 1 . 9 )

0 . 0 3 0

( 0 . 8 )

0 . 1 2 0

( 3 . 0 )

4 2

5 0

B o t t o m

0 . 0 8 0

( 2 . 0 )

0 . 0 2 8

( 0 . 7 )

2 6

2 7

2 8

0 . 0 2 8

1 4

( 0 . 7 )

1 5

1 6

0 . 0 9 2

( 2 . 3 )

4 1

4 0

5 1

5 2

2

1

0 . 0 3 0

( 0 . 8 )

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Murata Electronics North America DRWLS1271L User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual