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MS-V353
Schematics
21 pgs2.67 Mb0

MSI MS-V353 Schematics

This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
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Advanced Micro Devices
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6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
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REV:
SHEET NUMBER:
DOCUMENT NUMBER:
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prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
OUT
OUTININININININININININININININININ
Mechanical Key
PERn0
GND
PRSNT2_B48
GND
PETn7
PETp7
GND
GND
PETn6
PETp6
GND
GND
PETn5
PETp5
GND
GND
PETn4
PETp4
GND
GND
PETn3
PETp3
GND
GND
PETn2
PETp2
GND
GND
PETn1
PETp1
GND
GND
PETn0
PETp0
GND
+3.3V
GND
SMDAT
SMCLK
GND
+12V
+12V
+12V
GND
PERn7
PERp7
GND
GND
PERn6
PERp6
GND
GND
PERn5
PERp5
GND
GND
PERn4
PERp4
GND
GND
PERn3
PERp3
GND
GND
PERn2
PERp2
GND
GND
PERn1
PERp1
GND
GND
PERp0
GND
REFCLK-
REFCLK+
GND
PERST_
+3.3V
+3.3V
JTAG4
JTAG3
GND
+12V
+12V
PRSNT1_A1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIININOUT
C
VCC
Y
A
GND
B
8
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017091101 RMA工程課
石阿鋒 (00068760)
7
6
345
2
1
PCI-EXPRESS EDGE CONNECTOR
PCI-EXPRESS EDGE CONNECTOR
+1.8V
+1.8V
PRESENCE
PRESENCE
+12V_BUS
+12V_BUS
+3.3V_BUS
+3.3V_BUS
1
1
JTDIO_LOOP
JTDIO_LOOP
PCIE_REFCLKP
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_REFCLKN PERP0
PERP0
PERN0
PERN0
PERP1
PERP1
PERN1
PERN1
PERP2
PERP2
PERN2
PERN2
PERP3
PERP3
PERN3
PERN3
PERP4
PERP4
PERN4
PERN4
PERP5
PERP5
PERN5
PERN5
PERP6
PERP6
PERN6
PERN6
PERP7
PERP7
PERN7
PERN7
+12V_BUS+3.3V_BUS
+12V_BUS+3.3V_BUS
+3.3V_BUS
+3.3V_BUS
SMBCLK
IN
BI
SMBCLK
SMBDATA
SMBDATA
5
5
5
5
C
Place these caps as close to the PCIE
Place these caps as close to the PCIE
connector as possible
connector as possible
(1206)1.8MM H MAX
(1206)1.8MM H MAX
+12V_BUS
+12V_BUS
1
+12V_BUS
1
+12V_BUS
C1001
C1001
10uF
10uF
16V
16V
2 1
2 1
R1
45.3K
45.3K
1%
1%
2 1
2 1
+3.3V_BUS
+3.3V_BUS
R2
R2R1
45.3K
45.3K
1%
1%
2 1
2 1
MPCIE1
B1
B1
+12V
B2
B2
+12V
B3
B3
+12V
B4
B4
GND
B5
B5
SMCLK
B6
B6
SMDAT
B7
B7
GND
B8
B8
+3.3V
B13
B13
GND
B14
PETP0_GFXRP0
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
1
1
PETP0_GFXRP0
PETN0_GFXRN0
PETN0_GFXRN0
PETP1_GFXRP1
PETP1_GFXRP1
PETN1_GFXRN1
PETN1_GFXRN1
PETP2_GFXRP2
PETP2_GFXRP2
PETN2_GFXRN2
PETN2_GFXRN2
PETP3_GFXRP3
PETP3_GFXRP3
PETN3_GFXRN3
PETN3_GFXRN3
PETP4_GFXRP4
PETP4_GFXRP4
PETN4_GFXRN4
PETN4_GFXRN4
PETP5_GFXRP5
PETP5_GFXRP5
PETN5_GFXRN5
PETN5_GFXRN5
PETP6_GFXRP6
PETP6_GFXRP6
PETN6_GFXRN6
PETN6_GFXRN6
PETP7_GFXRP7
PETP7_GFXRP7
PETN7_GFXRN7
PETN7_GFXRN7 PRESENCE
PRESENCE
B14 B15
B15 B16
B16 B18
B18 B19
B19 B20
B20 B21
B21 B22
B22 B23
B23 B24
B24 B25
B25 B26
B26 B27
B27 B28
B28 B29
B29
B32
B32 B33
B33 B34
B34 B35
B35 B36
B36 B37
B37 B38
B38 B39
B39 B40
B40 B41
B41 B42
B42 B43
B43 B44
B44 B45
B45 B46
B46 B47
B47 B48
B48 B49
B49
PETp0 PETn0 GND
GND PETp1 PETn1 GND GND PETp2 PETn2 GND GND PETp3 PETn3 GND
GND PETp4 PETn4 GND GND PETp5 PETn5 GND GND PETp6 PETn6 GND GND PETp7 PETn7 GND PRSNT2_B48 GND
MPCIE1
Mechanical Key
PRSNT1_A1
+12V +12V
GND
JTAG3 JTAG4
+3.3V +3.3V
PERST_
GND REFCLK+ REFCLK-
GND
PERp0 PERn0
GND
GND
PERp1 PERn1
GND
GND
PERp2 PERn2
GND
GND
PERp3 PERn3
GND
GND
PERp4 PERn4
GND
GND
PERp5 PERn5
GND
GND
PERp6 PERn6
GND
GND
PERp7 PERn7
GND
A1
A1 A2
A2 A3
A3 A4
A4 A6
A6 A7
A7 A9
A9 A10
A10 A11
A11 A12
A12 A13
A13 A14
A14 A15
A15 A16
A16 A17
A17 A18
A18 A20
A20 A21
A21 A22
A22 A23
A23 A24
A24 A25
A25 A26
A26 A27
A27 A28
A28 A29
A29 A30
A30 A31
A31
A34
A34 A35
A35 A36
A36 A37
A37 A38
A38 A39
A39 A40
A40 A41
A41 A42
A42 A43
A43 A44
A44 A45
A45 A46
A46 A47
A47 A48
A48 A49
A49
R3
R3 10K
10K
1%
1%
DNI
DNI
2 1
2 1
1.8V_IN
1.8V_IN
R4
R4 10K
10K
DNI
DNI
2 1
2 1
15 14
15 14
IN
OUT OUT
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
2
2
+3.3V_BUS
+3.3V_BUS
2 11 6
2 1
1 6
+1.8V_EN
+1.8V_EN
2
2 2
2 2
2 2
2
2
2 2
2
2
2 2
2
2
2 2
2
2
2 2
2
2
2 2
2
2
2 2
2
2
2 2
2
R50
R50 10K
10K
1%
1%
DNI
DNI
Q1
Q1 MMDT3904-7
MMDT3904-7
DNI
DNI
PWR_IN
PWR_IN
R23
C50
C50
0.1uF
0.1uF
10V
10V
2 1
2 1
DNI
DNI
PWR_RST
PWR_RST
5
5
Q1
Q1 MMDT3904-7
MMDT3904-7
DNI
DNI
4 3
4 3
0R
0R
21R23
21
PERST#
PERST#
+3.3V_BUS
+3.3V_BUS
21
21
10K
10K
R1005
R1005
DNI
DNI
U4
U4
3
3
A
1
1
B C
74AUP1G57GM
74AUP1G57GM
R1007
Place R1007 in U4
Place R1007 in U4
+3.3V_BUS
+3.3V_BUS
VCC
Y
GND
21R1007
21
6.3V
0.1uF
0.1uF
6.3V
PERST#_BUF
PERST#_BUF
OUT
2 16
2 16
5
C1011
5 4
4 26
26
0RDNI
0RDNI
21C1011
21
DD
C
A
+12V_BUS
+12V_BUS
1
+12V_BUS
1
+12V_BUS
C1002
0.15uF
0.15uF
16V
16V
2 1
2 12 1
+3.3V_BUS
+3.3V_BUS
+3.3V_BUS
1
+3.3V_BUS
1
C1004
C1004 10uF
10uF
6.3V
6.3V
2 1
+3.3V_BUS
+3.3V_BUS
1
+3.3V_BUS
1
+3.3V_BUS
C1005
C1005
0.1uF
0.1uF
6.3V
6.3V
2 1
2 1
+12V_BUS
+12V_BUS
+12V_BUS
1
+12V_BUS
1
C1008
C1008
0.1uF
0.1uF
16V
16V
2 1
2 1
2 1
2 1
8
C1003
C1003C1002
0.15uF
0.15uF
16V
16V
2 1
2 1
CAP CER 10UF 10% 6.3V X5R
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
(0805)1.4MM MAX THICK
21
21
C1006
1uF
1uF
6.3V
C1009
0.1uF
0.1uF
16V
16V
6.3V
2 1
2 1
C1010
C1010C1009
0.1uF
0.1uF
16V
16V
2 1
2 1
7
C1007
C1007C1006
0.01uF
0.01uF
10V
10V
6
x8 PCIe
x8 PCIe
SYMBOL LEGEND
SYMBOL LEGEND
DNI
DNI
BUO
BUO
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
5
4
PCI-E Edge Connector
PCI-E Edge Connector
Fri Oct 28 17:09:42 2016
Fri Oct 28 17:09:42 2016 1.0
1 21
1 21
OF
105_CXXX00_00A
105_CXXX00_00A
3
DO NOT
DO NOT
INSTALL
INSTALL
# ACTIVE
# ACTIVE
LOW
LOW
DIGITAL
DIGITAL
GROUND
GROUND
ANALOG
ANALOG
GROUND
GROUND
BRING UP
BRING UP
ONLY
ONLY
REV:
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
2
Advanced Micro Devices
TITLE
TITLE
1
BB
A
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
INININININININININININ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSPX_EN
PERSTB
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
NC#N30 NC#N29
NC#N33 NC#N32
PCIE_TX7P PCIE_TX7N
PCIE_TX6P PCIE_TX6N
PCIE_TX5P PCIE_TX5N
PCIE_TX4P PCIE_TX4N
PCIE_TX3P PCIE_TX3N
PCIE_TX2P PCIE_TX2N
PCIE_TX1P PCIE_TX1N
NC#H33 NC#H32
NC#K30 NC#K29
NC#J33 NC#J32
NC#K33 NC#K32
NC#L30 NC#L29
NC#L33 NC#L32
PCIE_TX0P PCIE_TX0N
NC#M35 NC#L36
NC#N38 NC#M37
PCIE_RX7P PCIE_RX7N
PCIE_RX6P PCIE_RX6N
PCIE_RX5P PCIE_RX5N
PCIE_RX4P PCIE_RX4N
PCIE_RX3P PCIE_RX3N
PCIE_RX2P PCIE_RX2N
PCIE_RX1P PCIE_RX1N
NC#F35 NC#E37
NC#G38 NC#F37
NC#H35 NC#G36
NC#J38 NC#H37
NC#K35 NC#J36
NC#L38 NC#K37
PCIE_RX0P PCIE_RX0N
PCIE_REFCLKP PCIE_REFCLKN
PCIE_PVDD
PCIE_CALR_TX PCIE_CALR_RX
NC_BIF_VDDC
NC_BIF_VDDC
NC#38
NC#37
NC#36
NC#35
NC#34
NC#33
PCIE_VDDC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTININININININININ
8
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017091101 RMA工程課
石阿鋒 (00068760)
7
6
345
2
1
C
Oland PCIe Interface
Oland PCIe Interface
+1.8V
+1.8V
2 1
2 1
C1161 1uF
1uF
6.3V
6.3V
B11
B11
+0.95V
+0.95V
120R
120R
2 1
2 1
21
21
C1160 10uF
10uF
6.3V
6.3V
PCIE_TX0P
PCIE_TX0P
PCIE_TX0N
PCIE_TX0N
PCIE_TX1P
PCIE_TX1P
PCIE_TX1N
PCIE_TX1N
PCIE_TX2P
PCIE_TX2P
PCIE_TX2N
PCIE_TX2N
PCIE_TX3P
PCIE_TX3P
PCIE_TX3N
PCIE_TX3N
PCIE_TX4P
PCIE_TX4P
PCIE_TX4N
PCIE_TX4N
PCIE_TX5P
PCIE_TX5P
PCIE_TX5N
PCIE_TX5N
PCIE_TX6P
PCIE_TX6P
PCIE_TX6N
PCIE_TX6N
PCIE_TX7P
PCIE_TX7P
PCIE_TX7N
PCIE_TX7N
R1013 R1014
C1101 C1102
C1103 C1104
C1105 C1106
C1107 C1108
C1109 C1110
C1111 C1112
C1113 C1114
C1115 C1116
220nF for GEN3
220nF for GEN3
21C1101
21
0.22uF
0.22uF
21C1102
21
0.22uF
0.22uF
21C1103
21
0.22uF
0.22uF
21C1104
21
0.22uF
0.22uF
21C1105
21
0.22uF
0.22uF
21C1106
21
0.22uF
0.22uF
21C1107
21
0.22uF
0.22uF
21C1108
21
0.22uF
0.22uF
21C1109
21
0.22uF
0.22uF
21C1110
21
0.22uF
0.22uF
21C1111
21
0.22uF
0.22uF
21C1112
21
0.22uF
0.22uF
21C1113
21
0.22uF
0.22uF
21C1114
21
0.22uF
0.22uF
21C1115
21
0.22uF
0.22uF
21C1116
21
0.22uF
0.22uF
+0.95V
+0.95V
21R1013
21 21R1014
21
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
1%1.69K
1%1.69K
1%1K
1%1K
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
1
1
IN
17 1
17 1
IN
+PCIE_PVDD
+PCIE_PVDD
2 1
2 1
C1159 10uF
10uF
6.3V
6.3V
C1143
C1143U1C1189
10uF
10uF
6.3V
6.3V
2 1
2 1
C1158
C1158C1159C1161 C1160
10uF
10uF
6.3V
6.3V
2 1
2 1
C1189
1uF
1uF
6.3V
6.3V
2 1
2 1
2 1
2 1
C1150
C1150
1uF
1uF
6.3V
6.3V
2 1
2 1
C1173
C1173
1uF
1uF
6.3V
6.3V
2 1
2 1
C1151
C1151
1uF
1uF
6.3V
6.3V
2 1
2 1
NOTE: Some of the PCIE testpoints will
NOTE: Some of the PCIE testpoints will
be available through vias on traces.
be available through vias on traces.
TP110
TP110
TP109
TP109
TP107
TP107
TP108
TP108
C1175
C1175
0.1uF
0.1uF
6.3V
6.3V
2 1
2 1
R1015
C1152 1uF
1uF
6.3V
6.3V
1K
DNI
21R1015
DNI
1K
21
PERST#_BUF
PERST#_BUF
1.8V 200mA
1.8V 200mA
C1153
C1153C1152
1uF
1uF
6.3V
6.3V
2 1
2 1
2 1
2 1
PETP1_GFXRP1
PETP1_GFXRP1
PETN1_GFXRN1
PETN1_GFXRN1
PETP3_GFXRP3
PETP3_GFXRP3
PETN3_GFXRN3
PETN3_GFXRN3
PETP4_GFXRP4
PETP4_GFXRP4
PETN4_GFXRN4
PETN4_GFXRN4
PETP5_GFXRP5
PETP5_GFXRP5
PETN5_GFXRN5
PETN5_GFXRN5
PETP7_GFXRP7
PETP7_GFXRP7
PETN7_GFXRN7
PETN7_GFXRN7
PCIE_REFCLKN PCIE_CALRN
PCIE_REFCLKN PCIE_CALRN
C1154
C1154
1uF
1uF
6.3V
6.3V
PETP0_GFXRP0
PETP0_GFXRP0
PETN0_GFXRN0
PETN0_GFXRN0
PETP2_GFXRP2
PETP2_GFXRP2
PETN2_GFXRN2
PETN2_GFXRN2
PETP6_GFXRP6
PETP6_GFXRP6
PETN6_GFXRN6
PETN6_GFXRN6
PX_EN
PX_EN
C1155
C1155
1uF
1uF
6.3V
6.3V
2 1
2 1
U1
AA38
AA38
PCIE_RX0P
Y37
Y37
PCIE_RX0N
Y35
Y35
PCIE_RX1P
W36
W36
PCIE_RX1N
W38
W38
PCIE_RX2P
V37
V37
PCIE_RX2N
V35
V35
PCIE_RX3P
U36
U36
PCIE_RX3N
U38
U38
PCIE_RX4P
T37
T37
PCIE_RX4N
T35
T35
PCIE_RX5P
R36
R36
PCIE_RX5N
R38
R38
PCIE_RX6P
P37
P37
PCIE_RX6N
P35
P35
PCIE_RX7P
N36
N36
PCIE_RX7N
N38 N33
N38 N33
NC#N38
M37
M37
NC#M37
M35
M35
NC#M35
L36
L36
NC#L36
L38
L38
NC#L38
K37
K37
NC#K37
K35
K35
NC#K35
J36
J36
NC#J36
J38
J38
NC#J38
H37
H37
NC#H37
H35
H35
NC#H35
G36
G36
NC#G36
G38
G38
NC#G38
F37
F37
NC#F37
F35
F35
NC#F35
E37
E37
NC#E37
AB35
AB35
PCIE_REFCLKP
AA36
AA36
PCIE_REFCLKN
AA30
AA30
PERSTB
AB37
AB37
PCIE_PVDD
AA31
AA31
NC#33
AA32
AA32
NC#34
AA33
AA33
NC#35
AA34
AA34
NC#36
W30
W30
NC#37
Y31
Y31
NC#38
V28
V28
NC_BIF_VDDC
W29
W29
NC_BIF_VDDC
G30
G30
PCIE_VDDC
G31
G31
PCIE_VDDC
H29
H29
PCIE_VDDC
H30
H30
PCIE_VDDC
J29
J29
PCIE_VDDC
J30
J30
PCIE_VDDC
L28
L28
PCIE_VDDC
M28
M28
PCIE_VDDC
N28
N28
PCIE_VDDC
R28
R28
PCIE_VDDC
T28
T28
PCIE_VDDC
U28
U28
PCIE_VDDC
PCIE_TX0P PCIE_TX0N
PCIE_TX1P PCIE_TX1N
PCIE_TX2P PCIE_TX2N
PCIE_TX3P PCIE_TX3N
PCIE_TX4P PCIE_TX4N
PCIE_TX5P PCIE_TX5N
PCIE_TX6P PCIE_TX6N
PCIE_TX7P PCIE_TX7N
NC#N33 NC#N32
NC#N30 NC#N29
NC#L33 NC#L32
NC#L30 NC#L29
NC#K33 NC#K32
NC#J33 NC#J32
NC#K30 NC#K29
NC#H33 NC#H32
PCIE_CALR_TX PCIE_CALR_RX
VSSPX_EN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y33
Y33 Y32
Y32 W33
W33 W32
W32 U33
U33 U32
U32 U30
U30 U29
U29 T33
T33 T32
T32 T30
T30 T29
T29 P33
P33 P32
P32 P30
P30 P29
P29
N32
N32 N30
N30 N29
N29 L33
L33 L32
L32 L30
L30 L29
L29 K33
K33 K32
K32 J33
J33 J32
J32 K30
K30 K29
K29 H33
H33 H32
H32
Y30
Y30 Y29
Y29
AB39AL21
AB39AL21 E39
E39 F34
F34 F39
F39 G33
G33 G34
G34 H31
H31 H34
H34 H39
H39 J31
J31 J34
J34 K31
K31 K34
K34 K39
K39 L31
L31 L34
L34 M34
M34 M39
M39 N31
N31 N34
N34 P31
P31 P34
P34 P39
P39 R34
R34 T31
T31 T34
T34 T39
T39 U31
U31 U34
U34 V34
V34 Y39
Y39 V39
V39 W31
W31 W34
W34 Y34
Y34
PCIE_CALRPPCIE_REFCLKP
PCIE_CALRPPCIE_REFCLKP
PERP0
PERP0
PERN0
PERN0
PERP1
PERP1
PERN1
PERN1
PERP2
PERP2
PERN2
PERN2
PERP3
PERP3
PERN3
PERN3
PERP4
PERP4
PERN4
PERN4
PERP5
PERP5
PERN5
PERN5
PERP6
PERP6
PERN6
PERN6
PERP7
PERP7
PERN7
PERN7
PCIE_CALR_TX 1.69k pull up for Oland
PCIE_CALR_TX 1.69k pull up for Oland
PCIE_CALR_RX 1k pull up for Oland
PCIE_CALR_RX 1k pull up for Oland
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
DD
C
BB
A
8
7
6
5
4
OLAND M2 GDDR5
OLAND M2 GDDR5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
Oland PCIE Interface
Oland PCIE Interface
Fri Oct 28 17:09:40 2016
Fri Oct 28 17:09:40 2016 1.0
2 21
2 21
OF
105_CXXX00_00A
105_CXXX00_00A
3
REV:
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
2
Advanced Micro Devices
TITLE
TITLE
1
A
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
WEB1BWEB0B
WCKB1B_1
WCKB1B_0
WCKB1_1
WCKB1_0
WCKB0B_1
WCKB0B_0 WCKB0_1
WCKB0_0
RASB1BRASB0B
MVREFSB
MVREFDB
MEM_CALRP0
MAB1_9
MAB1_8
MAB1_7
MAB1_6
MAB1_5
MAB1_4
MAB1_3
MAB1_2
MAB1_1
MAB1_0
MAB0_9
MAB0_8
MAB0_7
MAB0_6
MAB0_5
MAB0_4
MAB0_3
MAB0_2
MAB0_1
MAB0_0
EDCB1_3
EDCB1_2
EDCB1_1
EDCB1_0
EDCB0_3
EDCB0_2
EDCB0_1
EDCB0_0
DQB1_9
DQB1_8
DQB1_7
DQB1_6
DQB1_5
DQB1_4
DQB1_31
DQB1_30
DQB1_3
DQB1_29
DQB1_28
DQB1_27
DQB1_26
DQB1_25
DQB1_24
DQB1_23
DQB1_22
DQB1_21
DQB1_20
DQB1_2
DQB1_19
DQB1_18
DQB1_17
DQB1_16
DQB1_15
DQB1_14
DQB1_13
DQB1_12
DQB1_11
DQB1_10
DQB1_1
DQB1_0
DQB0_9
DQB0_8
DQB0_7
DQB0_6
DQB0_5
DQB0_4
DQB0_31
DQB0_30
DQB0_3
DQB0_29
DQB0_28
DQB0_27
DQB0_26
DQB0_25
DQB0_24
DQB0_23
DQB0_22
DQB0_21
DQB0_20
DQB0_2
DQB0_19
DQB0_18
DQB0_17
DQB0_16
DQB0_15
DQB0_14
DQB0_13
DQB0_12
DQB0_11
DQB0_10
DQB0_1
DQB0_0
DDBIB1_3
DDBIB1_2
DDBIB1_1
DDBIB1_0
DDBIB0_3
DDBIB0_2
DDBIB0_1
DDBIB0_0
CSB1B_1
CSB1B_0
CSB0B_1
CSB0B_0
CLKB1B
CLKB1
CLKB0B
CLKB0
CKEB1CKEB0
CASB1BCASB0B
ADBIB1ADBIB0
WEA1BWEA0B
WCKA1B_1
WCKA1B_0
WCKA1_1
WCKA1_0
WCKA0B_1
WCKA0B_0 WCKA0_1
WCKA0_0
RASA1BRASA0B
MVREFSA
MVREFDA
MAA1_9
MAA1_8
MAA1_7
MAA1_6
MAA1_5
MAA1_4
MAA1_3
MAA1_2
MAA1_1
MAA1_0
MAA0_9
MAA0_8
MAA0_7
MAA0_6
MAA0_5
MAA0_4
MAA0_3
MAA0_2
MAA0_1
MAA0_0
EDCA1_3
EDCA1_2
EDCA1_1
EDCA1_0
EDCA0_3
EDCA0_2
EDCA0_1
EDCA0_0
DRAM_RST
DQA1_9
DQA1_8
DQA1_7
DQA1_6
DQA1_5
DQA1_4
DQA1_31
DQA1_30
DQA1_3
DQA1_29
DQA1_28
DQA1_27
DQA1_26
DQA1_25
DQA1_24
DQA1_23
DQA1_22
DQA1_21
DQA1_20
DQA1_2
DQA1_19
DQA1_18
DQA1_17
DQA1_16
DQA1_15
DQA1_14
DQA1_13
DQA1_12
DQA1_11
DQA1_10
DQA1_1
DQA1_0
DQA0_9
DQA0_8
DQA0_7
DQA0_6
DQA0_5
DQA0_4
DQA0_31
DQA0_30
DQA0_3
DQA0_29
DQA0_28
DQA0_27
DQA0_26
DQA0_25
DQA0_24
DQA0_23
DQA0_22
DQA0_21
DQA0_20
DQA0_2
DQA0_19
DQA0_18
DQA0_17
DQA0_16
DQA0_15
DQA0_14
DQA0_13
DQA0_12
DQA0_11
DQA0_10
DQA0_1
DQA0_0
DDBIA1_3
DDBIA1_2
DDBIA1_1
DDBIA1_0
DDBIA0_3
DDBIA0_2
DDBIA0_1
DDBIA0_0
CSA1B_1
CSA1B_0
CSA0B_1
CSA0B_0
CLKA1B
CLKA1
CLKA0B
CLKA0
CKEA1CKEA0
CASA1BCASA0B
ADBIA1ADBIA0
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUT
OUT
OUTBIBIBIBI
8
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017091101 RMA工程課
石阿鋒 (00068760)
7
6
345
2
1
C
A
(3) Oland MEM Interface Ch A&B
(3) Oland MEM Interface Ch A&B
U1
DQA0_<31..0>
3 4 3 4 3 4 3 4
3 4 3 4 3 4 3 4
3 4
3 4
DRAM_RST DRAM_RST_RR
4
4
DRAM_RST DRAM_RST_RR
OUT
R3630
R3630
49.9R
49.9R
1%
1%
21
21
C3607
C3607 120pF
120pF
50V
50V
2 1
2 1
DQA0_<31..0>
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
21
21
R3615
R3615 10R
10R
1%
1%
0
0
4 3
4 3
1
1
4 3
4 3
2
2
4 3
4 3
3
3
4 3
4 3
4
4
4 3
4 3
5
5
4 3
4 3
6
6
4 3
4 3
7
7
4 3
4 3
8
8
4 3
4 3
9
9
4 3
4 3
10
10
4 3
4 3
11
11
4 3
4 3
12
12
4 3
4 3
13
13
4 3
4 3
14
14
4 3
4 3
15
15
4 3
4 3
16
16
4 3
4 3
17
17
4 3
4 3
18
18
4 3
4 3
19
19
4 3
4 3
20
20
4 3
4 3
21
21
4 3
4 3
22
22
4 3
4 3
23
23
4 3
4 3
24
24
4 3
4 3
25
25
4 3
4 3
26
26
4 3
4 3
27
27
4 3
4 3
28
28
4 3
4 3
29
29
4 3
4 3
30
30
4 3
4 3
31
31
0
0
4 3
4 3
1
1
4 3
4 3
2
2
4 3
4 3
3
3
4 3
4 3
4
4
4 3
4 3
5
5
4 3
4 3
6
6
4 3
4 3
7
7
4 3
4 3
8
8
DRAM_RST_R
DRAM_RST_R
21
21
4
4
DQA0_<0>
DQA0_<0>
3
3
DQA0_<1>
DQA0_<1>
DQA0_<2>
DQA0_<2>
DQA0_<3>
DQA0_<3>
DQA0_<4>
DQA0_<4>
DQA0_<5>
DQA0_<5>
DQA0_<6>
DQA0_<6>
DQA0_<7>
DQA0_<7>
DQA0_<8>
DQA0_<8>
DQA0_<9>
DQA0_<9>
DQA0_<10>
DQA0_<10>
DQA0_<11>
DQA0_<11>
DQA0_<12>
DQA0_<12>
DQA0_<13>
DQA0_<13>
DQA0_<14>
DQA0_<14>
DQA0_<15>
DQA0_<15>
DQA0_<16>
DQA0_<16>
DQA0_<17>
DQA0_<17>
DQA0_<18>
DQA0_<18>
DQA0_<19>
DQA0_<19>
DQA0_<20>
DQA0_<20>
DQA0_<21>
DQA0_<21>
DQA0_<22>
DQA0_<22>
DQA0_<23>
DQA0_<23>
DQA0_<24>
DQA0_<24>
DQA0_<25>
DQA0_<25>
DQA0_<26>
DQA0_<26>
DQA0_<27>
DQA0_<27>
DQA0_<28>
DQA0_<28>
DQA0_<29>
DQA0_<29>
DQA0_<30>
DQA0_<30>
DQA0_<31>
DQA0_<31>
4
4 3
3
MAA0_<0>
MAA0_<0>
MAA0_<1>
MAA0_<1>
MAA0_<2>
MAA0_<2>
MAA0_<3>
MAA0_<3>
MAA0_<4>
MAA0_<4>
MAA0_<5>
MAA0_<5>
MAA0_<6>
MAA0_<6>
MAA0_<7>
MAA0_<7>
MAA0_<8>
MAA0_<8>
WCKA0_0
WCKA0_0 WCKA0B_0
WCKA0B_0 WCKA0_1
WCKA0_1 WCKA0B_1
WCKA0B_1
EDCA0_0
EDCA0_0
EDCA0_1
EDCA0_1
EDCA0_2
EDCA0_2
EDCA0_3
EDCA0_3
DDBIA0_1
DDBIA0_1 DDBIA0_2
DDBIA0_2
DDBIA0_3
DDBIA0_3
ADBIA0 ADBIA1
ADBIA0 ADBIA1
CSA0B_0
CSA0B_0
CASA0B
CASA0B
RASA0B
RASA0B
WEA0B
WEA0B CKEA0 CKEA1
CKEA0 CKEA1
CLKA0 CLKA1
CLKA0 CLKA1 CLKA0B
CLKA0B
R3612
R3612
5.1K
5.1K
1%
1%
C37
C37 C35
C35 A35
A35 E34
E34 G32
G32 D33
D33 F32
F32 E32
E32 D31
D31 F30
F30 C30
C30 A30
A30 F28
F28 C28
C28 A28
A28 E28
E28 D27
D27 F26
F26 C26
C26 A26
A26 F24
F24 C24
C24 A24
A24 E24
E24 C22
C22 A22
A22 F22
F22 D21
D21 A20
A20 F20
F20 D19
D19 E18
E18
G24
G24 J23
J23 H24
H24 J24
J24 H26
H26 J26
J26 H21
H21 G21
G21 H23
H23 M21
M21 A32
A32 C32
C32 D23
D23 E22
E22
C34
C34 D29
D29 D25
D25 E20
E20 A34
A34 E30
E30 E26
E26 C20
C20
K24
K24 K27
K27
H27
H27 G27
G27
AH11
AH11
DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31
MAA0_0 MAA0_1 MAA0_2 MAA0_3 MAA0_4 MAA0_5 MAA0_6 MAA0_7 MAA0_8 MAA0_9
WCKA0_0 WCKA0B_0
WCKA0_1 WCKA0B_1
EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3
DDBIA0_0 DDBIA0_1 DDBIA0_2 DDBIA0_3
CSA0B_0 CSA0B_1
CLKA0 CLKA0B
DRAM_RST
OLAND M2 GDDR5
OLAND M2 GDDR5
DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8
DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31
MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7
MAA1_8
MAA1_9 WCKA1_0
WCKA1B_0
WCKA1_1
WCKA1B_1
EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3
DDBIA1_0 DDBIA1_1 DDBIA1_2 DDBIA1_3
ADBIA1ADBIA0
CSA1B_0 CSA1B_1
CASA1BCASA0B
RASA1BRASA0B
WEA1BWEA0B CKEA1CKEA0 CLKA1
CLKA1B
MVREFDA
MVREFSA
4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3
4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3
C18
C18 A18
A18 F18
F18 D17
D17 A16
A16 F16
F16 D15
D15 E14
E14 F14
F14 D13
D13 F12
F12 A12
A12 D11
D11 F10
F10 A10
A10 C10
C10 G13
G13 H13
H13 J13
J13 H11
H11 G10
G10 G8
G8 K9
K9 K10
K10 G9
G9 A8
A8 C8
C8 E8
E8 A6
A6 C6
C6 E6
E6 A5
A5
H19
H19 H20
H20 L13
L13 G16
G16 J16
J16 H16
H16 J17
J17 H17
H17 J19
J19 M20
M20 C14
C14 A14
A14 E10
E10 D9
D9
E16
E16 E12
E12 J10
J10 D7
D7 C16
C16 C12
C12 J11
J11 F8
F8 G19J21
G19J21
M13
M13 K16
K16 K17K20
K17K20 K19K23
K19K23 L15K26
L15K26 J20K21
J20K21 J14
J14 H14
H14
L18
L18
L20
L20
DQA1_<0>
DQA1_<0>
DQA1_<1>
DQA1_<1>
DQA1_<2>
DQA1_<2>
DQA1_<3>
DQA1_<3>
DQA1_<4>
DQA1_<4>
DQA1_<5>
DQA1_<5>
DQA1_<6>
DQA1_<6>
DQA1_<7>
DQA1_<7> DQA1_<8>
DQA1_<8>
DQA1_<9>
DQA1_<9>
DQA1_<10>
DQA1_<10> DQA1_<11>
DQA1_<11>
DQA1_<12>
DQA1_<12> DQA1_<13>
DQA1_<13> DQA1_<14>
DQA1_<14>
DQA1_<15>
DQA1_<15>
DQA1_<16>
DQA1_<16>
DQA1_<17>
DQA1_<17>
DQA1_<18>
DQA1_<18>
DQA1_<19>
DQA1_<19>
DQA1_<20>
DQA1_<20>
DQA1_<21>
DQA1_<21>
DQA1_<22>
DQA1_<22>
DQA1_<23>
DQA1_<23>
DQA1_<24>
DQA1_<24>
DQA1_<25>
DQA1_<25>
DQA1_<26>
DQA1_<26>
DQA1_<27>
DQA1_<27>
DQA1_<28>
DQA1_<28>
DQA1_<29>
DQA1_<29>
DQA1_<30>
DQA1_<30>
DQA1_<31>
DQA1_<31>
MAA1_<0>
MAA1_<0>
MAA1_<1>
MAA1_<1>
MAA1_<2>
MAA1_<2>
MAA1_<3>
MAA1_<3>
MAA1_<4>
MAA1_<4>
MAA1_<5>
MAA1_<5>
MAA1_<6>
MAA1_<6>
MAA1_<7>
MAA1_<7>
MAA1_<8>
MAA1_<8>
WCKA1_0
WCKA1_0 WCKA1B_0
WCKA1B_0 WCKA1_1
WCKA1_1 WCKA1B_1
WCKA1B_1
EDCA1_0
EDCA1_0
EDCA1_1
EDCA1_1
EDCA1_2
EDCA1_2
EDCA1_3
EDCA1_3 DDBIA1_0DDBIA0_0
DDBIA1_0DDBIA0_0
DDBIA1_1
DDBIA1_1 DDBIA1_2
DDBIA1_2
DDBIA1_3
DDBIA1_3
CSA1B_0
CSA1B_0
CASA1B
CASA1B
RASA1B
RASA1B
WEA1B
WEA1B
CLKA1B
CLKA1B
MVREFD/S =0.7*
MVREFD/S =0.7*
VDDR1
VDDR1
(GDDR3/4/5)
(GDDR3/4/5)
0
0 1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9
10
10 11
11 12
12 13
13 14
14 15
15 16
16 17
17 18
18 19
19 20
20 21
21 22
22 23
23 24
24 25
25 26
26 27
27 28
28 29
29 30
30 31
31
MAA1_<8..0>
MAA1_<8..0>
0
0 1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8
MVREFD_A
MVREFD_A
DQA1_<31..0>
DQA1_<31..0>
BI BI
BI BI
BI BI BI BI
BI BI BI BI
BI
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
BI BIBIBI
3 4
OUT OUTOUTOUT
4
4 4
4 4
4 4
4
4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4
2 1
2 1
3 4
+MVDD +MVDD
+MVDD +MVDD
R3602
R3602
40.2R
40.2R
1%
1%
1%
1%
2 1
2 1
C3602
C3602 1uF
1uF
R3606
R3606
6.3V
6.3V
100R
100R
1%
1%
1%
1%
2 1
2 1
3 4
3 4
DQB0_<31..0>
DQB0_<31..0>
4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 3
4 3
4 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3
MAB0_<8..0>MAA0_<8..0>
MAB0_<8..0>MAA0_<8..0>
4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
R3601
R3601
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
4
4
DQB0_<0>
DQB0_<0>
3
3
0
0
DQB0_<1>
DQB0_<1>
1
1
DQB0_<2>
DQB0_<2>
2
2
DQB0_<3>
DQB0_<3>
3
3
DQB0_<4>
DQB0_<4>
4
4
DQB0_<5>
DQB0_<5>
5
5
DQB0_<6>
DQB0_<6>
6
6
DQB0_<7>
DQB0_<7>
7
7
DQB0_<8>
DQB0_<8>
8
8
DQB0_<9>
DQB0_<9>
9
9
DQB0_<10>
DQB0_<10>
10
10
DQB0_<11>
DQB0_<11>
11
11
DQB0_<12>
DQB0_<12>
12
12
DQB0_<13>
DQB0_<13>
13
13
DQB0_<14>
DQB0_<14>
14
14
DQB0_<15>
DQB0_<15>
15
15
DQB0_<16>
DQB0_<16>
16
16
DQB0_<17>
DQB0_<17>
17
17
DQB0_<18>
DQB0_<18>
18
18
DQB0_<19>
DQB0_<19>
19
19
DQB0_<20>
DQB0_<20>
20
20
DQB0_<21>
DQB0_<21>
21
21
DQB0_<22>
DQB0_<22>
22
22
DQB0_<23>
DQB0_<23>
23
23
DQB0_<24>
DQB0_<24>
24
24
DQB0_<25>
DQB0_<25>
25
25
DQB0_<26>
DQB0_<26>
26
26
DQB0_<27>
DQB0_<27>
27
27
DQB0_<28>
DQB0_<28>
28
28
DQB0_<29>
DQB0_<29>
29
29
DQB0_<30>
DQB0_<30>
30
30
DQB0_<31>
DQB0_<31>
31
31
4
4
MAB0_<0>
MAB0_<0>
3
3
0
0
MAB0_<1>
MAB0_<1>
1
1
MAB0_<2>
MAB0_<2>
2
2
MAB0_<3>
MAB0_<3>
3
3
MAB0_<4>
MAB0_<4>
4
4
MAB0_<5>
MAB0_<5>
5
5
MAB0_<6>
MAB0_<6>
6
6
MAB0_<7>
MAB0_<7>
7
7
MAB0_<8>
MAB0_<8>
8
8
WCKB0_0
WCKB0_0
WCKB0B_0
WCKB0B_0 WCKB0_1
WCKB0_1 WCKB0B_1
WCKB0B_1
EDCB0_0
EDCB0_0
EDCB0_1
EDCB0_1
EDCB0_2
EDCB0_2
EDCB0_3
EDCB0_3 DDBIB0_0
DDBIB0_0
DDBIB0_1
DDBIB0_1
DDBIB0_2
DDBIB0_2
DDBIB0_3
DDBIB0_3
ADBIB0 ADBIB1
ADBIB0 ADBIB1
CSB0B_0
CSB0B_0
CASB0B
CASB0B
RASB0B
RASB0B
WEB0B
WEB0B CKEB0 CKEB1
CKEB0 CKEB1
CLKB0 CLKB1
CLKB0 CLKB1 CLKB0B
CLKB0B
243R
243R
21
21
MEM_CALRP0
MEM_CALRP0
1%
1%
Oland MEMORY INTERFACE
Oland MEMORY INTERFACE
Fri Oct 28 17:09:40 2016
Fri Oct 28 17:09:40 2016
C5
C5
DQB0_0
C3
C3
DQB0_1
E3
E3
DQB0_2
E1
E1
DQB0_3
F1
F1
DQB0_4
F3
F3
DQB0_5
F5
F5
DQB0_6
G4
G4
DQB0_7
H5
H5
DQB0_8
H6
H6
DQB0_9
J4
J4
DQB0_10
K6
K6
DQB0_11
K5
K5
DQB0_12
L4
L4
DQB0_13
M6
M6
DQB0_14
M1
M1
DQB0_15
M3
M3
DQB0_16
M5
M5
DQB0_17
N4
N4
DQB0_18
P6
P6
DQB0_19
P5
P5
DQB0_20
R4
R4
DQB0_21
T6
T6
DQB0_22
T1
T1
DQB0_23
U4
U4
DQB0_24
V6
V6
DQB0_25
V1
V1
DQB0_26
V3
V3
DQB0_27
Y6
Y6
DQB0_28
Y1
Y1
DQB0_29
Y3
Y3
DQB0_30
Y5
Y5
DQB0_31
P8
P8
MAB0_0
T9
T9
MAB0_1
P9
P9
MAB0_2
N7
N7
MAB0_3
N8
N8
MAB0_4
N9
N9
MAB0_5
U9
U9
MAB0_6
U8
U8
MAB0_7
T8
T8
MAB0_8
U12
U12
MAB0_9
H3
H3
WCKB0_0
H1
H1
WCKB0B_0
T3
T3
WCKB0_1
T5
T5
WCKB0B_1
F6
F6
EDCB0_0
K3
K3
EDCB0_1
P3
P3
EDCB0_2
V5
V5
EDCB0_3
G7
G7
DDBIB0_0
K1
K1
DDBIB0_1
P1
P1
DDBIB0_2
W4
W4
DDBIB0_3
P10
P10
CSB0B_0
L10
L10
CSB0B_1
L9
L9
CLKB0
L8
L8
CLKB0B
M27
M27
MEM_CALRP0
3
3
OF
105_CXXX00_00A
105_CXXX00_00A
21
21
U1
U1U1
OLAND M2 GDDR5
OLAND M2 GDDR5
REV:
1.0
1.0
DQB1_<31..0>
AA4
AA4
DQB1_<0>
DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8
DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31
MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MAB1_7
MAB1_8
MAB1_9 WCKB1_0
WCKB1B_0
WCKB1_1
WCKB1B_1
EDCB1_0 EDCB1_1 EDCB1_2 EDCB1_3
DDBIB1_0 DDBIB1_1 DDBIB1_2 DDBIB1_3
ADBIB1ADBIB0
CSB1B_0 CSB1B_1
CASB1BCASB0B
RASB1BRASB0B
WEB1BWEB0B CKEB1CKEB0 CLKB1
CLKB1B
MVREFDB
MVREFSB
4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3
4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3
DQB1_<0>
AB6
AB6
DQB1_<1>
DQB1_<1>
AB1
AB1
DQB1_<2>
DQB1_<2>
AB3
AB3
DQB1_<3>
DQB1_<3>
AD6
AD6
DQB1_<4>
DQB1_<4>
AD1
AD1
DQB1_<5>
DQB1_<5>
AD3
AD3
DQB1_<6>
DQB1_<6>
AD5
AD5
DQB1_<7>
DQB1_<7>
AF1
AF1
DQB1_<8>
DQB1_<8>
AF3
AF3
DQB1_<9>
DQB1_<9>
AF6
AF6
DQB1_<10>
DQB1_<10>
AG4
AG4
DQB1_<11>
DQB1_<11>
AH5
AH5
DQB1_<12>
DQB1_<12>
AH6
AH6
DQB1_<13>
DQB1_<13>
AJ4
AJ4
DQB1_<14>
DQB1_<14>
AK3
AK3
DQB1_<15>
DQB1_<15>
AF8
AF8
DQB1_<16>
DQB1_<16>
AF9
AF9
DQB1_<17>
DQB1_<17>
AG8
AG8
DQB1_<18>
DQB1_<18>
AG7
AG7
DQB1_<19>
DQB1_<19>
AK9
AK9
DQB1_<20>
DQB1_<20>
AL7
AL7
DQB1_<21>
DQB1_<21>
AM8
AM8
DQB1_<22>
DQB1_<22>
AM7
AM7
DQB1_<23>
DQB1_<23>
AK1
AK1
DQB1_<24>
DQB1_<24>
AL4
AL4
DQB1_<25>
DQB1_<25>
AM6
AM6
DQB1_<26>
DQB1_<26>
AM1
AM1
DQB1_<27>
DQB1_<27>
AN4
AN4
DQB1_<28>
DQB1_<28>
AP3
AP3
DQB1_<29>
DQB1_<29>
AP1
AP1
DQB1_<30>
DQB1_<30>
AP5
AP5
DQB1_<31>
DQB1_<31>
Y9
Y9
MAB1_<0>
MAB1_<0>
W9
W9
MAB1_<1>
MAB1_<1>
AC8
AC8
MAB1_<2>
MAB1_<2>
AC9
AC9
MAB1_<3>
MAB1_<3>
AA7
AA7
MAB1_<4>
MAB1_<4>
AA8
AA8
MAB1_<5>
MAB1_<5>
Y8
Y8
MAB1_<6>
MAB1_<6>
AA9
AA9
MAB1_<7>
MAB1_<7>
W8
W8
MAB1_<8>
MAB1_<8>
V12
V12
WCKB1_0
AE4
AE4
WCKB1_0
AF5
WCKB1B_0
AF5
WCKB1B_0 WCKB1_1
AK6
AK6
WCKB1_1
AK5
WCKB1B_1
AK5
WCKB1B_1
AB5
AB5
EDCB1_0
EDCB1_0
AH1
AH1
EDCB1_1
EDCB1_1
AJ9
AJ9
EDCB1_2
EDCB1_2
AM5
AM5
EDCB1_3
EDCB1_3
AC4
AC4
DDBIB1_0
DDBIB1_0
AH3
AH3
DDBIB1_1
DDBIB1_1
AJ8
AJ8
DDBIB1_2
DDBIB1_2
AM3
AM3
DDBIB1_3
DDBIB1_3
W7T7
W7T7
AD10
AD10
CSB1B_0
CSB1B_0
AC10
AC10 AA10W10
AA10W10
CASB1B
CASB1B
Y10T10
RASB1B
Y10T10
RASB1B
AB11N10
WEB1B
AB11N10
WEB1B
AA11U10
AA11U10 AD8
AD8 AD7
AD7
CLKB1B
CLKB1B
Y12
Y12
MVREFD/S =0.7* 1%
MVREFD/S =0.7* 1%
VDDR1
VDDR1
(GDDR3/4/5)
(GDDR3/4/5)
AA12
AA12
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
DQB1_<31..0>
0
0 1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9
10
10 11
11 12
12 13
13 14
14 15
15 16
16 17
17 18
18 19
19 20
20 21
21 22
22 23
23 24
24 25
25 26
26 27
27 28
28 29
29 30
30 31
31
MAB1_<8..0>
MAB1_<8..0>
0
0 1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8
BI BI
BI BI
BI BI BI BI
BI BI BI BI
BI
OUT
OUT OUT OUT
OUT OUT
OUT
MVREFD_B
MVREFD_B
Advanced Micro Devices
4
4 4
4 4
4 4
4
4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4
4
4
4
4 4
4 4
4 4
4 4
4 4
4
C3603
C3603 1uF
1uF
6.3V
6.3V
2 1
2 1
TITLE
TITLE
R3603
R3603
40.2R
40.2R
1%
1%
2 1
2 1
R3607
R3607 100R
100R
1%
1%
2 1
2 1
1%
1%
DD
3 4
3 4
C
BB
A
8
7
6
5
4
3
2
1
9
9
A
B
C
D
E
8
7
7 46 5 123
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
D
1
A
B
58 6 3
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
C
E
OUTININININ
OUT
OUT
OUT
OUTBIBIBIBIINININININININBIBIBIBIINININININ
OUT
OUT
OUT
OUTBIBIBIBIININININININININ
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK# CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
IN
OUTINOUTININININ
OUT
OUT
OUT
OUTBIBIBIBIININININININ
IN
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK# CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
IN
IN
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK# CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
IN
OUT
IN
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK# CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
INININ
OUT
OUT
OUT
OUTBIBIBIINBIINININININININ
9
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017091101 RMA工程課
石阿鋒 (00068760)
8
7 46 5 123
E
D
C
B
A
(4) GDDR5 Memory Channel A&B
(4) GDDR5 Memory Channel A&B
4 3
4 3
4 3
4 3
+MVDD
+MVDD
C2007
C2008
C2008
C2007
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
2 1
2 1
0.1uF
0.1uF
0.1uF
0.1uF
+MVDD
+MVDD
4.7uF4V4.7uF
4.7uF4V4.7uF
4V
4V
9
GDDR5
C2022
C2022
6.3V
6.3V
2 1
2 1
1uF
1uF
GDDR5
23CNOPN001
23CNOPN001
U2000
U2000
C2024
C2023
C2024
C2023
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
1uF
1uF
1uF
1uF
C2025
C2025
6.3V
6.3V
1uF
1uF
VDDQ_B1
VDDQ_B3 VDDQ_B12 VDDQ_B14
VDDQ_D1
VDDQ_D3 VDDQ_D12 VDDQ_D14
VDDQ_E5 VDDQ_E10
VDDQ_F1
VDDQ_F3 VDDQ_F12 VDDQ_F14
VDDQ_G2 VDDQ_G13
VDDQ_H3 VDDQ_H12
VDDQ_K3 VDDQ_K12
VDDQ_L2 VDDQ_L13
VDDQ_M1
VDDQ_M3 VDDQ_M12 VDDQ_M14
VDDQ_N5 VDDQ_N10
VDDQ_P1
VDDQ_P3 VDDQ_P12 VDDQ_P14
VDDQ_T1
VDDQ_T3 VDDQ_T12 VDDQ_T14
VDD_C5 VDD_C10 VDD_D11
VDD_G1
VDD_G4 VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14 VDD_P11
VDD_R5 VDD_R10
VSSQ_A1 VSSQ_A3
VSSQ_A12 VSSQ_A14
VSSQ_C1 VSSQ_C3 VSSQ_C4
VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E1 VSSQ_E3
VSSQ_E12 VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1 VSSQ_N3
VSSQ_N12 VSSQ_N14
VSSQ_R1 VSSQ_R3 VSSQ_R4
VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V1 VSSQ_V3
VSSQ_V12 VSSQ_V14
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
+MVDD
+MVDD
C2145
C2145
6.3V
6.3V
2 1
2 1
1uF
1uF
2 1
2 1
+MVDD
+MVDD
DQA0_<31..0>
BI
OUT
DQA0_<31..0>
MAA0_<8..0>
MAA0_<8..0>
4
4
DQA0_<30>
DQA0_<30>
3
3
30 17
30 17
4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3
4 3
4 3
8
8
4 3
4 3
7
7
4 3
4 3
6
6
4 3
4 3
5
5
4 3
4 3
4
4
4 3
4 3
3
3
4 3
4 3
2
2
4 3
4 3
1
1
4 3
4 3
0
0
DQA0_<31>
DQA0_<31>
31
31
DQA0_<29>
DQA0_<29>
29
29
DQA0_<28>
DQA0_<28>
28
28
DQA0_<27>
DQA0_<27>
27
27
DQA0_<24>
DQA0_<24>
24
24
DQA0_<26>
DQA0_<26>
26
26
DQA0_<25>
DQA0_<25>
25
25
DQA0_<17>
DQA0_<17>
17
17
DQA0_<16>
DQA0_<16>
16
16
DQA0_<18>
DQA0_<18>
18
18
DQA0_<21>
DQA0_<21>
21
21
DQA0_<19>
DQA0_<19>
19
19
DQA0_<23>
DQA0_<23>
23
23
DQA0_<20>
DQA0_<20>
20
20
DQA0_<22>
DQA0_<22>
22
22
DQA0_<2>
DQA0_<2>
2
2
DQA0_<3>
DQA0_<3>
3
3
DQA0_<1>
DQA0_<1>
1
1
DQA0_<4>
DQA0_<4>
4
4
DQA0_<0>
DQA0_<0>
0
0
DQA0_<6>
DQA0_<6>
6
6
DQA0_<7>
DQA0_<7>
7
7
DQA0_<5>
DQA0_<5>
5
5
DQA0_<15>
DQA0_<15>
15
15
DQA0_<13>
DQA0_<13>
13
13
DQA0_<14>
DQA0_<14>
14
14
DQA0_<12>
DQA0_<12>
12
12
DQA0_<11>
DQA0_<11>
11
11
DQA0_<8>
DQA0_<8>
8
8
DQA0_<10>
DQA0_<10>
10
10
DQA0_<9>
DQA0_<9>
9
9
MAA0_<8>
MAA0_<8>
MAA0_<7>
MAA0_<7>
MAA0_<6>
MAA0_<6>
MAA0_<5>
MAA0_<5>
MAA0_<4>
MAA0_<4>
MAA0_<3>
MAA0_<3>
MAA0_<2>
MAA0_<2>
MAA0_<1>
MAA0_<1>
MAA0_<0>
MAA0_<0>
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0
M13
M13
DQ23__DQ15
M11
M11
DQ22__DQ14
N13
N13
DQ21__DQ13
N11
N11
DQ20__DQ12
T13
T13
DQ19__DQ11
T11
T11
DQ18__DQ10
V13
V13
DQ17__DQ9
V11
V11
DQ16__DQ8
F13
F13
DQ15__DQ23
F11
F11
DQ14__DQ22
E13
E13
DQ13__DQ21
E11
E11
DQ12__DQ20
B13
B13
DQ11__DQ19
B11
B11
DQ10__DQ18
A13
A13
DQ9__DQ17
A11
A11
DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9
K10
K10
A5_BA1__A3_BA3
K11
K11
A4_BA2__A2_BA0
H10
H10
A3_BA3__A5_BA1
H11
H11
A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
C2018
C2018
6.3V
6.3V
2 1
2 1
1uF
1uF
C2131C2126C2122
C2131C2126C2122
R13
R13 C13
C13
P13
P13 D13
D13
J11
J11 J12
J12
G12
G12 L12
L12
J13
J13 J10
J10
A10
A10 V10
V10
J14
J14
C2019
C2019
6.3V
6.3V
2 1
2 1
1uF
1uF
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE# CK# CK
CS#__WE# WE#__CS#
ZQ SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1 VREFD1
VREFD2
VREFC
J4
J4
ABI#
C2020
C2021
C2021
C2020
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
1uF
1uF
1uF
1uF
+MVDD
+MVDD
+MVDD
+MVDD
C2010
C2010
6.3V
6.3V
2 1
2 1
0.1uF
0.1uF
+MVDD
+MVDD
R2003
R2003 R2004
R2004
R2098
R2098
C2003
C2003
R2297
R2297
R2296
R2296
C2296
C2296
C2000
C2011
C2001
C2001
C2011
C2000
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
2 1
2 1
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
4.7uF4V4.7uF4V4.7uF
4.7uF4V4.7uF4V4.7uF
4V
4V
3
3
4 3
4 3
R2099
R2099
1%
1%
C2012
C2012
6.3V
6.3V
2 1
2 1
0.1uF
0.1uF
60.4R
60.4R
1%
1%
60.4R
60.4R
1%
1%
2.37K
2.37K
1%
1%
5.49K
5.49K
21
21
1%
1%
1uF
1uF
6.3V
6.3V
2.37K
2.37K
1%
1%
5.49K
5.49K
21
21
1%
1%
1uF
1uF
6.3V
6.3V
3
3
C2013
C2013
6.3V
6.3V
2 1
2 1
0.1uF
0.1uF
C2127C2137C2136C2135
C2127C2137C2136C2135
3
3 3
3 3
3 3
3
3
3 3
3 3
3 3
3
3
3 3
3
21
21 21
21
3
3 3
3
3
3 3
3
R2002
120R
120R
1%
1%
IN
21
21 21
21
21
21 21
21
IN
C2014
C2014
6.3V
6.3V
0.1uF
0.1uF
2 1
2 1
3
3 3
3 3
3 3
3
IN IN
IN IN IN
IN IN
C2015
C2015
6.3V
6.3V
0.1uF
0.1uF
WCKA0_0
WCKA0_0
IN
WCKA0B_0
WCKA0B_0
IN
WCKA0_1
WCKA0_1
IN
WCKA0B_1
WCKA0B_1
IN
EDCA0_3
EDCA0_3
OUT
EDCA0_2
EDCA0_2
OUT
EDCA0_0
EDCA0_0
OUT
EDCA0_1
EDCA0_1
OUT
DDBIA0_3
DDBIA0_3
BI
DDBIA0_2
DDBIA0_2
BI
DDBIA0_0
DDBIA0_0
BI
DDBIA0_1
DDBIA0_1
BI
RASA0B
RASA0B
CASA0B
CASA0B
CLKA0B
CLKA0B
CLKA0
CLKA0
CKEA0
CKEA0
CSA0B_0
CSA0B_0
WEA0B
WEA0B
21
1% 1%
1% 1%
DRAM_RST
DRAM_RST
1%
1%
1%
1%
REFD_A0
REFD_A0
1%
1%
1%
1%
VREFC_U2000
VREFC_U2000
ADBIA0
ADBIA0
C2016
C2017
C2017
C2016
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
2 1
2 1
1uF
1uF
1uF
1uF
4.7uF4V4.7uF
4.7uF4V4.7uF
4V
4V
4 3
GDDR5
DQB0_<31..0>
+MVDD +MVDD +MVDD
+MVDD +MVDD +MVDD
4 3
B1
B1 B3
B3 B12
B12 B14
B14 D1
D1 D3
D3 D12
D12 D14
D14 E5
E5 E10
E10 F1
F1 F3
F3 F12
F12 F14
F14 G2
G2 G13
G13 H3
H3 H12
H12 K3
K3 K12
K12 L2
L2 L13
L13 M1
M1 M3
M3 M12
M12 M14
M14 N5
N5 N10
N10 P1
P1 P3
P3 P12
P12 P14
P14 T1
T1 T3
T3 T12
T12 T14
T14
C5
C5 C10
C10 D11
D11 G1
G1 G4
G4 G11
G11 G14
G14 L1
L1 L4
L4 L11
L11 L14
L14 P11
P11 R5
R5 R10
R10
A1
A1 A3
A3 A12
A12 A14
A14 C1
C1 C3
C3 C4
C4 C11
C11 C12
C12 C14
C14 E1
E1 E3
E3 E12
E12 E14
E14 F5
F5 F10
F10 H2
H2 H13
H13 K2
K2 K13
K13 M5
M5 M10
M10 N1
N1 N3
N3 N12
N12 N14
N14 R1
R1 R3
R3 R4
R4 R11
R11 R12
R12 R14
R14 V1
V1 V3
V3 V12
V12 V14
V14
B5
B5 B10
B10 D10
D10 G5
G5 G10
G10 H1
H1 H14
H14 K1
K1 K14
K14 L5
L5 L10
L10 P10
P10 T5
T5 T10
T10
C2100
C2100
6.3V
6.3V
2 1
2 1
1uF
1uF
4 3
3
3
OUT
4
4
+MVDD
+MVDD
+MVDD
+MVDD
+MVDD
+MVDD
+MVDD
+MVDD
C2101
C2102
C2103
C2103
C2102
C2101
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
2 1
2 1
1uF
1uF
1uF
1uF
1uF
1uF
4.7uF
4.7uF4V4.7uF4V4.7uF
4.7uF
4.7uF4V4.7uF4V4.7uF
4V
4V
4V
4V
C2104
C2104
6.3V
6.3V
2 1
2 1
1uF
1uF
BI
MAA1_<8..0>
MAA1_<8..0>
R2203
R2203 R2204
R2204
3
3
R2299
R2299
R2298
R2298
C2298
C2298
R2209
R2209
R2210
R2210
C2241
C2241
C2106
C2105
C2105
C2106
6.3V
6.3V
6.3V
6.3V
2 1
2 1
1uF
1uF
1uF
1uF
C2238C2237C2236
C2238C2237C2236
DQA1_<31..0>
DQA1_<31..0>
8
8 0
0 1
1 3
3 2
2 5
5 4
4 6
6 7
7
3
3 3
3 3
3 3
3
3
3 3
3 3
3 3
3
3
3 3
3 3
3 3
3
3
3 3
3
21
21
60.4R
60.4R
21
21
1%
1%
60.4R
60.4R
1%
1%
3
3 3
3
3
3 3
3
4 3
4 3
IN
21
21
2.37K
2.37K
21
21
1%
1%
5.49K
5.49K
21
21
1%
1%
1uF
1uF
6.3V
6.3V
1%
1%
21
21
2.37K
2.37K
21
21
1%
1%
5.49K
5.49K
21
21
1%
1%
1uF
1uF
6.3V
6.3V
3
3
IN
C2107
C2108
C2108
C2107
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
2 1
2 1
1uF
1uF
1uF
1uF
4
4 3
DQA1_<17>
DQA1_<17>
3
4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3
IN IN
IN IN
OUT OUT OUT OUT
BI BI BI BI
IN IN
IN IN IN
IN IN
1%
1%
1%
1%
1%
1%
1%
1%
C2109
C2109
6.3V
6.3V
1uF
1uF
4.7uF4V4.7uF
4.7uF4V4.7uF
4V
4V
DQA1_<23>
DQA1_<23>
23 25
23 25
DQA1_<16>
DQA1_<16>
16
16
DQA1_<20>
DQA1_<20>
20
20
DQA1_<19>
DQA1_<19>
19
19
DQA1_<22>
DQA1_<22>
22
22
DQA1_<18>
DQA1_<18>
18
18
DQA1_<21>
DQA1_<21>
21
21
DQA1_<30>
DQA1_<30>
30
30
DQA1_<24>
DQA1_<24>
24
24
DQA1_<29>
DQA1_<29>
29
29
DQA1_<27>
DQA1_<27>
27
27
DQA1_<28>
DQA1_<28>
28
28
DQA1_<25>
DQA1_<25>
25
25
DQA1_<31>
DQA1_<31>
31
31
DQA1_<26>
DQA1_<26>
26
26
DQA1_<14>
DQA1_<14>
14
14
DQA1_<15>
DQA1_<15>
15
15
DQA1_<12>
DQA1_<12>
12
12
DQA1_<8>
DQA1_<8>
8
8
DQA1_<13>
DQA1_<13>
13
13
DQA1_<9>
DQA1_<9>
9
9
DQA1_<11>
DQA1_<11>
11
11
DQA1_<10>
DQA1_<10>
10
10
DQA1_<1>
DQA1_<1>
1
1
DQA1_<0>
DQA1_<0>
0
0
DQA1_<6>
DQA1_<6>
6
6
DQA1_<5>
DQA1_<5>
5
5
DQA1_<2>
DQA1_<2>
2
2
DQA1_<4>
DQA1_<4>
4
4
DQA1_<3>
DQA1_<3>
3
3
DQA1_<7>
DQA1_<7>
7
7
4 3
4 3
MAA1_<8>
MAA1_<8>
4 3
4 3
MAA1_<0>
MAA1_<0>
4 3
4 3
MAA1_<1>
MAA1_<1>
4 3
4 3
MAA1_<3>
MAA1_<3>
4 3
4 3
MAA1_<2>
MAA1_<2>
MAA1_<5>
MAA1_<5>
4 3
4 3 4 3
4 3
MAA1_<4>
MAA1_<4>
MAA1_<6>
MAA1_<6>
4 3
4 3 4 3
4 3
MAA1_<7>
MAA1_<7>
WCKA1_0
WCKA1_0
WCKA1B_0
WCKA1B_0
WCKA1_1
WCKA1_1
WCKA1B_1
WCKA1B_1
EDCA1_2
EDCA1_2
EDCA1_3
EDCA1_3
EDCA1_1
EDCA1_1
EDCA1_0
EDCA1_0
DDBIA1_2
DDBIA1_2
DDBIA1_3
DDBIA1_3
DDBIA1_1
DDBIA1_1
DDBIA1_0
DDBIA1_0
CASA1B
CASA1B
RASA1B
RASA1B
CLKA1B
CLKA1B
CLKA1
CLKA1
CKEA1
CKEA1
WEA1B
WEA1B
CSA1B_0
CSA1B_0
R2201
R2201R2002
2121
21
120R
120R
1%
1%
DRAM_RST
DRAM_RST
+MVDD
+MVDD
REFD_A1
REFD_A1
VREFC_U2200
VREFC_U2200
ADBIA1
ADBIA1
C2110
C2111
C2112
C2112
C2111
C2110
6.3V
6.3V
6.3V
6.3V
6.3V
1uF
1uF
6.3V
2 1
2 1
2 1
2 1
1uF
1uF
1uF
1uF
2 1
2 1
C2113
C2113
6.3V
6.3V
2 1
2 1
1uF
1uF
C2234C2228C2235C2227
C2234C2228C2235C2227
4.7uF
4.7uF
4V
4V
2 1
2 1
M2
M2 M4
M4 N2
N2 N4
N4 T2
T2 T4
T4 V2
V2 V4
V4
M13
M13 M11
M11 N13
N13 N11
N11 T13
T13 T11
T11 V13
V13 V11
V11 F13
F13 F11
F11 E13
E13 E11
E11 B13
B13 B11
B11 A13
A13 A11
A11
F2
F2 F4
F4 E2
E2 E4
E4 B2
B2 B4
B4 A2
A2 A4
A4
J5
J5 K4
K4 K5
K5
K10
K10 K11
K11 H10
H10 H11
H11
H5
H5 H4
H4
D4
D4 D5
D5 P4
P4 P5
P5 R2
R2
R13
R13 C13
C13
C2
C2 P2
P2
P13
P13 D13
D13
D2
D2
G3
G3 L3
L3
J3
J3
J11
J11 J12
J12
G12
G12 L12
L12
J13
J13 J10
J10
J2
J2 J1
J1
A5
A5 V5
V5
A10
A10 V10
V10
J14
J14
J4
J4
C2114
C2114
6.3V
6.3V
2 1
2 1
1uF
1uF
C2115
C2115
6.3V
6.3V
2 1
2 1
1uF
1uF
DQ31__DQ7 DQ30__DQ6 DQ29__DQ5 DQ28__DQ4 DQ27__DQ3 DQ26__DQ2 DQ25__DQ1 DQ24__DQ0 DQ23__DQ15 DQ22__DQ14 DQ21__DQ13 DQ20__DQ12 DQ19__DQ11 DQ18__DQ10 DQ17__DQ9 DQ16__DQ8 DQ15__DQ23 DQ14__DQ22 DQ13__DQ21 DQ12__DQ20 DQ11__DQ19 DQ10__DQ18 DQ9__DQ17 DQ8__DQ16 DQ7__DQ31 DQ6__DQ30 DQ5__DQ29 DQ4__DQ28 DQ3__DQ27 DQ2__DQ26 DQ1__DQ25 DQ0__DQ24
RFU_A12_NC A7_A8__A0_A10 A6_A11__A1_A9 A5_BA1__A3_BA3 A4_BA2__A2_BA0 A3_BA3__A5_BA1 A2_BA0__A4_BA2 A1_A9__A6_A11 A0_A10__A7_A8
WCK01__WCK23 WCK01#__WCK23#
WCK23__WCK01 WCK23#__WCK01#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
RAS#__CAS# CAS#__RAS#
CKE# CK# CK
CS#__WE# WE#__CS#
ZQ SEN
RESET# MF
Vpp_NC Vpp_NC1
VREFD1 VREFD2
VREFC
ABI#
23CNOPN001
23CNOPN001
U2200
U2200
VDDQ_B1
VDDQ_B3 VDDQ_B12 VDDQ_B14
VDDQ_D1
VDDQ_D3 VDDQ_D12 VDDQ_D14
VDDQ_E5 VDDQ_E10
VDDQ_F1
VDDQ_F3 VDDQ_F12 VDDQ_F14
VDDQ_G2 VDDQ_G13
VDDQ_H3 VDDQ_H12
VDDQ_K3 VDDQ_K12
VDDQ_L2 VDDQ_L13
VDDQ_M1
VDDQ_M3 VDDQ_M12 VDDQ_M14
VDDQ_N5 VDDQ_N10
VDDQ_P1
VDDQ_P3 VDDQ_P12 VDDQ_P14
VDDQ_T1
VDDQ_T3 VDDQ_T12 VDDQ_T14
VDD_C5 VDD_C10 VDD_D11
VDD_G1
VDD_G4 VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14 VDD_P11
VDD_R5 VDD_R10
VSSQ_A1 VSSQ_A3
VSSQ_A12 VSSQ_A14
VSSQ_C1 VSSQ_C3 VSSQ_C4
VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E1 VSSQ_E3
VSSQ_E12 VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1 VSSQ_N3
VSSQ_N12 VSSQ_N14
VSSQ_R1 VSSQ_R3 VSSQ_R4
VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V1 VSSQ_V3
VSSQ_V12 VSSQ_V14
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
+MVDD
+MVDD
C2116
C2117
C2118
C2118
C2117
C2116
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
1uF
1uF
1uF
1uF
1uF
1uF
+MVDD +MVDD +MVDD
+MVDD +MVDD +MVDD
C2124
C2125
C2130
C2130
C2125
C2124
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
2 1
2 1
10uF
10uF
10uF
10uF
10uF
10uF
2 1
2 1
C2201
C2201
6.3V
6.3V
1uF
1uF
B1
B1 B3
B3 B12
B12 B14
B14 D1
D1 D3
D3 D12
D12 D14
D14 E5
E5 E10
E10 F1
F1 F3
F3 F12
F12 F14
F14 G2
G2 G13
G13 H3
H3 H12
H12 K3
K3 K12
K12 L2
L2 L13
L13 M1
M1 M3
M3 M12
M12 M14
M14 N5
N5 N10
N10 P1
P1 P3
P3 P12
P12 P14
P14 T1
T1 T3
T3 T12
T12 T14
T14
+MVDD +MVDD
+MVDD +MVDD
C5
C5 C10
C10 D11
D11 G1
G1 G4
G4 G11
G11 G14
G14 L1
L1 L4
L4 L11
L11 L14
L14 P11
P11 R5
R5 R10
R10
A1
A1 A3
A3 A12
A12 A14
A14 C1
C1 C3
C3 C4
C4 C11
C11 C12
C12 C14
C14 E1
E1 E3
E3 E12
E12 E14
E14 F5
F5 F10
F10 H2
H2 H13
H13 K2
K2 K13
K13 M5
M5 M10
M10 N1
N1 N3
N3 N12
N12 N14
N14 R1
R1 R3
R3 R4
R4 R11
R11 R12
R12 R14
R14 V1
V1 V3
V3 V12
V12 V14
V14
B5
B5 B10
B10 D10
D10 G5
G5 G10
G10 H1
H1 H14
H14 K1
K1 K14
K14 L5
L5 L10
L10 P10
P10 T5
T5 T10
T10
2 1
2 1
4 3
4 3
C2205
C2205
6.3V
6.3V
2 1
2 1
1uF
1uF
C2337
C2337
6.3V
6.3V
2 1
2 1
10uF
10uF
+MVDD
+MVDD
+MVDD
+MVDD
C2338
C2338
6.3V
6.3V
2 1
2 1
10uF
10uF
4 3
4 3
OUT
C2339
C2339
6.3V
6.3V
10uF
10uF
+MVDD
+MVDD
7
DQB0_<31..0>
BI
MAB0_<8..0>
MAB0_<8..0>
R2403
R2403
R2404
R2404
3
3
R2499
R2499
R2498
R2498
C2498
C2498
1%
1%
R2497
R2497 R2496
R2496
C2496
C2496
2 1
2 1
60.4R
60.4R
1%
1%
60.4R
60.4R
1%
1%
4 3
4 3
2.37K
2.37K
1%
1%
5.49K
5.49K
21
21
1%
1%
1uF
1uF
6.3V
6.3V
2.37K
2.37K
1%
1%
5.49K
5.49K
21
21
1%
1%
1uF
1uF
6.3V
6.3V
C2030
C2030
6.3V
6.3V
10uF
10uF
2 1
2 1
3
3 3
3 3
3 3
3
3
3 3
3 3
3 3
3
3
3 3
3
21
21 21
21
3
3 3
3
3
3 3
3
IN
21
21 21
21
21
21 21
21
3
3
C2031
C2031
6.3V
6.3V
10uF
10uF
4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3 4 3
4 3
8
8 7
7 6
6 5
5 4
4 3
3 2
2 1
1 0
0
3
3 3
3 3
3 3
3
IN IN
R2400
R2400
120R
120R
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
IN
C2032
C2032
6.3V
6.3V
2 1
2 1
10uF
10uF
4
4 3
3
DQB0_<24>
DQB0_<24>
24
24
DQB0_<25>
DQB0_<25>
DQB0_<31>
DQB0_<31>
31
31
DQB0_<30>
DQB0_<30>
30
30
DQB0_<29>
DQB0_<29>
29
29
DQB0_<26>
DQB0_<26>
26
26
DQB0_<28>
DQB0_<28>
28
28
DQB0_<27>
DQB0_<27>
27
27
DQB0_<16>
DQB0_<16>
16
16
DQB0_<17>
DQB0_<17>
17
17
DQB0_<18>
DQB0_<18>
18
18
DQB0_<23>
DQB0_<23>
23
23
DQB0_<20>
DQB0_<20>
20
20
DQB0_<21>
DQB0_<21>
21
21
DQB0_<19>
DQB0_<19>
19
19
DQB0_<22>
DQB0_<22>
22
22
DQB0_<5>
DQB0_<5>
5
5
DQB0_<4>
DQB0_<4>
4
4
DQB0_<2>
DQB0_<2>
2
2
DQB0_<3>
DQB0_<3>
3
3
DQB0_<1>
DQB0_<1>
1
1
DQB0_<7>
DQB0_<7>
7
7
DQB0_<0>
DQB0_<0>
0
0
DQB0_<6>
DQB0_<6>
6
6
DQB0_<13>
DQB0_<13>
13
13
DQB0_<15>
DQB0_<15>
15
15
DQB0_<14>
DQB0_<14>
14
14
DQB0_<12>
DQB0_<12>
12
12
DQB0_<10>
DQB0_<10>
10
10
DQB0_<11>
DQB0_<11>
11
11
DQB0_<8>
DQB0_<8>
8
8
DQB0_<9>
DQB0_<9>
9
9
4 3
4 3
MAB0_<8>
MAB0_<8>
MAB0_<7>
MAB0_<7>
4 3
4 3
MAB0_<6>
MAB0_<6>
4 3
4 3
MAB0_<5>
MAB0_<5>
4 3
4 3
MAB0_<4>
MAB0_<4>
4 3
4 3
MAB0_<3>
MAB0_<3>
4 3
4 3
MAB0_<2>
MAB0_<2>
4 3
4 3
MAB0_<1>
MAB0_<1>
4 3
4 3
MAB0_<0>
MAB0_<0>
4 3
4 3
WCKB0_0
IN IN
IN IN
OUT OUT OUT OUT
BI BI BI BI
IN IN IN
IN IN
WCKB0_0
WCKB0B_0
WCKB0B_0
WCKB0_1
WCKB0_1
WCKB0B_1
WCKB0B_1
EDCB0_3
EDCB0_3
EDCB0_2
EDCB0_2
EDCB0_0
EDCB0_0
EDCB0_1
EDCB0_1
DDBIB0_3
DDBIB0_3
DDBIB0_2
DDBIB0_2
DDBIB0_0
DDBIB0_0
DDBIB0_1
DDBIB0_1
RASB0B
RASB0B
CASB0B
CASB0B
CLKB0B
CLKB0B
CLKB0
CLKB0
CKEB0
CKEB0
CSB0B_0
CSB0B_0
WEB0B
WEB0B
21 J13
21
1%
1%
DRAM_RST
DRAM_RST
REFD_B0
REFD_B0
VREFC_U2400
VREFC_U2400
ADBIB0
ADBIB0
+MVDD
+MVDD
C2233
C2230
C2230
C2233
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
10uF
10uF
10uF
10uF
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0
M13
M13
DQ23__DQ15
M11
M11
DQ22__DQ14
N13
N13
DQ21__DQ13
N11
N11
DQ20__DQ12
T13
T13
DQ19__DQ11
T11
T11
DQ18__DQ10
V13
V13
DQ17__DQ9
V11
V11
DQ16__DQ8
F13
F13
DQ15__DQ23
F11
F11
DQ14__DQ22
E13
E13
DQ13__DQ21
E11
E11
DQ12__DQ20
B13
B13
DQ11__DQ19
B11
B11
DQ10__DQ18
A13
A13
DQ9__DQ17
A11
A11
DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9
K10
K10
A5_BA1__A3_BA3
K11
K11
A4_BA2__A2_BA0
H10
H10
A3_BA3__A5_BA1
H11
H11
A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0
R13
R13
EDC2__EDC1
C13
C13
EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0#
P13
P13
DBI2#__DBI1#
D13
D13
DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE#
J11
J11
CK#
J12
J12
CK
G12
G12
CS#__WE#
L12
L12
WE#__CS#
J13
ZQ
J10
J10
SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1
A10
A10
VREFD1
V10
V10
VREFD2
J14
J14
VREFC
J4
J4
ABI#
58 6 3
GDDR5
23CNOPN001
23CNOPN001
U2400
U2400
VDDQ_B12 VDDQ_B14
VDDQ_D12 VDDQ_D14
VDDQ_E10
VDDQ_F12 VDDQ_F14
VDDQ_G13 VDDQ_H12 VDDQ_K12 VDDQ_L13
VDDQ_M12 VDDQ_M14
VDDQ_N10
VDDQ_P12 VDDQ_P14
VDDQ_T12 VDDQ_T14
VSSQ_A12 VSSQ_A14
VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E12 VSSQ_E14
VSSQ_F10 VSSQ_H13 VSSQ_K13 VSSQ_M10
VSSQ_N12 VSSQ_N14
VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V12 VSSQ_V14
4
VDDQ_B1 VDDQ_B3
VDDQ_D1 VDDQ_D3
VDDQ_E5 VDDQ_F1
VDDQ_F3
VDDQ_G2 VDDQ_H3 VDDQ_K3 VDDQ_L2 VDDQ_M1
VDDQ_M3
VDDQ_N5 VDDQ_P1
VDDQ_P3
VDDQ_T1 VDDQ_T3
VDD_C5 VDD_C10 VDD_D11
VDD_G1
VDD_G4 VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14 VDD_P11
VDD_R5 VDD_R10
VSSQ_A1 VSSQ_A3
VSSQ_C1 VSSQ_C3 VSSQ_C4
VSSQ_E1 VSSQ_E3
VSSQ_F5 VSSQ_H2 VSSQ_K2 VSSQ_M5 VSSQ_N1
VSSQ_N3
VSSQ_R1 VSSQ_R3 VSSQ_R4
VSSQ_V1 VSSQ_V3
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
B1
B1 B3
B3 B12
B12 B14
B14 D1
D1 D3
D3 D12
D12 D14
D14 E5
E5 E10
E10 F1
F1 F3
F3 F12
F12 F14
F14 G2
G2 G13
G13 H3
H3 H12
H12 K3
K3 K12
K12 L2
L2 L13
L13 M1
M1 M3
M3 M12
M12 M14
M14 N5
N5 N10
N10 P1
P1 P3
P3 P12
P12 P14
P14 T1
T1 T3
T3 T12
T12 T14
T14
C5
C5 C10
C10 D11
D11 G1
G1 G4
G4 G11
G11 G14
G14 L1
L1 L4
L4 L11
L11 L14
L14 P11
P11 R5
R5 R10
R10
A1
A1 A3
A3 A12
A12 A14
A14 C1
C1 C3
C3 C4
C4 C11
C11 C12
C12 C14
C14 E1
E1 E3
E3 E12
E12 E14
E14 F5
F5 F10
F10 H2
H2 H13
H13 K2
K2 K13
K13 M5
M5 M10
M10 N1
N1 N3
N3 N12
N12 N14
N14 R1
R1 R3
R3 R4
R4 R11
R11 R12
R12 R14
R14 V1
V1 V3
V3 V12
V12 V14
V14
B5
B5 B10
B10 D10
D10 G5
G5 G10
G10 H1
H1 H14
H14 K1
K1 K14
K14 L5
L5 L10
L10 P10
P10 T5
T5 T10
T10
4 3
4 3
4 3
OUT
+MVDD
+MVDD
+MVDD
+MVDD
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
DQB1_<31..0>
DQB1_<31..0>
BI
MAB1_<8..0>
MAB1_<8..0>
3
3 3
3 3
3 3
3
3
3 3
3 3
3 3
3
3
3 3
3 3
3 3
3
+MVDD
+MVDD
R2603
R2603 R2604
R2604
R2699
R2699
R2698
R2698
C2698
C2698
R2697
R2697
R2696
R2696
C2696
C2696
GDDR5 CHA&B
GDDR5 CHA&B
NOTE
NOTE
3
3 3
3
60.4R
60.4R
1%
1%
60.4R
60.4R
3
3
1%
1%
3
3 3
3
3
3 3
3
4 3
4 3
IN
21
21
2.37K
2.37K
21
21
1%
1%
5.49K
5.49K
21
21
1%
1%
1uF
1uF
6.3V
6.3V
21
21
2.37K
2.37K
21
21
1%
1%
5.49K
5.49K
21
21
1%
1%
1uF
1uF
6.3V
6.3V
3
3
Fri Oct 28 17:09:35 2016
Fri Oct 28 17:09:35 2016
18
18
4 3
4 3
20
20
4 3
4 3
16
16
4 3
4 3
19
19
4 3
4 3
17
17
4 3
4 3
22
22
4 3
4 3
21
21
4 3
4 3
23
23
4 3
4 3
30
30
4 3
4 3
27
27
4 3
4 3
29
29
4 3
4 3
25
25
4 3
4 3
26
26
4 3
4 3
24
24
4 3
4 3
28
28
4 3
4 3
31
31
4 3
4 3
14
14
4 3
4 3
15
15
4 3
4 3
13
13
4 3
4 3
8
8
4 3
4 3
11
11
4 3
4 3
9
9
4 3
4 3
12
12
4 3
4 3
10
10
4 3
4 3
3
3
4 3
4 3
0
0
4 3
4 3
2
2
4 3
4 3
1
1
4 3
4 3
5
5
4 3
4 3
6
6
4 3
4 3
4
4
4 3
4 3
7
7
4 3
4 3
8
8
4 3
4 3
0
0
4 3
4 3
1
1
4 3
4 3
3
3
4 3
4 3
2
2
4 3
4 3
5
5
4 3
4 3
4
4
4 3
4 3
6
6
4 3
4 3
7
7
IN IN
IN IN
OUT OUT OUT OUT
BI BI BI BI
IN IN
21
21 21
IN IN IN
IN IN
R2601
R2601
120R
120R
1%
1%
+MVDD
+MVDD
1%
1%
1%
1%
1%
1%
1%
1%
VREFC_U2600
VREFC_U2600
IN
105_CXXX00_00A
105_CXXX00_00A
4
4 3
DQB1_<18>
DQB1_<18>
3
DQB1_<20>
DQB1_<20>
DQB1_<16>
DQB1_<16>
DQB1_<19>
DQB1_<19>
DQB1_<17>
DQB1_<17>
DQB1_<22>
DQB1_<22>
DQB1_<21>
DQB1_<21>
DQB1_<23>
DQB1_<23>
DQB1_<30>
DQB1_<30>
DQB1_<27>
DQB1_<27>
DQB1_<29>
DQB1_<29>
DQB1_<25>
DQB1_<25>
DQB1_<26>
DQB1_<26>
DQB1_<24>
DQB1_<24>
DQB1_<28>
DQB1_<28>
DQB1_<31>
DQB1_<31>
DQB1_<14>
DQB1_<14>
DQB1_<15>
DQB1_<15>
DQB1_<13>
DQB1_<13>
DQB1_<8>
DQB1_<8>
DQB1_<11>
DQB1_<11>
DQB1_<9>
DQB1_<9>
DQB1_<12>
DQB1_<12>
DQB1_<10>
DQB1_<10>
DQB1_<3>
DQB1_<3>
DQB1_<0>
DQB1_<0>
DQB1_<2>
DQB1_<2>
DQB1_<1>
DQB1_<1>
DQB1_<5>
DQB1_<5>
DQB1_<6>
DQB1_<6>
DQB1_<4>
DQB1_<4>
DQB1_<7>
DQB1_<7>
MAB1_<8>
MAB1_<8>
MAB1_<0>
MAB1_<0>
MAB1_<1>
MAB1_<1>
MAB1_<3>
MAB1_<3>
MAB1_<2>
MAB1_<2>
MAB1_<5>
MAB1_<5>
MAB1_<4>
MAB1_<4>
MAB1_<6>
MAB1_<6>
MAB1_<7>
MAB1_<7>
WCKB1_0
WCKB1_0
WCKB1B_0
WCKB1B_0
WCKB1_1
WCKB1_1
WCKB1B_1
WCKB1B_1
EDCB1_2
EDCB1_2
EDCB1_3
EDCB1_3
EDCB1_1
EDCB1_1
EDCB1_0
EDCB1_0
DDBIB1_2
DDBIB1_2
DDBIB1_3
DDBIB1_3
DDBIB1_1
DDBIB1_1
DDBIB1_0
DDBIB1_0
CASB1B
CASB1B
RASB1B
RASB1B
CLKB1B
CLKB1B
CLKB1
CLKB1
CKEB1
CKEB1
WEB1B
WEB1B
CSB1B_0
CSB1B_0
21 J13
21
1%
1%
DRAM_RST
DRAM_RST
REFD_B1
REFD_B1
ADBIB1
ADBIB1
OF
M13
M13 M11
M11 N13
N13 N11
N11 T13
T13 T11
T11 V13
V13 V11
V11 F13
F13 F11
F11 E13
E13 E11
E11 B13
B13 B11
B11 A13
A13 A11
A11
K10
K10 K11
K11 H10
H10 H11
H11
R13
R13 C13
C13
P13
P13 D13
D13
J11
J11 J12
J12
G12
G12 L12
L12
J13 J10
J10
A10
A10 V10
V10
J14
J14
214
214
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0 DQ23__DQ15 DQ22__DQ14 DQ21__DQ13 DQ20__DQ12 DQ19__DQ11 DQ18__DQ10 DQ17__DQ9 DQ16__DQ8 DQ15__DQ23 DQ14__DQ22 DQ13__DQ21 DQ12__DQ20 DQ11__DQ19 DQ10__DQ18 DQ9__DQ17 DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9 A5_BA1__A3_BA3 A4_BA2__A2_BA0 A3_BA3__A5_BA1 A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE# CK# CK
CS#__WE# WE#__CS#
ZQ SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1 VREFD1
VREFD2
VREFC
J4
J4
ABI#
REV:
GDDR5
GDDR5
23CNOPN001
23CNOPN001
U2600
U2600
1.0
1.0
+MVDD
+MVDD
B1
VDDQ_B1
VDDQ_B3 VDDQ_B12 VDDQ_B14
VDDQ_D1
VDDQ_D3 VDDQ_D12 VDDQ_D14
VDDQ_E5 VDDQ_E10
VDDQ_F1
VDDQ_F3 VDDQ_F12 VDDQ_F14
VDDQ_G2 VDDQ_G13
VDDQ_H3 VDDQ_H12
VDDQ_K3 VDDQ_K12
VDDQ_L2 VDDQ_L13
VDDQ_M1
VDDQ_M3 VDDQ_M12 VDDQ_M14
VDDQ_N5 VDDQ_N10
VDDQ_P1
VDDQ_P3 VDDQ_P12 VDDQ_P14
VDDQ_T1
VDDQ_T3 VDDQ_T12 VDDQ_T14
VDD_C5 VDD_C10 VDD_D11
VDD_G1
VDD_G4 VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14 VDD_P11
VDD_R5 VDD_R10
VSSQ_A1 VSSQ_A3
VSSQ_A12 VSSQ_A14
VSSQ_C1 VSSQ_C3 VSSQ_C4
VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E1 VSSQ_E3
VSSQ_E12 VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1 VSSQ_N3
VSSQ_N12 VSSQ_N14
VSSQ_R1 VSSQ_R3 VSSQ_R4
VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V1 VSSQ_V3
VSSQ_V12 VSSQ_V14
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
B1 B3
B3 B12
B12 B14
B14 D1
D1 D3
D3 D12
D12 D14
D14 E5
E5 E10
E10 F1
F1 F3
F3 F12
F12 F14
F14 G2
G2 G13
G13 H3
H3 H12
H12 K3
K3 K12
K12 L2
L2 L13
L13 M1
M1 M3
M3 M12
M12 M14
M14 N5
N5 N10
N10 P1
P1 P3
P3 P12
P12 P14
P14 T1
T1 T3
T3 T12
T12 T14
T14
+MVDD
+MVDD
C5
C5 C10
C10 D11
D11 G1
G1 G4
G4 G11
G11 G14
G14 L1
L1 L4
L4 L11
L11 L14
L14 P11
P11 R5
R5 R10
R10
A1
A1 A3
A3 A12
A12 A14
A14 C1
C1 C3
C3 C4
C4 C11
C11 C12
C12 C14
C14 E1
E1 E3
E3 E12
E12 E14
E14 F5
F5 F10
F10 H2
H2 H13
H13 K2
K2 K13
K13 M5
M5 M10
M10 N1
N1 N3
N3 N12
N12 N14
N14 R1
R1 R3
R3 R4
R4 R11
R11 R12
R12 R14
R14 V1
V1 V3
V3 V12
V12 V14
V14
B5
B5 B10
B10 D10
D10 G5
G5 G10
G10 H1
H1 H14
H14 K1
K1 K14
K14 L5
L5 L10
L10 P10
P10 T5
T5 T10
T10
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
+MVDD
+MVDD
+MVDD
+MVDD
2016
2016
2
C2312
C2312
1uF
1uF
6.3V
6.3V
2 1
2 1
C2313
C2313
6.3V
6.3V
2 1
2 1
1uF
1uF
C2332C2327C2325C234021
C2332C2327C2325C2340
C2314
C2314
6.3V
6.3V
2 1
2 1
1uF
1uF
C2315
6.3V
6.3V
2 1
2 1
1uF
1uF
C2328
C2328
4.7uF
4.7uF
4V
4V
C2316
6.3V
6.3V
1uF
1uF
C2305
C2311
C2311
C2305
6.3V
6.3V
6.3V
6.3V
2 1
2 1
2 1
2 1
2 1
2 1
1uF
1uF
1uF
1uF
4.7uF4V4.7uF4V4.7uF4V4.7uF
4.7uF4V4.7uF4V4.7uF4V4.7uF
4V
4V
+MVDD
+MVDD
4.7uF4V4.7uF4V4.7uF4V4.7uF4V4.7uF4V4.7uF
4.7uF4V4.7uF4V4.7uF4V4.7uF4V4.7uF4V4.7uF
4V
4V
Advanced Micro Devices
TITLE
TITLE
C2316
C2315
1
2 1
2 1
C2317
C2317
6.3V
6.3V
2 1
2 1
1uF
1uF
C2318
C2318
6.3V
6.3V
2 1
2 1
1uF
1uF
C2319
C2319
6.3V
6.3V
2 1
2 1
1uF
1uF
C2036C2035C2039C2033C2042C2041
C2036C2035C2039C2033C2042C2041
C2320
C2320
6.3V
6.3V
2 1
2 1
1uF
1uF
C2321
C2321
6.3V
6.3V
2 1
2 1
1uF
1uF
C2322
C2322
6.3V
6.3V
1uF
1uF
E
D
C
B
A
9
9
A
B
C
D
E
8
7
7 46 5 123
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
D
1
A
B
58 6 3
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
C
E
ININOUT
OUT
IN
DP_VDDR
DP_VDDC
XTALOUT
XTALIN
XO_IN2
XO_IN
SPLL_VDDC
SPLL_PVSS
SPLL_PVDD
NC_XTAL_PVSS
NC_XTAL_PVDD
MPLL_PVDD
MPLL_PVDD
DP_VSSR
CLKTESTB
CLKTESTA
DBG_VREFG
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
NC#5
NC#4
NC#3
NC#2
NC#1
DBG_DATA9
DBG_DATA8
DBG_DATA7
DBG_DATA6
DBG_DATA5
DBG_DATA4
DBG_DATA3
DBG_DATA23
DBG_DATA22
DBG_DATA21
DBG_DATA20
DBG_DATA2
DBG_DATA19
DBG_DATA18
DBG_DATA17
DBG_DATA16
DBG_DATA15
DBG_DATA14
DBG_DATA13
DBG_DATA12
DBG_DATA11
DBG_DATA10
DBG_DATA1
DBG_DATA0
DBG_CNTL0
VDDR3
VDDR3
VDDR3
VDDR3
RSVD#AK27
TEST_PG
SMBDATA
SMBCLK
SDA
SCL
NC#75 NC#74
NC#73 NC#72
HPD1
GPIO_9_ROMSI
GPIO_8_ROMSO
GPIO_7_BLON
GPIO_6_TACH
GPIO_5_AC_BATT
GPIO_30
GPIO_29
GPIO_22_ROMCSB
GPIO_21
GPIO_20_PWRCNTL_1
GPIO_2
GPIO_19_CTF
GPIO_18_HPD3
GPIO_17_THERMAL_INT
GPIO_16
GPIO_15_PWRCNTL_0
GPIO_14_HPD2
GPIO_13
GPIO_12
GPIO_11
GPIO_10_ROMSCK
GPIO_1
GPIO_0
GENERICG_HPD6
GENERICF_HPD5
GENERICE_HPD4
GENERICD
GENERICC
GENERICB
GENERICA
RSVD#AJ27
CLKREQB
OUT
BIOS
OUT
OUT
OUT
OUT
OUT
OUTBIBI
OUT
OUT
CE
SI
SCK
HOLD
VDD
GND
WP
SO
9
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017091101 RMA工程課
石阿鋒 (00068760)
8
7 46 5 123
OLAND GPIOs Strap CF XTAL OSC
OLAND GPIOs Strap CF XTAL OSC
+3.3V_BUS
+3.3V_BUS
R4018R4017
R4018
R4017
4.7K 4.7K
E
18 16
18 16
18 16
18 16
OUT BI
4.7K 4.7K
2 1
2 1
2 1
2 1
D
C1
C1
1uF
1uF
6.3V
6.3V
2 1
2 1
1
1
OUT
1
1
BI
R33
R33 1K
1K
2 1
2 1
60mA
60mA
SMBCLK
SMBCLK
SMBDATA
SMBDATA
TEST_PG
TEST_PG
SCL
SCL
SDA
SDA
AF23
AF23 AF24
AF24 AG23
AG23 AG24
AG24
AK26
AK26 AJ26
AJ26
AJ23
AJ23 AH23
AH23
AF35
AF35 AG36
AG36 AJ27
AJ27 AK27
AK27 AN36
AN36 AP37
AP37
AH16
AH16
VDDR3 VDDR3 VDDR3 VDDR3
SCL SDA
SMBCLK SMBDATA
NC#75 NC#74 RSVD#AJ27 RSVD#AK27
NC#73 NC#72
TEST_PG
PN 2280007900G for 1Mbit (PM25LV010A-100SCE)
U1
U1
OLAND M2 GDDR5
OLAND M2 GDDR5
GPIO_0 GPIO_1 GPIO_2
GPIO_5_AC_BATT
GPIO_10_ROMSCK
GPIO_15_PWRCNTL_0
GPIO_17_THERMAL_INT
GPIO_20_PWRCNTL_1
GPIO_22_ROMCSB
GPIO_6_TACH
GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI
GPIO_11 GPIO_12 GPIO_13
GPIO_14_HPD2
GPIO_16
GPIO_18_HPD3
GPIO_19_CTF
GPIO_21 GPIO_29
GPIO_30
CLKREQB GENERICA GENERICB GENERICC GENERICD
GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6
HPD1
AH20
AH20 AH18
AH18 AN16
AN16
AH17
AH17 AJ17
AJ17 AK17
AK17 AJ13
AJ13 AH15
AH15 AJ16
AJ16 AK16
AK16 AL16
AL16 AM16
AM16 AM14
AM14 AM13
AM13 AK14
AK14 AG30
AG30 AN14
AN14 AM17
AM17 AL13
AL13 AJ14
AJ14 AK13
AK13 AG32
AG32 AG33
AG33 AN13
AN13 AJ19
AJ19 AK19
AK19 AJ20
AJ20 AK20
AK20 AJ24
AJ24 AH26
AH26 AH24
AH24 AK24
AK24
GPIO_8
GPIO_8
GPIO_9
GPIO_9
GPIO_10
GPIO_10
GPIO_22
GPIO_22
GPIO_29_VID2
GPIO_29_VID2
GPIO_30_VID3
GPIO_30_VID3
HPD1
HPD1
GPIO_7_VDDCI_VID0 GPIO_22_R
GPIO_7_VDDCI_VID0 GPIO_22_R
63
63
RP1
RP1
33R
33R
33R
33R
RP1
RP1
81
81 72
72
RP1
RP1
33R
33R
GPIO_14_HPD2
GPIO_14_HPD2
GPIO_15_VID0
GPIO_15_VID0
GPIO_16_VDDCI_VID1
GPIO_16_VDDCI_VID1
GPIO_17_THERMINT
GPIO_17_THERMINT
GPIO_19_CTF
GPIO_19_CTF
GPIO_20_VID1
GPIO_20_VID1
54
54
RP1
RP1
33R
33R
16
16
OUT
16
16
OUT
GENERICB
GENERICB
IN
CONNECT AT ASIC
CONNECT AT ASIC
R32
7
7
DNI
DNI
OUT
IN OUT OUT
IN OUT
OUT
16
16
9
9 16
16 16
16 18
18 17
17 16
16
CLKREQ# requires open drain connection,
CLKREQ# requires open drain connection,
10K
10K
21
21R32
and cannot be used as pinstrap
and cannot be used as pinstrap
GPIO_8_R
GPIO_8_R
PN 2280007900G for 1Mbit (PM25LV010A-100SCE)
BIOS1
BIOS(113?)
BIOS(113?)
8
8 7
7 6
6 5
5
SI
GPIO_9_R
GPIO_9_R
BIOS1
BIOS
+3.3V_BUS
+3.3V_BUS
+3.3V_BUS
+3.3V_BUS
R14
R14
4.7K
4.7K
2 1
2 1
VIDEO BIOS
VIDEO BIOS
FIRMWARE
FIRMWARE
U11
U11
1
1
CE
2
2
SO
3
3
WP
4
4
GND
PM25LD010C-SCE
PM25LD010C-SCE
VDD HOLD SCK
GPIO_10_R
GPIO_10_R
C4
C4
0.1uF
0.1uF
6.3V
6.3V
2 1
2 1
PIN BASED STRAPS
PIN BASED STRAPS
E
D
+3.3V_BUS
DNI
DNI
MR10
MR10
U1
U1
+1.8V
+1.8V
AU1
AF15
AF15
180mA
180mA
10mA/bit
10mA/bit
C6
C6 1uF
1uF
6.3V
6.3V
2 1
2 1
C
+1.8V
+1.8V
R17
R17
R18
R18
C8
C8
1%
1%
21
21
1%
1%
6.3V
6.3V
221R
221R
21
21
110R
110R
21
21
0.1uF
0.1uF
VREFG
VREFG
VDDR4
AG11
AG11
VDDR4
AG13
AG13
VDDR4
AD12
AD12
VDDR4
AF11
AF11
VDDR4
AG15
AG15
VDDR4
AF12
AF12
VDDR4
AF13
AF13
VDDR4
AR1
AR1
NC#1
AP8
AP8
DBG_CNTL0
AW8
AW8
NC#2
AR3
AR3
NC#3
AR8
AR8
NC#4
AU8
AU8
NC#5
AH13 AP12
AH13 AP12
DBG_VREFG
OLAND M2 GDDR5
OLAND M2 GDDR5
DBG_DATA0 DBG_DATA1 DBG_DATA2 DBG_DATA3 DBG_DATA4 DBG_DATA5 DBG_DATA6 DBG_DATA7 DBG_DATA8
DBG_DATA9 DBG_DATA10 DBG_DATA11
DBG_DATA12 DBG_DATA13 DBG_DATA14 DBG_DATA15 DBG_DATA16 DBG_DATA17 DBG_DATA18 DBG_DATA19 DBG_DATA20 DBG_DATA21 DBG_DATA22 DBG_DATA23
AU1 AU3
AU3 AW3
AW3 AP6
AP6 AW5
AW5 AU5
AU5 AR6
AR6 AW6
AW6 AU6
AU6 AT7
AT7 AV7
AV7 AN7
AN7 AV9
AV9 AT9
AT9 AR10
AR10 AW10
AW10 AU10
AU10 AP10
AP10 AV11
AV11 AT11
AT11 AR12
AR12 AW12
AW12 AU12
AU12
DNI
DNI
MR11
MR11
+3.3V_BUS
4.7K
4.7K
21
21
4.7K
4.7K
21
21
DNI
DNI
R10
R10
R11
R11
4.7K
4.7K
21
21
4.7K
4.7K
21
21
V1SYNC
V1SYNC
H1SYNC
H1SYNC
OUT
OUT
AUD[1:0]:
9 6
9 6
9 6
9 6
AUD[1] HSYNC
AUD[1] HSYNC
AUD[0]
AUD[0]
VSYNC
VSYNC
AUD[1:0]:
00 - No audio function;
00 - No audio function;
01 - Audio for DisplayPort only;
01 - Audio for DisplayPort only;
10 - Audio for DisplayPort and HDMI if dongle is detected;
10 - Audio for DisplayPort and HDMI if dongle is detected;
11 - Audio for both DisplayPort and HDMI.
11 - Audio for both DisplayPort and HDMI.
HDMI must only be enabled on systems that are legally entitled
HDMI must only be enabled on systems that are legally entitled
. It is the responsibility of the system designer to
. It is the responsibility of the system designer to
ensure that the system is entitled to support this feature
ensure that the system is entitled to support this feature
C
B
A
Place the crossfire
Place the crossfire
testpoints near the ASIC and
testpoints near the ASIC and
not the connector
not the connector
Please pay attention to the grounding
Please pay attention to the grounding
strategies for these filter capacitors to
strategies for these filter capacitors to
maintain a close loop for current.
maintain a close loop for current.
+1.8V
+1.8V
+1.8V
+1.8V
+0.95V
+0.95V
9
+1.8V
+1.8V
B5
B5
120R
120R
B6
B6
120R
120R
B7
B7
120R
120R
21
21
21
21
21
21
C24
C24 10uF
10uF
6.3V
6.3V
2 1
2 1
150mA
150mA
200mA
200mA
75mA
75mA
+0.95V
+0.95V
140mA
140mA
75mA
75mA
+SPV10
+SPV10
C34
C34
4.7uF
4.7uF
6.3V
6.3V
2 1
2 1
2 1
2 1
C31
4.7uF
4.7uF
6.3V
6.3V
2 1
2 1
C18
4.7uF
4.7uF
6.3V
6.3V
2 1
2 1
2 1
2 1
C13
C13 10uF
10uF
6.3V
6.3V
C35
C35
4.7uF
4.7uF
6.3V
6.3V
2 1
2 1
C16 1uF
1uF
6.3V
6.3V
2 1
2 1
C19C18
C19 1uF
1uF
6.3V
6.3V
2 1
2 1
2 1
2 1
C14
C14 1uF
1uF
6.3V
6.3V
C21
C21 1uF
1uF
6.3V
6.3V
2 1
2 1
+SPV18
+SPV18
C26
C26 1uF
1uF
6.3V
6.3V
2 1
2 1
C17C16C31
C17
0.1uF
0.1uF
6.3V
6.3V
2 1
2 1
2 1
2 12 1
2 1
7
C15
C15
0.1uF
0.1uF
6.3V
6.3V
C20
C20
0.1uF
0.1uF
6.3V
6.3V
C22
C22
0.1uF
0.1uF
6.3V
6.3V
2 1
2 1
C27
C27
0.1uF
0.1uF
6.3V
6.3V
AM32
AM32
AN32
AN32
AM10
AM10
AN10
AN10
AN9
AN9
AN31
AN31
H7
H7 H8
H8
DP_VDDR
DP_VSSR
DP_VDDC
SPLL_PVDD
SPLL_PVSS
SPLL_VDDC
MPLL_PVDD MPLL_PVDD
U1
U1
OLAND M2 GDDR5
OLAND M2 GDDR5
NC_XTAL_PVDD NC_XTAL_PVSS
XO_IN2
XO_IN
XTALIN
XTALOUT
CLKTESTA CLKTESTB
AF30
AF30 AF31
AF31
AW35
AW35
AW34
AW34
AV33
AV33
AU34
AU34
AK10
AK10 AL10
AL10
XTALIN
XTALIN
XTALOUT
XTALOUT
1st source: 502G270001G
1st source: 502G270001G
R37
R37
1M
1M
1%
1%
2 1
2 1
Y1
Y1
3
42
3
42
1
1
C45
27.000MHz
27.000MHz
C23
21C45
21
21C23
21
58 6 3
12pF
12pF
12pF
12pF
50V
50V
50V
50V
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
Oland GPIO STRAP PLL
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
4
Oland GPIO STRAP PLL
Fri Oct 28 17:09:38 2016
Fri Oct 28 17:09:38 2016
NOTE
NOTE
215
OF
105_CXXX00_00A
105_CXXX00_00A
215
REV:
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
2
TITLE
TITLE
1
B
A
DOCUMENT NUMBER:
TITLE:
17ci203
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
SWAPLOCKB
SWAPLOCKA
PS_3
PS_2
PS_1
PS_0
NC_SVI2
NC_SVI2
NC_SVI2
NC#39
NC#28 NC#27 NC#26
NC#25
NC#24 NC#23
GENLK_VSYNC
GENLK_CLK
CEC_1
OUT
VSYNC
VSS1DI
VDD1DI
RSET
R
HSYNC
G
DDCVGADATA
DDCVGACLK
B
AVSSQ AVSSN
AVSSN
AVSSN
AVDD
OUT
8
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017091101 RMA工程課
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7
6
5 4 3
2
1
See BOM for qualified filters
See BOM for qualified filters
Pseudo differential RGB should be routed from the ASIC to the display
Pseudo differential RGB should be routed from the ASIC to the display
connector without switching reference plane or running over split plane.
U1
+1.8V
+1.8V
D D
+1.8V
+1.8V
B1700
B1700
2 1
2 1
120R
120R
B1701
B1701
2 1
2 1
120R
120R
+AVDD_DAC1
+AVDD_DAC1
C1700
C1702
C1702
AC33
+VDD1DI
+VDD1DI
C1701C1700
C1701
1uF
1uF
6.3V
6.3V
2 1
2 1
C1703
C1703
1uF
1uF
6.3V
6.3V
2 1
2 1
2 1
2 1
2 1
2 1
0.1uF
0.1uF
6.3V
6.3V
0.1uF
0.1uF
6.3V
6.3V
R1700
R1700
499R
499R
1%
1%
RSET
RSET
21
21
AC33
VDD1DI
AC34
AC34
VSS1DI
AD34
AD34
AVDD
AE34 AE38
AE34 AE38
AVSSQ AVSSN
AB34
AB34
RSET
U1
OLAND M2 GDDR5
OLAND M2 GDDR5
AVSSN
AVSSN
HSYNC VSYNC
DDCVGACLK
DDCVGADATA
AD39
AD39
R
AD37
AD37
AE36
AE36
G
AD35
AD35
G_DAC1
G_DAC1
AF37
AF37
B
AC36
AC36 AC38
AC38
AJ30
AJ30 AJ31
AJ31
B_DAC1
B_DAC1
R1711
R1711 150R
150R
1%
1%
2 1
2 12 1
R1712
R1712 150R
150R
1%
1%
2 1
VGA
VGA
VGA
VGA
R1713
R1713
150R
150R
1%
1%
2 1
2 1
VGA
VGA
connector without switching reference plane or running over split plane.
VGA(3230000000G)
VGA(3230000000G)
L1710
VGA
VGA
R1701
R1701
150R
150R
1%
1%
2 1
2 1
VGA
VGA
R1702
R1702
150R
150R
1%
1%
2 1
2 1
VGA(3230000000G)
VGA(3230000000G)
VGA
VGA
R1703
R1703
150R
150R
1%
1%
2 1
2 1
L1710
0.047uH
0.047uH
VGA(3230000000G)
VGA(3230000000G)
0.047uH
0.047uH
0.047uH
0.047uH
L1711
L1711
L1712
L1712
21
21
21
21
21
21
A_R_DAC1R_DAC1
A_R_DAC1R_DAC1
A_G_DAC1
A_G_DAC1
A_B_DAC1
A_B_DAC1
9
9
9
9
9
9
C
9 5
9 5 9 5
9 5
OUT OUT
H1SYNC
H1SYNC
V1SYNC
V1SYNC
B B
U1
PCIE3.0 Support: R1054=2K, R1053=8.45K
PCIE3.0 Support: R1054=2K, R1053=8.45K
PCIE2.0 Support: R1054=4.75K,R1053=NC
PCIE2.0 Support: R1054=4.75K,R1053=NC
DNI
DNI
DNI
DNI
21R1051
21 21R1052
21
21C1052
21
0.082uF
0.082uF
21R1053
21 21R1054
21
21C1054
21
0.1uF
0.1uF
21R1055
21 21R1056
21
21C1056
21
0.68uF
0.68uF
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
R1051 R1052
C1052
R1053 R1054
C1054
R1055 R1056
C1056
5.1K
5.1K
16V
16V
6.3V
6.3V
4V
4V
1%3.24K
1%3.24K
1%5.62K
1%5.62K
1%8.45k
1%8.45k
1%2K
1%2K
1%4.75K
1%4.75K
PS_0
PS_0
PS_1
PS_1
PS_2
PS_2
AM34
AM34 AD31
AD31 AG31
AG31 AD33
AD33
PS_0 PS_1 PS_2 PS_3
U1
CEC_1
GENLK_CLK
GENLK_VSYNC
AC30
AC30
AD29
AD29 AC29
AC29
C
A
1%8.45K
DNI
DNI
+1.8V
+1.8V
MEM CONFIG ID: SEE MLPS Bit[3:1]
MEM CONFIG ID: SEE MLPS Bit[3:1]
PS_3[3:1] PU[R1057] PD[R1058]
PS_3[3:1] PU[R1057] PD[R1058]
000 NC 4.75K_3160475100G
000 NC 4.75K_3160475100G
001 8.45K_3160845100G 2.00K_3160200100G
001 8.45K_3160845100G 2.00K_3160200100G
010 4.53K_3160453100G 2.00K_3160200100G
010 4.53K_3160453100G 2.00K_3160200100G
011 6.98K_3160398100G 4.99K_3160499100G
011 6.98K_3160398100G 4.99K_3160499100G
100 4.53_3160453100G 4.99K_3160499100G
100 4.53_3160453100G 4.99K_3160499100G
101 3.24K_3160324100G 5.62K_3160562100G
101 3.24K_3160324100G 5.62K_3160562100G
110 3.40K_3160340100G 10.0K_3160100200G
110 3.40K_3160340100G 10.0K_3160100200G
111 4.75K_3160475100G NC
111 4.75K_3160475100G NC
R1057 R1058
C1058
21R1057
21 21R1058
21
21C1058 AK21
21 AK21
0.082uF
0.082uF
DNI
DNI
8
1%8.45K
1%4.75K
1%4.75K
16V
16V
7
PS_3
PS_3
AF32
AF32
V13
V13 U13
U13
AG21
AG21 AC32
AC32 AA29
AA29 AC31
AC31 AD30
AD30 AD32
AD32
6
NC#25 NC#28 NC#27 NC#26 NC#24 NC#23 NC_SVI2 NC_SVI2 NC_SVI2
OLAND M2 GDDR5
OLAND M2 GDDR5
SWAPLOCKA SWAPLOCKB
NC#39
AJ21
AJ21
AF33
AF33
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2016
2016
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
5
4
Oland DAC and MLPS
Oland DAC and MLPS
Fri Oct 28 17:09:42 2016
Fri Oct 28 17:09:42 2016
OF
105_CXXX00_00A
105_CXXX00_00A
NOTE
NOTE
3
REV:
216
216
1.0
1.0
C
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
2
TITLE
TITLE
1
A
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
G4 G3 G2 G1PWR_RTN
DP_PWR
AUX_CHn
AUX_CHp
Hot_Det
GND_6
CONFIG 2
CONFIG 1
GND_3
GND_2
GND_1
GND_0
ML_Lane_3n
ML_Lane_2n
ML_Lane_1n
ML_Lane_0n
ML_Lane_3p
ML_Lane_2p
ML_Lane_1p
ML_Lane_0p
Y4
Y3
GND1
Y2
Y1
D
C
A GND
B
Y4
Y3
GND1
Y2
Y1
D
C
A GND
B
CASE
CASE
CASE
CASE
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
OUTININININININBIININBIINBI
NC#AW18
NC#AW28
NC#AK29
NC#AM21
NC#AM29
NC#AM30
NC#AK30
NC#AN21
NC#AL29
NC#AL30
NC#71
NC#70
NC#69
NC#68
NC#67
NC#66
NC#65
NC#64
NC#63
NC#62
NC#61
NC#60
NC#59
NC#58
NC#57
NC#56
NC#55
NC#54
NC#53
NC#52
NC#51
NC#50
NC#49
NC#48
NC#47
NC#46
NC#45
NC#44
NC#43
NC#42
NC#41
NC#40
NC#32
NC#31
NC#30
NC#29
NC#22
NC#21
NC#20
NC#19
NC#18
NC#17
NC#16
NC#15
NC#14
NC#13
NC#12
NC#11
NC#10
NC#9
NC#8
NC#7
NC#6
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
DP_VSS
8
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017091101 RMA工程課
石阿鋒 (00068760)
7
6
345
2
1
C
A
8
U1
U1
AN17
AN17
DP_VSS
AN19
AN19
DP_VSS
AN27
AN27
DP_VSS
AN29
AN29
DP_VSS
AP16
AP16
DP_VSS
AP17
AP17
DP_VSS
AP18
AP18
DP_VSS
AP19
AP19
DP_VSS
AP27
AP27
DP_VSS
AP28
AP28
DP_VSS
AP29
AP29
DP_VSS
AP30
AP30
DP_VSS
AR18
AR18
DP_VSS
AR28
AR28
DP_VSS
AV17
AV17
DP_VSS
AV27
AV27
DP_VSS
AW14
AW14
DP_VSS
AW16
AW16
DP_VSS
AW20
AW20
DP_VSS
AW22
AW22
DP_VSS
AW24
AW24
DP_VSS
AW26
AW26
DP_VSS
AW30
AW30
DP_VSS
AW32
AW32
DP_VSS
AL30
AL30
NC#AL30
AL29
AL29
NC#AL29
AN21
AN21
NC#AN21
AK30
AK30
NC#AK30
AM30
AM30
NC#AM30
AM29
AM29
NC#AM29
AM21
AM21
NC#AM21
AK29
AK29
NC#AK29
AW28
AW28
NC#AW28
AW18
AW18
NC#AW18
OLAND M2 GDDR5
OLAND M2 GDDR5
7
D2500
D2500
D2501
D2501
D2502
21C3530
21 21C3531
21 21C3532
21 21C3533
21 21C3534
21 21C3536
21 21C3537
21 21C3538
21
R2701
R2703
DP
DP
Q1804
Q1804 2N7002E
2N7002E
1
1
DPA_GND
DPA_GND
Q2701
Q2701 2N7002E
2N7002E HDMI
HDMI
D2502
D2505
D2505
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DP;HDMI
DP;HDMI
6.3V
6.3V
DP;HDMI
DP;HDMI
6.3V
6.3V
DP;HDMI
DP;HDMI
6.3V
6.3V
DP;HDMI
DP;HDMI
6.3V
6.3V
DP;HDMI
DP;HDMI
6.3V
6.3V
DP;HDMI
DP;HDMI
6.3V
6.3V
DP;HDMI
DP;HDMI
6.3V
6.3V
DP;HDMI
DP;HDMI
6.3V
6.3V
HDMI
HDMI
HDMI
HDMI
DPA_DONGLE_DET
DPA_DONGLE_DET
7
7
5
5
R2713
499R1%499R1%499R1%499R1%499R1%499R1%499R1%499R
499R1%499R1%499R1%499R1%499R1%499R1%499R1%499R
1%
HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI
1%
HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI
2 1
2 1
AH12
AH12
NC#6
AP13
AP13
NC#7
AP14
AP14
NC#8
AP15
AP15
NC#9
AT13
AT13
NC#10
AN24
AN24
NC#11
AP20
AP20
NC#12
AP21
AP21
NC#13
AP22
AP22
NC#14
AP23
AP23
NC#15
AP24
AP24
NC#16
AP25
AP25
NC#17
AP26
AP26
NC#18
AU18
AU18
NC#19
AU28
AU28
NC#20
AV19
AV19
NC#21
AV29
AV29
NC#22
L27
L27
NC#29
N12
N12
NC#30
AG12
AG12
NC#31
M12
M12
NC#32
AR24
AR24
NC#40
AR14
AR14
NC#41
AT25
AT25
NC#42
AT15
AT15
NC#43
AV25
AV25
NC#44
AV15
AV15
NC#45
AU26
AU26
NC#46
AU16
AU16
NC#47
AR26
AR26
NC#48
AR16
AR16
NC#49
AT27
AT27
NC#50
AT17
AT17
NC#51
AU30
NC#52 NC#53 NC#54 NC#55 NC#56 NC#57 NC#58 NC#59 NC#60 NC#61 NC#62 NC#63 NC#64 NC#65 NC#66 NC#67 NC#68 NC#69 NC#70 NC#71
6
AU30 AR20
AR20 AV31
AV31 AT21
AT21 AT31
AT31 AV21
AV21 AR32
AR32 AU22
AU22 AU32
AU32 AR22
AR22 AT33
AT33 AT23
AT23 AV23
AV23 AU24
AU24 AT29
AT29 AR30
AR30 AV13
AV13 AU14
AU14 AT19
AT19 AU20
AU20
8
8
IN
8
8
IN
8
8
IN
8
8
IN
8
8
IN
8
8
IN
DPA_A3P
21
21
1
1
8
8 8
8
R2528
R2529
DPA_A3P
BI BI
DP;HDMI
DP;HDMI
MR2529
MR2529
0R
0R
2
2
DNI
DNI
DNI
DNI
21
21
Q1801
Q1801 2N7002DW
2N7002DW
6
6
AUX2P
AUX2P
AUX2N
AUX2N
0R
0R
21R2528
21
0R
0R
21R2529
21
DP;HDMI
DP;HDMI
MMR2528
MMR2528
0R
0R
+5V_VESA
+5V_VESA
C3535
C3541
MMR2529
21
21
MMR2529
4
4
5
5
DP;HDMI
DP;HDMI
0R
0R
Q1801
Q1801
2 1
2 1
2N7002DW
2N7002DW
DP;HDMI
DP;HDMI
3
3
AUX1_BYPSS_EN
AUX1_BYPSS_EN
MMBT3904
MMBT3904
+12V_BUS
+12V_BUS
Q1803
Q1803
DP
DP
+12V_BUS
+12V_BUS
R1804
R1804 10K
10K
DP;HDMI
DP;HDMI
2 12 3
2 1
2 3
R2344
R2344
10K
10K HDMI
HDMI
2 1
2 1
2 1 2 1
TMDP_EN
TMDP_EN
C2344
C2344
0.1uF
0.1uF
16V
16V
8
8
IN
8
8
IN
DDC2CLK
8
8
IN
8
8
BI
DDC2CLK
DDC2DATA
DDC2DATA
DP;HDMI DP;HDMI
DP;HDMI DP;HDMI
MR2528
MR2528
0R
0R
5
21C3535
21
6.3V
6.3V 21C3541
21
6.3V
6.3V
1
1
0.1uF
0.1uF
0.1uF
0.1uF
C3530 C3531 C3532 C3533 C3534 C3536 C3537 C3538
DP
DP
DP
DP
+12V_BUS
+12V_BUS
R1805
R1805 10K
10K
DP
DP
2 1
2 12 3
3
2
1
1
7
7 7
7 7
7 7
7 7
7 7
7 7
7 7
7
3
3
2
2
4
ESD5V3U1U-02LRH
ESD5V3U1U-02LRH
12
12
ESD5V3U1U-02LRH
ESD5V3U1U-02LRH
12
12
ESD5V3U1U-02LRH
ESD5V3U1U-02LRH
12
12
ESD5V3U1U-02LRH
ESD5V3U1U-02LRH
12
12
2.2K
2.2K
21R2701
21
2.2K
2.2K
21R2703
21
Q2513
Q2513
MMBT3904 10K
MMBT3904 10K
DP;HDMI
DP;HDMI
HPD1
HPD1
OUT
R2715
R2714
2 1
2 1
2 1
2 1
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
R2524
DPA_AUXP
7
7
DPA_AUXP
R2522
DPA_AUXN
7
7
DPA_AUXN
R2523
+3.3V_BUS
+3.3V_BUS
2 3
2 3
R2530
R2530 10K
10K
DP;HDMI
DP;HDMI
2 1
2 1
R2716
2 1
2 1
Oland Connector HDMI/DP
Oland Connector HDMI/DP
Fri Oct 28 17:09:39 2016 1.0
Fri Oct 28 17:09:39 2016 1.0
OPTIONAL ESD protection diodes
OPTIONAL ESD protection diodes
DPA_AUXN
DPA_AUXN
DPA_AUXP
DPA_AUXP
DPA_DONGLE_DET
DPA_DONGLE_DET
HPD_DPA
HPD_DPA
DP
DP
DP
DP
DP
DP
2 1R2523
2 1
R2527
R2527
1
1
R2717
2 1
2 1
7 21
7 21
21R2524
21
21R2522
21
7
7 7
7
7
7
7
7
DPA_0PDPA_A0P
DPA_0PDPA_A0P
7
7
DPA_0NDPA_A0N
DPA_0NDPA_A0N
7
7
DPA_1PDPA_A1P
DPA_1PDPA_A1P
7
7
DPA_1NDPA_A1N
DPA_1NDPA_A1N
7
7
DPA_2PDPA_A2P
DPA_2PDPA_A2P
7
7
DPA_2NDPA_A2N
DPA_2NDPA_A2N
7
7
DPA_3P
DPA_3P
7
7
DPA_3NDPA_A3N
7
7
DPA_3NDPA_A3N
1M
1M
100K
100K
100K
100K
+3.3V_BUS
+3.3V_BUS
+3.3V_BUS
+3.3V_BUS
HPD_DPA
7
7
HPD_DPA
21
21
DP;HDMI
DP;HDMI
R2719
R2718
2 1
2 1
2 1
2 1
OF
105_CXXX00_00A
105_CXXX00_00A
3
DPA_3N
DPA_3N
7
7
DPA_3P
DPA_3P
7
7
DPA_2N
DPA_2N
7
7
DPA_2P
DPA_2P
7
7
DPA_1N
DPA_1N
7
7
DPA_1P
DPA_1P
7
7
DPA_0N
DPA_0N
7
7
DPA_0P
DPA_0P
7
7
DPA_0P
DPA_0P
R2720
R2720R2719R2718R2717R2716R2715R2714R2713
2 1
2 1
DPA_0N
DPA_0N
F2501
F2501
1.5A
1.5A
DPA_1P
DPA_1P
DPA_1N
DPA_1N
+3.3V_DPA
+3.3V_DPA
DP
DP
21
21
DPA_2P
DPA_2P
7
7 7
7
7
7
1
1
A
2
2
B GND
4
4
C
5
5
D
RCLAMP0524P
RCLAMP0524P
1
1
A
2
2
B GND
4
4
C
5
5
D
RCLAMP0524P
RCLAMP0524P
C2540
22uF
22uF
6.3V
6.3V
2 1
2 1
DP
DP
DPA_2N
DPA_2N
DPA_3P
DPA_3P
DPA_AUXP
DPA_AUXP
DPA_AUXN
DPA_AUXN
HPD_DPA
HPD_DPA
OVERLAP HDMI WITH DP D
OVERLAP HDMI WITH DP D
REV:
D2506
D2506
D2504
D2504
DPA_3N
DPA_3N
GND1
GND1
DPA_3N
Y1 Y2
Y3 Y4
Y1 Y2
Y3 Y4
DPA_1M
DPA_1M
R2526C2540
R2526
5.1M
5.1M
DP
DP
2 1
2 1
+5V_VESA
+5V_VESA
10
10 9
9 83
83 7
7 6
6
10
10 9
9 83
83 7
7 6
6
2 1
2 1
DPA_3N
7
7
DPA_3P
DPA_3P
7
7
DPA_2N
DPA_2N
7
7
DPA_2P
DPA_2P
7
7
DPA_1N
DPA_1N
7
7
DPA_1P
DPA_1P
7
7
DPA_0N
DPA_0N
7
7
DPA_0P
DPA_0P
7
7
DP
DP
J2501
J2501
1
1
ML_Lane_0p
2
2
GND_0
3
3
ML_Lane_0n
4
4
ML_Lane_1p
5
5
GND_1
6
6
ML_Lane_1n
7
7
ML_Lane_2p
8
8
GND_2
9
9
ML_Lane_2n
10
10
ML_Lane_3p
11
11
GND_3
12
12
ML_Lane_3n
13
13
CONFIG 1
14
14
CONFIG 2
15
15
AUX_CHp
16
16
GND_6
17
17
AUX_CHn
G4
18
18
Hot_Det
20
20
DP_PWR
19
19
DP_W/GASKET
DP_W/GASKET
DISPLAYPORT
DISPLAYPORT
HDMI
HDMI
MJ2501
MJ2501
1
1
P1
2
2
P2
3
3
P3
4
4
P4
5
5
P5
6
6
P6
7
7
P7
8
8
P8
9
9
P9
10
10
P10
11
11
P11
12
12
P12
13
13
P13
14
14
P14
15
15
P15
16
16
P16
17
17
P17
18
18
P18
19
19
P19
LONG_TYPE-2_HDMI_W/TAB
LONG_TYPE-2_HDMI_W/TAB
LONG_TYPE-2_HDMI
C2722
C2722 1uF
1uF
6.3V
6.3V
HDMI
HDMI
LONG_TYPE-2_HDMI
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the information included herein.
TITLE:
G4
G4
G3
G3
G3
G2
G2
G2
G1
G1
G1PWR_RTN
20
20
CASE
21
21
CASE
22
22
CASE
23
23
CASE
Advanced Micro Devices
TITLE
TITLE
2
DD
C
BB
A
1
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