Page 1
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
SHEET NO. SHEET NAME
TABLE OF CONTENTS
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
D D
TABLE OF CONTENTS
SHEET NO. SHEET NAME
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
C
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
TOC
TOC
BAFFIN PCIE
BAFFIN PCIE
BAFFIN MEMORY
BAFFIN MEMORY
GDDR5 x32 CHAB
GDDR5 x32 CHAB
BAFFIN POWER GND
BAFFIN POWER GND
BAFFIN GPIO STRAPS CLK
BAFFIN GPIO STRAPS CLK
Baffin TMDP_LVTMDP
Baffin TMDP_LVTMDP
MXM3.1 Interface
MXM3.1 Interface
VDDC
VDDC
VDDCI
VDDCI
MVDD
MVDD
0.8V REG
0.8V REG
1.8V REG
1.8V REG
BACO & CTF & PWR Managerment
BACO & CTF & PWR Managerment
DEBUG & THERMAL
DEBUG & THERMAL
BLOCK DIAGRAM
BLOCK DIAGRAM
REVISION HISTORY
REVISION HISTORY
C
B B
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
A
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
TOC
TOC
Wed Sep 09 16:50:44 2015
Wed Sep 09 16:50:44 2015
OF
105_C985xx_00B
105_C985xx_00B
REV:
171
171
1.0
1.0
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
A
NOTES:
8
7
6
5
4
NOTE
NOTE
3
2
1
Page 2
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
ININININOUT
OUT
OUT
IN
REV 0.91
symbol2
PCIE_ZVSS
PX_EN
PERSTB
PCIE_TX7P
PCIE_TX7N
PCIE_TX6P
PCIE_TX6N
PCIE_TX5P
PCIE_TX5N
PCIE_TX4P
PCIE_TX4N
PCIE_TX3P
PCIE_TX3N
PCIE_TX2P
PCIE_TX2N
PCIE_TX1P
PCIE_TX1N
PCIE_TX0P
PCIE_TX0N
PCIE_RX7P
PCIE_RX7N
PCIE_RX6P
PCIE_RX6N
PCIE_RX5P
PCIE_RX5N
PCIE_RX4P
PCIE_RX4N
PCIE_RX3P
PCIE_RX3N
PCIE_RX2P
PCIE_RX2N
PCIE_RX1P
PCIE_RX1N
PCIE_RX0P
PCIE_RX0N
PCIE_REFCLKP
PCIE_REFCLKN
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
D D
U1
U1
AT41
PCIE_RXP<0>
8 2
8 2
8 2
8 2
8 2
C
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
PCIE_RXP<0>
PCIE_RXN<0>
PCIE_RXN<0>
PCIE_RXP<1>
PCIE_RXP<1>
PCIE_RXN<1>
PCIE_RXN<1>
PCIE_RXP<2>
PCIE_RXP<2>
PCIE_RXN<2>
PCIE_RXN<2>
PCIE_RXP<3>
PCIE_RXP<3>
PCIE_RXN<3>
PCIE_RXN<3>
PCIE_RXP<4>
PCIE_RXP<4>
PCIE_RXN<4>
PCIE_RXN<4>
PCIE_RXP<5>
PCIE_RXP<5>
PCIE_RXN<5>
PCIE_RXN<5>
PCIE_RXP<6>
PCIE_RXP<6>
PCIE_RXN<6>
PCIE_RXN<6>
PCIE_RXP<7>
PCIE_RXP<7>
PCIE_RXN<7>
PCIE_RXN<7>
PCIE_REFCLKP
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_REFCLKN
AT41
AT40
AT40
AR41
AR41
AR40
AR40
AP41
AP41
AP40
AP40
AM41
AM41
AM40
AM40
AL41
AL41
AL40
AL40
AK41
AK41
AK40
AK40
AJ41
AJ41
AJ40
AJ40
AH41
AH41
AH40
AH40
AV33
AV33
AU33
AU33
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_REFCLKP
PCIE_REFCLKN
symbol2
REV 0.91
BAFFIN - REV 0.90
BAFFIN - REV 0.90
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PERSTB
PX_EN
PCIE_ZVSS
PCIE_TXP<0>
AV35
AV35
AU35
AU35
AU38
AU38
AU39
AU39
AR37
AR37
AR38
AR38
AN37
AN37
AN38
AN38
AL37
AL37
AL38
AL38
AJ37
AJ37
AJ38
AJ38
AG37
AG37
AG38
AG38
AE37
AE37
AE38
AE38
AV41
AV41
AC41
AC41
AU41
AU41
PCIE_TXP<0>
PCIE_TXN<0>
PCIE_TXN<0>
PCIE_TXP<1>
PCIE_TXP<1>
PCIE_TXN<1>
PCIE_TXN<1>
PCIE_TXP<2>
PCIE_TXP<2>
PCIE_TXN<2>
PCIE_TXN<2>
PCIE_TXP<3>
PCIE_TXP<3>
PCIE_TXN<3>
PCIE_TXN<3>
PCIE_TXP<4>
PCIE_TXP<4>
PCIE_TXN<4>
PCIE_TXN<4>
PCIE_TXP<5>
PCIE_TXP<5>
PCIE_TXN<5>
PCIE_TXN<5>
PCIE_TXP<6>
PCIE_TXP<6>
PCIE_TXN<6>
PCIE_TXN<6>
PCIE_TXP<7>
PCIE_TXP<7>
PCIE_TXN<7>
PCIE_TXN<7>
PERSTb_RST#
PERSTb_RST#
PX_EN
PX_EN
PCIE_ZVSS
PCIE_ZVSS
KEEP THE TRACE SHORT
KEEP THE TRACE SHORT
R151
R151
R150
R150
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
DNI
DNI
200R
200R
PCIE_REFCLKP
8 2
8 2
IN
8 2
8 2
IN
8 2
8 2
IN
8 2
8 2
IN
8 2
8 2
OUT
8 2
8 2
OUT
8 9 14
8 9 14
IN
8 14
8 14
OUT
5%
1K
5%
1K
1%
1%
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_REFCLKN
PCIE_RXP<7..0>
PCIE_RXP<7..0>
PCIE_RXN<7..0>
PCIE_RXN<7..0>
PCIE_TXP<7..0>
PCIE_TXP<7..0>
PCIE_TXN<7..0>
PCIE_TXN<7..0>
C
B B
A
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
BAFFIN PCIE
BAFFIN PCIE
Mon Dec 14 13:53:01 2015
Mon Dec 14 13:53:01 2015
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
REV:
172
172
1.0
1.0
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
A
8
7
6
5
4
3
2
1
Page 3
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
BIBIBIBIBIBIBIBIBIBIBIBIBI
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBI
REV 0.91
symbol4
DRAM_RSTB
DQB1_31
DQB1_30
DQB1_29
DQB1_28
DQB1_27
DQB1_26
DQB1_25
DQB1_24
DQB1_23
DQB1_22
DQB1_21
DQB1_20
DQB1_19
DQB1_18
DQB1_17
DQB1_16
DQB1_15
DQB1_14
DQB1_13
DQB1_12
DQB1_11
DQB1_10
DQB1_9
DQB1_8
DQB1_7
DQB1_6
DQB1_5
DQB1_4
DQB1_3
DQB1_2
DQB1_1
DQB1_0
DQB0_31
DQB0_30
DQB0_29
DQB0_28
DQB0_27
DQB0_26
DQB0_25
DQB0_24
DQB0_23
DQB0_22
DQB0_21
DQB0_20
DQB0_19
DQB0_18
DQB0_17
DQB0_16
DQB0_15
DQB0_14
DQB0_13
DQB0_12
DQB0_11
DQB0_10
DQB0_9
DQB0_8
DQB0_7
DQB0_6
DQB0_5
DQB0_4
DQB0_3
DQB0_2
DQB0_1
DQB0_0
WEB1BWEB0B
WCKB1_1
WCKB1_0
WCKB1B_1
WCKB1B_0
WCKB0_1
WCKB0_0
WCKB0B_1
WCKB0B_0
RASB1BRASB0B
MVREFDBMEM_CALRB
MAB1_9
MAB1_8
MAB1_7
MAB1_6
MAB1_5
MAB1_4
MAB1_3
MAB1_2
MAB1_1
MAB1_0
MAB0_9
MAB0_8
MAB0_7
MAB0_6
MAB0_5
MAB0_4
MAB0_3
MAB0_2
MAB0_1
MAB0_0
EDCB1_3
EDCB1_2
EDCB1_1
EDCB1_0
EDCB0_3
EDCB0_2
EDCB0_1
EDCB0_0
DDBIB1_3
DDBIB1_2
DDBIB1_1
DDBIB1_0
DDBIB0_3
DDBIB0_2
DDBIB0_1
DDBIB0_0
CSB1B_0CSB0B_0
CLKB1B
CLKB1
CLKB0B
CLKB0
CKEB1CKEB0
CASB1BCASB0B
ADBIB1ADBIB0
REV 0.91
symbol3
DRAM_RSTA
DQA1_31
DQA1_30
DQA1_29
DQA1_28
DQA1_27
DQA1_26
DQA1_25
DQA1_24
DQA1_23
DQA1_22
DQA1_21
DQA1_20
DQA1_19
DQA1_18
DQA1_17
DQA1_16
DQA1_15
DQA1_14
DQA1_13
DQA1_12
DQA1_11
DQA1_10
DQA1_9
DQA1_8
DQA1_7
DQA1_6
DQA1_5
DQA1_4
DQA1_3
DQA1_2
DQA1_1
DQA1_0
DQA0_31
DQA0_30
DQA0_29
DQA0_28
DQA0_27
DQA0_26
DQA0_25
DQA0_24
DQA0_23
DQA0_22
DQA0_21
DQA0_20
DQA0_19
DQA0_18
DQA0_17
DQA0_16
DQA0_15
DQA0_14
DQA0_13
DQA0_12
DQA0_11
DQA0_10
DQA0_9
DQA0_8
DQA0_7
DQA0_6
DQA0_5
DQA0_4
DQA0_3
DQA0_2
DQA0_1
DQA0_0
WEA1BWEA0B
WCKA1_1
WCKA1_0
WCKA1B_1
WCKA1B_0
WCKA0_1
WCKA0_0
WCKA0B_1
WCKA0B_0
RASA1BRASA0B
MVREFDAMEM_CALRA
MAA1_9
MAA1_8
MAA1_7
MAA1_6
MAA1_5
MAA1_4
MAA1_3
MAA1_2
MAA1_1
MAA1_0
MAA0_9
MAA0_8
MAA0_7
MAA0_6
MAA0_5
MAA0_4
MAA0_3
MAA0_2
MAA0_1
MAA0_0
EDCA1_3
EDCA1_2
EDCA1_1
EDCA1_0
EDCA0_3
EDCA0_2
EDCA0_1
EDCA0_0
DDBIA1_3
DDBIA1_2
DDBIA1_1
DDBIA1_0
DDBIA0_3
DDBIA0_2
DDBIA0_1
DDBIA0_0
CSA1B_0CSA0B_0
CLKA1B
CLKA1
CLKA0B
CLKA0
CKEA1CKEA0
CASA1BCASA0B
ADBIA1ADBIA0
BI
OUTBIBIBIBIBIOUTBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIOUTBIOUTBIBIBIBI
OUTBIBIBIBIBIBIBIBI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
U1
DQA0_<31..0>
4 3
4 3
BI
D D
4 3
4 3
OUT
C
B B
DQA0_<31..0>
MAA0_<8..0>
MAA0_<8..0>
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
21R3600
21
120R
R3600
120R
DNI
DNI
4
4
3
3
DQA0_<0>
DQA0_<0>
0
0
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
1%
1%
DQA0_<1>
DQA0_<1>
1
1
DQA0_<2>
DQA0_<2>
2
2
DQA0_<3>
DQA0_<3>
3
3
DQA0_<4>
DQA0_<4>
4
4
DQA0_<5>
DQA0_<5>
5
5
DQA0_<6>
DQA0_<6>
6
6
DQA0_<7>
DQA0_<7>
7
7
DQA0_<8>
DQA0_<8>
8
8
DQA0_<9>
DQA0_<9>
9
9
DQA0_<10>
DQA0_<10>
10
10
DQA0_<11>
DQA0_<11>
11
11
DQA0_<12>
DQA0_<12>
12
12
DQA0_<13>
DQA0_<13>
13
13
DQA0_<14>
DQA0_<14>
14
14
DQA0_<15>
DQA0_<15>
15
15
DQA0_<16>
DQA0_<16>
16
16
DQA0_<17>
DQA0_<17>
17
17
DQA0_<18>
DQA0_<18>
18
18
DQA0_<19>
DQA0_<19>
19
19
DQA0_<20>
DQA0_<20>
20
20
DQA0_<21>
DQA0_<21>
21
21
DQA0_<22>
DQA0_<22>
22
22
DQA0_<23>
DQA0_<23>
23
23
DQA0_<24>
DQA0_<24>
24
24
DQA0_<25>
DQA0_<25>
25
25
DQA0_<26>
DQA0_<26>
26
26
DQA0_<27>
DQA0_<27>
27
27
DQA0_<28>
DQA0_<28>
28
28
DQA0_<29>
DQA0_<29>
29
29
DQA0_<30>
DQA0_<30>
30
30
DQA0_<31>
DQA0_<31>
31
31
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
WCKA0_0
WCKA0_0
WCKA0b_0
WCKA0b_0
WCKA0_1
WCKA0_1
WCKA0b_1
WCKA0b_1
EDCA0_0
EDCA0_0
EDCA0_1
EDCA0_1
EDCA0_2
EDCA0_2
EDCA0_3
EDCA0_3
DDBIA0_0
DDBIA0_0
DDBIA0_1
DDBIA0_1
DDBIA0_2
DDBIA0_2
DDBIA0_3
DDBIA0_3
ADBIA0
ADBIA0
CSA0b_0
CSA0b_0
CASA0b
CASA0b
RASA0b
RASA0b
WEA0b
WEA0b
CKEA0
CKEA0
CLKA0
CLKA0
CLKA0b
CLKA0b
MEM_CALRA
MEM_CALRA
MAA0_<0>
MAA0_<0>
3 4
3 4
3 4
MAA0_<1>
MAA0_<1>
3 4
3 4
MAA0_<2>
MAA0_<2>
3 4
3 4
3 4
MAA0_<3>
MAA0_<3>
3 4
3 4
MAA0_<4>
MAA0_<4>
3 4
3 4
MAA0_<5>
MAA0_<5>
3 4
3 4
MAA0_<6>
MAA0_<6>
3 4
3 4
MAA0_<7>
MAA0_<7>
3 4
3 4
MAA0_<8>
MAA0_<8>
L34
L34
L37
L37
L38
L38
J35
J35
G37
G37
E38
E38
E35
E35
D35
D35
H41
H41
H40
H40
G41
G41
G40
G40
E40
E40
D41
D41
D40
D40
C41
C41
C40
C40
B39
B39
A39
A39
B38
B38
B36
B36
A36
A36
B35
B35
A35
A35
B33
B33
B32
B32
A32
A32
B31
B31
A30
A30
B29
B29
B28
B28
A28
A28
G25
G25
H25
H25
E27
E27
D27
D27
D29
D29
H27
H27
H23
H23
E23
E23
D25
D25
H29
H29
D33
D33
E33
E33
A34
A34
B34
B34
G38
G38
F41
F41
B37
B37
A31
A31
J38
J38
F40
F40
A38
A38
B30
B30
E31
E31
D31
D31
L32
L32
symbol3
DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8
MAA0_9
WCKA0_0
WCKA0B_0
WCKA0_1
WCKA0B_1
EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3
DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3
CLKA0
CLKA0B
DRAM_RSTA
BAFFIN - REV 0.90
BAFFIN - REV 0.90
REV 0.91
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31
MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7
MAA1_8
MAA1_9
WCKA1_0
WCKA1B_0
WCKA1_1
WCKA1B_1
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3
DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3
ADBIA1ADBIA0
CSA1B_0CSA0B_0
CASA1BCASA0B
RASA1BRASA0B
WEA1BWEA0B
CKEA1CKEA0
CLKA1
CLKA1B
MVREFDAMEM_CALRA
DQA1_<31..0>
4
4
DQA1_<0>
DQA1_<0>
3
3
B27
B27
DQA1_<1>
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
DQA1_<1>
A27
A27
DQA1_<2>
DQA1_<2>
B26
B26
DQA1_<3>
DQA1_<3>
A26
A26
DQA1_<4>
DQA1_<4>
A24
A24
DQA1_<5>
DQA1_<5>
B23
B23
DQA1_<6>
DQA1_<6>
A23
A23
DQA1_<7>
DQA1_<7>
B22
B22
DQA1_<8>
DQA1_<8>
B20
B20
DQA1_<9>
DQA1_<9>
A20
A20
DQA1_<10>
DQA1_<10>
B19
B19
DQA1_<11>
DQA1_<11>
A19
A19
DQA1_<12>
DQA1_<12>
B17
B17
DQA1_<13>
DQA1_<13>
A16
A16
DQA1_<14>
DQA1_<14>
B16
B16
DQA1_<15>
DQA1_<15>
A15
A15
DQA1_<16>
DQA1_<16>
B15
B15
DQA1_<17>
DQA1_<17>
A14
A14
DQA1_<18>
DQA1_<18>
B14
B14
DQA1_<19>
DQA1_<19>
B13
B13
DQA1_<20>
DQA1_<20>
A11
A11
DQA1_<21>
DQA1_<21>
B11
B11
DQA1_<22>
DQA1_<22>
A10
A10
DQA1_<23>
DQA1_<23>
B10
B10
DQA1_<24>
DQA1_<24>
B8
B8
DQA1_<25>
DQA1_<25>
A7
A7
DQA1_<26>
DQA1_<26>
B7
B7
DQA1_<27>
DQA1_<27>
A6
A6
DQA1_<28>
DQA1_<28>
A4
A4
DQA1_<29>
DQA1_<29>
B4
B4
DQA1_<30>
DQA1_<30>
A3
A3
DQA1_<31>
DQA1_<31>
B3
B3
E15
3 4
3 4
E15
MAA1_<0>
MAA1_<0>
H15
3 4
3 4
H15
MAA1_<1>
MAA1_<1>
G13
3 4
3 4
G13
MAA1_<2>
MAA1_<2>
D13
3 4
3 4
D13
MAA1_<3>
MAA1_<3>
H11
3 4
3 4
H11
MAA1_<4>
MAA1_<4>
H13
3 4
3 4
H13
MAA1_<5>
MAA1_<5>
3 4
H17
3 4
H17
MAA1_<6>
MAA1_<6>
3 4
G17
3 4
G17
MAA1_<7>
MAA1_<7>
3 4
D15
3 4
D15
MAA1_<8>
MAA1_<8>
E11
E11
A22
A22
WCKA1_0
WCKA1_0
B21
B21
WCKA1b_0
WCKA1b_0
A8
A8
WCKA1_1
WCKA1_1
B9
B9
WCKA1b_1
WCKA1b_1
B24
B24
EDCA1_0
EDCA1_0
A18
A18
EDCA1_1
EDCA1_1
B12
EDCA1_2
EDCA1_2
B12
B6
EDCA1_3
EDCA1_3
B6
B25
B25
DDBIA1_0
DDBIA1_0
B18
B18
DDBIA1_1
DDBIA1_1
A12
A12
DDBIA1_2
DDBIA1_2
B5
B5
DDBIA1_3
DDBIA1_3
H19H21
H19H21
ADBIA1
ADBIA1
E7H31
E7H31
CSA1b_0
CSA1b_0
D17D23
D17D23
CASA1b
CASA1b
D19D21
RASA1b
RASA1b
D19D21
D11G29
D11G29
WEA1b
WEA1b
E19G21
E19G21
CKEA1
CKEA1
D7
D7
CLKA1
CLKA1
D9
D9
CLKA1b
CLKA1b
K17K15
K17K15
USE INTERNAL VREF USE INTERNAL VREF
USE INTERNAL VREF USE INTERNAL VREF
MVREFD = 0.7 * VDDR1
MVREFD = 0.7 * VDDR1
MVREFDA
MVREFDA
DQA1_<31..0>
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
MAA1_<8..0>
MAA1_<8..0>
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
BI
OUT
2 1
2 12 1
2 1
R3601
R3601
40.2R
40.2R
1%
1%
DNI
DNI
R3602
R3602
100R
100R
1%
1%
DNI
DNI
4 3
4 3
4 3
4 3
4 3
4 3
DRAM_RST_B
4
4
OUT
DRAM_RST_B
R3615
21R3615
21
49.9R
49.9R
BI
OUT
1%
1%
DQB0_<31..0>
DQB0_<31..0>
MAB0_<8..0>
MAB0_<8..0>
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
R3610
R3614
C3611
C3611
120pF
120pF
50V
50V
2 1
2 1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
120R
120R
10R
10R
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
21R3610
21
DNI
DNI
21R3614
21
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
1%
1%
1%
1%
R3613
R3613
5.1K
5.1K
1%
1%
2 1
2 1
4
4
3
3
DQB0_<0>
DQB0_<0>
DQB0_<1>
DQB0_<1>
DQB0_<2>
DQB0_<2>
DQB0_<3>
DQB0_<3>
DQB0_<4>
DQB0_<4>
DQB0_<5>
DQB0_<5>
DQB0_<6>
DQB0_<6>
DQB0_<7>
DQB0_<7>
DQB0_<8>
DQB0_<8>
DQB0_<9>
DQB0_<9>
DQB0_<10>
DQB0_<10>
DQB0_<11>
DQB0_<11>
DQB0_<12>
DQB0_<12>
DQB0_<13>
DQB0_<13>
DQB0_<14>
DQB0_<14>
DQB0_<15>
DQB0_<15>
DQB0_<16>
DQB0_<16>
DQB0_<17>
DQB0_<17>
DQB0_<18>
DQB0_<18>
DQB0_<19>
DQB0_<19>
DQB0_<20>
DQB0_<20>
DQB0_<21>
DQB0_<21>
DQB0_<22>
DQB0_<22>
DQB0_<23>
DQB0_<23>
DQB0_<24>
DQB0_<24>
DQB0_<25>
DQB0_<25>
DQB0_<26>
DQB0_<26>
DQB0_<27>
DQB0_<27>
DQB0_<28>
DQB0_<28>
DQB0_<29>
DQB0_<29>
DQB0_<30>
DQB0_<30>
3 4
3 4
MAB0_<0>
MAB0_<0>
3 4
3 4
MAB0_<1>
MAB0_<1>
3 4
3 4
MAB0_<2>
MAB0_<2>
3 4
3 4
MAB0_<3>
MAB0_<3>
3 4
3 4
MAB0_<4>
MAB0_<4>
3 4
3 4
MAB0_<5>
MAB0_<5>
3 4 3 4
3 4 3 4
MAB0_<6> MAB1_<6>
MAB0_<6> MAB1_<6>
3 4
3 4
MAB0_<7>
MAB0_<7>
3 4
3 4
MAB0_<8>
MAB0_<8>
WCKB0_0
WCKB0_0
WCKB0b_0
WCKB0b_0
WCKB0_1
WCKB0_1
WCKB0b_1
WCKB0b_1
EDCB0_0
EDCB0_0
EDCB0_1
EDCB0_1
EDCB0_2
EDCB0_2
EDCB0_3
EDCB0_3
DDBIB0_0
DDBIB0_0
DDBIB0_1
DDBIB0_1
DDBIB0_2
DDBIB0_2
DDBIB0_3
DDBIB0_3
ADBIB0
ADBIB0
CSB0b_0
CSB0b_0
CASB0b
CASB0b
RASB0b
RASB0b
WEB0b
WEB0b
CKEB0
CKEB0
CLKB0
CLKB0
CLKB0b
CLKB0b
MEM_CALRB
MEM_CALRB
DRAM_RST_B_R
DRAM_RST_B_R
AB2
AB2
AC1
AC1
AC2
AC2
AD1
AD1
AF1
AF1
AF2
AF2
AG1
AG1
AG2
AG2
AB1
AB1
AA2
AA2
AD2
AD2
AE2
AE2
AM11
AM11
C2
C2
DQB0_0
C1
C1
DQB0_1
D2
D2
DQB0_2
D1
D1
DQB0_3
F1
F1
DQB0_4
G2
G2
DQB0_5
G1
G1
DQB0_6
H2
H2
DQB0_7
K2
K2
DQB0_8
K1
K1
DQB0_9
L2
L2
DQB0_10
L1
L1
DQB0_11
N2
N2
DQB0_12
P2
P2
DQB0_13
P1
P1
DQB0_14
R2
R2
DQB0_15
R1
R1
DQB0_16
T2
T2
DQB0_17
T1
T1
DQB0_18
U2
U2
DQB0_19
W1
W1
DQB0_20
W2
W2
DQB0_21
Y1
Y1
DQB0_22
Y2
Y2
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
R5
R5
MAB0_0
R8
R8
MAB0_1
N7
N7
MAB0_2
N4
N4
MAB0_3
L8
L8
MAB0_4
N8
N8
MAB0_5
U8
U8
MAB0_6
U7
U7
MAB0_7
R4
R4
MAB0_8
L5
L5
MAB0_9
H1
H1
WCKB0_0
J2
J2
WCKB0B_0
WCKB0_1
WCKB0B_1
F2
F2
EDCB0_0
M2
M2
EDCB0_1
V1
V1
EDCB0_2
EDCB0_3
E2
E2
DDBIB0_0
M1
M1
DDBIB0_1
V2
V2
DDBIB0_2
DDBIB0_3
G4
G4
CLKB0
J4
J4
CLKB0B
DRAM_RSTB
BAFFIN - REV 0.90
BAFFIN - REV 0.90
U1
U1U1
symbol4
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31
MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MAB1_7
MAB1_8
MAB1_9
WCKB1_0
WCKB1B_0
WCKB1_1
WCKB1B_1
EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3
DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3
ADBIB1ADBIB0
CSB1B_0CSB0B_0
CASB1BCASB0B
RASB1BRASB0B
WEB1BWEB0B
CKEB1CKEB0
CLKB1
CLKB1B
MVREFDBMEM_CALRB
REV 0.91
DQB1_<31..0>
4
4
3
3
DQB1_<0>
DQB1_<0>
AH1
AH1
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3
4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4 3 4
3 4 3 4
DQB1_<1>
DQB1_<1>
AH2
AH2
DQB1_<2>
DQB1_<2>
AJ2
AJ2
DQB1_<3>
DQB1_<3>
AK1
AK1
DQB1_<4>
DQB1_<4>
AL2
AL2
DQB1_<5>
DQB1_<5>
AM1
AM1
DQB1_<6>
DQB1_<6>
AM2
AM2
DQB1_<7>
DQB1_<7>
AN2
AN2
DQB1_<8>
DQB1_<8>
AR1
AR1
DQB1_<9>
DQB1_<9>
AR2
AR2
DQB1_<10>
DQB1_<10>
AT1
AT1
DQB1_<11>
DQB1_<11>
AT2
AT2
DQB1_<12>
DQB1_<12>
AV2
AV2
DQB1_<13>
DQB1_<13>
AW1
AW1
DQB1_<14>
DQB1_<14>
AW2
AW2
DQB1_<15>
DQB1_<15>
AY3
AY3
DQB1_<16>
DQB1_<16>
BA3
BA3
DQB1_<17>
DQB1_<17>
AY4
AY4
DQB1_<18>
DQB1_<18>
BA4
BA4
DQB1_<19>
DQB1_<19>
AY5
AY5
DQB1_<20>
DQB1_<20>
BA7
BA7
DQB1_<21>
DQB1_<21>
AY7
AY7
DQB1_<22>
DQB1_<22>
AY8
AY8
DQB1_<23>
DQB1_<23>
BA8
BA8
DQB1_<24>
DQB1_<24>
AR4
AR4
DQB1_<25>
DQB1_<25>
AR5
AR5
DQB1_<26>
DQB1_<26>
AU4
AU4
AU7
AU7
DQB1_<27>
DQB1_<27>
DQB1_<28>
DQB1_<28>
AN8
AN8
DQB1_<29>
DQB1_<29>
AV11
AV11
DQB1_<30>
DQB1_<30>
AU11
AU11
DQB1_<31>DQB0_<31>
AP11
AP11
DQB1_<31>DQB0_<31>
3 4
AE7
AE7
AE8
AE8
AG5
AG5
AG4
AG4
AJ4
AJ4
AG8
AG8
AC8
AC8
AC5
AC5
AE4
AE4
AJ8
AJ8
AP1
AP1
AP2
AP2
AN4
AN4
AN5
AN5
AL1
AL1
AU2
AU2
BA6
BA6
AV7
AV7
AK2
AK2
AV1
AV1
AY6
AY6
AV9
AV9
AA8W8
AA8W8
AL8G5
AL8G5
AC4U4
AC4U4
AA4W4
AA4W4
AJ7L4
AJ7L4
AA7W5
AA7W5
AL5
AL5
AL4
AL4
U10R10
U10R10
3 4
MAB1_<0>
MAB1_<0>
3 4
3 4
MAB1_<1>
MAB1_<1>
3 4
3 4
MAB1_<2>
MAB1_<2>
3 4
3 4
MAB1_<3>
MAB1_<3>
3 4
3 4
MAB1_<4>
MAB1_<4>
3 4
3 4
MAB1_<5>
MAB1_<5>
3 4
3 4
MAB1_<7>
MAB1_<7>
3 4
3 4
MAB1_<8>
MAB1_<8>
WCKB1_0
WCKB1_0
WCKB1b_0
WCKB1b_0
WCKB1_1
WCKB1_1
WCKB1b_1
WCKB1b_1
EDCB1_0
EDCB1_0
EDCB1_1
EDCB1_1
EDCB1_2
EDCB1_2
EDCB1_3
EDCB1_3
DDBIB1_0
DDBIB1_0
DDBIB1_1
DDBIB1_1
DDBIB1_2
DDBIB1_2
DDBIB1_3
DDBIB1_3
ADBIB1
ADBIB1
CSB1b_0
CSB1b_0
CASB1b
CASB1b
RASB1b
RASB1b
WEB1b
WEB1b
CKEB1
CKEB1
CLKB1
CLKB1
CLKB1b
CLKB1b
MVREFD = 0.7 * VDDR1
MVREFD = 0.7 * VDDR1
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MVREFDB
MVREFDB
DQB1_<31..0>
MAB1_<8..0>
MAB1_<8..0>
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
BI
OUT
4 3 4 3
4 3 4 3
+MVDD+MVDD
+MVDD+MVDD
4 3
4 3
2 1
2 12 1
2 1
R3611
R3611
40.2R
40.2R
1%
1%
DNI
DNI
R3612
R3612
100R
100R
1%
1%
DNI
DNI
C
AMD - PLATFORM HARDWARE ENG
A
8
7
6
5
4
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
BAFFIN MEMORY
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
BAFFIN MEMORY
Mon Dec 14 13:52:57 2015
Mon Dec 14 13:52:57 2015
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
3
REV:
173
173
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
2
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
1
A
Page 4
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
INININ
OUT
OUT
OUT
OUTBIBIBIBI
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
INBIIN
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
INININININININ
OUT
OUT
OUT
OUT
OUTBIBIINBIBIININININININININININBIINOUTININ
OUT
OUTININ
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
ININOUT
OUTININBIBI
OUT
OUTBIBIINININININININININBIBIOUT
OUTBIBIININININININININININ
BI
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
OUTBIOUT
IN
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
17ci203
7
6
5 4 3
2
1
+MVDD
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
+MVDD
+MVDD
+MVDD
174
174
3 4
3 4
+MVDD
+MVDD
3 4
3 4
+MVDD
+MVDD
+MVDD
+MVDD
BI
OUT
R2603
R2603
R2604
R2604
REV:
DQB1_<31..0>
DQB1_<31..0>
L3
L3
MF = 1
MF = 1
L1
L1
MAB1_<8..0>
MAB1_<8..0>
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1%
1%
60.4R
60.4R
1%
1%
60.4R
60.4R
3
3
3
3
3
3
3
3
3
3
R2600
R2600
3 4
3 4
R2614
R2614
R2615
R2615
C2602
C2602
3
3
1.0
1.0
U2600
DQB1_<18>
DQB1_<18>
3 4
3 4
DQB1_<16>
DQB1_<16>
3 4
3 4
DQB1_<19>
DQB1_<19>
3 4
3 4
DQB1_<17>
DQB1_<17>
3 4
3 4
DQB1_<20>
DQB1_<20>
3 4
3 4
DQB1_<21>
DQB1_<21>
3 4
3 4
DQB1_<22>
DQB1_<22>
3 4
3 4
DQB1_<23>
DQB1_<23>
3 4
3 4
DQB1_<27>
DQB1_<27>
3 4
3 4
DQB1_<25>
DQB1_<25>
3 4
3 4
DQB1_<26>
DQB1_<26>
3 4
3 4
DQB1_<24>
DQB1_<24>
3 4
3 4
DQB1_<28>
DQB1_<28>
3 4
3 4
DQB1_<30>
DQB1_<30>
3 4
3 4
DQB1_<29>
DQB1_<29>
3 4
3 4
DQB1_<31>
DQB1_<31>
3 4
3 4
DQB1_<14>
DQB1_<14>
3 4
3 4
DQB1_<15>
DQB1_<15>
3 4
3 4
DQB1_<13>
DQB1_<13>
3 4
3 4
DQB1_<12>
DQB1_<12>
3 4
3 4
DQB1_<11>
DQB1_<11>
3 4
3 4
DQB1_<9>
DQB1_<9>
3 4
3 4
DQB1_<10>
DQB1_<10>
3 4
3 4
DQB1_<8>
DQB1_<8>
3 4
3 4
DQB1_<0>
DQB1_<0>
3 4
3 4
DQB1_<7>
DQB1_<7>
3 4
3 4
DQB1_<1>
DQB1_<1>
3 4
3 4
DQB1_<6>
DQB1_<6>
3 4
3 4
DQB1_<2>
DQB1_<2>
3 4
3 4
DQB1_<4>
DQB1_<4>
3 4
3 4
DQB1_<3>
DQB1_<3>
3 4
3 4
DQB1_<5>
DQB1_<5>
3 4
3 4
MAB1_<8>
MAB1_<8>
MAB1_<0>
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
IN
IN
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
ININ
1%
1%
120R
120R
IN
1%
1%
2.37K
2.37K
1%
1%
5.49K
5.49K
6.3V
6.3V
1uF
1uF
IN
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
MAB1_<0>
MAB1_<1>
MAB1_<1>
MAB1_<3>
MAB1_<3>
MAB1_<2>
MAB1_<2>
MAB1_<5>
MAB1_<5>
MAB1_<4>
MAB1_<4>
MAB1_<6>
MAB1_<6>
MAB1_<7>
MAB1_<7>
WCKB1_0
WCKB1_0
WCKB1b_0
WCKB1b_0
WCKB1_1
WCKB1_1
WCKB1B_1
WCKB1B_1
EDCB1_2
EDCB1_2
EDCB1_3
EDCB1_3
EDCB1_1
EDCB1_1
EDCB1_0
EDCB1_0
DDBIB1_2
DDBIB1_2
DDBIB1_3
DDBIB1_3
DDBIB1_1
DDBIB1_1
DDBIB1_0
DDBIB1_0
CASB1b
CASB1b
RASB1b
RASB1b
CKEB1
CKEB1
CLKB1b
CLKB1b
CLKB1
CLKB1
WEB1b
WEB1b
CSB1b_0
CSB1b_0
ZQ_B1
ZQ_B1
DRAM_RST_B
DRAM_RST_B
VREFC_B1
VREFC_B1
ADBIB1
ADBIB1
Advanced Micro Devices
2015
2015
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0
M13
M13
DQ23__DQ15
M11
M11
DQ22__DQ14
N13
N13
DQ21__DQ13
N11
N11
DQ20__DQ12
T13
T13
DQ19__DQ11
T11
T11
DQ18__DQ10
V13
V13
DQ17__DQ9
V11
V11
DQ16__DQ8
F13
F13
DQ15__DQ23
F11
F11
DQ14__DQ22
E13
E13
DQ13__DQ21
E11
E11
DQ12__DQ20
B13
B13
DQ11__DQ19
B11
B11
DQ10__DQ18
A13
A13
DQ9__DQ17
A11
A11
DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9
K10
K10
A5_BA1__A3_BA3
K11
K11
A4_BA2__A2_BA0
H10
H10
A3_BA3__A5_BA1
H11
H11
A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0
R13
R13
EDC2__EDC1
C13
C13
EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0#
P13
P13
DBI2#__DBI1#
D13
D13
DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE#
J11
J11
CK#
J12
J12
CK
G12
G12
CS#__WE#
L12
L12
WE#__CS#
J13
J13
ZQ
J10
J10
SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1
A10
A10
VREFD1
V10
V10
VREFD2
J14
J14
VREFC
J4
J4
ABI#
U2600U2400
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
2
+MVDD
+MVDD
U2000
6.3V
6.3V
6.3V
6.3V
21C2022
21C2021
0.1uF
0.1uF
0.1uF
0.1uF
C2022
C2021
6.3V
6.3V
6.3V
6.3V
21C2024
21C2023
0.1uF
0.1uF
0.1uF
0.1uF
C2024
C2023
U2000
6.3V
6.3V
6.3V
6.3V
21C2026
21C2025
0.1uF
0.1uF
0.1uF
0.1uF
C2026
C2025
6.3V
6.3V
21C2027
21212121212121
0.1uF
0.1uF
C2027
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
21C2028
21
4V10uF
4V10uF
C2028
BI
L1
L1
D D
MF = 0
MF = 0
L3
C
B B
A
3 4
3 4
+MVDD
+MVDD
+MVDD
+MVDD
OUT
R2003
R2003
R2004
R2004
8
L3
MAA0_<8..0>
MAA0_<8..0>
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1%
60.4R
1%
60.4R
1%
60.4R
1%
60.4R
3
3
3
3
3
3
3
3
3
3
R2000
R2000
3 4
3 4
R2014
R2014
R2015
R2015
C2002
C2002
3
3
+MVDD
+MVDD
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4 3 4
3 4 3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
IN
IN
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
120R
120R
IN
1%
2.37K
1%
2.37K
1%
5.49K
1%
5.49K
6.3V
1uF
6.3V
1uF
IN IN
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
21C2013
21C2012
21C2011
21C2010
21
C2013
C2012
C2011
C2010
1%
1%
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
21C2015
21C2014
C2015
C2014
DQA0_<31>
DQA0_<31>
DQA0_<24>
DQA0_<24>
DQA0_<30>
DQA0_<30>
DQA0_<25>
DQA0_<25>
DQA0_<29>
DQA0_<29>
DQA0_<27>
DQA0_<27>
DQA0_<28>
DQA0_<28>
DQA0_<26>
DQA0_<26>
DQA0_<17>
DQA0_<17>
DQA0_<16>
DQA0_<16>
DQA0_<18>
DQA0_<18>
DQA0_<19>
DQA0_<19>
DQA0_<20>
DQA0_<20>
DQA0_<22>
DQA0_<22>
DQA0_<21>
DQA0_<21>
DQA0_<23>
DQA0_<23>
DQA0_<5>
DQA0_<5>
DQA0_<6>
DQA0_<6>
DQA0_<4>
DQA0_<4>
DQA0_<7>
DQA0_<7>
DQA0_<3>
DQA0_<3>
DQA0_<1>
DQA0_<1>
DQA0_<2>
DQA0_<2>
DQA0_<0>
DQA0_<0>
DQA0_<13>
DQA0_<13>
DQA0_<15>
DQA0_<15>
DQA0_<12>
DQA0_<12>
DQA0_<14>
DQA0_<14>
DQA0_<10>
DQA0_<10>
DQA0_<11>
DQA0_<11>
DQA0_<9>
DQA0_<9>
DQA0_<8>
DQA0_<8>
MAA0_<8>
MAA0_<8>
MAA0_<7>
MAA0_<7>
MAA0_<6>
MAA0_<6>
MAA0_<5>
MAA0_<5>
MAA0_<4>
MAA0_<4>
MAA0_<3>
MAA0_<3>
MAA0_<2>
MAA0_<2>
MAA0_<1>
MAA0_<1>
MAA0_<0>
MAA0_<0>
WCKA0b_0
WCKA0b_0
WCKA0b_1
WCKA0b_1
DDBIA0_3
DDBIA0_3
DDBIA0_2
DDBIA0_2
DDBIA0_0
DDBIA0_0
DDBIA0_1
DDBIA0_1
DRAM_RST_B
DRAM_RST_B
VREFC_A0
VREFC_A0
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
21C2030
21C2017
21C2016
21
21212121212121
C2030
C2017
C2016
WCKA0_0
WCKA0_0
WCKA0_1
WCKA0_1
EDCA0_3
EDCA0_3
EDCA0_2
EDCA0_2
EDCA0_0
EDCA0_0
EDCA0_1
EDCA0_1
RASA0b
RASA0b
CASA0b
CASA0b
CKEA0
CKEA0
CLKA0b
CLKA0b
CLKA0
CLKA0
CSA0b_0
CSA0b_0
WEA0b
WEA0b
ZQ_A0
ZQ_A0
ADBIA0
ADBIA0
4V10uF
4V10uF
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0
M13
M13
DQ23__DQ15
M11
M11
DQ22__DQ14
N13
N13
DQ21__DQ13
N11
N11
DQ20__DQ12
T13
T13
DQ19__DQ11
T11
T11
DQ18__DQ10
V13
V13
DQ17__DQ9
V11
V11
DQ16__DQ8
F13
F13
DQ15__DQ23
F11
F11
DQ14__DQ22
E13
E13
DQ13__DQ21
E11
E11
DQ12__DQ20
B13
B13
DQ11__DQ19
B11
B11
DQ10__DQ18
A13
A13
DQ9__DQ17
A11
A11
DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9
K10
K10
A5_BA1__A3_BA3
K11
K11
A4_BA2__A2_BA0
H10
H10
A3_BA3__A5_BA1
H11
H11
A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0
R13
R13
EDC2__EDC1
C13
C13
EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0#
P13
P13
DBI2#__DBI1#
D13
D13
DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE#
J11
J11
CK#
J12
J12
CK
G12
G12
CS#__WE#
L12
L12
WE#__CS#
J13
J13
ZQ
J10
J10
SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1
A10
A10
VREFD1
V10
V10
VREFD2
J14
J14
VREFC
J4
J4
ABI#
+MVDD +MVDD
+MVDD +MVDD
6.3V
6.3V
21C2020
21
0.1uF
0.1uF
C2020
7
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
6.3V
6.3V
1uF
1uF
21C2210
21
C2210
+MVDD
+MVDD
+MVDD
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
21C2212
21C2211
C2212
C2211
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
21C2214
21C2213
C2214
C2213
3 4 3 4
3 4 3 4
3 4
3 4
+MVDD
+MVDD
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
21C2216
21C2215
C2216
C2215
BI
OUT
+MVDD
+MVDD
+MVDD
+MVDD
6.3V
6.3V
1uF
1uF
21C2217
21212121212121
C2217
R2203
R2203
R2204
R2204
+MVDD
+MVDD
21C2230
21
C2230
DQA1_<31..0>DQA0_<31..0>
DQA1_<31..0>DQA0_<31..0>
MF = 1
MF = 1
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
21C2222
21C2221
21C2220
212121
4V10uF
4V10uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C2222
C2221
C2220
L3
L3
L1
L1
MAA1_<8..0>
MAA1_<8..0>
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1%
1%
60.4R
60.4R
1%
1%
60.4R
60.4R
3
3
3
3
3
3
3
3
3
3
R2200
R2200
3 4
3 4
R2214
R2214
R2215
R2215
C2202
C2202
3
3
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
21C2227
21C2226
21C2225
21C2224
21C2223
2121212121
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C2227
C2226
C2225
C2224
C2223
6
IN
IN
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
120R
120R
IN
2.37K
2.37K
5.49K
5.49K
1uF
1uF
1%
1%
1%
1%
1%
1%
6.3V
6.3V
21C2228
21
C2228
DQA1_<26>
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
4V
4V
10uF
10uF
DQA1_<26>
DQA1_<25>
DQA1_<25>
DQA1_<27>
DQA1_<27>
DQA1_<24>
DQA1_<24>
DQA1_<31>
DQA1_<31>
DQA1_<28>
DQA1_<28>
DQA1_<29>
DQA1_<29>
DQA1_<30>
DQA1_<30>
DQA1_<19>
DQA1_<19>
DQA1_<17>
DQA1_<17>
DQA1_<18>
DQA1_<18>
DQA1_<16>
DQA1_<16>
DQA1_<22>
DQA1_<22>
DQA1_<20>
DQA1_<20>
DQA1_<23>
DQA1_<23>
DQA1_<21>
DQA1_<21>
DQA1_<13>
DQA1_<13>
DQA1_<15>
DQA1_<15>
DQA1_<12>
DQA1_<12>
DQA1_<14>
DQA1_<14>
DQA1_<11>
DQA1_<11>
DQA1_<8>
DQA1_<8>
DQA1_<10>
DQA1_<10>
DQA1_<9>
DQA1_<9>
DQA1_<0>
DQA1_<0>
DQA1_<6>
DQA1_<6>
DQA1_<1>
DQA1_<1>
DQA1_<7>
DQA1_<7>
DQA1_<2>
DQA1_<2>
DQA1_<4>
DQA1_<4>
DQA1_<3>
DQA1_<3>
DQA1_<5>
DQA1_<5>
MAA1_<8>
MAA1_<8>
MAA1_<0>
MAA1_<0>
MAA1_<1>
MAA1_<1>
MAA1_<3>
MAA1_<3>
MAA1_<2>
MAA1_<2>
MAA1_<5>
MAA1_<5>
MAA1_<4>
MAA1_<4>
MAA1_<6>
MAA1_<6>
MAA1_<7>
MAA1_<7>
WCKA1_0
WCKA1_0
WCKA1b_0
WCKA1b_0
WCKA1_1
WCKA1_1
WCKA1b_1
WCKA1b_1
EDCA1_3
EDCA1_3
EDCA1_2
EDCA1_2
EDCA1_1
EDCA1_1
EDCA1_0
EDCA1_0
DDBIA1_3
DDBIA1_3
DDBIA1_2
DDBIA1_2
DDBIA1_1
DDBIA1_1
DDBIA1_0
DDBIA1_0
CASA1b
CASA1b
RASA1b
RASA1b
CKEA1
CKEA1
CLKA1b
CLKA1b
CLKA1
CLKA1
WEA1b
WEA1b
CSA1b_0
CSA1b_0
ZQ_A1
ZQ_A1
DRAM_RST_B
DRAM_RST_B
VREFC_A1
VREFC_A1
ADBIA1
ADBIA1
+MVDD +MVDD
+MVDD +MVDD
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
21C2414
21C2413
21C2412
21C2411
21C2410
21
C2414
C2413
C2412
C2411
C2410
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
21C2416
21C2415
C2416
C2415
M2
M2
M4
M4
N2
N2
N4
N4
T2
T2
T4
T4
V2
V2
V4
V4
M13
M13
M11
M11
N13
N13
N11
N11
T13
T13
T11
T11
V13
V13
V11
V11
F13
F13
F11
F11
E13
E13
E11
E11
B13
B13
B11
B11
A13
A13
A11
A11
F2
F2
F4
F4
E2
E2
E4
E4
B2
B2
B4
B4
A2
A2
A4
A4
J5
J5
K4
K4
K5
K5
K10
K10
K11
K11
H10
H10
H11
H11
H5
H5
H4
H4
D4
D4
D5
D5
P4
P4
P5
P5
R2
R2
R13
R13
C13
C13
C2
C2
P2
P2
P13
P13
D13
D13
D2
D2
G3
G3
L3
L3
J3
J3
J11
J11
J12
J12
G12
G12
L12
L12
J13
J13
J10
J10
J2
J2
J1
J1
A5
A5
V5
V5
A10
A10
V10
V10
J14
J14
J4
J4
6.3V
6.3V
1uF
1uF
21C2417
21212121212121
C2417
21C2430
21
C2430
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
6.3V
6.3V
21C2420
21
4V10uF
4V10uF
0.1uF
0.1uF
C2420
6.3V
6.3V
6.3V
6.3V
21C2422
21C2421
0.1uF
0.1uF
0.1uF
0.1uF
C2422
C2421
6.3V
6.3V
6.3V
6.3V
21C2424
21C2423
0.1uF
0.1uF
0.1uF
0.1uF
C2424
C2423
U2200
U2200
6.3V
6.3V
21C2425
0.1uF
0.1uF
C2425
5
6.3V
6.3V
6.3V
6.3V
21C2427
21C2426
21212121212121
0.1uF
0.1uF
0.1uF
0.1uF
C2427
C2426
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
21C2428
21
4V10uF
4V10uF
C2428
+MVDD
3 4
3 4
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
21C2613
21C2612
C2613
C2612
3 4
3 4
+MVDD
+MVDD
+MVDD
+MVDD
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
21C2615
21C2614
C2615
C2614
BI
OUT
6.3V
6.3V
1uF
1uF
21C2616
C2616
R2403
R2403
R2404
R2404
6.3V
6.3V
1uF
1uF
21C2617
21212121212121
C2617
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
+MVDD
+MVDD
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
+MVDD +MVDD
+MVDD +MVDD
6.3V
6.3V
6.3V
6.3V
1uF
1uF
1uF
1uF
21C2611
21C2610
21
C2611
C2610
DQB0_<31..0>
DQB0_<31..0>
MF = 0
MF = 0
MAB0_<8..0>
MAB0_<8..0>
60.4R
60.4R
60.4R
60.4R
R2400
R2400
R2414
R2414
R2415
R2415
C2402
C2402
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
21C2622
21C2621
21C2620
21C2630
21
21
4V10uF
4V10uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C2622
C2621
C2620
C2630
L1
L1
L3
L3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1%
1%
1%
1%
3
3
3
3
3
3
3
3
3
3
3 4
3 4
3
3
6.3V
6.3V
6.3V
6.3V
21C2624
21C2623
0.1uF
0.1uF
0.1uF
0.1uF
C2624
C2623
OUT
OUT
OUT
OUT
BI
BI
BI
BI
120R
120R
2.37K
2.37K
5.49K
5.49K
1uF
1uF
6.3V
6.3V
21C2625
0.1uF
0.1uF
C2625
4
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
6.3V
6.3V
6.3V
6.3V
21C2627
21C2626
21212121212121
0.1uF
0.1uF
0.1uF
0.1uF
C2627
C2626
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
3 4
1%
1%
1%
1%
1%
1%
6.3V
6.3V
21C2628
21
C2628
DQB0_<31>
DQB0_<31>
DQB0_<25>
DQB0_<25>
DQB0_<30>
DQB0_<30>
DQB0_<24>
DQB0_<24>
DQB0_<29>
DQB0_<29>
DQB0_<27>
DQB0_<27>
DQB0_<28>
DQB0_<28>
DQB0_<26>
DQB0_<26>
DQB0_<18>
DQB0_<18>
DQB0_<16>
DQB0_<16>
DQB0_<19>
DQB0_<19>
DQB0_<17>
DQB0_<17>
DQB0_<20>
DQB0_<20>
DQB0_<23>
DQB0_<23>
DQB0_<21>
DQB0_<21>
DQB0_<22>
DQB0_<22>
DQB0_<12>
DQB0_<12>
DQB0_<14>
DQB0_<14>
DQB0_<13>
DQB0_<13>
DQB0_<15>
DQB0_<15>
DQB0_<11>
DQB0_<11>
DQB0_<10>
DQB0_<10>
DRAM_RST_B
DRAM_RST_B
4V10uF
4V10uF
M2
M2
M4
M4
N2
N2
N4
N4
T2
T2
T4
T4
V2
V2
V4
V4
M13
M13
M11
M11
N13
N13
N11
N11
T13
T13
T11
T11
V13
V13
V11
V11
F13
F13
F11
F11
E13
E13
E11
E11
B13
DQB0_<9>
DQB0_<9>
DQB0_<8>
DQB0_<8>
DQB0_<5>
DQB0_<5>
DQB0_<6>
DQB0_<6>
DQB0_<4>
DQB0_<4>
DQB0_<7>
DQB0_<7>
DQB0_<0>
DQB0_<0>
DQB0_<3>
DQB0_<3>
DQB0_<2>
DQB0_<2>
DQB0_<1>
DQB0_<1>
MAB0_<8>
MAB0_<8>
MAB0_<7>
MAB0_<7>
MAB0_<6>
MAB0_<6>
MAB0_<5>
MAB0_<5>
MAB0_<4>
MAB0_<4>
MAB0_<3>
MAB0_<3>
MAB0_<2>
MAB0_<2>
MAB0_<1>
MAB0_<1>
MAB0_<0>
MAB0_<0>
WCKB0_0
WCKB0_0
WCKB0b_0
WCKB0b_0
WCKB0_1
WCKB0_1
WCKB0b_1
WCKB0b_1
EDCB0_3
EDCB0_3
EDCB0_2
EDCB0_2
EDCB0_1
EDCB0_1
EDCB0_0
EDCB0_0
DDBIB0_3
DDBIB0_3
DDBIB0_2
DDBIB0_2
DDBIB0_1
DDBIB0_1
DDBIB0_0
DDBIB0_0
RASB0b
RASB0b
CASB0b
CASB0b
CKEB0
CKEB0
CLKB0b
CLKB0b
CLKB0
CLKB0
CSB0b_0
CSB0b_0
WEB0B
WEB0B
ZQ_B0
ZQ_B0
VREFC_B0
VREFC_B0
ADBIB0
ADBIB0
B13
B11
B11
A13
A13
A11
A11
F2
F2
F4
F4
E2
E2
E4
E4
B2
B2
B4
B4
A2
A2
A4
A4
J5
J5
K4
K4
K5
K5
K10
K10
K11
K11
H10
H10
H11
H11
H5
H5
H4
H4
D4
D4
D5
D5
P4
P4
P5
P5
R2
R2
R13
R13
C13
C13
C2
C2
P2
P2
P13
P13
D13
D13
D2
D2
G3
G3
L3
L3
J3
J3
J11
J11
J12
J12
G12
G12
L12
L12
J13
J13
J10
J10
J2
J2
J1
J1
A5
A5
V5
V5
A10
A10
V10
V10
J14
J14
J4
J4
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
U2400
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
GDDR5 x32 CHAB
GDDR5 x32 CHAB
Mon Dec 14 13:53:00 2015
Mon Dec 14 13:53:00 2015
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
3
+MVDD
+MVDD
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
+MVDD
+MVDD
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
1
C
A
Page 5
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
OUT
OUT
OUT
REV 0.91
symbol13
VSS#226
VSS#225
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VSS#116
VSS#224
VSS#223
VSS#222
VSS#221
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VSS#217
VSS#216
VSS#215
VSS#214
VSS#213
VSS#212
VSS#211
VSS#210
VSS#209
VSS#208
VSS#207
VSS#206
VSS#205
VSS#204
VSS#203
VSS#202
VSS#201
VSS#200
VSS#199
VSS#198
VSS#197
VSS#196
VSS#195
VSS#194
VSS#193
VSS#192
VSS#191
VSS#190
VSS#189
VSS#188
VSS#187
VSS#186
VSS#185
VSS#184
VSS#183
VSS#182
VSS#181
VSS#180
VSS#179
VSS#178
VSS#177
VSS#176
VSS#175
VSS#174
VSS#173
VSS#172
VSS#171
VSS#170
VSS#169
VSS#168
VSS#167
VSS#166
VSS#165
VSS#164
VSS#163
VSS#162
VSS#161
VSS#160
VSS#159
VSS#158
VSS#157
VSS#156
VSS#155
VSS#154
VSS#153
VSS#152
VSS#151
VSS#150
VSS#149
VSS#148
VSS#147
VSS#146
VSS#145
VSS#144
VSS#143
VSS#142
VSS#141
VSS#140
VSS#139
VSS#138
VSS#137
VSS#136
VSS#135
VSS#134
VSS#133
VSS#132
VSS#131
VSS#130
VSS#129
VSS#128
VSS#127
VSS#126
VSS#125
VSS#124
VSS#123
VSS#122
VSS#121
VSS#120
VSS#119
VSS#118
VSS#117
REV 0.91
symbol12
VSS#114
VSS#113
VSS#112
VSS#111
VSS#110
VSS#109
VSS#108
VSS#107
VSS#106
VSS#105
VSS#104
VSS#103
VSS#102
VSS#101
VSS#100
VSS#99
VSS#98
VSS#97
VSS#96
VSS#95
VSS#94
VSS#93
VSS#92
VSS#91
VSS#90
VSS#89
VSS#88
VSS#87
VSS#86
VSS#85
VSS#84
VSS#83
VSS#82
VSS#81
VSS#80
VSS#79
VSS#78
VSS#77
VSS#76
VSS#75
VSS#74
VSS#73
VSS#72
VSS#71
VSS#70
VSS#69
VSS#68
VSS#67
VSS#66
VSS#65
VSS#64
VSS#63
VSS#62
VSS#61
VSS#60
VSS#59
VSS#58
VSS#57
VSS#56
VSS#55
VSS#54
VSS#53
VSS#52
VSS#51
VSS#50
VSS#49
VSS#48
VSS#47
VSS#46
VSS#45
VSS#44
VSS#43
VSS#42
VSS#41
VSS#40
VSS#39
VSS#38
VSS#37
VSS#36
VSS#35
VSS#34
VSS#33
VSS#32
VSS#31
VSS#30
VSS#29
VSS#28
VSS#27
VSS#26
VSS#25
VSS#24
VSS#23
VSS#22
VSS#21
VSS#20
VSS#19
VSS#18
VSS#17
VSS#16
VSS#15
VSS#14
VSS#13
VSS#12
VSS#11
VSS#10
VSS#9
VSS#8
VSS#7
VSS#6
VSS#5
VSS#4
VSS#3
VSS#2
VSS#1
VSS#0
REV 0.91
symbol14
VDD_08
VSS
VSS
VDD_08#5
VDD_08#4
VDD_18#2
VDD_18#1
VDD_18#0
VDD_08#3
VDD_08#2
VDD_08#1
VMEMIO#10
VMEMIO#9
VMEMIO#8
VMEMIO#7
VMEMIO#6
VMEMIO#5
VMEMIO#4
VMEMIO#3
VMEMIO#2
VMEMIO#1
VMEMIO#0
VDD_08#0
REV 0.91
symbol9
VDDC#67
VDDC#57
VDDC#66
VDDC#65
VDDC#64
VDDC#63
VDDC#62
VDDC#61
VDDC#60
VDDC#59
VDDC#58
VDDC#56
VDDC#55
VDDC#54
VDDC#53
VDDC#52
VDDC#51
VDDC#50
VDDC#49
VDDC#48
VDDC#47
VDDC#46
VDDC#45
VDDC#44
VDDC#43
VDDC#42
VDDC#41
VDDC#40
VDDC#39
VDDC#38
VDDC#37
VDDC#36
VDDC#35
VDDC#34
VDDC#33
VDDC#32
VDDC#31
VDDC#30
VDDC#29
VDDC#28
VDDC#27
VDDC#26
VDDC#25
VDDC#24
VDDC#23
VDDC#22
VDDC#21
VDDC#20
VDDC#19
VDDC#18
VDDC#17
VDDC#16
VDDC#15
VDDC#14
VDDC#13
VDDC#12
VDDC#11
VDDC#10
VDDC#9
VDDC#8
VDDC#7
VDDC#6
VDDC#5
VDDC#4
VDDC#3
VDDC#2
VDDC#1
VDDC#0
VDDCI#6
VDDCI#8
VDDCI#7
VDDCI#5
VDDCI#4
VDDCI#3
VDDCI#2
VDDCI#1
VDDCI#0
FB_VDDCI
FB_VMEMIO
FB_VSS
FB_VDDC
OUT
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
+VDDC
+VDDC
N13
N13
VDDC#0
N15
N15
VDDC#1
N21
N21
C1200
1uF 1uF 1uF 1uF 1uF
1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V
6.3V 6.3V 6.3V 6.3V
2 1
2 1
2 1
2 12 1
D D
C1205
C1205
1uF
1uF
6.3V
6.3V
2 1
C1221
C1220
C1220
47uF
47uF
47uF
47uF
2.5V
2.5V
2.5V
2.5V
2 1
2 12 12 12 12 1
2 1
2 1
C1226
C1225
C1225
47uF
47uF
47uF
47uF
2.5V
2.5V
2.5V
2.5V
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
C1222
47uF
47uF
2.5V
2.5V
C1227
C1227C1226
47uF
47uF
2.5V
2.5V
2 1
2 1
2 1
2 1
C1223
47uF
47uF
2.5V
2.5V
2 1
2 1
2 1
2 1
C1204C1203C1202C1201C1200
6.3V
6.3V
C1224C1223C1222C1221
C1224
47uF
47uF
2.5V
2.5V
C1204
C1203
C1202
C1201
C
B B
A
+MVDD
+MVDD
C1314
C1313
C1312
C1311
C1310
C1310
1uF
1uF 1uF
1uF
1uF 1uF
6.3V
6.3V
6.3V
C1316
1uF
1uF
6.3V
6.3V
C1321
C1321
22uF
22uF
2.5V
2.5V
2 1
2 1
2 1
2 1
6.3V
C1317
1uF
1uF
6.3V
6.3V
2 1
2 1
2 1
2 1
6.3V
6.3V
2 1
2 1
2 1
C1315
C1315
1uF
1uF
6.3V
6.3V
2 1
2 1
2 12 1
C1320
C1320
22uF
22uF
2.5V
2.5V
2 1
2 1
8
7
C1314C1313C1312C1311
1uF 1uF
1uF 1uF
6.3V 6.3V
6.3V 6.3V
2 1
2 1
C1319
C1318
C1319C1318C1317C1316
1uF
1uF
1uF
1uF
6.3V
6.3V
6.3V
6.3V
2 1
2 1
N23
N23
N29
N29
N31
N31
R13
R13
R15
R15
R21
R21
R23
R23
R29
R29
R31
R31
U13
U13
U15
U15
U21
U21
U23
U23
U29
U29
U31
U31
W13
W13
W15
W15
W21
W21
W23
W23
W29
W29
W31
W31
AA13
AA13
AA15
AA15
AA21
AA21
AA23
AA23
AA29
AA29
AA31
AA31
AC13
AC13
AC15
AC15
AC21
AC21
AC23
AC23
AC29
AC29
AC31
AC31
AE13
AE13
AE15
AE15
AE21
AE21
AE23
AE23
AE29
AE29
AE31
AE31
AG13
AG13
AG15
AG15
AG21
AG21
AG23
AG23
AG29
AG29
AG31
AG31
AJ13
AJ13
AJ15
AJ15
AJ17
AJ17
AJ19
AJ19
AJ21
AJ21
AJ23
AJ23
AJ25
AJ25
AJ27
AJ27
AJ29
AJ29
AJ31
AJ31
AL13
AL13
AL15
AL15
AL17
AL17
AL19
AL19
AL21
AL21
AL23
AL23
AL25
AL25
AL27
AL27
AL29
AL29
AL31
AL31
K11
K11
K13
K13
K19
K19
K23
K23
K27
K27
K31
K31
L10
L10
N10
N10
W10
W10
AC10
AC10
AG10
AG10
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
VDDC#59
VDDC#60
VDDC#61
VDDC#62
VDDC#63
VDDC#64
VDDC#65
VDDC#66
VDDC#67
BAFFIN - REV 0.90
BAFFIN - REV 0.90
VMEMIO#0
VMEMIO#1
VMEMIO#2
VMEMIO#3
VMEMIO#4
VMEMIO#5
VMEMIO#6
VMEMIO#7
VMEMIO#8
VMEMIO#9
VMEMIO#10
BAFFIN - REV 0.90
BAFFIN - REV 0.90
symbol9
REV 0.91
symbol14
REV 0.91
6
U1
U1
U1
U1
VDDCI#0
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
FB_VMEMIO
FB_VDDCI
FB_VDDC
FB_VSS
VDD_18#0
VDD_18#1
VDD_18#2
VDD_08#0
VDD_08#1
VDD_08#2
VDD_08#3
VDD_08#4
VDD_08#5
VDD_08
VSS
VSS
L13
L13
L17
L17
L21
L21
L25
L25
L29
L29
N11
N11
U11
U11
AA11
AA11
AE11
AE11
C3
C3
AV13
AV13
AR13
AR13
AU13
AU13
AM15
AM15
AP15
AP15
AR15
AR15
AC32
AC32
AG32
AG32
AG35
AG35
AJ32
AJ32
AJ34
AJ34
AL34
AL34
W32
W32
AM23
AM23
AM17
AM17
2 1
2 1
C1251
1uF 1uF 1uF
1uF 1uF 1uF
6.3V 6.3V 6.3V
6.3V 6.3V 6.3V
2 1
2 1
2 1
2 12 1
C1271
C1270
C1271C1270
22uF
22uF
22uF
22uF
2.5V
2.5V
2.5V
2.5V
2 1
C1400
6.3V
6.3V
2 1
2 1
2 1
2 1
1uF 1uF 1uF 1uF
1uF 1uF 1uF 1uF
6.3V
6.3V
C1451C1450
C1451C1450
1uF
1uF
C1401
C1401C1400
1uF1uF
1uF1uF
C1253C1252C1251
2 1
2 1
FB_VMEMIO
FB_VMEMIO
FB_VDDCI
FB_VDDCI
FB_VDDC
FB_VDDC
FB_VSSC
FB_VSSC
C1402
C1402
1uF
1uF
6.3V6.3V
6.3V6.3V
2 1
2 1
6.3V6.3V
6.3V6.3V
C1253
C1252
5
+VDDCI
+VDDCI
11
11
OUT
9
9
OUT
9
9
OUT
9
9
OUT
C1456C1455C1454C1453C1452
C1456C1455C1454C1453C1452
1uF 1uF
6.3V 6.3V 6.3V 6.3V
6.3V 6.3V 6.3V 6.3V
1uF 1uF
+1.8V
+1.8V
+0.8V
+0.8V
4
A2
A2
VSS#0
A5
A5
VSS#1
A9
A9
VSS#2
A13
A13
VSS#3
A17
A17
VSS#4
A21
A21
VSS#5
A25
A25
VSS#6
A29
A29
VSS#7
A33
A33
VSS#8
A37
A37
VSS#9
A40
A40
VSS#10
B1
B1
VSS#11
B40
B40
VSS#12
B41
B41
VSS#13
C5
C5
VSS#14
C7
C7
VSS#15
C9
C9
VSS#16
C11
C11
VSS#17
C13
C13
VSS#18
C15
C15
VSS#19
C17
C17
VSS#20
C19
C19
VSS#21
C21
C21
VSS#22
C23
C23
VSS#23
C25
C25
VSS#24
C27
C27
VSS#25
C29
C29
VSS#26
C31
C31
VSS#27
C33
C33
VSS#28
C35
C35
VSS#29
C37
C37
VSS#30
C39
C39
VSS#31
E1
E1
VSS#32
E3
E3
VSS#33
E4
E4
VSS#34
E9
E9
VSS#35
E13
E13
VSS#36
E17
E17
VSS#37
E21
E21
VSS#38
E25
E25
VSS#39
E29
E29
VSS#40
E39
E39
VSS#41
E41
E41
VSS#42
G3
G3
VSS#43
G7
G7
VSS#44
G11
G11
VSS#45
G15
G15
VSS#46
G19
G19
VSS#47
G23
G23
VSS#48
G27
G27
VSS#49
G31
G31
VSS#50
G35
G35
VSS#51
G39
G39
VSS#52
J1
J1
VSS#53
J3
J3
VSS#54
J5
J5
VSS#55
J34
J34
VSS#56
J37
J37
VSS#57
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
BAFFIN POWER GND
BAFFIN POWER GND
Mon Dec 14 13:53:00 2015
Mon Dec 14 13:53:00 2015
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
3
symbol12
REV 0.91
BAFFIN - REV 0.90
BAFFIN - REV 0.90
175
175
U1
REV:
VSS#58
VSS#59
VSS#60
VSS#61
VSS#62
VSS#63
VSS#64
VSS#65
VSS#66
VSS#67
VSS#68
VSS#69
VSS#70
VSS#71
VSS#72
VSS#73
VSS#74
VSS#75
VSS#76
VSS#77
VSS#78
VSS#79
VSS#80
VSS#81
VSS#82
VSS#83
VSS#84
VSS#85
VSS#86
VSS#87
VSS#88
VSS#89
VSS#90
VSS#91
VSS#92
VSS#93
VSS#94
VSS#95
VSS#96
VSS#97
VSS#98
VSS#99
VSS#100
VSS#101
VSS#102
VSS#103
VSS#104
VSS#105
VSS#106
VSS#107
VSS#108
VSS#109
VSS#110
VSS#111
VSS#112
VSS#113
VSS#114
1.0
1.0
U1
U1U1
J39
J39
J40
J40
J41
J41
K21
K21
K25
K25
K29
K29
K40
K40
L3
L3
L7
L7
L11
L11
L15
L15
L19
L19
L23
L23
L27
L27
L31
L31
L35
L35
L39
L39
N1
N1
N3
N3
N5
N5
N17
N17
N19
N19
N25
N25
N27
N27
N32
N32
N37
N37
N39
N39
R3
R3
R7
R7
R11
R11
R17
R17
R19
R19
R25
R25
R27
R27
R32
R32
R35
R35
R39
R39
U1
U1
U3
U3
U5
U5
U17
U17
U19
U19
U25
U25
U27
U27
U32
U32
U37
U37
U39
U39
W3
W3
W7
W7
W11
W11
W17
W17
W19
W19
W25
W25
W27
W27
W39
W39
AA1
AA1
AA3
AA3
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
AA5
AA5
VSS#115
AA10
AA10
VSS#116
AA17
AA17
VSS#117
AA19
AA19
VSS#118
AA25
AA25
VSS#119
AA27
AA27
VSS#120
AA32
AA32
VSS#121
AA39
AA39
VSS#122
AC3
AC3
VSS#123
AC7
AC7
VSS#124
AC11
AC11
VSS#125
AC17
AC17
VSS#126
AC19
AC19
VSS#127
AC25
AC25
VSS#128
AC27
AC27
VSS#129
AC39
AC39
VSS#130
AE1
AE1
VSS#131
AE3
AE3
VSS#132
AE5
AE5
VSS#133
AE10
AE10
VSS#134
AE17
AE17
VSS#135
AE19
AE19
VSS#136
AE25
AE25
VSS#137
AE27
AE27
VSS#138
AE32
AE32
VSS#139
AE35
AE35
VSS#140
AE39
AE39
VSS#141
AG3
AG3
VSS#142
AG7
AG7
VSS#143
AG11
AG11
VSS#144
AG17
AG17
VSS#145
AG19
AG19
VSS#146
AG25
AG25
VSS#147
AG27
AG27
VSS#148
AG39
AG39
VSS#149
AG40
AG40
VSS#150
AG41
AG41
VSS#151
AJ1
AJ1
VSS#152
AJ3
AJ3
VSS#153
AJ5
AJ5
VSS#154
AJ10
AJ10
VSS#155
AJ11
AJ11
VSS#156
AJ35
AJ35
VSS#157
AJ39
AJ39
VSS#158
AL3
AL3
VSS#159
AL7
AL7
VSS#160
AL10
AL10
VSS#161
AL11
AL11
VSS#162
AL32
AL32
VSS#163
AL35
AL35
VSS#164
AL39
AL39
VSS#165
AN1
AN1
VSS#166
AN3
AN3
VSS#167
AN7
AN7
VSS#168
AN35
AN35
VSS#169
AN39
AN39
VSS#170
Advanced Micro Devices
2015
2015
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
symbol13
REV 0.91
BAFFIN - REV 0.90
BAFFIN - REV 0.90
VSS#171
VSS#172
VSS#173
VSS#174
VSS#175
VSS#176
VSS#177
VSS#178
VSS#179
VSS#180
VSS#181
VSS#182
VSS#183
VSS#184
VSS#185
VSS#186
VSS#187
VSS#188
VSS#189
VSS#190
VSS#191
VSS#192
VSS#193
VSS#194
VSS#195
VSS#196
VSS#197
VSS#198
VSS#199
VSS#200
VSS#201
VSS#202
VSS#203
VSS#204
VSS#205
VSS#206
VSS#207
VSS#208
VSS#209
VSS#210
VSS#211
VSS#212
VSS#213
VSS#214
VSS#215
VSS#216
VSS#217
VSS#218
VSS#219
VSS#220
VSS#221
VSS#222
VSS#223
VSS#224
VSS#225
VSS#226
AN40
AN40
AN41
AN41
AP13
AP13
AP17
AP17
AR3
AR3
AR7
AR7
AR11
AR11
AR19
AR19
AR21
AR21
AR25
AR25
AR27
AR27
AR31
AR31
AR35
AR35
AR39
AR39
AU1
AU1
AU3
AU3
AU9
AU9
AU23
AU23
AU29
AU29
AW3
AW3
AW5
AW5
AW7
AW7
AW9
AW9
AW11
AW11
AW13
AW13
AW15
AW15
AW17
AW17
AW19
AW19
AW21
AW21
AW23
AW23
AW25
AW25
AW27
AW27
AW29
AW29
AW31
AW31
AW33
AW33
AW35
AW35
AW37
AW37
AW39
AW39
AY1
AY1
AY2
AY2
AY9
AY9
AY12
AY12
AY17
AY17
AY23
AY23
AY29
AY29
AY37
AY37
AY40
AY40
AY41
AY41
BA2
BA2
BA5
BA5
BA9
BA9
BA17
BA17
BA23
BA23
BA29
BA29
BA37
BA37
BA40
BA40
2
1
C
A
Page 6
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
SSON
XIN
CLKOUT1
VSS
XOUT
VDD
BIBIOUT
OUT
OUTBIIN
OUT
OUT
BI
SI
SCK
HOLD
VDD
GND
WP
SO
CE
IN
OUTINOUTINOUT
OUT
OUT
OUT
OUTININ
IN
BIOS
REV 0.91
symbol11
DBGDATA_15
DBGDATA_14
DBGDATA_13
DBGDATA_12
DBGDATA_11
DBGDATA_10
DBGDATA_9
DBGDATA_8
DBGDATA_7
DBGDATA_6
DBGDATA_5
DBGDATA_4
DBGDATA_3
DBGDATA_2
DBGDATA_1
DBGDATA_0
IN
OUTININ
OUT
OUT
IN
REV 0.91
symbol5
GENERICG
RSVD#R34
RSVD#K41
VDD_33
TEST_PG_BACO
SWAPLOCKB
SWAPLOCKA
GENLK_VSYNC
GENLK_CLK
VSYNC
HSYNC
WAKEB
DDCVGADATA
DDCVGACLK
CLKREQB
TEST_PG
DIGON
BL_ENABLE
BL_PWM_DIM
SMBDAT
SMBCLK
SDA
SCL
HPD1
GPIO_SVT
GPIO_SVD
GPIO_SVC
GPIO_30
GPIO_29
GPIO_22_ROMCSB
GPIO_21
GPIO_20
GPIO_19_CTF
GPIO_18_HPD3
GPIO_17_THERMAL_INT
GPIO_16_8P_DETECT
GPIO_15
GPIO_14_HPD2
GPIO_13
GPIO_12
GPIO_11
GPIO_10_ROMSCK
GPIO_9_ROMSI
GPIO_8_ROMSO
GPIO_6_TACH
GPIO_5_REG_HOT_AC_BATT
GPIO_2
GPIO_1
GPIO_0
GENERICF_HPD5
GENERICE_HPD4
GENERICD
GENERICC
GENERICB
GENERICA
REV 0.91
symbol6
ANALOGIO
XTALOUT
XTALIN
PLLCHARZ_L
PLLCHARZ_H
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
SCL/SDA
SCL/SDA
ADDRESS
DEVICE
DEVICE
D D
DIG POT
DIG POT
LM89-1
LM89-1
ADDRESS
0x5C
0x5C
0x9A
0x9A
R5
SVC
R1199
SVC
SVD
SVD
SVT
SVT
21R1199
21
0R
0R
5%
5%
9 14
9 14
OUT
9 14
9 14
BI
9
9
IN
HOW TO SIMPLIFY CIRCUITS?
HOW TO SIMPLIFY CIRCUITS?
BACO MODE, 1.8V alway on?
BACO MODE, 1.8V alway on?
VDDC_PGOOD
9
9
IN
VDDC_PGOOD
C
U1
U1
symbol11
DBGDATA_0
DBGDATA_1
DBGDATA_2
DBGDATA_3
DBGDATA_4
DBGDATA_5
DBGDATA_6
DBGDATA_7
DBGDATA_8
DBGDATA_9
DBGDATA_10
DBGDATA_11
DBGDATA_12
DBGDATA_13
B B
REV 0.91
BAFFIN - REV 0.90
BAFFIN - REV 0.90
DBGDATA_14
DBGDATA_15
U1
U1
symbol6
A
REV 0.91
BAFFIN - REV 0.90
BAFFIN - REV 0.90
8
L40
L40
L41
L41
M40
M40
M41
M41
N40
N40
N41
N41
P40
P40
P41
P41
R40
R40
R41
R41
T40
T40
T41
T41
U40
U40
U41
U41
V40
V40
V41
V41
XTALIN
XTALOUT
PLLCHARZ_L
PLLCHARZ_H
ANALOGIO
6
6
DBGDATA_<0>
DBGDATA_<0>
6
6
DBGDATA_<1>
DBGDATA_<1>
6
6
DBGDATA_<2>
DBGDATA_<2>
DBGDATA_<3>
6
6
DBGDATA_<3>
DBGDATA_<4>
6
6
DBGDATA_<4>
6
DBGDATA_<5>
6
DBGDATA_<5>
6
DBGDATA_<6>
6
DBGDATA_<6>
6
6
DBGDATA_<7>
DBGDATA_<7>
DBGDATA_<8>
DBGDATA_<8>
DBGDATA_<9>
DBGDATA_<9>
DBGDATA_<10>
DBGDATA_<10>
DBGDATA_<11>
DBGDATA_<11>
DBGDATA_<12>
DBGDATA_<12>
DBGDATA_<13>
DBGDATA_<13>
DBGDATA_<14>
DBGDATA_<14>
DBGDATA_<15>
DBGDATA_<15>
1.8V 200MHz
1.8V 200MHz
BA39
6
BA39
6
AY39
AY39
AV15
AV15
AU15
AU15
AY38
AY38
XTALIN
XTALIN
XTALOUT
XTALOUT
PLLCHARZ_L
PLLCHARZ_L
PLLCHARZ_H
PLLCHARZ_H
ANALOGIO
ANALOGIO
R5
R6
R6
R7
R7
R1150
10K
10K
5%
5%
2 1
2 1
2 1
2 1
KEEP THE CLOCK PATH
KEEP THE CLOCK PATH
AS SHORT AS POSSIBLE
AS SHORT AS POSSIBLE
C1107
C1107
1uF
1uF
6.3V
6.3V
TP1100
TP1100
TP1101
TP1101
TP1102
TP1102
TP1103
TP1103
TP1104
TP1104
TP1105
TP1105
TP1106
TP1106
TP1107
TP1107
TP1108
TP1108
TP1109
TP1109
TP1110
TP1110
TP1111
TP1111
TP1112
TP1112
TP1113
TP1113
TP1114
TP1114
TP1115
TP1115
MR53
MR53
R71
R71
0R
0R
0R
0R
0R
0R
DNI
DNI
15
15
6
6
15
15
8
8
5%
5%
5%
5%
5%
5%
TP51
TP51
TP52
TP52
8
8
+1.8V
+1.8V
1%16.2K
1%16.2K
7
OUT
BI
OUT
BI
R1167R1150
R1167
10K
10K
5%
5%
2 1
2 1
2 1
2 1
C1106
C1106
1uF
1uF
6.3V
6.3V
6
6
5%0R
5%0R
+VDD33
+VDD33
8
8
OUT
8
8
BI
TEST_PG
TEST_PG
TEST_PG_BACO
TEST_PG_BACO
XTALIN
XTALIN
10K
10K
5%
5%
+VDD33
+VDD33
R4R3
R4R3
10K
10K
5%
5%
SCL
SCL
SDA
SDA
G_SMBCLK
G_SMBCLK
G_SMBDAT
G_SMBDAT
GPIO_SVC
GPIO_SVC
GPIO_SVD
GPIO_SVD
GPIO_SVT
GPIO_SVT
DDCVGACLK
DDCVGACLK
DDCVGADATA
DDCVGADATA
C52
C52
AM31
AM31
C1
C1
1uF
1uF
6.3V
6.3V
AC35
AC35
AC34
AC34
AW40
AW40
AW41
AW41
AU17
AU17
AV17
AV17
AR17
AR17
AN34
AN34
AP31
AP31
AY13
AY13
BA13
BA13
K41
K41
R34
R34
18pF 50V
18pF 50V
SL_CLK_100M
SL_CLK_100M
6
6
VDD_33
SCL
SDA
SMBCLK
SMBDAT
GPIO_SVC
GPIO_SVD
GPIO_SVT
DDCVGACLK
DDCVGADATA
TEST_PG
TEST_PG_BACO
RSVD#K41
RSVD#R34
REV 0.91
5%0R
5%0R
XTALIN
XTALIN
U1
U1
symbol5
GPIO_5_REG_HOT_AC_BATT
BAFFIN - REV 0.90
BAFFIN - REV 0.90
SI_XTALOUT SI_XTALIN
SI_XTALOUT SI_XTALIN
3 2
3 2
4
4
GPIO_6_TACH
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_16_8P_DETECT
GPIO_17_THERMAL_INT
XOUT
CLKOUT1
Si51214-A1EAGM
Si51214-A1EAGM
GPIO_15
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20
GPIO_21
GPIO_22_ROMCSB
GPIO_29
GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG
CLKREQB
BL_ENABLE
BL_PWM_DIM
SWAPLOCKA
SWAPLOCKB
GENLK_CLK
GENLK_VSYNC
Y51
Y51
1
1
27.000MHz
27.000MHz
R51
R51
1%1M
1%1M
U50
U50
27MHz OSC OPTION
27MHz OSC OPTION
R1211
R1211
21
21
5%0R
5%0R
GPIO_0
GPIO_1
GPIO_2
HPD1
WAKEB
DIGON
HSYNC
VSYNC
3
3
42
42
21
21
XIN
VDD
SSON
VSS
W40
W40
AA40
AA40
AA35
AA35
AA34
AA34
U35
U35
AP25
AP25
AM25
AM25
AM27
AM27
W41
W41
Y40
Y40
Y41
Y41
AU21
AU21
AA41
AA41
U34
U34
R37
R37
AV25
AV25
R38
R38
AB40
AB40
AB41
AB41
AP27
AP27
W37
W37
W38
W38
BA38
BA38
AV29
AV29
AU31
AU31
AV31
AV31
AU25
AU25
AV23
AV23
AM29
AM29
AV21
AV21
AV40
AV40
AU40
AU40
AC40
AC40
AC37
AC37
AC38
AC38
W34
W34
W35
W35
AG34
AG34
AE34
AE34
AR29
AR29
AP29
AP29
1
1
5
5
6
6
27MHZ_1V8
27MHZ_1V8
6
GPIO_0
GPIO_0
GPIO_2
GPIO_2
GPIO_5
GPIO_5
GPIO_8_ROMSO
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_10_ROMSCK
GPIO_11
GPIO_11
GPIO_12
GPIO_12
GPIO_13
GPIO_13
HPD2
HPD2
GPIO_15
GPIO_15
MB_ALERTB
MB_ALERTB
HPD3
HPD3
GPIO_19_CTF
GPIO_19_CTF
GPIO_20
GPIO_20
GPIO_21
GPIO_21
GPIO_22_ROMCSb
GPIO_22_ROMCSb
GPIO_29
GPIO_29
GPIO_30
GPIO_30
GENERICA
GENERICA
GENERICB
GENERICB
HPD4
HPD4
HPD5
HPD5
HPD1
HPD1
CLKREQB
CLKREQB
G_WAKEb
G_WAKEb
FPVCC
FPVCC
GPIO7_BLON
GPIO7_BLON
BLON_PWM
BLON_PWM
HSYNC
HSYNC
VSYNC
VSYNC
R52R53
C53
C53
SI_VDD
SI_VDD
SI_SS_SEL
SI_SS_SEL
DNI
DNI
R1210
R1210
221R
221R
1%
1%
2 1
2 1
DNI
DNI
8 6
8 6
OUT
6
6
2121
21R5221R53
50V18pF
50V18pF
OUT
+3VRUN
1
1
Q1100
Q1100
4
+3VRUN
21R1104
21
3
3
8
8
IN
6
5%33R
5%33R
81
2 1
2 1
10K
10K
5%
5%
R1105
R1105
100K
100K
1%
1%
DNI
DNI
DNI
DNI
81RP1
72
72RP1
63
63RP1
54
54RP1
R1106
R1106
510R
510R
RP1
RP1
RP1
6
6
6
6
6
6
8 6 6
8 6 6
6
6
6
6
5%0R
5%0R
XTALOUT
XTALOUT
21
21
R1209
R1209
182R
182R
1%
1%
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
IN
IN
OUT
6
6
27MHZ_REF
27MHZ_REF
8
8
6
6
8 15
8 15
8
8
14
14
8 6
8 6
6
6
14
14
8
8
8
8
8
8
8
8
8
8
8
8
C54
C54
0.1uF
0.1uF
6.3V
6.3V
B50
B50
R54
R54
R55
R55
120R
120R
RP1
+VDD33
+VDD33
+3VRUN
+3VRUN
10K
10K
5%
5%
DNI
DNI
+1.8V
+1.8V
21
21
+1.8V
+1.8V
5%5.1K
5%5.1K
5%5.1K
5%5.1K
DNI
DNI
8
8
IN
R35R34R33
R35R34R33
10K
10K
5%
5%
5%33R
5%33R
5%33R
5%33R
5%33R
5%33R
DNI
DNI
R1104
2
2
21
21
6
ROMSO
ROMSO
6
6
ROMSI
ROMSI
ROMSCK
ROMSCK
6
6
ROMCSb
ROMCSb
5
VIDEO BIOS
VIDEO BIOS
FIRMWARE
FIRMWARE
U10
U10
3 8
3 8
WP
2
2
SO
5
5
SI
6
6
SCK
CE
GD25Q40BTI
GD25Q40BTI
DNI
DNI
5%0R
5%0R
WAKEb
WAKEb
8
8
OUT
8
8
OUT
8
8
OUT
+3VRUN
+3VRUN
VDD
7
7
HOLD
GND
8
8
IN
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
C10
C10
0.1uF
0.1uF
6.3V
6.3V
41
41
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
BAFFIN GPIO STRAPS CLK
BAFFIN GPIO STRAPS CLK
NOTE
NOTE
BIOS1
BIOS1
BIOS
+VDD33
+VDD33
21MR9
OF
21
DNI
DNI
10K 5%
21MR31
21
10K 5%
DNI
DNI
DNI
DNI
DNI
DNI
10K
10K
DNI
DNI
10K
10K
DNI
DNI
DNI
DNI
10K
10K
DNI
DNI
10K
10K
DNI
DNI
10K 5%
10K 5%
DNI
DNI
10K
10K
DNI
DNI
10K
10K
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
10K
10K
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%
5%
5%
5%
5%10K
5%10K
5%
5%
5%
5%
5%
5%
5%
5%
5%10K
5%10K
5%10K
5%10K
+1.8V
+1.8V
5%10K
5%10K
5%
5%
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
176
176
MR9
MR31
MR11
MR11
MR12
MR12
MR13
MR13
MR14
MR14
MR15
MR15
MR16
MR16
MR17
MR17
MR18
MR18
MR19
MR19
MR20
MR20
MR21
MR21
MR22
MR22
MR23
MR23
MR24
MR24
MR25
MR25
MR26
MR26
MR27
MR27
MR28
MR28
MR29
MR29
MR30
MR30
Mon Dec 14 13:52:58 2015
Mon Dec 14 13:52:58 2015
105_C985xx_00B
105_C985xx_00B
3
R9
R31
R11
R11
R12
R12
R13
R13
R14
R14
R15
R15
R16
R16
R17
R17
R18
R18
R19
R19
R20
R20
R21
R21
R22
R22
R23
R23
R24
R24
R25
R25
R26
R26
R27
R27
R28
R28
R29
R29
R30
R30
10K 5%
10K 5%
10K
10K
10K 5%
10K 5%
10K
10K
10K
10K
10K 5%
10K 5%
10K 5%
10K 5%
10K 5%
10K 5%
REV:
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
PIN STRAPS
PIN STRAPS
21R9
21
5%10K
5%10K
GPIO_0
GPIO_0
21R31
21
5%10K
5%
5%
5%10K
5%10K
5%
5%
5%
5%
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
1.0
1.0
GPIO_215%10K
GPIO_21
GPIO_2
GPIO_2
ROMSO
ROMSO
ROMSI
ROMSI
GPIO_11
GPIO_11
GPIO_12
GPIO_12
GPIO_13
GPIO_13
GPIO_15
GPIO_15
GPIO_20
GPIO_20
ROMCSb
ROMCSb
GPIO_29
GPIO_29
HSYNC
HSYNC
VSYNC
VSYNC
DBGDATA_<0>
DBGDATA_<0>
DBGDATA_<1>
DBGDATA_<1>
DBGDATA_<2>
DBGDATA_<2>
DBGDATA_<3>
DBGDATA_<3>
DBGDATA_<4>
DBGDATA_<4>
DBGDATA_<5>
DBGDATA_<5>
DBGDATA_<6>
DBGDATA_<6>
DBGDATA_<7>
DBGDATA_<7>
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
PINSTRAP_BIF_TX_HALF_SWING (0)
PINSTRAP_BIF_TX_HALF_SWING (0)
6
6
8
8
DIRECT GRAPHICS MEMORY ACCESS
DIRECT GRAPHICS MEMORY ACCESS
PINSTRAP_BIF_GEN3_EN_A (1)
PINSTRAP_BIF_GEN3_EN_A (1)
6
6
PINSTRAP_BIF_CLK_PM_EN (0)
PINSTRAP_BIF_CLK_PM_EN (0)
6
6
PINSTRAP_SMS_EN_HARD (0)
PINSTRAP_SMS_EN_HARD (0)
6
6
6
PINSTRAP_ROM_CONFIG [0] IF BIOS_ROM_EN = 1 (1)
PINSTRAP_ROM_CONFIG [0] IF BIOS_ROM_EN = 1 (1)
6
PINSTRAP_BIF_MEM_AP_SIZE [0] IF BIOS_ROM_EN = 0
PINSTRAP_BIF_MEM_AP_SIZE [0] IF BIOS_ROM_EN = 0
6
PINSTRAP_ROM_CONFIG [1] IF BIOS_ROM_EN = 1 (0)
PINSTRAP_ROM_CONFIG [1] IF BIOS_ROM_EN = 1 (0)
6
PINSTRAP_BIF_MEM_AP_SIZE [1] IF BIOS_ROM_EN = 0
PINSTRAP_BIF_MEM_AP_SIZE [1] IF BIOS_ROM_EN = 0
PINSTRAP_ROM_CONFIG [2] IF BIOS_ROM_EN = 1 (1)
PINSTRAP_ROM_CONFIG [2] IF BIOS_ROM_EN = 1 (1)
6
6
PINSTRAP_BIF_MEM_AP_SIZE [2] IF BIOS_ROM_EN = 0
PINSTRAP_BIF_MEM_AP_SIZE [2] IF BIOS_ROM_EN = 0
PINSTRAP_EFUSE_RD_DISABLE (0)
PINSTRAP_EFUSE_RD_DISABLE (0)
6
6
PINSTRAP_TX_DEEMPH_EN (0)
PINSTRAP_TX_DEEMPH_EN (0)
8
8
6
6
PINSTRAP_BIOS_ROM_EN (1)
PINSTRAP_BIOS_ROM_EN (1)
6
6
PINSTRAP_BIF_VGA_DIS (0)
PINSTRAP_BIF_VGA_DIS (0)
8
8
6
6
6
PINSTRAP_AUD [0] (0)
PINSTRAP_AUD [0] (0)
6
PINSTRAP_AUD [1] (0)
PINSTRAP_AUD [1] (0)
6
6
PINSTRAP_AUD_PORT_CONN [0] (0)
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
2015
2015
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
PINSTRAP_AUD_PORT_CONN [0] (0)
PINSTRAP_AUD_PORT_CONN [1] (0)
PINSTRAP_AUD_PORT_CONN [1] (0)
PINSTRAP_AUD_PORT_CONN [2] (0)
PINSTRAP_AUD_PORT_CONN [2] (0)
PINSTRAP_BOARD_CONFIG [0] (0)
PINSTRAP_BOARD_CONFIG [0] (0)
PINSTRAP_BOARD_CONFIG [1] (0)
PINSTRAP_BOARD_CONFIG [1] (0)
PINSTRAP_BOARD_CONFIG [2] (0)
PINSTRAP_BOARD_CONFIG [2] (0)
PINSTRAP_SMBUS_ADDR [0] (0)
PINSTRAP_SMBUS_ADDR [0] (0)
PINSTRAP_SMBUS_ADDR [1] (0)
PINSTRAP_SMBUS_ADDR [1] (0)
Advanced Micro Devices
2
1
C
A
Page 7
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
OUT
BI
REV 0.91
symbol15
TX2M_DPE0N
DDCAUX5P
DDCAUX5N
TX1P_DPE1P
TX0P_DPE2P
TXCEP_DPE3P
TX2P_DPE0P
TX1M_DPE1N
TX0M_DPE2N
TXCEM_DPE3N
BI
BI
REV 0.91
symbol8
AUX1N
DDC1DATA
AUX1P
DDC1CLK
TXCDM_DPD3N
TXCCM_DPC3N
TXCCP_DPC3P
TX3M_DPC2N
TX3P_DPC2P
TX4M_DPC1N
TX4P_DPC1P
TX5M_DPC0N
TX5P_DPC0P
TXCDP_DPD3P
TX0M_DPD2N
TX0P_DPD2P
TX1M_DPD1N
TX1P_DPD1P
TX2M_DPD0N
TX2P_DPD0P
DDC2DATA
DDC2CLK
AUX2P
AUX2N
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
REV 0.91
symbol7
AUX_ZVSS
DDCAUX3N
DDCAUX3P
DDCAUX4P
DDCAUX4N
TXCBP_DPB3P
TXCBM_DPB3N
TXCAP_DPA3P
TXCAM_DPA3N
TX2P_DPB0P
TX2M_DPB0N
TX1P_DPB1P
TX1M_DPB1N
TX0P_DPB2P
TX0M_DPB2N
TX5P_DPA0P
TX5M_DPA0N
TX4P_DPA1P
TX4M_DPA1N
TX3P_DPA2P
TX3M_DPA2N
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIOUT
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
D D
C
U1U1
U1
symbol7
TX2P_DPB0P
TX2M_DPB0N
TX1P_DPB1P
TX1M_DPB1N
TX0P_DPB2P
TX0M_DPB2N
TXCBP_DPB3P
TXCBM_DPB3N
DDCAUX3P
DDCAUX3N
AY32
AY32
BA32
BA32
AY31
AY31
BA31
BA31
AY30
AY30
BA30
BA30
AY28
AY28
BA28
BA28
AM21
AM21
AP21
AP21
TX2P_DPB0P
TX2P_DPB0P
TX2M_DPB0N
TX2M_DPB0N
TX1P_DPB1P
TX1P_DPB1P
TX1M_DPB1N
TX1M_DPB1N
TX0P_DPB2P
TX0P_DPB2P
TX0M_DPB2N
TX0M_DPB2N
TXCBP_DPB3P
TXCBP_DPB3P
TXCBM_DPB3N
TXCBM_DPB3N
DDCAUX3P
DDCAUX3P
DDCAUX3N
DDCAUX3N
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
U1
symbol8
TX2P_DPD0P
TX2M_DPD0N
TX1P_DPD1P
TX1M_DPD1N
TX0P_DPD2P
TX0M_DPD2N
TXCDP_DPD3P
TXCDM_DPD3N
AUX1P
AUX1N
DDC1CLK
DDC1DATA
AY22
AY22
BA22
BA22
AY21
AY21
BA21
BA21
AY20
AY20
BA20
BA20
AY19
AY19
BA19
BA19
AY11
AY11
BA11
BA11
AY10
AY10
BA10
BA10
TX2P_DPD0P
TX2P_DPD0P
TX2M_DPD0N
TX2M_DPD0N
TX1P_DPD1P
TX1P_DPD1P
TX1M_DPD1N
TX1M_DPD1N
TX0P_DPD2P
TX0P_DPD2P
TX0M_DPD2N
TX0M_DPD2N
TXCDP_DPD3P
TXCDP_DPD3P
TXCDM_DPD3N
TXCDM_DPD3N
DDCAUX1P
DDCAUX1P
DDCAUX1N
DDCAUX1N
51K
51K
R38
R38
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUTOUT
8
8
OUT
8
8
BI
21
21
5%
5%
U1
U1
symbol15
TX2P_DPE0P
TX2M_DPE0N
TX1P_DPE1P
TX1M_DPE1N
TX0P_DPE2P
TX0M_DPE2N
TXCEP_DPE3P
TXCEM_DPE3N
AY18
AY18
BA18
BA18
AY16
AY16
BA16
BA16
AY15
AY15
BA15
BA15
AY14
AY14
BA14
BA14
TX2P_DPE0P
TX2P_DPE0P
TX2M_DPE0N
TX2M_DPE0N
TX1P_DPE1P
TX1P_DPE1P
TX1M_DPE1N
TX1M_DPE1N
TX0P_DPE2P
TX0P_DPE2P
TX0M_DPE2N
TX0M_DPE2N
TXCDP_DPE3P
TXCDP_DPE3P
TXCDM_DPE3N
TXCDM_DPE3N
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
C
AY27
AUX2P
AUX2N
AY27
BA27
BA27
AY26
AY26
BA26
BA26
AY25
AY25
BA25
BA25
AY24
AY24
BA24
BA24
AP19
AP19
AM19
AM19
AV19
AV19
AU19
AU19
TX2P_DPC0P
TX2P_DPC0P
TX2M_DPC0N
TX2M_DPC0N
TX1P_DPC1P
TX1P_DPC1P
TX1M_DPC1N
TX1M_DPC1N
TX0P_DPC2P
TX0P_DPC2P
TX0M_DPC2N
TX0M_DPC2N
TXCCP_DPC3P
TXCCP_DPC3P
TXCCM_DPC3N
TXCCM_DPC3N
DDCAUX2P
DDCAUX2P
DDCAUX2N
DDCAUX2N
51K
51K
R40
R40
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
OUT
8
8
BI
21
21
5%
5%
REV 0.91
BAFFIN - REV 0.90
BAFFIN - REV 0.90
DDCAUX5P
DDCAUX5N
AU27
AU27
AV27
AV27
DDCAUX5P
DDCAUX5P
DDCAUX5N
DDCAUX5N
OUT
BI
8
8
8
8
AY36
TX5P_DPA0P
TX5M_DPA0N
TX4P_DPA1P
TX4M_DPA1N
TX3P_DPA2P
TX3M_DPA2N
TXCAP_DPA3P
TXCAM_DPA3N
R1700
R1700
B B
150R
150R
1%
1%
AUX_ZVSS
AUX_ZVSS
BA12
BA12
AUX_ZVSS
REV 0.91
DDCAUX4P
DDCAUX4N
AY36
BA36
BA36
AY35
AY35
BA35
BA35
AY34
AY34
BA34
BA34
AY33
AY33
BA33
BA33
AR23
AR23
AP23
AP23
TX2P_DPA0P
TX2P_DPA0P
TX2M_DPA0N
TX2M_DPA0N
TX1P_DPA1P
TX1P_DPA1P
TX1M_DPA1N
TX1M_DPA1N
TX0P_DPA2P
TX0P_DPA2P
TX0M_DPA2N
TX0M_DPA2N
TXCAP_DPA3P
TXCAP_DPA3P
TXCAM_DPA3N
TXCAM_DPA3N
DDCAUX4P
DDCAUX4P
DDCAUX4N
DDCAUX4N
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
REV 0.91
BAFFIN - REV 0.90BAFFIN - REV 0.90
BAFFIN - REV 0.90BAFFIN - REV 0.90
TX5P_DPC0P
TX5M_DPC0N
TX4P_DPC1P
TX4M_DPC1N
TX3P_DPC2P
TX3M_DPC2N
TXCCP_DPC3P
TXCCM_DPC3N
DDC2CLK
DDC2DATA
A
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
BAFFIN TMDP_LVTMDP
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
8
7
6
5
4
BAFFIN TMDP_LVTMDP
Mon Dec 14 13:53:01 2015
Mon Dec 14 13:53:01 2015
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
3
REV:
177
177
1.0
1.0
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
2
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
1
A
Page 8
9
9
A
B
C
D
E
8
7
7 46 5 123
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
D
1
A
B
58 6 3
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
C
E
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTININININININININININININININININININININININININININININININININININININININININININ
OUTINOUT
OUT
OUT
OUT
OUT
OUTINININININOUT
OUT
OUT
OUT
OUTININININININININININININ
IN
Part 1 of 2
Mechanical Key
3V3
3V3
DP_A_HPD
DP_B_HPD
DP_B_AUX
DP_B_AUX#
GND
DP_B_L3
DP_B_L3#
GND
DP_B_L2
DP_B_L2#
GND
DP_B_L1
DP_B_L1#
GND
DP_B_L0
DP_B_L0#
GND
3V3_242
3V3_240
RSVD
DP_D_HPD
DP_C_HPD
DP_D_AUX
DP_D_AUX#
GND
DP_D_L3
DP_D_L3#
GND
DP_D_L2
DP_D_L2#
GND
DP_D_L1
DP_D_L1#
GND
DP_D_L0
DP_D_L0#
GND
LVDS_LTX0
LVDS_LTX0#
GND
LVDS_LTX1
LVDS_LTX1#
GND
LVDS_LTX2
LVDS_LTX2#
GND
LVDS_LTX3
LVDS_LTX3#
GND
LVDS_LCLK
LVDS_LCLK#
GND
VGA_BLUE
VGA_GREEN
VGA_RED
GND
VGA_HSYC
VGA_VSYC
VGA_DDC_CLK
VGA_DDC_DAT
PEX_RST#
PEX_CLK_REQ#
GND
PEX_TX0
PEX_TX0#
GND
PEX_TX1
PEX_TX1#
GND
PEX_TX2
PEX_TX2#
GND
PRSNT_L#
DP_A_AUX
DP_A_AUX#
GND
DP_A_L3
DP_A_L3#
GND
DP_A_L2
DP_A_L2#
GND
DP_A_L1
DP_A_L1#
GND
DP_A_L0
DP_A_L0#
GND
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
DP_C_AUX
DP_C_AUX#
GND
DP_C_L3
DP_C_L3#
GND
DP_C_L2
DP_C_L2#
GND
DP_C_L1
DP_C_L1#
GND
DP_C_L0
DP_C_L0#
GND
LVDS_UTX0
LVDS_UTX0#
GND
LVDS_UTX1
LVDS_UTX1#
GND
LVDS_UTX2
LVDS_UTX2#
GND
LVDS_UTX3
LVDS_UTX3#
GND
LVDS_UCLK
LVDS_UCLK#
JTAG_TRST#
JTAG_TMS
JTAG_TCLK
JTAG_TDI
JTAG_TDO
GND
PEX_REFCLK
PEX_REFCLK#
GND
PEX_RX0
PEX_RX0#
GND
PEX_RX1
PEX_RX1#
GND
PEX_RX2
PEX_RX2#
GND
GND
PEX_TX3
PEX_TX3#
GND
PEX_TX4
PEX_TX4#
GND
PEX_TX5
PEX_TX5#
GND
PEX_TX6
PEX_TX6#
GND
PEX_TX7
PEX_TX7#
GND
PEX_TX8
PEX_TX8#
GND
PEX_TX9
PEX_TX9#
GND
PEX_TX10
PEX_TX10#
GND
PEX_TX11
PEX_TX11#
GND
PEX_TX12
PEX_TX12#
GND
PEX_TX13
PEX_TX13#
GND
PEX_TX14
PEX_TX14#
GND
PEX_TX15
PEX_TX15#
GND
OEM6
OEM4
OEM2
OEM0
GND
SMB_CLK
SMB_DAT
GPIO2
GPIO1
GPIO0
TH_PWM
TH_ALERT#
TH_OVERT#
PWR_LEVEL
JTAG_TESTEN
LVDS_U_HPD
GND
27MHZ_REF
PWR_EN
PWR_GOOD
WAKE#
PRSNT_R#
GND
PWR_SRC_E2
GND
PEX_RX3
PEX_RX3#
GND
PEX_RX4
PEX_RX4#
GND
PEX_RX5
PEX_RX5#
GND
PEX_RX6
PEX_RX6#
GND
PEX_RX7
PEX_RX7#
GND
PEX_RX8
PEX_RX8#
GND
PEX_RX9
PEX_RX9#
GND
PEX_RX10
PEX_RX10#
GND
PEX_RX11
PEX_RX11#
GND
PEX_RX12
PEX_RX12#
GND
PEX_RX13
PEX_RX13#
GND
PEX_RX14
PEX_RX14#
GND
PEX_RX15
PEX_RX15#
GND
OEM7_45
OEM5_43
OEM3_41
OEM1_39
GND
LVDS_DDC_CLK
LVDS_DDC_DAT
LVDS_L_HPD_31
HDMI_CEC
PNL_PWM
PNL_BL_EN
PNL_PWR_EN
VGA_DISABLE#
PEX_STD_SW#
GND
GND
GND
GND
5V
5V
5V
5V
5V
GND
PWR_SRC_E1
OUT
OUT
OUT
OUTINBIINOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Part 2 of 2
MTG5
MTG6
MTG4
MTG3
MTG2
MTG1
IN
IN
9
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
8
7 46 5 123
E
D
C
B
A
GPIO_20
6
6
OUT
6
6
OUT
6
6
OUT
GPIO_20
GPIO_0
GPIO_0
BSH111
BSH111
GPIO_29
GPIO_29
Q4
Q4
BSH111
BSH111
Q3
Q3
R2107
R2107
3
3
2
2
3
3
2
2
7
7
7
7
2 8
2 8
OUT
2 8
2 8
OUT
2 8
2 8
OUT
2 8
2 8
OUT
2 8
2 8
OUT
2 8
2 8
OUT
8 14
8 14
OUT
6 8
6 8
6 8
6 8
6 8
6 8
6 8
6 8
6 8
6 8
9
PCIE_REFCLKP
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_REFCLKN
PCIE_RXP<7..0>
PCIE_RXP<7..0>
PCIE_RXN<7..0>
PCIE_RXN<7..0>
PCIE_TXP<7..0>
PCIE_TXP<7..0>
PCIE_TXN<7..0>
PCIE_TXN<7..0>
RUNPWROK
RUNPWROK
OUT
OUT
OUT
OUT
OUT
5%
5%
100K
100K
R2146
R2146
5%
5%
100K
100K
R2155
R2155
5%
5%
100K
100K
R2156
R2156
5%
5%
100K
100K
R2157
R2157
5%
5%
100K
100K
R2159
R2159
HPD1
HPD1
HPD2
HPD2
HPD3
HPD3
HPD4
HPD4
HPD5
HPD5
0R
0R
1
1
Q2
Q2
R2108
R2108
1
1
IN
IN
R2109
R2109
3
3
2
2
DDCAUX5N
DDCAUX5N
DDCAUX5P
DDCAUX5P
0R
0R
BSH111
BSH111
1
1
0R
0R
R1909
R1909
4.7K
4.7K
5%
5%
+VDD33
+VDD33
G_PWR_SRC
G_PWR_SRC
+5VRUN
+5VRUN
R1911
R1911
4.7K
4.7K
5%
5%
15
15
15
15
15
15
15
15
15
15
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
2 8
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
C1006
C1006
C1005
MXM
MXM
0.1uF
0.1uF
16V
16V
2 1
2 1
PCIE_TXN<7>
PCIE_TXN<7>
PCIE_TXP<7>
PCIE_TXP<7>
PCIE_TXN<6>
PCIE_TXN<6>
PCIE_TXP<6>
PCIE_TXP<6>
PCIE_TXN<5>
PCIE_TXN<5>
PCIE_TXP<5>
PCIE_TXP<5>
PCIE_TXN<4>
PCIE_TXN<4>
PCIE_TXP<4>
PCIE_TXP<4>
PCIE_TXN<3>
PCIE_TXN<3>
PCIE_TXP<3>
PCIE_TXP<3>
PCIE_TXN<2>
PCIE_TXN<2>
PCIE_TXP<2>
PCIE_TXP<2>
PCIE_TXN<1>
PCIE_TXN<1>
PCIE_TXP<1>
PCIE_TXP<1>
PCIE_TXN<0>
PCIE_TXN<0>
PCIE_TXP<0>
PCIE_TXP<0>
PCIE_REFCLKN
PCIE_REFCLKN
8 2
8 2
PCIE_REFCLKP
PCIE_REFCLKP
8 2
8 2
JTAG_TDO
JTAG_TDO
JTAG_TDI
JTAG_TDI
JTAG_TCK
JTAG_TCK
JTAG_TMS
JTAG_TMS
JTAG_TRSTB
JTAG_TRSTB
TX2M_DPD0N
TX2M_DPD0N
TX2P_DPD0P
TX2P_DPD0P
TX1M_DPD1N
TX1M_DPD1N
TX1P_DPD1P
TX1P_DPD1P
TX0M_DPD2N
TX0M_DPD2N
TX0P_DPD2P
TX0P_DPD2P
TXCDM_DPD3N
TXCDM_DPD3N
TXCDP_DPD3P
TXCDP_DPD3P
DDCAUX4N
DDCAUX4N
DDCAUX4P
DDCAUX4P
TX2M_DPB0N
TX2M_DPB0N
TX2P_DPB0P
TX2P_DPB0P
TX1M_DPB1N
TX1M_DPB1N
TX1P_DPB1P
TX1P_DPB1P
TX0M_DPB2N
TX0M_DPB2N
TX0P_DPB2P
TX0P_DPB2P
TXCBM_DPB3N
TXCBM_DPB3N
TXCBP_DPB3P
TXCBP_DPB3P
DDCAUX2N
DDCAUX2N
DDCAUX2P
DDCAUX2P
C1003
C1003
MXMMXM
MXMMXM
1000pF2.2uF
1000pF2.2uF
50V25V
50V25V
PEX_STD_SW#
PEX_STD_SW#
VGA_DISABLE#
VGA_DISABLE#
8
8
8
8
8
8
8 6
8 6
+3VRUN
+3VRUN
+3VRUN
+3VRUN
R1000
R1000
R1001
R1001
100K
100K
100K
100K
5%
5%
5%
100K
100K
15
15
DNI
DNI
OUT
R1907
R1907
GPIO_5
GPIO_5
0R
0R
0R
0R
2 1
2 1
PWR_EN_IN
PWR_EN_IN
+VDD33
+VDD33
1%
1%
21
21
OUT
5%
5%
5%
5%
8 2 9 14
8 2 9 14
4.7K
4.7K
5%
GENERICA
GENERICA
GENERICB
GENERICB
R159R158
R159R158
4.7K
4.7K
5%5%
5%5%
6
6
+VDD33
+VDD33
R118
R118
MR118
MR118
OUT
OUT
DNI
DNI
R156
R156
10K
10K
5%
5%
2 1
R157
R157
10K
10K
5%
5%
2 1
2 1 2 1
+VDD33
+VDD33
DNI
DNI
6
6
6
6
MB_ALERTB
MB_ALERTB
MB_THERMB
MB_THERMB
R155
R155
5%
5%
0R
0R
1K
1K
14 8
14 8
5%1K
5%1K
3
3
Q102
Q102
5%
1
1
5%
2N7002L
2N7002L
2
2
R1801
R1801
100K 100K
100K 100K
5%
5%
R2116
R2116
CLKREQb
CLKREQb
58 6 3
C1004C1005
C1004
MXM
MXM
0.1uF
0.1uF
16V
16V
2 1
2 1
FPVCC_MB
FPVCC_MB
BL_ENA
BL_ENA
BL_BRIGHT_MB
BL_BRIGHT_MB
HPD5
HPD5
R210
R210
MXM
MXM
0R
0R
J100
J100
PWR_SRC_E1
GND
1
1
5V
3
3
5V
5
5
5V
7
7
5V
5V
GND
13
13
GND
15
15
GND
17
17
GND
19
19
PEX_STD_SW#
21
21
VGA_DISABLE#
23
23
PNL_PWR_EN
25
25
PNL_BL_EN
27
27
PNL_PWM
29 30
29 30
HDMI_CEC
31
31
LVDS_L_HPD_31
33
33
LVDS_DDC_DAT
35
35
LVDS_DDC_CLK
37
37
GND
OEM1_39
OEM3_41
OEM5_43
45
45
OEM7_45
47
47
GND
49
49
PEX_RX15#
51
51
PEX_RX15
53
53
GND
55
55
PEX_RX14#
57
57
PEX_RX14
59
59
GND
61
61
PEX_RX13#
63
63
PEX_RX13
65
65
GND
67
67
PEX_RX12#
69
69
PEX_RX12
71
71
GND
73
73
PEX_RX11#
75
75
PEX_RX11
77
77
GND
79
79
PEX_RX10#
81
81
PEX_RX10
83
83
GND
85
85
PEX_RX9#
87
87
PEX_RX9
89
89
GND
91
91
PEX_RX8#
93
93
PEX_RX8
95
95
GND
97
97
PEX_RX7#
99
99
PEX_RX7
101
101
GND
103
103
PEX_RX6#
105
105
PEX_RX6
107
107
GND
109
109
PEX_RX5#
111
111
PEX_RX5
113
113
GND
115
115
PEX_RX4#
117
117
PEX_RX4
119
119
GND
121
121
PEX_RX3#
123
123
PEX_RX3
125
125
GND
GND
135
135
PEX_RX2#
137
137
PEX_RX2
GND
141
141
PEX_RX1#
143
143
PEX_RX1
GND
147
147
PEX_RX0#
149
149
PEX_RX0
GND
153 154
153 154
PEX_REFCLK#
PEX_REFCLK
157
157
GND
159
159
JTAG_TDO
161
161
JTAG_TDI
163
163
JTAG_TCLK
165
165
JTAG_TMS
167
167
JTAG_TRST#
169
169
LVDS_UCLK#
171
171
LVDS_UCLK
GND
175
175
LVDS_UTX3#
177
177
LVDS_UTX3
GND
181
181
LVDS_UTX2#
183
183
LVDS_UTX2
GND
187
187
LVDS_UTX1#
189
189
LVDS_UTX1
GND
193
193
LVDS_UTX0#
195
195
LVDS_UTX0
GND
199
199
DP_C_L0#
201
201
DP_C_L0
GND
205
205
DP_C_L1#
207
207
DP_C_L1
GND
211
211
DP_C_L2#
213
213
DP_C_L2
GND
217
217
DP_C_L3#
219
219
DP_C_L3
GND
223
223
DP_C_AUX#
225
225
DP_C_AUX
227
227
RSVD
229
229
RSVD
231
231
RSVD
233
233
RSVD
235
235
RSVD
RSVD
239
239
RSVD
241
241
RSVD
243
243
RSVD
245
245
RSVD
247
247
RSVD
249
249
RSVD
251
251
GND
253
253
DP_A_L0#
255
255
DP_A_L0
257
257
GND
259
259
DP_A_L1#
261
261
DP_A_L1
263
263
GND
265
265
DP_A_L2#
267
267
DP_A_L2
269
269
GND
271
271
DP_A_L3#
273
273
DP_A_L3
275
275
GND
277
277
DP_A_AUX#
279
279
DP_A_AUX
281
281
PRSNT_L#
J100
J100
Part 2 of 2
MTG1
MTG1
MTG1
MTG2
MTG2
MTG2
MTG3
MTG3
MTG3
MTG4
MTG4
MTG4
MTG5
MTG5
MTG5
MTG6
MTG6
MTG6
Part 1 of 2
Mechanical Key
NA
NA
NA
NA
PEX_CLK_REQ#
7
PWR_SRC_E2
GND
PRSNT_R#
WAKE#
PWR_GOOD
PWR_EN
27MHZ_REF
GND
LVDS_U_HPD
JTAG_TESTEN
PWR_LEVEL
TH_OVERT#
TH_ALERT#
TH_PWM
GPIO0
GPIO1
GPIO2
SMB_DAT
SMB_CLK
GND
OEM0
OEM2
OEM4
OEM6
GND
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
GND
PEX_TX2#
PEX_TX2
GND
PEX_TX1#
PEX_TX1
GND
PEX_TX0#
PEX_TX0
GND
PEX_RST#
VGA_DDC_DAT
VGA_DDC_CLK
VGA_VSYC
VGA_HSYC
GND
VGA_RED
VGA_GREEN
VGA_BLUE
GND
LVDS_LCLK#
LVDS_LCLK
GND
LVDS_LTX3#
LVDS_LTX3
GND
LVDS_LTX2#
LVDS_LTX2
GND
LVDS_LTX1#
LVDS_LTX1
GND
LVDS_LTX0#
LVDS_LTX0
GND
DP_D_L0#
DP_D_L0
GND
DP_D_L1#
DP_D_L1
GND
DP_D_L2#
DP_D_L2
GND
DP_D_L3#
DP_D_L3
GND
DP_D_AUX#
DP_D_AUX
DP_C_HPD
DP_D_HPD
RSVD
3V3_240
3V3_242
GND
DP_B_L0#
DP_B_L0
GND
DP_B_L1#
DP_B_L1
GND
DP_B_L2#
DP_B_L2
GND
DP_B_L3#
DP_B_L3
GND
DP_B_AUX#
DP_B_AUX
DP_B_HPD
DP_A_HPD
3V3
3V3
E2E1
E2E1
E4E3
E4E3
2
2
4
4
6
6
8
8
109
109
1211
1211
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
32
32
34
34
36
36
38
38
4039
4039
4241
4241
4443
4443
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
70
72
72
74
74
76
76
78
78
80
80
82
82
84
84
86
86
88
88
90
90
92
92
94
94
96
96
98
98
100
100
102
102
104
104
106
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
122
122
124
124
134133
134133
136
136
138
138
140139
140139
142
142
144
144
146145
146145
148
148
150
150
152151
152151
156155
156155
158
158
160
160
162
162
164
164
166
166
168
168
170
170
172
172
174173
174173
176
176
178
178
180179
180179
182
182
184
184
186185
186185
188
188
190
190
192191
192191
194
194
196
196
198197
198197
200
200
202
202
204203
204203
206
206
208
208
210209
210209
212
212
214
214
216215
216215
218
218
220
220
222221
222221
224
224
226
226
228
228
230
230
232
232
234
234
236
236
238237
238237
240
240
242
242
244
244
246
246
248
248
250
250
252
252
254
254
256
256
258
258
260
260
262
262
264
264
266
266
268
268
270
270
272
272
274
274
276
276
278
278
280
280
WAKEb
WAKEb
0R
0R
PWR_GOOD
PWR_GOOD
DGPU_PWR_EN
DGPU_PWR_EN
27MHZ_REF
27MHZ_REF
TESTEN
TESTEN
PWR_LEVEL
PWR_LEVEL
MB_THERMB
MB_THERMB
MB_ALERTB
MB_ALERTB
TH_PWM
TH_PWM
SMB_DAT
SMB_DAT
SMB_CLK
SMB_CLK
STEREO_SYNC
STEREO_SYNC
PCIE_RXN<7>
PCIE_RXN<7>
PCIE_RXP<7>
PCIE_RXP<7>
PCIE_RXN<6>
PCIE_RXN<6>
PCIE_RXP<6>
PCIE_RXP<6>
PCIE_RXN<5>
PCIE_RXN<5>
PCIE_RXP<5>
PCIE_RXP<5>
PCIE_RXN<4>
PCIE_RXN<4>
PCIE_RXP<4>
PCIE_RXP<4>
PCIE_RXN<3>
PCIE_RXN<3>
PCIE_RXP<3>
PCIE_RXP<3>
PCIE_RXN<2>
PCIE_RXN<2>
PCIE_RXP<2>
PCIE_RXP<2>
PCIE_RXN<1>
PCIE_RXN<1>
PCIE_RXP<1>
PCIE_RXP<1>
PCIE_RXN<0>
PCIE_RXN<0>
PCIE_RXP<0>
PCIE_RXP<0>
PEX_CLK_REQb
PEX_CLK_REQb
PEX_RSTb
PEX_RSTb
TXCDM_DPE3N
TXCDM_DPE3N
TXCDP_DPE3P
TXCDP_DPE3P
TX2M_DPE0N
TX2M_DPE0N
TX2P_DPE0P
TX2P_DPE0P
TX1M_DPE1N
TX1M_DPE1N
TX1P_DPE1P
TX1P_DPE1P
TX0M_DPE2N
TX0M_DPE2N
TX0P_DPE2P
TX0P_DPE2P
TX2M_DPC0N
TX2M_DPC0N
TX2P_DPC0P
TX2P_DPC0P
TX1M_DPC1N
TX1M_DPC1N
TX1P_DPC1P
TX1P_DPC1P
TX0M_DPC2N
TX0M_DPC2N
TX0P_DPC2P
TX0P_DPC2P
TXCCM_DPC3N
TXCCM_DPC3N
TXCCP_DPC3P
TXCCP_DPC3P
DDCAUX3N
DDCAUX3N
DDCAUX3P
DDCAUX3P
HPD4
HPD4
HPD3
HPD3
TX2M_DPA0N
TX2M_DPA0N
TX2P_DPA0P
TX2P_DPA0P
TX1M_DPA1N
TX1M_DPA1N
TX1P_DPA1P
TX1P_DPA1P
TX0M_DPA2N
TX0M_DPA2N
TX0P_DPA2P
TX0P_DPA2P
TXCAM_DPA3N
TXCAM_DPA3N
TXCAP_DPA3P
TXCAP_DPA3P
DDCAUX1N
DDCAUX1N
DDCAUX1P
DDCAUX1P
HPD1
HPD1
HPD2
HPD2
R1009
R1009
MXM
MXM
6
5%
5%
R1007
R1007
5%
5%
0R
0R
OUT
15 8
15 8
6 8 15
6 8 15
OUT
8
8
8
8
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8
8
6
6
8 6
8 6
R154
R154
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8 6
8 6
8 6
8 6
5%0R
5%0R
21
21
OUT
OUT
0R
0R
R2111
R2111
15
15
C35
C35
100pF
100pF
50V
50V
2 1
2 1
PERSTb_RST#
PERSTb_RST#
DDCVGADATA
DDCVGADATA
DDCVGACLK
DDCVGACLK
+3VRUN
+3VRUN
C1007
C1007
MXM
MXM
1uF
1uF
6.3V
6.3V
2 1
2 1
+3VRUN
+3VRUN
C1001C1002
C1001C1002
MXMMXM
MXMMXM
1uF10uF
1uF10uF
6.3V6.3V
6.3V6.3V
6
6
6
5%
5%
R2118
R2118
R2121
R2121
DNI
DNI
0R
0R
OUT
OUT
+3VRUN
+3VRUN
PWR_EN
PWR_EN
21
21
OUT
5%
5%
100K
100K
R1004
R1004
+3VRUN+3VRUN
+3VRUN+3VRUN
6
6
6
6
R209
R209
5%
5%
+3VRUN
+3VRUN
DNI
DNI
R2100
R2100
21
21
0R
OUT
CTFb
CTFb
CTFb
CTFb
14
14
IN
IN
IN
1
1
2
2
NC7SZ08P5X
NC7SZ08P5X
0R
0R
6 8 15
6 8 15
15 8
15 8
14 8
14 8
U1000
U1000
R1008
R1008
0R
2N7002DW
Q2100
2N7002DW
Q2100
4
3
3
4
4
RUNPWROK
RUNPWROK
DNI
DNI
5%
5%
+3VRUN
+3VRUN
8 14
8 14
53
53
U1000
U1000
NC7SZ08P5X
NC7SZ08P5X
C1000
C1000
0.1uF
0.1uF
10V
10V
4
5
5
R2101
R2101
10K
10K
5%
5%
C2106
C2106
0.1uF
0.1uF
2 1
2 1
Q2100
Q2100
2N7002DW
2N7002DW
+3VRUN
+3VRUN
2 1
2 11
6
6
1
R2162
R2162
R2161
R2161
R2163
R2163
R2164
R2164
R2115
R2115
280K
280K
0R 5%
0R 5%
21
21
VDDCI_PGOOD
VDDCI_PGOOD
5%0R
5%0R
21
21
MVDD_PGOOD
MVDD_PGOOD
0R
0R
5%
5%
21
+0.8V_PGOOD
+0.8V_PGOOD
21
0R
0R
5%
5%
+1.8V_PGOOD
+1.8V_PGOOD
21
21
Chose R2115 and C2106 values such that:
Chose R2115 and C2106 values such that:
the delay between PX_EN ramp-down to Q2100 turn-on time is 25mSec min
the delay between PX_EN ramp-down to Q2100 turn-on time is 25mSec min
2
PX_EN
PX_EN
2
MXM specs asks for mandatory support of
MXM specs asks for mandatory support of
PWR_GOOD from module, but optional for
PWR_GOOD from module, but optional for
motherboard to use it
motherboard to use it
For BACO designs where motherboards monitor
For BACO designs where motherboards monitor
PWR_GOOD: Do not install R1050
PWR_GOOD: Do not install R1050
For Non-BACO designs, or BACO designs where
For Non-BACO designs, or BACO designs where
motherboards do not monitor PWR_GOOD:
motherboards do not monitor PWR_GOOD:
Do not install Q1060, R1052 and C1059. Install R1050.
Do not install Q1060, R1052 and C1059. Install R1050.
IN
2 14
2 14
IN
IN
IN
IN
9
9
11
11
12
12
13
13
E
D
BL_BRIGHT
R2128
R2128
0R
0R
DNI
DNI
R2129
BL_ENA
BL_ENA
8
8
6
6
0R
0R
0R
0R
R2129
R2130
R2130
5%
5%
5%
5%
BL_BRIGHT
BLON_PWM
BLON_PWM
GPIO7_BLON
GPIO7_BLON
8
8
6
6
IN
6
6
IN
C
R2132
BL_BRIGHT_MB
BL_BRIGHT_MB
8 8
8 8
FPVCC_MB FPVCC
FPVCC_MB FPVCC
8
8
8 2 9 14
8 2 9 14
OUT
6
6
IN
6
6
BI
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
MXM3.1 INTERFACE
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
4
MXM3.1 INTERFACE
Mon Dec 14 13:52:57 2015
Mon Dec 14 13:52:57 2015
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
178
178
R2132
0R
0R
R2133
R2133
0R
0R
PERSTb_RST#
PERSTb_RST#
G_SMBCLK
G_SMBCLK
G_SMBDAT
G_SMBDAT
5%
5%
5%
5%
DNI
DNI
4.7K 4.7K
4.7K 4.7K
5%
5%
REV:
R212
R212
0R
0R
BL_BRIGHT
BL_BRIGHT
6
6
IN
+3VRUN
+3VRUN
DNI
DNI
R211
R211
4.7K
4.7K
5%
5%
SM_EN
SM_EN
5
5
Q203
4
1.0
1.0
4
DNI
DNI
DNI
DNI
1
1
R214R213
R214R213
5%
5%
Q203
3
3
2N7002DW
2N7002DW
8
8
SMB_CLK
R217
R217
0R
0R
R219
R219
0R
0R
Q203
Q203
2
2
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
SMB_CLK
8
8
SMB_DAT
SMB_DAT
6
6
2N7002DW
2N7002DW
Advanced Micro Devices
2015
2015
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
R218
R218
R220
R220
2
+VDD33+VDD33+VDD33+VDD33
+VDD33+VDD33+VDD33+VDD33
R216
R216
MXM
MXM
100K
100K
R215
R215
5%
5%
MXM
MXM
100K
100K
5%
5%
PBAT_SMBCLK
5%
5%
5%
5%
PBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBDAT
OUT
OUT
15
15
15
15
0R
0R
0R
0R
B
A
1
Page 9
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
+++++++
OUTINOUT
OUT
OUTINOUT
OUT
OUT
OUT
TH
THTHTH
PHASE2
LGATE2
PVCC
LGATE1
PHASE1
UGATE1
BOOT1
LGATEA1
PHASEA1
UGATEA1
BOOTA1
PWMA2
TONSETA
OCP_L
VCC
IBIAS
COMPA
FBA
VSENA
ISENA2P
ISENA2N
ISENA1N
ISENA1P
EN
PGOODA
PGOOD
SET2
SET1
OFSA
OFS
SVT
SVD
SVC
PWROK
VDDIO
IMONA
V064
IMON
RGND
COMP
FB
VSEN
ISEN3N
ISEN3P
ISEN1P
ISEN1N
ISEN2N
ISEN2P
TONSET
PWM3
BOOT2
UGATE2
OUT
OUT
OUT
INININ
IN
+
+
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
17ci203
7
6
5 4 3
2
1
+5VRUN
+5VRUN
R633
R633
5%
5%
2.2R
2.2R
D D
VDDC_UG1
VDDC_UG1
9
9
VDDC_PH1
VDDC_PH1
9
9
VDDC_LG1
VDDC_LG1
9
9
VDDC_LG2
VDDC_LG2
9
9
VDDC_PH2
9
VDDC_PH2
21
21
R625
R625
0R
0R
R504
R504
100R
100R
R656
R656
0R
0R
R654
R654
100R
100R
R518
R518
100R
100R
R651
R651
14K
14K
R519
R519
0R
0R
1
1
2
2
10K
10K
0R
0R
9
9
9
C618
C618
0.22uF
0.22uF
R670
R670
R662
R662
21
21
5%
5%
21
21
5%
5%
21
21
5%
5%
21
21
5%
5%
21
21
5%
5%
21
2121
1%
1%
21
21
5%
5%
R590
R590
U590
U590
VDDC_UG2
VDDC_UG2
21
2.2R
2.2R
25V
25V
R520
R520
1K
1K
R521
R521
1K
1K
21
21
1%
1%
C641
C641
50V
50V
4.7pF
4.7pF
C502
C502
0.47uF
0.47uF
16V
16V
AGND
AGND
21
21
DNI
DNI
5%
5%
4
4
R624
R624
1%
1%
1%
1%
R663
R663
1
1
21
2
2
2121
5%
5%
3
3
4
4
5
5
21
6
6
21
21
7
7
21
8
8
9
9
10
10
11
11
12
12
13
13
1%19.1K1%910K
1%19.1K1%910K
RT8880CGQW
RT8880CGQW
C640
C640
270pF
270pF
G_PWR_SRC
G_PWR_SRC
R611
R611
21
21
5%
5%
4.7R
4.7R
9
9
9
9
9
9
9
9
C
B B
AGND
AGND
AGND
AGND
A
5
5
5
5
10
10
8 2 14
8 2 14
AGND
AGND
IN
IN
IN
IN
FB_VDDC
FB_VDDC
VDDC_LOC_P
VDDC_LOC_P
9
9
FB_VSSC
FB_VSSC
VDDC_LOC_N
VDDC_LOC_N
9
9
VDDCI_LOC_N
VDDCI_LOC_N
VDDC_THERM_P
VDDC_THERM_P
9
9
VDDC_THERM_N
VDDC_THERM_N
9
9
NS555
NS555
21
21
SCHEMATIC
SCHEMATIC
R666
R666
0R 5%
0R 5%
PERSTb_RST#
PERSTb_RST#
VDDCI_PGOOD
VDDCI_PGOOD
9 8
9 8
0.1uF
0.1uF
+5VRUN
+5VRUN
C645
C645
21
21
+3VRUN NC7SZ08P5X
+3VRUN NC7SZ08P5X
2 1
2 1
C503
C503
C604
C604
1uF
1uF
25V
25V
21
21
16V
16V
R649
R649
10K
10K
50V82pF
50V82pF
R655
R655
11K
11K
2 1
2 1
R612
R612
21
21
1%
1%
110K
110K
VDDC_ISENP2
VDDC_ISENP2
VDDC_ISENN2
VDDC_ISENN2
VDDC_ISENN1
VDDC_ISENN1
VDDC_ISENP1
VDDC_ISENP1
C504
C504
0.1uF
0.1uF
R517
R517
0R
0R
21
21
1%
1%
21
0.5%
0.5%
R657
R657
10K
10K
5%
5%
DNI
DNI
21
21
16V
16V
5%
5%
R648
R648
17.4K
17.4K
1%
1%
U601
U601
UGATE2
BOOT2
PWM3
TONSET
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
VSEN
FB
COMP
50V
50V
R628
R628
21.5K
21.5K
R522
R522
0R
0R
14
14
1%
1%
5%
5%
+3VRUN
+3VRUN
53
53
NC7SZ08P5X
NC7SZ08P5X
C500
C500
2.2uF
2.2uF
10V
10V
RGND
21
21
U590
U590
IMON
15
15
R646
R646
20.5K
20.5K
1%
1%
52
52
PHASE2
V064
16
16
8.06K
8.06K
2 1
2 1
51
51
LGATE2
IMONA
17
17
R667
R667
C590
C590
0.1uF
0.1uF
16V
16V
50
50
PVCC
+1.8V
+1.8V
48
49
48
49
LGATE1
PHASE1
SVC
PWROK
VDDIO
18
20
19
18
20
19
VDDCI_THERM_P
VDDCI_THERM_P
21
21
1%
1%
VDDCI_THERM_N
VDDCI_THERM_N
R631
R631
2.2R
2.2R
VDDC_PWROK
VDDC_PWROK
47
47
UGATE1
SVD
21
21
5%
5%
C626
C626
0.22uF
0.22uF
25V
25V
R500
R500
2.2R
2.2R
5%
5%
2 1
2 1
46
46
BOOT1
SVT
22
22
44
45
44
45
LGATEA1
PHASEA1
OFS
23
23
10
10
10
10
C622
C622
2.2uF
2.2uF
10V
10V
43
43
UGATEA1
OFSA
24
24
SET1
25
25
C646
C646
0.22uF
0.22uF
25V
25V
R501
R501
2.2R
2.2R
5%
5%
2 1
2 1
42
42
BOOTA1
SET2
26
26
41
41
PWMA2
40
40
TONSETA
THTHTH
555453
555453
AGND
AGND
2 1
2 1
PGOOD
PGOODA
ISENA1P
ISENA1N
ISENA2N
ISENA2P
VSENA
FBA
COMPA
IBIAS
VCC
OCP_L
TH
56
56
AGND
AGND
R669
R669
0R
0R
5%
5%
1%
1%
140K
140K
39
39
38
38
37
37
EN
36
36
35
35
34
34
33
33
32
32
31
31
30
30
29
29
28
28
27
27
C643
C643
0.1uF
0.1uF
10V
10V
AGND AGND AGND
AGND AGND AGND
20K
20K
1%
1%
DNI
DNI
5%
5%
2 1
2 1
VCC5
VCC5
VDDCI_LG
VDDCI_LG
VDDCI_PH1
VDDCI_PH1
VDDCI_UG
VDDCI_UG
R503R502
R503R502
4.7R
4.7R
C611
C611
1uF
1uF
25V
25V
R511
R511
0R
0R
R512
R512
0R
0R
R513
R513
0R
0R
R626
R626
100K
100K
VCC5
VCC5
OCP_L
OCP_L
AGND
AGND
SVT
SVT
SVD
SVD
SVC
SVC
OUT
OUT
OUT
G_PWR_SRC
G_PWR_SRC
21
21
5%
5%
21
21
5%
5%
21
21
5%
5%
21
21
5%
5%
R523
R523
1%
1%
1K
1K
R642
R642
158K
158K
21
21
1%
1%
AGND
AGND
2.2R
2.2R
C642
C642
2.2uF
2.2uF
10V
10V
R629R630
R629R630
20K
20K
1%
1%
AGND
AGND
R645R620
R645R620
0R0R
0R0R
5% 1%
5% 1%
6
6
OUT
6 14
6 14
OUT
6 14
6 14
OUT
21
21
R618
R618
C621
C621
10V
10V
1.5pF
1.5pF
1%
1%
10
10
10
10
10
10
VDDC_PGOOD
VDDC_PGOOD
VDDCI_PGOOD
VDDCI_PGOOD
VDDC_I_EN
VDDC_I_EN
C505
C505
0.1uF
0.1uF
16V
16V
C627
C627
21
21
50V
50V
+5VRUN
+5VRUN
5%
5%
+1.8V
+1.8V
R516
R516
4.7K
4.7K
5%
5%
5
5
IN
10
10
IN
VDDCI_ISENP1
VDDCI_ISENP1
VDDCI_ISENN1
VDDCI_ISENN1
21
21
R659
R659
120K
120K
1%
1%
R622
R622
4.99K
4.99K
1%
1%
R613
R613
1%
1%
R637
R637
909R
909R
VCC5
VCC5
AGND
AGND
FB_VDDCI
FB_VDDCI
VDDCI_LOC_P
VDDCI_LOC_P
6
6
OUT
8 9
8 9
OUT
14
14
OUT
OUT
OUT
C628
C628
82pF
82pF
R635
R635
412K
412K
1%
1%
R632
R632
20.5K
20.5K
1%
1%
R636
R636
475R13.3K0.1uF
475R13.3K0.1uF
1%
1%
R610
R610
5.1R
5.1R
5%
5%
10K
10K
0R
0R
10K
10K
50V
50V
10
10
10
10
R634
R634
R524
R524
R640
R640
G_PWR_SRC
G_PWR_SRC
12
12
12
12
++
C541C540
C541
C552
C552
4.7uF
4.7uF
25V
25V
2 1
2 1
C543
C542
C542
35V
35V
2 1
2 1
2 1
2 1
R505
R505
21
21
5%
5%
0R
0R
R506
R506
21
21
5%100R
5%100R
+5VRUN
+5VRUN
21
21
1%
1%
21
21
5%
5%
21
21
1%
1%
VDDC_UG1
VDDC_UG1
9
9
VDDC_PH1
VDDC_PH1
9
9
VDDC_LG1
VDDC_LG1
9
9
VDDC_UG2
VDDC_UG2
9
9
VDDC_PH2
VDDC_PH2
9
9
VDDC_LG2
VDDC_LG2
9
9
9
9
9
9
G_PWR_SRC
G_PWR_SRC
C569
4.7uF
4.7uF
25V
25V
2 1
2 1
VDDC_THERM_P
VDDC_THERM_P
VDDC_THERM_N
VDDC_THERM_N
C556
C556C569
4.7uF
4.7uF
35V
35V
2 1
2 1
2 1
2 1
DNI
DNI
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
C544
C543
4.7uF
4.7uF
25V 35V
25V 35V
2 1
2 1
DNI
DNI
0R
0R
C557
C557
4.7uF
4.7uF
35V
35V
2 1
2 1
DNI
DNI
0R
0R
VDDC
VDDC
NOTE
NOTE
C545
C544
C545
4.7uF4.7uF
4.7uF4.7uF
4.7uF
4.7uF
25V
25V
35V
35V
2 1
2 1
VDDC_UG1_CTL
R507
R507
C558
4.7uF
4.7uF
25V
25V
R509
R509
Mon Dec 14 13:52:58 2015
Mon Dec 14 13:52:58 2015
VDDC_UG1_CTL
21
21
5%
5%
4
4
C559
4.7uF
4.7uF
35V
35V
2 1
2 1
21
21
5%
5%
4
4
21
21
R508
R508
21
21
VDDC_UG2_CTL
VDDC_UG2_CTL
R5009
R5009
C540
22uF
22uF
25V
25V
C546
C546
4.7uF
4.7uF
2 1
2 1
4
4
40A
40A
Q512
Q512
BSZ035N03MS
BSZ035N03MS
321
321
C560C559C558
C560
4.7uF
4.7uF
25V
25V
4
4
98765
98765
Q522
Q522
BSZ035N03MS
BSZ035N03MS
321
321
98765
98765
40A
40A
2 1
2 1
1%
1%
10K
10K
1%
1%
10K
10K
OF
105_C985xx_00B
105_C985xx_00B
4
4
4
4
15uF
15uF
25V
25V
179
179
98765
98765
40A
40A
Q510
Q510
BSZ100N03MS
BSZ100N03MS
321
321
98765
98765
40A
40A
Q511
Q511
BSZ035N03MS
BSZ035N03MS
321
321
98765
98765
40A
Q520
40A
Q520
BSZ100N03MS
BSZ100N03MS
321
321
98765
98765
40A
40A
Q521
Q521
BSZ035N03MS
BSZ035N03MS
321
321
98765
98765
40A
40A
Q513
Q513
BSZ100N03MS
SCHEMATIC
SCHEMATIC
NS500
NS500
2 1
2 1
SCHEMATIC
SCHEMATIC
NS501
NS501
2 1
2 1
1.0
1.0
BSZ100N03MS
321
321
0.33uH
0.33uH
R570
R570
1.5K
1%
1%
1.5K
98765
98765
40A
40A
Q523
Q523
BSZ100N03MS
BSZ100N03MS
321
321
0.33uH
0.33uH
R575
R575
1%
1.5K
1.5K
1%
ML510
ML510
0.33uH
0.33uH
L510
L510
ML520
ML520
0.33uH
0.33uH
L520
L520
21
21
21
21
C547
C547
C548
C548
0.1uF
0.1uF
22uF
SCHEMATIC
SCHEMATIC
NS505
NS505
2 1
2 1
C553
C553
16V
16V
0.47uF
0.47uF
R527
R527
1.5K
1.5K
C567
C567
0.47uF
0.47uF
R528
R528
1.5K
1.5K
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
VDDC_ISENN1
21
21
VDDC_ISENN1
1%
1%
VDDC_ISENP1
VDDC_ISENP1
R572
R572
100K
100K
1%
1%
2 1
2 1
21
21
21
21
SCHEMATIC
SCHEMATIC
NS506
NS506
2 1
2 1
16V
16V
VDDC_ISENN2
21
21
VDDC_ISENN2
1%
1%
VDDC_ISENP2
VDDC_ISENP2
Advanced Micro Devices
2015
2015
9
9
9
9
16V
16V
C561
C561
0.1uF
0.1uF
9
9
9
9
12
12
12
12
22uF
2.5V
2.5V
2 1
2 1
MC554
330uF
330uF
2V
2V
C562
22uF
22uF
2.5V
2.5V
2 1
2 1
C595
220uF
220uF
R581
R581
100R
100R
5%
5%
12
12
++
2 1
2 1
12
12
+ ++
NS1
NS1
NS2
NS2
MC555
MC555MC554
330uF
330uF
2V
2V
C563
22uF
22uF
2.5V
2.5V
C597 C596C595
C597
220uF
220uF
2V2V
2V2V
SCHEMATIC
SCHEMATIC
SCHEMATIC
SCHEMATIC
TITLE:
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
4
4
R529
R529
1R
1R
5%
5%
DNI
DNI
2 1
2 1
C506
C506
3300pF
3300pF
50V 1.8V
50V 1.8V
2 1
2 1
DNI
DNI
PLACE CLOSE TO THE VDDC INDUCTOR (L510&L520)
PLACE CLOSE TO THE VDDC INDUCTOR (L510&L520)
4
4
R530
R530
1R
1R
5%
5%
DNI
DNI
2 1
2 1
C507
C507
3300pF
3300pF
50V
50V
2 1
2 1
DNI
DNI
REV:
12
12
C554
470uF
470uF
C564C562
C564
22uF
22uF
2 1
2 1
21
VDDC_LOC_P
21
VDDC_LOC_P
21
VDDC_LOC_N
21
VDDC_LOC_N
+VDDC
+VDDC
C551
C551
22uF
22uF
2.5V
2.5V
2 1
2 1
12
12
++
C555
C555C554
470uF
470uF
1.8V
1.8V
C565
C565C563
22uF
22uF
2.5V16V 2.5V
2.5V16V 2.5V
2 1
2 1
12
12
C596
220uF
220uF
2V
2V
9
9
9
9
C
A
8
7
6
5
4
3
2
1
Page 10
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
+
OUT
OUT
IN+IN
OUT
OUT
IN
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
D D
G_PWR_SRC
G_PWR_SRC
VDDCI_THERM_P
VDDCI_THERM_P
C526
C526
C527
4.7uF
4.7uF
4.7uF
4.7uF
25V 25V 25V 25V
25V 25V 25V 25V
2 1
C
2 1
2 1
2 1
2 1
2 1
9
9
IN
VDDCI_PH1
9
9
IN
9
9
IN
VDDCI_PH1
VDDCI_LG
VDDCI_LG
C528
4.7uF
4.7uF
35V
35V
DNI
DNI
2 1
2 1
C529
C529
4.7uF
4.7uF
35V
35V
DNI
DNI
2 1
2 1
C530
4.7uF
4.7uF
R563
R563
0R
0R
2 1
2 1
5%
5%
C531
C531C530C528C527
4.7uF
4.7uF
21
21
VDDCI_UG1VDDCI_UG
VDDCI_UG1VDDCI_UG
R599
R599
R668
R668
100K
2 1
2 1
L551
L551
0.47uH
0.47uH
0.47uF
0.47uF
100K
1%
1%
C539
C539
R526
R526
1.05K
1.05K
21
21
NS503
NS503
16V
16V
1%
1%
SCHEMATIC
SCHEMATIC
2 1
2 1
21
21
VDDCI_ISENN1
VDDCI_ISENN1
VDDCI_ISENP1
VDDCI_ISENP1
0.1uF
0.1uF
16V
16V
2 1
2 1
OUT
OUT
C535C534
22uF
22uF
2.5V
2.5V
2 1
2 1
9
9
9
9
VDDCI_THERM_N
VDDCI_THERM_N
C537
C536
C537
22uF
22uF
22uF
22uF
2.5V
2.5V
2.5V
2.5V
2 1
2 1
12
12
+
MC578
MC578
330uF
330uF
2V
2V
98765
98765
40A
40A
Q550
Q550
BSZ100N03MS
21
21
1%
1%
10K
10K
4
4
4
4
BSZ100N03MS
321
321
98765
98765
40A
40A
Q551
Q551
BSZ035N03MS
BSZ035N03MS
321
321
2 1
2 1
2 1
2 1
R531
R531
1R
1R
5%
5%
DNI
DNI
C508
C508
3300pF
3300pF
50V
50V
DNI
DNI
SCHEMATIC
SCHEMATIC
NS502
NS502
2 1
2 1
1.91K 1%
1.91K 1%
R565
R565
9
9
C
9
9
+VDDCI
+VDDCI
C538
C538C536C535C534
22uF
22uF
2.5V
2.5V
2 1
2 1
NS504
NS504
21
21
VDDCI_LOC_P
VDDCI_LOC_P
SCHEMATIC
SCHEMATIC
12
12
+
C578
C578
470uF
470uF
1.8V
1.8V
R566
R566
100R
100R
5%
5%
NS509
NS509
SCHEMATIC
SCHEMATIC
VDDCI_LOC_N
21
21
VDDCI_LOC_N
OUT
OUT
9
9
9
9
B B
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
A
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
VDDCI
VDDCI
Mon Dec 14 13:52:58 2015
Mon Dec 14 13:52:58 2015
OF
105_C985xx_00B
105_C985xx_00B
REV:
1710
1710
1.0
1.0
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
A
NOTES:
8
7
6
5
4
NOTE
NOTE
3
2
1
Page 11
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
IN+IN
OUT+IN
TH
TH
VTT
VTTIN
BOOT
UGATE
PHASE
LGATE
PGND
CS
VDDP
VDD
PGOOD
TON
S5
S3
FB
VDDQ
VTTREF
GND
VTTSNS
VTTGND
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
D D
R700
0R
0R
R700
21
21
+MVDD
C700
C700
0.1uF
0.1uF
6.3V
6.3V
2 1
2 1
MVDD_EN
IN
G_PWR_SRC
G_PWR_SRC
OUT
MVDD_EN
MVDD_PGOOD
MVDD_PGOOD
R701
750K
750K
R701
1%
1%
14 15 11
14 15 11
21
21
14
14
8
8
C
+5VRUN
+5VRUN
C707
C707
1000pF
1000pF
50V
50V
+MVDD_FB
+MVDD_FB
2 1
2 1
R703
R703
2.2R
2.2R
21
21
C708
2 1
2 1
6
6
7
7
8
8
+MVDD
GS7271-ACQ3
GS7271-ACQ3
22
21
22
21
TH
TH
FB
S3
S5
TON
PGOOD
C709
C709C708
0.1uF1uF
0.1uF1uF
6.3V6.3V
6.3V6.3V
2 1
2 1
C712
C712
10uF
10uF
6.3V
6.3V
2 1
2 1
4191
5
5
4
VDDQ
VTTREF
VDDP
VDD
12
11
12
11
2
2
3
3
GND
VTTSNS
PGND
CS
14
13
14
13
R705
11.8K
11.8K
1%
1%
2 1
2 1
1
VTTGND
VTTIN
BOOT
UGATE
PHASE
LGATE
15
15
MVDD_OCSET
MVDD_OCSET
C710
C710R705
0.01uF
0.01uF
25V
25V
2 1
2 1
VTT
U700
U700
20
20
19
18
18
179
179
1610
1610
M_Boot
M_Boot
2 1
2 1
R702
R702
1R
1R
5%
5%
MVDD_BOOT
MVDD_BOOT
25V
25V
C711
0.22uF
0.22uF
C711
21
21
C704C702
C702
C701
C701
0.01uF
0.01uF
0.01uF
0.01uF
25V
25V
25V
98765
98765
Q700
Q700
BSZ100N03MS
BSZ100N03MS
321
4
321
MVDD_UGATEMVDD_PHASE
MVDD_UGATEMVDD_PHASE
21
21
1%
1%
10K
10K
R704
R704
4
98765
98765
2 1
L700
L700
0.47uH
0.47uH
1%
1%
15K
15K
R706
R706
21
21
25V
2 1
2 1
2 1
2 1
2 1
21
21
16V
0.033uF
16V
0.033uF
C719
C719
21
21
C703
4.7uF
4.7uF
35V
35V
C704
4.7uF
4.7uF
25V
25V
2 1
2 1
2 1
2 1
C705
C705
4.7uF
4.7uF
35V
35V
G_PWR_SRC
G_PWR_SRC
C706C703
C706
4.7uF
4.7uF
35V
35V
2 1
2 1
+MVDD
+MVDD
C713
C713
1.8V
1.8V
12
12
+
MC713
MC713
330uF470uF
330uF470uF
2V
2V
C716
C716
2.2uF
2.2uF
2.5V
2.5V
2 1
2 1
2 1
2 1
C717
C717
22uF
22uF
2.5V
2.5V
C718
C718
22uF
22uF
2.5V
2.5V
2 1
2 1
12
12
+
C
R707
R707
2.2R
2.2R
5%
5%
2 12 1
2 1
C720
C720
0.0022uF
0.0022uF
50V
50V
2 1
C722
C722
0.1uF
0.1uF
25V
25V
21
21
NS700
NS700
NS_VIA
NS_VIA
21
21
+MVDD_FB
+MVDD_FB
R722
21
10R
10R
5% 5%
5% 5%
21
21
1%
1%
10K
10K
R708
R708
2 1
2 1
C721
C721
1000pF
1000pF
50V
50V
R723R722
R723
21
2121
FB_VMEMIO
10R
10R
MVDD=0.75V*(1+Rfb1/Rfb2)
MVDD=0.75V*(1+Rfb1/Rfb2)
FB_VMEMIO
IN
5
5
MVDD_LGATE
MVDD_LGATE
Q701
Q701
4
4
321
321
BSZ0901NS
BSZ0901NS
VDDC_VDDCI
VDDC_VDDCI
B B
14 15 11
14 15 11
IN
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
A
5
4
8
7
6
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
MVDD
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
MVDD
Mon Dec 14 13:52:58 2015
Mon Dec 14 13:52:58 2015
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
3
REV:
1711
1711
1.0
1.0
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
2
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
1
A
Page 12
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
IN+IN
OUT
AIN
PGND
PGND
PGND
PGND
PGND
FB
LX
LX
LX
LX
LX
BOOT
TON
VIN
VIN
VIN
SS
PFM
EN
POK
VCC
AGND
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
D D
+5VRUN
+5VRUN
21
R900
21R900
2.2R
2.2R
C902
C902
1uF
1uF
10V
10V
2 1
2 1
R902
R902
10K
10K
5%
5%
C
0.8V_EN
14
14
IN
+5VRUN
+5VRUN
0.8V_EN
R904
R904
10K
10K
5%
5%
C905
C905
0.01uF
0.01uF
R906
R906
100K
100K
1%
1%
R901
R901
10K
10K
+3VRUN
+3VRUN
5%
5%
U900
U900
1
1
POK
2
2
EN
3
3
PFM
4
4
AGND
5
5
FB
6
6
TON
GS9230-ATQ
GS9230-ATQ
23
23
SS
AIN
7
7
22
22
VIN
VIN
8
8
21
21
VCC
VIN
9
9
19
20
19
20
BOOT
PGND
PGND
PGND
PGND
PGND
LX
10
10
2 1
2 1
18
18
11
11
LX
LX
LX
LX
C900
1uF
1uF
10V
10V
0.1uF
0.1uF
25V
25V
21
21
17
17
16
16
15
15
14
14
13
13
12
12
2 1
2 1
C904
C904
C901C900
C901
0.1uF
0.1uF
10V
10V
+0.8V_PGOOD
+0.8V_PGOOD
R903
R903
68.1K
68.1K
470pF
470pF
DNI
DNI
1%
1%
C911
C911
L900
L900
21
DNI
DNI
50V
50V
8
8
OUT
+0.8V
1uH
1uH
21
21
12
12
C906
C906
0.1uF
0.1uF
C910
C910
DNI
DNI
21
2121
50V0.0033uF
50V0.0033uF
21
21
Ref=0.8v
Ref=0.8v
+
C907
C907
470uF
470uF
1.8V
1.8V
ESR = 6m
ESR = 6m
C908
C908
2.2uF
2.2uF
2.5V
2.5V
2 1
2 1
R908
R908
10K 1%
10K 1%
C918
C909
C918C909
22uF
22uF
22uF
22uF
2.5V
2.5V
2.5V
2.5V
2 1
2 1
2 1
2 1
21
21
21
21
NS900
NS900
+0.8V
C
+0.8V_FB
C912
C913
C912
10uF
10uF
10uF
10uF
16V
16V
16V
16V
2 1
2 1
2 1
2 1
2 1
2 1
C914
1uF
1uF
10V
10V
2 1
2 1
C915
C915C914C913
0.1uF
0.1uF
10V
10V
+0.8V_FB
IN
14
14
B B
A
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
0.8V REG
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
8
7
6
5
4
0.8V REG
Mon Dec 14 13:52:59 2015
Mon Dec 14 13:52:59 2015
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
3
REV:
1712
1712
1.0
1.0
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
2
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
1
A
Page 13
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
+
IN
OUT
IN
AIN
PGND
PGND
PGND
PGND
PGND
FB
LX
LX
LX
LX
LX
BOOT
TON
VIN
VIN
VIN
SS
PFM
EN
POK
VCC
AGND
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
17ci203
7
6
5 4 3
2
1
D D
R951
R951
10K
10K
+3VRUN
+3VRUN
5%
5%
23
POK
EN
PFM
AGND
FB
TON
23
7
7
U950
U950
1
1
2
2
3
3
4
4
5
5
6
6
GS9230-ATQ
GS9230-ATQ
22
22
SS
AIN
8
8
21
21
VIN
VIN
9
9
20
20
VCC
VIN
BOOT
C950
C950
10V
10V
2 1
2 1
C952
C952
0.1uF 25V
0.1uF 25V
19
18
19
18
LX
PGND
LX
LX
PGND
PGND
PGND
PGND
LX
LX
11
10
11
10
C951
C951
0.1uF1uF
0.1uF1uF
10V
10V
2 1
2 1
+1.8V_PGOOD
+1.8V_PGOOD
21
21
L950
L950
17
17
16
16
15
15
14
14
13
13
12
12
R953
R953
DNI
DNI
1%68.1K
1%68.1K
TC950
TC950
21
21
0.0033uF
0.0033uF
DNI
DNI
21
21
50V470pF
50V470pF
OUT
C961
C961
21
21
8
8
2.2uH
2.2uH
DNI
DNI
21
21
50V
50V
Ref=0.8v
Ref=0.8v
C955
C955
0.1uF
0.1uF
+
12
12
C954
C954
220uF
220uF
2V
2V
C956
C956
22uF
22uF
R955
R955
+1.8V
+1.8V
SCHEMATIC
SCHEMATIC
21
21
NS950
NS950
21
21
1%10K
1%10K
+5VRUN
+5VRUN
R950
21R950
2.2R
2.2R
21
C959
C959
1uF
1uF
10V
10V
2 1
2 1
R952
R952
10K
10K
5%
5%
C
1.8V_EN
14
14
IN
+5VRUN
+5VRUN
1.8V_EN
R954
R954
10K
10K
5%
5%
C953
C953
0.01uF
0.01uF
R956
R956
100K
100K
1%
1%
C
+1.8V_REG_FB
C962
10uF
10uF
10uF
10uF
16V16V
16V16V
2 1
2 1
2 1
2 1
2 1
2 1
C964C963C962
10V
10V
C965
C965
0.1uF1uF
0.1uF1uF
10V
10V
2 1
2 1
C964
C963
+1.8V_REG_FB
IN
14
14
B B
A
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
8
7
6
5
4
1.8V REG
1.8V REG
Mon Dec 14 13:52:59 2015
Mon Dec 14 13:52:59 2015
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
3
REV:
1713
1713
1.0
1.0
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
2
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
1
A
Page 14
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
OUT
OUT
OUT
OUTINOUT
OUT
OUTINOUTININININ
IN
SS
VDD
GNDEN
VOUT
VIN
OUT
OUT
OUT
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
D D
Power up Sequence Management
Power up Sequence Management
10K 5%
10K 5%
RUNPWROK
8 14
8 14
IN
RUNPWROK
R1303
21R1303
21
Circuits to support BACO
Circuits to support BACO
PX_EN
2 8
2 8
IN
PX_EN =0, for Normal Operation
C
PX_EN =0, for Normal Operation
PX_EN =1, for BACO mode to shut down power rails except VDD_GPIO33, PCIE_VDDC and 1.8V rail
PX_EN =1, for BACO mode to shut down power rails except VDD_GPIO33, PCIE_VDDC and 1.8V rail
PX_EN
C1302
C1302
0.1uF
0.1uF
10V
10V
2 1
2 1
+3VRUN
+3VRUN
R1306
R1306
10K
10K
1%
1%
R1307
1.5K
1%
1.5K
1%
R1307
21
Q1300
Q1300
2N7002
2N7002
21
C1305
C1305
0.1uF
0.1uF
10V
10V
3
3
1
1
2
2
SN74LVC1G08DBV
SN74LVC1G08DBV
U1300
U1300
1
1
2
2
SN74LVC1G08DBV
SN74LVC1G08DBV
U1300
U1300
+3VRUN
+3VRUN
4
4
C1306
C1306
53
53
0.1uF 10V
0.1uF 10V
PX_MODE
PX_MODE
Pre-PWROK Output Voltage
Pre-PWROK Output Voltage
+1.8V
+1.8V
3-PADS/2
3-PADS/2
R1308
R1308
R1309
R1309
R1310
R1310
R1311
R1311
R1300
R1300
DNI
0.8V_EN
0.8V_EN
14 12
14 12
PWR_EN
14
14
14
14
8 14
8 14
PWR_EN
RUNPWROK
RUNPWROK
PX_MODE
PX_MODE
PX_MODE
PX_MODE
8 14
8 14
IN
21
21
14
14
OUT
DNI
10K 5%
10K 5%
R1301
R1301
R1304
R1304
R1302
R1302
R1336
R1336
21
21
5%10K
5%10K
1.8V_EN
C1300
C1300
0.1uF
0.1uF
10V
10V
2 1
2 1
DNI
DNI
C1304
C1304
0.1uF
0.1uF
10V
10V
2 1
2 1
C1301
C1301
0.1uF
0.1uF
10V
10V
2 1
2 1
C1336
C1336
0.1uF
0.1uF
10V
10V
2 1
2 1
1.8V_EN
0.8V_EN
0.8V_EN
VDDC_I_EN
VDDC_I_EN
MVDD_EN
MVDD_EN
OUT
OUT
OUT
OUT
13
13
12 14
12 14
9
9
11
11
+0.8V_FB
+0.8V_FB
+1.8V_REG_FB
+1.8V_REG_FB
+VDD33
+VDD33
GPIO_30
IN
GPIO_30
6
6
21
21
5%10K
5%10K
21
21
21
21
5%10K
5%10K
21
21
5%10K
5%10K
R1335
R1335
10K
10K
1%
1%
2 12 1
2 1
R1305
R1305
10K
10K
1%
1%
2 1
DNI
DNI
DNI
DNI
1
1
R1334
R1334
51.1K
51.1K
1%
1%
2 1
2 1
3
3
2
2
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
5%10K
Q1304
Q1304
2N7002
2N7002
SVC
SVC
SVD
SVD
R1337
R1337
10K
10K
1%
1%
2 1
2 1
R1333
R1333
8.06K
8.06K
1%
1%
2 1
2 1
R1332
R1332
12.4K
12.4K
1%
1%
2 1
2 1
OUT
OUT
+MVDD_FB
+MVDD_FB
6 9
6 9
6 9
6 9
OUT
OUT
GPIO21
GPIO21
GPIO21
GPIO21
SVD
SVC
SVC
12
12
13
13
15 11
15 11
OUT
R1332=43.2K@1.35V if add POT U1400
R1332=43.2K@1.35V if add POT U1400
VREF 0.75V
VREF 0.75V
0
0
1
1
12.4K
12.4K
10K(9.98K)
10K(9.98K)
SVD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1.355V
1.355V
1.501V
1.501V
V
V
1.1
1.1
1.0
1.0
0.9
0.9
0.8
0.8
C
3.3v switch
3.3v switch
+3VRUN
+3VRUN
R1342
B B
C1341
+3VRUN
+3VRUN
C1342
C1342
MXM
MXM
10uF
10uF
6.3V
6.3V
2 1
2 1
R1341
PWR_EN
8 14
8 14
IN
PWR_EN
R1341
C1341
0.1uF
0.1uF
10V
10V
2 1
2 12 1
C1343
C1343
0.1uF
0.1uF
10V
10V
2 1
VDD33_EN
VDD33_EN
21
21
5%10K
5%10K
C1344
C1344
0.1uF
0.1uF
10V
10V
2 1
2 1
C1
C1
A1
A1
R1342
0R 5%
0R 5%
U2
U2
VDD
VIN
APL3527GHAI
APL3527GHAI
21
21
VOUT
GNDEN
+VDD33
+VDD33
A2
A2
C1347C1346
C1347
C2
C2
SS
B2B1
B2B1
2 1
2 1
C1345
C1345
220pF
220pF
50V
50V
C1346
1uF
1uF
6.3V
6.3V
2 1
2 1
10uF
10uF
6.3V
6.3V
2 1
2 1
6
6
IN
CTF
CTF
GPIO_19_CTF
GPIO_19_CTF
R1324
8 2 9
8 2 9
IN
21R1324
5%4.7K
5%4.7K
21
PERSTb_RST#
PERSTb_RST#
D1300
D1300
BAT54S
BAT54S
1
1
2
2
A
DESCRETE CRTICAL TEMPERATURE FAILURE LATCH CIRCUITS
DESCRETE CRTICAL TEMPERATURE FAILURE LATCH CIRCUITS
(OPTIONAL)
(OPTIONAL)
R1325
R1325
5%47K
5%47K
3
3
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
BACO & CTF & PWR Managerment
BACO & CTF & PWR Managerment
Mon Dec 14 13:52:59 2015
Mon Dec 14 13:52:59 2015
SHEET NUMBER:
DOCUMENT NUMBER:
+3VRUN
+3VRUN
23
23
Q1301
Q1301
MMBT3906
MMBT3906
CTF_VCNTL
CTF_VCNTL
R1323
R1323
20K
20K
5%
5%
C1309
C1309
1uF
1uF
6.3V
6.3V
1
1
1714
1714
CTF_TRIP
CTF_TRIP
R1327
R1327
100K
100K
5%
5%
OF
105_C985xx_00B
105_C985xx_00B
1
1
R1315
R1315
20K
20K
5%
5%
R1321
5%1K
5%1K
DNI
DNI
1.0
1.0
R1321
21R1320
R1320
R1322
R1322
20K
20K
5%
5%
Q1303
Q1303
MMBT3904
MMBT3904
2 3
2 3
5%2.2K 5%2.2K
5%2.2K 5%2.2K
21
REV:
CTFb
CTFb
21
1
5%0R
5%0R
R1331R1330
R1331R1330
121
C1331
C1331
0.1uF
0.1uF
6.3V
6.3V
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
Q1302
Q1302
MMBT3904
MMBT3904
2 3
2 3
Advanced Micro Devices
2015
2015
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
OUT
8
8
A
NOTES:
8
7
6
5
4
NOTE
NOTE
3
2
1
Page 15
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
EXT_CAP
A
W
SDA
SCL
ADDR
RESET_N VDD
VSS
GND
THM
THM
INBIIN
OUT
OUT
OUT
IN
REV 0.91
symbol10
TEMPINRETURN
TEMPIN0
TS_A
TSVDD
GPIO_28_FDO
DPLUS
DMINUS
SMBCLK
SMBDATA
ALERT
GND T_CRIT_A
D-
D+
VDD
ININOUT
OUT
OUTININININ
OUT
REV 0.91
symbol1
TEST6
BP_1
BP_0
TESTEN
JTAG_TRSTB
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
OUT
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
JTAG
JTAG
TP1002
D D
TP1002
TP1003
TP1003
+1.8V
+1.8V
SCHEMATIC
SCHEMATIC
SCHEMATIC
SCHEMATIC
DIGITAL POT
DIGITAL POT
+3VRUN
2 1
2 1
+3VRUN
C1070
0.1uF
0.1uF
6.3V
6.3V
6.3V
6.3V
2 1
2 1
C1071C1070
C1071
10uF
10uF
6.3V
6.3V
+MVDD_FB
+MVDD_FB
2 1
2 1
R1072
R1072
7.5K
7.5K
1%
1%
OUT
14 11
14 11
ADDRESS
ADDRESS
GND
R4002R4001
R4002R4001
10K10K
10K10K
5%5%
5%5%
AA38
BP_0
BP_0
R4003
R4003
R4004
R4004
R4000
R4000
33R
33R
33R
33R
0R
0R
5%
5%
5%
5%
5%
5%
DIECRACKMON
DIECRACKMON
BP_1
BP_1
AA38
BP_0
AA37
AA37
BP_1
TEST6
BAFFIN - REV 0.90
BAFFIN - REV 0.90
U1
U1
symbol1
JTAG_TRSTB
REV 0.91
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK
TESTEN
AF41
AF41
AD40
AD40
AD41
AD41
AE41
AE41
AE40B2
AE40B2
AF40
AF40
JTAG_TDO
JTAG_TDO
JTAG_TDI
JTAG_TDI
JTAG_TMS
JTAG_TMS
JTAG_TCK
JTAG_TCK
TESTEN
TESTEN
8
JTAG_TRSTb
JTAG_TRSTb
8
R4005
R4005
MR4005
MR4005
OUT
IN
IN
IN
IN
DNI
DNI
8
8
8
8
8
8
8
8
8
8
+3VRUN
+3VRUN
5%
5%
1K
1K
5%
5%
1K
1K
+3VRUN
+3VRUN
MR4006
MR4006
1K
1K
5%
5%
DNI
DNI
R4006
R4006
1K
1K
5%
5%
GND
Vdd
Vdd
NC
NC
0101111
0101111
0101100
0101100
0101110
0101110
6 15
6 15
6 15
6 15
IN
BI
+3VRUN
+3VRUN
SCL
SCL
SDA
SDA
R1070
R1070
R1071
R1071
R1060
R1060
R1061
R1061
10K 5%
10K 5%
10K 5%
10K 5%
0R
0R
0R 5%
0R 5%
5%
5%
DNI
DNI
DNI
DNI
SCL_MVDD
SCL_MVDD
SDA_MVDD
SDA_MVDD
U1400
U1400
7
7
RESET_N VDD
10
10
ADDR
9
9
SCL
8
8
SDA
6
6
GND
11
11
THM
12
12
THM
20K
20K
EXT_CAP
VSS
1
1
3
3
W
2
2
A
C1072
5
5
4
4
21
1uF
1uF
21C1072
THERMAL
THERMAL
+1.8V
+1.8V
C200
C
Q200
Q200
MMBT3904
MMBT3904
OPTIONAL EXTERNAL THERMAL SENSOR
OPTIONAL EXTERNAL THERMAL SENSOR
6 15
6 15
B B
IN
6 15
6 15
IN
8
8
OUT
8
8
OUT
SCL
SCL
SDA
SDA
2 3
2 3
R202
R202
0R
0R
5%
5%
DNI
DNI
1
1
R1313
R1313
R1314
R1314
PBAT_SMBCLK
PBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBDAT
TP200
TP200
0R
0R
0R
0R
C201
C201
0.0022uF
0.0022uF
50V
50V
C200
1uF
1uF
6.3V
6.3V
TEMPIN0
TEMPIN0
TEMPINRETURN
TEMPINRETURN
TS_A
TS_A
5%
5%
5%
5%
AM13
AM13
TSVDD
J8
J8
TEMPIN0
J7
J7
TEMPINRETURN
N38
N38
TS_A
BAFFIN - REV 0.90
BAFFIN - REV 0.90
C1307
C1307
U1301
U1301
8
8
SMBCLK
7
7
SMBDATA
6
6
ALERT
5
5
GND T_CRIT_A
LM89-1DIMM
LM89-1DIMM
U1
U1
symbol10
REV 0.91
21
21
0.1uF
0.1uF
VDD
D+
D-
DPLUS
DMINUS
GPIO_28_FDO
6.3V
6.3V
1
1
2
2
3
3
4
4
N35
N35
N34
N34
U38
U38
0R
0R
0.0022uF
0.0022uF
R1312
R1312
R1316
R1316
R1317
R1317
R1318
R1318
R1319
R1319
GPU_DPLUS
GPU_DPLUS
GPU_DMINUS
GPU_DMINUS
GPIO_28_FDO
GPIO_28_FDO
R200
R200
10K
10K
5%
5%
DNI
DNI
21
21
5%
5%
C1308
C1308
50V
50V
GPU_DPLUS
GPU_DPLUS
GPU_DMINUS
GPU_DMINUS
DNI
DNI
DNI
DNI
+3VRUN
+3VRUN
0R
0R
0R
0R
0R
0R
0R
0R
15
15
15
15
15
15
OUT
OUT
5%
5%
5%
5%
5%
5%
5%
5%
ADDRESS
ADDRESS
15
15
15
15
MB_THERMB
MB_THERMB
MB_ALERTB
MB_ALERTB
0x9A
0x9A
OUT
IN
8
8
6 8
6 8
C
A
LM89 OR LM96
LM89 OR LM96
+3VRUN
+3VRUN
R1326
R1326
DNI
DNI
3K
+3VRUN
+3VRUN
53
53
3K
5%
5%
U1302
U1302
NC7SZ08P5X
NC7SZ08P5X
R1328
R1328
R1329
R1329
DNI
DNI
21
21
0R 5%
0R 5%
GPIO_28_FDO
0R
0R
5%
5%
GPIO_28_FDO
IN
15
15
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
DEBUG & THERMAL
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
NOTES:
5
4
DEBUG & THERMAL
Mon Dec 14 13:52:57 2015
Mon Dec 14 13:52:57 2015
OF
105_C985xx_00B
105_C985xx_00B
NOTE
NOTE
3
REV:
1715
1715
1.0
1.0
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
2
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
1
A
21
21
6
NC7SZ08P5X
NC7SZ08P5X
U1302
U1302
TH_PWM
8
8
OUT
TH_PWM
8
4
4
C1330
C1330
0.1uF
0.1uF
6.3V
6.3V
7
1
1
2
2
2 1
2 1
Page 16
DOCUMENT NUMBER:
TITLE:
C
is provided only to entities under a non-disclosure agreement with AMD
NOTES:
2
OF
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7
6
6
5 4 3
3
2
SHEET:
SHEET NUMBER:
DATE:
This AMD Board schematic and design is the exclusive property of AMD, and
Advanced Micro Devices
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
information included herein.
responsibility for any consequences resulting from use of the
of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
MEMORY CHANNEL A & B
MEMORY CHANNEL A & B
GDDR5 4PCS 256Mx32
GDDR5 4PCS 256Mx32
D D
POWER REGULATORS
POWER REGULATORS
FROM +PWR_SRC
FROM +PWR_SRC
+VDDC,VDDCI, +MVDD
+VDDC,VDDCI, +MVDD
FROM +5VRUN
FROM +5VRUN
1.8V_REG, PCIE_REG
1.8V_REG, PCIE_REG
TMDP
TMDP
TMDPA
TMDPA
DDCAUX1
DDCAUX1
HPD1
HPD1
DP_A
DP_A
DP_A_LX/LX#
DP_A_LX/LX#
DP_A_AUX/AUX#
DP_A_AUX/AUX#
DP_A_HPD
DP_A_HPD
DP_B
FROM +3VRUN
FROM +3VRUN
VDD33
VDD33
FROM +VDDC
C
FROM +VDDC
VDDC, VDDCI
VDDC, VDDCI
FROM +MVDD
FROM +MVDD
VMEMIO, MVDDQ/C
VMEMIO, MVDDQ/C
FROM 1.8V_REG
FROM 1.8V_REG
VDD18
VDD18
FROM PCIE_REG
FROM PCIE_REG
VDD08
VDD08
STRAPS
STRAPS
BIOS
BIOS
OSC/SS
OSC/SS
DYNAMIC MVDD
DYNAMIC MVDD
DYNAMIC VDDC/I
DYNAMIC VDDC/I
GPIO
GPIO
ROM
ROM
XTALIN/OUT
XTALIN/OUT
GPIO21
GPIO21
SVI2
SVI2
TMDPB
TMDPB
DDCAUX2
DDCAUX2
HPD2
HPD2
TMDPC
TMDPC
DDCAUX3
DDCAUX3
HPD3
HPD3
TMDPD
TMDPD
DDCAUX4
DDCAUX4
HPD4
HPD4
TMDPE
TMDPE
DDCAUX5
DDCAUX5
HPD5
HPD5
DP_B
DP_B_LX/LX#
DP_B_LX/LX#
DP_B_AUX/AUX#
DP_B_AUX/AUX#
DP_B_HPD
DP_B_HPD
DP_C
DP_C
DP_C_LX/LX#
DP_C_LX/LX#
DP_C_AUX/AUX#
DP_C_AUX/AUX#
DP_C_HPD
DP_C_HPD
DP_D
DP_D
DP_D_LX/LX#
DP_D_LX/LX#
DP_D_AUX/AUX#
DP_D_AUX/AUX#
DP_D_HPD
DP_D_HPD
DP_E
DP_E
DP_D_LX/LX#
DP_D_LX/LX#
DP_D_AUX/AUX#
DP_D_AUX/AUX#
DP_D_HPD
DP_D_HPD
C
POWER DELIVERY
B B
MXM3.0 SOURCE
MXM3.0 SOURCE
+PWR_SRC +3VRUN +5VRUN
+PWR_SRC +3VRUN +5VRUN
ENABLE CIRCUIT
ENABLE CIRCUIT
SMPS
SMPS
PWR_EN
PWR_EN
3VRUN (3.3V/1A)
3VRUN (3.3V/1A)
5VRUN (5V/2.5A)
5VRUN (5V/2.5A)
PWR_SRC (7~20V/UP TO 10A)
PWR_SRC (7~20V/UP TO 10A)
A
POWER DELIVERY
MXM3.0 CONNECTOR
MXM3.0 CONNECTOR
GPU M2
GPU M2
GPIO19_CTF
GPIO19_CTF
PCIE
PCIE
THERMAL
THERMAL
SMBCLK/DATA
SMBCLK/DATA
SCL/SDA
SCL/SDA
D+/D-
D+/D-
GPIO17
GPIO17
GPIO19_CTF
GPIO19_CTF
External thermal sensor
External thermal sensor
MxM3.1 TYPE A
MxM3.1 TYPE A
BAFFIN GDDR5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
BAFFIN GDDR5
BLOCK DIAGRAM
BLOCK DIAGRAM
Mon Dec 14 13:36:59 2015
Mon Dec 14 13:36:59 2015
OF
105_C985xx_00B
105_C985xx_00B
1716
1716
SMB_CLK/DAT
SMB_CLK/DAT
TH_ALERT#
TH_ALERT#
TH_OVERT#
TH_OVERT#
REV:
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Advanced Micro Devices
2015
2015
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
A
NOTES:
8
7
6
5
4
NOTE
NOTE
3
2
1
Page 17
OF
TITLE:
2
REV:
4
A
C
D D
1
1
A
B B
C
5
8
8
7
7 6
5 4 3
3
2
DATE:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
6
DOCUMENT NUMBER: SHEET NUMBER:
PCB
ENGINEER:
REVISION DESCRIPTON
responsibility for any consequences resulting from use of the information included herein.
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
C Advanced Micro Devices
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
NOTES:
Rev
SCH
Rev
Date
REVISION HISTORY
AMD
8
00017967 jonepei(裴亮樂)
RD(C)2017091902 RMA工程課
石阿鋒 (00068760)
7
6
5 4 3
2
1
AMD
REVISION HISTORY
SCH
Rev
D D
1
1
PCB
Rev
00A
00A
00B
00B
Date
08/23/20150
08/23/20150
11/25/2015
11/25/2015
INITIAL DESIGN
INITIAL DESIGN
1.ADD DDCVGADATA/CLK
1.ADD DDCVGADATA/CLK
2.MVDD SWITCH GPIO CHANGED TO GPIO30
2.MVDD SWITCH GPIO CHANGED TO GPIO30
3.ADD GPIO21 PULL UP/DOWN
3.ADD GPIO21 PULL UP/DOWN
4 ADD 3.3V SWITCH
4 ADD 3.3V SWITCH
5 REMAPPING DPA, DPB AND DPC, DPD TO SUPPORT DL_DVI
5 REMAPPING DPA, DPB AND DPC, DPD TO SUPPORT DL_DVI
6 JTAG FOLLOW MXM3.1 SPEC
6 JTAG FOLLOW MXM3.1 SPEC
TITLE:
BAFFIN GL Pro 4x32 G5 TYPE A
BAFFIN GL Pro 4x32 G5 TYPE A
ENGINEER:
Peak
Peak
NOTES:
105_C985xx_00B
DOCUMENT NUMBER: SHEET NUMBER:
NOTE
NOTE
105_C985xx_00B
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the information included herein.
REVISION DESCRIPTON
DATE:
2015
2015
C Advanced Micro Devices
1717Mon Dec 07 17:12:09 2015
OF
1717Mon Dec 07 17:12:09 2015
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
REV:
1.0
1.0
C
B B
C
A
8
7 6
5
4
3
2
1
A
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