Page 1
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(1) PCI-EXPRESS EDGE CONNECTOR
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
GPIO_4_SMBCLK
7
IN
GPIO_3_SMBDATA
7
BI
PLACE THESE CAPS AS CLOSE TO
PCIE CONNECTOR AS POSSIBLE
+12V_BUS
C157
C151
C152
10uF
0.15uF
0.15uF
16V
16V
C
C
C
B B
+3.3V_BUS
16V
C153
C154
C155
10uF
0.1uF
1uF
6.3V
0.01uF
6.3V
6.3V
C156
10V
+3.3V_BUS +3.3V_BUS +12V_BUS +12V_BUS +3.3V_BUS
R105
45.3K
1%
DNI DNI
C C
Mechanical Key
MPCIE1
x16 PCIe
PRSNT1_A1
PERST_
REFCLK+
REFCLK-
RSVD_A19
RSVD_A32
RSVD_A33
RSVD_A50
PERp10
PERn10
PERp11
PERn11
PERp12
PERn12
PERp13
PERn13
PERp14
PERn14
PERp15
PERn15
A1
A2
+12V
A3
+12V
A4
GND
A5
JTAG2
A6
JTAG3
A7
JTAG4
A8
JTAG5
A9
+3.3V
A10
+3.3V
A11
A12
GND
A13
A14
A15
GND
A16
PERp0
A17
PERn0
A18
GND
A19
A20
GND
A21
PERp1
A22
PERn1
A23
GND
A24
GND
A25
PERp2
A26
PERn2
A27
GND
A28
GND
A29
PERp3
A30
PERn3
A31
GND
A32
A33
A34
GND
A35
PERp4
A36
PERn4
A37
GND
A38
GND
A39
PERp5
A40
PERn5
A41
GND
A42
GND
A43
PERp6
A44
PERn6
A45
GND
A46
GND
A47
PERp7
A48
PERn7
A49
GND
A50
A51
GND
A52
PERp8
A53
PERn8
A54
GND
A55
GND
A56
PERp9
A57
PERn9
A58
GND
A59
GND
A60
A61
A62
GND
A63
GND
A64
A65
A66
GND
A67
GND
A68
A69
A70
GND
A71
GND
A72
A73
A74
GND
A75
GND
A76
A77
A78
GND
A79
GND
A80
A81
A82
GND
B1
+12V
B2
R106
45.3K
1%
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PETP0_GFXRP0
OUT
PETN0_GFXRN0
OUT
PETP1_GFXRP1
OUT
PETN1_GFXRN1
OUT
PETP2_GFXRP2
OUT
PETN2_GFXRN2
OUT
PETP3_GFXRP3
OUT
PETN3_GFXRN3
OUT
PETP4_GFXRP4
OUT
PETN4_GFXRN4
OUT
PETP5_GFXRP5
OUT
PETN5_GFXRN5
OUT
PETP6_GFXRP6
OUT
PETN6_GFXRN6
OUT
PETP7_GFXRP7
OUT
PETN7_GFXRN7
OUT
PETP8_GFXRP8
OUT
PETN8_GFXRN8
OUT
PETP9_GFXRP9
OUT
PETN9_GFXRN9
OUT
PETP10_GFXRP10
OUT
PETN10_GFXRN10
OUT
PETP11_GFXRP11
OUT
PETN11_GFXRN11
OUT
PETP12_GFXRP12
OUT
PETN12_GFXRN12
OUT
PETP13_GFXRP13
OUT
PETN13_GFXRN13
OUT
PETP14_GFXRP14
OUT
PETN14_GFXRN14
OUT
PETP15_GFXRP15
OUT
PETN15_GFXRN15
OUT
PRESENCE
1
+12V
B3
+12V
B4
GND
B5
SMCLK
B6
SMDAT
B7
GND
B8
+3.3V
B9
JTAG1
B10
3.3Vaux
B11
WAKE_
B12
RSVD_B12
B13
GND
B14
PETp0
B15
PETn0
B16
GND
B17
PRSNT2_B17
B18
GND
B19
PETp1
B20
PETn1
B21
GND
B22
GND
B23
PETp2
B24
PETn2
B25
GND
B26
GND
B27
PETp3
B28
PETn3
B29
GND
B30
RSVD_B30
B31
PRSNT2_B31
B32
GND
B33
PETp4
B34
PETn4
B35
GND
B36
GND
B37
PETp5
B38
PETn5
B39
GND
B40
GND
B41
PETp6
B42
PETn6
B43
GND
B44
GND
B45
PETp7
B46
PETn7
B47
GND
B48
PRSNT2_B48
B49
GND
B50
PETp8
B51
PETn8
B52
GND
B53
GND
B54
PETp9
B55
PETn9
B56
GND
B57
GND
B58
PETp10
B59
PETn10
B60
GND
B61
GND
B62
PETp11
B63
PETn11
B64
GND
B65
GND
B66
PETp12
B67
PETn12
B68
GND
B69
GND
B70
PETp13
B71
PETn13
B72
GND
B73
GND
B74
PETp14
B75
PETn14
B76
GND
B77
GND
B78
PETp15
B79
PETn15
B80
GND
B81
PRSNT2_B81
B82
RSVD_B82
PRESENCE
JTDIO_LOOP
PCIE_REFCLKP
PCIE_REFCLKN
PERP0
PERN0
PERP1
PERN1
PERP2
PERN2
PERP3
PERN3
PERP4
PERN4
PERP5
PERN5
PERP6
PERN6
PERP7
PERN7
PERP8
PERN8
PERP9
PERN9
PERP10
PERN10
PERP11
PERN11
PERP12
PERN12
PERP13
PERN13
PERP14
PERN14
PERP15
PERN15
SYSTEM JTAG TDI AND
TDO ARE HARD WIRED.
1
2
OUT
2
OUT
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
DD
DD
DD
1.8V_EN
19,18
IN
PERSTB
+3.3V_BUS
U100B
NC7SZ08P5X
3 5
U100A
1
2
NC7SZ08P5X
C158
0.1uF
6.3V
PERSTB_BUF
4
2,20
OUT
C
C
C
BB
BB
BB
SYMBOL LEGEND
DO NOT
DNI
INSTALL
ACTIVE
b or #
LOW
BRING UP
BUO
ONLY
DIGITAL
GROUND
ANALOG
GROUND
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
A
A
A
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
PCIE EDGE CONNECTOR
PCIE EDGE CONNECTOR
PCIE EDGE CONNECTOR
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:18 2015 1.0
Thu Jan 15 02:26:18 2015 1.0
Thu Jan 15 02:26:18 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
123
123
123
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
REV:
REV:
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
Page 2
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(2) TRINIDAD PCIE INTERFACE
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
SOME PCIE TEST POINTS ARE
A A
C
C
C
B B
C C
+0.95V
A
A
A
OVERLAP C141 AND MC141
AVAILABLE THROUGH VIAS ON TRACES
TP101
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
+0.95V
+1.8V
TP102
TP117
TP118
C175
C176
1uF
1uF
6.3V
6.3V
C141
MC141
4.7uF
10uF
6.3V
6.3V
C137
1uF
6.3V
C133
1uF
6.3V
C147
1uF
6.3V
C161
C162
0.1uF
0.1uF
6.3V
6.3V
OVERLAP C148 AND MC148
PETP0_GFXRP0
PETN0_GFXRN0
PETP1_GFXRP1
PETN1_GFXRN1
PETP2_GFXRP2
PETN2_GFXRN2
PETP3_GFXRP3
PETN3_GFXRN3
PETP4_GFXRP4
PETN4_GFXRN4
PETP5_GFXRP5
PETN5_GFXRN5
PETP6_GFXRP6
PETN6_GFXRN6
PETP7_GFXRP7
PETN7_GFXRN7
PETP8_GFXRP8
PETN8_GFXRN8
PETP9_GFXRP9
PETN9_GFXRN9
PETP10_GFXRP10
PETN10_GFXRN10
PETP11_GFXRP11
PETN11_GFXRN11
PETP12_GFXRP12
PETN12_GFXRN12
PETP13_GFXRP13
PETN13_GFXRN13
PETP14_GFXRP14
PETN14_GFXRN14
PETP15_GFXRP15
PETN15_GFXRN15
PCIE_REFCLKP
1
IN
PCIE_REFCLKN
1
IN
PCIE_REFCLKx_OUTx
WORKSTATION DESIGNS
MAY USE THIS FEATURE
PERSTB_BUF
1,20
IN
C171
C172
C177
10uF
1uF
1uF
6.3V
6.3V
6.3V
C140
C136
C139
0.01uF
1uF
0.1uF
6.3V
6.3V
6.3V
C138
C142
1uF
1uF
6.3V
6.3V
C146
C144
C145
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1319
C150
C1284
1uF
1uF
1uF
6.3V
6.3V
6.3V
10u
C148
C163
0.1uF
6.3V
MC148
C160
4.7uF
10uF
10uF
6.3V
6.3V
4V
AR50
PCIE_RX0P
AP49
PCIE_RX0N
AP51
PCIE_RX1P
AN52
PCIE_RX1N
AN50
PCIE_RX2P
AM49
PCIE_RX2N
AM51
PCIE_RX3P
AL52
PCIE_RX3N
AL50
PCIE_RX4P
AK49
PCIE_RX4N
AK51
PCIE_RX5P
AJ52
PCIE_RX5N
AJ50
PCIE_RX6P
AH49
PCIE_RX6N
AH51
PCIE_RX7P
AG52
PCIE_RX7N
AG50
PCIE_RX8P
AF49
PCIE_RX8N
AF51
PCIE_RX9P
AE52
PCIE_RX9N
AE50
PCIE_RX10P
AD49
PCIE_RX10N
AD51
PCIE_RX11P
AC52
PCIE_RX11N
AC50
PCIE_RX12P
AB49
PCIE_RX12N
AB51
PCIE_RX13P
AA52
PCIE_RX13N
AA50
PCIE_RX14P
Y49
PCIE_RX14N
Y51
PCIE_RX15P
W52
PCIE_RX15N
AR47
PCIE_REFCLKP
AR46
PCIE_REFCLKN
AN44
PCIE_REFCLKP_OUT0
AN43
PCIE_REFCLKN_OUT0
AT51
PCIE_REFCLKP_OUT1
AR52
PCIE_REFCLKN_OUT1
AU48
PERSTB
AK40
BIF_VDDC
AG40
BIF_VDDC
AH41
C173
1uF
6.3V
BIF_VDDC
AL41
BIF_VDDC
AT42
PCIE_PVDD
AU42
PCIE_PVDD
AR48
NC_PCIE_VDDR
AT43
NC_PCIE_VDDR
AT44
NC_PCIE_VDDR
AT45
NC_PCIE_VDDR
AT46
NC_PCIE_VDDR
AT47
NC_PCIE_VDDR
AT48
NC_PCIE_VDDR
AB43
PCIE_VDDC
AB44
PCIE_VDDC
AB45
PCIE_VDDC
AD42
PCIE_VDDC
AF42
PCIE_VDDC
AG42
PCIE_VDDC
AH42
PCIE_VDDC
AK42
PCIE_VDDC
AL42
PCIE_VDDC
AM42
PCIE_VDDC
AN42
PCIE_VDDC
AR42
PCIE_VDDC
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
PART 2 OF 18
PITCAIRN
U1B
AN47
PCIE_TX0P
AN46
PCIE_TX0N
AM44
PCIE_TX1P
AM43
PCIE_TX1N
AM47
PCIE_TX2P
AM46
PCIE_TX2N
AL44
PCIE_TX3P
AL43
PCIE_TX3N
AL47
PCIE_TX4P
AL46
PCIE_TX4N
AJ44
PCIE_TX5P
AJ43
PCIE_TX5N
AJ47
PCIE_TX6P
AJ46
PCIE_TX6N
AH44
PCIE_TX7P
AH43
PCIE_TX7N
AH47
PCIE_TX8P
AH46
PCIE_TX8N
AF44
PCIE_TX9P
AF43
PCIE_TX9N
P
C
I
E
X
P
R
E
S
S
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_CALRP_TX
PCIE_CALRN_RX
AF47
AF46
AE44
AE43
AE47
AE46
AC44
AC43
AC47
AC46
AB47
AB46
AR44
AR43
T51
PX_EN
AA48
VSS
AB48
VSS
AB53
VSS
AC45
VSS
AC48
VSS
AD48
VSS
AD53
VSS
AE45
VSS
AE48
VSS
AF45
VSS
AF48
VSS
AF53
VSS
AG48
VSS
AH45
VSS
AH48
VSS
AH53
VSS
AJ45
VSS
AJ48
VSS
AK48
VSS
AK53
VSS
AL45
VSS
AL48
VSS
AM45
VSS
AM48
VSS
AM53
VSS
AN45
VSS
AN48
VSS
AP48
VSS
AP53
VSS
AR45
VSS
AT49
VSS
AT53
VSS
W50
VSS
Y48
VSS
Y53
VSS
4
4
4
5
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_CALRP_TX
PCIE_CALRN_RX
PX_EN
R150
DNI
PCIE_VSS MERGED TO VSS IN PITCAIRN
FOR BARTS, USE 110NF
C100
6.3V0.22uF
C101
6.3V0.22uF
C102
6.3V0.22uF
C103
6.3V0.22uF
C104
6.3V0.22uF
C105 6.3V0.22uF
C106
6.3V0.22uF
C107
6.3V0.22uF
C108
6.3V0.22uF
C109
6.3V0.22uF
C111
6.3V0.22uF
C110
6.3V0.22uF
C112
6.3V0.22uF
C113
6.3V0.22uF
C114
6.3V0.22uF
C115 6.3V0.22uF
C116
6.3V0.22uF
C117 6.3V0.22uF
C118
6.3V0.22uF
C119
6.3V0.22uF
C120
6.3V0.22uF
C121
6.3V0.22uF
C122
0.22uF 6.3V
C123
6.3V0.22uF
C124
0.22uF 6.3V
C125
6.3V0.22uF
C126 0.22uF 6.3V
C127
6.3V0.22uF
C128
6.3V0.22uF
C129 0.22uF 6.3V
C130
0.22uF 6.3V
C131
0.22uF 6.3V
R100 1.69K 1%
R101 1K 1%
GROUND PX_EN (T51) FOR BARTS (NO BACO)
1K
5%
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD PCIE INTERFACE
TRINIDAD PCIE INTERFACE
TRINIDAD PCIE INTERFACE
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:19 2015 1.0
Thu Jan 15 02:26:19 2015 1.0
Thu Jan 15 02:26:19 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
PERP0
OUT
PERN0
OUT
PERP1
OUT
PERN1
OUT
PERP2
OUT
PERN2
OUT
PERP3
OUT
PERN3
OUT
PERP4
OUT
PERN4
OUT
PERP5
OUT
PERN5
OUT
PERP6
OUT
PERN6
OUT
PERP7
OUT
PERN7
OUT
PERP8
OUT
PERN8
OUT
PERP9
OUT
PERN9
OUT
PERP10
OUT
PERN10
OUT
PERP11
OUT
PERN11
OUT
PERP12
OUT
PERN12
OUT
PERP13
OUT
PERN13
OUT
PERP14
OUT
PERN14
OUT
PERP15
OUT
PERN15
OUT
PCIE_CALRP_TX:
PU R100 (1.69K) FOR PITCAIRN
+0.95V
PCIE_CALRN_RX:
PU R101 (1K) FOR PITCAIRN
19,20
OUT
223
223
223
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
DD
DD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
REV:
REV:
REV:
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
DD
C
C
C
BB
BB
BB
A
A
A
Page 3
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(3) TRINIDAD MEM INTERFACE CH A/B
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
DQA0_<0>
5,3
A A
C
C
C
B B
C C
BI
DQA0_<1>
5,3
BI
DQA0_<2>
5,3
BI
DQA0_<3>
5,3
BI
DQA0_<4>
5,3
BI
DQA0_<5>
5,3
BI
DQA0_<6>
5,3
BI
DQA0_<7>
5,3
BI
DQA0_<8>
5,3
BI
DQA0_<9>
5,3
BI
DQA0_<10>
5,3
BI
DQA0_<11>
5,3
BI
DQA0_<12>
5,3
BI
DQA0_<13>
5,3
BI
DQA0_<14>
5,3
BI
DQA0_<15>
5,3
BI
DQA0_<16>
5,3
BI
DQA0_<17>
5,3
BI
DQA0_<18>
5,3
BI
DQA0_<19>
5,3
BI
DQA0_<20>
5,3
BI
DQA0_<21>
5,3
BI
DQA0_<22>
5,3
BI
DQA0_<23>
5,3
BI
DQA0_<24>
5,3
BI
DQA0_<25>
5,3
BI
DQA0_<26>
5,3
BI
DQA0_<27>
5,3
BI
DQA0_<28>
5,3
BI
DQA0_<29>
5,3
BI
DQA0_<30>
5,3
BI
DQA0_<31>
5,3
BI
MAA0_<0>
5,3
BI
MAA0_<1>
5,3
BI
MAA0_<2>
5,3
BI
MAA0_<3>
5,3
BI
MAA0_<4>
5,3
BI
MAA0_<5>
5,3
BI
MAA0_<6>
5,3
BI
MAA0_<7>
5,3
BI
MAA0_<8>
5,3
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
WCKA0_0
WCKA0B_0
WCKA0_1
WCKA0B_1
EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3
DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3
ADBIA0
CSA0B_0
CASA0B
RASA0B
WEA0B
CKEA0
CLKA0
CLKA0B
R52
P49
P51
P53
M53
M51
L50
K49
T44
T45
T47
R43
R45
P47
P42
N42
K48
J50
H48
H53
G50
F53
F49
E51
D47
C46
A46
E46
C44
A44
E44
F44
J43
H47
L47
L45
M46
L46
H43
G43
G45
P43
K51
K53
E48
C49
N50
R47
H51
D45
M49
R46
H49
F46
G46
M47
M44
K42
J47
M43
J42
P44
P45
U42
T41
DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8
MAA0_9
WCKA0_0
WCKA0B_0
WCKA0_1
WCKA0B_1
EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3
DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3
ADBIA0
CSA0B_0
CSA0B_1
CASA0B
RASA0B
WEA0B
CKEA0
CLKA0
CLKA0B
NC_MEM_CALRP0
NC_MEM_CALRN0
U1C
PART 3 OF 18
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
B
A
N
K
A
5
DQA1_<0>
3
D43
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31
MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7
MAA1_8
MAA1_9
WCKA1_0
WCKA1B_0
WCKA1_1
WCKA1B_1
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3
DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3
CSA1B_0
CSA1B_1
CASA1B
RASA1B
CLKA1B
MVREFDA
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
ADBIA1
WEA1B
CKEA1
CLKA1
DQA1_<1>
E42
DQA1_<2>
A42
DQA1_<3>
C42
DQA1_<4>
C40
DQA1_<5>
A40
DQA1_<6>
E40
DQA1_<7>
F40
DQA1_<8>
A38
DQA1_<9>
E38
DQA1_<10>
F38
DQA1_<11>
D37
DQA1_<12>
E36
DQA1_<13>
D35
DQA1_<14>
C34
DQA1_<15>
A34
DQA1_<16>
M41
DQA1_<17>
L39
DQA1_<18>
M40
DQA1_<19>
M38
DQA1_<20>
M36
DQA1_<21>
K35
DQA1_<22>
L35
DQA1_<23>
M35
DQA1_<24>
G32
DQA1_<25>
J32
DQA1_<26>
H31
DQA1_<27>
G31
DQA1_<28>
K28
DQA1_<29>
H28
DQA1_<30>
G28
DQA1_<31>
J26
MAA1_<0>
H39
MAA1_<1>
G39
MAA1_<2>
J38
MAA1_<3>
G38
MAA1_<4>
G36
MAA1_<5>
H36
MAA1_<6>
G40
MAA1_<7>
J40
MAA1_<8>
H40
L32
WCKA1_0
C38
WCKA1B_0
D39
WCKA1_1
K33
WCKA1B_1
L33
EDCA1_0
F42
EDCA1_1
A36
EDCA1_2
L36
EDCA1_3
J29
DDBIA1_0
D41
DDBIA1_1
C36
DDBIA1_2
M37
DDBIA1_3
H29
ADBIA1
K39
CSA1B_0
J36
J35
CASA1B
L40
RASA1B
K38
WEA1B
G35
CKEA1
G42
CLKA1
H33
CLKA1B
G33
MVREF_A MVREF_B
M42
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
+MVDD +MVDD
R3602
40.2R
1%
C3602
R3606
1uF
100R
6.3V
1%
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
R3601 120R 1%
DQB0_<0>
DQB0_<1>
DQB0_<2>
DQB0_<3>
DQB0_<4>
DQB0_<5>
DQB0_<6>
DQB0_<7>
DQB0_<8>
DQB0_<9>
DQB0_<10>
DQB0_<11>
DQB0_<12>
DQB0_<13>
DQB0_<14>
DQB0_<15>
DQB0_<16>
DQB0_<17>
DQB0_<18>
DQB0_<19>
DQB0_<20>
DQB0_<21>
DQB0_<22>
DQB0_<23>
DQB0_<24>
DQB0_<25>
DQB0_<26>
DQB0_<27>
DQB0_<28>
DQB0_<29>
DQB0_<30>
DQB0_<31>
MAB0_<0>
MAB0_<1>
MAB0_<2>
MAB0_<3>
MAB0_<4>
MAB0_<5>
MAB0_<6>
MAB0_<7>
MAB0_<8>
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
WCKB0_0
WCKB0B_0
WCKB0_1
WCKB0B_1
EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3
DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3
ADBIB0
CSB0B_0
CASB0B
RASB0B
WEB0B
CKEB0
CLKB0
CLKB0B
MEM_CALRP1
E34
F34
D33
E32
F32
D31
C30
A30
D29
C28
A28
E28
C26
A26
E26
F26
G26
H26
K25
G25
G23
H23
G22
H22
A24
E24
F24
D23
E22
F22
D21
C20
M23
L23
L26
M26
L28
M28
M21
L21
K22
K32
E30
F30
D25
C24
A32
D27
J25
A22
C32
F28
J23
C22
L22
K29
M30
G21
M24
M31
J21
L31
K31
T16
U17
DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
MAB0_0
MAB0_1
MAB0_2
MAB0_3
MAB0_4
MAB0_5
MAB0_6
MAB0_7
MAB0_8
MAB0_9
WCKB0_0
WCKB0B_0
WCKB0_1
WCKB0B_1
EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3
DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3
ADBIB0
CSB0B_0
CSB0B_1
CASB0B
RASB0B
WEB0B
CKEB0
CLKB0
CLKB0B
MEM_CALRP1
NC_MEM_CALRN1
U1D
PART 4 OF 18
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
B
A
N
K
B
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31
MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MAB1_7
MAB1_8
MAB1_9
WCKB1_0
WCKB1B_0
WCKB1_1
WCKB1B_1
EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3
DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3
ADBIB1
CSB1B_0
CSB1B_1
CASB1B
RASB1B
WEB1B
CLKB1B
MVREFDB
DQB1_<0>
A20
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3
5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
CKEB1
CLKB1
DQB1_<1>
E20
DQB1_<2>
F20
DQB1_<3>
D19
DQB1_<4>
E18
DQB1_<5>
D17
DQB1_<6>
C16
DQB1_<7>
A16
DQB1_<8>
D15
DQB1_<9>
C14
DQB1_<10>
A14
DQB1_<11>
E14
DQB1_<12>
A12
DQB1_<13>
E12
DQB1_<14>
F12
DQB1_<15>
D11
DQB1_<16>
G15
DQB1_<17>
H15
DQB1_<18>
G14
DQB1_<19>
H14
DQB1_<20>
G11
DQB1_<21>
J11
DQB1_<22>
G9
DQB1_<23>
G8
DQB1_<24>
E10
DQB1_<25>
D9
DQB1_<26>
C8
DQB1_<27>
A8
DQB1_<28>
D7
DQB1_<29>
A6
DQB1_<30>
E6
DQB1_<31>
C5
MAB1_<0>
L18
MAB1_<1>
K18
MAB1_<2>
J16
MAB1_<3>
K16
MAB1_<4>
L15
MAB1_<5>
G16
MAB1_<6>
J19
MAB1_<7>
H19
MAB1_<8>
G18
L12
WCKB1_0
F16
WCKB1B_0
E16
WCKB1_1
A10
WCKB1B_1
C10
EDCB1_0
A18
EDCB1_1
C12
EDCB1_2
H11
EDCB1_3
F8
DDBIB1_0
C18
DDBIB1_1
D13
DDBIB1_2
G12
DDBIB1_3
E8
ADBIB1
H18
CSB1B_0
J15
L14
CASB1B
G19
RASB1B
M18
WEB1B
K14
CKEB1
L19
CLKB1
K12
CLKB1B
J12
M17
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
R3603
40.2R
1%
C3603
R3607
1uF
100R
6.3V
1%
DD
DD
DD
C
C
C
BB
BB
BB
N41
MVREFSA
PITCAIRN
A
A
A
MVREFD/S = 0.7 * VDDR1
DRAM_RST1
5
OUT
R3630 49.9R 1%
R3615 1%10R
C3607
120pF
50V
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
DRAM_RST1_RDRAM_RST1_RR
V43
DRAM_RST1
R3612
5.1K
1%
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD MEM CH AB
TRINIDAD MEM CH AB
TRINIDAD MEM CH AB
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:19 2015 1.0
Thu Jan 15 02:26:19 2015 1.0
Thu Jan 15 02:26:19 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
PITCAIRN
323
323
323
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
MVREFSB
M19
REV:
REV:
REV:
MVREFD/S = 0.7 * VDDR1
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
A
A
A
1
1
1
8
Page 4
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
(4) TRINIDAD MEM INTERFACE CH C/D
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
DQC0_<0>
6,4
A A
C
C
C
B B
C C
BI
DQC0_<1>
6,4
BI
DQC0_<2>
6,4
BI
DQC0_<3>
6,4
BI
DQC0_<4>
6,4
BI
DQC0_<5>
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
R3614 1%120R
DQC0_<6>
DQC0_<7>
DQC0_<8>
DQC0_<9>
DQC0_<10>
DQC0_<11>
DQC0_<12>
DQC0_<13>
DQC0_<14>
DQC0_<15>
DQC0_<16>
DQC0_<17>
DQC0_<18>
DQC0_<19>
DQC0_<20>
DQC0_<21>
DQC0_<22>
DQC0_<23>
DQC0_<24>
DQC0_<25>
DQC0_<26>
DQC0_<27>
DQC0_<28>
DQC0_<29>
DQC0_<30>
DQC0_<31>
MAC0_<0>
MAC0_<1>
MAC0_<2>
MAC0_<3>
MAC0_<4>
MAC0_<5>
MAC0_<6>
MAC0_<7>
MAC0_<8>
WCKC0_0
WCKC0B_0
WCKC0_1
WCKC0B_1
EDCC0_0
EDCC0_1
EDCC0_2
EDCC0_3
DDBIC0_0
DDBIC0_1
DDBIC0_2
DDBIC0_3
ADBIC0
CSC0B_0
CASC0B
RASC0B
WEC0B
CKEC0
CLKC0
CLKC0B
MEM_CALRP2
BB17
BA16
E3
F5
F1
G4
H1
H3
J4
K5
H7
J7
L9
L7
P8
P7
R8
R7
L4
M6
M5
M1
P5
P1
P3
R4
T1
T3
U4
V5
W4
Y6
Y5
Y1
V11
V10
T9
T10
R11
T7
W9
W8
V7
M11
K1
K3
T6
T5
H6
L8
M3
V1
H5
M7
N4
V3
V8
R9
P11
W7
V12
P10
W11
M10
M9
DQC0_0
DQC0_1
DQC0_2
DQC0_3
DQC0_4
DQC0_5
DQC0_6
DQC0_7
DQC0_8
DQC0_9
DQC0_10
DQC0_11
DQC0_12
DQC0_13
DQC0_14
DQC0_15
DQC0_16
DQC0_17
DQC0_18
DQC0_19
DQC0_20
DQC0_21
DQC0_22
DQC0_23
DQC0_24
DQC0_25
DQC0_26
DQC0_27
DQC0_28
DQC0_29
DQC0_30
DQC0_31
MAC0_0
MAC0_1
MAC0_2
MAC0_3
MAC0_4
MAC0_5
MAC0_6
MAC0_7
MAC0_8
MAC0_9
WCKC0_0
WCKC0B_0
WCKC0_1
WCKC0B_1
EDCC0_0
EDCC0_1
EDCC0_2
EDCC0_3
DDBIC0_0
DDBIC0_1
DDBIC0_2
DDBIC0_3
ADBIC0
CSC0B_0
CSC0B_1
CASC0B
RASC0B
WEC0B
CKEC0
CLKC0
CLKC0B
MEM_CALRP2
NC_MEM_CALRN2
U1E
PART 5 OF 18
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
B
A
N
K
C
6
DQC1_<0>
4
Y3
DQC1_0
DQC1_1
DQC1_2
DQC1_3
DQC1_4
DQC1_5
DQC1_6
DQC1_7
DQC1_8
DQC1_9
DQC1_10
DQC1_11
DQC1_12
DQC1_13
DQC1_14
DQC1_15
DQC1_16
DQC1_17
DQC1_18
DQC1_19
DQC1_20
DQC1_21
DQC1_22
DQC1_23
DQC1_24
DQC1_25
DQC1_26
DQC1_27
DQC1_28
DQC1_29
DQC1_30
DQC1_31
MAC1_0
MAC1_1
MAC1_2
MAC1_3
MAC1_4
MAC1_5
MAC1_6
MAC1_7
MAC1_8
MAC1_9
WCKC1_0
WCKC1B_0
WCKC1_1
WCKC1B_1
EDCC1_0
EDCC1_1
EDCC1_2
EDCC1_3
DDBIC1_0
DDBIC1_1
DDBIC1_2
DDBIC1_3
ADBIC1
CSC1B_0
CSC1B_1
CASC1B
RASC1B
WEC1B
CLKC1B
MVREFDC
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
CKEC1
CLKC1
DQC1_<1>
AA4
DQC1_<2>
AB6
DQC1_<3>
AB5
DQC1_<4>
AC4
DQC1_<5>
AD6
DQC1_<6>
AD5
DQC1_<7>
AD1
DQC1_<8>
AB8
DQC1_<9>
AB7
DQC1_<10>
AC8
DQC1_<11>
AC7
DQC1_<12>
AE7
DQC1_<13>
AE10
DQC1_<14>
AF8
DQC1_<15>
AF7
DQC1_<16>
AF6
DQC1_<17>
AF5
DQC1_<18>
AF1
DQC1_<19>
AF3
DQC1_<20>
AH5
DQC1_<21>
AH1
DQC1_<22>
AH3
DQC1_<23>
AJ4
DQC1_<24>
AK1
DQC1_<25>
AK3
DQC1_<26>
AL4
DQC1_<27>
AM6
DQC1_<28>
AM5
DQC1_<29>
AN4
DQC1_<30>
AP6
DQC1_<31>
AP5
MAC1_<0>
AC12
MAC1_<1>
AC11
MAC1_<2>
AF11
MAC1_<3>
AF12
MAC1_<4>
AH11
MAC1_<5>
AH12
MAC1_<6>
AA12
MAC1_<7>
AA11
MAC1_<8>
AB10
AM10
WCKC1_0
AE4
WCKC1B_0
AD3
WCKC1_1
AK5
WCKC1B_1
AK6
EDCC1_0
AB1
EDCC1_1
AE9
EDCC1_2
AG4
EDCC1_3
AM1
DDBIC1_0
AB3
DDBIC1_1
AC9
DDBIC1_2
AH6
DDBIC1_3
AM3
ADBIC1
AB11
CSC1B_0
AJ10
AK12
CASC1B
AA7
RASC1B
AD12
WEC1B
AL12
CKEC1
AA9
CLKC1
AL11
CLKC1B
AL10
MVREF_C MVREF_D
U12
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
+MVDD +MVDD
R3618
40.2R
1%
C3612
R3621
1uF
100R
6.3V
1%
DQD0_<0>
6,4
BI
DQD0_<1>
6,4
BI
DQD0_<2>
6,4
BI
DQD0_<3>
6,4
BI
DQD0_<4>
6,4
BI
DQD0_<5>
6,4
BI
DQD0_<6>
6,4
BI
DQD0_<7>
6,4
BI
DQD0_<8>
6,4
BI
DQD0_<9>
6,4
BI
DQD0_<10>
6,4
BI
DQD0_<11>
6,4
BI
DQD0_<12>
6,4
BI
DQD0_<13>
6,4
BI
DQD0_<14>
6,4
BI
DQD0_<15>
6,4
BI
DQD0_<16>
6,4
BI
DQD0_<17>
6,4
BI
DQD0_<18>
6,4
BI
DQD0_<19>
6,4
BI
DQD0_<20>
6,4
BI
DQD0_<21>
6,4
BI
DQD0_<22>
6,4
BI
DQD0_<23>
6,4
BI
DQD0_<24>
6,4
BI
DQD0_<25>
6,4
BI
DQD0_<26>
6,4
BI
DQD0_<27>
6,4
BI
DQD0_<28>
6,4
BI
DQD0_<29>
6,4
BI
DQD0_<30>
6,4
BI
DQD0_<31>
6,4
BI
MAD0_<0>
6,4
BI
MAD0_<1>
6,4
BI
MAD0_<2>
6,4
BI
MAD0_<3>
6,4
BI
MAD0_<4>
6,4
BI
MAD0_<5>
6,4
BI
MAD0_<6>
6,4
BI
MAD0_<7>
6,4
BI
MAD0_<8>
6,4
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
WCKD0_0
WCKD0B_0
WCKD0_1
WCKD0B_1
EDCD0_0
EDCD0_1
EDCD0_2
EDCD0_3
DDBID0_0
DDBID0_1
DDBID0_2
DDBID0_3
ADBID0
CSD0B_0
CASD0B
RASD0B
WED0B
CKED0
CLKD0
CLKD0B
AF9
AH7
AH8
AH10
AL7
AL8
AM9
AM7
AR12
AR11
AR10
AT12
AV12
AY12
AW11
BA12
AP1
AP3
AR4
AT5
AU4
AV6
AV5
AV1
AY6
AY5
AY1
AY3
BB3
BB1
BB5
BC4
AW8
AW7
AV9
AV7
AT7
AT8
AY7
AY9
AY8
AM11
AN10
AN11
AV3
AW4
AJ9
AT11
AT1
BB6
AJ8
AU12
AT3
BA4
AW10
AT9
AR9
AY11
AV10
AR7
BB7
AN8
AN7
DQD0_0
DQD0_1
DQD0_2
DQD0_3
DQD0_4
DQD0_5
DQD0_6
DQD0_7
DQD0_8
DQD0_9
DQD0_10
DQD0_11
DQD0_12
DQD0_13
DQD0_14
DQD0_15
DQD0_16
DQD0_17
DQD0_18
DQD0_19
DQD0_20
DQD0_21
DQD0_22
DQD0_23
DQD0_24
DQD0_25
DQD0_26
DQD0_27
DQD0_28
DQD0_29
DQD0_30
DQD0_31
MAD0_0
MAD0_1
MAD0_2
MAD0_3
MAD0_4
MAD0_5
MAD0_6
MAD0_7
MAD0_8
MAD0_9
WCKD0_0
WCKD0B_0
WCKD0_1
WCKD0B_1
EDCD0_0
EDCD0_1
EDCD0_2
EDCD0_3
DDBID0_0
DDBID0_1
DDBID0_2
DDBID0_3
ADBID0
CSD0B_0
CSD0B_1
CASD0B
RASD0B
WED0B
CKED0
CLKD0
CLKD0B
PART 6 OF 18
U1F
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
B
A
N
K
D
DQD1_0
DQD1_1
DQD1_2
DQD1_3
DQD1_4
DQD1_5
DQD1_6
DQD1_7
DQD1_8
DQD1_9
DQD1_10
DQD1_11
DQD1_12
DQD1_13
DQD1_14
DQD1_15
DQD1_16
DQD1_17
DQD1_18
DQD1_19
DQD1_20
DQD1_21
DQD1_22
DQD1_23
DQD1_24
DQD1_25
DQD1_26
DQD1_27
DQD1_28
DQD1_29
DQD1_30
DQD1_31
MAD1_0
MAD1_1
MAD1_2
MAD1_3
MAD1_4
MAD1_5
MAD1_6
MAD1_7
MAD1_8
MAD1_9
WCKD1_0
WCKD1B_0
WCKD1_1
WCKD1B_1
EDCD1_0
EDCD1_1
EDCD1_2
EDCD1_3
DDBID1_0
DDBID1_1
DDBID1_2
DDBID1_3
ADBID1
CSD1B_0
CSD1B_1
CASD1B
RASD1B
WED1B
CLKD1B
MVREFDD
6
DQD1_<0>
4
BD6
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
CKED1
CLKD1
DQD1_<1>
BD5
DQD1_<2>
BD1
DQD1_<3>
BD3
DQD1_<4>
BF5
DQD1_<5>
BF1
DQD1_<6>
BF3
DQD1_<7>
BG4
DQD1_<8>
BL5
DQD1_<9>
BJ6
DQD1_<10>
BN6
DQD1_<11>
BK7
DQD1_<12>
BN8
DQD1_<13>
BH8
DQD1_<14>
BK9
DQD1_<15>
BH10
DQD1_<16>
BB13
DQD1_<17>
BB14
DQD1_<18>
BG14
DQD1_<19>
BE15
DQD1_<20>
BC15
DQD1_<21>
BG16
DQD1_<22>
BE16
DQD1_<23>
BD16
DQD1_<24>
BJ10
DQD1_<25>
BK11
DQD1_<26>
BL12
DQD1_<27>
BN12
DQD1_<28>
BN14
DQD1_<29>
BL14
DQD1_<30>
BJ14
DQD1_<31>
BM15
6
MAD1_<0>
4
BC9
MAD1_<1>
BG8
MAD1_<2>
BG11
MAD1_<3>
BE11
MAD1_<4>
BF12
MAD1_<5>
BF11
MAD1_<6>
BC8
MAD1_<7>
BC7
MAD1_<8>
BE7
BC14
WCKD1_0
BH5
WCKD1B_0
BJ3
WCKD1_1
BL10
WCKD1B_1
BN10
EDCD1_0
BE4
EDCD1_1
BL8
EDCD1_2
BG15
EDCD1_3
BK13
DDBID1_0
BF6
DDBID1_1
BJ8
DDBID1_2
BF15
DDBID1_3
BJ12
ADBID1
BF7
CSD1B_0
BG12
BD12
CASD1B
BB10
RASD1B
BG9
WED1B
BC12
CKED1
BB9
CLKD1
BD14
CLKD1B
BE14
BB12
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
R3619
40.2R
1%
C3611
R3620
1uF
100R
6.3V
1%
DD
DD
DD
C
C
C
BB
BB
BB
W12
MVREFSC
PITCAIRN
A
A
A
MVREFD/S = 0.7 * VDDR1 MVREFD/S = 0.7 * VDDR1
DRAM_RST2
6
OUT
R3629 49.9R 1%
R3616 1%10R
C3617
120pF
50V
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
DRAM_RST2_RDRAM_RST2_RR
BC18
DRAM_RST2
R3627
5.1K
1%
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD MEM CH CD
TRINIDAD MEM CH CD
TRINIDAD MEM CH CD
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:20 2015 1.0
Thu Jan 15 02:26:20 2015 1.0
Thu Jan 15 02:26:20 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
PITCAIRN
423
423
423
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
MVREFSD
BA13
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
REV:
REV:
REV:
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
Page 5
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(5) GDDR5 MEMORY CH A/B
5
14
DQA0_<14>
3
3,5
BI
15
DQA0_<15>
3,5
BI
13
DQA0_<13>
3,5
BI
12
DQA0_<12>
3,5
BI
10
DQA0_<10>
3,5
BI
9
DQA0_<9>
3,5
BI
11
DQA0_<11>
3,5
BI
8
DQA0_<8>
3,5
BI
7
DQA0_<7>
3,5
A A
C
C
C
B B
+MVDD
R2001 1%60.4R
R2000 1%60.4R
C C
+MVDD
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
R2002 120R 1%
R2003 5%1K
3,5
R2004 5%1K
R2009 1%2.37K
R2010 1%5.49K
C2005 6.3V1uF
3
BI
6
DQA0_<6>
BI
4
DQA0_<4>
BI
5
DQA0_<5>
BI
0
DQA0_<0>
BI
2
DQA0_<2>
BI
1
DQA0_<1>
BI
3
DQA0_<3>
BI
21
DQA0_<21>
BI
22
DQA0_<22>
BI
20
DQA0_<20>
BI
23
DQA0_<23>
BI
19
DQA0_<19>
BI
18
DQA0_<18>
BI
16
DQA0_<16>
BI
17
DQA0_<17>
BI
26
DQA0_<26>
BI
25
DQA0_<25>
BI
24
DQA0_<24>
BI
27
DQA0_<27>
BI
28
DQA0_<28>
BI
30
DQA0_<30>
BI
29
DQA0_<29>
BI
31
DQA0_<31>
BI
5
8
MAA0_<8>
3
BI
7
MAA0_<7>
BI
6
MAA0_<6>
BI
5
MAA0_<5>
BI
4
MAA0_<4>
BI
3
MAA0_<3>
BI
2
MAA0_<2>
BI
1
MAA0_<1>
BI
0
MAA0_<0>
BI
WCKA0_1
IN
WCKA0B_1
IN
WCKA0_0
IN
WCKA0B_0
IN
EDCA0_1
OUT
EDCA0_0
OUT
EDCA0_2
OUT
EDCA0_3
OUT
DDBIA0_1
BI
DDBIA0_0
BI
DDBIA0_2
BI
DDBIA0_3
BI
RASA0B
IN
CASA0B
IN
CKEA0
IN
CLKA0B
IN
CLKA0
IN
CSA0B_0
IN
WEA0B
IN
ZQ_A0 ZQ_A1 ZQ_B0 ZQ_B1
SEN_A0 SEN_A1 SEN_B0 SEN_B1
DRAM_RST1
IN
MF_A0 MF_A1 MF_B0 MF_B1
VREFC_A0 VREFC_A1 VREFC_B0 VREFC_B1
ADBIA0
IN
23CNOPN001
U2000
M2
DQ31__DQ7
M4
DQ30__DQ6
N2
DQ29__DQ5
N4
DQ28__DQ4
T2
DQ27__DQ3
T4
DQ26__DQ2
V2
DQ25__DQ1
V4
DQ24__DQ0
M13
DQ23__DQ15
M11
DQ22__DQ14
N13
DQ21__DQ13
N11
DQ20__DQ12
T13
DQ19__DQ11
T11
DQ18__DQ10
V13
DQ17__DQ9
V11
DQ16__DQ8
F13
DQ15__DQ23
F11
DQ14__DQ22
E13
DQ13__DQ21
E11
DQ12__DQ20
B13
DQ11__DQ19
B11
DQ10__DQ18
A13
DQ9__DQ17
A11
DQ8__DQ16
F2
DQ7__DQ31
F4
DQ6__DQ30
E2
DQ5__DQ29
E4
DQ4__DQ28
B2
DQ3__DQ27
B4
DQ2__DQ26
A2
DQ1__DQ25
A4
DQ0__DQ24
J5
RFU_A12_NC
K4
A7_A8__A0_A10
K5
A6_A11__A1_A9
K10
A5_BA1__A3_BA3
K11
A4_BA2__A2_BA0
H10
A3_BA3__A5_BA1
H11
A2_BA0__A4_BA2
H5
A1_A9__A6_A11
H4
A0_A10__A7_A8
D4
WCK01__WCK23
D5
WCK01#__WCK23#
P4
WCK23__WCK01
P5
WCK23#__WCK01#
R2
EDC3__EDC0
R13
EDC2__EDC1
C13
EDC1__EDC2
C2
EDC0__EDC3
P2
DBI3#__DBI0#
P13
DBI2#__DBI1#
D13
DBI1#__DBI2#
D2
DBI0#__DBI3#
G3
RAS#__CAS#
L3
CAS#__RAS#
J3
CKE#
J11
CK#
J12
CK
G12
CS#__WE#
L12
WE#__CS#
J13
ZQ
J10
SEN
J2
RESET#
J1
MF
A5
Vpp_NC
V5
Vpp_NC1
A10
VREFD1
V10
VREFD2
J14
VREFC
J4
ABI#
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
+MVDD
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
+MVDD
R2101 60.4R 1%
R2100 1%60.4R
R2102 1%120R
R2103 5%1K
R2104 5%1K
+MVDD
R2109 1%2.37K
R2110 1%5.49K
C2105 1uF 6.3V
5
5
DQA1_<5>
3
3,5
BI
6
DQA1_<6>
3,5
BI
4
DQA1_<4>
3,5
BI
7
DQA1_<7>
3,5
BI
3
DQA1_<3>
3,5
BI
2
DQA1_<2>
3,5
BI
1
DQA1_<1>
3,5
BI
0
DQA1_<0>
3,5
BI
11
DQA1_<11>
3,5
BI
10
DQA1_<10>
3,5
BI
8
DQA1_<8>
3,5
BI
9
DQA1_<9>
3,5
BI
12
DQA1_<12>
3,5
BI
14
DQA1_<14>
3,5
BI
13
DQA1_<13>
3,5
BI
15
DQA1_<15>
3,5
BI
24
DQA1_<24>
3,5
BI
25
DQA1_<25>
3,5
BI
27
DQA1_<27>
3,5
BI
26
DQA1_<26>
3,5
BI
31
DQA1_<31>
3,5
BI
29
DQA1_<29>
3,5
BI
30
DQA1_<30>
3,5
BI
28
DQA1_<28>
3,5
BI
17
DQA1_<17>
3,5
BI
16
DQA1_<16>
3,5
BI
19
DQA1_<19>
3,5
BI
18
DQA1_<18>
3,5
BI
20
DQA1_<20>
3,5
BI
22
DQA1_<22>
3,5
BI
21
DQA1_<21>
3,5
BI
23
DQA1_<23>
3,5
BI
5
8
MAA1_<8>
3
3,5
BI
0
MAA1_<0>
3,5
BI
1
MAA1_<1>
3,5
BI
3
MAA1_<3>
3,5
BI
2
MAA1_<2>
3,5
BI
5
MAA1_<5>
3,5
BI
4
MAA1_<4>
3,5
BI
6
MAA1_<6>
3,5
BI
7
MAA1_<7>
3,5
BI
WCKA1_1
3
IN
WCKA1B_1
3
IN
WCKA1_0
3
IN
WCKA1B_0
3
IN
EDCA1_0
3
OUT
EDCA1_1
3
OUT
EDCA1_3
3
OUT
EDCA1_2
3
OUT
DDBIA1_0
3
BI
DDBIA1_1
3
BI
DDBIA1_3
3
BI
DDBIA1_2
3
BI
CASA1B
3
IN
RASA1B
3
IN
CKEA1
3
IN
CLKA1B
3
IN
CLKA1
3
IN
WEA1B
3
IN
CSA1B_0
3
IN
DRAM_RST1
3,5
IN
ADBIA1
3
IN
M2
M4
N2
N4
T2
T4
V2
V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5
K10
K11
H10
H11
H5
H4
D4
D5
P4
P5
R2
R13
C13
C2
P2
P13
D13
D2
G3
L3
J3
J11
J12
G12
L12
J13
J10
J2
J1
A5
V5
A10
V10
J14
J4
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
23CNOPN001
U2100
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
+MVDD
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
+MVDD
R2201 60.4R 1%
R2200 1%60.4R
R2202 1%120R
R2203 5%1K
R2204 5%1K
R2209 1%2.37K
R2210 1%5.49K
C2205 1uF 6.3V
5
30
DQB0_<30>
3
3,5
BI
25
DQB0_<25>
3,5
BI
29
DQB0_<29>
3,5
BI
24
DQB0_<24>
3,5
BI
28
DQB0_<28>
3,5
BI
26
DQB0_<26>
3,5
BI
31
DQB0_<31>
3,5
BI
27
DQB0_<27>
3,5
BI
17
DQB0_<17>
3,5
BI
16
DQB0_<16>
3,5
BI
18
DQB0_<18>
3,5
BI
19
DQB0_<19>
3,5
BI
21
DQB0_<21>
3,5
BI
23
DQB0_<23>
3,5
BI
20
DQB0_<20>
3,5
BI
22
DQB0_<22>
3,5
BI
5
DQB0_<5>
3,5
BI
6
DQB0_<6>
3,5
BI
4
DQB0_<4>
3,5
BI
7
DQB0_<7>
3,5
BI
3
DQB0_<3>
3,5
BI
2
DQB0_<2>
3,5
BI
1
DQB0_<1>
3,5
BI
0
DQB0_<0>
3,5
BI
11
DQB0_<11>
3,5
BI
10
DQB0_<10>
3,5
BI
8
DQB0_<8>
3,5
BI
9
DQB0_<9>
3,5
BI
12
DQB0_<12>
3,5
BI
13
DQB0_<13>
3,5
BI
14
DQB0_<14>
3,5
BI
15
DQB0_<15>
3,5
BI
5
8
MAB0_<8>
3
3,5
BI
7
MAB0_<7>
3,5
BI
6
MAB0_<6>
3,5
BI
5
MAB0_<5>
3,5
BI
4
MAB0_<4>
3,5
BI
3
MAB0_<3>
3,5
BI
2
MAB0_<2>
3,5
BI
1
MAB0_<1>
3,5
BI
0
MAB0_<0>
3,5
BI
WCKB0_0
3
IN
WCKB0B_0
3
IN
WCKB0_1
3
IN
WCKB0B_1
3
IN
EDCB0_3
3
OUT
EDCB0_2
3
OUT
EDCB0_0
3
OUT
EDCB0_1
3
OUT
DDBIB0_3
3
BI
DDBIB0_2
3
BI
DDBIB0_0
3
BI
DDBIB0_1
3
BI
RASB0B
3
IN
CASB0B
3
IN
CKEB0
3
IN
CLKB0B
3
IN
CLKB0
3
IN
CSB0B_0
3
IN
WEB0B
3
IN
DRAM_RST1
3,5
IN
ADBIB0
3
IN
M2
M4
N2
N4
T2
T4
V2
V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5
K10
K11
H10
H11
H5
H4
D4
D5
P4
P5
R2
R13
C13
C2
P2
P13
D13
D2
G3
L3
J3
J11
J12
G12
L12
J13
J10
J2
J1
A5
V5
A10
V10
J14
J4
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
23CNOPN001
U2200
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
+MVDD
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
+MVDD
R2301 1%60.4R
R2300 1%60.4R
+MVDD
R2302 120R 1%
R2303 1K 5%
R2304 5%1K
R2309 1%2.37K
R2310 1%5.49K
C2305 6.3V1uF
5
5
DQB1_<5>
3
3,5
BI
6
DQB1_<6>
3,5
BI
4
DQB1_<4>
3,5
BI
7
DQB1_<7>
3,5
BI
3
DQB1_<3>
3,5
BI
2
DQB1_<2>
3,5
BI
1
DQB1_<1>
3,5
BI
0
DQB1_<0>
3,5
BI
11
DQB1_<11>
3,5
BI
10
DQB1_<10>
3,5
BI
8
DQB1_<8>
3,5
BI
9
DQB1_<9>
3,5
BI
12
DQB1_<12>
3,5
BI
13
DQB1_<13>
3,5
BI
14
DQB1_<14>
3,5
BI
15
DQB1_<15>
3,5
BI
25
DQB1_<25>
3,5
BI
24
DQB1_<24>
3,5
BI
27
DQB1_<27>
3,5
BI
26
DQB1_<26>
3,5
BI
29
DQB1_<29>
3,5
BI
30
DQB1_<30>
3,5
BI
28
DQB1_<28>
3,5
BI
31
DQB1_<31>
3,5
BI
17
DQB1_<17>
3,5
BI
16
DQB1_<16>
3,5
BI
18
DQB1_<18>
3,5
BI
19
DQB1_<19>
3,5
BI
20
DQB1_<20>
3,5
BI
22
DQB1_<22>
3,5
BI
21
DQB1_<21>
3,5
BI
23
DQB1_<23>
3,5
BI
5
8
MAB1_<8>
3
3,5
BI
0
MAB1_<0>
3,5
BI
1
MAB1_<1>
3,5
BI
3
MAB1_<3>
3,5
BI
2
MAB1_<2>
3,5
BI
5
MAB1_<5>
3,5
BI
4
MAB1_<4>
3,5
BI
6
MAB1_<6>
3,5
BI
7
MAB1_<7>
3,5
BI
WCKB1_1
3
IN
WCKB1B_1
3
IN
WCKB1_0
3
IN
WCKB1B_0
3
IN
EDCB1_0
3
OUT
EDCB1_1
3
OUT
EDCB1_3
3
OUT
EDCB1_2
3
OUT
DDBIB1_0
3
BI
DDBIB1_1
3
BI
DDBIB1_3
3
BI
DDBIB1_2
3
BI
CASB1B
3
IN
RASB1B
3
IN
CKEB1
3
IN
CLKB1B
3
IN
CLKB1
3
IN
WEB1B
3
IN
CSB1B_0
3
IN
DRAM_RST1
3,5
IN
ADBIB1
3
IN
M2
M4
N2
N4
T2
T4
V2
V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5
K10
K11
H10
H11
H5
H4
D4
D5
P4
P5
R2
R13
C13
C2
P2
P13
D13
D2
G3
L3
J3
J11
J12
G12
L12
J13
J10
J2
J1
A5
V5
A10
V10
J14
J4
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
GDDR5
23CNOPN001
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
DD
DD
DD
C
C
C
BB
BB
BB
U2300
+MVDD
C20080.1uF
C20090.1uF
C20100.1uF
C20120.1uF
C20130.1uF
C20140.1uF
A
A
A
C20070.1uF
C20150.1uF
D D
+MVDD
C20231uF
C20241uF
C20251uF
C20261uF
C20281uF
C20191uF
C20201uF
8
8
8
1
C20291uF
+MVDD
C21170.1uF
C21100.1uF
C21120.1uF
C21150.1uF
C21070.1uF
C21080.1uF
+MVDD
C204010uF
C204110uF
C21181uF
C21191uF
7
7
7
2
C21160.1uF
C21090.1uF
C21211uF
C21221uF
C21261uF
C21271uF
C21201uF
C21291uF
+MVDD
C2218
C22120.1uF
C22130.1uF
C22060.1uF
C22080.1uF
+MVDD
C214010uF
C214110uF
C22191uF
C22201uF
6
6
6
3
C22140.1uF
C22090.1uF
C22110.1uF
0.1uF
C22271uF
C22281uF
C22291uF
C22231uF
C22301uF
C22261uF
+MVDD
C23060.1uF
C23120.1uF
+MVDD
C224010uF
C224110uF
C23191uF
C23211uF C23080.1uF
C23221uF C23090.1uF
C23231uF C23110.1uF
C23241uF
5
5
5
4
+MVDD
MC204010uF
MC214110uF
MC214010uF
MC234010uF
MC224110uF
MC224010uF
MC204110uF
C23170.1uF
C23140.1uF
C23160.1uF
DRAM SCAN PINS
SSH [J2] - SCAN SHIFT
C234010uF
C234110uF
SCK [G12] - SCAN CLOCK
SOUT [C2] - SCAN OUTPUT
SEN [J10] - SCAN ENABLE
SOE# [J1] - SCAN OUTPUT ENABLE
4
4
4
5
C23251uF
C23261uF
C23281uF
MC234110uF
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
GDDR5 MEM CH AB
GDDR5 MEM CH AB
GDDR5 MEM CH AB
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:20 2015 1.0
Thu Jan 15 02:26:20 2015 1.0
Thu Jan 15 02:26:20 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
523
523
523
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
REV:
REV:
REV:
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
Page 6
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(6) GDDR5 MEMORY CH C/D
6
14
DQC0_<14>
4
4,6
BI
15
DQC0_<15>
4,6
BI
13
DQC0_<13>
4,6
BI
12
DQC0_<12>
4,6
BI
11
DQC0_<11>
4,6
BI
9
DQC0_<9>
4,6
BI
10
DQC0_<10>
4,6
BI
8
DQC0_<8>
4,6
BI
6
DQC0_<6>
4,6
R2401 1%60.4R
R2400 1%60.4R
R2403 1K 5%
R2404 5%1K
R2409 1%2.37K
R2410 1%5.49K
C2405 6.3V1uF
C24070.1uF
C24080.1uF
BI
7
DQC0_<7>
4,6
BI
4
DQC0_<4>
4,6
BI
5
DQC0_<5>
4,6
BI
2
DQC0_<2>
4,6
BI
1
DQC0_<1>
4,6
BI
3
DQC0_<3>
4,6
BI
0
DQC0_<0>
4,6
BI
20
DQC0_<20>
4,6
BI
21
DQC0_<21>
4,6
BI
23
DQC0_<23>
4,6
BI
22
DQC0_<22>
4,6
BI
19
DQC0_<19>
4,6
BI
18
DQC0_<18>
4,6
BI
17
DQC0_<17>
4,6
BI
16
DQC0_<16>
4,6
BI
26
DQC0_<26>
4,6
BI
25
DQC0_<25>
4,6
BI
27
DQC0_<27>
4,6
BI
24
DQC0_<24>
4,6
BI
28
DQC0_<28>
4,6
BI
29
DQC0_<29>
4,6
BI
30
DQC0_<30>
4,6
BI
31
DQC0_<31>
4,6
BI
6
8
MAC0_<8>
4
4,6
BI
7
MAC0_<7>
4,6
BI
6
MAC0_<6>
4,6
BI
5
MAC0_<5>
4,6
BI
4
MAC0_<4>
4,6
BI
3
MAC0_<3>
4,6
BI
2
MAC0_<2>
4,6
BI
1
MAC0_<1>
4,6
BI
0
MAC0_<0>
4,6
BI
WCKC0_1
4
IN
WCKC0B_1
4
IN
WCKC0_0
4
IN
WCKC0B_0
4
IN
EDCC0_1
4
OUT
EDCC0_0
4
OUT
EDCC0_2
4
OUT
EDCC0_3
4
OUT
DDBIC0_1
4
BI
DDBIC0_0
4
BI
DDBIC0_2
4
BI
DDBIC0_3
4
BI
RASC0B
4
IN
CASC0B
4
IN
CKEC0
4
IN
CLKC0B
4
IN
CLKC0
4
IN
CSC0B_0
4
IN
WEC0B
4
IN
R2402 1%120R
C24090.1uF
ZQ_C0 ZQ_C1 ZQ_D0 ZQ_D1
SEN_C0 SEN_C1 SEN_D0 SEN_D1
DRAM_RST2
4,6
IN
MF_C0 MF_C1 MF_D0 MF_D1
VREFC_C0 VREFC_C1 VREFC_D0 VREFC_D1
ADBIC0
4
IN
C24140.1uF
C24150.1uF
C24100.1uF
C24110.1uF
C24130.1uF
A A
C
C
C
B B
+MVDD
C C
+MVDD
+MVDD
A
A
A
23CNOPN001
U2400
M2
DQ31__DQ7
M4
DQ30__DQ6
N2
DQ29__DQ5
N4
DQ28__DQ4
T2
DQ27__DQ3
T4
DQ26__DQ2
V2
DQ25__DQ1
V4
DQ24__DQ0
M13
DQ23__DQ15
M11
DQ22__DQ14
N13
DQ21__DQ13
N11
DQ20__DQ12
T13
DQ19__DQ11
T11
DQ18__DQ10
V13
DQ17__DQ9
V11
DQ16__DQ8
F13
DQ15__DQ23
F11
DQ14__DQ22
E13
DQ13__DQ21
E11
DQ12__DQ20
B13
DQ11__DQ19
B11
DQ10__DQ18
A13
DQ9__DQ17
A11
DQ8__DQ16
F2
DQ7__DQ31
F4
DQ6__DQ30
E2
DQ5__DQ29
E4
DQ4__DQ28
B2
DQ3__DQ27
B4
DQ2__DQ26
A2
DQ1__DQ25
A4
DQ0__DQ24
J5
RFU_A12_NC
K4
A7_A8__A0_A10
K5
A6_A11__A1_A9
K10
A5_BA1__A3_BA3
K11
A4_BA2__A2_BA0
H10
A3_BA3__A5_BA1
H11
A2_BA0__A4_BA2
H5
A1_A9__A6_A11
H4
A0_A10__A7_A8
D4
WCK01__WCK23
D5
WCK01#__WCK23#
P4
WCK23__WCK01
P5
WCK23#__WCK01#
R2
EDC3__EDC0
R13
EDC2__EDC1
C13
EDC1__EDC2
C2
EDC0__EDC3
P2
DBI3#__DBI0#
P13
DBI2#__DBI1#
D13
DBI1#__DBI2#
D2
DBI0#__DBI3#
G3
RAS#__CAS#
L3
CAS#__RAS#
J3
CKE#
J11
CK#
J12
CK
G12
CS#__WE#
L12
WE#__CS#
J13
ZQ
J10
SEN
J2
RESET#
J1
MF
A5
Vpp_NC
V5
Vpp_NC1
A10
VREFD1
V10
VREFD2
J14
VREFC
J4
ABI#
+MVDD
C25060.1uF
C25070.1uF
D D
+MVDD
C24231uF
C24171uF
C24181uF
C24191uF
8
8
8
1
C24251uF
C24201uF
C24211uF
C24221uF
+MVDD
C244010uF
C244110uF
C25211uF
C25221uF
7
7
7
2
+MVDD
B1
VDDQ_B1
B3
VDDQ_B3
B12
VDDQ_B12
B14
VDDQ_B14
D1
VDDQ_D1
D3
VDDQ_D3
D12
VDDQ_D12
D14
VDDQ_D14
E5
VDDQ_E5
E10
VDDQ_E10
F1
VDDQ_F1
F3
VDDQ_F3
F12
VDDQ_F12
F14
VDDQ_F14
G2
VDDQ_G2
G13
VDDQ_G13
H3
VDDQ_H3
H12
VDDQ_H12
K3
VDDQ_K3
K12
VDDQ_K12
L2
VDDQ_L2
L13
VDDQ_L13
M1
VDDQ_M1
M3
VDDQ_M3
M12
VDDQ_M12
M14
VDDQ_M14
N5
VDDQ_N5
N10
VDDQ_N10
P1
VDDQ_P1
P3
VDDQ_P3
P12
VDDQ_P12
P14
VDDQ_P14
T1
VDDQ_T1
T3
VDDQ_T3
T12
VDDQ_T12
T14
VDDQ_T14
+MVDD
C5
VDD_C5
C10
VDD_C10
D11
VDD_D11
G1
VDD_G1
G4
VDD_G4
G11
VDD_G11
G14
VDD_G14
L1
VDD_L1
L4
VDD_L4
L11
VDD_L11
L14
VDD_L14
P11
VDD_P11
R5
VDD_R5
R10
VDD_R10
A1
VSSQ_A1
A3
VSSQ_A3
A12
VSSQ_A12
A14
VSSQ_A14
C1
VSSQ_C1
C3
VSSQ_C3
C4
VSSQ_C4
C11
VSSQ_C11
C12
VSSQ_C12
C14
VSSQ_C14
E1
VSSQ_E1
E3
VSSQ_E3
E12
VSSQ_E12
E14
VSSQ_E14
F5
VSSQ_F5
F10
VSSQ_F10
H2
VSSQ_H2
H13
VSSQ_H13
K2
VSSQ_K2
K13
VSSQ_K13
M5
VSSQ_M5
M10
VSSQ_M10
N1
VSSQ_N1
N3
VSSQ_N3
N12
VSSQ_N12
N14
VSSQ_N14
R1
VSSQ_R1
R3
VSSQ_R3
R4
VSSQ_R4
R11
VSSQ_R11
R12
VSSQ_R12
R14
VSSQ_R14
V1
VSSQ_V1
V3
VSSQ_V3
V12
VSSQ_V12
V14
VSSQ_V14
B5
VSS_B5
B10
VSS_B10
D10
VSS_D10
G5
VSS_G5
G10
VSS_G10
H1
VSS_H1
H14
VSS_H14
K1
VSS_K1
K14
VSS_K14
L5
VSS_L5
L10
VSS_L10
P10
VSS_P10
T5
VSS_T5
T10
VSS_T10
C25090.1uF
C25120.1uF
C25130.1uF
C25231uF C25080.1uF
C25241uF
C25251uF
C2526
1uF
+MVDD
R2501 1%60.4R
R2500 1%60.4R
R2503 5%1K
R2504 5%1K
+MVDD
R2509 1%2.37K
+MVDD
R2510 1%5.49K
C2505 6.3V1uF
+MVDD
C25190.1uF
C25150.1uF
C25271uF
C25281uF
C254010uF
C26070.1uF
+MVDD
C254110uF
C26171uF
6
6
6
3
6
20
DQC1_<20>
4
4,6
BI
21
DQC1_<21>
4,6
BI
23
DQC1_<23>
4,6
BI
22
DQC1_<22>
4,6
BI
19
DQC1_<19>
4,6
BI
18
DQC1_<18>
4,6
BI
17
DQC1_<17>
4,6
BI
16
DQC1_<16>
4,6
BI
26
DQC1_<26>
4,6
BI
25
DQC1_<25>
4,6
BI
27
DQC1_<27>
4,6
BI
24
DQC1_<24>
4,6
BI
28
DQC1_<28>
4,6
BI
29
DQC1_<29>
4,6
BI
30
DQC1_<30>
4,6
BI
31
DQC1_<31>
4,6
BI
14
DQC1_<14>
4,6
BI
15
DQC1_<15>
4,6
BI
13
DQC1_<13>
4,6
BI
12
DQC1_<12>
4,6
BI
10
DQC1_<10>
4,6
BI
8
DQC1_<8>
4,6
BI
11
DQC1_<11>
4,6
BI
9
DQC1_<9>
4,6
BI
1
DQC1_<1>
4,6
BI
6
DQC1_<6>
4,6
BI
2
DQC1_<2>
4,6
BI
7
DQC1_<7>
4,6
BI
3
DQC1_<3>
4,6
BI
5
DQC1_<5>
4,6
BI
0
DQC1_<0>
4,6
BI
4
DQC1_<4>
4,6
BI
6
8
MAC1_<8>
4
4,6
BI
0
MAC1_<0>
4,6
BI
1
MAC1_<1>
4,6
BI
3
MAC1_<3>
4,6
BI
2
MAC1_<2>
4,6
BI
5
MAC1_<5>
4,6
BI
4
MAC1_<4>
4,6
BI
6
MAC1_<6>
4,6
BI
7
MAC1_<7>
4,6
BI
WCKC1_0
4
IN
WCKC1B_0
4
IN
WCKC1_1
4
IN
WCKC1B_1
4
IN
EDCC1_2
4
OUT
EDCC1_3
4
OUT
EDCC1_1
4
OUT
EDCC1_0
4
OUT
DDBIC1_2
4
BI
DDBIC1_3
4
BI
DDBIC1_1
4
BI
DDBIC1_0
4
BI
CASC1B
4
IN
RASC1B
4
IN
CKEC1
4
IN
CLKC1B
4
IN
CLKC1
4
IN
WEC1B
4
IN
CSC1B_0
4
IN
R2502 1%120R
DRAM_RST2
4,6
IN
ADBIC1
4
IN
C26090.1uF
C26110.1uF
C26120.1uF
C26130.1uF
C26140.1uF
C26191uF C26080.1uF
C26201uF
C26211uF C26100.1uF
C26221uF
C26231uF
C26241uF
C26251uF
C264010uF
M2
M4
N2
N4
T2
T4
V2
V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5
K10
K11
H10
H11
H5
H4
D4
D5
P4
P5
R2
R13
C13
C2
P2
P13
D13
D2
G3
L3
J3
J11
J12
G12
L12
J13
J10
J2
J1
A5
V5
A10
V10
J14
J4
C264110uF
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
23CNOPN001
+MVDD
+MVDD
U2500
C27070.1uF
C27171uF
5
5
5
4
+MVDD
B1
VDDQ_B1
B3
VDDQ_B3
B12
VDDQ_B12
B14
VDDQ_B14
D1
VDDQ_D1
D3
VDDQ_D3
D12
VDDQ_D12
D14
VDDQ_D14
E5
VDDQ_E5
E10
VDDQ_E10
F1
VDDQ_F1
F3
VDDQ_F3
F12
VDDQ_F12
F14
VDDQ_F14
G2
VDDQ_G2
G13
VDDQ_G13
H3
VDDQ_H3
H12
VDDQ_H12
K3
VDDQ_K3
K12
VDDQ_K12
L2
VDDQ_L2
L13
VDDQ_L13
M1
VDDQ_M1
M3
VDDQ_M3
M12
VDDQ_M12
M14
VDDQ_M14
N5
VDDQ_N5
N10
VDDQ_N10
P1
VDDQ_P1
P3
VDDQ_P3
P12
VDDQ_P12
P14
VDDQ_P14
T1
VDDQ_T1
T3
VDDQ_T3
T12
VDDQ_T12
T14
VDDQ_T14
+MVDD
C5
VDD_C5
C10
VDD_C10
D11
VDD_D11
G1
VDD_G1
G4
VDD_G4
G11
VDD_G11
G14
VDD_G14
L1
VDD_L1
L4
VDD_L4
L11
VDD_L11
L14
VDD_L14
P11
VDD_P11
R5
VDD_R5
R10
VDD_R10
A1
VSSQ_A1
A3
VSSQ_A3
A12
VSSQ_A12
A14
VSSQ_A14
C1
VSSQ_C1
C3
VSSQ_C3
C4
VSSQ_C4
C11
VSSQ_C11
C12
VSSQ_C12
C14
VSSQ_C14
E1
VSSQ_E1
E3
VSSQ_E3
E12
VSSQ_E12
E14
VSSQ_E14
F5
VSSQ_F5
F10
VSSQ_F10
H2
VSSQ_H2
H13
VSSQ_H13
K2
VSSQ_K2
K13
VSSQ_K13
M5
VSSQ_M5
M10
VSSQ_M10
N1
VSSQ_N1
N3
VSSQ_N3
N12
VSSQ_N12
N14
VSSQ_N14
R1
VSSQ_R1
R3
VSSQ_R3
R4
VSSQ_R4
R11
VSSQ_R11
R12
VSSQ_R12
R14
VSSQ_R14
V1
VSSQ_V1
V3
VSSQ_V3
V12
VSSQ_V12
V14
VSSQ_V14
B5
VSS_B5
B10
VSS_B10
D10
VSS_D10
G5
VSS_G5
G10
VSS_G10
H1
VSS_H1
H14
VSS_H14
K1
VSS_K1
K14
VSS_K14
L5
VSS_L5
L10
VSS_L10
P10
VSS_P10
T5
VSS_T5
T10
VSS_T10
C27080.1uF
C27201uF C27110.1uF
C27211uF C27120.1uF
C27181uF
C27191uF C27100.1uF
+MVDD
R2601 1%60.4R
R2600 1%60.4R
R2603 5%1K
R2604 5%1K
R2609 1%2.37K
+MVDD
R2610 5.49K 1%
C2605 6.3V1uF
+MVDD
12
MC254110uF
C2800
330uF
2.5V
C274110uF
MC254010uF
DRAM SCAN PINS
SSH [J2] - SCAN SHIFT
SCK [G12] - SCAN CLOCK
SOUT [C2] - SCAN OUTPUT
SEN [J10] - SCAN ENABLE
SOE# [J1] - SCAN OUTPUT ENABLE
+
C27140.1uF
C27150.1uF
C27160.1uF
C27221uF
C27231uF
C27241uF
C274010uF
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
R2602 1%120R
4,6
4
MC244010uF
MC274110uF
MC274010uF
4
4
4
5
6
13
DQD0_<13>
4
15
DQD0_<15>
12
DQD0_<12>
14
DQD0_<14>
11
DQD0_<11>
9
DQD0_<9>
10
DQD0_<10>
8
DQD0_<8>
7
DQD0_<7>
6
DQD0_<6>
4
DQD0_<4>
5
DQD0_<5>
0
DQD0_<0>
2
DQD0_<2>
1
DQD0_<1>
3
DQD0_<3>
20
DQD0_<20>
21
DQD0_<21>
23
DQD0_<23>
22
DQD0_<22>
19
DQD0_<19>
17
DQD0_<17>
18
DQD0_<18>
16
DQD0_<16>
26
DQD0_<26>
25
DQD0_<25>
27
DQD0_<27>
24
DQD0_<24>
28
DQD0_<28>
29
DQD0_<29>
30
DQD0_<30>
31
DQD0_<31>
6
8
MAD0_<8>
4
7
MAD0_<7>
6
MAD0_<6>
5
MAD0_<5>
4
MAD0_<4>
3
MAD0_<3>
2
MAD0_<2>
1
MAD0_<1>
0
MAD0_<0>
WCKD0_1
IN
WCKD0B_1
IN
WCKD0_0
IN
WCKD0B_0
IN
EDCD0_1
OUT
EDCD0_0
OUT
EDCD0_2
OUT
EDCD0_3
OUT
DDBID0_1
BI
DDBID0_0
BI
DDBID0_2
BI
DDBID0_3
BI
RASD0B
IN
CASD0B
IN
CKED0
IN
CLKD0B
IN
CLKD0
IN
CSD0B_0
IN
WED0B
IN
DRAM_RST2
IN
ADBID0
IN
MC264110uF
MC264010uF
MC244110uF
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
23CNOPN001
U2600
M2
DQ31__DQ7
M4
DQ30__DQ6
N2
DQ29__DQ5
N4
DQ28__DQ4
T2
DQ27__DQ3
T4
DQ26__DQ2
V2
DQ25__DQ1
V4
DQ24__DQ0
M13
DQ23__DQ15
M11
DQ22__DQ14
N13
DQ21__DQ13
N11
DQ20__DQ12
T13
DQ19__DQ11
T11
DQ18__DQ10
V13
DQ17__DQ9
V11
DQ16__DQ8
F13
DQ15__DQ23
F11
DQ14__DQ22
E13
DQ13__DQ21
E11
DQ12__DQ20
B13
DQ11__DQ19
B11
DQ10__DQ18
A13
DQ9__DQ17
A11
DQ8__DQ16
F2
DQ7__DQ31
F4
DQ6__DQ30
E2
DQ5__DQ29
E4
DQ4__DQ28
B2
DQ3__DQ27
B4
DQ2__DQ26
A2
DQ1__DQ25
A4
DQ0__DQ24
J5
RFU_A12_NC
K4
A7_A8__A0_A10
K5
A6_A11__A1_A9
K10
A5_BA1__A3_BA3
K11
A4_BA2__A2_BA0
H10
A3_BA3__A5_BA1
H11
A2_BA0__A4_BA2
H5
A1_A9__A6_A11
H4
A0_A10__A7_A8
D4
WCK01__WCK23
D5
WCK01#__WCK23#
P4
WCK23__WCK01
P5
WCK23#__WCK01#
R2
EDC3__EDC0
R13
EDC2__EDC1
C13
EDC1__EDC2
C2
EDC0__EDC3
P2
DBI3#__DBI0#
P13
DBI2#__DBI1#
D13
DBI1#__DBI2#
D2
DBI0#__DBI3#
G3
RAS#__CAS#
L3
CAS#__RAS#
J3
CKE#
J11
CK#
J12
CK
G12
CS#__WE#
L12
WE#__CS#
J13
ZQ
J10
SEN
J2
RESET#
J1
MF
A5
Vpp_NC
V5
Vpp_NC1
A10
VREFD1
V10
VREFD2
J14
VREFC
J4
ABI#
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
GDDR5 MEM CH CD
GDDR5 MEM CH CD
GDDR5 MEM CH CD
Thu Jan 15 02:26:21 2015 1.0
Thu Jan 15 02:26:21 2015 1.0
Thu Jan 15 02:26:21 2015 1.0
623
623
623
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
+MVDD
+MVDD
REV:
REV:
REV:
R2701 1%60.4R
R2700 1%60.4R
R2703 5%1K
R2704 5%1K
+MVDD
R2709 1%2.37K
R2710 1%5.49K
C2705 6.3V1uF
6
5
DQD1_<5>
4
4,6
BI
6
DQD1_<6>
4,6
BI
7
DQD1_<7>
4,6
BI
4
DQD1_<4>
4,6
BI
3
DQD1_<3>
4,6
BI
1
DQD1_<1>
4,6
BI
2
DQD1_<2>
4,6
BI
0
DQD1_<0>
4,6
BI
10
DQD1_<10>
4,6
BI
9
DQD1_<9>
4,6
BI
11
DQD1_<11>
4,6
BI
8
DQD1_<8>
4,6
BI
12
DQD1_<12>
4,6
BI
13
DQD1_<13>
4,6
BI
14
DQD1_<14>
4,6
BI
15
DQD1_<15>
4,6
BI
24
DQD1_<24>
4,6
BI
25
DQD1_<25>
4,6
BI
27
DQD1_<27>
4,6
BI
26
DQD1_<26>
4,6
BI
30
DQD1_<30>
4,6
BI
29
DQD1_<29>
4,6
BI
31
DQD1_<31>
4,6
BI
28
DQD1_<28>
4,6
BI
17
DQD1_<17>
4,6
BI
16
DQD1_<16>
4,6
BI
18
DQD1_<18>
4,6
BI
19
DQD1_<19>
4,6
BI
21
DQD1_<21>
4,6
BI
22
DQD1_<22>
4,6
BI
20
DQD1_<20>
4,6
BI
23
DQD1_<23>
4,6
BI
6
8
MAD1_<8>
4
4,6
BI
0
MAD1_<0>
4,6
BI
1
MAD1_<1>
4,6
BI
3
MAD1_<3>
4,6
BI
2
MAD1_<2>
4,6
BI
5
MAD1_<5>
4,6
BI
4
MAD1_<4>
4,6
BI
6
MAD1_<6>
4,6
BI
7
MAD1_<7>
4,6
BI
WCKD1_1
4
IN
WCKD1B_1
4
IN
WCKD1_0
4
IN
WCKD1B_0
4
IN
EDCD1_0
4
OUT
EDCD1_1
4
OUT
EDCD1_3
4
OUT
EDCD1_2
4
OUT
DDBID1_0
4
BI
DDBID1_1
4
BI
DDBID1_3
4
BI
DDBID1_2
4
BI
CASD1B
4
IN
RASD1B
4
IN
CKED1
4
IN
CLKD1B
4
IN
CLKD1
4
IN
WED1B
4
IN
CSD1B_0
4
IN
R2702 1%120R
DRAM_RST2
4,6
IN
ADBID1
4
IN
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
M2
M4
N2
N4
T2
T4
V2
V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5
K10
K11
H10
H11
H5
H4
D4
D5
P4
P5
R2
R13
C13
C2
P2
P13
D13
D2
G3
L3
J3
J11
J12
G12
L12
J13
J10
J2
J1
A5
V5
A10
V10
J14
J4
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
23CNOPN001
U2700
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
1
1
1
8
DD
DD
DD
C
C
C
BB
BB
BB
A
A
A
Page 7
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(7) TRINIDAD GPIO STRAP CF XTAL
+1.8V
R5000
4.99K
1%
A A
B B
C
C
C
C C
D D
+1.8V
A
A
A
R5001
4.99K
1%
+1.8V
R5004
4.99K
1%
R5005
4.99K
1%
SCL/SDA BUS:
I2C ADDRESS
DDCVGA BUS:
I2C ADDRESS
0x98
+1.8V
R50 1%221R
R51 110R 1%
C50 6.3V0.1uF
PS_0
C5000
0.082uF
16V
PS_2
C5002
0.082uF
16V
C29
10uF
6.3V
TP62
PAY ATTENTION TO THE GROUNDING
STRATEGIES FOR THESE FILTER CAPACITORS TO
MAINTAIN A CLOSE LOOP FOR CURRENT.
8
8
8
1
7
7
FUNCTION
FUNCTION
EXT TEMP SENSOR
C5
4.7uF
6.3V
+1.8V
B1
120R
+0.95V
B4
120R
+1.8V
B5
120R
+0.95V
B6
120R
+1.8V
B7
220R
+1.8V
R5002
4.99K
1%
PS_1
R5003
C5001
4.99K
0.082uF
1%
16V
7
+1.8V
R5006
4.99K
1%
PS_3
7
R5007
C5003
4.99K
0.082uF
1%
16V
7
7
7
7
1 2
1 2
1 2
1 2
C6
1uF
6.3V
DVOCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
VREFG
DEVICE
DEVICE
LM96163
BF23
VDDR4#1
BF25
VDDR4#2
BG23
C7
VDDR4#3
1uF
BG25
VDDR4#4
6.3V
BC42
SWAPLOCKA
BE43
SWAPLOCKB
BG38
GENLK_CLK
BG39
GENLK_VSYNC
BD19
DVPCLK
BD26
DVPCNTL_0
BE28
DVPCNTL_1
BE19
DVPCNTL_2
BE29
DVPCNTL_MVP_0
BF29
DVPCNTL_MVP_1
BG36
VREFG
12
C24
10uF
6.3V
R33 1K 5%
U1H
PART 8 OF 18
D
V
P
PITCAIRN
+DPLL_PVDD
C13
C14
10uF
1uF
6.3V
6.3V
DNI
+DPLL_VDDC
C31
C16
4.7uF
1uF
6.3V
6.3V
DNI
+SPLL_PVDD
C18
C19
10uF
1uF
6.3V
6.3V
+SPLL_VDDC
C21
1uF
6.3V
+MPLL_PVDD
C34
C35
C26
4.7uF
4.7uF
1uF
6.3V
6.3V
6.3V
7
7
7
2
1
21
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
DNI
1
21
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
C15
0.1uF
6.3V
DNI
C17
0.1uF
6.3V
C20
0.1uF
6.3V
C22
0.1uF
6.3V
C27
0.1uF
6.3V
BI
OUT
OUT
BI
+3.3V_BUS
+1.8V
PS_0
7
PS_1
7
PS_2
7
PS_3
7
GPIO_3_SMBDATA
GPIO_4_SMBCLK
DDCVGACLK
DDCVGADATA
TEST_PWRGOOD
DVPDATA_0
BC21
DVPDATA_1
BE21
DVPDATA_2
BD21
DVPDATA_3
BE22
DVPDATA_4
BD22
DVPDATA_5
BC22
DVPDATA_6
BE23
DVPDATA_7
7
BD23
DVPDATA_8
BD25
DVPDATA_9
BC25
DVPDATA_10
BG26
DVPDATA_11
BE26
BE31
BD31
BG32
BE32
BD32
BE33
BD33
BE35
BD35
BE36
BD36
BC36
PLACE THE CROSSFIRE TEST POINTS
NEAR THE ASIC AND NOT THE CONNECTOR
BM39
DPLL_PVDD
BK39
DPLL_PVSS
BJ40
DPLL_VDDC
BC29
SPLL_PVDD
BC28
SPLL_PVSS
BC26
SPLL_VDDC
H8
MPLL_PVDD#1
J9
MPLL_PVDD#2
L11
MPLL_PVDD#3
BB38
VDDR3
BB40
VDDR3
BC38
C1
VDDR3
1uF
BC39
VDDR3
6.3V
BB35
VDD_CT
BB36
VDD_CT
BB37
C30
VDD_CT
1uF
BC35
VDD_CT
6.3V
BD42
PS_0
BE42
PS_1
BF42
PS_2
BG42
PS_3
AY42
SMB_DAT
AV42
SMB_CLK
V47
SCL
V46
SDA
U50
DDCVGACLK
U52
DDCVGADATA
AY44
CEC_1
AV47
TEST_PG
AV48
NC
AV49
NC
BH16
NC
BH17
NC
BH43
NC
BJ16
NC
T48
NC
T49
NC
U48
NC
V51
NC
AW44
NC
BG43
NC
7
7
7
7
7
7
7
TP60
7
7
7
U1I
PART 9 OF 18
P
L
L
S
X
T
A
L
PITCAIRN
3
U1G
PART 7 OF 18
GPIO_5_REG_HOT
PITCAIRN
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_8P_DETECT
GPIO_17_THERMAL_INT
G
GPIO_18_HPD3
P
I
GPIO_20_PWRCNTL_1
O
GPIO_22_ROMCSB
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6
RSVD#7_DIGON
RSVD#8_VARYBL
GPIO_0
GPIO_1
GPIO_2
GPIO_6_TACH
GPIO_7_BLON
GPIO_11
GPIO_12
GPIO_13
GPIO_19_CTF
GPIO_21
GPIO_29
GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD
CLKREQB
RSVD#1
RSVD#2
RSVD#3
RSVD#4
RSVD#5
RSVD#6
GPIO_0_VDDC_VID0
V49
BF39
GPIO_2
BD28
BD39
GPIO_6_TACH
V48
BD40
BE46
BF46
BG46
GPIO_11_PWRCNTL_3
AA44
GPIO_12_VDDC_VID4
BA50
GPIO_13_VDDC_VID5
BA52
GPIO_14_VDDC_VID3
AV45
GPIO_15_VDDC_VID1
W44
V45
GPIO_17_THERM_INT
AA45
AV44
GPIO_19_CTF
W43
GPIO_20_VDDC_VID2
W45
BF38
GPIO_22_ROMCSB
BE47
GPIO_29_VDDC_VID6
BF43
GPIO_30_VDDC_VID7
BE40
BH41
BE38
BE39
GENERICD
BG29
HPD4
BC31
HPD5
BC32
HPD6
BA48
HPD1
BE45
HPD1
AA43
AA47
TS_A
AM19
AR19
AN18
AM18
AN19
AR18
AV53
AV51
19,14
OUT
7
20,21
IN
7,19
OUT
19,14
OUT
19,14
OUT
19,14
OUT
19,14
OUT
21
IN
20
OUT
19,14
OUT
19,14
OUT
19,14
OUT
7
10
IN
10
IN
11
IN
9
IN
33R
1 8
RP1A
33R
2 7
RP1B
33R
3 6
RP1C
+3.3V_BUS
R14
2.2K
5%
33R
4 5
RP1D
GPIO_8_RGPIO_8_ROMSO
GPIO_9_RGPIO_9_ROMSI
GPIO_10_RGPIO_10_ROMSCK
GPIO_22_R
MR8 10K 5%
+3.3V_BUS +3.3V_BUS
3
2
5
6
1
+3.3V_BUS
R8 5%10K
DNI
R10 10K 5%
R11 10K 5%
CROSSFIRE
LOWER CABLE CARD EDGE
schematic
614NOPN128
DVOCLK
7
CLK_1
DVPCNTL_2
7
DE_1
DVPDATA_1
7
7
DVPDATA_3
7
DVPDATA_5
7
DVPDATA_7
7
DVPDATA_9
7
DVPDATA_11
7
DVPCNTL_1
7
RSVD
GENERICD
7
FLOW_CONTROL_1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J2
DVPDATA_0
DVPDATA_2
DVPDATA_4
DVPDATA_6
DVPDATA_8
DVPDATA_10
DVPCNTL_0
GPIO_2
SWAP_LOCK_1
MR15 5%10K
7
7
7
7
7
7
7
7
DNI
Y2
R38 1M 1%
XIN_OSC_1
XOUT_OSC_1
5%0R
B5000
120R
C32
UNNAMED_7_CAP_I416_B
12
27.000MHz
UNNAMED_7_CAP_I412_A
C33
18pF
50V
1 2
R24 51.1R 1%
R25 51.1R 1%
50V18pF
C12
18pF 50V
3
4
Y1
27.000MHz
1
2
R37 1%1M
C11
18pF
50V
+1.8V
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD GPIO STRAP CF XTAL
TRINIDAD GPIO STRAP CF XTAL
TRINIDAD GPIO STRAP CF XTAL
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:22 2015 1.0
Thu Jan 15 02:26:22 2015 1.0
Thu Jan 15 02:26:22 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
723
723
723
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
6
6
6
BM41
XO_IN2
BK41
XO_IN
7
BN40
XTALIN
7
BL40
XTALOUT
+XTAL_VDDR
BF40
XTAL_VDDR
BG40
XTAL_VSS
CLKTESTA CLKTESTA_C
BM17
CLKTESTA
CLKTESTB CLKTESTB_C
BK17
CLKTESTB
XIN_OSC
7
XOUT_OSC
7
XIN_OSC
XOUT_OSC
C5100
4.7uF
6.3V
C23 6.3V0.1uF
C28 0.1uF 6.3V
ROUTE 50OHMS SINGLE ENDED OR 100OHMS DIFFERENTIAL
KEEP THEM SHORT
R60
1 2
0R 5%
1 2
1 2
0R 5%
5
5
5
4
R61
5%0R
R30
1 2
R31
VIDEO BIOS
FIRMWARE
WP
SO
SI
SCK
CE
PM25LV010A-100SC
DNI
DNI
DNI
U11
VDD
HOLD
GND
GPIO_11_PWRCNTL_3
GPIO_11_PWRCNTL_3
VSYNC
HSYNC
GPIO_28_TS_FDO
8
7
C4
0.1uF
6.3V
4
PIN BASED STRAPS
REV:
REV:
REV:
GPIO(13,12,11) - CONFIG[2..0]
CONFIG[2]
CONFIG[1]
CONFIG[0]
7 19
HSYNC = AUD[1], VSYNC = AUD[0]
AUD[0]
8
OUT
AUD[1]
8
OUT
HDMI MUST ONLY BE ENABLED ON SYSTMES THAT ARE LEGALLY
ENTITLED. IT IS THE RESPONSIBILITY OF THE SYSTEM DESIGNER
TO SUPPORT THIS FEATURE.
GPIO(8) - BIF_CLK_PM_EN
0 - DISABLE CLKREQb POWER MANAGEMENT CAPABILITY
1 - ENABLE CLKREQb POWER MANAGEMENT CAPABILITY
ENSURE THAT NO LOGIC CONFLICTS WITH THIS SIGNAL DURING RESET.
GPIO(28) - MLPS_DIS
0 - ENABLE MLPS
20
OUT
1 - DISALBE MLPS
100 - 512KBIT (ST) M25P05A
101 - 1MBIT (ST) M25P10A
101 - 2MBIT (ST) M25P20
101 - 4MBIT (ST) M25P40
101 - 8MBIT (ST) M25P80
100 - 512KBIT (CHINGIS) PM25LV512
101 - 1MBIT (CHINGIS) PM25LV010
00 - NO AUDIO FUNCTION
01 - AUDIO FOR DP ONLY
10 - AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED
11 - AUDIO FOR BOTH DP AND HDMI
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
DD
DD
DD
C
C
C
BB
BB
BB
A
A
A
1
1
1
8
Page 8
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(8) TRINIDAD DAC1 LOCK
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
DD
DD
DD
R1501
150R
1%
R1504
150R
1%
R1509
150R
1%
1
2 4
1
2 4
L1503
L1504
L1505
U1500A
74AHCT1G126GW
U1501A
74AHCT1G126GW
SEE BOM FOR QUALIFIED FILTERS
1 2
0.047uH
1 2
1 2
0.047uH
C1504
8pF
50V
C1506
8pF
50V
0.047uH
C1509
8pF
50V
HSYNC_DAC_B
VSYNC_DAC_B
L1500
L1501
L1502
1 2
1 2
1 2
0.047uH
0.047uH
0.047uH
C1503
12pF
50V
C1505
12pF
50V
C1510
12pF
50V
R1514 5%24R
R1515 5%24R
A_R_DAC_F
A_G_DAC_F
A_B_DAC_F
HSYNC_DAC_R
VSYNC_DAC_R
C1512
12pF
50V
DNI
C1513
12pF
50V
DNI
8,11
OUT
8,11
OUT
8,11
OUT
8,11
OUT
8,11
OUT
C
C
C
BB
BB
BB
U1J
+1.8V
1 2
B1600
120R
+1.8V
1 2
B1601
120R
PAY ATTENTION TO THE GROUNDING
STRATEGIES FOR THESE FILTER CAPACITORS TO
MAINTAIN A CLOSE LOOP FOR CURRENT.
C
C
C
B B
+VDD1DI
+AVDD
R1500 1%499R
C1500
C1501
1uF
0.1uF
6.3V
6.3V
AW45
C1507
C1508
1uF
0.1uF
6.3V
6.3V
RSET
PART 10 OF 18
AY45
VDD1DI
VSS1DI
BB45
AVDD
BC45
AVDD
BB44
AVSSQ
D
A
C
BB43
RSET
PITCAIRN
+5V_VESA
C1514 6.3V0.1uF
U1500B
74AHCT1G126GW
3 5
+5V_VESA
C1515 6.3V0.1uF
U1501B
74AHCT1G126GW
3 5
AY47
R
AY46
AVSSN
BB47
G
BB46
AVSSN
BC47
B
BC46
AVSSN
AW46
HSYNC
AW47
VSYNC
HSYNC
7
OUT
VSYNC
7
OUT
R_DAC R_DAC_L
R1503
150R
1%
G_DAC G_DAC_L
R1508
150R
1%
B_DAC B_DAC_L
R1513
150R
1%
C C
OPTIONAL ESD PROTECTION DIODES
D1500 ESD5V3U1U-02LRH
12
D1501 ESD5V3U1U-02LRH
12
D1502 ESD5V3U1U-02LRH
12
D1505 ESD8V0R1B-02LRH
12
D1506 ESD8V0R1B-02LRH
A
A
A
12
D D
8
8
8
1
7
7
7
2
A_R_DAC_F
A_G_DAC_F
A_B_DAC_F
HSYNC_DAC_R
VSYNC_DAC_R
8 11
8 11
8 11
8 11
8 11
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD DAC
TRINIDAD DAC
TRINIDAD DAC
SHEET:
SHEET:
SHEET:
Wed Jul 30 07:10:44 2014 1.0
Wed Jul 30 07:10:44 2014 1.0
Wed Jul 30 07:10:44 2014 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
5
5
6
6
6
3
5
4
4
4
4
5
823
823
823
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
REV:
REV:
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
Page 9
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(9) TRINIDAD TMDP A/B
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
+1.8V
C1700
C1701
C1702
A A
C
C
C
B B
PLEASE PAY ATTENTION TO THE GROUNDING
STRATEGIES FOR THESE FILTER CAPACITORS TO
MAINTAIN A CLOSE LOOP FOR CURRENT
C C
1uF
6.3V
C1703
0.1uF
6.3V
C1706
4.7uF
6.3V
+0.95V
C1710
1uF
6.3V
C1713
0.1uF
6.3V
C1716
4.7uF
6.3V
R1700 1%150R
C1738
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1704
C1705
C1719
0.1uF
0.1uF
0.1uF
6.3V
6.3V
6.3V
C1707
C1708
C1709
4.7uF
4.7uF
4.7uF
6.3V
6.3V
6.3V
C1711
1uF
6.3V
C1714
0.1uF
6.3V
C1717
4.7uF
6.3V
DPAB_CALR
BF33
DP_VDDR
BG33
DP_VDDR
BH32
DP_VDDR
BH33
DP_VDDR
BH34
DP_VDDR
BH35
DP_VDDR
BF22
NC_DP_VDDR
BF45
NC_DP_VDDR
BG22
NC_DP_VDDR
BG45
NC_DP_VDDR
BH20
NC_DP_VDDR
BH21
NC_DP_VDDR
BH42
NC_DP_VDDR
BH44
NC_DP_VDDR
BH45
NC_DP_VDDR
BJ42
NC_DP_VDDR
BL18
NC_DP_VDDR
BN18
NC_DP_VDDR
BF28
DP_VDDC
BF31
DP_VDDC
BG28
DP_VDDC
BG31
DP_VDDC
BH26
DP_VDDC
BH27
DP_VDDC
BH28
DP_VDDC
BH29
DP_VDDC
BF47
NC_DP_VDDC
BF48
NC_DP_VDDC
BG47
NC_DP_VDDC
BG48
NC_DP_VDDC
BC50
DP_VSSR
BD48
DP_VSSR
BD53
DP_VSSR
BE48
DP_VSSR
BF35
DP_VSSR
BF53
DP_VSSR
BG21
DP_VSSR
BG35
DP_VSSR
BH24
DP_VSSR
BH25
DP_VSSR
BH30
DP_VSSR
BH31
DP_VSSR
BH36
DP_VSSR
BH37
DP_VSSR
BH46
DP_VSSR
BH47
DP_VSSR
BJ18
DP_VSSR
BL38
DP_VSSR
BM19
DP_VSSR
BM43
DP_VSSR
BN20
DP_VSSR
BN22
DP_VSSR
BN24
DP_VSSR
BN26
DP_VSSR
BN28
DP_VSSR
BN30
DP_VSSR
BN32
DP_VSSR
BN34
DP_VSSR
BN36
DP_VSSR
BN38
DP_VSSR
BN44
DP_VSSR
BN46
DP_VSSR
BF36
DPAB_CALR
U1K
PART 11 OF 18
PITCAIRN
+5V_POWER
TMDS_Data0/5_Shield
TMDS_Data1/3_Shield
TMDS_Data2/4_Shield
TMDS_Clock_Shield
GND_(for_+5V)
+5V_VESA
B14
C1740
1uF
16V
SCREW1903
B19
SCREW1904
B11
B3
B22
B15
DD
DD
DD
C
C
C
BB
BB
BB
BM33
TX2P_DPA0P
BL32
TX2M_DPA0N
BJ32
TX1P_DPA1P
BK31
TX1M_DPA1N
BM31
TX0P_DPA2P
BL30
TX0M_DPA2N
BJ30
TXCAP_DPA3P
BK29
TXCAM_DPA3N
BM29
DDCCLK_AUX3P
BL28
DDCDATA_AUX3N
T
M
D
P
A
/
B
BJ38
TX5P_DPB0P
BK37
TX5M_DPB0N
BM37
TX4P_DPB1P
BL36
TX4M_DPB1N
BJ36
TX3P_DPB2P
BK35
TX3M_DPB2N
BM35
TXCBP_DPB3P
BL34
TXCBM_DPB3N
BJ44
DDCCLK_AUX5P
BK43
DDCDATA_AUX5N
DPA_TX2P
DPA_TX2N
DPA_TX1P
DPA_TX1N
DPA_TX0P
DPA_TX0N
DPA_TXCP
DPA_TXCN
DDC3CLK_HDMI
DDC3DAT_HDMI
DPB_TX5P
DPB_TX5N
DPB_TX4P
DPB_TX4N
DPB_TX3P
DPB_TX3N
OUT
BI
DDC5DAT_DVI
C1720 6.3V0.1uF
C1721 6.3V0.1uF
C1722 0.1uF 6.3V
C1723 0.1uF 6.3V
C1724 6.3V0.1uF
C1725 6.3V0.1uF
C1726 6.3V0.1uF
C1727 0.1uF 6.3V
10
10
DVI_EN
11,10
IN
C1728 6.3V0.1uF
C1729 6.3V0.1uF
C1730 6.3V0.1uF
C1731 0.1uF 6.3V
9
C1732 6.3V0.1uF
C1733 6.3V0.1uF
ABTX5P
ABTX5N
ABTX4N
ABTX3N
+5V_VESA
R1701
R1702
2.2K
2.2K
5%
5%
7
OUT
R1720 499R 1%
ABTX2P
R1721 1%499R
ABTX2N
R1722 499R 1%
R1723 1%499R
ABTX1N
R1724 499R 1%
ABTX0P
R1725 1%499R
ABTX0N
R1726 499R 1%
ABTXCP
R1727 499R 1%
R1728 1%499R
R1729 1%499R
R1730 499R 1%
ABTX4P
R1731 1%499R
R1732 499R 1%
R1733 1%499R
DPAB_GND
61
Q1700B
2
2N7002DW
+3.3V_BUS
6
Q1701A
R1703 5%10K
2
MMDT3904-7
HPD1
R1704 5%10K
1
ABTX2P
9
ABTX2N
9
ABTX1P
9
ABTX1N
9
ABTX0P
9
ABTX0N
9
ABTXCP
9
ABTXCN
9
ABTX5P
9
ABTX5N
9
ABTX4P
9
ABTX4N
ABTX3P
9
ABTX3N
9
DDC5CLK_DVI
9
DDC5DAT_DVI
9
HPD_AB_DVIUNNAMED_9_NPN_I292_B
J1900B
B2
TMDS_Data2+
B1
TMDS_Data2-
B10
TMDS_Data1+
B9
TMDS_Data1-
B18
TMDS_Data0+
B17
TMDS_Data0-
B23
TMDS_Clock+
B24
TMDS_Clock-
B21
TMDS_Data5+
B20
TMDS_Data5-
B5
TMDS_Data4+
B4
TMDS_Data4-
B13
TMDS_Data3+
B12
TMDS_Data3-
B6
DDC_Clock
B7
DDC_Data
B8
Analog_VSYNC
B16
Hot_Plug_Detect
DVI-D_OVER_DVI-I
STACKED DVI - TOP
OPTIONAL ESD PROTECTION DIODES
D1700 ESD5V3U1U-02LRH
12
D1701 ESD5V3U1U-02LRH
12
D1702 ESD5V3U1U-02LRH
12
D1703 ESD5V3U1U-02LRH
12
D1704 ESD5V3U1U-02LRH
12
D1705 ESD5V3U1U-02LRH
12
D1706 ESD5V3U1U-02LRH
12
D1707 ESD5V3U1U-02LRH
12
D1708 ESD5V3U1U-02LRH
12
D1709 ESD5V3U1U-02LRH
12
D1710 ESD5V3U1U-02LRH
12
D1711 ESD5V3U1U-02LRH
A
A
A
D D
8
8
8
1
7
7
7
2
12
D1712 ESD5V3U1U-02LRH
12
D1713 ESD5V3U1U-02LRH
12
D1714 ESD5V3U1U-02LRH
12
D1715
ESD5V3U1U-02LRH
12
D1716
ESD5V3U1U-02LRH
12
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
ABTX2P
ABTX2N
ABTX1P
ABTX1N
ABTX0P
ABTX0N
ABTXCP
ABTXCN
ABTX5P
ABTX5N
ABTX4P
ABTX4N
ABTX3P
ABTX3N
DDC5CLK_DVI
DDC5DAT_DVI
HPD_AB_DVI
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
6
6
6
3
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD TMDPAB dDVI TOP
TRINIDAD TMDPAB dDVI TOP
TRINIDAD TMDPAB dDVI TOP
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:22 2015 1.0
Thu Jan 15 02:26:22 2015 1.0
Thu Jan 15 02:26:22 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
5
5
5
4
4
4
4
5
923
923
923
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
REV:
REV:
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
Page 10
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(10) TRINIDAD TMDP C/D
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
PART 12 OF 18
T
M
D
P
C
/
D
PITCAIRN
U1L
DDC3CLK_HDMI
DDC3DAT_HDMI
10
10
10
10
10
10
10
10
10
10
+3.3V_BUS
DPC_0P
DPC_0N
DPC_1P
DPC_1N
DPC_2P
DPC_2N
DPC_3P
DPC_3N
AUX1P_DPC
AUX1N_DPC
HPD_DPC
DPC_DONGLE_DET
10
10
10
10
10
10
10
10
R1806 5.1M 5%
DTX2P
DTX2N
DTX1P
DTX1N
DTX0P
DTX0N
DTXCAP
DTXCAN
HPD_HDMI
TX2P_DPC0P
TX2M_DPC0N
TX1P_DPC1P
TX1M_DPC1N
TX0P_DPC2P
TX0M_DPC2N
TXCCP_DPC3P
TXCCM_DPC3N
DDC1CLK
DDC1DATA
TX5P_DPD0P
TX5M_DPD0N
TX4P_DPD1P
TX4M_DPD1N
TX3P_DPD2P
TX3M_DPD2N
TXCDP_DPD3P
TXCDM_DPD3N
DDC2CLK
DDC2DATA
BM23
BL22
BJ22
BK21
BM21
BL20
BJ20
BK19
BH19
AUX1P
BH18
AUX1N
BG19
BG18
BJ28
BK27
BM27
BL26
BJ26
BK25
BM25
BL24
BJ24
AUX2P
BK23
AUX2N
BH23
BH22
DPC_C0P
DPC_C0N
DPC_C1P
DPC_C1N
DPC_C2P
DPC_C2N
DPC_C3P
DPC_C3N
AUX1P
AUX1N
DDC1CLK
DDC1DATA
DPD_TX2P
DPD_TX2N
DPD_TX1P
DPD_TX1N
DPD_TX0P
DPD_TX0N
DPD_TXCP
DPD_TXCN
Q1801B
2N7002DW
2
61
C1801 0.1uF 6.3V
C1802 6.3V0.1uF
C1805 6.3V0.1uF
C1806 6.3V0.1uF
C1807 6.3V0.1uF
C1808 6.3V0.1uF
C1809 6.3V0.1uF
C1810 6.3V0.1uF
C1811 6.3V0.1uF
C1812 0.1uF 6.3V
34
Q1801A
2N7002DW
5
C1829 6.3V0.1uF
C1830 6.3V0.1uF
C1831 6.3V0.1uF
C1832 6.3V0.1uF
C1833 6.3V0.1uF
C1834 6.3V0.1uF
C1835 6.3V0.1uF
C1836 0.1uF 6.3V
AUX1_BYPSS_EN
+5V_VESA
R1802 5%100K
Q1800A
MMBT3904
6
1
+3.3V_BUS
Q1823
R1803 5%100K
R1807 5%10K
2
R1808 10K 5%
R1801 1M 5%
1
2 3
N28404577
N62218298
R1829 5%10K
R1828 10K 5%
+12V_BUS +12V_BUS +3.3V_BUS
R1804
R1805
10K
10K
5%
5%
7
OUT
3
Q1800B
MMDT3904-7
4
R1830
R1831
2.2K
2.2K
5%
5%
DDC3DAT_HDMI
1
Q1804
5
N50484859
2 3
2N7002E
DVI_EN
11,9
IN
7
1
OUT
HPD4
DTX2P
R1825 499R 1%
DTX2N
R1824 499R 1%
DTX1P
R1823 1%499R
DTX1N
R1822 1%499R
DTX0P
R1821 499R 1%
DTX0N
R1820 1%499R
DTXCAP
R1819 499R 1%
DTXCAN
R1818 1%499R
DPD_GND
Q1820
2N7002E
2 3
HPD5
MMDT3904-7
J1800
1
ML_Lane_0p
ML_Lane_0n
ML_Lane_1p
ML_Lane_1n
ML_Lane_2p
ML_Lane_2n
ML_Lane_3p
ML_Lane_3n
AUX_CHp
AUX_CHn
Hot_Det
CONFIG 1
CONFIG 2
DP_RECEPTACLE_W/TAB
1
TMDS Data 2+
3
TMDS Data 2-
4
TMDS Data 1+
6
TMDS Data 1-
7
TMDS Data 0+
9
TMDS Data 0-
10
TMDS Clock+
12
TMDS Clock-
15
DDC Clock
16
DDC Data
19
Hot Plog Detect
14
NC
13
CEC
J2501
HDMI_W/TAB
DP_PWR
PWR_RTN
GND_2
GND_0
GND_1
GND_3
GND_6
GND (+5V)
3
4
6
7
9
10
12
15
17
18
13
14
Dp_I206_PIN14
9,10
OUT
9,10
BI
+3.3V_DP
20
C1817
C1840
22uF
100uF
6.3V
6.3V
SCREW1800
SCREW
19
G1
G1
G2
G2
G3
G3
G4
G4
2
5
8
11
16
+5V_VESA
18
+5V Pwr
C1737
1uF
6.3V
8
D0 Shld
5
D1 Shld
2
D2 Shld
11
Clk Shld
17
20
CASE
21
CASE
22
CASE
23
CASE
+3.3V_BUS
F1800
12
1.5A
DD
DD
DD
C
C
C
BB
BB
BB
A A
C
C
C
B B
R1800 1%150R
C C
DPCD_CALR
BF18
DPCD_CALR
OPTIONAL ESD PROTECTION DIODES
6
6
6
3
D1852 ESD5V3U1U-02LRH
12
D1853
ESD5V3U1U-02LRH
12
DNI
DNI
DDC3CLK_HDMI
DDC3DAT_HDMI
5
5
5
4
9 10
9 10
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD TMDPCD DP HDMI
TRINIDAD TMDPCD DP HDMI
TRINIDAD TMDPCD DP HDMI
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:22 2015 1.0
Thu Jan 15 02:26:22 2015 1.0
Thu Jan 15 02:26:22 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
4
4
4
5
10 23
10 23
10 23
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
REV:
REV:
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
D1800
DPC_0P DPC_0P
5
10
10
10
10
10
10 10
10
A
A
A
D D
D6Y4
DPC_0N DPC_0N
4
7
C
Y3
3
8
GND
2
B
1
A
5
D6Y4
4
C
3
GND
2
B
1
A
RCLAMP0524P
D1802
RCLAMP0524P
GND1
9
Y2
10
Y1
7
Y3
8
GND1
9
Y2
10
Y1
D1809 ESD5V3U1U-02LRH
D1808 ESD5V3U1U-02LRH
D1810 ESD5V3U1U-02LRH
D1811 ESD5V3U1U-02LRH
D1812 ESD5V3U1U-02LRH
DPC_1P DPC_1P
DPC_1N DPC_1N
DPC_2P DPC_2P
DPC_2N DPC_2N
DPC_3P DPC_3P
DPC_3N DPC_3N
8
8
8
1
DTX2P DTX2P
10 10
10
DTX2N DTX2N
10
10
DTX1P DTX1P
10 10
10
DTX1N DTX1N
10
10
DTXCAN DTXCAN
10
10
DTXCAP DTXCAP
10
10
DTX0N DTX0N
10
DTX0P DTX0P
10
10
12
12
12
12
12
7
7
7
2
5
D6Y4
4
C
3
GND
2
B
1
A
5
D6Y4
4
C
3
GND
2
B
1
A
AUX1N_DPC
AUX1P_DPC
HPD_DPC
HPD_HDMI
DPC_DONGLE_DET
D1850
Y3
GND1
Y2
Y1
RCLAMP0524P DNI
D1851
Y3
GND1
Y2
Y1
10
10
7
8
9
10
7
8
9
10
DNIRCLAMP0524P
10
10
10
10
10
10
10
Page 11
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(11) TRINIDAD LVTMDP E/F
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
C
C
C
B B
R1900 150R 1%
C C
OPTIONAL ESD PROTECTION DIODES
D1900 ESD5V3U1U-02LRH
D1901 ESD5V3U1U-02LRH
D1902 ESD5V3U1U-02LRH
D1903 ESD5V3U1U-02LRH
D1904 ESD5V3U1U-02LRH
D1905 ESD5V3U1U-02LRH
D1906 ESD5V3U1U-02LRH
D1907 ESD5V3U1U-02LRH
D1908 ESD5V3U1U-02LRH
D1909 ESD5V3U1U-02LRH
D1910 ESD5V3U1U-02LRH
8
8
8
1
D1911 ESD5V3U1U-02LRH
D1912 ESD5V3U1U-02LRH
D1913 ESD5V3U1U-02LRH
D1503
D1504
D1507
A
A
A
D D
DPEF_CALR
12
12
12
12
12
12
12
12
12
12
12
12
12
12
ESD8V0R1B-02LRH
12
ESD8V0R1B-02LRH
12
ESD8V0R1B-02LRH
12
BC48
EFTX2P
EFTX2M
EFTX1P
EFTX1M
EFTX0P
EFTX0M
EFTXCP
EFTXCM
EFTX5P
EFTX5M
EFTX4P
EFTX4M
EFTX3P
EFTX3M
DDC6DATA_DVI
DDC6CLK_DVI
HPD_EF_DVI
DPEF_CALR
2
U1M
PART 13 OF 18
BL49
RSVD_L3P
BN48
RSVD_L3N
BJ48
L2P_TX2P_DPE0P
BK47
L2N_TX2M_DPE0N
BM47
L1P_TX1P_DPE1P
BL46
L1N_TX1M_DPE1N
BJ46
L0P_TX0P_DPE2P
BK45
L0N_TX0M_DPE2N
BM45
LP_TXCEP_DPE3P
BL44
LN_TXCEM_DPE3N
BJ34
DDCCLK_AUX4P
L
V
T
M
D
P
E
/
F
PITCAIRN
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
7
7
7
DDCDATA_AUX4N
RSVD_U3P
RSVD_U3N
U2P_TX5P_DPF0P
U2N_TX5M_DPF0N
U1P_TX4P_DPF1P
U1N_TX4M_DPF1N
U0P_TX3P_DPF2P
U0N_TX3M_DPF2N
UP_TXCFP_DPF3P
UN_TXCFM_DPF3N
DDCCLK_AUX6P
DDCCLK_AUX6N
BK33
BC52
BD51
BD49
BE50
BE52
BF51
BF49
BG50
BG52
BH53
BH49
BJ51
DPE_TX2P
DPE_TX2N
DPE_TX1P
DPE_TX1N
DPE_TX0P
DPE_TX0N
DPE_TXCAP
DPE_TXCAN
DPF_TX5P
DPF_TX5N
DPF_TX4P
DPF_TX4N
DPF_TX3P
DPF_TX3N
DDC6CLK_DVI
11
DDC6DATA_DVI
11
6
6
6
3
11 8
+5V_VESA
11 8
11 8
11 8
11 8
SINGLE DVI OPTION
C1904 0.1uF 6.3V
C1905 0.1uF 6.3V
C1906 0.1uF 6.3V
C1907 0.1uF 6.3V
C1908 0.1uF 6.3V
C1909 0.1uF 6.3V
C1910 0.1uF 6.3V
C1911 6.3V0.1uF
C1920 0.1uF 6.3V
C1921 0.1uF 6.3V
C1922 0.1uF 6.3V
C1923 0.1uF 6.3V
C1924 6.3V0.1uF
C1925 0.1uF 6.3V
EFTX2M
11
EFTX2P
11
EFTX4M
11
EFTX4P
11
DDC6CLK_DVI
11
DDC6DATA_DVI
11
VSYNC_DAC_R
EFTX1M
11
EFTX1P
11
EFTX3M
11
EFTX3P
11
+5V_VESA
HPD_EF_DVI
11
EFTX0M
11
EFTX0P
11
EFTX5M
11
EFTX5P
11
EFTXCP
11
EFTXCM
11
A_R_DAC_F
A_G_DAC_F
A_B_DAC_F
HSYNC_DAC_R
5
5
5
4
EFTX2P
R1901 499R 1%
R1903 499R 1%
EFTX2M
R1902 499R 1%
R1905 1%499R
EFTX1M
EFTX0P
R1904 499R 1%
R1907 499R 1%
EFTX0M
R1906 1%499R
EFTXCP
R1908 499R 1%
R1909 499R 1%
R1911 499R 1%
R1910 1%499R
EFTX4P
R1913 1%499R
R1912 499R 1%
+12V_BUS
R1917
100K
5%
DVI_EN
9,10
CASE#M3
CASE#M4
CASE#M5
CASE#M6
OUT
EFTX3M
27
28
29
30
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
EFTX5P
EFTX5M
EFTX4M
+5V_VESA
R1505
R1506
2.2K
2.2K
5%
5%
MJ1900
25
CASE
1
TMDS_Data2-
2
TMDS_Data2+
3
TMDS_Data2/4_Shield
4
TMDS_Data4-
5
TMDS_Data4+
6
DDC_Clock
7
DDC_Data
8
Analog_VSYNC
9
TMDS_Data1-
10
TMDS_Data1+
11
TMDS_Data1/3_Shield
12
TMDS_Data3-
13
TMDS_Data3+
14
+5V_Power
15
GND_(for_+5V)
16
Hot_Plug_Detect
17
TMDS_Data0-
18
TMDS_Data0+
19
TMDS_Data0/5_Shield
20
TMDS_Data5-
21
TMDS_Data5+
22
TMDS_Clock_Shield
23
TMDS_Clock+
24
TMDS_Clock-
C1
Analog_Red
C2
Analog_Green
C3
Analog_Blue
C4
Analog_HYNC
C5
Analog_GND
C6
Analog_GND#C6
26
CASE#M2
DVI-I_BLACK
R1914 499R 1%
DPEF_GND
34
Q1700A
5
2N7002DW
C1917
0.1uF
16V
11
11
11
11
11
11
11
11
11
11
11
11
11
11
+3.3V_BUS
Q1701B
MMDT3904-7
HPD6
7
OUT
TRINIDAD LVTMDPEF dDVI Bottom
TRINIDAD LVTMDPEF dDVI Bottom
TRINIDAD LVTMDPEF dDVI Bottom
Thu Jan 15 02:26:23 2015 1.0
Thu Jan 15 02:26:23 2015 1.0
Thu Jan 15 02:26:23 2015 1.0
11 23
11 23
11 23
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
3
4
11
11
UNNAMED_11_NPN_I158_B
5
R1915 5%10K
R1916 5%10K
DD
DD
DD
EFTX2P
EFTX2M
EFTX1P
EFTX1M
EFTX0P
EFTX0M
EFTXCP
EFTXCM
EFTX5P
EFTX5M
EFTX4P
EFTX4M
EFTX3P
EFTX3M
EFTX2P
EFTX2M
EFTX1P
EFTX1M
EFTX0P
EFTX0M
EFTXCP
EFTXCM
EFTX5P
EFTX5M
EFTX4P
EFTX4M
EFTX3P
EFTX3M
DDC6CLK_DVI
DDC6DATA_DVI
A_R_DAC_F
8,11
IN
A_G_DAC_F
8,11
IN
A_B_DAC_F
8,11
IN
HSYNC_DAC_R
8,11
IN
VSYNC_DAC_R
8,11
IN
HPD_EF_DVI
11
REV:
REV:
REV:
11
11
11
11
11
11
11
11
11
11
11
11
11
11
A2
TMDS_Data2+
A1
TMDS_Data2-
A10
TMDS_Data1+
A9
TMDS_Data1-
A18
TMDS_Data0+
A17
TMDS_Data0-
A23
TMDS_Clock+
A24
TMDS_Clock-
A21
TMDS_Data5+
A20
TMDS_Data5-
A5
TMDS_Data4+
A4
TMDS_Data4-
A13
TMDS_Data3+
A12
TMDS_Data3-
A6
DDC_Clock
A7
DDC_Data
C1
Analog_Red
C2
Analog_Green
C3
Analog_Blue
C4
Analog_HYNC
A8
Analog_VSYNC
A16
Hot_Plug_Detect
DVI-D_OVER_DVI-I
STACKED DVI - BOTTOM
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
J1900A
+5V_POWER
TMDS_Data0/5_Shield
TMDS_Data1/3_Shield
TMDS_Data2/4_Shield
TMDS_Clock_Shield
GND_(for_+5V)
Analog_GND
Analog_GND#C6
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
C
C
C
+5V_VESA
A14
C1926
1uF
16V
BB
BB
BB
SCREW1900
A19
A11
A3
A22
A15
C5
C6
SCREW1901
A
A
A
1
1
1
8
Page 12
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(12) TRINIDAD POWER
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
B B
C C
+VDDC +VDDC +MVDD
C1209
C1200
C1203
C1204
C1205
C1206
C1207
1uF
1uF
1uF
1uF
1uF
1uF
C1221
C1222
C1223
C1224
C1225
C1226
1uF
1uF
1uF
1uF
1uF
1uF
C1237
C1238
C1239
C1240
C1241
C1242
C
C
C
1uF
1uF
1uF
1uF
1uF
1uF
C1247
C1248
C1249
C1250
C1251
C1252
1uF
1uF
1uF
1uF
1uF
1uF
C1257
C1258
C1259
C1260
C1261
C1262
1uF
1uF
1uF
1uF
1uF
1uF
C1267
C1268
C1269
C1270
C1271
C1272
1uF
1uF
1uF
1uF
1uF
1uF
C1277
C1278
1uF
1uF
C1210
C1208
1uF
C1227
1uF
C1243
1uF
C1253
1uF
C1263
1uF
C1273
1uF
C1211
1uF
1uF
1uF
C1202
C1229
C1228
1uF
1uF
1uF
C1245
C1246
C1244
1uF
1uF
1uF
C1255
C1256
C1254
1uF
1uF
1uF
C1265
C1266
C1264
1uF
1uF
1uF
C1275
C1276
C1274
1uF
1uF
1uF
AA21
AA23
AA26
AA28
AA31
AA33
AB19
AB22
AB24
AB27
AB30
AB32
AB35
AC18
AC21
AC23
AC26
AC28
AC31
AC33
AC36
AD17
AD19
AD22
AD24
AD27
AD30
AD32
AD35
AD37
AD40
AF16
AF18
AF21
AF23
AF26
AF28
AF31
AF33
AF36
AF38
AG17
AG19
AG22
AG24
AG27
AG30
AG32
AG35
AG37
AH16
AH18
AH21
AH23
AH26
AH28
AH31
AH33
AH36
AH38
AK17
AK19
AK22
AK24
AK27
AK30
AK32
AK35
AK37
AL18
AL21
AL23
AL26
AL28
AL31
AL33
AL36
U1N
PART 14 OF 18
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
PITCAIRN
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
P
VDDC
O
VDDC
W
VDDC
E
R
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
FB_VDDC
FB_VSSC
AL38
AM22
AM24
AM27
AM30
AM32
AM35
AM37
AM40
AN21
AN23
AN26
AN28
AN31
AN33
AN36
AN38
AN41
AR22
AR24
AR27
AR30
AR32
AR35
AR37
AR40
AT23
AT26
AT28
AT31
AT33
AT36
AT38
AT41
AU24
AU27
AU30
AU32
AU35
AU37
AU40
AV26
AV28
AV31
AV33
AV36
AV38
AV41
AY24
AY27
AY30
AY32
AY35
AY37
AY40
BA26
BA28
BA31
BA33
BA36
BA38
BB24
BB27
BB30
BB32
T26
T28
U24
U27
U30
V23
V26
V28
V31
W22
W24
W27
W30
W32
AF41
AG41
VDDC_VSEN
OUT
VDDC_VRTN
OUT
C1212
C1213
C1214
C1215
C1216
C1201
C1217
C1218
C1219
C1220
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
C1230
C1231
C1232
C1233
C1234
C1235
C1236
C1279
C1281
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
C1282
C1283
22uF
22uF
14
14
C1402
C1403
C1404
C1406
C1407
C1408
C1401
1uF
1uF
1uF
1uF
C1411
C1412
C1410
1uF
1uF
1uF
C1420
C1421
1uF
1uF
C1432
C1430
C1431
1uF
1uF
1uF
C1442
C1441
1uF
1uF
C1452
C1450
C1451
1uF
1uF
1uF
1uF
C1415
1uF
C1425
1uF
C1433
C1435
1uF
1uF
C1443
C1444
C1445
1uF
1uF
1uF
C1454
C1455
1uF
1uF
C1409
1uF
1uF
1uF
C1416
C1417
1uF
1uF
C1426
C1427
C1429
1uF
1uF
1uF
C1436
C1437
C1438
C1439
1uF
1uF
1uF
1uF
C1446
1uF
C1456
1uF
C1449
1uF
C1457
C1458
1uF
1uF
C1468
C1469
1uF
1uF
AA13
AA6
AB12
AC13
AE6
AJ6
AL13
AM12
AN13
AN6
AR14
AT13
AU14
AU6
AV13
AV16
AY14
AY17
BA18
BA6
BB19
BC11
BE6
BE9
BF8
BG7
BH13
BH9
F13
F17
F21
F25
F29
F33
F37
F41
F45
G47
H46
J45
J48
L43
M12
M14
M22
M32
N13
N16
N18
N21
N23
N31
N33
N36
N38
N48
P12
P14
P17
P19
P37
P40
T13
T18
T38
U14
U40
V13
V16
V41
W14
W42
U1O
PART 15 OF 18
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
P
VDDR1
O
VDDR1
W
VDDR1
E
R
VDDR1
VDDR1
VDDR1
VDDR1
F9
VDDR1
VDDR1
G7
VDDR1
VDDR1
VDDR1
VDDR1
J6
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
N6
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
U6
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
PITCAIRN
FB_VDDCI
FB_VSSCI
AA16
VDDCI
AA18
VDDCI
AA36
VDDCI
AA38
VDDCI
AA41
VDDCI
AB14
VDDCI
AB17
VDDCI
AB37
VDDCI
AB40
VDDCI
AB42
VDDCI
AC16
VDDCI
AC38
VDDCI
AC41
VDDCI
AD14
VDDCI
AF13
VDDCI
AG12
VDDCI
AG14
VDDCI
AH13
VDDCI
AK14
VDDCI
AL16
VDDCI
AM14
VDDCI
AM17
VDDCI
AN16
VDDCI
AR17
VDDCI
AT16
VDDCI
AT18
VDDCI
AT21
VDDCI
AU17
VDDCI
AU19
VDDCI
AU22
VDDCI
AV18
VDDCI
AV21
VDDCI
AV23
VDDCI
AY19
VDDCI
AY22
VDDCI
BA21
VDDCI
BA23
VDDCI
M27
VDDCI
N26
VDDCI
N28
VDDCI
P22
VDDCI
P24
VDDCI
P27
VDDCI
P30
VDDCI
P32
VDDCI
P35
VDDCI
T21
VDDCI
T23
VDDCI
T31
VDDCI
T33
VDDCI
T36
VDDCI
U19
VDDCI
U22
VDDCI
U32
VDDCI
U35
VDDCI
U37
VDDCI
V18
VDDCI
V21
VDDCI
V33
VDDCI
V36
VDDCI
V38
VDDCI
W17
VDDCI
W19
VDDCI
W35
VDDCI
W37
VDDCI
W40
VDDCI
VDDCI_SV
BB22
BB23
C1302
C1303
C1304
C1305
C1306
C1300
C1301
1uF
1uF
1uF
1uF
C1310
C1311
1uF
1uF
C1320
C1321
1uF
1uF
C1336
C1337
1uF
1uF
C1330
C1331
22uF
22uF
1uF
C1312
C1313
C1314
1uF
1uF
1uF
C1322
C1323
C1324
1uF
1uF
1uF
C1338
C1339
C1340
1uF
1uF
1uF
C1332
C1333
C1334
22uF
22uF
22uF
15
OUT
C1307
1uF
1uF
1uF
C1315
C1316
C1317
1uF
1uF
1uF
C1325
C1326
C1327
1uF
1uF
1uF
C1341
C1342
1uF
1uF
C1335
22uF
+VDDCI
DD
DD
DD
C1308
C1309
1uF
1uF
C1318
1uF
C1328
C1329
C
C
1uF
1uF
C
BB
BB
BB
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD POWER
TRINIDAD POWER
TRINIDAD POWER
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:23 2015
Thu Jan 15 02:26:23 2015
Thu Jan 15 02:26:23 2015
DATE:
DATE:
DATE:
12 23
12 23
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
12 23
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
OF
OF
OF
REV:
REV:
REV:
6
A
A
A
Page 13
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(13) TRINIDAD GROUND
A48
AA10
AA14
A A
C
C
C
B B
C C
A
A
A
D D
8
8
8
1
7
7
7
2
AA17
AA19
AA2
AA22
AA24
AA27
AA30
AA32
AA35
AA37
AA40
AA42
AA8
AB13
AB16
AB18
AB21
AB23
AB26
AB28
AB31
AB33
AB36
AB38
AB41
AB9
AC10
AC14
AC17
AC19
AC2
AC22
AC24
AC27
AC30
AC32
AC35
AC37
AC40
AC42
AC6
AD13
AD16
AD18
AD21
AD23
AD26
AD28
AD31
AD33
AD36
AD38
AD41
AE11
AE2
AE8
AF10
AF14
AF17
AF19
AF22
AF24
AF27
AF30
AF32
AF35
AF37
AF40
AG13
AG16
AG18
AG2
AG21
AG23
AG26
AG28
AG31
AG33
AG36
AG38
AG6
AH14
AH17
AH19
AH22
AH24
AH27
AH30
AH32
AH35
AH37
AH40
AH9
AJ11
AJ2
AJ7
AK13
AK16
AK18
AK21
AK23
AK26
AK28
AK31
AK33
AK36
AK38
AK41
AL14
AL17
AL19
AL2
AL22
AL24
AL27
AL30
AL32
AL35
AL37
AL40
AL6
AL9
U1P
PART 16 OF 18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G
N
VSS
D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PITCAIRN
AM13
VSS
AM16
VSS
AM21
VSS
AM23
VSS
AM26
VSS
AM28
VSS
AM31
VSS
AM33
VSS
AM36
VSS
AM38
VSS
AM41
VSS
AM8
VSS
AN12
VSS
AN14
VSS
AN17
VSS
AN2
VSS
AN22
VSS
AN24
VSS
AN27
VSS
AN30
VSS
AN32
VSS
AN35
VSS
AN37
VSS
AN40
VSS
AN9
VSS
AR13
VSS
AR16
VSS
AR2
VSS
AR21
VSS
AR23
VSS
AR26
VSS
AR28
VSS
AR31
VSS
AR33
VSS
AR36
VSS
AR38
VSS
AR41
VSS
AR6
VSS
AR8
VSS
AT10
VSS
AT14
VSS
AT17
VSS
AT19
VSS
AT22
VSS
AT24
VSS
AT27
VSS
AT30
VSS
AT32
VSS
AT35
VSS
AT37
VSS
AT40
VSS
AT6
VSS
AU13
VSS
AU16
VSS
AU18
VSS
AU2
VSS
AU21
VSS
AU23
VSS
AU26
VSS
AU28
VSS
AU31
VSS
AU33
VSS
AU36
VSS
AU38
VSS
AU41
VSS
AU50
VSS
AU52
VSS
AV11
VSS
AV14
VSS
AV17
VSS
AV19
VSS
AV22
VSS
AV24
VSS
AV27
VSS
AV30
VSS
AV32
VSS
AV35
VSS
AV37
VSS
AV40
VSS
AV43
VSS
AV46
VSS
AV8
VSS
AW2
VSS
AW50
VSS
AW52
VSS
AW6
VSS
AW9
VSS
AY10
VSS
AY13
VSS
AY16
VSS
AY18
VSS
AY21
VSS
AY23
VSS
AY26
VSS
AY28
VSS
AY31
VSS
AY33
VSS
AY36
VSS
AY38
VSS
AY41
VSS
AY48
VSS
AY49
VSS
B11
VSS
B13
VSS
B15
VSS
B17
VSS
B19
VSS
B21
VSS
B23
VSS
B25
VSS
B27
VSS
B29
VSS
B31
VSS
B33
VSS
B35
VSS
B37
VSS
B39
VSS
B41
VSS
B43
VSS
B45
VSS
B47
VSS
B7
VSS
B9
VSS
BA14
VSS
6
6
6
3
BA17
BA19
BA2
BA22
BA24
BA27
BA30
BA32
BA35
BA37
BA40
BA41
BB11
BB16
BB18
BB21
BB26
BB28
BB31
BB33
BB48
BB49
BB51
BB53
BB8
BC16
BC19
BC2
BC23
BC33
BC40
BC6
BD15
BD18
BD29
BD38
BE12
BE18
BE2
BE25
BE8
BF14
BF16
BF19
BF21
BF26
BF32
BF9
BG2
BG6
BH1
BH11
BH12
BH14
BH15
BH38
BH39
BH40
BH7
BL42
BL16
BK15
BM11
BM13
BM7
BM9
BN42
BN16
F10
F11
F14
F15
F18
F19
F23
F27
F31
F35
F36
F39
F43
F47
G2
G29
G48
G52
G6
H12
H16
H21
H25
H32
H35
H38
H42
H45
J14
J18
J22
J28
J31
J33
J39
J46
J52
K15
K19
K21
K23
K26
K36
K40
L16
L25
L29
L38
U1Q
PART 17 OF 18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G
N
VSS
D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H9
VSS
VSS
VSS
J2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K6
VSS
VSS
L2
VSS
VSS
VSS
VSS
PITCAIRN
5
5
5
4
L42
VSS
L48
VSS
L52
VSS
L6
VSS
M13
VSS
M16
VSS
M33
VSS
M45
VSS
M48
VSS
M8
VSS
N12
VSS
N14
VSS
N17
VSS
N19
VSS
N2
VSS
N22
VSS
N24
VSS
N27
VSS
N30
VSS
N32
VSS
N35
VSS
N37
VSS
N40
VSS
N52
VSS
P13
VSS
P16
VSS
P18
VSS
P21
VSS
P23
VSS
P26
VSS
P28
VSS
P31
VSS
P33
VSS
P36
VSS
P38
VSS
P41
VSS
P46
VSS
P48
VSS
P6
VSS
P9
VSS
R10
VSS
R2
VSS
R44
VSS
R48
VSS
R50
VSS
R6
VSS
T11
VSS
T12
VSS
T14
VSS
T17
VSS
T19
VSS
T22
VSS
T24
VSS
T27
VSS
T30
VSS
T32
VSS
T35
VSS
T37
VSS
T40
VSS
T42
VSS
T43
VSS
T46
VSS
T53
VSS
T8
VSS
U13
VSS
U16
VSS
U18
VSS
U2
VSS
U21
VSS
U23
VSS
U26
VSS
U28
VSS
U31
VSS
U33
VSS
U36
VSS
U38
VSS
U41
VSS
V14
VSS
V17
VSS
V19
VSS
V22
VSS
V24
VSS
V27
VSS
V30
VSS
V32
VSS
V35
VSS
V37
VSS
V40
VSS
V42
VSS
V44
VSS
V6
VSS
V9
VSS
W10
VSS
W13
VSS
W16
VSS
W18
VSS
W2
VSS
W21
VSS
W23
VSS
W26
VSS
W28
VSS
W31
VSS
W33
VSS
W36
VSS
W38
VSS
W41
VSS
W48
VSS
W6
VSS
A4
VSS
A50
VSS
BK1
VSS
BK53
VSS
BL3
VSS
BL51
VSS
BN4
VSS
BN50
VSS
C3
VSS
C51
VSS
D1
VSS
D53
VSS
V53
VSS
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD GND
TRINIDAD GND
TRINIDAD GND
SHEET:
SHEET:
SHEET:
Wed Jul 30 07:10:46 2014 1.0
Wed Jul 30 07:10:46 2014 1.0
Wed Jul 30 07:10:46 2014 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
13 23
13 23
13 23
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
REV:
REV:
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
DD
DD
DD
C
C
C
BB
BB
BB
A
A
A
Page 14
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
14
14
14
14
14
14
14
14
+12V_BUS_SOURCE1
NR601
10K
1%
567
Q603
R603
UNNAMED_26_MOSN2D3STH_I263_G4 UNNAMED_26_MOSN2D3STH_I264_G4
1 2
4
5%0R
NTMFS4C05N
MR603
10K
1%
123
OUT
IN
C632
0.1uF
6.3V
DNI
TR601
1K
1%
VDDC_VFB
TR602
UGATE1_CTR
14
LGATE1_CTR
14
19
19
1K 1%
567
Q602
UNNAMED_26_MOSN2D3STH_I247_G4
4
5%
NTMFS4C10N
R602
123
0R
1 2
567
Q604
4
NTMFS4C05N
5%
123
R604
0R
1 2
+12V_BUS_SOURCE1
PWM4
14
PWM4_EN
TR634
14
NCP5901BMNTBG
4
4
4
5
R609
2.2R
5%
UNNAMED_26_CAP_I164_A
C609
0.0022uF
50V
CSP1
14
CSN1
14
NR634
2.2R
5%
UNNAMED_26_CAP_I148_A
C654
1uF
16V
U602
4
DRVH
VCC
2
PWM
3
UNNAMED_26_CAP_I136_A
EN
5%2.2R
TC634
0.1uF
16V
GND
6
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
UGATE2_CTR
14
+VDDC
L601
0.22uH
1 2
12
NS601
NS602
UNNAMED_26_NETSHORT_I248_N2
R605
10K
C605
1%
CSP1
50V0.1uF
R606
1 2
100K 1%
D604
BAT54KFILM
12
UNNAMED_26_CAP_I137_A
NR620
2.2R
5%
8
1
BST
7
SW
5
DRVL
9
TH
UGATE4_CTR
C655
0.22uF
PHASE4
25V
PHASE4
LGATE4_CTR
VDDC
VDDC
VDDC
Wed Jul 30 07:10:42 2014 1.0
Wed Jul 30 07:10:42 2014 1.0
Wed Jul 30 07:10:42 2014 1.0
14 23
14 23
14 23
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
PHASE2
12
14
LGATE2_CTR
14
CSN1
C606
0.1uF
16V
UGATE3_CTR
14
PHASE3
14
LGATE3_CTR
14
UGATE4_CTR
14
PHASE4
14
14
LGATE4_CTR
14
14
14
OF
OF
OF
6
+12V_EXT_A_SOURCE1
NR611
10K
1%
567
Q613
R613
UNNAMED_26_MOSN2D3STH_I253_G4 UNNAMED_26_MOSN2D3STH_I254_G4
1 2
4
0R 5%
NTMFS4C05N
MR613
10K
1%
NR621
10K
1%
1 2
0R 5%
MR623
10K
1%
NR631
10K
1%
1 2
0R 5%
NR633
10K
1%
123
+12V_EXT_A_SOURCE1
567
Q623
R623
UNNAMED_26_MOSN2D3STH_I189_G4 UNNAMED_26_MOSN2D3STH_I192_G4
4
NTMFS4C05N
123
+12V_BUS_SOURCE1
567
Q633
R633
UNNAMED_26_MOSN2D3STH_I183_G4 UNNAMED_26_MOSN2D3STH_I184_G4
4
NTMFS4C05N
123
REV:
REV:
REV:
567
Q612
UNNAMED_26_MOSN2D3STH_I256_G4
4
5%
NTMFS4C10N
R612
123
0R
UGATE2_CTR
1 2
14
567
Q614
4
NTMFS4C05N
5%
123
R614
0R
LGATE2_CTR
1 2
14
567
Q622
UNNAMED_26_MOSN2D3STH_I203_G4
4
5%
NTMFS4C10N
R622
123
0R
UGATE3_CTR
1 2
14
567
Q624
4
NTMFS4C05N
5%
123
R624
0R
LGATE3_CTR
1 2
14
567
Q632
UNNAMED_26_MOSN2D3STH_I186_G4
4
5%
NTMFS4C10N
R632
123
0R
UGATE4_CTR
1 2
14
567
Q634
4
NTMFS4C05N
5%
123
R634
0R
LGATE4_CTR
1 2
14
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
NS611
R619
2.2R
5%
C619
0.0022uF
50V
CSP2
14
CSN2
14
NS621
R629
2.2R
5%
C629
0.0022uF
50V
CSP3
14
CSN3
14
NS631
R639
2.2R
5%
UNNAMED_26_CAP_I178_AUNNAMED_26_CAP_I198_AUNNAMED_26_CAP_I212_A
C639
0.0022uF
50V
CSP4
14
CSN4
14
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
L611 0.22uH
1 2
12
UNNAMED_26_NETSHORT_I259_N2
R615
10K
1%
0.1uF 50V
1 2
100K 1%
L621
0.22uH
1 2
12
R625
10K
1%
R626
1 2
100K 1%
L631 0.22uH
1 2
12
UNNAMED_26_NETSHORT_I195_N2UNNAMED_26_NETSHORT_I209_N2
R635
10K
1%
CSP4
1 2
100K 1%
1
1
1
+VDDC
DD
DD
DD
12
NS612
C615
CSN2
CSP2
C616
0.1uF
16V
R616
C
C
C
+VDDC
12
NS622
C625
CSN3
CSP3
50V0.1uF
C626
0.1uF
16V
BB
BB
BB
+VDDC
12
NS632
C635
CSN4
50V0.1uF
C636
0.1uF
16V
R636
A
A
A
8
+VDDC
12
12
12
12
+
C676
820uF
2.5V
+
+
C678
C677
820uF
820uF
2.5V
2.5V
12
12
+
+
C679
C680
820uF
820uF
2.5V
2.5V
12
+
+
C681
C682
820uF
820uF
2.5V
2.5V
12
12
+
C683
820uF
2.5V
12
+
+
TC682
TC683
330uF
330uF
2.5V
2.5V
A A
+VDDC
C684
22uF
4V
C693
C694
22uF
22uF
4V
4V
MC642
MC643
22uF
22uF
4V
4V
MC651
MC652
22uF
22uF
4V
4V
+12V_BUS_SOURCE1
C692
22uF
4V
C695
C696
C697
C698
C699
22uF
22uF
22uF
4V
MC644
22uF
4V
MC653
22uF
4V
22uF
4V
4V
4V
MC645
MC646
MC647
22uF
22uF
22uF
4V
4V
4V
MC654
22uF
4V
MC641
22uF
22uF
4V
4V
MC648
22uF
4V
C660
10uF
16V
+12V_EXT_A_SOURCE1
C668
10uF
16V
phase4
MC670
C
C
C
B B
C C
BOOST3
14
PHASE3
14
BOOST2
14
PHASE2
14
A
A
A
D D
BOOST1
14
PHASE1
14
0.015uF
10V
High Frequency Decoupling - Place Last
+12V_BUS
D601
BAT54KFILM
1 2
R659
1 2
UNNAMED_26_CAP_I58_A
5%2.2R
C651
0.22uF
25V
+12V_BUS
D602
BAT54KFILM
1 2
R660
1 2
UNNAMED_26_CAP_I12_A
2.2R 5%
C652
0.22uF
25V
+12V_BUS
D603
BAT54KFILM
1 2
R661
1 2
UNNAMED_26_CAP_I9_A
5%2.2R
C653
0.22uF
25V
8
8
8
1
14
14
14
1 2
1K 5%
R643
1%15K
C641
0.1uF 6.3V
7
7
7
2
R640
C640
0.1uF 6.3V
C644
0.1uF
10V
UNNAMED_26_CAP_I73_B
IMON
R644
1 2
1 2
1 2
1K 1%
LGATE3_CTR
1%13K
1 2
R646
R647
10
11
12
R645
VDDC_FBB
5%47R
+3.3V_BUS
GPIO_0_VDDC_VID0
7,19
IN
GPIO_15_VDDC_VID1
7,19
IN
GPIO_20_VDDC_VID2
7,19
IN
GPIO_14_VDDC_VID3
7,19
IN
GPIO_12_VDDC_VID4
7,19
IN
GPIO_13_VDDC_VID5
7,19
IN
GPIO_29_VDDC_VID6
7,19
IN
GPIO_30_VDDC_VID7
7,19
IN
+5V
R642
1 2
1K 5%
VDDC_VSEN
12,14
IN
VDDC_VRTN
12
IN
R699
1 2
TR603
0R
5%
1 2
1 2
1%1K
C643
0.1uF
10V
14
BOOST3
PHASE3
PWM4_EN
UGATE3_CTR
46
47
48
TG3
BST3
SWN3
1
BG3
2
PSI
3
VID0
4
VID1
5
VID2
6
VID3
7
VID4
8
VID5
9
VID6
VID7/AMD
UNNAMED_26_NCP5395T_I103_ROSC UNNAMED_26_NCP5901B_I157_BST
ROSC
UNNAMED_26_NCP5395T_I103_ILIM
ILIM
IMON14VSP15VSN16DIFFOUT17COMP18VFB19VDRP20VDFB21CSSUM22DAC2312VMON24VCC
UNNAMED_26_NCP5395T_I103_IMON
13
1%100K
C642
0.01uF
50V
C645
R648
UNNAMED_26_CAP_I38_A UNNAMED_26_CAP_I41_A UNNAMED_26_CAP_I43_AUNNAMED_26_CAP_I43_B
1 2
5%3.3K
25V560pF
MC601
UNNAMED_26_CAP_I34_B
0.0018uF 50V
R650
47K
1 2
C661
10uF
16V
C669
10uF
16V
14
45
DRVON
UNNAMED_26
BOOST2
44
BST2
14
C646
UNNAMED_26_RES_I36_A
1 2
UNNAMED_26_RES_I35_A
1 2
1K 1%
+12V_BUS_SOURCE1
12
+
C662
C663
10uF
10uF
16V
16V
C670
10uF
16V
14
1 2
C631
1uF
16V
14
14
14
14
PHASE1
PHASE2
VCCP
14
LGATE2_CTR
UGATE2_CTR
40
41
42
43
BG2
TG2
VCCP
SWN2
U601
NCP5395TMNR2G
UNNAMED_26_NCP5395T_I103_CSSUM
VDDC_VFB
R653
1K
PR621
1%
1K
1%
C647
50V47pF
50V22pF
R652
1 2
1K 1%
R649
1%1K
R651
6
6
6
3
+12V_EXT_A_SOURCE1
12
C656
270uF
16V
+
+12V_EXT_A_SOURCE1
C665
C664
10uF
10uF
16V
16V
phase3
+12V_BUS_SOURCE1
C673
C672
10uF
10uF
16V
16V
phase1
+12V_BUS
R698
2.2R
5%
14
14
14
BOOST1
UGATE1_CTR
37
38
39
57
TG1
BST1
SWN1
AGND58AGND59AGND60AGND61AGND62AGND63AGND64AGND
AGND50AGND51AGND52AGND53AGND54AGND55AGND56AGND
UNNAMED_26_CAP_I46_A UNNAMED_26_CAP_I46_B
49
C648
0.0047uF
50V
R654
1K
1%
UNNAMED_26_CAP_I48_A
1 2
UNNAMED_26_CAP_I53_A
2.2R 5%
C650
1uF
16V
C649
1uF
R657
16V
1.2K
5%
C657
270uF
16V
R655
R656
+12V_EXT_A_SOURCE1
12
+
C658
270uF
16V
UGATE1_CTR
14
PHASE1
14
C666
10uF
16V
C674
10uF
16V
36
BG1
35
G4
34
VR_RDY
33
EN
32
CS1N
31
CS1P
30
CS2N
29
CS2P
28
CS3N
27
CS3P
26
CS4N
25
CS4P
+5V
+12V_EXT_A_SOURCE1
1%10K
C667
10uF
16V
C675
10uF
16V
14
14
PWM4
LGATE1_CTR
PWM4
LGATE1_CTR
14
R658
1K
1%
VDDC_POK
VDDC_EN
CSN1
CSP1
CSN2
CSP2
CSN3
CSP3
CSN4
CSP4
1%1K
DNI
TR655
+VDDC +5V
5%
TR604
0R
1 2
VDDC_VSEN
12 14 14
5
5
5
4
Page 15
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(15) VDDCI
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
+VDDCI_SOURCE
A A
567
NTMFS4C05N
R805
0R 5%
+PW_VDDCI_LGATE
R814
0R 5%
share pad of R714,R709
NTMFS4C10N
567
Q803
UNNAMED_15_MOSN2D3STH_I15_G4
4
123
1
BOOT
2
UGATE
UNNAMED_15_GS7253_I11_OCSET
3
OCSET
4
LGATE5VCC
10
GND
9
GND
+VDDCI_COMP
C2
0.1uF
+VDDCI_FB
Q801
UNNAMED_15_MOSN2D3STH_I42_G4
4
U801
GS7256-ASO
123
COMP/EN
PHASE
FB
GND
GND
+PW_VDDCI_UGATE
15
+PW_VDDCI_PHASE
15
+PW_VDDCI_LGATE
C
C
C
B B
15
C C
R821
COMPENSATION CIRCUIT
402
5%0R
R822
5%0R
+VDDCI_B
15
+PW_VDDCI_UGATE
15
1 2
R815
1 2
3.48K 1%
+PW_VDDCI_LGATE
15
+VDDCI_COMP
C811
0.01uF
10V
UNNAMED_15_CAP_I4_B
C812
15pF
50V
R812
34K
1%
UNNAMED_15_CAP_I5_B
R809
0R
5%
L801
1.0uH
Input Bulk CAPs
R811
10K
1%
Place R1 and R4 close to
PWM and routed with
separate 20mil trace to
the ASIC
BOOT CIRCUIT
12
+
C831
270uF
16V
12
Sense Point
NS800
UNNAMED_15_NETSHORT_I50_N2
R800
603
0R
5%
C813
560pF
25V
UNNAMED_15_CAP_I32_B
R813
0R
5%
+VDDCI_B
+PW_VDDCI_PHASE
15
15
+VDDCI_B
R816
0R
5%
UNNAMED_15_CAP_I21_A
C805
0.1uF
C823
C824
C829
0.1uF
0.015uF
VDDCI_SV
C830
22uF
22uF
4V
4V
0805 6.3V0805 6.3V402402
IN
12
12
+
C825
820uF
2.5V
6.3 x 9 mm, TH
Output Bulk CAPsOutput MLCC
8
7
6
12
11
15 19
19 15
C818
0.15uF
603
+PW_VDDCI_PHASE
+VDDCI_COMP
+VDDCI_FB
+VDDCI_VCC
C803
0.22uF
FILTERED SMPS VCC
+VDDCI_VCC
15
C820
10uF
R819
2.2R
5%
UNNAMED_15_CAP_I28_B
C808
1uF
Place Rs and Cs across QL
15
19 15
15
+VDDCI_FB
19,15
OUT
+12V_BUS
R807
2.2R
5%
C807
0.1uF
C821
10uF
12061206
1 2
19,15
DD
DD
DD
+VDDCI
12
+
C3
820uF
2.5V
C
C
C
BB
BB
BB
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
VDDCI
VDDCI
VDDCI
SHEET:
SHEET:
SHEET:
Wed Jul 30 07:10:40 2014
Wed Jul 30 07:10:40 2014
Wed Jul 30 07:10:40 2014
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
105_C634xx_00B
105_C634xx_00B
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
105_C634xx_00B
3
3
3
OF
OF
OF
REV:
REV:
REV:
2315
2315
2315
6
A
A
A
Page 16
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(16) MVDD
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
+12V_BUS_SOURCE1
+MVDD_SOURCE
+12V_BUS_SOURCE1
DD
DD
DD
L701
Input Bulk CAPs
1uH
19,16
Place R1 and R4 close to
PWM and routed with
separate 20mil trace to
the ASIC
BOOT CIRCUIT
12
+
C731
270uF
16V
+MVDD
12
12
+
C723
C724
C729
0.1uF
0.015uF
402 402
NS703
UNNAMED_16_NETSHORT_I37_N1
1 2
Output MLCC
+MVDD
NS_VIA
603
5%
UNNAMED_16_CAP_I34_A
C713
560pF
25V
UNNAMED_16_CAP_I34_B
R711
R713
10K
0R
1%
5%
+MVDD_B
+MVDD_B
R716
0R
5%
UNNAMED_16_CAP_I16_A
C705
0.1uF
+PW_MVDD_PHASE
R700 0R
16
16
22uF
4V
0805 6.3V 0805 6.3V
C730
22uF
4V
C725
820uF
2.5V
6.3 x 9 mm, TH
Output Bulk CAPs
+
C726
820uF
2.5V
C
C
C
BB
BB
BB
C718
0.15uF
603
567
Q701
UNNAMED_16_MOSN2D3STH_I52_G4
4
NTMFS4C10N
123
16
+PW_MVDD_UGATE
16
+PW_MVDD_PHASE
R721
402
5%0R
R715
C712
15pF
50V
R705
1 2
1%3.48K
5%0R
R714
+PW_MVDD_LGATE
567
Q703
UNNAMED_16_MOSN2D3STH_I24_G4
4
NTMFS4C05N
123
U701
1
2
3
4
10
9
BOOT
UGATE
UNNAMED_16_GS7253_I22_OCSET
OCSET
LGATE5VCC
GND
GND
GS7256-ASO
+MVDD_COMP
TC712
0.1uF
COMP/EN
8
PHASE
7
6
FB
12
GND
11
GND
19 16
+MVDD_FB
5%0R
16 19
+MVDD_FB
+MVDD_VCC
C703
0.22uF
16
+PW_MVDD_PHASE
+MVDD_COMP
+MVDD_VCC
C
C
C
B B
C C
16
+PW_MVDD_LGATE
R722
0R 5%
+MVDD_B
16 16
+PW_MVDD_UGATE
16
1 2
+PW_MVDD_LGATE
16
COMPENSATION CIRCUIT FILTERED SMPS VCC
+MVDD_COMP
C711
0.01uF
10V
UNNAMED_16_CAP_I2_B
R712
34K
1%
UNNAMED_16_CAP_I7_B
R709
0R
5%
16
19
16
R719
2.2R
5%
UNNAMED_16_CAP_I29_B
C708
1uF
Place Rs and Cs across QL
19,16
+12V_BUS
R707
2.2R
5%
C707
0.1uF
C720
10uF
1206 1206
OUT
C721
10uF
1 2
+MVDD_FB
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
A
A
A
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
MVDD
MVDD
MVDD
SHEET:
SHEET:
SHEET:
Wed Jul 30 07:10:42 2014 1.0
Wed Jul 30 07:10:42 2014 1.0
Wed Jul 30 07:10:42 2014 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
16 23
16 23
16 23
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
REV:
REV:
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
Page 17
(17) 0.95V
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
1
8
8
8
2
7
7
7
3
6
6
6
4
54332
54332
54332
5
6
7
8
1
1
1
A A
D D
D D
D D
+5V
C931
C943
1uF
0.1uF
16V
16V
DNI
R944
10K
5%
C
C
C
B B
19
B B
B B
B B
C C
0.95V_EN
IN
R902
10K
5%
+0.95V_VIN
C939
C914
C902
10uF
16V
C903
10uF
1uF
0.1uF
16V
16V
16V
+3.3V_BUS
R900
10K
5%
C900
UNNAMED_25_APW8713_I28_BOOT
POK
EN
PFM
AGND
FB
TON
20
21
22
23
SS
VIN
LDO
BOOT
LDOIN8VIN9VIN10LX11LX
7
0.1uF 25V
18LX19
PGND
17
LX
16
LX
15
PGND
14
PGND
13
PGND
12
PGND
UNNAMED_25_APW8713_I28_LX
UNNAMED_25_APW8713_I28_SS
C909
0.01uF
R904
100K
APW8713QB
U900
1
2
UNNAMED_25_APW8713_I28_PFM
3
4
5
UNNAMED_25_APW8713_I28_TON
6
1%
0.95V_PGOOD
1 2
L900
1 2
ML900
1 2
DNI
R901
1%68.1K
TC901
DNI
UNNAMED_25_CAP_I21_B
470pF
50V
19
OUT
2.2uH
C938
C915
C916
C917
C918
C910
C911
C912
0.1uF
22uF
22uF
22uF
22uF
2.2uH
C901
DNI
50V0.0033uF
22uF
+0.95V_REG_FB
C919
22uF
22uF
22uF
NS900
R903
1 2
0.1%1K
19
IN
+0.95V
C
C
C
1 2
UNNAMED_25_NETSHORT_I39_N1
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
214
214
214
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
A
A
A
8
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
A
A
A
D D
8
8
8
1
7
7
7
2
6
6
6
3
5
5
5
4
5
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
0.95V REG
0.95V REG
0.95V REG
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:32:13 2015
Thu Jan 15 02:32:13 2015
Thu Jan 15 02:32:13 2015
DATE:
DATE:
DATE:
17 23
17 23
NOTE
NOTE
NOTE
17 23
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
NOTES:
NOTES:
NOTES:
OF
OF
OF
REV:
REV:
REV:
6
Page 18
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(18) SMALL RAIL REGULATORS
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
VIN = 3.0V TO 3.6V MAX
LDO #1:
PCB: 50 TO 70mm SQ. COPPER AREA FOR COOLING
+3.3V_BUS
1.8V_POK
18 19
R307 1%1.8R
R306 1.8R 1%
R305 1%1.8R
R304 1.8R 1%
Use 3x1.8R
1206 1/2W
0.5A per R
1.8V_POK
18,19
OUT
1.8V_EN
19,1,18
IN
C312
0.1uF
6.3V
C
C
C
B B
DNI
1.8V_EN
19 1 18
LDO1_VIN
18 18
+5V
18
+5V
LDO1_VIN
18 18
+5V
18
C305
C306
10uF
1uF
6.3V
10V
MU300
1
POK
2
EN
3
VIN
4
CNTL5NC
UP0104PDC8
OVERLAP U300 AND MU300
1
POK
2
EN
3
VIN
4
VDD5NC
GS7103-A
VOUT = +1.8V +/- 2%
8
GND
LDO1_FB
7
FB
+1.8V
6
VOUT
9
GND
U300
8
GND
LDO1_FB
18
7
FB
+1.8V
6
VOUT
9
THMPAD
C C
IOUT = 1.3A RMS MAX
+12V_EXT_A +12V_BUS
MR401
0R
5%
18
R302
C304
12.7K
33pF
1%
50V
R5
R301
10K
1%
R4
VOUT = Vref x (1 + R5/R4)
+1.8V
C301
C300
C303
10uF
10uF
0.1uF
6.3V
6.3V
6.3V
UNNAMED_19_CAP_I71_A
REGULATOR FOR +5V RAILS
IOUT MAX = 150mA
R401
0R
MC78M05CDT
5%
REG1
1
IN
GND
TAB
C400
1uF
2
4
16V
MREG1
3
IN
ADJ
1
Pin out: 1-G/ADJ, 2-O,3-I
TAB
4
SPX1117M3
DD
DD
DD
+5V +5V_VESA
3
OUT
C425
1uF
16V
2
OUT
F400
1 2
200mA
24V
C426
10uF
6.3V
C401
1uF
6.3V
C
C
C
BB
BB
BB
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
A
A
A
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SMALL RAIL REGULATORS
SMALL RAIL REGULATORS
SMALL RAIL REGULATORS
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:23 2015 1.0
Thu Jan 15 02:26:23 2015 1.0
Thu Jan 15 02:26:23 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
18 23
18 23
18 23
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
REV:
REV:
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
Page 19
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(19) POWER MANAGEMENT
A A
+12V_EXT_A
J1000
1
+12V
2
+12V
3
+12V
4
GND
6
GND
5
Sense
POWER_HEADER
C
C
C
B B
C C
VDDC VOLTAGE CONTROL
+3.3V_BUS
R4107
10K
5%
7,14,19
OUT
7,14,19
OUT
7,14,19
OUT
7,14,19
OUT
7,14,19
OUT
7,14,19
OUT
7,14,19
A
A
A
D D
OUT
R4114
10K
5%
8
8
8
1
C1004
47pF
50V
C1003
10uF
16V
R4108
R4109
R4110
10K
5%
R4115
10K
5%
R4111
10K
10K
10K
5%
5%
5%
R4116
R4117
R4118
10K
10K
10K
5%
5%
5%
7,14,19
OUT
2
7
7
7
3
6
6
6
4
5
6
345
345
345
optinal
BUS 12V and AUX A POWER UP SEQ
+12V_BUS
R1002
11.3K
+3.3V_BUS
1%
R1004
1K
1%
+12V_EXT_A
12V_BUS_UP
R1030
11.3K
1%
12V_EXTA_UP
R1040
1K
1%
R1019
2.32K
1%
0.3vddc
R1020
1K
1%
CTF_OUT
20
IN
7 19 14
7 19 14
7 19 14
7 19 14
7 19 14
7 19 14
7 19 14
R4113
R4112
10K
10K
5%
5%
R4119
10K
5%
0.1uF
10V
R4120
10K
5%
7
7
7
2
R221 5%2.2K
GPIO_0_VDDC_VID0
GPIO_30_VDDC_VID7
GPIO_29_VDDC_VID6
GPIO_13_VDDC_VID5
GPIO_12_VDDC_VID4
GPIO_14_VDDC_VID3
GPIO_20_VDDC_VID2
GPIO_15_VDDC_VID1
MC1255
MC1248
0.1uF
10V
+3.3V_BUS
R4127
10K
5%
R4128
10K
5%
3.3V_BUS_UP
+3.3V_BUS
R1031
5.11K
1%
6
2
Q1010A
MMDT3904-7
1
N32204028 N32204141
3
5
Q1010B
MMDT3904-7
4
+12V_BUS
R1042
10K
1%
6
2
Q1009A
MMDT3904-7
1
6
UNNAMED_17_NPN_I411_B
2
Q210A
MMDT3904-7
PLACE CLOSE
1
TO ITS CTLR
7 19 14
MC1249
MC1250
MC1251
0.1uF
10V
GPIO_30_VDDC_VID7
GPIO_29_VDDC_VID6
GPIO_13_VDDC_VID5
GPIO_12_VDDC_VID4
GPIO_14_VDDC_VID3
GPIO_20_VDDC_VID2
GPIO_15_VDDC_VID1
GPIO_0_VDDC_VID0
MC1252
0.1uF
10V
0.1uF
0.1uF
10V
10V
3
N36200648
5
Q210B
MMDT3904-7
C1009
4
0.1uF
PLACE CLOSE
16V
TO ITS CTLR
3
5
Q1009B
MMDT3904-7
PLACE CLOSE
C1010
4
0.1uF
TO ITS CTLR
16V
MR223 5%0R
MC1253
0.1uF
10V
IN
IN
IN
IN
IN
IN
IN
DNI
INTERNAL CTF LATCH - 1.8V VDDCT REQUIRED
15
OUT
MC1254
0.1uF
10V
MVDD VOLTAGE
RESISTOR TO SET
+MVDD OUTPUT VOLTAGE
IN
VOUT = VREF * (1+RFB1/RFB2)
6
6
6
3
+3.3V_BUS
R1008
10K
1%
R1108
10K
1%
+VDDCI_FB
R4085
10K
5%
VDDCI_FB_VID1
1
R810
10K
2 3
5%
+MVDD_FB
OUT
RFB2
R710
7.15K
1%
1.8V_EN
VDDCI VOLTAGE CONTROL
Q4085
2N7002E
16
5
5
5
NAND
2V
0.7VDDC
OUT
BUS RAILS (3.3V/12V UP) -> +1.8V -> 0.935V
GPIO_11_PWRCNTL_3
17
IN
4
1,18
POWER UP SEQUENCE
19
18
0.95V_PGOOD
17
18
19
+0.95V_REG_FB
0.8V
1.8V_POK
1.8V_POK
+12V_BUS
+3.3V_BUS
+1.8V: >1.4V
+0.935V:>2.5V
+VDDC: >0.7V
+VDDCI: FLOAT
+MVDD: 2.0V
IN
R950
17.4K
1%
BIF_VDDC
VDDC -> VDDCI
MVDD
optinal
R1111 5%0R
R1222 0R 5%
MR1333 5%0R
+VDDC SOURCE
7
R450 0R 5%
MR450 0R 5%
MR451 5%0R
4
4
4
+0.95V_VIN
5
VDDC_EN
0.95V_EN
VDDC_EN
18,19
IN
14
IN
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
+3.3V_BUS
R1006
10K
19 17
19 14
5%
R1007 5%5.1K
14 19
+3.3V_BUS
R1627
2.2K
5%
R1693 5%20K
1.8V_POK
VDDC_POK
+12V_BUS INPUT
+12V_BUS
L1080 0.47uH
Irms=7A Idc=9.5A
+12V_EXT_A
L1083 0.47uH
+12V_BUS_SOURCE1
DUAL
FOOTPRINT
PHASE-1
1 2
R1093 0R 5%
R1095 5%0R
1 2
POWER MANAGEMENT
POWER MANAGEMENT
POWER MANAGEMENT
Wed Jul 30 07:14:28 2014 1.0
Wed Jul 30 07:14:28 2014 1.0
Wed Jul 30 07:14:28 2014 1.0
PHASE-4
TH
TOROID
+VDDCI_SOURCE
VDDCI
19 23
19 23
19 23
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
N54311143
UNNAMED_17_CAP_I206_A
C1011
1uF
6.3V
C1632
1uF
6.3V
+VDDCI_SOURCE
+12V_BUS
R1009
10K
5%
UNNAMED_17_NPN_I408_C
6
2
Q1013A
MMDT3904-7
1
+12V_BUS
R1635
10K
5%
UNNAMED_17_NPN_I451_C
1
Q1604
MMBT3904
2 3
+12V_EXT_A INPUT
+12V_EXT_A
+12V_BUS_SOURCE1
REV:
REV:
REV:
2
2
2
R1010 5.1K
5%
R1012 5%5.1K
PX_EN
2,20
IN
IN BACO MODE
TURN OFF
VDDC, VDDCI AND MVDD
R1611 5%5.1K
R1652 5%5.1K
+12V_EXT_A_SOURCE1
DUAL
FOOTPRINT
R1098 0R 5%
R1099 5%0R
L1082
1 2
0.47uH
+MVDD_SOURCE
R1091 5%0R
R1092 0R 5%
MVDD OPTIONAL1
+MVDD_SOURCE
MR1091 0R 5%
MR1092 5%0R
MVDD OPTIONAL2
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
C
C
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
UNNAMED_17_CAP_I385_A
7
UNNAMED_17_NPN_I409_B
5
2
C1012
1uF
6.3V
UNNAMED_17_NPN_I441_B
1
UNNAMED_17_NPN_I452_B
1
2014
2014
2014
3
Q1013B
MMDT3904-7
4
6
Q1016A
MMDT3904-7
1
R1014 1%10K
Q1605
MMBT3904
2 3
Q1606
MMBT3904
2 3
PHASE-23
+MVDD_SOURCE
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
+3.3V_BUS
R1023
10K
5%
0.95V_EN
C1111
1uF
6.3V
+3.3V_BUS
R1013
10K
5%
VDDC_EN
3
UNNAMED_17_NPN_I407_B
5
Q1016B
MMDT3904-7
4
R1015
10K
1%
DNI
+MVDD_COMP
+VDDCI_COMP
12
+
C1090
22uF
16V
Trinidad XT/PRO GD517ci203
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
8
1
1
1
17,19
OUT
DD
DD
DD
14,19
OUT
C
C
C
16
OUT
15
OUT
BB
BB
BB
A
A
A
1
1
1
8
Page 20
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
9
9
9
2
8
8
8
3
7 465 123
7 465 123
7 465 123
4
5
6
7
8
E
E
E
A A
5
CTF_BACO
12V_FAN
UNNAMED_20_MOSP_I156_G
1
MMDT3904-7
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
+12V_BUS +12V_EXT_A
NR200
0R
5%
23
Q252
AO3415L
R2645%2.2K
12
HEADER IS 2MM
IT DOES NOT FOLLOW
2.54MM SPACING AS 4-PIN
PWM FAN SPECIFICATION
12
B200
MR200
MB200
220R
220R
0R
5%
OVERLAP
MC209
10uF
R253
16V
0R
0805
5%
DNI
CTF_OUT
20 19
J200
4
3
2
1
HEADER_1X4_SHROUDED
FM1
SW_FB
1
FM2
SW_FB
1
FM3
SW_FB
1
FM4
SW_FB
1
Trinidad XT/PRO GD517ci203
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
D
D
D
C
C
C
B
B
FM5
SW_FB
1
FM6
SW_FB
1
1
1
1
8
B
A
A
A
(20) MECHANICAL AND THERMAL MANAGEMENT
U1R
+1.8V
1 2
B202
120R
D
D
D
+TSVDD
C200
C213
1uF
0.1uF
6.3V
6.3V
B B
C
C
C
CRITICAL TEMPERATURE FAULT
IF CRITICAL TEMPERATURE IS REACHED THIS WILL FORCE THE FAN TO RUN AT FULL
SPEED WHILE POWER IS REMOVED
THIS IS AN OPEN COLLECTOR SIGNAL. ACTIVE LEVEL IS HARD PULL DOWN TO GROUND.
GPIO_19_CTF
PERSTB_BUF
R236 4.7K 5%
D200
1 2
BAT54KFILM
7
C C
B
B
B
IN
1,2,20
IN
HEATSINKS
MT202
SHROUD HOLE
1
8
1
NA
23456
7
23456
CYPRESS_PRO_HEATSINK
HS2A
D D
A
A
A
7120E87000G
Barts Pro Channel Fansink
9
9
9
1
1234567
8
CYPRESS_PRO_HEATSINK
HS2B
9
1011121314
16
17
15
CYPRESS_PRO_HEATSINK
HS2C
1819202122
23
PART 18 OF 18
AY53
TSVDD
AY51
TSVSS
BC43
NC_TSVSSQ
T
S
S
F
D
R239 47K 5%
MT203
NA
7
CYPRESS_PRO_HEATSINK
HS2D
2627282930
1
8
21
23456
31
O
PITCAIRN
IN
MT204
NA
7
32
SHROUD HOLE
UNNAMED_20_RES_I10_A
24
25
2
W47
DPLUS
W46
DMINUS
AA46
TS_FDO
+3.3V_BUS
CTF_THERM
CTF_TRIP
R214
100K
5%
R222 5%0R
CTF BYPASS
MT205
8
1
NA
23456
Curacao_fansinks
7123B00100G
1234567
GPIO_28_TS_FDO
7
23
7
HS1A
GPU_DPLUS
GPU_DMINUS
OUT
R240
20K
5%
21
IN
C203
0.0022uF
50V
R248 5%20K
21
OUT
R241
20K
5%
1
N65064848
DNI
Q209
MMBT3906
R233
20K
5%
1
Q215
MMBT3904
2 3
C210
1uF
6.3V
MT206
8
1
8
NA
23456
7
8
83W
7
7
7
3
IN
1
R213 5%2.2K
MT207
23456
Curacao_fansinks
9
1011121314
21
+3.3V_BUS
R200
20K
5%
DNI
PWM
R242
1K
5%
CTF_OUT
NA
7
HS1B
R247
20K
5%
DNI
IN CASE OF
INTERNAL PU
CTF_FAN
1
TO MAXIMIZE FAN OUTPUT
DURING CTF TRIGGER
2 3
19,20
OUT
8
Curacao_fansinks
Curacao_fansinks
HS1C
16
17
24
1819202122
25
23
2627282930
15
Q206
MMBT3904
PWM_B
OUT
6
2
Q203A
MMDT3904-7
1
+3.3V_BUS
R244
5.1K
5%
R234 5%1K
FOR 4-WIRE FAN
ASSY202
SCREW
7020003300G
ASSY201
BRACKET
DUAL
8020056000G
HS1D
31
DP, HDMI, Stacked-DVI
ASSY203
32
BRACKET
DUAL
8020056100G
DP, HDMI, Stacked-DVI W TAB
4
BRACKET MT HOLES
BKT1
BRACKET
DUAL
802005610AG
58 6 3
58 6 3
58 6 3
5
PX_EN
2,19
+3.3V_BUS +12V_EXT_A
UNNAMED_20_NPN_I177_B
5
4
4
4
R257 20K 5%
IN
1,2,20
IN
R228
10K
5%
DNI
GPIO_6_TACH
7,21
OUT
3
Q203B
MMDT3904-7
4
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
NOTES:
NOTES:
NOTES:
+3.3V_BUS
UNNAMED_20_NPN_I171_B
2
PERSTB_BUF
R229
10K
5%
R232 1K
1%
R235
3.83K
1%
MECHANICAL AND THERMAL
MECHANICAL AND THERMAL
MECHANICAL AND THERMAL
NOTE
NOTE
NOTE
6
R4502
20K
5%
6
Q250A
MMDT3904-7
1
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
1
A
2
B
3
CLR
4
GND5Q
Wed Jul 30 07:10:40 2014
Wed Jul 30 07:10:40 2014
Wed Jul 30 07:10:40 2014
OF
OF
OF
C252
0.1uF
6.3V
U200
SN74LVC1G123DCT
+3.3V_BUS
8
UNNAMED_20_74VC1G123_I137_REXT
7
6
Q2_OUT
C251
0.1uF
10V
Q_OUT_R
R260 20K 5%
C253
REV:
REV:
REV:
MMDT3904-7
5
R261 5%1M
6.3V10uF
1.0
1.0
1.0
FAN_EN
VCC
Rext/Cext
Cext
2320
2320
2320
R256
10K
5%
R255
10K
5%
UNNAMED_20_NPN_I173_C
6
3
Q251B
2
1
4
Q251A
3
Q250B
MMDT3904-7
4
+3.3V_BUS
BAV99
3
1 2
D222
FAN_PWM
TACH
FANOUT_P
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
C
C
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
OVERLAP
2014
2014
2014
E
E
E
Page 21
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(21) DEBUG CIRCUITS
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
JTAG
FOR ALL BRING UP BOARDS DNI R4000 AND STUFF R4003
OTHERWISE THE TAPC WILL BE STUCK IN TEST-LOGIG-RESET
AND BE USELESS SINCE TRSTb IS NOT ON THE CONNECTOR
PART 1 OF 18
J
T
A
G
PITCAIRN
U1A
JTAG_TDO
AW43
JTAG_TDO
JTAG_TDI
BA42
JTAG_TDI
JTAG_TMS
AY43
JTAG_TMS
JTAG_TCK
BB42
JTAG_TCK
AW48
TESTEN
JTAG_TRSTB
BB41
JTAG_TRSTB
C
C
C
B B
J3
X_PIN1*2
L3
Single end
RGB
50 ohm +/- 10%
0.140mm
C C
A
A
A
D D
8
8
8
1
5.51 mils
J4
X_PIN1*2
L3
Single end
Memory
45 ohm +/- 5 ohm
0.175mm
6.89 mils
J5
X_PIN1*2
Bottom
Single end
Memory
45 ohm +/- 5 ohm
0.130mm
5.12 mils
7
7
7
2
J6
341
L3
Different
TMDS
85 ohm +/- 10 %
0.11 mm / 0.140 mm
4.33 mils / 5.51 mils
LM96163 FOR BACKUP THERMAL CONTROL
J4004
HEADER_RECEPT_2X4
7 8
5 6
3 4
1 2
R4003 1K 5%
R4000 1K 5%
2
impedence
+3.3V_BUS
+3.3V_BUS
DNI
+3.3V_BUS
R4001
1K
5%
DNI
R4002
1K
5%
J7
341
2
impedence
TOP
Different
Memory clock
80 ohm +/- 10 %
0.130 mm / 0.180 mm
5.12 mils / 7.09 mils
DDCVGACLK
7
IN
DDCVGADATA
7
BI
GPIO_6_TACH
20,7
IN
GPIO_17_THERM_INT
7
OUT
TP4003
TP4004
J8
341
2
impedence
Bottom
Different
PCIE
85 ohm +/- 10 %
0.11 mm / 0.140 mm
4.33 mils / 5.51 mils
+3.3V_BUS
R45
4.7K
5%
R39
R40
4.7K
10K
5%
5%
R43 5%0R
C4009
0.01uF
10V
DNI
TACH CONNECTION IS FOR TESTING
AND RPM MEASUREMENT ONLY
THERM_INTB
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
DEBUG CIRCUITS
DEBUG CIRCUITS
DEBUG CIRCUITS
SHEET:
SHEET:
SHEET:
Wed Jul 30 07:10:46 2014 1.0
Wed Jul 30 07:10:46 2014 1.0
Wed Jul 30 07:10:46 2014 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
5
5
6
6
6
3
5
4
4
4
4
5
U4003
10
SMBCLK
9
SMBDAT
8
TACH
7
ALERT
6
GND
LM96163CISD
21 23
21 23
21 23
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
THMPAD
DD
DD
DD
+3.3V_BUS
C4007
1uF
6.3V
TCRITBTESTEN
R4016 0R 5%
1
TCRIT
2
VDD
3
D+
4
D-
LM_PWM
R4015 33R 5%
5
PWN
11
REV:
REV:
REV:
CTF_THERM
OUT
GPU_DPLUS
IN
GPU_DMINUS
IN
PWM
DNI
OUT
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
20
20
20
20
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
C
C
C
BB
BB
BB
A
A
A
1
1
1
8
Page 22
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
MEMORY CHANNEL A&B MEMORY CHANNEL C&D
GDDR5 4pcs 64M/128Mx32 GDDR5 4pcs 64M/128Mx32
DD
DD
DD
EXTERNAL CONNECTOR
+12V_EXT_A
JTAG/I2C
DEBUG
1x
POWER REGULATORS
FROM +12V_BUS, +12V_EXT_A
+VDDC, +VDDCI, +MVDD, +5V, +0.935V, FAN
C
C
C
B B
From +3.3V_BUS
+1.8V, +BIF_VDDC, +3.3V_DP, VDDR3
From +VDDC (SMPS)
VDDC
From +VDDCI (SMPS)
VDDCI
From +MVDD (SMPS)
VDDR1, MVDDQ/C
From +1.8V (LDO)
PCIE_VDDR, VDDR4, DPLL_PVDD, SPLL_PVDD
MPLL_PVDD, XTAL_VDDR, VDD1DI, AVDD
DP_VDDR, TSVDD
From +0.935V (SMPS)
PCIE_VDDC, DPLL_VDDC, SPLL_VDDC, DP_VDDC
BIF_VDDC
From +BIF_VDDC (SMPS)
BIF_VDDC
C C
CROSS FIRE
INTERLINK
FAN
REGULATOR HOT
DYNAMIC POWER MANAGEMENT
POWER DELIVERY
STRAPS
VBIOS DVI-I
SPEED CONTROL
TEMPERATURE
SENSE
INTERRUPT
TEMP SENSING
BUILT-IN PWM
JTAG
CROSSFIRE
DVOCLK
DVPCNTL_[0..2]
DVPDATA[11:0]
GPIO[2]
GENERIC D
MLPS
GPIO
ROM
THERM
DDCVGA
GPIO17
GPIO6_TACH
D+/D-
TS_FDO
GPIO5
VDDC GPIO20/15
VDDCI GPIO11/0
CH A/B/C/D
TMDPC
DDC1 AUX1
HPD4
TMDPD
DDC2 AUX2
TMDPAB
DDC4
LVTMDPEF
CRTDAC
DDCAUX6
HPD5
HPD1
HPD6
AC COUPLING CAPS
AC COUPLING CAPS
TERMINATIONS
AC COUPLING CAPS
TERMINATIONS
AC COUPLING CAPS
TERMINATIONS
RGB FILTERS
DP
CONNECTOR
HDMI
CONNECTOR
+5V_VESA
CONNECTOR
DL-DVI
+5V_VESA
DVI-I
CONNECTOR
DL-DVI
+3.3V_DP
+5V_VESA
TOP
BOTTOM
C
C
C
BB
BB
BB
PITCAIRN
POWER SEQUENCING
CIRCUIT
BACO
CRITICAL TEMPERATURE
PX_EN
GPIO19_CTF
L3
100MHz
CLOCK
27MHz
CRYSTAL
PCI-EXPRESS
XO_IN2
XO_IN
XTALIN
XTALOUT
PCI-E Trinidad GDDR5 8pcs x32
DP HDMI SDVI FH 6L(CR)
+12V_BUS
+3.3V_BUS
A
A
A
D D
8
8
8
1
7
7
7
2
PCI-EXPRESS BUS
6
6
6
3
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
SHEET:
SHEET:
SHEET:
Wed May 14 09:29:44 2014
Wed May 14 09:29:44 2014
Wed May 14 09:29:44 2014
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
5
5
5
4
4
4
4
5
22 23
22 23
22 23
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
REV:
REV:
REV:
A
A
A
Page 23
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
TITLE:
TITLE:
AMD
AMD
AMD
REVISION HISTORY
REVISION HISTORY
REVISION HISTORY
SCH
SCH
SCH
PCB
PCB
PCB
Date
Date
Date
Rev
Rev
Rev
Rev
Rev
Rev
A A
D D
D D
D D
0 00A
1 00B
01/07/2010
7/23/2014
TITLE:
1. add 3 decoupling caps for VDDC output
2. add 1 output cap for VDDCI
3. change MVDD solution
2
7
7
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
ENGINEER:
ENGINEER:
ENGINEER:
XXX
XXX
XXX
NOTES:
NOTES:
NOTES:
3
6
6
6
DOCUMENT NUMBER: SHEET NUMBER:
DOCUMENT NUMBER: SHEET NUMBER:
DOCUMENT NUMBER: SHEET NUMBER:
NOTE
NOTE
NOTE
4
54332
54332
54332
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the information included herein.
responsibility for any consequences resulting from use of the information included herein.
REVISION DESCRIPTON
REVISION DESCRIPTON
REVISION DESCRIPTON
responsibility for any consequences resulting from use of the information included herein.
5
DATE:
DATE:
DATE:
Wed Jul 23 09:06:58 2014
Wed Jul 23 09:06:58 2014
Wed Jul 23 09:06:58 2014
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
6
7
23 23
23 23
23 23
OF
OF
OF
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
17ci203
8
1
1
1
1.0
1.0
1.0
REV:
REV:
REV:
C
C
C
B B
C
C
C
B B
B B
B B
C C
A
A
A
D D
8
8
8
1
76
76
76
2
3
5
5
5
4
4
4
4
5
6
2
2
2
7
1
1
1
8
A
A
A
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