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MS-V334
Schematics
23 pgs798.19 Kb0

MSI MS-V334 Schematics

1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(1) PCI-EXPRESS EDGE CONNECTOR
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
GPIO_4_SMBCLK
7
IN
GPIO_3_SMBDATA
7
BI
PLACE THESE CAPS AS CLOSE TO PCIE CONNECTOR AS POSSIBLE
+12V_BUS
C157
C151
C152
10uF
0.15uF
0.15uF
16V
16V
C
C
C
B B
+3.3V_BUS
16V
C153
C154
C155
10uF
0.1uF
1uF
6.3V
0.01uF
6.3V
6.3V
C156
10V
+3.3V_BUS +3.3V_BUS +12V_BUS +12V_BUS +3.3V_BUS
R105
45.3K 1%
DNI DNI
C C
Mechanical Key
MPCIE1
x16 PCIe
PRSNT1_A1
PERST_
REFCLK+
REFCLK-
RSVD_A19
RSVD_A32 RSVD_A33
RSVD_A50
PERp10 PERn10
PERp11 PERn11
PERp12 PERn12
PERp13 PERn13
PERp14 PERn14
PERp15 PERn15
A1 A2
+12V
A3
+12V
A4
GND
A5
JTAG2
A6
JTAG3
A7
JTAG4
A8
JTAG5
A9
+3.3V
A10
+3.3V
A11
A12
GND
A13 A14 A15
GND
A16
PERp0
A17
PERn0
A18
GND
A19 A20
GND
A21
PERp1
A22
PERn1
A23
GND
A24
GND
A25
PERp2
A26
PERn2
A27
GND
A28
GND
A29
PERp3
A30
PERn3
A31
GND
A32 A33 A34
GND
A35
PERp4
A36
PERn4
A37
GND
A38
GND
A39
PERp5
A40
PERn5
A41
GND
A42
GND
A43
PERp6
A44
PERn6
A45
GND
A46
GND
A47
PERp7
A48
PERn7
A49
GND
A50 A51
GND
A52
PERp8
A53
PERn8
A54
GND
A55
GND
A56
PERp9
A57
PERn9
A58
GND
A59
GND
A60 A61 A62
GND
A63
GND
A64 A65 A66
GND
A67
GND
A68 A69 A70
GND
A71
GND
A72 A73 A74
GND
A75
GND
A76 A77 A78
GND
A79
GND
A80 A81 A82
GND
B1
+12V
B2
R106
45.3K 1%
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
PETP0_GFXRP0
OUT
PETN0_GFXRN0
OUT
PETP1_GFXRP1
OUT
PETN1_GFXRN1
OUT
PETP2_GFXRP2
OUT
PETN2_GFXRN2
OUT
PETP3_GFXRP3
OUT
PETN3_GFXRN3
OUT
PETP4_GFXRP4
OUT
PETN4_GFXRN4
OUT
PETP5_GFXRP5
OUT
PETN5_GFXRN5
OUT
PETP6_GFXRP6
OUT
PETN6_GFXRN6
OUT
PETP7_GFXRP7
OUT
PETN7_GFXRN7
OUT
PETP8_GFXRP8
OUT
PETN8_GFXRN8
OUT
PETP9_GFXRP9
OUT
PETN9_GFXRN9
OUT
PETP10_GFXRP10
OUT
PETN10_GFXRN10
OUT
PETP11_GFXRP11
OUT
PETN11_GFXRN11
OUT
PETP12_GFXRP12
OUT
PETN12_GFXRN12
OUT
PETP13_GFXRP13
OUT
PETN13_GFXRN13
OUT
PETP14_GFXRP14
OUT
PETN14_GFXRN14
OUT
PETP15_GFXRP15
OUT
PETN15_GFXRN15
OUT
PRESENCE
1
+12V
B3
+12V
B4
GND
B5
SMCLK
B6
SMDAT
B7
GND
B8
+3.3V
B9
JTAG1
B10
3.3Vaux
B11
WAKE_
B12
RSVD_B12
B13
GND
B14
PETp0
B15
PETn0
B16
GND
B17
PRSNT2_B17
B18
GND
B19
PETp1
B20
PETn1
B21
GND
B22
GND
B23
PETp2
B24
PETn2
B25
GND
B26
GND
B27
PETp3
B28
PETn3
B29
GND
B30
RSVD_B30
B31
PRSNT2_B31
B32
GND
B33
PETp4
B34
PETn4
B35
GND
B36
GND
B37
PETp5
B38
PETn5
B39
GND
B40
GND
B41
PETp6
B42
PETn6
B43
GND
B44
GND
B45
PETp7
B46
PETn7
B47
GND
B48
PRSNT2_B48
B49
GND
B50
PETp8
B51
PETn8
B52
GND
B53
GND
B54
PETp9
B55
PETn9
B56
GND
B57
GND
B58
PETp10
B59
PETn10
B60
GND
B61
GND
B62
PETp11
B63
PETn11
B64
GND
B65
GND
B66
PETp12
B67
PETn12
B68
GND
B69
GND
B70
PETp13
B71
PETn13
B72
GND
B73
GND
B74
PETp14
B75
PETn14
B76
GND
B77
GND
B78
PETp15
B79
PETn15
B80
GND
B81
PRSNT2_B81
B82
RSVD_B82
PRESENCE
JTDIO_LOOP
PCIE_REFCLKP PCIE_REFCLKN
PERP0 PERN0
PERP1 PERN1
PERP2 PERN2
PERP3 PERN3
PERP4 PERN4
PERP5 PERN5
PERP6 PERN6
PERP7 PERN7
PERP8 PERN8
PERP9 PERN9
PERP10 PERN10
PERP11 PERN11
PERP12 PERN12
PERP13 PERN13
PERP14 PERN14
PERP15 PERN15
SYSTEM JTAG TDI AND TDO ARE HARD WIRED.
1
2
OUT
2
OUT
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
DD
DD
DD
1.8V_EN
19,18
IN
PERSTB
+3.3V_BUS
U100B
NC7SZ08P5X
3 5
U100A
1
2
NC7SZ08P5X
C158
0.1uF
6.3V
PERSTB_BUF
4
2,20
OUT
C
C
C
BB
BB
BB
SYMBOL LEGEND
DO NOT
DNI
INSTALL
ACTIVE
b or #
LOW
BRING UP
BUO
DIGITAL GROUND
ANALOG GROUND
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
A
A
A
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG #48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
PCIE EDGE CONNECTOR
PCIE EDGE CONNECTOR
PCIE EDGE CONNECTOR
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:18 2015 1.0
Thu Jan 15 02:26:18 2015 1.0
Thu Jan 15 02:26:18 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
123
123
123
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
REV:
REV:
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(2) TRINIDAD PCIE INTERFACE
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
SOME PCIE TEST POINTS ARE
A A
C
C
C
B B
C C
+0.95V
A
A
A
OVERLAP C141 AND MC141
AVAILABLE THROUGH VIAS ON TRACES
TP101
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
+0.95V
+1.8V
TP102
TP117
TP118
C175
C176
1uF
1uF
6.3V
6.3V
C141
MC141
4.7uF
10uF
6.3V
6.3V
C137
1uF
6.3V
C133
1uF
6.3V
C147
1uF
6.3V
C161
C162
0.1uF
0.1uF
6.3V
6.3V
OVERLAP C148 AND MC148
PETP0_GFXRP0 PETN0_GFXRN0
PETP1_GFXRP1 PETN1_GFXRN1
PETP2_GFXRP2 PETN2_GFXRN2
PETP3_GFXRP3 PETN3_GFXRN3
PETP4_GFXRP4 PETN4_GFXRN4
PETP5_GFXRP5 PETN5_GFXRN5
PETP6_GFXRP6 PETN6_GFXRN6
PETP7_GFXRP7 PETN7_GFXRN7
PETP8_GFXRP8 PETN8_GFXRN8
PETP9_GFXRP9 PETN9_GFXRN9
PETP10_GFXRP10 PETN10_GFXRN10
PETP11_GFXRP11 PETN11_GFXRN11
PETP12_GFXRP12 PETN12_GFXRN12
PETP13_GFXRP13 PETN13_GFXRN13
PETP14_GFXRP14 PETN14_GFXRN14
PETP15_GFXRP15 PETN15_GFXRN15
PCIE_REFCLKP
1
IN
PCIE_REFCLKN
1
IN
PCIE_REFCLKx_OUTx WORKSTATION DESIGNS MAY USE THIS FEATURE
PERSTB_BUF
1,20
IN
C171
C172
C177
10uF
1uF
1uF
6.3V
6.3V
6.3V
C140
C136
C139
0.01uF
1uF
0.1uF
6.3V
6.3V
6.3V
C138
C142
1uF
1uF
6.3V
6.3V
C146
C144
C145
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1319
C150
C1284
1uF
1uF
1uF
6.3V
6.3V
6.3V
10u
C148
C163
0.1uF
6.3V
MC148
C160
4.7uF
10uF
10uF
6.3V
6.3V
4V
AR50
PCIE_RX0P
AP49
PCIE_RX0N
AP51
PCIE_RX1P
AN52
PCIE_RX1N
AN50
PCIE_RX2P
AM49
PCIE_RX2N
AM51
PCIE_RX3P
AL52
PCIE_RX3N
AL50
PCIE_RX4P
AK49
PCIE_RX4N
AK51
PCIE_RX5P
AJ52
PCIE_RX5N
AJ50
PCIE_RX6P
AH49
PCIE_RX6N
AH51
PCIE_RX7P
AG52
PCIE_RX7N
AG50
PCIE_RX8P
AF49
PCIE_RX8N
AF51
PCIE_RX9P
AE52
PCIE_RX9N
AE50
PCIE_RX10P
AD49
PCIE_RX10N
AD51
PCIE_RX11P
AC52
PCIE_RX11N
AC50
PCIE_RX12P
AB49
PCIE_RX12N
AB51
PCIE_RX13P
AA52
PCIE_RX13N
AA50
PCIE_RX14P
Y49
PCIE_RX14N
Y51
PCIE_RX15P
W52
PCIE_RX15N
AR47
PCIE_REFCLKP
AR46
PCIE_REFCLKN
AN44
PCIE_REFCLKP_OUT0
AN43
PCIE_REFCLKN_OUT0
AT51
PCIE_REFCLKP_OUT1
AR52
PCIE_REFCLKN_OUT1
AU48
PERSTB
AK40
BIF_VDDC
AG40
BIF_VDDC
AH41
C173
1uF
6.3V
BIF_VDDC
AL41
BIF_VDDC
AT42
PCIE_PVDD
AU42
PCIE_PVDD
AR48
NC_PCIE_VDDR
AT43
NC_PCIE_VDDR
AT44
NC_PCIE_VDDR
AT45
NC_PCIE_VDDR
AT46
NC_PCIE_VDDR
AT47
NC_PCIE_VDDR
AT48
NC_PCIE_VDDR
AB43
PCIE_VDDC
AB44
PCIE_VDDC
AB45
PCIE_VDDC
AD42
PCIE_VDDC
AF42
PCIE_VDDC
AG42
PCIE_VDDC
AH42
PCIE_VDDC
AK42
PCIE_VDDC
AL42
PCIE_VDDC
AM42
PCIE_VDDC
AN42
PCIE_VDDC
AR42
PCIE_VDDC
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
PART 2 OF 18
PITCAIRN
U1B
AN47
PCIE_TX0P
AN46
PCIE_TX0N
AM44
PCIE_TX1P
AM43
PCIE_TX1N
AM47
PCIE_TX2P
AM46
PCIE_TX2N
AL44
PCIE_TX3P
AL43
PCIE_TX3N
AL47
PCIE_TX4P
AL46
PCIE_TX4N
AJ44
PCIE_TX5P
AJ43
PCIE_TX5N
AJ47
PCIE_TX6P
AJ46
PCIE_TX6N
AH44
PCIE_TX7P
AH43
PCIE_TX7N
AH47
PCIE_TX8P
AH46
PCIE_TX8N
AF44
PCIE_TX9P
AF43
PCIE_TX9N
P C I E X P R E S S
PCIE_TX10P PCIE_TX10N
PCIE_TX11P PCIE_TX11N
PCIE_TX12P PCIE_TX12N
PCIE_TX13P PCIE_TX13N
PCIE_TX14P PCIE_TX14N
PCIE_TX15P PCIE_TX15N
PCIE_CALRP_TX
PCIE_CALRN_RX
AF47 AF46
AE44 AE43
AE47 AE46
AC44 AC43
AC47 AC46
AB47 AB46
AR44
AR43
T51
PX_EN
AA48
VSS
AB48
VSS
AB53
VSS
AC45
VSS
AC48
VSS
AD48
VSS
AD53
VSS
AE45
VSS
AE48
VSS
AF45
VSS
AF48
VSS
AF53
VSS
AG48
VSS
AH45
VSS
AH48
VSS
AH53
VSS
AJ45
VSS
AJ48
VSS
AK48
VSS
AK53
VSS
AL45
VSS
AL48
VSS
AM45
VSS
AM48
VSS
AM53
VSS
AN45
VSS
AN48
VSS
AP48
VSS
AP53
VSS
AR45
VSS
AT49
VSS
AT53
VSS
W50
VSS
Y48
VSS
Y53
VSS
4
4
4
5
PCIE_TX0P PCIE_TX0N
PCIE_TX1P PCIE_TX1N
PCIE_TX2P PCIE_TX2N
PCIE_TX3P PCIE_TX3N
PCIE_TX4P PCIE_TX4N
PCIE_TX5P PCIE_TX5N
PCIE_TX6P PCIE_TX6N
PCIE_TX7P PCIE_TX7N
PCIE_TX8P PCIE_TX8N
PCIE_TX9P PCIE_TX9N
PCIE_TX10P PCIE_TX10N
PCIE_TX11P PCIE_TX11N
PCIE_TX12P PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_CALRP_TX
PCIE_CALRN_RX
PX_EN
R150
DNI
PCIE_VSS MERGED TO VSS IN PITCAIRN
FOR BARTS, USE 110NF
C100
6.3V0.22uF
C101
6.3V0.22uF
C102
6.3V0.22uF
C103
6.3V0.22uF
C104
6.3V0.22uF
C105 6.3V0.22uF
C106
6.3V0.22uF
C107
6.3V0.22uF
C108
6.3V0.22uF
C109
6.3V0.22uF
C111
6.3V0.22uF
C110
6.3V0.22uF
C112
6.3V0.22uF
C113
6.3V0.22uF
C114
6.3V0.22uF
C115 6.3V0.22uF
C116
6.3V0.22uF
C117 6.3V0.22uF
C118
6.3V0.22uF
C119
6.3V0.22uF
C120
6.3V0.22uF
C121
6.3V0.22uF
C122
0.22uF 6.3V
C123
6.3V0.22uF
C124
0.22uF 6.3V
C125
6.3V0.22uF
C126 0.22uF 6.3V
C127
6.3V0.22uF
C128
6.3V0.22uF
C129 0.22uF 6.3V
C130
0.22uF 6.3V
C131
0.22uF 6.3V
R100 1.69K 1%
R101 1K 1%
GROUND PX_EN (T51) FOR BARTS (NO BACO)
1K 5%
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG #48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD PCIE INTERFACE
TRINIDAD PCIE INTERFACE
TRINIDAD PCIE INTERFACE
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:19 2015 1.0
Thu Jan 15 02:26:19 2015 1.0
Thu Jan 15 02:26:19 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
PERP0
OUT
PERN0
OUT
PERP1
OUT
PERN1
OUT
PERP2
OUT
PERN2
OUT
PERP3
OUT
PERN3
OUT
PERP4
OUT
PERN4
OUT
PERP5
OUT
PERN5
OUT
PERP6
OUT
PERN6
OUT
PERP7
OUT
PERN7
OUT
PERP8
OUT
PERN8
OUT
PERP9
OUT
PERN9
OUT
PERP10
OUT
PERN10
OUT
PERP11
OUT
PERN11
OUT
PERP12
OUT
PERN12
OUT
PERP13
OUT
PERN13
OUT
PERP14
OUT
PERN14
OUT
PERP15
OUT
PERN15
OUT
PCIE_CALRP_TX: PU R100 (1.69K) FOR PITCAIRN
+0.95V
PCIE_CALRN_RX: PU R101 (1K) FOR PITCAIRN
19,20
OUT
223
223
223
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
DD
DD
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
REV:
REV:
REV:
responsibility for any consequences resulting from use of the information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
DD
C
C
C
BB
BB
BB
A
A
A
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
(3) TRINIDAD MEM INTERFACE CH A/B
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
DQA0_<0>
5,3
A A
C
C
C
B B
C C
BI
DQA0_<1>
5,3
BI
DQA0_<2>
5,3
BI
DQA0_<3>
5,3
BI
DQA0_<4>
5,3
BI
DQA0_<5>
5,3
BI
DQA0_<6>
5,3
BI
DQA0_<7>
5,3
BI
DQA0_<8>
5,3
BI
DQA0_<9>
5,3
BI
DQA0_<10>
5,3
BI
DQA0_<11>
5,3
BI
DQA0_<12>
5,3
BI
DQA0_<13>
5,3
BI
DQA0_<14>
5,3
BI
DQA0_<15>
5,3
BI
DQA0_<16>
5,3
BI
DQA0_<17>
5,3
BI
DQA0_<18>
5,3
BI
DQA0_<19>
5,3
BI
DQA0_<20>
5,3
BI
DQA0_<21>
5,3
BI
DQA0_<22>
5,3
BI
DQA0_<23>
5,3
BI
DQA0_<24>
5,3
BI
DQA0_<25>
5,3
BI
DQA0_<26>
5,3
BI
DQA0_<27>
5,3
BI
DQA0_<28>
5,3
BI
DQA0_<29>
5,3
BI
DQA0_<30>
5,3
BI
DQA0_<31>
5,3
BI
MAA0_<0>
5,3
BI
MAA0_<1>
5,3
BI
MAA0_<2>
5,3
BI
MAA0_<3>
5,3
BI
MAA0_<4>
5,3
BI
MAA0_<5>
5,3
BI
MAA0_<6>
5,3
BI
MAA0_<7>
5,3
BI
MAA0_<8>
5,3
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
WCKA0_0 WCKA0B_0
WCKA0_1 WCKA0B_1
EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3
DDBIA0_0 DDBIA0_1 DDBIA0_2 DDBIA0_3
ADBIA0
CSA0B_0
CASA0B RASA0B WEA0B
CKEA0
CLKA0 CLKA0B
R52 P49 P51 P53 M53 M51 L50 K49 T44 T45 T47 R43 R45 P47 P42 N42 K48 J50 H48 H53 G50 F53 F49 E51 D47 C46 A46 E46 C44 A44 E44 F44
J43 H47 L47 L45 M46 L46 H43 G43 G45 P43
K51 K53
E48 C49
N50 R47 H51 D45
M49 R46 H49 F46
G46
M47 M44
K42 J47 M43
J42
P44 P45
U42
T41
DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31
MAA0_0 MAA0_1 MAA0_2 MAA0_3 MAA0_4 MAA0_5 MAA0_6 MAA0_7 MAA0_8 MAA0_9
WCKA0_0 WCKA0B_0
WCKA0_1 WCKA0B_1
EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3
DDBIA0_0 DDBIA0_1 DDBIA0_2 DDBIA0_3
ADBIA0
CSA0B_0 CSA0B_1
CASA0B RASA0B WEA0B
CKEA0
CLKA0 CLKA0B
NC_MEM_CALRP0
NC_MEM_CALRN0
U1C
PART 3 OF 18
M E M O R Y
I N T E R F A C E
B A N K
A
5
DQA1_<0>
3
D43
DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8
DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31
MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7
MAA1_8
MAA1_9
WCKA1_0
WCKA1B_0
WCKA1_1
WCKA1B_1
EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3
DDBIA1_0 DDBIA1_1 DDBIA1_2 DDBIA1_3
CSA1B_0 CSA1B_1
CASA1B
RASA1B
CLKA1B
MVREFDA
3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5
3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5
ADBIA1
WEA1B
CKEA1
CLKA1
DQA1_<1>
E42
DQA1_<2>
A42
DQA1_<3>
C42
DQA1_<4>
C40
DQA1_<5>
A40
DQA1_<6>
E40
DQA1_<7>
F40
DQA1_<8>
A38
DQA1_<9>
E38
DQA1_<10>
F38
DQA1_<11>
D37
DQA1_<12>
E36
DQA1_<13>
D35
DQA1_<14>
C34
DQA1_<15>
A34
DQA1_<16>
M41
DQA1_<17>
L39
DQA1_<18>
M40
DQA1_<19>
M38
DQA1_<20>
M36
DQA1_<21>
K35
DQA1_<22>
L35
DQA1_<23>
M35
DQA1_<24>
G32
DQA1_<25>
J32
DQA1_<26>
H31
DQA1_<27>
G31
DQA1_<28>
K28
DQA1_<29>
H28
DQA1_<30>
G28
DQA1_<31>
J26
MAA1_<0>
H39
MAA1_<1>
G39
MAA1_<2>
J38
MAA1_<3>
G38
MAA1_<4>
G36
MAA1_<5>
H36
MAA1_<6>
G40
MAA1_<7>
J40
MAA1_<8>
H40 L32
WCKA1_0
C38
WCKA1B_0
D39
WCKA1_1
K33
WCKA1B_1
L33
EDCA1_0
F42
EDCA1_1
A36
EDCA1_2
L36
EDCA1_3
J29
DDBIA1_0
D41
DDBIA1_1
C36
DDBIA1_2
M37
DDBIA1_3
H29
ADBIA1
K39
CSA1B_0
J36 J35
CASA1B
L40
RASA1B
K38
WEA1B
G35
CKEA1
G42
CLKA1
H33
CLKA1B
G33
MVREF_A MVREF_B
M42
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
+MVDD +MVDD
R3602
40.2R 1%
C3602
R3606
1uF
100R
6.3V
1%
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5 5
5 5
5 5 5 5
5 5 5 5
5
5
5 5 5
5
5 5
R3601 120R 1%
DQB0_<0> DQB0_<1> DQB0_<2> DQB0_<3> DQB0_<4> DQB0_<5> DQB0_<6> DQB0_<7> DQB0_<8> DQB0_<9> DQB0_<10> DQB0_<11> DQB0_<12> DQB0_<13> DQB0_<14> DQB0_<15> DQB0_<16> DQB0_<17> DQB0_<18> DQB0_<19> DQB0_<20> DQB0_<21> DQB0_<22> DQB0_<23> DQB0_<24> DQB0_<25> DQB0_<26> DQB0_<27> DQB0_<28> DQB0_<29> DQB0_<30> DQB0_<31>
MAB0_<0> MAB0_<1> MAB0_<2> MAB0_<3> MAB0_<4> MAB0_<5> MAB0_<6> MAB0_<7> MAB0_<8>
BI BI
BI BI
BI BI BI BI
BI BI BI BI
BI
OUT
OUT OUT OUT
OUT
OUT OUT
WCKB0_0 WCKB0B_0
WCKB0_1 WCKB0B_1
EDCB0_0 EDCB0_1 EDCB0_2 EDCB0_3
DDBIB0_0 DDBIB0_1 DDBIB0_2 DDBIB0_3
ADBIB0
CSB0B_0
CASB0B RASB0B WEB0B
CKEB0
CLKB0 CLKB0B
MEM_CALRP1
E34 F34 D33 E32 F32 D31 C30 A30 D29 C28 A28 E28 C26 A26 E26 F26 G26 H26 K25 G25 G23 H23 G22 H22 A24 E24 F24 D23 E22 F22 D21 C20
M23 L23 L26 M26 L28 M28 M21 L21 K22 K32
E30 F30
D25 C24
A32 D27 J25 A22
C32 F28 J23 C22
L22
K29 M30
G21 M24 M31
J21
L31 K31
T16
U17
DQB0_0 DQB0_1 DQB0_2 DQB0_3 DQB0_4 DQB0_5 DQB0_6 DQB0_7 DQB0_8 DQB0_9 DQB0_10 DQB0_11 DQB0_12 DQB0_13 DQB0_14 DQB0_15 DQB0_16 DQB0_17 DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 DQB0_25 DQB0_26 DQB0_27 DQB0_28 DQB0_29 DQB0_30 DQB0_31
MAB0_0 MAB0_1 MAB0_2 MAB0_3 MAB0_4 MAB0_5 MAB0_6 MAB0_7 MAB0_8 MAB0_9
WCKB0_0 WCKB0B_0
WCKB0_1 WCKB0B_1
EDCB0_0 EDCB0_1 EDCB0_2 EDCB0_3
DDBIB0_0 DDBIB0_1 DDBIB0_2 DDBIB0_3
ADBIB0
CSB0B_0 CSB0B_1
CASB0B RASB0B WEB0B
CKEB0
CLKB0 CLKB0B
MEM_CALRP1
NC_MEM_CALRN1
U1D
PART 4 OF 18
M E M O R Y
I N T E R F A C E
B A N K
B
DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8
DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31
MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MAB1_7
MAB1_8
MAB1_9
WCKB1_0
WCKB1B_0
WCKB1_1
WCKB1B_1
EDCB1_0 EDCB1_1 EDCB1_2 EDCB1_3
DDBIB1_0 DDBIB1_1 DDBIB1_2 DDBIB1_3
ADBIB1
CSB1B_0 CSB1B_1
CASB1B
RASB1B
WEB1B
CLKB1B
MVREFDB
DQB1_<0>
A20
3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3
5 3 5
3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5
CKEB1
CLKB1
DQB1_<1>
E20
DQB1_<2>
F20
DQB1_<3>
D19
DQB1_<4>
E18
DQB1_<5>
D17
DQB1_<6>
C16
DQB1_<7>
A16
DQB1_<8>
D15
DQB1_<9>
C14
DQB1_<10>
A14
DQB1_<11>
E14
DQB1_<12>
A12
DQB1_<13>
E12
DQB1_<14>
F12
DQB1_<15>
D11
DQB1_<16>
G15
DQB1_<17>
H15
DQB1_<18>
G14
DQB1_<19>
H14
DQB1_<20>
G11
DQB1_<21>
J11
DQB1_<22>
G9
DQB1_<23>
G8
DQB1_<24>
E10
DQB1_<25>
D9
DQB1_<26>
C8
DQB1_<27>
A8
DQB1_<28>
D7
DQB1_<29>
A6
DQB1_<30>
E6
DQB1_<31>
C5
MAB1_<0>
L18
MAB1_<1>
K18
MAB1_<2>
J16
MAB1_<3>
K16
MAB1_<4>
L15
MAB1_<5>
G16
MAB1_<6>
J19
MAB1_<7>
H19
MAB1_<8>
G18 L12
WCKB1_0
F16
WCKB1B_0
E16
WCKB1_1
A10
WCKB1B_1
C10
EDCB1_0
A18
EDCB1_1
C12
EDCB1_2
H11
EDCB1_3
F8
DDBIB1_0
C18
DDBIB1_1
D13
DDBIB1_2
G12
DDBIB1_3
E8
ADBIB1
H18
CSB1B_0
J15 L14
CASB1B
G19
RASB1B
M18
WEB1B
K14
CKEB1
L19
CLKB1
K12
CLKB1B
J12
M17
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5,3
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
BI
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
5
OUT
R3603
40.2R 1%
C3603
R3607
1uF
100R
6.3V
1%
DD
DD
DD
C
C
C
BB
BB
BB
N41
MVREFSA
PITCAIRN
A
A
A
MVREFD/S = 0.7 * VDDR1
DRAM_RST1
5
OUT
R3630 49.9R 1%
R3615 1%10R
C3607
120pF 50V
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
DRAM_RST1_RDRAM_RST1_RR
V43
DRAM_RST1
R3612
5.1K 1%
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG #48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD MEM CH AB
TRINIDAD MEM CH AB
TRINIDAD MEM CH AB
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:19 2015 1.0
Thu Jan 15 02:26:19 2015 1.0
Thu Jan 15 02:26:19 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
PITCAIRN
323
323
323
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
MVREFSB
M19
REV:
REV:
REV:
MVREFD/S = 0.7 * VDDR1
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
A
A
A
1
1
1
8
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
(4) TRINIDAD MEM INTERFACE CH C/D
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
DQC0_<0>
6,4
A A
C
C
C
B B
C C
BI
DQC0_<1>
6,4
BI
DQC0_<2>
6,4
BI
DQC0_<3>
6,4
BI
DQC0_<4>
6,4
BI
DQC0_<5>
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
R3614 1%120R
DQC0_<6> DQC0_<7> DQC0_<8> DQC0_<9> DQC0_<10> DQC0_<11> DQC0_<12> DQC0_<13> DQC0_<14> DQC0_<15> DQC0_<16> DQC0_<17> DQC0_<18> DQC0_<19> DQC0_<20> DQC0_<21> DQC0_<22> DQC0_<23> DQC0_<24> DQC0_<25> DQC0_<26> DQC0_<27> DQC0_<28> DQC0_<29> DQC0_<30> DQC0_<31>
MAC0_<0> MAC0_<1> MAC0_<2> MAC0_<3> MAC0_<4> MAC0_<5> MAC0_<6> MAC0_<7> MAC0_<8>
WCKC0_0 WCKC0B_0
WCKC0_1 WCKC0B_1
EDCC0_0 EDCC0_1 EDCC0_2 EDCC0_3
DDBIC0_0 DDBIC0_1 DDBIC0_2 DDBIC0_3
ADBIC0
CSC0B_0
CASC0B RASC0B WEC0B
CKEC0
CLKC0 CLKC0B
MEM_CALRP2
BB17
BA16
E3 F5 F1 G4 H1 H3
J4 K5 H7
J7
L9
L7 P8 P7 R8 R7
L4 M6 M5 M1 P5 P1 P3 R4 T1 T3 U4 V5 W4 Y6 Y5 Y1
V11 V10
T9
T10 R11
T7 W9 W8 V7
M11
K1 K3
T6 T5
H6
L8 M3 V1
H5 M7 N4 V3
V8
R9
P11
W7
V12 P10
W11
M10
M9
DQC0_0 DQC0_1 DQC0_2 DQC0_3 DQC0_4 DQC0_5 DQC0_6 DQC0_7 DQC0_8 DQC0_9 DQC0_10 DQC0_11 DQC0_12 DQC0_13 DQC0_14 DQC0_15 DQC0_16 DQC0_17 DQC0_18 DQC0_19 DQC0_20 DQC0_21 DQC0_22 DQC0_23 DQC0_24 DQC0_25 DQC0_26 DQC0_27 DQC0_28 DQC0_29 DQC0_30 DQC0_31
MAC0_0 MAC0_1 MAC0_2 MAC0_3 MAC0_4 MAC0_5 MAC0_6 MAC0_7 MAC0_8 MAC0_9
WCKC0_0 WCKC0B_0
WCKC0_1 WCKC0B_1
EDCC0_0 EDCC0_1 EDCC0_2 EDCC0_3
DDBIC0_0 DDBIC0_1 DDBIC0_2 DDBIC0_3
ADBIC0
CSC0B_0 CSC0B_1
CASC0B RASC0B WEC0B
CKEC0
CLKC0 CLKC0B
MEM_CALRP2
NC_MEM_CALRN2
U1E
PART 5 OF 18
M E M O R Y
I N T E R F A C E
B A N K
C
6
DQC1_<0>
4
Y3
DQC1_0 DQC1_1 DQC1_2 DQC1_3 DQC1_4 DQC1_5 DQC1_6 DQC1_7 DQC1_8
DQC1_9 DQC1_10 DQC1_11 DQC1_12 DQC1_13 DQC1_14 DQC1_15 DQC1_16 DQC1_17 DQC1_18 DQC1_19 DQC1_20 DQC1_21 DQC1_22 DQC1_23 DQC1_24 DQC1_25 DQC1_26 DQC1_27 DQC1_28 DQC1_29 DQC1_30 DQC1_31
MAC1_0
MAC1_1
MAC1_2
MAC1_3
MAC1_4
MAC1_5
MAC1_6
MAC1_7
MAC1_8
MAC1_9
WCKC1_0
WCKC1B_0
WCKC1_1
WCKC1B_1
EDCC1_0 EDCC1_1 EDCC1_2 EDCC1_3
DDBIC1_0 DDBIC1_1 DDBIC1_2 DDBIC1_3
ADBIC1
CSC1B_0 CSC1B_1
CASC1B
RASC1B
WEC1B
CLKC1B
MVREFDC
6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4
6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
6 4
CKEC1
CLKC1
DQC1_<1>
AA4
DQC1_<2>
AB6
DQC1_<3>
AB5
DQC1_<4>
AC4
DQC1_<5>
AD6
DQC1_<6>
AD5
DQC1_<7>
AD1
DQC1_<8>
AB8
DQC1_<9>
AB7
DQC1_<10>
AC8
DQC1_<11>
AC7
DQC1_<12>
AE7
DQC1_<13>
AE10
DQC1_<14>
AF8
DQC1_<15>
AF7
DQC1_<16>
AF6
DQC1_<17>
AF5
DQC1_<18>
AF1
DQC1_<19>
AF3
DQC1_<20>
AH5
DQC1_<21>
AH1
DQC1_<22>
AH3
DQC1_<23>
AJ4
DQC1_<24>
AK1
DQC1_<25>
AK3
DQC1_<26>
AL4
DQC1_<27>
AM6
DQC1_<28>
AM5
DQC1_<29>
AN4
DQC1_<30>
AP6
DQC1_<31>
AP5
MAC1_<0>
AC12
MAC1_<1>
AC11
MAC1_<2>
AF11
MAC1_<3>
AF12
MAC1_<4>
AH11
MAC1_<5>
AH12
MAC1_<6>
AA12
MAC1_<7>
AA11
MAC1_<8>
AB10 AM10
WCKC1_0
AE4
WCKC1B_0
AD3
WCKC1_1
AK5
WCKC1B_1
AK6
EDCC1_0
AB1
EDCC1_1
AE9
EDCC1_2
AG4
EDCC1_3
AM1
DDBIC1_0
AB3
DDBIC1_1
AC9
DDBIC1_2
AH6
DDBIC1_3
AM3
ADBIC1
AB11
CSC1B_0
AJ10 AK12
CASC1B
AA7
RASC1B
AD12
WEC1B
AL12
CKEC1
AA9
CLKC1
AL11
CLKC1B
AL10
MVREF_C MVREF_D
U12
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
+MVDD +MVDD
R3618
40.2R 1%
C3612
R3621
1uF
100R
6.3V
1%
DQD0_<0>
6,4
BI
DQD0_<1>
6,4
BI
DQD0_<2>
6,4
BI
DQD0_<3>
6,4
BI
DQD0_<4>
6,4
BI
DQD0_<5>
6,4
BI
DQD0_<6>
6,4
BI
DQD0_<7>
6,4
BI
DQD0_<8>
6,4
BI
DQD0_<9>
6,4
BI
DQD0_<10>
6,4
BI
DQD0_<11>
6,4
BI
DQD0_<12>
6,4
BI
DQD0_<13>
6,4
BI
DQD0_<14>
6,4
BI
DQD0_<15>
6,4
BI
DQD0_<16>
6,4
BI
DQD0_<17>
6,4
BI
DQD0_<18>
6,4
BI
DQD0_<19>
6,4
BI
DQD0_<20>
6,4
BI
DQD0_<21>
6,4
BI
DQD0_<22>
6,4
BI
DQD0_<23>
6,4
BI
DQD0_<24>
6,4
BI
DQD0_<25>
6,4
BI
DQD0_<26>
6,4
BI
DQD0_<27>
6,4
BI
DQD0_<28>
6,4
BI
DQD0_<29>
6,4
BI
DQD0_<30>
6,4
BI
DQD0_<31>
6,4
BI
MAD0_<0>
6,4
BI
MAD0_<1>
6,4
BI
MAD0_<2>
6,4
BI
MAD0_<3>
6,4
BI
MAD0_<4>
6,4
BI
MAD0_<5>
6,4
BI
MAD0_<6>
6,4
BI
MAD0_<7>
6,4
BI
MAD0_<8>
6,4
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
WCKD0_0 WCKD0B_0
WCKD0_1 WCKD0B_1
EDCD0_0 EDCD0_1 EDCD0_2 EDCD0_3
DDBID0_0 DDBID0_1 DDBID0_2 DDBID0_3
ADBID0
CSD0B_0
CASD0B RASD0B WED0B
CKED0
CLKD0 CLKD0B
AF9 AH7 AH8
AH10
AL7
AL8 AM9 AM7
AR12 AR11 AR10 AT12 AV12 AY12
AW11
BA12
AP1
AP3
AR4
AT5
AU4
AV6
AV5
AV1
AY6
AY5
AY1
AY3
BB3
BB1
BB5
BC4
AW8 AW7
AV9
AV7
AT7
AT8
AY7
AY9
AY8
AM11
AN10 AN11
AV3
AW4
AJ9
AT11
AT1
BB6
AJ8
AU12
AT3
BA4
AW10
AT9
AR9
AY11 AV10
AR7
BB7
AN8
AN7
DQD0_0 DQD0_1 DQD0_2 DQD0_3 DQD0_4 DQD0_5 DQD0_6 DQD0_7 DQD0_8 DQD0_9 DQD0_10 DQD0_11 DQD0_12 DQD0_13 DQD0_14 DQD0_15 DQD0_16 DQD0_17 DQD0_18 DQD0_19 DQD0_20 DQD0_21 DQD0_22 DQD0_23 DQD0_24 DQD0_25 DQD0_26 DQD0_27 DQD0_28 DQD0_29 DQD0_30 DQD0_31
MAD0_0 MAD0_1 MAD0_2 MAD0_3 MAD0_4 MAD0_5 MAD0_6 MAD0_7 MAD0_8 MAD0_9
WCKD0_0 WCKD0B_0
WCKD0_1 WCKD0B_1
EDCD0_0 EDCD0_1 EDCD0_2 EDCD0_3
DDBID0_0 DDBID0_1 DDBID0_2 DDBID0_3
ADBID0
CSD0B_0 CSD0B_1
CASD0B RASD0B WED0B
CKED0
CLKD0 CLKD0B
PART 6 OF 18
U1F
M E M O R Y
I N T E R F A C E
B A N K
D
DQD1_0 DQD1_1 DQD1_2 DQD1_3 DQD1_4 DQD1_5 DQD1_6 DQD1_7 DQD1_8
DQD1_9 DQD1_10 DQD1_11 DQD1_12 DQD1_13 DQD1_14 DQD1_15 DQD1_16 DQD1_17 DQD1_18 DQD1_19 DQD1_20 DQD1_21 DQD1_22 DQD1_23 DQD1_24 DQD1_25 DQD1_26 DQD1_27 DQD1_28 DQD1_29 DQD1_30 DQD1_31
MAD1_0
MAD1_1
MAD1_2
MAD1_3
MAD1_4
MAD1_5
MAD1_6
MAD1_7
MAD1_8
MAD1_9
WCKD1_0
WCKD1B_0
WCKD1_1
WCKD1B_1
EDCD1_0 EDCD1_1 EDCD1_2 EDCD1_3
DDBID1_0 DDBID1_1 DDBID1_2 DDBID1_3
ADBID1
CSD1B_0 CSD1B_1
CASD1B
RASD1B
WED1B
CLKD1B
MVREFDD
6
DQD1_<0>
4
BD6
6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4
6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4
6 4
6 4 6 4 6 4
6 4 6 4 6 4 6 4
CKED1
CLKD1
DQD1_<1>
BD5
DQD1_<2>
BD1
DQD1_<3>
BD3
DQD1_<4>
BF5
DQD1_<5>
BF1
DQD1_<6>
BF3
DQD1_<7>
BG4
DQD1_<8>
BL5
DQD1_<9>
BJ6
DQD1_<10>
BN6
DQD1_<11>
BK7
DQD1_<12>
BN8
DQD1_<13>
BH8
DQD1_<14>
BK9
DQD1_<15>
BH10
DQD1_<16>
BB13
DQD1_<17>
BB14
DQD1_<18>
BG14
DQD1_<19>
BE15
DQD1_<20>
BC15
DQD1_<21>
BG16
DQD1_<22>
BE16
DQD1_<23>
BD16
DQD1_<24>
BJ10
DQD1_<25>
BK11
DQD1_<26>
BL12
DQD1_<27>
BN12
DQD1_<28>
BN14
DQD1_<29>
BL14
DQD1_<30>
BJ14
DQD1_<31>
BM15
6
MAD1_<0>
4
BC9
MAD1_<1>
BG8
MAD1_<2>
BG11
MAD1_<3>
BE11
MAD1_<4>
BF12
MAD1_<5>
BF11
MAD1_<6>
BC8
MAD1_<7>
BC7
MAD1_<8>
BE7 BC14
WCKD1_0
BH5
WCKD1B_0
BJ3
WCKD1_1
BL10
WCKD1B_1
BN10
EDCD1_0
BE4
EDCD1_1
BL8
EDCD1_2
BG15
EDCD1_3
BK13
DDBID1_0
BF6
DDBID1_1
BJ8
DDBID1_2
BF15
DDBID1_3
BJ12
ADBID1
BF7
CSD1B_0
BG12 BD12
CASD1B
BB10
RASD1B
BG9
WED1B
BC12
CKED1
BB9
CLKD1
BD14
CLKD1B
BE14
BB12
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6,4
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
BI
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
R3619
40.2R 1%
C3611
R3620
1uF
100R
6.3V
1%
DD
DD
DD
C
C
C
BB
BB
BB
W12
MVREFSC
PITCAIRN
A
A
A
MVREFD/S = 0.7 * VDDR1 MVREFD/S = 0.7 * VDDR1
DRAM_RST2
6
OUT
R3629 49.9R 1%
R3616 1%10R
C3617
120pF 50V
D D
5
5
8
8
8
1
7
7
7
2
6
6
6
3
5
4
4
4
4
5
DRAM_RST2_RDRAM_RST2_RR
BC18
DRAM_RST2
R3627
5.1K 1%
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG #48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD MEM CH CD
TRINIDAD MEM CH CD
TRINIDAD MEM CH CD
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:20 2015 1.0
Thu Jan 15 02:26:20 2015 1.0
Thu Jan 15 02:26:20 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
PITCAIRN
423
423
423
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
MVREFSD
BA13
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
REV:
REV:
REV:
responsibility for any consequences resulting from use of the information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(5) GDDR5 MEMORY CH A/B
5
14
DQA0_<14>
3
3,5
BI
15
DQA0_<15>
3,5
BI
13
DQA0_<13>
3,5
BI
12
DQA0_<12>
3,5
BI
10
DQA0_<10>
3,5
BI
9
DQA0_<9>
3,5
BI
11
DQA0_<11>
3,5
BI
8
DQA0_<8>
3,5
BI
7
DQA0_<7>
3,5
A A
C
C
C
B B
+MVDD
R2001 1%60.4R R2000 1%60.4R
C C
+MVDD
3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5
3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5
3 3
3 3
3 3 3 3
3 3 3 3
3 3
3 3 3
3 3
R2002 120R 1%
R2003 5%1K
3,5
R2004 5%1K
R2009 1%2.37K R2010 1%5.49K
C2005 6.3V1uF
3
BI
6
DQA0_<6>
BI
4
DQA0_<4>
BI
5
DQA0_<5>
BI
0
DQA0_<0>
BI
2
DQA0_<2>
BI
1
DQA0_<1>
BI
3
DQA0_<3>
BI
21
DQA0_<21>
BI
22
DQA0_<22>
BI
20
DQA0_<20>
BI
23
DQA0_<23>
BI
19
DQA0_<19>
BI
18
DQA0_<18>
BI
16
DQA0_<16>
BI
17
DQA0_<17>
BI
26
DQA0_<26>
BI
25
DQA0_<25>
BI
24
DQA0_<24>
BI
27
DQA0_<27>
BI
28
DQA0_<28>
BI
30
DQA0_<30>
BI
29
DQA0_<29>
BI
31
DQA0_<31>
BI
5
8
MAA0_<8>
3
BI
7
MAA0_<7>
BI
6
MAA0_<6>
BI
5
MAA0_<5>
BI
4
MAA0_<4>
BI
3
MAA0_<3>
BI
2
MAA0_<2>
BI
1
MAA0_<1>
BI
0
MAA0_<0>
BI
WCKA0_1
IN
WCKA0B_1
IN
WCKA0_0
IN
WCKA0B_0
IN
EDCA0_1
OUT
EDCA0_0
OUT
EDCA0_2
OUT
EDCA0_3
OUT
DDBIA0_1
BI
DDBIA0_0
BI
DDBIA0_2
BI
DDBIA0_3
BI
RASA0B
IN
CASA0B
IN
CKEA0
IN
CLKA0B
IN
CLKA0
IN
CSA0B_0
IN
WEA0B
IN
ZQ_A0 ZQ_A1 ZQ_B0 ZQ_B1 SEN_A0 SEN_A1 SEN_B0 SEN_B1
DRAM_RST1
IN
MF_A0 MF_A1 MF_B0 MF_B1
VREFC_A0 VREFC_A1 VREFC_B0 VREFC_B1
ADBIA0
IN
23CNOPN001
U2000
M2
DQ31__DQ7
M4
DQ30__DQ6
N2
DQ29__DQ5
N4
DQ28__DQ4
T2
DQ27__DQ3
T4
DQ26__DQ2
V2
DQ25__DQ1
V4
DQ24__DQ0
M13
DQ23__DQ15
M11
DQ22__DQ14
N13
DQ21__DQ13
N11
DQ20__DQ12
T13
DQ19__DQ11
T11
DQ18__DQ10
V13
DQ17__DQ9
V11
DQ16__DQ8
F13
DQ15__DQ23
F11
DQ14__DQ22
E13
DQ13__DQ21
E11
DQ12__DQ20
B13
DQ11__DQ19
B11
DQ10__DQ18
A13
DQ9__DQ17
A11
DQ8__DQ16
F2
DQ7__DQ31
F4
DQ6__DQ30
E2
DQ5__DQ29
E4
DQ4__DQ28
B2
DQ3__DQ27
B4
DQ2__DQ26
A2
DQ1__DQ25
A4
DQ0__DQ24
J5
RFU_A12_NC
K4
A7_A8__A0_A10
K5
A6_A11__A1_A9
K10
A5_BA1__A3_BA3
K11
A4_BA2__A2_BA0
H10
A3_BA3__A5_BA1
H11
A2_BA0__A4_BA2
H5
A1_A9__A6_A11
H4
A0_A10__A7_A8
D4
WCK01__WCK23
D5
WCK01#__WCK23#
P4
WCK23__WCK01
P5
WCK23#__WCK01#
R2
EDC3__EDC0
R13
EDC2__EDC1
C13
EDC1__EDC2
C2
EDC0__EDC3
P2
DBI3#__DBI0#
P13
DBI2#__DBI1#
D13
DBI1#__DBI2#
D2
DBI0#__DBI3#
G3
RAS#__CAS#
L3
CAS#__RAS#
J3
CKE#
J11
CK#
J12
CK
G12
CS#__WE#
L12
WE#__CS#
J13
ZQ
J10
SEN
J2
RESET#
J1
MF
A5
Vpp_NC
V5
Vpp_NC1
A10
VREFD1
V10
VREFD2
J14
VREFC
J4
ABI#
VDDQ_B1
VDDQ_B3 VDDQ_B12 VDDQ_B14
VDDQ_D1
VDDQ_D3 VDDQ_D12 VDDQ_D14
VDDQ_E5 VDDQ_E10
VDDQ_F1
VDDQ_F3 VDDQ_F12 VDDQ_F14
VDDQ_G2 VDDQ_G13
VDDQ_H3 VDDQ_H12
VDDQ_K3 VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3 VDDQ_M12 VDDQ_M14
VDDQ_N5 VDDQ_N10
VDDQ_P1
VDDQ_P3 VDDQ_P12 VDDQ_P14
VDDQ_T1
VDDQ_T3 VDDQ_T12 VDDQ_T14
VDD_C5 VDD_C10 VDD_D11
VDD_G1
VDD_G4 VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3 VSSQ_A12 VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4 VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E1
VSSQ_E3 VSSQ_E12 VSSQ_E14
VSSQ_F5 VSSQ_F10
VSSQ_H2 VSSQ_H13
VSSQ_K2 VSSQ_K13
VSSQ_M5 VSSQ_M10
VSSQ_N1
VSSQ_N3 VSSQ_N12 VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4 VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V1
VSSQ_V3 VSSQ_V12 VSSQ_V14
VSS_B5 VSS_B10 VSS_D10
VSS_G5
VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5 VSS_T10
+MVDD
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
+MVDD
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12
+MVDD
E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
+MVDD
R2101 60.4R 1% R2100 1%60.4R
R2102 1%120R R2103 5%1K
R2104 5%1K
+MVDD
R2109 1%2.37K R2110 1%5.49K
C2105 1uF 6.3V
5
5
DQA1_<5>
3
3,5
BI
6
DQA1_<6>
3,5
BI
4
DQA1_<4>
3,5
BI
7
DQA1_<7>
3,5
BI
3
DQA1_<3>
3,5
BI
2
DQA1_<2>
3,5
BI
1
DQA1_<1>
3,5
BI
0
DQA1_<0>
3,5
BI
11
DQA1_<11>
3,5
BI
10
DQA1_<10>
3,5
BI
8
DQA1_<8>
3,5
BI
9
DQA1_<9>
3,5
BI
12
DQA1_<12>
3,5
BI
14
DQA1_<14>
3,5
BI
13
DQA1_<13>
3,5
BI
15
DQA1_<15>
3,5
BI
24
DQA1_<24>
3,5
BI
25
DQA1_<25>
3,5
BI
27
DQA1_<27>
3,5
BI
26
DQA1_<26>
3,5
BI
31
DQA1_<31>
3,5
BI
29
DQA1_<29>
3,5
BI
30
DQA1_<30>
3,5
BI
28
DQA1_<28>
3,5
BI
17
DQA1_<17>
3,5
BI
16
DQA1_<16>
3,5
BI
19
DQA1_<19>
3,5
BI
18
DQA1_<18>
3,5
BI
20
DQA1_<20>
3,5
BI
22
DQA1_<22>
3,5
BI
21
DQA1_<21>
3,5
BI
23
DQA1_<23>
3,5
BI
5
8
MAA1_<8>
3
3,5
BI
0
MAA1_<0>
3,5
BI
1
MAA1_<1>
3,5
BI
3
MAA1_<3>
3,5
BI
2
MAA1_<2>
3,5
BI
5
MAA1_<5>
3,5
BI
4
MAA1_<4>
3,5
BI
6
MAA1_<6>
3,5
BI
7
MAA1_<7>
3,5
BI
WCKA1_1
3
IN
WCKA1B_1
3
IN
WCKA1_0
3
IN
WCKA1B_0
3
IN
EDCA1_0
3
OUT
EDCA1_1
3
OUT
EDCA1_3
3
OUT
EDCA1_2
3
OUT
DDBIA1_0
3
BI
DDBIA1_1
3
BI
DDBIA1_3
3
BI
DDBIA1_2
3
BI
CASA1B
3
IN
RASA1B
3
IN
CKEA1
3
IN
CLKA1B
3
IN
CLKA1
3
IN
WEA1B
3
IN
CSA1B_0
3
IN
DRAM_RST1
3,5
IN
ADBIA1
3
IN
M2 M4 N2 N4 T2 T4 V2
V4 M13 M11
N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5
K10 K11 H10 H11
H5
H4
D4
D5
P4
P5
R2
R13 C13
C2
P2
P13 D13
D2
G3
L3
J3
J11 J12
G12
L12
J13 J10
J2
J1
A5
V5
A10 V10
J14
J4
DQ31__DQ7 DQ30__DQ6 DQ29__DQ5 DQ28__DQ4 DQ27__DQ3 DQ26__DQ2 DQ25__DQ1 DQ24__DQ0 DQ23__DQ15 DQ22__DQ14 DQ21__DQ13 DQ20__DQ12 DQ19__DQ11 DQ18__DQ10 DQ17__DQ9 DQ16__DQ8 DQ15__DQ23 DQ14__DQ22 DQ13__DQ21 DQ12__DQ20 DQ11__DQ19 DQ10__DQ18 DQ9__DQ17 DQ8__DQ16 DQ7__DQ31 DQ6__DQ30 DQ5__DQ29 DQ4__DQ28 DQ3__DQ27 DQ2__DQ26 DQ1__DQ25 DQ0__DQ24
RFU_A12_NC A7_A8__A0_A10 A6_A11__A1_A9 A5_BA1__A3_BA3 A4_BA2__A2_BA0 A3_BA3__A5_BA1 A2_BA0__A4_BA2 A1_A9__A6_A11 A0_A10__A7_A8
WCK01__WCK23 WCK01#__WCK23#
WCK23__WCK01 WCK23#__WCK01#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
RAS#__CAS# CAS#__RAS#
CKE# CK# CK
CS#__WE# WE#__CS#
ZQ SEN
RESET# MF
Vpp_NC Vpp_NC1
VREFD1 VREFD2
VREFC
ABI#
23CNOPN001
U2100
VDDQ_B1
VDDQ_B3 VDDQ_B12 VDDQ_B14
VDDQ_D1
VDDQ_D3 VDDQ_D12 VDDQ_D14
VDDQ_E5 VDDQ_E10
VDDQ_F1
VDDQ_F3 VDDQ_F12 VDDQ_F14
VDDQ_G2 VDDQ_G13
VDDQ_H3 VDDQ_H12
VDDQ_K3 VDDQ_K12
VDDQ_L2 VDDQ_L13
VDDQ_M1
VDDQ_M3 VDDQ_M12 VDDQ_M14
VDDQ_N5 VDDQ_N10
VDDQ_P1
VDDQ_P3 VDDQ_P12 VDDQ_P14
VDDQ_T1
VDDQ_T3 VDDQ_T12 VDDQ_T14
VDD_C5 VDD_C10 VDD_D11 VDD_G1
VDD_G4 VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14 VDD_P11 VDD_R5 VDD_R10
VSSQ_A1
VSSQ_A3 VSSQ_A12 VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4 VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E1
VSSQ_E3 VSSQ_E12 VSSQ_E14
VSSQ_F5 VSSQ_F10
VSSQ_H2 VSSQ_H13
VSSQ_K2 VSSQ_K13
VSSQ_M5 VSSQ_M10
VSSQ_N1
VSSQ_N3 VSSQ_N12 VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4 VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V1
VSSQ_V3 VSSQ_V12 VSSQ_V14
VSS_B5 VSS_B10 VSS_D10 VSS_G5
VSS_G10
VSS_H1 VSS_H14 VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10 VSS_T5 VSS_T10
+MVDD
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
+MVDD
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12
+MVDD
E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
+MVDD
R2201 60.4R 1% R2200 1%60.4R
R2202 1%120R
R2203 5%1K
R2204 5%1K
R2209 1%2.37K R2210 1%5.49K C2205 1uF 6.3V
5
30
DQB0_<30>
3
3,5
BI
25
DQB0_<25>
3,5
BI
29
DQB0_<29>
3,5
BI
24
DQB0_<24>
3,5
BI
28
DQB0_<28>
3,5
BI
26
DQB0_<26>
3,5
BI
31
DQB0_<31>
3,5
BI
27
DQB0_<27>
3,5
BI
17
DQB0_<17>
3,5
BI
16
DQB0_<16>
3,5
BI
18
DQB0_<18>
3,5
BI
19
DQB0_<19>
3,5
BI
21
DQB0_<21>
3,5
BI
23
DQB0_<23>
3,5
BI
20
DQB0_<20>
3,5
BI
22
DQB0_<22>
3,5
BI
5
DQB0_<5>
3,5
BI
6
DQB0_<6>
3,5
BI
4
DQB0_<4>
3,5
BI
7
DQB0_<7>
3,5
BI
3
DQB0_<3>
3,5
BI
2
DQB0_<2>
3,5
BI
1
DQB0_<1>
3,5
BI
0
DQB0_<0>
3,5
BI
11
DQB0_<11>
3,5
BI
10
DQB0_<10>
3,5
BI
8
DQB0_<8>
3,5
BI
9
DQB0_<9>
3,5
BI
12
DQB0_<12>
3,5
BI
13
DQB0_<13>
3,5
BI
14
DQB0_<14>
3,5
BI
15
DQB0_<15>
3,5
BI
5
8
MAB0_<8>
3
3,5
BI
7
MAB0_<7>
3,5
BI
6
MAB0_<6>
3,5
BI
5
MAB0_<5>
3,5
BI
4
MAB0_<4>
3,5
BI
3
MAB0_<3>
3,5
BI
2
MAB0_<2>
3,5
BI
1
MAB0_<1>
3,5
BI
0
MAB0_<0>
3,5
BI
WCKB0_0
3
IN
WCKB0B_0
3
IN
WCKB0_1
3
IN
WCKB0B_1
3
IN
EDCB0_3
3
OUT
EDCB0_2
3
OUT
EDCB0_0
3
OUT
EDCB0_1
3
OUT
DDBIB0_3
3
BI
DDBIB0_2
3
BI
DDBIB0_0
3
BI
DDBIB0_1
3
BI
RASB0B
3
IN
CASB0B
3
IN
CKEB0
3
IN
CLKB0B
3
IN
CLKB0
3
IN
CSB0B_0
3
IN
WEB0B
3
IN
DRAM_RST1
3,5
IN
ADBIB0
3
IN
M2 M4 N2 N4 T2 T4 V2
V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11
F2
F4
E2
E4
B2
B4
A2
A4
J5 K4 K5
K10 K11 H10 H11
H5 H4
D4 D5
P4 P5
R2
R13 C13
C2
P2
P13 D13
D2
G3
L3
J3
J11 J12
G12 L12
J13 J10
J2
J1
A5
V5
A10 V10
J14
J4
DQ31__DQ7 DQ30__DQ6 DQ29__DQ5 DQ28__DQ4 DQ27__DQ3 DQ26__DQ2 DQ25__DQ1 DQ24__DQ0 DQ23__DQ15 DQ22__DQ14 DQ21__DQ13 DQ20__DQ12 DQ19__DQ11 DQ18__DQ10 DQ17__DQ9 DQ16__DQ8 DQ15__DQ23 DQ14__DQ22 DQ13__DQ21 DQ12__DQ20 DQ11__DQ19 DQ10__DQ18 DQ9__DQ17 DQ8__DQ16 DQ7__DQ31 DQ6__DQ30 DQ5__DQ29 DQ4__DQ28 DQ3__DQ27 DQ2__DQ26 DQ1__DQ25 DQ0__DQ24
RFU_A12_NC A7_A8__A0_A10 A6_A11__A1_A9 A5_BA1__A3_BA3 A4_BA2__A2_BA0 A3_BA3__A5_BA1 A2_BA0__A4_BA2 A1_A9__A6_A11 A0_A10__A7_A8
WCK01__WCK23 WCK01#__WCK23#
WCK23__WCK01 WCK23#__WCK01#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
RAS#__CAS# CAS#__RAS#
CKE# CK# CK
CS#__WE# WE#__CS#
ZQ SEN
RESET# MF
Vpp_NC Vpp_NC1
VREFD1 VREFD2
VREFC
ABI#
23CNOPN001
U2200
VDDQ_B1
VDDQ_B3 VDDQ_B12 VDDQ_B14
VDDQ_D1
VDDQ_D3 VDDQ_D12 VDDQ_D14
VDDQ_E5 VDDQ_E10
VDDQ_F1
VDDQ_F3 VDDQ_F12 VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3 VDDQ_H12
VDDQ_K3 VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3 VDDQ_M12 VDDQ_M14
VDDQ_N5 VDDQ_N10
VDDQ_P1
VDDQ_P3 VDDQ_P12 VDDQ_P14
VDDQ_T1
VDDQ_T3 VDDQ_T12 VDDQ_T14
VDD_C5 VDD_C10 VDD_D11
VDD_G1
VDD_G4
VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14 VDD_P11
VDD_R5 VDD_R10
VSSQ_A1
VSSQ_A3 VSSQ_A12 VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4 VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E1
VSSQ_E3 VSSQ_E12 VSSQ_E14
VSSQ_F5 VSSQ_F10
VSSQ_H2 VSSQ_H13
VSSQ_K2 VSSQ_K13
VSSQ_M5 VSSQ_M10
VSSQ_N1
VSSQ_N3 VSSQ_N12 VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4 VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V1
VSSQ_V3 VSSQ_V12 VSSQ_V14
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
+MVDD
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
+MVDD
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12
+MVDD
E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
+MVDD
R2301 1%60.4R R2300 1%60.4R
+MVDD
R2302 120R 1% R2303 1K 5%
R2304 5%1K
R2309 1%2.37K R2310 1%5.49K
C2305 6.3V1uF
5
5
DQB1_<5>
3
3,5
BI
6
DQB1_<6>
3,5
BI
4
DQB1_<4>
3,5
BI
7
DQB1_<7>
3,5
BI
3
DQB1_<3>
3,5
BI
2
DQB1_<2>
3,5
BI
1
DQB1_<1>
3,5
BI
0
DQB1_<0>
3,5
BI
11
DQB1_<11>
3,5
BI
10
DQB1_<10>
3,5
BI
8
DQB1_<8>
3,5
BI
9
DQB1_<9>
3,5
BI
12
DQB1_<12>
3,5
BI
13
DQB1_<13>
3,5
BI
14
DQB1_<14>
3,5
BI
15
DQB1_<15>
3,5
BI
25
DQB1_<25>
3,5
BI
24
DQB1_<24>
3,5
BI
27
DQB1_<27>
3,5
BI
26
DQB1_<26>
3,5
BI
29
DQB1_<29>
3,5
BI
30
DQB1_<30>
3,5
BI
28
DQB1_<28>
3,5
BI
31
DQB1_<31>
3,5
BI
17
DQB1_<17>
3,5
BI
16
DQB1_<16>
3,5
BI
18
DQB1_<18>
3,5
BI
19
DQB1_<19>
3,5
BI
20
DQB1_<20>
3,5
BI
22
DQB1_<22>
3,5
BI
21
DQB1_<21>
3,5
BI
23
DQB1_<23>
3,5
BI
5
8
MAB1_<8>
3
3,5
BI
0
MAB1_<0>
3,5
BI
1
MAB1_<1>
3,5
BI
3
MAB1_<3>
3,5
BI
2
MAB1_<2>
3,5
BI
5
MAB1_<5>
3,5
BI
4
MAB1_<4>
3,5
BI
6
MAB1_<6>
3,5
BI
7
MAB1_<7>
3,5
BI
WCKB1_1
3
IN
WCKB1B_1
3
IN
WCKB1_0
3
IN
WCKB1B_0
3
IN
EDCB1_0
3
OUT
EDCB1_1
3
OUT
EDCB1_3
3
OUT
EDCB1_2
3
OUT
DDBIB1_0
3
BI
DDBIB1_1
3
BI
DDBIB1_3
3
BI
DDBIB1_2
3
BI
CASB1B
3
IN
RASB1B
3
IN
CKEB1
3
IN
CLKB1B
3
IN
CLKB1
3
IN
WEB1B
3
IN
CSB1B_0
3
IN
DRAM_RST1
3,5
IN
ADBIB1
3
IN
M2 M4
N2 N4 T2 T4 V2
V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5 K10 K11 H10 H11
H5
H4
D4
D5
P4
P5
R2 R13 C13
C2
P2 P13 D13
D2
G3
L3
J3
J11 J12
G12
L12
J13 J10
J2
J1
A5
V5
A10 V10
J14
J4
DQ31__DQ7 DQ30__DQ6 DQ29__DQ5 DQ28__DQ4 DQ27__DQ3 DQ26__DQ2 DQ25__DQ1 DQ24__DQ0 DQ23__DQ15 DQ22__DQ14 DQ21__DQ13 DQ20__DQ12 DQ19__DQ11 DQ18__DQ10 DQ17__DQ9 DQ16__DQ8 DQ15__DQ23 DQ14__DQ22 DQ13__DQ21 DQ12__DQ20 DQ11__DQ19 DQ10__DQ18 DQ9__DQ17 DQ8__DQ16 DQ7__DQ31 DQ6__DQ30 DQ5__DQ29 DQ4__DQ28 DQ3__DQ27 DQ2__DQ26 DQ1__DQ25 DQ0__DQ24
RFU_A12_NC A7_A8__A0_A10 A6_A11__A1_A9 A5_BA1__A3_BA3 A4_BA2__A2_BA0 A3_BA3__A5_BA1 A2_BA0__A4_BA2 A1_A9__A6_A11 A0_A10__A7_A8
WCK01__WCK23 WCK01#__WCK23#
WCK23__WCK01 WCK23#__WCK01#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
RAS#__CAS# CAS#__RAS#
CKE# CK# CK
CS#__WE# WE#__CS#
ZQ SEN
RESET# MF
Vpp_NC Vpp_NC1
VREFD1 VREFD2
VREFC
ABI#
GDDR5
23CNOPN001
VDDQ_B1
VDDQ_B3 VDDQ_B12 VDDQ_B14
VDDQ_D1
VDDQ_D3 VDDQ_D12 VDDQ_D14
VDDQ_E5 VDDQ_E10
VDDQ_F1
VDDQ_F3 VDDQ_F12 VDDQ_F14
VDDQ_G2 VDDQ_G13
VDDQ_H3 VDDQ_H12
VDDQ_K3 VDDQ_K12
VDDQ_L2 VDDQ_L13
VDDQ_M1
VDDQ_M3 VDDQ_M12 VDDQ_M14
VDDQ_N5 VDDQ_N10
VDDQ_P1
VDDQ_P3 VDDQ_P12 VDDQ_P14
VDDQ_T1
VDDQ_T3 VDDQ_T12 VDDQ_T14
VDD_C5 VDD_C10 VDD_D11
VDD_G1
VDD_G4
VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14 VDD_P11
VDD_R5 VDD_R10
VSSQ_A1
VSSQ_A3 VSSQ_A12 VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4 VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E1
VSSQ_E3 VSSQ_E12 VSSQ_E14
VSSQ_F5 VSSQ_F10
VSSQ_H2 VSSQ_H13
VSSQ_K2 VSSQ_K13
VSSQ_M5 VSSQ_M10
VSSQ_N1
VSSQ_N3 VSSQ_N12 VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4 VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V1
VSSQ_V3 VSSQ_V12 VSSQ_V14
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
+MVDD
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
+MVDD
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
DD
DD
DD
C
C
C
BB
BB
BB
U2300
+MVDD
C20080.1uF
C20090.1uF
C20100.1uF
C20120.1uF
C20130.1uF
C20140.1uF
A
A
A
C20070.1uF
C20150.1uF
D D
+MVDD
C20231uF
C20241uF
C20251uF
C20261uF
C20281uF
C20191uF
C20201uF
8
8
8
1
C20291uF
+MVDD
C21170.1uF
C21100.1uF
C21120.1uF
C21150.1uF
C21070.1uF
C21080.1uF
+MVDD
C204010uF
C204110uF
C21181uF
C21191uF
7
7
7
2
C21160.1uF
C21090.1uF
C21211uF
C21221uF
C21261uF
C21271uF
C21201uF
C21291uF
+MVDD
C2218
C22120.1uF
C22130.1uF
C22060.1uF
C22080.1uF
+MVDD
C214010uF
C214110uF
C22191uF
C22201uF
6
6
6
3
C22140.1uF
C22090.1uF
C22110.1uF
0.1uF
C22271uF
C22281uF
C22291uF
C22231uF
C22301uF
C22261uF
+MVDD
C23060.1uF
C23120.1uF
+MVDD
C224010uF
C224110uF
C23191uF
C23211uF C23080.1uF
C23221uF C23090.1uF
C23231uF C23110.1uF
C23241uF
5
5
5
4
+MVDD
MC204010uF
MC214110uF
MC214010uF
MC234010uF
MC224110uF
MC224010uF
MC204110uF
C23170.1uF
C23140.1uF
C23160.1uF
DRAM SCAN PINS SSH [J2] - SCAN SHIFT
C234010uF
C234110uF
SCK [G12] - SCAN CLOCK SOUT [C2] - SCAN OUTPUT SEN [J10] - SCAN ENABLE SOE# [J1] - SCAN OUTPUT ENABLE
4
4
4
5
C23251uF
C23261uF
C23281uF
MC234110uF
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG #48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
GDDR5 MEM CH AB
GDDR5 MEM CH AB
GDDR5 MEM CH AB
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:20 2015 1.0
Thu Jan 15 02:26:20 2015 1.0
Thu Jan 15 02:26:20 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
523
523
523
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
REV:
REV:
REV:
responsibility for any consequences resulting from use of the information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
1
1
1
8
A
A
A
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(6) GDDR5 MEMORY CH C/D
6
14
DQC0_<14>
4
4,6
BI
15
DQC0_<15>
4,6
BI
13
DQC0_<13>
4,6
BI
12
DQC0_<12>
4,6
BI
11
DQC0_<11>
4,6
BI
9
DQC0_<9>
4,6
BI
10
DQC0_<10>
4,6
BI
8
DQC0_<8>
4,6
BI
6
DQC0_<6>
4,6
R2401 1%60.4R R2400 1%60.4R
R2403 1K 5%
R2404 5%1K
R2409 1%2.37K R2410 1%5.49K
C2405 6.3V1uF
C24070.1uF
C24080.1uF
BI
7
DQC0_<7>
4,6
BI
4
DQC0_<4>
4,6
BI
5
DQC0_<5>
4,6
BI
2
DQC0_<2>
4,6
BI
1
DQC0_<1>
4,6
BI
3
DQC0_<3>
4,6
BI
0
DQC0_<0>
4,6
BI
20
DQC0_<20>
4,6
BI
21
DQC0_<21>
4,6
BI
23
DQC0_<23>
4,6
BI
22
DQC0_<22>
4,6
BI
19
DQC0_<19>
4,6
BI
18
DQC0_<18>
4,6
BI
17
DQC0_<17>
4,6
BI
16
DQC0_<16>
4,6
BI
26
DQC0_<26>
4,6
BI
25
DQC0_<25>
4,6
BI
27
DQC0_<27>
4,6
BI
24
DQC0_<24>
4,6
BI
28
DQC0_<28>
4,6
BI
29
DQC0_<29>
4,6
BI
30
DQC0_<30>
4,6
BI
31
DQC0_<31>
4,6
BI
6
8
MAC0_<8>
4
4,6
BI
7
MAC0_<7>
4,6
BI
6
MAC0_<6>
4,6
BI
5
MAC0_<5>
4,6
BI
4
MAC0_<4>
4,6
BI
3
MAC0_<3>
4,6
BI
2
MAC0_<2>
4,6
BI
1
MAC0_<1>
4,6
BI
0
MAC0_<0>
4,6
BI
WCKC0_1
4
IN
WCKC0B_1
4
IN
WCKC0_0
4
IN
WCKC0B_0
4
IN
EDCC0_1
4
OUT
EDCC0_0
4
OUT
EDCC0_2
4
OUT
EDCC0_3
4
OUT
DDBIC0_1
4
BI
DDBIC0_0
4
BI
DDBIC0_2
4
BI
DDBIC0_3
4
BI
RASC0B
4
IN
CASC0B
4
IN
CKEC0
4
IN
CLKC0B
4
IN
CLKC0
4
IN
CSC0B_0
4
IN
WEC0B
4
IN
R2402 1%120R
C24090.1uF
ZQ_C0 ZQ_C1 ZQ_D0 ZQ_D1 SEN_C0 SEN_C1 SEN_D0 SEN_D1
DRAM_RST2
4,6
IN
MF_C0 MF_C1 MF_D0 MF_D1
VREFC_C0 VREFC_C1 VREFC_D0 VREFC_D1
ADBIC0
4
IN
C24140.1uF
C24150.1uF
C24100.1uF
C24110.1uF
C24130.1uF
A A
C
C
C
B B
+MVDD
C C
+MVDD
+MVDD
A
A
A
23CNOPN001
U2400
M2
DQ31__DQ7
M4
DQ30__DQ6
N2
DQ29__DQ5
N4
DQ28__DQ4
T2
DQ27__DQ3
T4
DQ26__DQ2
V2
DQ25__DQ1
V4
DQ24__DQ0
M13
DQ23__DQ15
M11
DQ22__DQ14
N13
DQ21__DQ13
N11
DQ20__DQ12
T13
DQ19__DQ11
T11
DQ18__DQ10
V13
DQ17__DQ9
V11
DQ16__DQ8
F13
DQ15__DQ23
F11
DQ14__DQ22
E13
DQ13__DQ21
E11
DQ12__DQ20
B13
DQ11__DQ19
B11
DQ10__DQ18
A13
DQ9__DQ17
A11
DQ8__DQ16
F2
DQ7__DQ31
F4
DQ6__DQ30
E2
DQ5__DQ29
E4
DQ4__DQ28
B2
DQ3__DQ27
B4
DQ2__DQ26
A2
DQ1__DQ25
A4
DQ0__DQ24
J5
RFU_A12_NC
K4
A7_A8__A0_A10
K5
A6_A11__A1_A9
K10
A5_BA1__A3_BA3
K11
A4_BA2__A2_BA0
H10
A3_BA3__A5_BA1
H11
A2_BA0__A4_BA2
H5
A1_A9__A6_A11
H4
A0_A10__A7_A8
D4
WCK01__WCK23
D5
WCK01#__WCK23#
P4
WCK23__WCK01
P5
WCK23#__WCK01#
R2
EDC3__EDC0
R13
EDC2__EDC1
C13
EDC1__EDC2
C2
EDC0__EDC3
P2
DBI3#__DBI0#
P13
DBI2#__DBI1#
D13
DBI1#__DBI2#
D2
DBI0#__DBI3#
G3
RAS#__CAS#
L3
CAS#__RAS#
J3
CKE#
J11
CK#
J12
CK
G12
CS#__WE#
L12
WE#__CS#
J13
ZQ
J10
SEN
J2
RESET#
J1
MF
A5
Vpp_NC
V5
Vpp_NC1
A10
VREFD1
V10
VREFD2
J14
VREFC
J4
ABI#
+MVDD
C25060.1uF
C25070.1uF
D D
+MVDD
C24231uF
C24171uF
C24181uF
C24191uF
8
8
8
1
C24251uF
C24201uF
C24211uF
C24221uF
+MVDD
C244010uF
C244110uF
C25211uF
C25221uF
7
7
7
2
+MVDD
B1
VDDQ_B1
B3
VDDQ_B3
B12
VDDQ_B12
B14
VDDQ_B14
D1
VDDQ_D1
D3
VDDQ_D3
D12
VDDQ_D12
D14
VDDQ_D14
E5
VDDQ_E5
E10
VDDQ_E10
F1
VDDQ_F1
F3
VDDQ_F3
F12
VDDQ_F12
F14
VDDQ_F14
G2
VDDQ_G2
G13
VDDQ_G13
H3
VDDQ_H3
H12
VDDQ_H12
K3
VDDQ_K3
K12
VDDQ_K12
L2
VDDQ_L2
L13
VDDQ_L13
M1
VDDQ_M1
M3
VDDQ_M3
M12
VDDQ_M12
M14
VDDQ_M14
N5
VDDQ_N5
N10
VDDQ_N10
P1
VDDQ_P1
P3
VDDQ_P3
P12
VDDQ_P12
P14
VDDQ_P14
T1
VDDQ_T1
T3
VDDQ_T3
T12
VDDQ_T12
T14
VDDQ_T14
+MVDD
C5
VDD_C5
C10
VDD_C10
D11
VDD_D11
G1
VDD_G1
G4
VDD_G4
G11
VDD_G11
G14
VDD_G14
L1
VDD_L1
L4
VDD_L4
L11
VDD_L11
L14
VDD_L14
P11
VDD_P11
R5
VDD_R5
R10
VDD_R10
A1
VSSQ_A1
A3
VSSQ_A3
A12
VSSQ_A12
A14
VSSQ_A14
C1
VSSQ_C1
C3
VSSQ_C3
C4
VSSQ_C4
C11
VSSQ_C11
C12
VSSQ_C12
C14
VSSQ_C14
E1
VSSQ_E1
E3
VSSQ_E3
E12
VSSQ_E12
E14
VSSQ_E14
F5
VSSQ_F5
F10
VSSQ_F10
H2
VSSQ_H2
H13
VSSQ_H13
K2
VSSQ_K2
K13
VSSQ_K13
M5
VSSQ_M5
M10
VSSQ_M10
N1
VSSQ_N1
N3
VSSQ_N3
N12
VSSQ_N12
N14
VSSQ_N14
R1
VSSQ_R1
R3
VSSQ_R3
R4
VSSQ_R4
R11
VSSQ_R11
R12
VSSQ_R12
R14
VSSQ_R14
V1
VSSQ_V1
V3
VSSQ_V3
V12
VSSQ_V12
V14
VSSQ_V14
B5
VSS_B5
B10
VSS_B10
D10
VSS_D10
G5
VSS_G5
G10
VSS_G10
H1
VSS_H1
H14
VSS_H14
K1
VSS_K1
K14
VSS_K14
L5
VSS_L5
L10
VSS_L10
P10
VSS_P10
T5
VSS_T5
T10
VSS_T10
C25090.1uF
C25120.1uF
C25130.1uF
C25231uF C25080.1uF
C25241uF
C25251uF
C2526
1uF
+MVDD
R2501 1%60.4R R2500 1%60.4R
R2503 5%1K
R2504 5%1K
+MVDD
R2509 1%2.37K
+MVDD
R2510 1%5.49K
C2505 6.3V1uF
+MVDD
C25190.1uF
C25150.1uF
C25271uF
C25281uF
C254010uF
C26070.1uF
+MVDD
C254110uF
C26171uF
6
6
6
3
6
20
DQC1_<20>
4
4,6
BI
21
DQC1_<21>
4,6
BI
23
DQC1_<23>
4,6
BI
22
DQC1_<22>
4,6
BI
19
DQC1_<19>
4,6
BI
18
DQC1_<18>
4,6
BI
17
DQC1_<17>
4,6
BI
16
DQC1_<16>
4,6
BI
26
DQC1_<26>
4,6
BI
25
DQC1_<25>
4,6
BI
27
DQC1_<27>
4,6
BI
24
DQC1_<24>
4,6
BI
28
DQC1_<28>
4,6
BI
29
DQC1_<29>
4,6
BI
30
DQC1_<30>
4,6
BI
31
DQC1_<31>
4,6
BI
14
DQC1_<14>
4,6
BI
15
DQC1_<15>
4,6
BI
13
DQC1_<13>
4,6
BI
12
DQC1_<12>
4,6
BI
10
DQC1_<10>
4,6
BI
8
DQC1_<8>
4,6
BI
11
DQC1_<11>
4,6
BI
9
DQC1_<9>
4,6
BI
1
DQC1_<1>
4,6
BI
6
DQC1_<6>
4,6
BI
2
DQC1_<2>
4,6
BI
7
DQC1_<7>
4,6
BI
3
DQC1_<3>
4,6
BI
5
DQC1_<5>
4,6
BI
0
DQC1_<0>
4,6
BI
4
DQC1_<4>
4,6
BI
6
8
MAC1_<8>
4
4,6
BI
0
MAC1_<0>
4,6
BI
1
MAC1_<1>
4,6
BI
3
MAC1_<3>
4,6
BI
2
MAC1_<2>
4,6
BI
5
MAC1_<5>
4,6
BI
4
MAC1_<4>
4,6
BI
6
MAC1_<6>
4,6
BI
7
MAC1_<7>
4,6
BI
WCKC1_0
4
IN
WCKC1B_0
4
IN
WCKC1_1
4
IN
WCKC1B_1
4
IN
EDCC1_2
4
OUT
EDCC1_3
4
OUT
EDCC1_1
4
OUT
EDCC1_0
4
OUT
DDBIC1_2
4
BI
DDBIC1_3
4
BI
DDBIC1_1
4
BI
DDBIC1_0
4
BI
CASC1B
4
IN
RASC1B
4
IN
CKEC1
4
IN
CLKC1B
4
IN
CLKC1
4
IN
WEC1B
4
IN
CSC1B_0
4
IN
R2502 1%120R
DRAM_RST2
4,6
IN
ADBIC1
4
IN
C26090.1uF
C26110.1uF
C26120.1uF
C26130.1uF
C26140.1uF
C26191uF C26080.1uF
C26201uF
C26211uF C26100.1uF
C26221uF
C26231uF
C26241uF
C26251uF
C264010uF
M2 M4 N2 N4 T2 T4 V2
V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5 K10 K11 H10 H11
H5
H4
D4
D5
P4
P5
R2 R13 C13
C2
P2 P13 D13
D2
G3
L3
J3 J11 J12
G12 L12
J13 J10
J2
J1
A5
V5
A10 V10
J14
J4
C264110uF
DQ31__DQ7 DQ30__DQ6 DQ29__DQ5 DQ28__DQ4 DQ27__DQ3 DQ26__DQ2 DQ25__DQ1 DQ24__DQ0 DQ23__DQ15 DQ22__DQ14 DQ21__DQ13 DQ20__DQ12 DQ19__DQ11 DQ18__DQ10 DQ17__DQ9 DQ16__DQ8 DQ15__DQ23 DQ14__DQ22 DQ13__DQ21 DQ12__DQ20 DQ11__DQ19 DQ10__DQ18 DQ9__DQ17 DQ8__DQ16 DQ7__DQ31 DQ6__DQ30 DQ5__DQ29 DQ4__DQ28 DQ3__DQ27 DQ2__DQ26 DQ1__DQ25 DQ0__DQ24
RFU_A12_NC A7_A8__A0_A10 A6_A11__A1_A9 A5_BA1__A3_BA3 A4_BA2__A2_BA0 A3_BA3__A5_BA1 A2_BA0__A4_BA2 A1_A9__A6_A11 A0_A10__A7_A8
WCK01__WCK23 WCK01#__WCK23#
WCK23__WCK01 WCK23#__WCK01#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
RAS#__CAS# CAS#__RAS#
CKE# CK# CK
CS#__WE# WE#__CS#
ZQ SEN
RESET# MF
Vpp_NC Vpp_NC1
VREFD1 VREFD2
VREFC
ABI#
23CNOPN001
+MVDD
+MVDD
U2500
C27070.1uF
C27171uF
5
5
5
4
+MVDD
B1
VDDQ_B1
B3
VDDQ_B3
B12
VDDQ_B12
B14
VDDQ_B14
D1
VDDQ_D1
D3
VDDQ_D3
D12
VDDQ_D12
D14
VDDQ_D14
E5
VDDQ_E5
E10
VDDQ_E10
F1
VDDQ_F1
F3
VDDQ_F3
F12
VDDQ_F12
F14
VDDQ_F14
G2
VDDQ_G2
G13
VDDQ_G13
H3
VDDQ_H3
H12
VDDQ_H12
K3
VDDQ_K3
K12
VDDQ_K12
L2
VDDQ_L2
L13
VDDQ_L13
M1
VDDQ_M1
M3
VDDQ_M3
M12
VDDQ_M12
M14
VDDQ_M14
N5
VDDQ_N5
N10
VDDQ_N10
P1
VDDQ_P1
P3
VDDQ_P3
P12
VDDQ_P12
P14
VDDQ_P14
T1
VDDQ_T1
T3
VDDQ_T3
T12
VDDQ_T12
T14
VDDQ_T14
+MVDD
C5
VDD_C5
C10
VDD_C10
D11
VDD_D11
G1
VDD_G1
G4
VDD_G4
G11
VDD_G11
G14
VDD_G14
L1
VDD_L1
L4
VDD_L4
L11
VDD_L11
L14
VDD_L14
P11
VDD_P11
R5
VDD_R5
R10
VDD_R10
A1
VSSQ_A1
A3
VSSQ_A3
A12
VSSQ_A12
A14
VSSQ_A14
C1
VSSQ_C1
C3
VSSQ_C3
C4
VSSQ_C4
C11
VSSQ_C11
C12
VSSQ_C12
C14
VSSQ_C14
E1
VSSQ_E1
E3
VSSQ_E3
E12
VSSQ_E12
E14
VSSQ_E14
F5
VSSQ_F5
F10
VSSQ_F10
H2
VSSQ_H2
H13
VSSQ_H13
K2
VSSQ_K2
K13
VSSQ_K13
M5
VSSQ_M5
M10
VSSQ_M10
N1
VSSQ_N1
N3
VSSQ_N3
N12
VSSQ_N12
N14
VSSQ_N14
R1
VSSQ_R1
R3
VSSQ_R3
R4
VSSQ_R4
R11
VSSQ_R11
R12
VSSQ_R12
R14
VSSQ_R14
V1
VSSQ_V1
V3
VSSQ_V3
V12
VSSQ_V12
V14
VSSQ_V14
B5
VSS_B5
B10
VSS_B10
D10
VSS_D10
G5
VSS_G5
G10
VSS_G10
H1
VSS_H1
H14
VSS_H14
K1
VSS_K1
K14
VSS_K14
L5
VSS_L5
L10
VSS_L10
P10
VSS_P10
T5
VSS_T5
T10
VSS_T10
C27080.1uF
C27201uF C27110.1uF
C27211uF C27120.1uF
C27181uF
C27191uF C27100.1uF
+MVDD
R2601 1%60.4R R2600 1%60.4R
R2603 5%1K
R2604 5%1K
R2609 1%2.37K
+MVDD
R2610 5.49K 1% C2605 6.3V1uF
+MVDD
12
MC254110uF
C2800
330uF
2.5V
C274110uF
MC254010uF
DRAM SCAN PINS SSH [J2] - SCAN SHIFT SCK [G12] - SCAN CLOCK SOUT [C2] - SCAN OUTPUT SEN [J10] - SCAN ENABLE SOE# [J1] - SCAN OUTPUT ENABLE
+
C27140.1uF
C27150.1uF
C27160.1uF
C27221uF
C27231uF
C27241uF
C274010uF
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4,6
BI
4 4
4 4
4 4 4 4
4 4 4 4
4 4
4 4 4
4 4
R2602 1%120R
4,6
4
MC244010uF
MC274110uF
MC274010uF
4
4
4
5
6
13
DQD0_<13>
4
15
DQD0_<15>
12
DQD0_<12>
14
DQD0_<14>
11
DQD0_<11>
9
DQD0_<9>
10
DQD0_<10>
8
DQD0_<8>
7
DQD0_<7>
6
DQD0_<6>
4
DQD0_<4>
5
DQD0_<5>
0
DQD0_<0>
2
DQD0_<2>
1
DQD0_<1>
3
DQD0_<3>
20
DQD0_<20>
21
DQD0_<21>
23
DQD0_<23>
22
DQD0_<22>
19
DQD0_<19>
17
DQD0_<17>
18
DQD0_<18>
16
DQD0_<16>
26
DQD0_<26>
25
DQD0_<25>
27
DQD0_<27>
24
DQD0_<24>
28
DQD0_<28>
29
DQD0_<29>
30
DQD0_<30>
31
DQD0_<31>
6
8
MAD0_<8>
4
7
MAD0_<7>
6
MAD0_<6>
5
MAD0_<5>
4
MAD0_<4>
3
MAD0_<3>
2
MAD0_<2>
1
MAD0_<1>
0
MAD0_<0>
WCKD0_1
IN
WCKD0B_1
IN
WCKD0_0
IN
WCKD0B_0
IN
EDCD0_1
OUT
EDCD0_0
OUT
EDCD0_2
OUT
EDCD0_3
OUT
DDBID0_1
BI
DDBID0_0
BI
DDBID0_2
BI
DDBID0_3
BI
RASD0B
IN
CASD0B
IN
CKED0
IN
CLKD0B
IN
CLKD0
IN
CSD0B_0
IN
WED0B
IN
DRAM_RST2
IN
ADBID0
IN
MC264110uF
MC264010uF
MC244110uF
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
23CNOPN001
U2600
M2
DQ31__DQ7
M4
DQ30__DQ6
N2
DQ29__DQ5
N4
DQ28__DQ4
T2
DQ27__DQ3
T4
DQ26__DQ2
V2
DQ25__DQ1
V4
DQ24__DQ0
M13
DQ23__DQ15
M11
DQ22__DQ14
N13
DQ21__DQ13
N11
DQ20__DQ12
T13
DQ19__DQ11
T11
DQ18__DQ10
V13
DQ17__DQ9
V11
DQ16__DQ8
F13
DQ15__DQ23
F11
DQ14__DQ22
E13
DQ13__DQ21
E11
DQ12__DQ20
B13
DQ11__DQ19
B11
DQ10__DQ18
A13
DQ9__DQ17
A11
DQ8__DQ16
F2
DQ7__DQ31
F4
DQ6__DQ30
E2
DQ5__DQ29
E4
DQ4__DQ28
B2
DQ3__DQ27
B4
DQ2__DQ26
A2
DQ1__DQ25
A4
DQ0__DQ24
J5
RFU_A12_NC
K4
A7_A8__A0_A10
K5
A6_A11__A1_A9
K10
A5_BA1__A3_BA3
K11
A4_BA2__A2_BA0
H10
A3_BA3__A5_BA1
H11
A2_BA0__A4_BA2
H5
A1_A9__A6_A11
H4
A0_A10__A7_A8
D4
WCK01__WCK23
D5
WCK01#__WCK23#
P4
WCK23__WCK01
P5
WCK23#__WCK01#
R2
EDC3__EDC0
R13
EDC2__EDC1
C13
EDC1__EDC2
C2
EDC0__EDC3
P2
DBI3#__DBI0#
P13
DBI2#__DBI1#
D13
DBI1#__DBI2#
D2
DBI0#__DBI3#
G3
RAS#__CAS#
L3
CAS#__RAS#
J3
CKE#
J11
CK#
J12
CK
G12
CS#__WE#
L12
WE#__CS#
J13
ZQ
J10
SEN
J2
RESET#
J1
MF
A5
Vpp_NC
V5
Vpp_NC1
A10
VREFD1
V10
VREFD2
J14
VREFC
J4
ABI#
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG #48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
GDDR5 MEM CH CD
GDDR5 MEM CH CD
GDDR5 MEM CH CD
Thu Jan 15 02:26:21 2015 1.0
Thu Jan 15 02:26:21 2015 1.0
Thu Jan 15 02:26:21 2015 1.0
623
623
623
VDDQ_B1
VDDQ_B3 VDDQ_B12 VDDQ_B14
VDDQ_D1
VDDQ_D3 VDDQ_D12 VDDQ_D14
VDDQ_E5 VDDQ_E10
VDDQ_F1
VDDQ_F3 VDDQ_F12 VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3 VDDQ_H12
VDDQ_K3 VDDQ_K12
VDDQ_L2 VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12 VDDQ_M14
VDDQ_N5 VDDQ_N10
VDDQ_P1
VDDQ_P3 VDDQ_P12 VDDQ_P14
VDDQ_T1
VDDQ_T3 VDDQ_T12 VDDQ_T14
VDD_C5 VDD_C10 VDD_D11
VDD_G1
VDD_G4
VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14 VDD_P11
VDD_R5 VDD_R10
VSSQ_A1
VSSQ_A3 VSSQ_A12 VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4 VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E1
VSSQ_E3 VSSQ_E12 VSSQ_E14
VSSQ_F5 VSSQ_F10
VSSQ_H2 VSSQ_H13
VSSQ_K2 VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3 VSSQ_N12 VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4 VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V1
VSSQ_V3 VSSQ_V12 VSSQ_V14
VSS_B5 VSS_B10 VSS_D10
VSS_G5
VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
+MVDD
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
+MVDD
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
+MVDD
+MVDD
REV:
REV:
REV:
R2701 1%60.4R R2700 1%60.4R
R2703 5%1K
R2704 5%1K
+MVDD
R2709 1%2.37K R2710 1%5.49K
C2705 6.3V1uF
6
5
DQD1_<5>
4
4,6
BI
6
DQD1_<6>
4,6
BI
7
DQD1_<7>
4,6
BI
4
DQD1_<4>
4,6
BI
3
DQD1_<3>
4,6
BI
1
DQD1_<1>
4,6
BI
2
DQD1_<2>
4,6
BI
0
DQD1_<0>
4,6
BI
10
DQD1_<10>
4,6
BI
9
DQD1_<9>
4,6
BI
11
DQD1_<11>
4,6
BI
8
DQD1_<8>
4,6
BI
12
DQD1_<12>
4,6
BI
13
DQD1_<13>
4,6
BI
14
DQD1_<14>
4,6
BI
15
DQD1_<15>
4,6
BI
24
DQD1_<24>
4,6
BI
25
DQD1_<25>
4,6
BI
27
DQD1_<27>
4,6
BI
26
DQD1_<26>
4,6
BI
30
DQD1_<30>
4,6
BI
29
DQD1_<29>
4,6
BI
31
DQD1_<31>
4,6
BI
28
DQD1_<28>
4,6
BI
17
DQD1_<17>
4,6
BI
16
DQD1_<16>
4,6
BI
18
DQD1_<18>
4,6
BI
19
DQD1_<19>
4,6
BI
21
DQD1_<21>
4,6
BI
22
DQD1_<22>
4,6
BI
20
DQD1_<20>
4,6
BI
23
DQD1_<23>
4,6
BI
6
8
MAD1_<8>
4
4,6
BI
0
MAD1_<0>
4,6
BI
1
MAD1_<1>
4,6
BI
3
MAD1_<3>
4,6
BI
2
MAD1_<2>
4,6
BI
5
MAD1_<5>
4,6
BI
4
MAD1_<4>
4,6
BI
6
MAD1_<6>
4,6
BI
7
MAD1_<7>
4,6
BI
WCKD1_1
4
IN
WCKD1B_1
4
IN
WCKD1_0
4
IN
WCKD1B_0
4
IN
EDCD1_0
4
OUT
EDCD1_1
4
OUT
EDCD1_3
4
OUT
EDCD1_2
4
OUT
DDBID1_0
4
BI
DDBID1_1
4
BI
DDBID1_3
4
BI
DDBID1_2
4
BI
CASD1B
4
IN
RASD1B
4
IN
CKED1
4
IN
CLKD1B
4
IN
CLKD1
4
IN
WED1B
4
IN
CSD1B_0
4
IN
R2702 1%120R
DRAM_RST2
4,6
IN
ADBID1
4
IN
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
M2 M4 N2 N4 T2 T4 V2
V4 M13 M11 N13 N11 T13 T11 V13 V11 F13 F11 E13 E11 B13 B11 A13 A11
F2
F4
E2
E4
B2
B4
A2
A4
J5 K4 K5
K10 K11 H10 H11
H5 H4
D4 D5
P4 P5
R2
R13 C13
C2
P2
P13 D13
D2
G3
L3
J3
J11 J12
G12 L12
J13 J10
J2
J1
A5 V5
A10 V10
J14
J4
DQ31__DQ7 DQ30__DQ6 DQ29__DQ5 DQ28__DQ4 DQ27__DQ3 DQ26__DQ2 DQ25__DQ1 DQ24__DQ0 DQ23__DQ15 DQ22__DQ14 DQ21__DQ13 DQ20__DQ12 DQ19__DQ11 DQ18__DQ10 DQ17__DQ9 DQ16__DQ8 DQ15__DQ23 DQ14__DQ22 DQ13__DQ21 DQ12__DQ20 DQ11__DQ19 DQ10__DQ18 DQ9__DQ17 DQ8__DQ16 DQ7__DQ31 DQ6__DQ30 DQ5__DQ29 DQ4__DQ28 DQ3__DQ27 DQ2__DQ26 DQ1__DQ25 DQ0__DQ24
RFU_A12_NC A7_A8__A0_A10 A6_A11__A1_A9 A5_BA1__A3_BA3 A4_BA2__A2_BA0 A3_BA3__A5_BA1 A2_BA0__A4_BA2 A1_A9__A6_A11 A0_A10__A7_A8
WCK01__WCK23 WCK01#__WCK23#
WCK23__WCK01 WCK23#__WCK01#
EDC3__EDC0 EDC2__EDC1 EDC1__EDC2 EDC0__EDC3
DBI3#__DBI0# DBI2#__DBI1# DBI1#__DBI2# DBI0#__DBI3#
RAS#__CAS# CAS#__RAS#
CKE# CK# CK
CS#__WE# WE#__CS#
ZQ SEN
RESET# MF
Vpp_NC Vpp_NC1
VREFD1 VREFD2
VREFC
ABI#
23CNOPN001
U2700
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
VDDQ_B1
VDDQ_B3 VDDQ_B12 VDDQ_B14
VDDQ_D1
VDDQ_D3 VDDQ_D12 VDDQ_D14
VDDQ_E5 VDDQ_E10
VDDQ_F1
VDDQ_F3 VDDQ_F12 VDDQ_F14
VDDQ_G2 VDDQ_G13
VDDQ_H3 VDDQ_H12
VDDQ_K3 VDDQ_K12
VDDQ_L2 VDDQ_L13
VDDQ_M1
VDDQ_M3 VDDQ_M12 VDDQ_M14
VDDQ_N5 VDDQ_N10
VDDQ_P1
VDDQ_P3 VDDQ_P12 VDDQ_P14
VDDQ_T1
VDDQ_T3 VDDQ_T12 VDDQ_T14
VDD_C5 VDD_C10 VDD_D11
VDD_G1
VDD_G4
VDD_G11 VDD_G14
VDD_L1
VDD_L4 VDD_L11 VDD_L14 VDD_P11
VDD_R5 VDD_R10
VSSQ_A1
VSSQ_A3 VSSQ_A12 VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4 VSSQ_C11 VSSQ_C12 VSSQ_C14
VSSQ_E1
VSSQ_E3 VSSQ_E12 VSSQ_E14
VSSQ_F5 VSSQ_F10
VSSQ_H2 VSSQ_H13
VSSQ_K2 VSSQ_K13
VSSQ_M5 VSSQ_M10
VSSQ_N1
VSSQ_N3 VSSQ_N12 VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4 VSSQ_R11 VSSQ_R12 VSSQ_R14
VSSQ_V1
VSSQ_V3 VSSQ_V12 VSSQ_V14
VSS_B5 VSS_B10 VSS_D10
VSS_G5 VSS_G10
VSS_H1 VSS_H14
VSS_K1 VSS_K14
VSS_L5 VSS_L10 VSS_P10
VSS_T5 VSS_T10
+MVDD
B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14
+MVDD
C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10
A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 V1 V3 V12 V14
B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10
1
1
1
8
DD
DD
DD
C
C
C
BB
BB
BB
A
A
A
1
MSI CONFIDENTIAL
00017967 jonepei(裴亮樂)
RD(C)2017031703 RMA工程課
石阿鋒 (00068760)
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(7) TRINIDAD GPIO STRAP CF XTAL
+1.8V
R5000
4.99K 1%
A A
B B
C
C
C
C C
D D
+1.8V
A
A
A
R5001
4.99K 1%
+1.8V
R5004
4.99K 1%
R5005
4.99K 1%
SCL/SDA BUS:
I2C ADDRESS
DDCVGA BUS:
I2C ADDRESS
0x98
+1.8V
R50 1%221R R51 110R 1%
C50 6.3V0.1uF
PS_0
C5000
0.082uF 16V
PS_2
C5002
0.082uF 16V
C29
10uF
6.3V
TP62
PAY ATTENTION TO THE GROUNDING STRATEGIES FOR THESE FILTER CAPACITORS TO MAINTAIN A CLOSE LOOP FOR CURRENT.
8
8
8
1
7
7
FUNCTION
FUNCTION
EXT TEMP SENSOR
C5
4.7uF
6.3V
+1.8V
B1
120R
+0.95V
B4
120R
+1.8V
B5
120R
+0.95V
B6
120R
+1.8V
B7
220R
+1.8V
R5002
4.99K 1%
PS_1
R5003
C5001
4.99K
0.082uF
1%
16V
7
+1.8V
R5006
4.99K 1%
PS_3
7
R5007
C5003
4.99K
0.082uF
1%
16V
7
7 7 7
1 2
1 2
1 2
1 2
C6
1uF
6.3V
DVOCLK
DVPCNTL_0 DVPCNTL_1 DVPCNTL_2
VREFG
DEVICE
DEVICE
LM96163
BF23
VDDR4#1
BF25
VDDR4#2
BG23
C7
VDDR4#3
1uF
BG25
VDDR4#4
6.3V
BC42
SWAPLOCKA
BE43
SWAPLOCKB
BG38
GENLK_CLK
BG39
GENLK_VSYNC
BD19
DVPCLK
BD26
DVPCNTL_0
BE28
DVPCNTL_1
BE19
DVPCNTL_2
BE29
DVPCNTL_MVP_0
BF29
DVPCNTL_MVP_1
BG36
VREFG
12
C24
10uF
6.3V
R33 1K 5%
U1H
PART 8 OF 18
D V P
PITCAIRN
+DPLL_PVDD
C13
C14
10uF
1uF
6.3V
6.3V
DNI
+DPLL_VDDC
C31
C16
4.7uF
1uF
6.3V
6.3V
DNI
+SPLL_PVDD
C18
C19
10uF
1uF
6.3V
6.3V
+SPLL_VDDC
C21
1uF
6.3V
+MPLL_PVDD
C34
C35
C26
4.7uF
4.7uF
1uF
6.3V
6.3V
6.3V
7
7
7
2
1
21
DVPDATA_10 DVPDATA_11
DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23
DNI
1
21
DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9
C15
0.1uF
6.3V
DNI
C17
0.1uF
6.3V
C20
0.1uF
6.3V
C22
0.1uF
6.3V
C27
0.1uF
6.3V
BI OUT
OUT BI
+3.3V_BUS
+1.8V
PS_0
7
PS_1
7
PS_2
7
PS_3
7
GPIO_3_SMBDATA GPIO_4_SMBCLK
DDCVGACLK DDCVGADATA
TEST_PWRGOOD
DVPDATA_0
BC21
DVPDATA_1
BE21
DVPDATA_2
BD21
DVPDATA_3
BE22
DVPDATA_4
BD22
DVPDATA_5
BC22
DVPDATA_6
BE23
DVPDATA_7
7
BD23
DVPDATA_8
BD25
DVPDATA_9
BC25
DVPDATA_10
BG26
DVPDATA_11
BE26
BE31 BD31 BG32 BE32 BD32 BE33 BD33 BE35 BD35 BE36 BD36 BC36
PLACE THE CROSSFIRE TEST POINTS NEAR THE ASIC AND NOT THE CONNECTOR
BM39
DPLL_PVDD
BK39
DPLL_PVSS
BJ40
DPLL_VDDC
BC29
SPLL_PVDD
BC28
SPLL_PVSS
BC26
SPLL_VDDC
H8
MPLL_PVDD#1
J9
MPLL_PVDD#2
L11
MPLL_PVDD#3
BB38
VDDR3
BB40
VDDR3
BC38
C1
VDDR3
1uF
BC39
VDDR3
6.3V
BB35
VDD_CT
BB36
VDD_CT
BB37
C30
VDD_CT
1uF
BC35
VDD_CT
6.3V
BD42
PS_0
BE42
PS_1
BF42
PS_2
BG42
PS_3
AY42
SMB_DAT
AV42
SMB_CLK
V47
SCL
V46
SDA
U50
DDCVGACLK
U52
DDCVGADATA
AY44
CEC_1
AV47
TEST_PG
AV48
NC
AV49
NC
BH16
NC
BH17
NC
BH43
NC
BJ16
NC
T48
NC
T49
NC
U48
NC
V51
NC
AW44
NC
BG43
NC
7 7 7 7 7 7 7
TP60
7 7 7
U1I
PART 9 OF 18
P L L S
X T A L
PITCAIRN
3
U1G
PART 7 OF 18
GPIO_5_REG_HOT
PITCAIRN
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_8P_DETECT
GPIO_17_THERMAL_INT
G
GPIO_18_HPD3
P I
GPIO_20_PWRCNTL_1
O
GPIO_22_ROMCSB
GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6
RSVD#7_DIGON
RSVD#8_VARYBL
GPIO_0 GPIO_1 GPIO_2
GPIO_6_TACH GPIO_7_BLON
GPIO_11 GPIO_12 GPIO_13
GPIO_19_CTF
GPIO_21
GPIO_29 GPIO_30
GENERICA GENERICB GENERICC GENERICD
CLKREQB
RSVD#1 RSVD#2 RSVD#3 RSVD#4 RSVD#5 RSVD#6
GPIO_0_VDDC_VID0
V49 BF39
GPIO_2
BD28
BD39
GPIO_6_TACH
V48 BD40 BE46 BF46 BG46
GPIO_11_PWRCNTL_3
AA44
GPIO_12_VDDC_VID4
BA50
GPIO_13_VDDC_VID5
BA52
GPIO_14_VDDC_VID3
AV45
GPIO_15_VDDC_VID1
W44 V45
GPIO_17_THERM_INT
AA45 AV44
GPIO_19_CTF
W43
GPIO_20_VDDC_VID2
W45 BF38
GPIO_22_ROMCSB
BE47
GPIO_29_VDDC_VID6
BF43
GPIO_30_VDDC_VID7
BE40
BH41 BE38 BE39
GENERICD
BG29
HPD4
BC31
HPD5
BC32
HPD6
BA48
HPD1
BE45
HPD1
AA43
AA47
TS_A
AM19 AR19 AN18 AM18 AN19 AR18 AV53 AV51
19,14
OUT
7
20,21
IN
7,19
OUT
19,14
OUT
19,14
OUT
19,14
OUT
19,14
OUT
21
IN
20
OUT
19,14
OUT
19,14
OUT
19,14
OUT
7
10
IN
10
IN
11
IN
9
IN
33R
1 8
RP1A
33R
2 7
RP1B
33R
3 6
RP1C
+3.3V_BUS
R14
2.2K 5%
33R
4 5
RP1D
GPIO_8_RGPIO_8_ROMSO GPIO_9_RGPIO_9_ROMSI GPIO_10_RGPIO_10_ROMSCK GPIO_22_R
MR8 10K 5%
+3.3V_BUS +3.3V_BUS
3 2 5 6 1
+3.3V_BUS
R8 5%10K
DNI
R10 10K 5%
R11 10K 5%
CROSSFIRE
LOWER CABLE CARD EDGE
schematic
614NOPN128
DVOCLK
7
CLK_1
DVPCNTL_2
7
DE_1
DVPDATA_1
7
7
DVPDATA_3
7
DVPDATA_5
7
DVPDATA_7
7
DVPDATA_9
7
DVPDATA_11
7
DVPCNTL_1
7
RSVD
GENERICD
7
FLOW_CONTROL_1
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
J2
DVPDATA_0
DVPDATA_2
DVPDATA_4
DVPDATA_6
DVPDATA_8
DVPDATA_10
DVPCNTL_0
GPIO_2
SWAP_LOCK_1
MR15 5%10K
7
7
7
7
7
7
7
7
DNI
Y2
R38 1M 1%
XIN_OSC_1
XOUT_OSC_1
5%0R
B5000
120R
C32
UNNAMED_7_CAP_I416_B
12
27.000MHz
UNNAMED_7_CAP_I412_A
C33
18pF
50V
1 2
R24 51.1R 1% R25 51.1R 1%
50V18pF
C12
18pF 50V
3
4
Y1
27.000MHz
1
2
R37 1%1M
C11
18pF
50V
+1.8V
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG #48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TRINIDAD GPIO STRAP CF XTAL
TRINIDAD GPIO STRAP CF XTAL
TRINIDAD GPIO STRAP CF XTAL
SHEET:
SHEET:
SHEET:
Thu Jan 15 02:26:22 2015 1.0
Thu Jan 15 02:26:22 2015 1.0
Thu Jan 15 02:26:22 2015 1.0
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
723
723
723
OF
OF
OF
105_C634xx_00B
105_C634xx_00B
105_C634xx_00B
3
3
3
6
6
6
6
BM41
XO_IN2
BK41
XO_IN
7
BN40
XTALIN
7
BL40
XTALOUT
+XTAL_VDDR
BF40
XTAL_VDDR
BG40
XTAL_VSS
CLKTESTA CLKTESTA_C
BM17
CLKTESTA
CLKTESTB CLKTESTB_C
BK17
CLKTESTB
XIN_OSC
7
XOUT_OSC
7
XIN_OSC
XOUT_OSC
C5100
4.7uF
6.3V
C23 6.3V0.1uF C28 0.1uF 6.3V
ROUTE 50OHMS SINGLE ENDED OR 100OHMS DIFFERENTIAL KEEP THEM SHORT
R60
1 2
0R 5%
1 2
1 2
0R 5%
5
5
5
4
R61
5%0R
R30
1 2
R31
VIDEO BIOS
FIRMWARE
WP SO SI
SCK
CE
PM25LV010A-100SC
DNI
DNI
DNI
U11
VDD
HOLD
GND
GPIO_11_PWRCNTL_3
GPIO_11_PWRCNTL_3
VSYNC
HSYNC
GPIO_28_TS_FDO
8 7
C4
0.1uF
6.3V
4
PIN BASED STRAPS
REV:
REV:
REV:
GPIO(13,12,11) - CONFIG[2..0] CONFIG[2]
CONFIG[1]
CONFIG[0]
7 19
HSYNC = AUD[1], VSYNC = AUD[0] AUD[0]
8
OUT
AUD[1]
8
OUT
HDMI MUST ONLY BE ENABLED ON SYSTMES THAT ARE LEGALLY ENTITLED. IT IS THE RESPONSIBILITY OF THE SYSTEM DESIGNER TO SUPPORT THIS FEATURE.
GPIO(8) - BIF_CLK_PM_EN 0 - DISABLE CLKREQb POWER MANAGEMENT CAPABILITY 1 - ENABLE CLKREQb POWER MANAGEMENT CAPABILITY ENSURE THAT NO LOGIC CONFLICTS WITH THIS SIGNAL DURING RESET.
GPIO(28) - MLPS_DIS 0 - ENABLE MLPS
20
OUT
1 - DISALBE MLPS
100 - 512KBIT (ST) M25P05A 101 - 1MBIT (ST) M25P10A 101 - 2MBIT (ST) M25P20 101 - 4MBIT (ST) M25P40 101 - 8MBIT (ST) M25P80 100 - 512KBIT (CHINGIS) PM25LV512 101 - 1MBIT (CHINGIS) PM25LV010
00 - NO AUDIO FUNCTION 01 - AUDIO FOR DP ONLY 10 - AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED 11 - AUDIO FOR BOTH DP AND HDMI
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD
is provided only to entities under a non-disclosure agreement with AMD for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than
prohibited. Use of this schematic and design for any purpose other than evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD.
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this
AMD makes no representations or warranties of any kind regarding this schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims
of merchantability or fitness for a particular purpose, and disclaims responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the
responsibility for any consequences resulting from use of the information included herein.
information included herein.
information included herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
Trinidad XT/PRO GD5
DD
DD
DD
C
C
C
BB
BB
BB
A
A
A
1
1
1
8
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