MSI MS-V305 Schematics rev1.0

1

2

3

4

5

6

7

8

(1) PCI-EXPRESS EDGE CONNECTOR

A A

+3.3V_BUS

GPIO_4_SMBCLK

7

IN

GPIO_3_SMBDATA

7

BI

PLACE THESE CAPS AS CLOSE TO
PCIE CONNECTOR AS POSSIBLE

+12V_BUS

C157

C151

C152

10uF

0.15uF

0.15uF

16V

16V

B B

+3.3V_BUS

16V

C153

C154

C155

10uF

6.3V

C156

0.1uF

1uF

0.01uF

6.3V

6.3V

10V

C C

+3.3V_BUS +3.3V_BUS +12V_BUS +12V_BUS +3.3V_BUS

R105

45.3K
1%

DNI DNI

Q100A

2N7002DW

R106

45.3K
1%

+3.3V_BUS

2
2

2
2

2
2

2
2

2
2

2
2

2
2

2
2

2
2

2
2

2
2

2
2

2
2

2
2

2
2

2
2

DNI

126

453

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

Q100B

2N7002DW

DNI

PETP0_GFXRP0
PETN0_GFXRN0

PETP1_GFXRP1
PETN1_GFXRN1

PETP2_GFXRP2
PETN2_GFXRN2

PETP3_GFXRP3
PETN3_GFXRN3

PETP4_GFXRP4
PETN4_GFXRN4

PETP5_GFXRP5
PETN5_GFXRN5

PETP6_GFXRP6
PETN6_GFXRN6

PETP7_GFXRP7
PETN7_GFXRN7

PETP8_GFXRP8
PETN8_GFXRN8

PETP9_GFXRP9
PETN9_GFXRN9

PETP10_GFXRP10
PETN10_GFXRN10

PETP11_GFXRP11
PETN11_GFXRN11

PETP12_GFXRP12
PETN12_GFXRN12

PETP13_GFXRP13
PETN13_GFXRN13

PETP14_GFXRP14
PETN14_GFXRN14

PETP15_GFXRP15
PETN15_GFXRN15

PRESENCE

SMCLK
SMDAT

B1

+12V

B2

+12V

B3

+12V

B4

GND

B5

SMCLK

B6

SMDAT

B7

GND

B8

+3.3V

B9

JTAG1

B10

3.3Vaux

B11

WAKE_

B12

RSVD_B12

B13

GND

B14

PETp0

B15

PETn0

B16

GND

B17

PRSNT2_B17

B18

GND

B19

PETp1

B20

PETn1

B21

GND

B22

GND

B23

PETp2

B24

PETn2

B25

GND

B26

GND

B27

PETp3

B28

PETn3

B29

GND

B30

RSVD_B30

B31

PRSNT2_B31

B32

GND

B33

PETp4

B34

PETn4

B35

GND

B36

GND

B37

PETp5

B38

PETn5

B39

GND

B40

GND

B41

PETp6

B42

PETn6

B43

GND

B44

GND

B45

PETp7

B46

PETn7

B47

GND

B48

PRSNT2_B48

B49

GND

B50

PETp8

B51

PETn8

B52

GND

B53

GND

B54

PETp9

B55

PETn9

B56

GND

B57

GND

B58

PETp10

B59

PETn10

B60

GND

B61

GND

B62

PETp11

B63

PETn11

B64

GND

B65

GND

B66

PETp12

B67

PETn12

B68

GND

B69

GND

B70

PETp13

B71

PETn13

B72

GND

B73

GND

B74

PETp14

B75

PETn14

B76

GND

B77

GND

B78

PETp15

B79

PETn15

B80

GND

B81

PRSNT2_B81

B82

RSVD_B82

MPCIE1

Mechanical Key

x16 PCIe

PRSNT1_A1

PERST_

REFCLK+

REFCLK-

RSVD_A19

RSVD_A32
RSVD_A33

RSVD_A50

PERp10
PERn10

PERp11
PERn11

PERp12
PERn12

PERp13
PERn13

PERp14
PERn14

PERp15
PERn15

A1
A2

+12V

A3

+12V

A4

GND

A5

JTAG2

A6

JTAG3

A7

JTAG4

A8

JTAG5

A9

+3.3V

A10

+3.3V

A11
A12

GND

A13
A14
A15

GND

A16

PERp0

A17

PERn0

A18

GND

A19
A20

GND

A21

PERp1

A22

PERn1

A23

GND

A24

GND

A25

PERp2

A26

PERn2

A27

GND

A28

GND

A29

PERp3

A30

PERn3

A31

GND

A32
A33
A34

GND

A35

PERp4

A36

PERn4

A37

GND

A38

GND

A39

PERp5

A40

PERn5

A41

GND

A42

GND

A43

PERp6

A44

PERn6

A45

GND

A46

GND

A47

PERp7

A48

PERn7

A49

GND

A50
A51

GND

A52

PERp8

A53

PERn8

A54

GND

A55

GND

A56

PERp9

A57

PERn9

A58

GND

A59

GND

A60
A61
A62

GND

A63

GND

A64
A65
A66

GND

A67

GND

A68
A69
A70

GND

A71

GND

A72
A73
A74

GND

A75

GND

A76
A77
A78

GND

A79

GND

A80
A81
A82

GND

PRESENCE

JTDIO_LOOP

PCIE_REFCLKP
PCIE_REFCLKN

PERP0
PERN0

PERP1
PERN1

PERP2
PERN2

PERP3
PERN3

PERP4
PERN4

PERP5
PERN5

PERP6
PERN6

PERP7
PERN7

PERP8
PERN8

PERP9
PERN9

PERP10
PERN10

PERP11
PERN11

PERP12
PERN12

PERP13
PERN13

PERP14
PERN14

PERP15
PERN15

SYSTEM JTAG TDI AND
TDO ARE HARD WIRED.

19,18

2

OUT

2

OUT

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

2

IN

+3.3V_BUS

R102 5%

10K

C199

0.1uF

6.3V

1.8V_EN

R103 5%

+3.3V_BUS

3 5

0R

DNI

U100B

NC7SZ08P5X

IN

PERSTB

U100A

RST_EN

1
2

NC7SZ08P5X

R104 5%

1K

PLACE R104 IN U100

C158

0.1uF

6.3V

PERSTB_BUF

4

DNI

2,20

OUT

SYMBOL LEGEND

DO NOT

DNI

INSTALL

ACTIVE

b or #

LOW

BRING UP

BUO

ONLY

DIGITAL
GROUND

ANALOG
GROUND

D D

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

MS-V305

01 PCI-EXPRESS EDGE CONNECTOR

01 PCI-EXPRESS EDGE CONNECTOR

01 PCI-EXPRESS EDGE CONNECTOR

Sheet of

Sheet of

Sheet of

8

123

123

123

10

10

10

1

(2) CURACAO PCIE INTERFACE

2

3

4

5

6

7

8

SOME PCIE TEST POINTS ARE

A A

B B

C C

OVERLAP C141 AND MC141

POPULATE FOR BARTS ONLY

+0.95V

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

+0.95V

+1.8V

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

AVAILABLE THROUGH VIAS ON TRACES

C175

C176

1uF

1uF

6.3V

6.3V

MC141

C141

10uF

4.7uF

6.3V

6.3V

C137

1uF

6.3V

C133

1uF

6.3V

C147

1uF

6.3V

C161

C162

0.1uF

0.1uF

6.3V

6.3V

TP101

TP102

TP117

TP118

PETP0_GFXRP0
PETN0_GFXRN0

PETP1_GFXRP1
PETN1_GFXRN1

PETP2_GFXRP2
PETN2_GFXRN2

PETP3_GFXRP3
PETN3_GFXRN3

PETP4_GFXRP4
PETN4_GFXRN4

PETP5_GFXRP5
PETN5_GFXRN5

PETP6_GFXRP6
PETN6_GFXRN6

PETP7_GFXRP7
PETN7_GFXRN7

PETP8_GFXRP8
PETN8_GFXRN8

PETP9_GFXRP9
PETN9_GFXRN9

PETP10_GFXRP10
PETN10_GFXRN10

PETP11_GFXRP11
PETN11_GFXRN11

PETP12_GFXRP12
PETN12_GFXRN12

PETP13_GFXRP13
PETN13_GFXRN13

PETP14_GFXRP14
PETN14_GFXRN14

PETP15_GFXRP15
PETN15_GFXRN15

PCIE_REFCLKP

1

IN

PCIE_REFCLKN

1

IN

PCIE_REFCLKx_OUTx
WORKSTATION DESIGNS
MAY USE THIS FEATURE

PERSTB_BUF

1,20

IN

C171

C172

C177

10uF

1uF

1uF

6.3V

6.3V

6.3V

C139

C140

C136

0.1uF

0.01uF

1uF

6.3V

6.3V

6.3V

C142

C138

1uF

1uF

6.3V

6.3V

C145

C146

C144

1uF

1uF

1uF

6.3V

6.3V

6.3V

C1284

C1319

C150

1uF

1uF

1uF

6.3V

6.3V

6.3V

10u

C160

C148

C163

10uF

4.7uF

0.1uF
4V

6.3V

6.3V

AR50

PCIE_RX0P

AP49

PCIE_RX0N

AP51

PCIE_RX1P

AN52

PCIE_RX1N

AN50

PCIE_RX2P

AM49

PCIE_RX2N

AM51

PCIE_RX3P

AL52

PCIE_RX3N

AL50

PCIE_RX4P

AK49

PCIE_RX4N

AK51

PCIE_RX5P

AJ52

PCIE_RX5N

AJ50

PCIE_RX6P

AH49

PCIE_RX6N

AH51

PCIE_RX7P

AG52

PCIE_RX7N

AG50

PCIE_RX8P

AF49

PCIE_RX8N

AF51

PCIE_RX9P

AE52

PCIE_RX9N

AE50

PCIE_RX10P

AD49

PCIE_RX10N

AD51

PCIE_RX11P

AC52

PCIE_RX11N

AC50

PCIE_RX12P

AB49

PCIE_RX12N

AB51

PCIE_RX13P

AA52

PCIE_RX13N

AA50

PCIE_RX14P

Y49

PCIE_RX14N

Y51

PCIE_RX15P

W52

PCIE_RX15N

AR47

PCIE_REFCLKP

AR46

PCIE_REFCLKN

AN44

PCIE_REFCLKP_OUT0

AN43

PCIE_REFCLKN_OUT0

AT51

PCIE_REFCLKP_OUT1

AR52

PCIE_REFCLKN_OUT1

AU48

PERSTB

AK40

BIF_VDDC

AG40

BIF_VDDC

AH41

C173

1uF

6.3V

MC148

10uF

6.3V

AU42
AR48

AB43
AB44
AB45
AD42

AG42
AH42
AK42

AM42

AL41

AT42

AT43
AT44
AT45
AT46
AT47
AT48

AF42

AL42
AN42

AR42

BIF_VDDC
BIF_VDDC

PCIE_PVDD
PCIE_PVDD

NC_PCIE_VDDR
NC_PCIE_VDDR
NC_PCIE_VDDR
NC_PCIE_VDDR
NC_PCIE_VDDR
NC_PCIE_VDDR
NC_PCIE_VDDR

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

OVERLAP C148 AND MC148

PART 2 OF 18

PITCAIRN

U1A

AN47

PCIE_TX0P

AN46

PCIE_TX0N

AM44

PCIE_TX1P

AM43

PCIE_TX1N

AM47

PCIE_TX2P

AM46

PCIE_TX2N

AL44

PCIE_TX3P

AL43

PCIE_TX3N

AL47

PCIE_TX4P

AL46

PCIE_TX4N

AJ44

PCIE_TX5P

AJ43

PCIE_TX5N

AJ47

PCIE_TX6P

AJ46

PCIE_TX6N

AH44

PCIE_TX7P

AH43

PCIE_TX7N

AH47

PCIE_TX8P

AH46

PCIE_TX8N

AF44

PCIE_TX9P

AF43

PCIE_TX9N

P
C
I
E
X
P
R
E
S
S

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

PCIE_CALRP_TX

PCIE_CALRN_RX

AF47
AF46

AE44
AE43

AE47
AE46

AC44
AC43

AC47
AC46

AB47
AB46

AR44

AR43

T51

PX_EN

AA48

VSS

AB48

VSS

AB53

VSS

AC45

VSS

AC48

VSS

AD48

VSS

AD53

VSS

AE45

VSS

AE48

VSS

AF45

VSS

AF48

VSS

AF53

VSS

AG48

VSS

AH45

VSS

AH48

VSS

AH53

VSS

AJ45

VSS

AJ48

VSS

AK48

VSS

AK53

VSS

AL45

VSS

AL48

VSS

AM45

VSS

AM48

VSS

AM53

VSS

AN45

VSS

AN48

VSS

AP48

VSS

AP53

VSS

AR45

VSS

AT49

VSS

AT53

VSS

W50

VSS

Y48

VSS

Y53

VSS

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

PCIE_CALRP_TX

PCIE_CALRN_RX

PX_EN

R150

DNI

PCIE_VSS MERGED TO VSS IN PITCAIRN

FOR BARTS, USE 110NF

C100
C101

C102
C103

C104

C106
C107

C108
C109

C111
C110

C112
C113

C114

C116

C118
C119

C120
C121

C122
C123

C124
C125

C126

C127

C128

C129

C130
C131

R100

R101

GROUND PX_EN (T51) FOR BARTS (NO BACO)

1K
5%

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

0.22uF

1.69K

1K

PERP0

6.3V

PERN0

6.3V

PERP1

6.3V

PERN1

6.3V

PERP2

6.3V

PERN2

6.3VC105

PERP3

6.3V

PERN3

6.3V

PERP4

6.3V

PERN4

6.3V

PERP5

6.3V

PERN5

6.3V

PERP6

6.3V

PERN6

6.3V

PERP7

6.3V

PERN7

6.3VC115

PERP8

6.3V

PERN8

6.3VC117

PERP9

6.3V

PERN9

6.3V

PERP10

6.3V

PERN10

6.3V

PERP11

6.3V

PERN11

6.3V

PERP12

6.3V

PERN12

6.3V

PERP13

6.3V

PERN13

6.3V

PERP14

6.3V

PERN14

6.3V

PERP15

6.3V

PERN15

6.3V

1%

+0.95V

1%

19,20

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

PCIE_CALRP_TX:
PU R100 (1.69K) FOR PITCAIRN

PCIE_CALRN_RX:
PU R101 (1K) FOR PITCAIRN

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

D D

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

MS-V305

02 CURACAO PCIE INTERFACE

02 CURACAO PCIE INTERFACE

02 CURACAO PCIE INTERFACE

Sheet of

Sheet of

Sheet of

8

10

10

10

223

223

223

1

(3) CURACAO MEM INTERFACE CH A/B

2

3

4

5

6

7

8

U1B

DQA0_<0>

5

A A

B B

C C

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

R52

DQA0_<1>

P49

DQA0_<2>

P51

DQA0_<3>

P53

DQA0_<4>

M53

DQA0_<5>

M51

DQA0_<6>

L50

DQA0_<7>

K49

DQA0_<8>

T44

DQA0_<9>

T45

DQA0_<10>

T47

DQA0_<11>

R43

DQA0_<12>

R45

DQA0_<13>

P47

DQA0_<14>

P42

DQA0_<15>

N42

DQA0_<16>

K48

DQA0_<17>

J50

DQA0_<18>

H48

DQA0_<19>

H53

DQA0_<20>

G50

DQA0_<21>

F53

DQA0_<22>

F49

DQA0_<23>

E51

DQA0_<24>

D47

DQA0_<25>

C46

DQA0_<26>

A46

DQA0_<27>

E46

DQA0_<28>

C44

DQA0_<29>

A44

DQA0_<30>

E44

DQA0_<31>

F44

MAA0_<0>

J43

MAA0_<1>

H47

MAA0_<2>

L47

MAA0_<3>

L45

MAA0_<4>

M46

MAA0_<5>

L46

MAA0_<6>

H43

MAA0_<7>

G43

MAA0_<8>

G45
P43

WCKA0_0

K51

WCKA0B_0

K53

WCKA0_1

E48

WCKA0B_1

C49

EDCA0_0

N50

EDCA0_1

R47

EDCA0_2

H51

EDCA0_3

D45

DDBIA0_0

M49

DDBIA0_1

R46

DDBIA0_2

H49

DDBIA0_3

F46

ADBIA0 ADBIA1 ADBIB0 ADBIB1

G46

CSA0B_0 CSA1B_0 CSB0B_0 CSB1B_0

M47
M44

CASA0B CASA1B CASB0B CASB1B

K42

RASA0B RASA1B RASB0B RASB1B

J47

WEA0B WEA1B WEB0B WEB1B

M43

CKEA0 CKEA1 CKEB0 CKEB1

J42

CLKA0

P44

CLKA0B

P45

U42
T41

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8
MAA0_9

WCKA0_0
WCKA0B_0

WCKA0_1
WCKA0B_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3

ADBIA0

CSA0B_0
CSA0B_1

CASA0B
RASA0B
WEA0B

CKEA0

CLKA0
CLKA0B

NC_MEM_CALRP0

NC_MEM_CALRN0

PART 3 OF 18

M
E
M
O
R
Y

I
N
T
E
R
F
A
C
E

B
A
N
K

A

DQA1_<0>

D43

DQA1_0

DQA1_<1>

E42

DQA1_1

DQA1_<2>

A42

DQA1_2

DQA1_<3>

C42

DQA1_3

DQA1_<4>

C40

DQA1_4

DQA1_<5>

A40

DQA1_5

DQA1_<6>

E40

DQA1_6

DQA1_<7>

F40

DQA1_7

DQA1_<8>

A38

DQA1_8

DQA1_<9>

E38

DQA1_9

DQA1_<10>

F38

DQA1_10

DQA1_<11>

D37

DQA1_11

DQA1_<12>

E36

DQA1_12

DQA1_<13>

D35

DQA1_13

DQA1_<14>

C34

DQA1_14

DQA1_<15>

A34

DQA1_15

DQA1_<16>

M41

DQA1_16

DQA1_<17>

L39

DQA1_17

DQA1_<18>

M40

DQA1_18

DQA1_<19>

M38

DQA1_19

DQA1_<20>

M36

DQA1_20

DQA1_<21>

K35

DQA1_21

DQA1_<22>

L35

DQA1_22

DQA1_<23>

M35

DQA1_23

DQA1_<24>

G32

DQA1_24

DQA1_<25>

J32

DQA1_25

DQA1_<26>

H31

DQA1_26

DQA1_<27>

G31

DQA1_27

DQA1_<28>

K28

DQA1_28

DQA1_<29>

H28

DQA1_29

DQA1_<30>

G28

DQA1_30

DQA1_<31>

J26

DQA1_31

MAA1_<0>

H39

MAA1_0

MAA1_<1>

G39

MAA1_1

MAA1_<2>

J38

MAA1_2

MAA1_<3>

G38

MAA1_3

MAA1_<4>

G36

MAA1_4

MAA1_<5>

H36

MAA1_5

MAA1_<6>

G40

MAA1_6

MAA1_<7>

J40

MAA1_7

MAA1_<8>

H40

MAA1_8

L32

MAA1_9

WCKA1_0

C38

WCKA1_0

WCKA1B_0

D39

WCKA1B_0

WCKA1_1

K33

WCKA1_1

WCKA1B_1

L33

WCKA1B_1

EDCA1_0

F42

EDCA1_0

EDCA1_1

A36

EDCA1_1

EDCA1_2

L36

EDCA1_2

EDCA1_3

J29

EDCA1_3

DDBIA1_0

D41

DDBIA1_0

DDBIA1_1

C36

DDBIA1_1

DDBIA1_2

M37

DDBIA1_2

DDBIA1_3

H29

DDBIA1_3

K39

ADBIA1

J36

CSA1B_0

J35

CSA1B_1

L40

CASA1B

K38

RASA1B

G35

WEA1B

G42

CKEA1

CLKA1

H33

CLKA1

CLKA1B

G33

CLKA1B

MVREF_A MVREF_B

M42

MVREFDA

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

+MVDD +MVDD

R3602

40.2R
1%

C3602

R3606

1uF

100R

6.3V

1%

R3601

DQB0_<0>

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

120R

E34
F34
D33
E32
F32
D31
C30
A30
D29
C28
A28
E28
C26
A26
E26
F26
G26
H26
K25
G25
G23
H23
G22
H22
A24
E24
F24
D23
E22
F22
D21
C20

M23
L23
L26
M26
L28
M28
M21
L21
K22
K32

E30
F30

D25
C24

A32
D27
J25
A22

C32
F28
J23
C22

L22

K29
M30

G21
M24
M31

J21
L31

K31

T16
U17

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31

MAB0_0
MAB0_1
MAB0_2
MAB0_3
MAB0_4
MAB0_5
MAB0_6
MAB0_7
MAB0_8
MAB0_9

WCKB0_0
WCKB0B_0

WCKB0_1
WCKB0B_1

EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3

DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3

ADBIB0

CSB0B_0
CSB0B_1

CASB0B
RASB0B
WEB0B

CKEB0

CLKB0
CLKB0B

MEM_CALRP1

NC_MEM_CALRN1

DQB0_<1>
DQB0_<2>
DQB0_<3>
DQB0_<4>
DQB0_<5>
DQB0_<6>
DQB0_<7>
DQB0_<8>
DQB0_<9>
DQB0_<10>
DQB0_<11>
DQB0_<12>
DQB0_<13>
DQB0_<14>
DQB0_<15>
DQB0_<16>
DQB0_<17>
DQB0_<18>
DQB0_<19>
DQB0_<20>
DQB0_<21>
DQB0_<22>
DQB0_<23>
DQB0_<24>
DQB0_<25>
DQB0_<26>
DQB0_<27>
DQB0_<28>
DQB0_<29>
DQB0_<30>
DQB0_<31>

MAB0_<0>
MAB0_<1>
MAB0_<2>
MAB0_<3>
MAB0_<4>
MAB0_<5>
MAB0_<6>
MAB0_<7>
MAB0_<8>

WCKB0_0
WCKB0B_0

WCKB0_1
WCKB0B_1

EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3

DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3

CLKB0
CLKB0B

MEM_CALRP1

1%

U1C

PART 4 OF 18

M
E
M
O
R
Y

I
N
T
E
R
F
A
C
E

B
A
N
K

B

DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8

DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

MAB1_0

MAB1_1

MAB1_2

MAB1_3

MAB1_4

MAB1_5

MAB1_6

MAB1_7

MAB1_8

MAB1_9

WCKB1_0

WCKB1B_0

WCKB1_1

WCKB1B_1

EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3

DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3

ADBIB1

CSB1B_0
CSB1B_1

CASB1B

RASB1B

WEB1B

CLKB1B

MVREFDB

DQB1_<0>

A20

DQB1_<1>

E20

DQB1_<2>

F20

DQB1_<3>

D19

DQB1_<4>

E18

DQB1_<5>

D17

DQB1_<6>

C16

DQB1_<7>

A16

DQB1_<8>

D15

DQB1_<9>

C14

DQB1_<10>

A14

DQB1_<11>

E14

DQB1_<12>

A12

DQB1_<13>

E12

DQB1_<14>

F12

DQB1_<15>

D11

DQB1_<16>

G15

DQB1_<17>

H15

DQB1_<18>

G14

DQB1_<19>

H14

DQB1_<20>

G11

DQB1_<21>

J11

DQB1_<22>

G9

DQB1_<23>

G8

DQB1_<24>

E10

DQB1_<25>

D9

DQB1_<26>

C8

DQB1_<27>

A8

DQB1_<28>

D7

DQB1_<29>

A6

DQB1_<30>

E6

DQB1_<31>

C5

MAB1_<0>

L18

MAB1_<1>

K18

MAB1_<2>

J16

MAB1_<3>

K16

MAB1_<4>

L15

MAB1_<5>

G16

MAB1_<6>

J19

MAB1_<7>

H19

MAB1_<8>

G18
L12

WCKB1_0

F16

WCKB1B_0

E16

WCKB1_1

A10

WCKB1B_1

C10

EDCB1_0

A18

EDCB1_1

C12

EDCB1_2

H11

EDCB1_3

F8

DDBIB1_0

C18

DDBIB1_1

D13

DDBIB1_2

G12

DDBIB1_3

E8
H18

J15
L14

G19
M18
K14

L19

CKEB1

CLKB1

K12

CLKB1

CLKB1B

J12

M17

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

R3603

40.2R
1%

R3607

C3603

100R

1uF

1%

6.3V

DRAM_RST1 DRAM_RST1_RDRAM_RST1_RR

R3630

49.9R

PITCAIRN

MVREFSA

N41

MVREFD/S = 0.7 * VDDR1

5

OUT

1%

R3615 1%

C3607

120pF
50V

10R

V43

DRAM_RST1

R3612

5.1K
1%

PITCAIRN

MVREFSB

M19

MVREFD/S = 0.7 * VDDR1

D D

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

MS-V305

03 CURACAO MEM CH AB

03 CURACAO MEM CH AB

03 CURACAO MEM CH AB

Sheet of

Sheet of

Sheet of

8

10

10

10

323

323

323

1

2

(4) CURACAO MEM INTERFACE CH C/D

3

4

5

6

7

8

U1D

DQC0_<0>

6,

A A

B B

C C

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

R3614

120R

1%

E3

DQC0_<1>

F5

DQC0_<2>

F1

DQC0_<3>

G4

DQC0_<4>

H1

DQC0_<5>

H3

DQC0_<6>

J4

DQC0_<7>

K5

DQC0_<8>

H7

DQC0_<9>

J7

DQC0_<10>

L9

DQC0_<11>

L7

DQC0_<12>

P8

DQC0_<13>

P7

DQC0_<14>

R8

DQC0_<15>

R7

DQC0_<16>

L4

DQC0_<17>

M6

DQC0_<18>

M5

DQC0_<19>

M1

DQC0_<20>

P5

DQC0_<21>

P1

DQC0_<22>

P3

DQC0_<23>

R4

DQC0_<24>

T1

DQC0_<25>

T3

DQC0_<26>

U4

DQC0_<27>

V5

DQC0_<28>

W4

DQC0_<29>

Y6

DQC0_<30>

Y5

DQC0_<31>

Y1

MAC0_<0>

V11

MAC0_<1>

V10

MAC0_<2>

T9

MAC0_<3>

T10

MAC0_<4>

R11

MAC0_<5>

T7

MAC0_<6>

W9

MAC0_<7>

W8

MAC0_<8>

V7

M11

WCKC0_0

K1

WCKC0B_0

K3

WCKC0_1

T6

WCKC0B_1

T5

EDCC0_0

H6

EDCC0_1

L8

EDCC0_2

M3

EDCC0_3

V1

DDBIC0_0

H5

DDBIC0_1

M7

DDBIC0_2

N4

DDBIC0_3

V3

ADBIC0 ADBIC1 ADBID0 ADBID1

V8

CSC0B_0 CSC1B_0 CSD0B_0 CSD1B_0

R9

P11

CASC0B CASC1B CASD0B CASD1B

W7

RASC0B RASC1B RASD0B RASD1B

V12

WEC0B WEC1B WED0B WED1B

P10

CKEC0 CKEC1 CKED0 CKED1

W11

CLKC0

M10

CLKC0B

M9

MEM_CALRP2

BB17
BA16

DQC0_0
DQC0_1
DQC0_2
DQC0_3
DQC0_4
DQC0_5
DQC0_6
DQC0_7
DQC0_8
DQC0_9
DQC0_10
DQC0_11
DQC0_12
DQC0_13
DQC0_14
DQC0_15
DQC0_16
DQC0_17
DQC0_18
DQC0_19
DQC0_20
DQC0_21
DQC0_22
DQC0_23
DQC0_24
DQC0_25
DQC0_26
DQC0_27
DQC0_28
DQC0_29
DQC0_30
DQC0_31

MAC0_0
MAC0_1
MAC0_2
MAC0_3
MAC0_4
MAC0_5
MAC0_6
MAC0_7
MAC0_8
MAC0_9

WCKC0_0
WCKC0B_0

WCKC0_1
WCKC0B_1

EDCC0_0
EDCC0_1
EDCC0_2
EDCC0_3

DDBIC0_0
DDBIC0_1
DDBIC0_2
DDBIC0_3

ADBIC0

CSC0B_0
CSC0B_1

CASC0B
RASC0B
WEC0B

CKEC0

CLKC0
CLKC0B

MEM_CALRP2

NC_MEM_CALRN2

PART 5 OF 18

M
E
M
O
R
Y

I
N
T
E
R
F
A
C
E

B
A
N
K

C

DQC1_<0>

Y3

DQC1_0

DQC1_<1>

AA4

DQC1_1

DQC1_<2>

AB6

DQC1_2

DQC1_<3>

AB5

DQC1_3

DQC1_<4>

AC4

DQC1_4

DQC1_<5>

AD6

DQC1_5

DQC1_<6>

AD5

DQC1_6

DQC1_<7>

AD1

DQC1_7

DQC1_<8>

AB8

DQC1_8

DQC1_<9>

AB7

DQC1_9

DQC1_<10>

AC8

DQC1_10

DQC1_<11>

AC7

DQC1_11

DQC1_<12>

AE7

DQC1_12

DQC1_<13>

AE10

DQC1_13

DQC1_<14>

AF8

DQC1_14

DQC1_<15>

AF7

DQC1_15

DQC1_<16>

AF6

DQC1_16

DQC1_<17>

AF5

DQC1_17

DQC1_<18>

AF1

DQC1_18

DQC1_<19>

AF3

DQC1_19

DQC1_<20>

AH5

DQC1_20

DQC1_<21>

AH1

DQC1_21

DQC1_<22>

AH3

DQC1_22

DQC1_<23>

AJ4

DQC1_23

DQC1_<24>

AK1

DQC1_24

DQC1_<25>

AK3

DQC1_25

DQC1_<26>

AL4

DQC1_26

DQC1_<27>

AM6

DQC1_27

DQC1_<28>

AM5

DQC1_28

DQC1_<29>

AN4

DQC1_29

DQC1_<30>

AP6

DQC1_30

DQC1_<31>

AP5

DQC1_31

MAC1_<0>

AC12

MAC1_0

MAC1_<1>

AC11

MAC1_1

MAC1_<2>

AF11

MAC1_2

MAC1_<3>

AF12

MAC1_3

MAC1_<4>

AH11

MAC1_4

MAC1_<5>

AH12

MAC1_5

MAC1_<6>

AA12

MAC1_6

MAC1_<7>

AA11

MAC1_7

MAC1_<8>

AB10

MAC1_8

AM10

MAC1_9

WCKC1_0

AE4

WCKC1_0

WCKC1B_0

AD3

WCKC1B_0

WCKC1_1

AK5

WCKC1_1

WCKC1B_1

AK6

WCKC1B_1

EDCC1_0

AB1

EDCC1_0

EDCC1_1

AE9

EDCC1_1

EDCC1_2

AG4

EDCC1_2

EDCC1_3

AM1

EDCC1_3

DDBIC1_0

AB3

DDBIC1_0

DDBIC1_1

AC9

DDBIC1_1

DDBIC1_2

AH6

DDBIC1_2

DDBIC1_3

AM3

DDBIC1_3

AB11

ADBIC1

AJ10

CSC1B_0

AK12

CSC1B_1

AA7

CASC1B

AD12

RASC1B

AL12

WEC1B

AA9

CKEC1

CLKC1

AL11

CLKC1

CLKC1B

AL10

CLKC1B

MVREF_C MVREF_D

U12

MVREFDC

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

+MVDD +MVDD

R3618

40.2R
1%

C3612

R3621

1uF

100R

6.3V

1%

DQD0_<0>

WCKD0_0
WCKD0B_0

WCKD0_1
WCKD0B_1

EDCD0_0
EDCD0_1
EDCD0_2
EDCD0_3

DDBID0_0
DDBID0_1
DDBID0_2
DDBID0_3

CLKD0
CLKD0B

DQD0_<1>
DQD0_<2>
DQD0_<3>
DQD0_<4>
DQD0_<5>
DQD0_<6>
DQD0_<7>
DQD0_<8>
DQD0_<9>
DQD0_<10>
DQD0_<11>
DQD0_<12>
DQD0_<13>
DQD0_<14>
DQD0_<15>
DQD0_<16>
DQD0_<17>
DQD0_<18>
DQD0_<19>
DQD0_<20>
DQD0_<21>
DQD0_<22>
DQD0_<23>
DQD0_<24>
DQD0_<25>
DQD0_<26>
DQD0_<27>
DQD0_<28>
DQD0_<29>
DQD0_<30>
DQD0_<31>

MAD0_<0>
MAD0_<1>
MAD0_<2>
MAD0_<3>
MAD0_<4>
MAD0_<5>
MAD0_<6>
MAD0_<7>
MAD0_<8>

AH10

AR12
AR11
AR10

AW11

AM11
AN10

AN11

AU12

AW10

AF9

DQD0_0

AH7

DQD0_1

AH8

DQD0_2
DQD0_3

AL7

DQD0_4

AL8

DQD0_5

AM9

DQD0_6

AM7

DQD0_7
DQD0_8
DQD0_9
DQD0_10

AT12

DQD0_11

AV12

DQD0_12

AY12

DQD0_13
DQD0_14

BA12

DQD0_15

AP1

DQD0_16

AP3

DQD0_17

AR4

DQD0_18

AT5

DQD0_19

AU4

DQD0_20

AV6

DQD0_21

AV5

DQD0_22

AV1

DQD0_23

AY6

DQD0_24

AY5

DQD0_25

AY1

DQD0_26

AY3

DQD0_27

BB3

DQD0_28

BB1

DQD0_29

BB5

DQD0_30

BC4

DQD0_31

AW8

MAD0_0

AW7

MAD0_1

AV9

MAD0_2

AV7

MAD0_3

AT7

MAD0_4

AT8

MAD0_5

AY7

MAD0_6

AY9

MAD0_7

AY8

MAD0_8
MAD0_9

WCKD0_0
WCKD0B_0

AV3

WCKD0_1

AW4

WCKD0B_1

AJ9

EDCD0_0

AT11

EDCD0_1

AT1

EDCD0_2

BB6

EDCD0_3

AJ8

DDBID0_0
DDBID0_1

AT3

DDBID0_2

BA4

DDBID0_3

ADBID0

AT9

CSD0B_0

AR9

CSD0B_1

AY11

CASD0B

AV10

RASD0B

AR7

WED0B

BB7

CKED0

AN8

CLKD0

AN7

CLKD0B

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

PART 6 OF 18

?

U1E

DQD1_<0>

BD6

DQD1_0

DQD1_<1>

BD5

DQD1_1

DQD1_<2>

BD1

DQD1_2

DQD1_<3>

BD3

DQD1_3

DQD1_<4>

BF5

DQD1_4

DQD1_<5>

BF1

DQD1_5

DQD1_<6>

BF3

DQD1_6

DQD1_<7>

BG4

DQD1_7

DQD1_<8>

BL5

DQD1_8

DQD1_<9>

BJ6

DQD1_9

DQD1_<10>

BN6

DQD1_10

DQD1_<11>

BK7

DQD1_11

DQD1_<12>

BN8

DQD1_12

DQD1_<13>

BH8

DQD1_13

DQD1_<14>

BK9

DQD1_14

DQD1_<15>

BH10

DQD1_15

DQD1_<16>

BB13

DQD1_16

DQD1_<17>

BB14

DQD1_17

DQD1_<18>

BG14

DQD1_18

DQD1_<19>

BE15

DQD1_19

DQD1_<20>

BC15

DQD1_20

DQD1_<21>

BG16

DQD1_21

DQD1_<22>

BE16

DQD1_22

DQD1_<23>

BD16

DQD1_23

DQD1_<24>

BJ10

DQD1_24

DQD1_<25>

BK11

DQD1_25

DQD1_<26>

BL12

DQD1_26

DQD1_<27>

BN12

DQD1_27

DQD1_<28>

BN14

DQD1_28

DQD1_<29>

BL14

DQD1_29

DQD1_<30>

BJ14

DQD1_30

DQD1_<31>

BM15

DQD1_31

MAD1_<0>

BC9

MAD1_0

MAD1_<1>

BG8

MAD1_1

MAD1_<2>

BG11

MAD1_2

M
E
M
O
R
Y

I
N
T
E
R
F
A
C
E

B
A
N
K

D

MAD1_3
MAD1_4
MAD1_5
MAD1_6
MAD1_7
MAD1_8
MAD1_9

WCKD1_0

WCKD1B_0

WCKD1_1

WCKD1B_1

EDCD1_0
EDCD1_1
EDCD1_2
EDCD1_3

DDBID1_0
DDBID1_1
DDBID1_2
DDBID1_3

ADBID1

CSD1B_0
CSD1B_1

CASD1B
RASD1B

WED1B

CLKD1B

MVREFDD

MAD1_<3>

BE11

MAD1_<4>

BF12

MAD1_<5>

BF11

MAD1_<6>

BC8

MAD1_<7>

BC7

MAD1_<8>

BE7
BC14

WCKD1_0

BH5

WCKD1B_0

BJ3

WCKD1_1

BL10

WCKD1B_1

BN10

EDCD1_0

BE4

EDCD1_1

BL8

EDCD1_2

BG15

EDCD1_3

BK13

DDBID1_0

BF6

DDBID1_1

BJ8

DDBID1_2

BF15

DDBID1_3

BJ12
BF7

BG12
BD12

BB10
BG9
BC12

BB9

CKED1

CLKD1

BD14

CLKD1

CLKD1B

BE14

BB12

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

BI

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

R3619

40.2R
1%

C3611

R3620

1uF

100R

6.3V

1%

PITCAIRN

MVREFSC

W12

DRAM_RST2 DRAM_RST2_RDRAM_RST2_RR

6

OUT

R3629 1%

49.9R

R3616

10R

1%

BC18

DRAM_RST2

C3617

120pF
50V

R3627

5.1K
1%

PITCAIRN

MVREFSD

BA13

MVREFD/S = 0.7 * VDDR1MVREFD/S = 0.7 * VDDR1

D D

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

MS-V305

04 CURACAO MEM CH CD

04 CURACAO MEM CH CD

04 CURACAO MEM CH CD

8

Sheet of

Sheet of

Sheet of

423

423

423

10

10

10

1

2

3

4

5

6

7

8

(5) GDDR5 MEMORY CH A/B

DQA0_<14>
DQA0_<15>
DQA0_<13>
DQA0_<12>
DQA0_<10>
DQA0_<9>
DQA0_<11>
DQA0_<8>
DQA0_<7>
DQA0_<6>
DQA0_<4>
DQA0_<5>
DQA0_<0>
DQA0_<2>

A A

B B

C C

+MVDD

+MVDD

+MVDD

+MVDD

R2001 1%
R2000 1%

R2003 5%

R2004 5%

R2005 1%
R2006 1%
C2001 6.3V

R2007 1%
R2008 1%
C2003 6.3V

R2009 1%
R2010 1%
C2005 6.3V

+MVDD

C2007

C2008

0.1uF

0.1uF

+MVDD

C2019

C2020

1uF

1uF

DQA0_<1>
DQA0_<3>
DQA0_<21>
DQA0_<22>
DQA0_<20>
DQA0_<23>
DQA0_<19>
DQA0_<18>
DQA0_<16>
DQA0_<17>
DQA0_<26>
DQA0_<25>
DQA0_<24>
DQA0_<27>
DQA0_<28>
DQA0_<30>
DQA0_<29>
DQA0_<31>

MAA0_<8>
MAA0_<7>
MAA0_<6>
MAA0_<5>
MAA0_<4>
MAA0_<3>
MAA0_<2>
MAA0_<1>
MAA0_<0>

WCKA0_1

3

IN

WCKA0B_1

3

IN

WCKA0_0

3

IN

WCKA0B_0

3

IN

EDCA0_1

3

OUT

EDCA0_0

3

OUT

EDCA0_2

3

OUT

EDCA0_3

3

OUT

DDBIA0_1

3

BI

DDBIA0_0

3

BI

DDBIA0_2

3

BI

DDBIA0_3

3

BI

RASA0B

3

IN

CASA0B

3

IN

60.4R

60.4R

CKEA0 CKEA1 CKEB0 CKEB1

3

IN

CLKA0B

3

IN

CLKA0

3

IN

CSA0B_0

3

IN

WEA0B

3

IN

ZQ_A0 ZQ_A1 ZQ_B0 ZQ_B1

R2002

120R

1%

SEN_A0 SEN_A1 SEN_B0 SEN_B1

1K

DRAM_RST1 DRAM_RST1 DRAM_RST1 DRAM_RST1

3,5

IN

MF_A0 MF_A1 MF_B0 MF_B1

1K

2.37K

5.49K

VREFD1_A0 VREFD1_A1 VREFD1_B0 VREFD1_B1

1uF

2.37K

5.49K

VREFD2_A0 VREFD2_A1 VREFD2_B0 VREFD2_B1

1uF

2.37K

5.49K

VREFC_A0 VREFC_A1 VREFC_B0 VREFC_B1

1uF

ADBIA0 ADBIA1 ADBIB0 ADBIB1

3

IN

C2010

C2012

C2013

C2014

C2015

C2009

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

C2024

C2025

C2026

C2028

C2029

C2023

1uF

1uF

1uF

1uF

1uF

1uF

23CNOPN001

U2000

M2

DQ31__DQ7

M4

DQ30__DQ6

N2

DQ29__DQ5

N4

DQ28__DQ4

T2

DQ27__DQ3

T4

DQ26__DQ2

V2

DQ25__DQ1

V4

DQ24__DQ0

M13

DQ23__DQ15

M11

DQ22__DQ14

N13

DQ21__DQ13

N11

DQ20__DQ12

T13

DQ19__DQ11

T11

DQ18__DQ10

V13

DQ17__DQ9

V11

DQ16__DQ8

F13

DQ15__DQ23

F11

DQ14__DQ22

E13

DQ13__DQ21

E11

DQ12__DQ20

B13

DQ11__DQ19

B11

DQ10__DQ18

A13

DQ9__DQ17

A11

DQ8__DQ16

F2

DQ7__DQ31

F4

DQ6__DQ30

E2

DQ5__DQ29

E4

DQ4__DQ28

B2

DQ3__DQ27

B4

DQ2__DQ26

A2

DQ1__DQ25

A4

DQ0__DQ24

J5

RFU_A12_NC

K4

A7_A8__A0_A10

K5

A6_A11__A1_A9

K10

A5_BA1__A3_BA3

K11

A4_BA2__A2_BA0

H10

A3_BA3__A5_BA1

H11

A2_BA0__A4_BA2

H5

A1_A9__A6_A11

H4

A0_A10__A7_A8

D4

WCK01__WCK23

D5

WCK01#__WCK23#

P4

WCK23__WCK01

P5

WCK23#__WCK01#

R2

EDC3__EDC0

R13

EDC2__EDC1

C13

EDC1__EDC2

C2

EDC0__EDC3

P2

DBI3#__DBI0#

P13

DBI2#__DBI1#

D13

DBI1#__DBI2#

D2

DBI0#__DBI3#

G3

RAS#__CAS#

L3

CAS#__RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS#__WE#

L12

WE#__CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp_NC

V5

Vpp_NC1

A10

VREFD1

V10

VREFD2

J14

VREFC

J4

ABI#

+MVDD

C2107

0.1uF

+MVDD

C2040

C2041

C2118

10uF

10uF

1uF

+MVDD

B1

VDDQ_B1

B3

VDDQ_B3

B12

VDDQ_B12

B14

VDDQ_B14

D1

VDDQ_D1

D3

VDDQ_D3

D12

VDDQ_D12

D14

VDDQ_D14

E5

VDDQ_E5

E10

VDDQ_E10

F1

VDDQ_F1

F3

VDDQ_F3

F12

VDDQ_F12

F14

VDDQ_F14

G2

VDDQ_G2

G13

VDDQ_G13

H3

VDDQ_H3

H12

VDDQ_H12

K3

VDDQ_K3

K12

VDDQ_K12

L2

VDDQ_L2

L13

VDDQ_L13

M1

VDDQ_M1

M3

VDDQ_M3

M12

VDDQ_M12

M14

VDDQ_M14

N5

VDDQ_N5

N10

VDDQ_N10

P1

VDDQ_P1

P3

VDDQ_P3

P12

VDDQ_P12

P14

VDDQ_P14

T1

VDDQ_T1

T3

VDDQ_T3

T12

VDDQ_T12

T14

VDDQ_T14

+MVDD

C5

VDD_C5

C10

VDD_C10

D11

VDD_D11

G1

VDD_G1

G4

VDD_G4

G11

VDD_G11

G14

VDD_G14

L1

VDD_L1

L4

VDD_L4

L11

VDD_L11

L14

VDD_L14

P11

VDD_P11

R5

VDD_R5

R10

VDD_R10

A1

VSSQ_A1

A3

VSSQ_A3

A12

VSSQ_A12

A14

VSSQ_A14

C1

VSSQ_C1

C3

VSSQ_C3

C4

VSSQ_C4

C11

VSSQ_C11

C12

VSSQ_C12

C14

VSSQ_C14

E1

VSSQ_E1

E3

VSSQ_E3

E12

VSSQ_E12
VSSQ_E14

VSSQ_F5

VSSQ_F10

VSSQ_H2

VSSQ_H13

VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10

VSSQ_N1

VSSQ_N3
VSSQ_N12
VSSQ_N14

VSSQ_R1

VSSQ_R3

VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14

VSSQ_V1

VSSQ_V3
VSSQ_V12
VSSQ_V14

VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10

VSS_H1
VSS_H14

VSS_K1
VSS_K14

VSS_L5
VSS_L10
VSS_P10

VSS_T5
VSS_T10

C2108

C2109

C2110

0.1uF

0.1uF

0.1uF

C2119

C2120

C2121

1uF

1uF

1uF

+MVDD

E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

C2112

C2115

0.1uF

0.1uF

C2122

C2126

1uF

1uF

R2101
R2100 1%

+MVDD

R2105 1%

+MVDD

R2106 1%
C2101 6.3V

R2107 1%

+MVDD

R2108 1%
C2103 6.3V

R2109 1%

+MVDD

R2110 1%
C2105

C2117

C2116

0.1uF

0.1uF

C2129

C2140

C2141

C2127

1uF

10uF

10uF

1uF

DQA1_<5>
DQA1_<6>
DQA1_<4>
DQA1_<7>
DQA1_<3>
DQA1_<2>
DQA1_<1>
DQA1_<0>
DQA1_<11>
DQA1_<10>
DQA1_<8>
DQA1_<9>
DQA1_<12>
DQA1_<14>
DQA1_<13>
DQA1_<15>
DQA1_<24>
DQA1_<25>
DQA1_<27>
DQA1_<26>
DQA1_<31>
DQA1_<29>
DQA1_<30>
DQA1_<28>
DQA1_<17>
DQA1_<16>
DQA1_<19>
DQA1_<18>
DQA1_<20>
DQA1_<22>
DQA1_<21>
DQA1_<23>

MAA1_<8>
MAA1_<0>
MAA1_<1>
MAA1_<3>
MAA1_<2>
MAA1_<5>
MAA1_<4>
MAA1_<6>
MAA1_<7>

WCKA1_1

3

IN

WCKA1B_1

3

IN

WCKA1_0

3

IN

WCKA1B_0

3

IN

EDCA1_0

3

OUT

EDCA1_1

3

OUT

EDCA1_3 EDCB0_0

3

OUT

EDCA1_2

3

OUT

DDBIA1_0

3

BI

DDBIA1_1

3

BI

DDBIA1_3 DDBIB0_0

3

BI

DDBIA1_2

3

BI

CASA1B

3

IN

RASA1B

3

IN

60.4R

1%

60.4R

3

IN

CLKA1B

3

IN

CLKA1

3

IN

WEA1B

3

IN

CSA1B_0

3

IN

R2102 1%

120R

R2103 5%

1K

3,5

IN

R2104 5%

1K

2.37K

5.49K

1uF

2.37K

5.49K

1uF

2.37K

5.49K

1uF

6.3V

3

IN

+MVDD

C2212

C2213

C2206

0.1uF

+MVDD

C2219

1uF

C2214

C2208

C2209

C2211

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

C2227

C2228

C2229

C2220

C2223

C2226

1uF

1uF

1uF

1uF

1uF

1uF

23CNOPN001

U2100

M2

DQ31__DQ7

M4

DQ30__DQ6

N2

DQ29__DQ5

N4

DQ28__DQ4

T2

DQ27__DQ3

T4

DQ26__DQ2

V2

DQ25__DQ1

V4

DQ24__DQ0

M13

DQ23__DQ15

M11

DQ22__DQ14

N13

DQ21__DQ13

N11

DQ20__DQ12

T13

DQ19__DQ11

T11

DQ18__DQ10

V13

DQ17__DQ9

V11

DQ16__DQ8

F13

DQ15__DQ23

F11

DQ14__DQ22

E13

DQ13__DQ21

E11

DQ12__DQ20

B13

DQ11__DQ19

B11

DQ10__DQ18

A13

DQ9__DQ17

A11

DQ8__DQ16

F2

DQ7__DQ31

F4

DQ6__DQ30

E2

DQ5__DQ29

E4

DQ4__DQ28

B2

DQ3__DQ27

B4

DQ2__DQ26

A2

DQ1__DQ25

A4

DQ0__DQ24

J5

RFU_A12_NC

K4

A7_A8__A0_A10

K5

A6_A11__A1_A9

K10

A5_BA1__A3_BA3

K11

A4_BA2__A2_BA0

H10

A3_BA3__A5_BA1

H11

A2_BA0__A4_BA2

H5

A1_A9__A6_A11

H4

A0_A10__A7_A8

D4

WCK01__WCK23

D5

WCK01#__WCK23#

P4

WCK23__WCK01

P5

WCK23#__WCK01#

R2

EDC3__EDC0

R13

EDC2__EDC1

C13

EDC1__EDC2

C2

EDC0__EDC3

P2

DBI3#__DBI0#

P13

DBI2#__DBI1#

D13

DBI1#__DBI2#

D2

DBI0#__DBI3#

G3

RAS#__CAS#

L3

CAS#__RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS#__WE#

L12

WE#__CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp_NC

V5

Vpp_NC1

A10

VREFD1

V10

VREFD2

J14

VREFC

J4

ABI#

C2218

0.1uF

C2230

C2240

C2241

1uF

10uF

10uF

+MVDD

B1

VDDQ_B1

B3

VDDQ_B3

B12

VDDQ_B12

B14

VDDQ_B14

D1

VDDQ_D1

D3

VDDQ_D3

D12

VDDQ_D12

D14

VDDQ_D14

E5

VDDQ_E5

E10

VDDQ_E10

F1

VDDQ_F1

F3

VDDQ_F3

F12

VDDQ_F12

F14

VDDQ_F14

G2

VDDQ_G2

G13

VDDQ_G13

H3

VDDQ_H3

H12

VDDQ_H12

K3

VDDQ_K3

K12

VDDQ_K12

L2

VDDQ_L2

L13

VDDQ_L13

M1

VDDQ_M1

M3

VDDQ_M3

M12

VDDQ_M12

M14

VDDQ_M14

N5

VDDQ_N5

N10

VDDQ_N10

P1

VDDQ_P1

P3

VDDQ_P3

P12

VDDQ_P12

P14

VDDQ_P14

T1

VDDQ_T1

T3

VDDQ_T3

T12

VDDQ_T12

T14

VDDQ_T14

+MVDD

C5

VDD_C5

C10

VDD_C10

D11

VDD_D11

G1

VDD_G1

G4

VDD_G4

G11

VDD_G11

G14

VDD_G14

L1

VDD_L1

L4

VDD_L4

L11

VDD_L11

L14

VDD_L14

P11

VDD_P11

R5

VDD_R5

R10

VDD_R10

A1

VSSQ_A1

A3

VSSQ_A3

A12

VSSQ_A12

A14

VSSQ_A14

C1

VSSQ_C1

C3

VSSQ_C3

C4

VSSQ_C4

C11

VSSQ_C11

C12

VSSQ_C12

C14

VSSQ_C14

E1

VSSQ_E1

E3

VSSQ_E3

E12

VSSQ_E12
VSSQ_E14

VSSQ_F5

VSSQ_F10

VSSQ_H2

VSSQ_H13

VSSQ_K2

VSSQ_K13

VSSQ_M5

VSSQ_M10

VSSQ_N1

VSSQ_N3
VSSQ_N12
VSSQ_N14

VSSQ_R1

VSSQ_R3

VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14

VSSQ_V1

VSSQ_V3
VSSQ_V12
VSSQ_V14

VSS_B5
VSS_B10
VSS_D10

VSS_G5
VSS_G10

VSS_H1

VSS_H14

VSS_K1

VSS_K14

VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10

+MVDD

C2306

C2308

0.1uF

0.1uF

+MVDD

C2319

C2321

1uF

1uF

+MVDD

E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

C2309

C2311

0.1uF

0.1uF

C2322

C2323

1uF

1uF

R2201
R2200 1%

R2203 5%

R2204 5%

R2205 1%

+MVDD

R2206 1%
C2201 6.3V

R2207 1%

+MVDD

R2208 1%
C2203 6.3V

R2209 1%

+MVDD

R2210 1%
C2205 6.3V

C2317

C2312

C2314

C2316

0.1uF

0.1uF

0.1uF

0.1uF

C2324

1uF

C2341

C2325

C2326

C2328

C2340

10uF

1uF

1uF

1uF

10uF

DQB0_<30>
DQB0_<25>
DQB0_<29>
DQB0_<24>
DQB0_<28>
DQB0_<26>
DQB0_<31>
DQB0_<27>
DQB0_<17>
DQB0_<16>
DQB0_<18>
DQB0_<19>
DQB0_<21>
DQB0_<23>
DQB0_<20>
DQB0_<22>
DQB0_<5>
DQB0_<6>
DQB0_<4>
DQB0_<7>
DQB0_<3>
DQB0_<2>
DQB0_<1>
DQB0_<0>
DQB0_<11>
DQB0_<10>
DQB0_<8>
DQB0_<9>
DQB0_<12>
DQB0_<13>
DQB0_<14>
DQB0_<15>

MAB0_<8>
MAB0_<7>
MAB0_<6>
MAB0_<5>
MAB0_<4>
MAB0_<3>
MAB0_<2>
MAB0_<1>
MAB0_<0>

WCKB0_0

3

IN

WCKB0B_0

3

IN

WCKB0_1

3

IN

WCKB0B_1

3

IN

EDCB0_3 EDCB1_0

3

OUT

EDCB0_2

3

OUT

3

OUT

EDCB0_1

3

OUT

DDBIB0_3 DDBIB1_0

3

BI

DDBIB0_2

3

BI

3

BI

DDBIB0_1

3

BI

RASB0B

3

IN

CASB0B

3

IN

60.4R

1%

60.4R

3

IN

CLKB0B

3

IN

CLKB0

3

IN

CSB0B_0

3

IN

WEB0B

3

IN

R2202 1%

120R

1K

3,5

IN

1K

2.37K

5.49K

1uF

2.37K

5.49K

1uF

2.37K

5.49K

1uF

3

IN

DRAM SCAN PINS
SSH [J2] - SCAN SHIFT
SCK [G12] - SCAN CLOCK
SOUT [C2] - SCAN OUTPUT
SEN [J10] - SCAN ENABLE
SOE# [J1] - SCAN OUTPUT ENABLE

M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11

K10
K11
H10
H11

R13
C13

P13
D13

G12

M2
M4

N2
N4
T2
T4
V2
V4

F2
F4
E2
E4
B2
B4
A2
A4

K4
K5

H5
H4

D4
D5

P4
P5

R2

C2
P2

D2

G3

J11
J12

L12

J13
J10

A10
V10

J14

J5

L3

J3

J2
J1

A5
V5

J4

DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24

RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8

WCK01__WCK23
WCK01#__WCK23#

WCK23__WCK01
WCK23#__WCK01#

EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3

DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#

RAS#__CAS#
CAS#__RAS#

CKE#
CK#
CK

CS#__WE#
WE#__CS#

ZQ
SEN

RESET#
MF

Vpp_NC
Vpp_NC1

VREFD1
VREFD2

VREFC

ABI#

23CNOPN001

U2200

VDDQ_B1

VDDQ_B3
VDDQ_B12
VDDQ_B14

VDDQ_D1

VDDQ_D3
VDDQ_D12
VDDQ_D14

VDDQ_E5
VDDQ_E10

VDDQ_F1

VDDQ_F3
VDDQ_F12
VDDQ_F14

VDDQ_G2
VDDQ_G13

VDDQ_H3
VDDQ_H12

VDDQ_K3
VDDQ_K12

VDDQ_L13

VDDQ_M1

VDDQ_M3
VDDQ_M12
VDDQ_M14

VDDQ_N5
VDDQ_N10

VDDQ_P1

VDDQ_P3
VDDQ_P12
VDDQ_P14

VDDQ_T1

VDDQ_T3
VDDQ_T12
VDDQ_T14

VSSQ_A1

VSSQ_A3
VSSQ_A12
VSSQ_A14

VSSQ_C1

VSSQ_C3

VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14

VSSQ_E1

VSSQ_E3
VSSQ_E12
VSSQ_E14

VSSQ_F5
VSSQ_F10

VSSQ_H2
VSSQ_H13

VSSQ_K2
VSSQ_K13

VSSQ_M5
VSSQ_M10

VSSQ_N1

VSSQ_N3

VSSQ_N12

VSSQ_N14

VSSQ_R1

VSSQ_R3

VSSQ_R4

VSSQ_R11

VSSQ_R12

VSSQ_R14

VSSQ_V1

VSSQ_V3

VSSQ_V12

VSSQ_V14

+MVDD

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2

VDDQ_L2

L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

+MVDD

C5

VDD_C5

C10

VDD_C10

D11

VDD_D11

G1

VDD_G1

G4

VDD_G4

G11

VDD_G11

G14

VDD_G14

L1

VDD_L1

L4

VDD_L4

L11

VDD_L11

L14

VDD_L14

P11

VDD_P11

R5

VDD_R5

R10

VDD_R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12

+MVDD

E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5

VSS_B5

B10

VSS_B10

D10

VSS_D10

G5

VSS_G5

G10

VSS_G10

H1

VSS_H1

H14

VSS_H14

K1

VSS_K1

K14

VSS_K14

L5

VSS_L5

L10

VSS_L10

P10

VSS_P10

T5

VSS_T5

T10

VSS_T10

+MVDD

+MVDD

+MVDD

R2301 1%
R2300 1%

R2302
R23031K5%

R2304 5%

+MVDD

R2305
R2306 1%
C2301 6.3V

R2307 1%
R2308 1%
C2303 6.3V

R2309 1%
R2310 1%
C2305 6.3V

DQB1_<5>
DQB1_<6>
DQB1_<4>
DQB1_<7>
DQB1_<3>
DQB1_<2>
DQB1_<1>
DQB1_<0>
DQB1_<11>
DQB1_<10>
DQB1_<8>
DQB1_<9>
DQB1_<12>
DQB1_<13>
DQB1_<14>
DQB1_<15>
DQB1_<25>
DQB1_<24>
DQB1_<27>
DQB1_<26>
DQB1_<29>
DQB1_<30>
DQB1_<28>
DQB1_<31>
DQB1_<17>
DQB1_<16>
DQB1_<18>
DQB1_<19>
DQB1_<20>
DQB1_<22>
DQB1_<21>
DQB1_<23>

MAB1_<8>
MAB1_<0>
MAB1_<1>
MAB1_<3>
MAB1_<2>
MAB1_<5>
MAB1_<4>
MAB1_<6>
MAB1_<7>

WCKB1_1

3

IN

WCKB1B_1

3

IN

WCKB1_0

3

IN

WCKB1B_0

3

IN

3

OUT

EDCB1_1

3

OUT

EDCB1_3

3

OUT

EDCB1_2

3

OUT

3

BI

DDBIB1_1

3

BI

DDBIB1_3

3

BI

DDBIB1_2

3

BI

CASB1B

3

IN

RASB1B

3

IN

60.4R

60.4R

3

IN

CLKB1B

3

IN

CLKB1

3

IN

WEB1B

3

IN

CSB1B_0

3

IN

120R

1%

3,5

IN

1K

2.37K

1%

5.49K

1uF

2.37K

5.49K

1uF

2.37K

5.49K

1uF

3

IN

M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11

K10
K11
H10
H11

R13
C13

P13
D13

J11
J12

G12
L12

J13
J10

A10
V10

J14

M2
M4
N2
N4
T2
T4
V2
V4

F2
F4
E2
E4
B2
B4
A2
A4

J5
K4
K5

H5
H4

D4
D5

P4
P5

R2

C2
P2

D2

G3

L3

J3

J2

J1

A5

V5

J4

DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24

RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8

WCK01__WCK23
WCK01#__WCK23#

WCK23__WCK01
WCK23#__WCK01#

EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3

DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#

RAS#__CAS#
CAS#__RAS#

CKE#
CK#
CK

CS#__WE#
WE#__CS#

ZQ
SEN

RESET#
MF

Vpp_NC
Vpp_NC1

VREFD1
VREFD2

VREFC

ABI#

GDDR5

23CNOPN001

U2300

VDDQ_B12
VDDQ_B14

VDDQ_D12
VDDQ_D14

VDDQ_E10

VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13

VDDQ_H12

VDDQ_K12

VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14

VDDQ_N10

VDDQ_P12
VDDQ_P14

VDDQ_T12
VDDQ_T14

VSSQ_A12
VSSQ_A14

VSSQ_C11
VSSQ_C12
VSSQ_C14

VSSQ_E12
VSSQ_E14

VSSQ_F10

VSSQ_H13

VSSQ_K13
VSSQ_M5
VSSQ_M10

VSSQ_N12
VSSQ_N14

VSSQ_R11
VSSQ_R12
VSSQ_R14

VSSQ_V12
VSSQ_V14

VDDQ_B1
VDDQ_B3

VDDQ_D1
VDDQ_D3

VDDQ_E5

VDDQ_F1
VDDQ_F3

VDDQ_H3

VDDQ_K3

VDDQ_L2

VDDQ_N5

VDDQ_P1
VDDQ_P3

VDDQ_T1
VDDQ_T3

VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14

VDD_L11
VDD_L14
VDD_P11

VDD_R10

VSSQ_A1
VSSQ_A3

VSSQ_C1
VSSQ_C3
VSSQ_C4

VSSQ_E1
VSSQ_E3

VSSQ_F5

VSSQ_H2

VSSQ_K2

VSSQ_N1
VSSQ_N3

VSSQ_R1
VSSQ_R3
VSSQ_R4

VSSQ_V1
VSSQ_V3

VSS_B10
VSS_D10
VSS_G5
VSS_G10

VSS_H14

VSS_K14

VSS_L10
VSS_P10

VSS_T10

+MVDD

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

+MVDD

C5

VDD_C5

C10
D11
G1
G4
G11
G14
L1

VDD_L1

L4

VDD_L4

L11
L14
P11
R5

VDD_R5

R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5

VSS_B5

B10
D10
G5
G10
H1

VSS_H1

H14
K1

VSS_K1

K14
L5

VSS_L5

L10
P10
T5

VSS_T5

T10

DQA0_<0>

5

BI

DQA0_<1>

5

BI

DQA0_<2>

5

BI

DQA0_<3>

5

BI

DQA0_<4>

5

BI

DQA0_<5>

5

BI

DQA0_<6>

5

BI

DQA0_<7>

5

BI

DQA0_<8>

5

BI

DQA0_<9>

5

BI

DQA0_<10>

5

BI

DQA0_<11>

5

BI

DQA0_<12>

5

BI

DQA0_<13>

5

BI

DQA0_<14>

5

BI

DQA0_<15>

5

BI

DQA0_<16>

5

BI

D D

DQA0_<17>

5

BI

DQA0_<18>

5

BI

DQA0_<19>

5

BI

DQA0_<20>

5

BI

DQA0_<21>

5

BI

DQA0_<22>

5

BI

DQA0_<23>

5

BI

DQA0_<24>

5

BI

DQA0_<25>

5

BI

DQA0_<26>

5

BI

DQA0_<27>

5

BI

DQA0_<28>

5

BI

DQA0_<29>

5

BI

DQA0_<30>

5

BI

DQA0_<31>

5

BI

1

MAA0_<0>

5

OUT

MAA0_<1>

5

OUT

MAA0_<2>

5

OUT

MAA0_<3>

5

OUT

MAA0_<4>

5

OUT

MAA0_<5>

5

OUT

MAA0_<6>

5

OUT

MAA0_<7>

5

OUT

MAA0_<8>

5

OUT

2

DQA1_<0>
DQA1_<1>
DQA1_<2>
DQA1_<3>
DQA1_<4>
DQA1_<5>
DQA1_<6>
DQA1_<7>
DQA1_<8>
DQA1_<9>
DQA1_<10>
DQA1_<11>
DQA1_<12>
DQA1_<13>
DQA1_<14>
DQA1_<15>
DQA1_<16>
DQA1_<17>
DQA1_<18>
DQA1_<19>
DQA1_<20>
DQA1_<21>
DQA1_<22>
DQA1_<23>
DQA1_<24>
DQA1_<25>
DQA1_<26>
DQA1_<27>
DQA1_<28>
DQA1_<29>
DQA1_<30>
DQA1_<31>

MAA1_<0>

5

BI

MAA1_<1>

5

BI

MAA1_<2>

5

BI

MAA1_<3>

5

BI

MAA1_<4>

5

BI

MAA1_<5>

5

BI

MAA1_<6>

5

BI

MAA1_<7>

5

BI

MAA1_<8>

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

3

DQB0_<0>

5

BI

DQB0_<1>

5

BI

DQB0_<2>

5

BI

DQB0_<3>

5

BI

DQB0_<4>

5

BI

DQB0_<5>

5

BI

DQB0_<6>

5

BI

DQB0_<7>

5

BI

DQB0_<8>

5

BI

DQB0_<9>

5

BI

DQB0_<10>

5

BI

DQB0_<11>

5

BI

DQB0_<12>

5

BI

DQB0_<13>

5

BI

DQB0_<14>

5

BI

DQB0_<15>

5

BI

DQB0_<16>

5

BI

DQB0_<17>

5

BI

DQB0_<18>

5

BI

DQB0_<19>

5

BI

DQB0_<20>

5

BI

DQB0_<21>

5

BI

DQB0_<22>

5

BI

DQB0_<23>

5

BI

DQB0_<24>

5

BI

DQB0_<25>

5

BI

DQB0_<26>

5

BI

DQB0_<27>

5

BI

DQB0_<28>

5

BI

DQB0_<29>

5

BI

DQB0_<30>

5

BI

DQB0_<31>

5

BI

4

MAB0_<0>

5

OUT

MAB0_<1>

5

OUT

MAB0_<2>

5

OUT

MAB0_<3>

5

OUT

MAB0_<4>

5

OUT

MAB0_<5>

5

OUT

MAB0_<6>

5

OUT

MAB0_<7>

5

OUT

MAB0_<8>

5

OUT

5

DQB1_<0>
DQB1_<1>
DQB1_<2>
DQB1_<3>
DQB1_<4>
DQB1_<5>
DQB1_<6>
DQB1_<7>
DQB1_<8>
DQB1_<9>
DQB1_<10>
DQB1_<11>
DQB1_<12>
DQB1_<13>
DQB1_<14>
DQB1_<15>
DQB1_<16>
DQB1_<17>
DQB1_<18>
DQB1_<19>
DQB1_<20>
DQB1_<21>
DQB1_<22>
DQB1_<23>
DQB1_<24>
DQB1_<25>
DQB1_<26>
DQB1_<27>
DQB1_<28>
DQB1_<29>
DQB1_<30>
DQB1_<31>

MAB1_<0>

5

BI

MAB1_<1>

5

BI

MAB1_<2>

5

BI

MAB1_<3>

5

BI

MAB1_<4>

5

BI

MAB1_<5>

5

BI

MAB1_<6>

5

BI

MAB1_<7>

5

BI

MAB1_<8>

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

6

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

5

OUT

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev
Custom

Custom

Custom
Date:

Date:

7

Date:

05 GDDR5 MEM CH AB

05 GDDR5 MEM CH AB

05 GDDR5 MEM CH AB

Friday, August 16, 2013

Friday, August 16, 2013

Friday, August 16, 2013

MS-V305

Sheet of

Sheet of

Sheet of

8

523

523

523

10

10

10

1

2

3

4

5

6

7

8

(6) GDDR5 MEMORY CH C/D

DQC0_<14>
DQC0_<15>
DQC0_<13>
DQC0_<12>
DQC0_<11>
DQC0_<9>
DQC0_<10>
DQC0_<8>
DQC0_<6>
DQC0_<7>
DQC0_<4>
DQC0_<5>
DQC0_<2>
DQC0_<1>

A A

B B

C C

+MVDD

R2401
R2400

R2405

+MVDD

R2406
C2401

R2407

+MVDD

R2408
C2403

R2409

+MVDD

R2410
C2405

+MVDD

C2407

C2408

0.1uF

0.1uF

+MVDD

C2417

C2418

1uF

1uF

DQC0_<3>
DQC0_<0>
DQC0_<20>
DQC0_<21>
DQC0_<23>
DQC0_<22>
DQC0_<19>
DQC0_<18>
DQC0_<17>
DQC0_<16>
DQC0_<26>
DQC0_<25>
DQC0_<27>
DQC0_<24>
DQC0_<28>
DQC0_<29>
DQC0_<30>
DQC0_<31>

MAC0_<8>
MAC0_<7>
MAC0_<6>
MAC0_<5>
MAC0_<4>
MAC0_<3>
MAC0_<2>
MAC0_<1>
MAC0_<0>

WCKC0_1

4

IN

WCKC0B_1

4

IN

WCKC0_0

4

IN

WCKC0B_0

4

IN

EDCC0_1

4

OUT

EDCC0_0

4

OUT

EDCC0_2

4

OUT

EDCC0_3 EDCC1_0

4

OUT

DDBIC0_1

4

BI

DDBIC0_0

4

BI

DDBIC0_2

4

BI

DDBIC0_3 DDBIC1_0

4

BI

RASC0B

4

IN

CASC0B

4

IN

60.4R

1%

60.4R

1%

CKEC0 CKEC1 CKED0 CKED1

4

IN

CLKC0B

4

IN

CLKC0

4

IN

CSC0B_0

4

IN

WEC0B

4

IN

ZQ_C0 ZQ_C1 ZQ_D0 ZQ_D1

R2402

120R

1%

SEN_C0 SEN_C1 SEN_D0 SEN_D1

R24031K5%

DRAM_RST2 DRAM_RST2 DRAM_RST2 DRAM_RST2

4,6

IN

MF_C0 MF_C1 MF_D0 MF_D1

R24041K5%

2.37K

1%

5.49K

1%

VREFD1_C0 VREFD1_C1 VREFD1_D0 VREFD1_D1

1uF

6.3V

2.37K

1%

5.49K

1%

VREFD2_C0 VREFD2_C1 VREFD2_D0 VREFD2_D1

1uF

6.3V

2.37K

1%

5.49K

1%

VREFC_C0 VREFC_C1 VREFC_D0 VREFC_D1

1uF

6.3V

ADBIC0 ADBIC1 ADBID0 ADBID1

4

IN

C2410

C2411

C2413

C2414

C2415

C2409

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

C2420

C2421

C2422

C2423

C2425

C2419

1uF

1uF

C2440

1uF

1uF

1uF

1uF

10uF

23CNOPN001

U2400

M2

DQ31__DQ7

M4

DQ30__DQ6

N2

DQ29__DQ5

N4

DQ28__DQ4

T2

DQ27__DQ3

T4

DQ26__DQ2

V2

DQ25__DQ1

V4

DQ24__DQ0

M13

DQ23__DQ15

M11

DQ22__DQ14

N13

DQ21__DQ13

N11

DQ20__DQ12

T13

DQ19__DQ11

T11

DQ18__DQ10

V13

DQ17__DQ9

V11

DQ16__DQ8

F13

DQ15__DQ23

F11

DQ14__DQ22

E13

DQ13__DQ21

E11

DQ12__DQ20

B13

DQ11__DQ19

B11

DQ10__DQ18

A13

DQ9__DQ17

A11

DQ8__DQ16

F2

DQ7__DQ31

F4

DQ6__DQ30

E2

DQ5__DQ29

E4

DQ4__DQ28

B2

DQ3__DQ27

B4

DQ2__DQ26

A2

DQ1__DQ25

A4

DQ0__DQ24

J5

RFU_A12_NC

K4

A7_A8__A0_A10

K5

A6_A11__A1_A9

K10

A5_BA1__A3_BA3

K11

A4_BA2__A2_BA0

H10

A3_BA3__A5_BA1

H11

A2_BA0__A4_BA2

H5

A1_A9__A6_A11

H4

A0_A10__A7_A8

D4

WCK01__WCK23

D5

WCK01#__WCK23#

P4

WCK23__WCK01

P5

WCK23#__WCK01#

R2

EDC3__EDC0

R13

EDC2__EDC1

C13

EDC1__EDC2

C2

EDC0__EDC3

P2

DBI3#__DBI0#

P13

DBI2#__DBI1#

D13

DBI1#__DBI2#

D2

DBI0#__DBI3#

G3

RAS#__CAS#

L3

CAS#__RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS#__WE#

L12

WE#__CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp_NC

V5

Vpp_NC1

A10

VREFD1

V10

VREFD2

J14

VREFC

J4

ABI#

+MVDD

C2506

0.1uF

+MVDD

C2441

C2521

1uF

10uF

+MVDD

B1

VDDQ_B1

B3

VDDQ_B3

B12

VDDQ_B12

B14

VDDQ_B14

D1

VDDQ_D1

D3

VDDQ_D3

D12

VDDQ_D12

D14

VDDQ_D14

E5

VDDQ_E5

E10

VDDQ_E10

F1

VDDQ_F1

F3

VDDQ_F3

F12

VDDQ_F12

F14

VDDQ_F14

G2

VDDQ_G2

G13

VDDQ_G13

H3

VDDQ_H3

H12

VDDQ_H12

K3

VDDQ_K3

K12

VDDQ_K12

L2

VDDQ_L2

L13

VDDQ_L13

M1

VDDQ_M1

M3

VDDQ_M3

M12

VDDQ_M12

M14

VDDQ_M14

N5

VDDQ_N5

N10

VDDQ_N10

P1

VDDQ_P1

P3

VDDQ_P3

P12

VDDQ_P12

P14

VDDQ_P14

T1

VDDQ_T1

T3

VDDQ_T3

T12

VDDQ_T12

T14

VDDQ_T14

+MVDD

C5

VDD_C5

C10

VDD_C10

D11

VDD_D11

G1

VDD_G1

G4

VDD_G4

G11

VDD_G11

G14

VDD_G14

L1

VDD_L1

L4

VDD_L4

L11

VDD_L11

L14

VDD_L14

P11

VDD_P11

R5

VDD_R5

R10

VDD_R10

A1

VSSQ_A1

A3

VSSQ_A3

A12

VSSQ_A12

A14

VSSQ_A14

C1

VSSQ_C1

C3

VSSQ_C3

C4

VSSQ_C4

C11

VSSQ_C11

C12

VSSQ_C12

C14

VSSQ_C14

E1

VSSQ_E1

E3

VSSQ_E3

E12

VSSQ_E12
VSSQ_E14

VSSQ_F5

VSSQ_F10

VSSQ_H2

VSSQ_H13

VSSQ_K2

VSSQ_K13

VSSQ_M5

VSSQ_M10

VSSQ_N1

VSSQ_N3
VSSQ_N12
VSSQ_N14

VSSQ_R1

VSSQ_R3

VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14

VSSQ_V1

VSSQ_V3
VSSQ_V12
VSSQ_V14

VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10

VSS_H1
VSS_H14

VSS_K1
VSS_K14

VSS_L5
VSS_L10
VSS_P10

VSS_T5
VSS_T10

C2509

C2512

C2507

C2508

0.1uF

0.1uF

0.1uF

0.1uF

C2525

C2522

C2523

C2524

1uF

1uF

1uF

1uF

+MVDD

E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

C2513

C2515

0.1uF

0.1uF

C2526

C2527

1uF

1uF

R2501
R2500

+MVDD

R2505

+MVDD

R2506
C2501

R2507

+MVDD

R2508
C2503

R2509

+MVDD

R2510
C2505

+MVDD

C2519

0.1uF

C2528

C2540

1uF

10uF

C2607

0.1uF

+MVDD

C2541

C2617

10uF

1uF

DQC1_<20>
DQC1_<21>
DQC1_<23>
DQC1_<22>
DQC1_<19>
DQC1_<18>
DQC1_<17>
DQC1_<16>
DQC1_<26>
DQC1_<25>
DQC1_<27>
DQC1_<24>
DQC1_<28>
DQC1_<29>
DQC1_<30>
DQC1_<31>
DQC1_<14>
DQC1_<15>
DQC1_<13>
DQC1_<12>
DQC1_<10>
DQC1_<8>
DQC1_<11>
DQC1_<9>
DQC1_<1>
DQC1_<6>
DQC1_<2>
DQC1_<7>
DQC1_<3>
DQC1_<5>
DQC1_<0>
DQC1_<4>

MAC1_<8>
MAC1_<0>
MAC1_<1>
MAC1_<3>
MAC1_<2>
MAC1_<5>
MAC1_<4>
MAC1_<6>
MAC1_<7>

WCKC1_0

4

IN

WCKC1B_0

4

IN

WCKC1_1

4

IN

WCKC1B_1

4

IN

EDCC1_2

4

OUT

EDCC1_3 EDCD0_0

4

OUT

EDCC1_1

4

OUT

4

OUT

DDBIC1_2

4

BI

DDBIC1_3 DDBID0_0

4

BI

DDBIC1_1

4

BI

4

BI

CASC1B

4

IN

RASC1B

4

IN

60.4R

1%

60.4R

1%

4

IN

CLKC1B

4

IN

CLKC1

4

IN

WEC1B

4

IN

CSC1B_0

4

IN

R2502

120R

1%

R25031K5%

4,6

IN

R25041K5%

2.37K

1%

5.49K

1%

1uF

6.3V

2.37K

1%

5.49K

1%

1uF

6.3V

2.37K

1%

5.49K

1%

1uF

6.3V

4

IN

C2611

C2612

C2613

C2608

0.1uF

C2619

1uF

C2614

C2609

C2610

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

C2622

C2623

C2624

C2625

C2620

C2621

1uF

1uF

1uF

1uF

1uF

1uF

23CNOPN001

U2500

M2

DQ31__DQ7

M4

DQ30__DQ6

N2

DQ29__DQ5

N4

DQ28__DQ4

T2

DQ27__DQ3

T4

DQ26__DQ2

V2

DQ25__DQ1

V4

DQ24__DQ0

M13

DQ23__DQ15

M11

DQ22__DQ14

N13

DQ21__DQ13

N11

DQ20__DQ12

T13

DQ19__DQ11

T11

DQ18__DQ10

V13

DQ17__DQ9

V11

DQ16__DQ8

F13

DQ15__DQ23

F11

DQ14__DQ22

E13

DQ13__DQ21

E11

DQ12__DQ20

B13

DQ11__DQ19

B11

DQ10__DQ18

A13

DQ9__DQ17

A11

DQ8__DQ16

F2

DQ7__DQ31

F4

DQ6__DQ30

E2

DQ5__DQ29

E4

DQ4__DQ28

B2

DQ3__DQ27

B4

DQ2__DQ26

A2

DQ1__DQ25

A4

DQ0__DQ24

J5

RFU_A12_NC

K4

A7_A8__A0_A10

K5

A6_A11__A1_A9

K10

A5_BA1__A3_BA3

K11

A4_BA2__A2_BA0

H10

A3_BA3__A5_BA1

H11

A2_BA0__A4_BA2

H5

A1_A9__A6_A11

H4

A0_A10__A7_A8

D4

WCK01__WCK23

D5

WCK01#__WCK23#

P4

WCK23__WCK01

P5

WCK23#__WCK01#

R2

EDC3__EDC0

R13

EDC2__EDC1

C13

EDC1__EDC2

C2

EDC0__EDC3

P2

DBI3#__DBI0#

P13

DBI2#__DBI1#

D13

DBI1#__DBI2#

D2

DBI0#__DBI3#

G3

RAS#__CAS#

L3

CAS#__RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS#__WE#

L12

WE#__CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp_NC

V5

Vpp_NC1

A10

VREFD1

V10

VREFD2

J14

VREFC

J4

ABI#

+MVDD

+MVDD

C2640

C2641

10uF

10uF

+MVDD

B1

VDDQ_B1

B3

VDDQ_B3

B12

VDDQ_B12

B14

VDDQ_B14

D1

VDDQ_D1

D3

VDDQ_D3

D12

VDDQ_D12

D14

VDDQ_D14

E5

VDDQ_E5

E10

VDDQ_E10

F1

VDDQ_F1

F3

VDDQ_F3

F12

VDDQ_F12

F14

VDDQ_F14

G2

VDDQ_G2

G13

VDDQ_G13

H3

VDDQ_H3

H12

VDDQ_H12

K3

VDDQ_K3

K12

VDDQ_K12

L2

VDDQ_L2

L13

VDDQ_L13

M1

VDDQ_M1

M3

VDDQ_M3

M12

VDDQ_M12

M14

VDDQ_M14

N5

VDDQ_N5

N10

VDDQ_N10

P1

VDDQ_P1

P3

VDDQ_P3

P12

VDDQ_P12

P14

VDDQ_P14

T1

VDDQ_T1

T3

VDDQ_T3

T12

VDDQ_T12

T14

VDDQ_T14

+MVDD

C5

VDD_C5

C10

VDD_C10

D11

VDD_D11

G1

VDD_G1

G4

VDD_G4

G11

VDD_G11

G14

VDD_G14

L1

VDD_L1

L4

VDD_L4

L11

VDD_L11

L14

VDD_L14

P11

VDD_P11

R5

VDD_R5

R10

VDD_R10

A1

VSSQ_A1

A3

VSSQ_A3

A12

VSSQ_A12

A14

VSSQ_A14

C1

VSSQ_C1

C3

VSSQ_C3

C4

VSSQ_C4

C11

VSSQ_C11

C12

VSSQ_C12

C14

VSSQ_C14

E1

VSSQ_E1

E3

VSSQ_E3

E12

VSSQ_E12

E14

VSSQ_E14

F5

VSSQ_F5

F10

VSSQ_F10

H2

VSSQ_H2

H13

VSSQ_H13

K2

VSSQ_K2

K13

VSSQ_K13

M5

VSSQ_M5

M10

VSSQ_M10

N1

VSSQ_N1

N3

VSSQ_N3

N12

VSSQ_N12

N14

VSSQ_N14

R1

VSSQ_R1

R3

VSSQ_R3

R4

VSSQ_R4

R11

VSSQ_R11

R12

VSSQ_R12

R14

VSSQ_R14

V1

VSSQ_V1

V3

VSSQ_V3

V12

VSSQ_V12

V14

VSSQ_V14

B5

VSS_B5

B10

VSS_B10

D10

VSS_D10

G5

VSS_G5

G10

VSS_G10

H1

VSS_H1

H14

VSS_H14

K1

VSS_K1

K14

VSS_K14

L5

VSS_L5

L10

VSS_L10

P10

VSS_P10

T5

VSS_T5

T10

VSS_T10

C2707

C2708

C2710

C2711

0.1uF

0.1uF

0.1uF

0.1uF

C2717

C2718

C2719

C2720

1uF

1uF

1uF

1uF

+MVDD

R2601
R2600

R26031K5%

R26041K5%

R2605

+MVDD

R2606

C2601

R2607

+MVDD

R2608

C2603

R2609

+MVDD

R2610

C2605

C2716

C2712

C2714

C2715

0.1uF

0.1uF

0.1uF

0.1uF

DRAM SCAN PINS
SSH [J2] - SCAN SHIFT
SCK [G12] - SCAN CLOCK

C2724

C2740

C2721

1uF

C2741

C2722

C2723

1uF

1uF

SOUT [C2] - SCAN OUTPUT
SEN [J10] - SCAN ENABLE

1uF

10uF

10uF

SOE# [J1] - SCAN OUTPUT ENABLE

DQD0_<13>
DQD0_<15>
DQD0_<12>
DQD0_<14>
DQD0_<11>
DQD0_<9>
DQD0_<10>
DQD0_<8>
DQD0_<7>
DQD0_<6>
DQD0_<4>
DQD0_<5>
DQD0_<0>
DQD0_<2>
DQD0_<1>
DQD0_<3>
DQD0_<20>
DQD0_<21>
DQD0_<23>
DQD0_<22>
DQD0_<19>
DQD0_<17>
DQD0_<18>
DQD0_<16>
DQD0_<26>
DQD0_<25>
DQD0_<27>
DQD0_<24>
DQD0_<28>
DQD0_<29>
DQD0_<30>
DQD0_<31>

MAD0_<8>
MAD0_<7>
MAD0_<6>
MAD0_<5>
MAD0_<4>
MAD0_<3>
MAD0_<2>
MAD0_<1>
MAD0_<0>

WCKD0_1

4

IN

WCKD0B_1

4

IN

WCKD0_0

4

IN

WCKD0B_0

4

IN

EDCD0_1

4

OUT

4

OUT

EDCD0_2

4

OUT

EDCD0_3

4

OUT

DDBID0_1

4

BI

4

BI

DDBID0_2

4

BI

DDBID0_3

4

BI

RASD0B

4

IN

CASD0B

4

IN

60.4R

1%

60.4R

1%

4

IN

CLKD0B

4

IN

CLKD0

4

IN

CSD0B_0

4

IN

WED0B

4

IN

R2602

120R

1%

4,6

IN

2.37K

1%

5.49K

1%

1uF

6.3V

2.37K

1%

5.49K

1%

1uF

6.3V

2.37K

1%

5.49K

1%

1uF

6.3V

4

IN

M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11

K10
K11
H10
H11

R13
C13

P13
D13

G12

M2
M4

N2
N4
T2
T4
V2
V4

F2
F4
E2
E4
B2
B4
A2
A4

K4
K5

H5
H4

D4
D5

P4
P5

R2

C2
P2

D2

G3

J11
J12

L12

J13
J10

A10
V10

J14

J5

L3

J3

J2
J1

A5
V5

J4

DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24

RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8

WCK01__WCK23
WCK01#__WCK23#

WCK23__WCK01
WCK23#__WCK01#

EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3

DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#

RAS#__CAS#
CAS#__RAS#

CKE#
CK#
CK

CS#__WE#
WE#__CS#

ZQ
SEN

RESET#
MF

Vpp_NC
Vpp_NC1

VREFD1
VREFD2

VREFC

ABI#

23CNOPN001

U2600

VDDQ_B12
VDDQ_B14

VDDQ_D12
VDDQ_D14

VDDQ_E10

VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13

VDDQ_H12

VDDQ_K12

VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14

VDDQ_N10

VDDQ_P12
VDDQ_P14

VDDQ_T12
VDDQ_T14

VSSQ_A12
VSSQ_A14

VSSQ_C11
VSSQ_C12
VSSQ_C14

VSSQ_E12
VSSQ_E14

VSSQ_F10

VSSQ_H13

VSSQ_K13
VSSQ_M5
VSSQ_M10

VSSQ_N12
VSSQ_N14

VSSQ_R11
VSSQ_R12
VSSQ_R14

VSSQ_V12
VSSQ_V14

VDDQ_B1
VDDQ_B3

VDDQ_D1
VDDQ_D3

VDDQ_E5

VDDQ_F1
VDDQ_F3

VDDQ_H3

VDDQ_K3

VDDQ_L2

VDDQ_N5

VDDQ_P1
VDDQ_P3

VDDQ_T1
VDDQ_T3

VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14

VDD_L11
VDD_L14
VDD_P11

VDD_R10

VSSQ_A1
VSSQ_A3

VSSQ_C1
VSSQ_C3
VSSQ_C4

VSSQ_E1
VSSQ_E3

VSSQ_F5

VSSQ_H2

VSSQ_K2

VSSQ_N1
VSSQ_N3

VSSQ_R1
VSSQ_R3
VSSQ_R4

VSSQ_V1
VSSQ_V3

VSS_B10
VSS_D10
VSS_G5
VSS_G10

VSS_H14

VSS_K14

VSS_L10
VSS_P10

VSS_T10

+MVDD

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

+MVDD

C5

VDD_C5

C10
D11
G1
G4
G11
G14
L1

VDD_L1

L4

VDD_L4

L11
L14
P11
R5

VDD_R5

R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5

VSS_B5

B10
D10
G5
G10
H1

VSS_H1

H14
K1

VSS_K1

K14
L5

VSS_L5

L10
P10
T5

VSS_T5

T10

+MVDD

R2701
R2700

+MVDD

R2705

+MVDD

R2706
C2701

R2707

+MVDD

R2708
C2703

R2709

+MVDD

R2710
C2705

4

IN

4

IN

4

IN

4

IN

4

OUT

4

OUT

4

OUT

4

OUT

4

BI

4

BI

4

BI

4

BI

4

IN

4

IN

60.4R

1%

60.4R

1%

4

IN

4

IN

4

IN

4

IN

4

IN

R2702

R27031K5%

4,6

IN

R27041K5%

2.37K

5.49K

1uF

2.37K

5.49K

1uF

2.37K

5.49K

1uF

4

IN

DQD1_<5>
DQD1_<6>
DQD1_<7>
DQD1_<4>
DQD1_<3>
DQD1_<1>
DQD1_<2>
DQD1_<0>
DQD1_<10>
DQD1_<9>
DQD1_<11>
DQD1_<8>
DQD1_<12>
DQD1_<13>
DQD1_<14>
DQD1_<15>
DQD1_<24>
DQD1_<25>
DQD1_<27>
DQD1_<26>
DQD1_<30>
DQD1_<29>
DQD1_<31>
DQD1_<28>
DQD1_<17>
DQD1_<16>
DQD1_<18>
DQD1_<19>
DQD1_<21>
DQD1_<22>
DQD1_<20>
DQD1_<23>

MAD1_<8>
MAD1_<0>
MAD1_<1>
MAD1_<3>
MAD1_<2>
MAD1_<5>
MAD1_<4>
MAD1_<6>
MAD1_<7>

WCKD1_1
WCKD1B_1

WCKD1_0
WCKD1B_0

EDCD1_0
EDCD1_1
EDCD1_3
EDCD1_2

DDBID1_0
DDBID1_1
DDBID1_3
DDBID1_2

CASD1B
RASD1B

CLKD1B
CLKD1

WED1B
CSD1B_0

120R

1%

1%
1%

6.3V

1%
1%

6.3V

1%
1%

6.3V

23CNOPN001

U2700

M2

DQ31__DQ7

M4

DQ30__DQ6

N2

DQ29__DQ5

N4

DQ28__DQ4

T2

DQ27__DQ3

T4

DQ26__DQ2

V2

DQ25__DQ1

V4

DQ24__DQ0

M13

DQ23__DQ15

M11

DQ22__DQ14

N13

DQ21__DQ13

N11

DQ20__DQ12

T13

DQ19__DQ11

T11

DQ18__DQ10

V13

DQ17__DQ9

V11

DQ16__DQ8

F13

DQ15__DQ23

F11

DQ14__DQ22

E13

DQ13__DQ21

E11

DQ12__DQ20

B13

DQ11__DQ19

B11

DQ10__DQ18

A13

DQ9__DQ17

A11

DQ8__DQ16

F2

DQ7__DQ31

F4

DQ6__DQ30

E2

DQ5__DQ29

E4

DQ4__DQ28

B2

DQ3__DQ27

B4

DQ2__DQ26

A2

DQ1__DQ25

A4

DQ0__DQ24

J5

RFU_A12_NC

K4

A7_A8__A0_A10

K5

A6_A11__A1_A9

K10

A5_BA1__A3_BA3

K11

A4_BA2__A2_BA0

H10

A3_BA3__A5_BA1

H11

A2_BA0__A4_BA2

H5

A1_A9__A6_A11

H4

A0_A10__A7_A8

D4

WCK01__WCK23

D5

WCK01#__WCK23#

P4

WCK23__WCK01

P5

WCK23#__WCK01#

R2

EDC3__EDC0

R13

EDC2__EDC1

C13

EDC1__EDC2

C2

EDC0__EDC3

P2

DBI3#__DBI0#

P13

DBI2#__DBI1#

D13

DBI1#__DBI2#

D2

DBI0#__DBI3#

G3

RAS#__CAS#

L3

CAS#__RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS#__WE#

L12

WE#__CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp_NC

V5

Vpp_NC1

A10

VREFD1

V10

VREFD2

J14

VREFC

J4

ABI#

VDDQ_B1

VDDQ_B3
VDDQ_B12
VDDQ_B14

VDDQ_D1

VDDQ_D3
VDDQ_D12
VDDQ_D14

VDDQ_E5
VDDQ_E10

VDDQ_F1

VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13

VDDQ_H3
VDDQ_H12

VDDQ_K3
VDDQ_K12

VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14

VDDQ_N5
VDDQ_N10

VDDQ_P1

VDDQ_P3
VDDQ_P12
VDDQ_P14

VDDQ_T1

VDDQ_T3
VDDQ_T12
VDDQ_T14

VDD_C10

VDD_D11

VDD_G11

VDD_G14

VDD_P11

VDD_R10

VSSQ_A1

VSSQ_A3
VSSQ_A12
VSSQ_A14

VSSQ_C1

VSSQ_C3

VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14

VSSQ_E1

VSSQ_E3
VSSQ_E12
VSSQ_E14

VSSQ_F5
VSSQ_F10

VSSQ_H2
VSSQ_H13

VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10

VSSQ_N1

VSSQ_N3
VSSQ_N12
VSSQ_N14

VSSQ_R1

VSSQ_R3

VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14

VSSQ_V1

VSSQ_V3
VSSQ_V12
VSSQ_V14

+MVDD

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

+MVDD

C5

VDD_C5

C10
D11
G1

VDD_G1

G4

VDD_G4

G11
G14
L1

VDD_L1

L4

VDD_L4

L11

VDD_L11

L14

VDD_L14

P11
R5

VDD_R5

R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14

B5

VSS_B5

B10

VSS_B10

D10

VSS_D10

G5

VSS_G5

G10

VSS_G10

H1

VSS_H1

H14

VSS_H14

K1

VSS_K1

K14

VSS_K14

L5

VSS_L5

L10

VSS_L10

P10

VSS_P10

T5

VSS_T5

T10

VSS_T10

DQC0_<0>

6,

BI

DQC0_<1>

6,

BI

DQC0_<2>

6,

BI

DQC0_<3>

6,

BI

DQC0_<4>

6,

BI

DQC0_<5>

6,

BI

DQC0_<6>

6,

BI

DQC0_<7>

6,

BI

DQC0_<8>

6,

BI

DQC0_<9>

6,

BI

DQC0_<10>

6,

BI

DQC0_<11>

6,

BI

DQC0_<12>

6,

BI

DQC0_<13>

6,

BI

DQC0_<14>

6,

BI

DQC0_<15>

6,

BI

DQC0_<16>

6,

BI

DQC0_<17>

6,

BI

DQC0_<18>

6,

BI

D D

DQC0_<19>

6,

BI

DQC0_<20>

6,

BI

DQC0_<21>

6,

BI

DQC0_<22>

6,

BI

DQC0_<23>

6,

BI

DQC0_<24>

6,

BI

DQC0_<25>

6,

BI

DQC0_<26>

6,

BI

DQC0_<27>

6,

BI

DQC0_<28>

6,

BI

DQC0_<29>

6,

BI

DQC0_<30>

6,

BI

DQC0_<31>

6,

BI

1

MAC0_<0>

6,

OUT

MAC0_<1>

6,

OUT

MAC0_<2>

6,

OUT

MAC0_<3>

6,

OUT

MAC0_<4>

6,

OUT

MAC0_<5>

6,

OUT

MAC0_<6>

6,

OUT

MAC0_<7>

6,

OUT

MAC0_<8>

6,

OUT

DQC1_<0>
DQC1_<1>
DQC1_<2>
DQC1_<3>
DQC1_<4>
DQC1_<5>
DQC1_<6>
DQC1_<7>
DQC1_<8>
DQC1_<9>
DQC1_<10>
DQC1_<11>
DQC1_<12>
DQC1_<13>
DQC1_<14>
DQC1_<15>
DQC1_<16>
DQC1_<17>
DQC1_<18>
DQC1_<19>
DQC1_<20>
DQC1_<21>
DQC1_<22>
DQC1_<23>
DQC1_<24>
DQC1_<25>
DQC1_<26>
DQC1_<27>
DQC1_<28>
DQC1_<29>
DQC1_<30>
DQC1_<31>

2

MAC1_<0>

6,

BI

MAC1_<1>

6,

BI

MAC1_<2>

6,

BI

MAC1_<3>

6,

BI

MAC1_<4>

6,

BI

MAC1_<5>

6,

BI

MAC1_<6>

6,

BI

MAC1_<7>

6,

BI

MAC1_<8>

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

3

DQD0_<0>

6,

BI

DQD0_<1>

6,

BI

DQD0_<2>

6,

BI

DQD0_<3>

6,

BI

DQD0_<4>

6,

BI

DQD0_<5>

6,

BI

DQD0_<6>

6,

BI

DQD0_<7>

6,

BI

DQD0_<8>

6,

BI

DQD0_<9>

6,

BI

DQD0_<10>

6,

BI

DQD0_<11>

6,

BI

DQD0_<12>

6,

BI

DQD0_<13>

6,

BI

DQD0_<14>

6,

BI

DQD0_<15>

6,

BI

DQD0_<16>

6,

BI

DQD0_<17>

6,

BI

DQD0_<18>

6,

BI

DQD0_<19>

6,

BI

DQD0_<20>

6,

BI

DQD0_<21>

6,

BI

DQD0_<22>

6,

BI

DQD0_<23>

6,

BI

DQD0_<24>

6,

BI

DQD0_<25>

6,

BI

DQD0_<26>

6,

BI

DQD0_<27>

6,

BI

DQD0_<28>

6,

BI

DQD0_<29>

6,

BI

DQD0_<30>

6,

BI

DQD0_<31>

6,

BI

4

MAD0_<0>

6,

OUT

MAD0_<1>

6,

OUT

MAD0_<2>

6,

OUT

MAD0_<3>

6,

OUT

MAD0_<4>

6,

OUT

MAD0_<5>

6,

OUT

MAD0_<6>

6,

OUT

MAD0_<7>

6,

OUT

MAD0_<8>

6,

OUT

DQD1_<0>
DQD1_<1>
DQD1_<2>
DQD1_<3>
DQD1_<4>
DQD1_<5>
DQD1_<6>
DQD1_<7>
DQD1_<8>
DQD1_<9>
DQD1_<10>
DQD1_<11>
DQD1_<12>
DQD1_<13>
DQD1_<14>
DQD1_<15>
DQD1_<16>
DQD1_<17>
DQD1_<18>
DQD1_<19>
DQD1_<20>
DQD1_<21>
DQD1_<22>
DQD1_<23>
DQD1_<24>
DQD1_<25>
DQD1_<26>
DQD1_<27>
DQD1_<28>
DQD1_<29>
DQD1_<30>
DQD1_<31>

5

MAD1_<0>

6,

BI

MAD1_<1>

6,

BI

MAD1_<2>

6,

BI

MAD1_<3>

6,

BI

MAD1_<4>

6,

BI

MAD1_<5>

6,

BI

MAD1_<6>

6,

BI

MAD1_<7>

6,

BI

MAD1_<8>

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

BI

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

6,

OUT

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev
Custom

Custom

Custom
Date:

Date:

6

7

Date:

06 GDDR5 MEM CH CD

06 GDDR5 MEM CH CD

06 GDDR5 MEM CH CD

Friday, August 16, 2013

Friday, August 16, 2013

Friday, August 16, 2013

MS-V305

Sheet of

Sheet of

Sheet of

8

623

623

623

10

10

10

1

2

3

4

5

6

7

8

(7) CURACAO GPIO STRAP CF XTAL

+1.8V

R5000

4.99K
1%

+1.8V

SCL/SDA BUS:

I2C ADDRESS

PS_0

C5000

R5001

0.082uF

4.99K
16V

1%

R5004

4.99K

1%

PS_2

R5005

C5002

4.99K

0.082uF

1%

16V

A A

B B

DDCVGA BUS:

I2C ADDRESS

0x98

+1.8V

C29

10uF

6.3V

TP04
TP03

TP62

C C

TP65

+1.8V

R50

C50

D D

PAY ATTENTION TO THE GROUNDING
STRATEGIES FOR THESE FILTER CAPACITORS TO
MAINTAIN A CLOSE LOOP FOR CURRENT.

1

+1.8V

R5002

4.99K
1%

PS_1

R5003

C5001

4.99K

0.082uF

1%

16V

+1.8V

R5006

4.99K
1%

PS_3

R5007

C5003

4.99K

0.082uF

1%

16V

FUNCTION

FUNCTION

EXT TEMP SENSOR

221R
110R

0.1uF

+1.8V

+0.95V

+0.95V

+1.8V

DEVICE

DEVICE

LM96163

C5

C6

C7

4.7uF

1uF

1uF

6.3V

6.3V

6.3V

SWAPLOCKA
SWAPLOCKB

GENLK_CLK GENLK_CLK
GENLK_VSYNC

DVOCLK

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DVP_MVP_CNTL_1 GENERICD

1%
1%R51

6.3V

1 2

B1

120R

1 2

B4

120R

+1.8V

1 2

B5

120R

1 2

B6

120R

12

B7

220R

BF23
BF25
BG23
BG25

BC42
BE43

BG38
BG39

BD19
BD26

BE28
BE19

BE29
BF29

BG36

R4079

10K
5%

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#4

SWAPLOCKA
SWAPLOCKB

GENLK_CLK
GENLK_VSYNC

DVPCLK

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DVPCNTL_MVP_0
DVPCNTL_MVP_1

VREFG

C24

10uF

6.3V

C34

4.7uF

6.3V

+3.3V_BUS

+3.3V_BUS

R4080

10K
5%

R1832

27K
5%

+1.8V

U1F

PART 8 OF 18

D
V
P

PITCAIRN

+DPLL_PVDD

C14

C13

1uF

10uF

6.3V

6.3V

DNI

+DPLL_VDDC

C31

C16

4.7uF

1uF

6.3V

6.3V

DNI

+SPLL_PVDD

C18

C19

10uF

1uF

6.3V

6.3V

+SPLL_VDDC

C21

1uF

6.3V

+MPLL_PVDD

C35

C26

4.7uF

1uF

6.3V

6.3V

2

1

21

DVPDATA_10
DVPDATA_11

DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

DNI

1

21

1K
1K

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9

C15

0.1uF

6.3V

DNI

C17

0.1uF

6.3V

C20

0.1uF

6.3V

C22

0.1uF

6.3V

C27

0.1uF

6.3V

BI
OUT

OUT
BI

5%R98
5%R33

+3.3V_BUS

C1

1uF

6.3V

+1.8V

C30

1uF

6.3V

PS_0
PS_1
PS_2
PS_3

GPIO_3_SMBDATA
GPIO_4_SMBCLK

SCL
SDA

DDCVGACLK
DDCVGADATA

CEC_1

DNI

TEST_PWRGOOD

DVPDATA_0

BC21

DVPDATA_1

BE21

DVPDATA_2

BD21

DVPDATA_3

BE22

DVPDATA_4

BD22

DVPDATA_5

BC22

DVPDATA_6

BE23

DVPDATA_7

BD23

DVPDATA_8

BD25

DVPDATA_9

BC25

DVPDATA_10

BG26

DVPDATA_11

BE26
BE31

BD31
BG32
BE32
BD32
BE33

DVPDATA_18

BD33
BE35
BD35
BE36
BD36
BC36

PLACE THE CROSSFIRE TEST POINTS
NEAR THE ASIC AND NOT THE CONNECTOR

BM39

DPLL_PVDD

BK39

DPLL_PVSS

BJ40

DPLL_VDDC

BC29

SPLL_PVDD

BC28

SPLL_PVSS

BC26

SPLL_VDDC

H8

MPLL_PVDD#1

J9

MPLL_PVDD#2

L11

MPLL_PVDD#3

BB38

BB40
BC38
BC39

BB35

BB36

BB37
BC35

BD42

BE42

BF42
BG42

AY42

AV42

U50
U52

AY44

AV47

AV48

AV49
BH16
BH17
BH43

BJ16

U48

AW44

BG43

PART 9 OF 18

PITCAIRN

VDDR3
VDDR3
VDDR3
VDDR3

VDD_CT
VDD_CT
VDD_CT
VDD_CT

PS_0
PS_1
PS_2
PS_3

SMB_DAT
SMB_CLK

V47

SCL

V46

SDA

DDCVGACLK
DDCVGADATA

CEC_1

TEST_PG

NC
NC
NC
NC
NC
NC

T48

NC

T49

NC
NC

V51

NC
NC
NC

TP60

TP61

U1G

P
L
L
S

X
T
A
L

3

U1H

PART 7 OF 18

GPIO_17_THERMAL_INT

G
P
I
O

PITCAIRN

CROSSFIRE

LOWER CABLE CARD EDGE

DVOCLK

CLK_1

DVPCNTL_2

DE_1

DVPDATA_1

DVPDATA_3

DVPDATA_5

DVPDATA_7

DVPDATA_9

DVPDATA_11

DVPCNTL_1

RSVD

FLOW_CONTROL_1

XO_IN2

BM41

XO_IN2

XO_IN

BK41

XO_IN

BN40

XTALIN

BL40

XTALOUT

+XTAL_VDDR

BF40

XTAL_VDDR

BG40

XTAL_VSS

CLKTESTA CLKTESTA_C

BM17

CLKTESTA

CLKTESTB CLKTESTB_C

BK17

CLKTESTB

V49

GPIO_0

BF39

GPIO_1

BD28

GPIO_2

GPIO5REGHOT

BD39

GPIO_5_REG_HOT

V48

GPIO_6_TACH

BD40

GPIO_7_BLON

BE46

GPIO_8_ROMSO

BF46

GPIO_9_ROMSI

BG46

GPIO_10_ROMSCK

AA44

GPIO_11

BA50

GPIO_12

BA52

GPIO_13

AV45

GPIO_14_HPD2

W44

GPIO_15_PWRCNTL_0

V45

GPIO_16_8P_DETECT

AA45
AV44

GPIO_18_HPD3

W43

GPIO_19_CTF

W45

GPIO_20_PWRCNTL_1

BF38

GPIO_21

BE47

GPIO_22_ROMCSB

BF43

GPIO_29

BE40

GPIO_30

BH41

GENERICA

BE38

GENERICB

BE39

GENERICC

BG29

GENERICD

BC31

GENERICE_HPD4

BC32

GENERICF_HPD5

BA48

GENERICG_HPD6

BE45

HPD1

AA43

CLKREQB

AA47

TS_A

AM19

RSVD#1

AR19

RSVD#2

AN18

RSVD#3

AM18

RSVD#4

AN19

RSVD#5

AR18

RSVD#6

AV53

RSVD#7_DIGON

AV51

RSVD#8_VARYBL

614NOPN128

1 2
3 4
5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

J2

33R

5%R22

5%

33R

R26

C5100

4.7uF

6.3V

0.1uF

C23

0.1uF

ROUTE 50OHMS SINGLE ENDED OR 100OHMS DIFFERENTIAL
KEEP THEM SHORT

GPIO_0_PWRCNTL_4
GPIO_1
GPIO_2

GPIO_6_TACH

GPIO_8_ROMSO
GPIO_9_ROMSI

GPIO_11_PWRCNTL_3
GPIO_12_VDDC_VID4
GPIO_13_VDDC_VID5

GPIO_14_VDDC_VID3

GPIO_15_VDDC_VID1

GPIO_17_THERM_INT

GPIO_19_CTF
GPIO_20_VDDC_VID2

GPIO_22_ROMCSB

GPIO_29_VDDC_VID6
GPIO_30_VDDC_VID7

GENERICD
HPD4
HPD5
HPD6

HPD1

CLKREQB

6.3V

6.3VC28

4

DVPDATA_0

DVPDATA_2

DVPDATA_4

DVPDATA_6

DVPDATA_8

DVPDATA_10

DVPCNTL_0

GPIO_2

SWAP_LOCK_1

+3.3V_BUS

19,,

OUT

IN

OUT
OUT
OUT
OUT
OUT

IN

OUT
OUT

OUT
OUT

IN
IN
IN

IN

18pF

C11

50V

1 2

B5000

120R

R24
R25

R81

10K
5%

20,21

19,
19,
19,
19
19

21

20
19

19
19

10
10
11

9,10

R35

XOUT_OSC

CLK_100M

CLK_27M

33R

1 8

RP1A

33R

2 7

RP1B

33R

3 6

RP1C

33R

4 5

RP1D

+3.3V_BUS

R80

10K
5%

KEEP XIN_OSC AND XOUT_OSC
AS SHORT AS POSSIBLE TO
MINIMIZE STRAY CAPACITANCE

XOUT_OSC

UNNAMED_7_RES_I407_B UNNAMED_7_RES_I408_A

5%

0R

10

XTALOUT

5

100M_OUT

9

27M_OUT

XIN_OSC

XOUT_OSC

+1.8V

1%

51.1R
1%

51.1R

VIDEO BIOS

FIRMWARE

+3.3V_BUS +3.3V_BUS

U11

10K

DNI

10K

DNI

10K

DNI

10K

DNI

10K

DNI

DNI

DNI

VDD33_100M

VDD33_27MVREFG

SS_SEL0
SS_SEL1

+3.3V_BUS

5%

5%MR6

5%

5%MR8

5%MR15

3
2
5
6
1

R1

R2

R7

R8

R10

R11

R13

R15

R16

R17

C9

0.1uF

6.3V

6

GPIO_8_R
GPIO_9_R
GPIO_10_RGPIO_10_ROMSCK
GPIO_22_R

+3.3V_BUS

R14

2.2K
5%

MR1

MR7

1M

1%R37

Y1

XIN_OSC

123

4

27.000MHz

SL16020DC

U12

R36

1

XTALIN

4

VDD_100M

8

VDD_27M

7

SS_SEL0

3

SS_SEL1

6

GND_100M

2

GND_27M

11

GND_PAD

C12

5%

0R

18pF

50V

5

WP
SO
SI

SCK

CE

PM25LV010A-100SC

5%

10K

5%

10K

10K

5%R3

DNI

10K

5%R5

DNI

10K

5%R6

5%

10K

DNI

5%

10K

5%

10K

DNI

5%

10K

DNI

5%

10K

DNI

5%

10K

DNI

5%

10K

5%

10K

DNI

C10

0.1uF

6.3V

VDD

HOLD

GND

GPIO_0_PWRCNTL_4

GPIO_0_PWRCNTL_4

GPIO_1

GPIO_2

GPIO_2

GPIO_9_R

GPIO_13_VDDC_VID5

GPIO_13_VDDC_VID5

GPIO_12_VDDC_VID4

GPIO_12_VDDC_VID4

GPIO_11_PWRCNTL_3

GPIO_11_PWRCNTL_3

VSYNC

HSYNC

GPIO_8_R

GPIO_8_R

GPIO_28_TS_FDO

GENLK_VSYNC

B2

120R

B3

120R

8
7

C4

0.1uF

6.3V

4

PIN BASED STRAPS

+3.3V_BUS

12
12

+3.3V_BUS

R20

5.1K
5%

R28

5.1K
5%

GPIO(0) - TX_CFG_DRV_FULL_SWING (TRANSMITTER POWER SAVING ENABLE)
0: 50% TX OUTPUT SWING
1: FULL TX OUTPUT SWING (DEFAULT SETTING FOR DESKTOP)

GPIO(1) - TX_DEEMPH_EN (TRANSMITTER DE-EMPHASIS ENABLE)
0: TX DE-EMPHASIS DISABLED
1: TX DE-EMPHASIS ENABLED (DEFAULT SETTING FOR DESKTOP)

GPIO(2) - BIF_GEN3_EN_A
0 : DRIVER CONTROLLED GEN3
1 : STRAP CONTROLLED GEN3

GPIO(9) - BIF_VGA_DIS
0 : VGA CONTROLLER CAPACITIY ENABLED (NORMAL OPERATION)
1 : THE DEVICE WILL NOT BE RECOGNIZED AS THE SYSTEM'S VGA CONTROLLER

GPIO(13,12,11) - CONFIG[2..0]
CONFIG[2]

CONFIG[1]

CONFIG[0]

HSYNC = AUD[1], VSYNC = AUD[0]
AUD[0]

8

OUT

AUD[1]

8

OUT

HDMI MUST ONLY BE ENABLED ON SYSTMES THAT ARE LEGALLY
ENTITLED. IT IS THE RESPONSIBILITY OF THE SYSTEM DESIGNER
TO SUPPORT THIS FEATURE.

GPIO(8) - BIF_CLK_PM_EN
0 - DISABLE CLKREQb POWER MANAGEMENT CAPABILITY
1 - ENABLE CLKREQb POWER MANAGEMENT CAPABILITY
ENSURE THAT NO LOGIC CONFLICTS WITH THIS SIGNAL DURING RESET.

GPIO(28) - MLPS_DIS
0 - ENABLE MLPS

20,

OUT

1 - DISALBE MLPS

GENLK_VSYNK - CEC_DIS

GENLK_CLK - SMS_EN_HARD

R21

5.1K
5%

DNIDNI

R29

5.1K
5%

100 - 512KBIT (ST) M25P05A
101 - 1MBIT (ST) M25P10A
101 - 2MBIT (ST) M25P20
101 - 4MBIT (ST) M25P40
101 - 8MBIT (ST) M25P80
100 - 512KBIT (CHINGIS) PM25LV512
101 - 1MBIT (CHINGIS) PM25LV010

00 - NO AUDIO FUNCTION
01 - AUDIO FOR DP ONLY
10 - AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED
11 - AUDIO FOR BOTH DP AND HDMI

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Date:

Date:

7

Date:

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MS-V305

Custom

Custom

Custom

07 CURACAO GPIO STRAP CF XTAL

07 CURACAO GPIO STRAP CF XTAL

07 CURACAO GPIO STRAP CF XTAL

Friday, August 16, 2013

Friday, August 16, 2013

Friday, August 16, 2013

Sheet of

Sheet of

Sheet of

8

10

10

10

723

723

723

1

2

3

4

5

6

7

8

(8) CURACAO DAC1 LOCK

A A

R1501

150R
1%

R1504

150R
1%

R1509

150R
1%

SEE BOM FOR QUALIFIED FILTERS

1 2

L1503

1 2

L1504

1 2

L1505

0.047uH

C1504

8pF
50V

0.047uH

C1506

8pF
50V

0.047uH

C1509

8pF
50V

1 2

L1500

1 2

L1501

1 2

L1502

0.047uH

C1503

12pF
50V

0.047uH

C1505

12pF
50V

0.047uH

A_B_DAC_F

C1510

12pF
50V

A_R_DAC_F
A_G_DAC_F
A_B_DAC_F

HSYNC_DAC_R
VSYNC_DAC_R

11,

OUT

11,

OUT

11,

OUT

11,

OUT

11,

OUT

U1I

+1.8V

1 2

B1600

120R

+1.8V

1 2

B1601

120R

PAY ATTENTION TO THE GROUNDING
STRATEGIES FOR THESE FILTER CAPACITORS TO
MAINTAIN A CLOSE LOOP FOR CURRENT.

B B

+VDD1DI

+AVDD

R1500

AY45

C1500

C1501

1uF

0.1uF

6.3V

6.3V

AW45

BB45
BC45

C1507

C1508

1uF

0.1uF

6.3V

6.3V

BB44

RSET

499R

1%

BB43

PART 10 OF 18

VDD1DI

VSS1DI

AVDD
AVDD

AVSSQ

D
A
C

RSET

PITCAIRN

+5V_VESA

C1514

AY47

R

AY46

AVSSN

BB47

G

BB46

AVSSN

BC47

B

BC46

AVSSN

AW46

HSYNC

AW47

VSYNC

0.1uF

6.3V

R_DAC R_DAC_L

R1503

150R
1%

G_DAC G_DAC_L

R1508

150R
1%

B_DAC B_DAC_L

R1513

150R
1%

1

+5V_VESA

3 5

U1500B

74AHCT1G126GW

C1515

HSYNC HSYNC_DAC_B

7

OUT

0.1uF

6.3V

2 4

U1500A

74AHCT1G126GW

R1514

24R

5%

C1512

12pF
50V

DNI

1

VSYNC VSYNC_DAC_B

7

U1501B

74AHCT1G126GW

3 5

C C

OUT

2 4

U1501A

74AHCT1G126GW

R1515

24R

5%

C1513

12pF
50V

DNI

OPTIONAL ESD PROTECTION DIODES

D1500 ESD5V3U1U-02LRH

12

D1501 ESD5V3U1U-02LRH

12

D1502 ESD5V3U1U-02LRH

12

D1505 ESD8V0R1B-02LRH

12

D1506 ESD8V0R1B-02LRH

12

D D

1

2

A_R_DAC_F

A_G_DAC_F

A_B_DAC_F

HSYNC_DAC_R

VSYNC_DAC_R

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

3

4

5

6

7

Friday, August 16, 2013

MS-V305

08 CURACAO DAC

08 CURACAO DAC

08 CURACAO DAC

Sheet of

Sheet of

Sheet of

8

10

10

10

823

823

823

1

(9) CURACAO TMDP A/B

2

3

4

5

6

7

8

+1.8V

C1700

C1701

C1702

1uF

1uF

1uF

6.3V

6.3V

C1704

C1703

0.1uF

0.1uF

6.3V

6.3V

C1707

C1706

4.7uF

4.7uF

6.3V

6.3V

C1711

C1710

1uF

1uF

6.3V

6.3V

C1714

C1713

0.1uF

0.1uF

6.3V

6.3V

C1717

C1716

4.7uF

4.7uF

6.3V

6.3V

R1700 1%

150R

6.3V

C1705

0.1uF

6.3V

C1708

4.7uF

6.3V

A A

+0.95V

B B

PLEASE PAY ATTENTION TO THE GROUNDING
STRATEGIES FOR THESE FILTER CAPACITORS TO
MAINTAIN A CLOSE LOOP FOR CURRENT

C1738

1uF

6.3V

C1719

0.1uF

6.3V

C1709

4.7uF

6.3V

DPAB_CALR

BF33
BG33
BH32
BH33
BH34
BH35

BF22
BF45
BG22
BG45
BH20
BH21
BH42
BH44
BH45

BL18
BN18

BF28
BF31
BG28
BG31
BH26
BH27
BH28
BH29

BF47
BF48
BG47
BG48

BC50
BD48
BD53
BE48
BF35
BF53
BG21
BG35
BH24
BH25
BH30
BH31
BH36
BH37
BH46
BH47

BL38
BM19
BM43
BN20
BN22
BN24
BN26
BN28
BN30
BN32
BN34
BN36
BN38
BN44
BN46

DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR

NC_DP_VDDR
NC_DP_VDDR
NC_DP_VDDR
NC_DP_VDDR
NC_DP_VDDR
NC_DP_VDDR
NC_DP_VDDR
NC_DP_VDDR
NC_DP_VDDR

BJ42

NC_DP_VDDR
NC_DP_VDDR
NC_DP_VDDR

DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC

NC_DP_VDDC
NC_DP_VDDC
NC_DP_VDDC
NC_DP_VDDC

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

BJ18

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

BF36

DPAB_CALR

C C

D D

U1J

PART 11 OF 18

PITCAIRN

OPTIONAL ESD PROTECTION DIODES

D1700 ESD5V3U1U-02LRH

D1701 ESD5V3U1U-02LRH

D1702 ESD5V3U1U-02LRH

D1703 ESD5V3U1U-02LRH

D1704 ESD5V3U1U-02LRH

D1705 ESD5V3U1U-02LRH

D1706 ESD5V3U1U-02LRH

D1707 ESD5V3U1U-02LRH

D1708 ESD5V3U1U-02LRH

D1709 ESD5V3U1U-02LRH

D1710 ESD5V3U1U-02LRH

D1711 ESD5V3U1U-02LRH

D1712 ESD5V3U1U-02LRH

D1713 ESD5V3U1U-02LRH

D1714 ESD5V3U1U-02LRH

D1715

TX2P_DPA0P

TX2M_DPA0N

TX1P_DPA1P

TX1M_DPA1N

TX0P_DPA2P

TX0M_DPA2N

TXCAP_DPA3P

TXCAM_DPA3N

DDCCLK_AUX3P

DDCDATA_AUX3N

T
M
D
P

A
/
B

TX5P_DPB0P

TX5M_DPB0N

TX4P_DPB1P

TX4M_DPB1N

TX3P_DPB2P

TX3M_DPB2N

TXCBP_DPB3P

TXCBM_DPB3N

DDCCLK_AUX5P

DDCDATA_AUX5N

12
12
12
12
12
12
12
12
12
12
12
12
12
12

12

ESD5V3U1U-02LRH

12

BM33
BL32
BJ32
BK31
BM31
BL30
BJ30
BK29

BM29
BL28

BJ38
BK37
BM37
BL36
BJ36
BK35
BM35
BL34

BJ44
BK43

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

ABTX2P

ABTX2N

ABTX1P

ABTX1N

ABTX0P

ABTX0N

ABTXCP

ABTXCN

ABTX5P

ABTX5N

ABTX4P

ABTX4N

ABTX3P

ABTX3N

DDC5CLK_DVI

DDC5DAT_DVI

DPA_TX2P

DPA_TX2N

DPA_TX1P

DPA_TX1N

DPA_TX0P

DPA_TX0N

DPA_TXCP

DPA_TXCN

DDC3CLK_HDMI

DDC3DAT_HDMI

DPB_TX5P

DPB_TX5N

DPB_TX4P

DPB_TX4N

DPB_TX3P

DPB_TX3N

UNNAMED_9_CAP_I264_B

C1720 6.3V

0.1uF

UNNAMED_9_CAP_I262_B

C1721 6.3V

0.1uF

UNNAMED_9_CAP_I263_B

C1722

0.1uF

6.3V

UNNAMED_9_CAP_I260_B

C1723

0.1uF

6.3V

UNNAMED_9_CAP_I261_B

C1724 6.3V

0.1uF

UNNAMED_9_CAP_I259_B

C1725

0.1uF

6.3V

UNNAMED_9_CAP_I258_B

C1726 6.3V

0.1uF

UNNAMED_9_CAP_I257_B

C1727

0.1uF

6.3V

10

OUT

10

BI

UNNAMED_9_CAP_I233_B

C1728

0.1uF

6.3V

UNNAMED_9_CAP_I234_B

C1729

0.1uF

6.3V

UNNAMED_9_CAP_I230_B

C1730 6.3V

0.1uF

UNNAMED_9_CAP_I228_B

C1731

0.1uF

6.3V

UNNAMED_9_CAP_I229_B

C1732 6.3V

0.1uF

UNNAMED_9_CAP_I227_B

C1733 6.3V

0.1uF

DDC5DAT_DVI

L1720

1 2

L1721

1 2

L1722

1 2

L1723

1 2

L1724

1 2

L1725

1 2

L1726

1 2

L1727

1 2

L1728

1 2

L1729

1 2

L1730

1 2

L1731

1 2

L1732

1 2

L1733

1 2

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

0.0082uH

ABTX2P

R1720

499R

1%

R1721 1%

499R

ABTX2N

R1722

499R

1%

R1723 1%

499R

ABTX1N

ABTX0P

R1724

499R

1%

R1725 1%

499R

ABTX0N

R1726

499R

1%

ABTXCP

R1727

499R

1%

R1728 1%

499R

ABTX5P

ABTX5N

R1729 1%

499R

R1730

499R

1%

ABTX4P

ABTX4N

R1731 1%

499R

R1732

499R

R1733 1%

DPAB_GND

MMBT3904

1%

499R

+3.3V_BUS

Q1701

UNNAMED_9_NPN_I242_B

R1703 5%

10K

1

R1704 5%

2 3

10K

ABTX3N

DVI_EN

11,10

IN

+5V_VESA

R1701

2.2K
5%

7

Q1700

1

SI2304DS

2 3

R1702

2.2K
5%

HPD1

OUT

ABTX2P

ABTX2N

ABTX1P

ABTX1N

ABTX0P

ABTX0N

ABTXCP

ABTXCN

ABTX5P

ABTX5N

ABTX4P

ABTX4N

ABTX3P

ABTX3N

DDC5CLK_DVI

DDC5DAT_DVI

HPD_AB_DVI

ABTX0N
ABTX0P
ABTX1N

ABTX1P

ABTX2N
ABTX2P

ABTX3N

ABTX3P

ABTX4N
ABTX4P
ABTX5N
ABTX5P
DDC5CLK_DVI
DDC5DAT_DVI

ABTXCN

ABTXCP

HPD_AB_DVI

SCREW1903

SCREW1904

+5V_VESA

C1740

1uF
16V

SHIELD1

1

SHIELD5

5

SHIELD7

7

TX0-

B17

TX0+

B18

TX1-

B9

TX1+

B10

TX2-

B1

TX2+

B2

SHLD24

B3

SHLD13

B11

SHLD05

B19

TX3-

B12

TX3+

B13

TX4-

B4

TX4+

B5

TX5-

B20

TX5+

B21

DDCC

B6

DDCD

B7

VDDC

B14

GND

B15

SHLDC

B22

TXC-

B24

TXC+

B23

GND

B8

HPD

B16

2/2 UPPER

17 9 1

16

24

STACKED DVI - TOP

J1900A

VVVV305

COMMON

TOWS_multi_con_dvi_1

8

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

MS-V305

09 CURACAO TMDPAB dDVI TOP

09 CURACAO TMDPAB dDVI TOP

09 CURACAO TMDPAB dDVI TOP

Sheet of

Sheet of

Sheet of

8

10

10

10

923

923

923

1

(10) CURACAO TMDP C/D

2

3

4

5

6

7

8

U1K

PART 12 OF 18

A A

T
M
D
P

C
/
D

B B

R1800

DPCD_CALR

150R

1%

BF18

DPCD_CALR

PITCAIRN

TX2P_DPC0P

TX2M_DPC0N

TX1P_DPC1P

TX1M_DPC1N

TX0P_DPC2P

TX0M_DPC2N

TXCCP_DPC3P

TXCCM_DPC3N

DDC1CLK

DDC1DATA

TX5P_DPD0P

TX5M_DPD0N

TX4P_DPD1P

TX4M_DPD1N

TX3P_DPD2P

TX3M_DPD2N

TXCDP_DPD3P

TXCDM_DPD3N

DDC2CLK

DDC2DATA

BM23
BL22
BJ22
BK21
BM21
BL20
BJ20
BK19

BH19

AUX1P

BH18

AUX1N

BG19
BG18

BJ28
BK27
BM27
BL26
BJ26
BK25
BM25
BL24

BJ24

AUX2P

BK23

AUX2N

BH23
BH22

DPC_C0P

DPC_C0N

DPC_C1P

DPC_C1N

DPC_C2P

DPC_C2N

DPC_C3P

DPC_C3N

AUX1P

AUX1N

DDC1CLK

DDC1DATA

DPD_TX2P

DPD_TX2N

DPD_TX1P

DPD_TX1N

DPD_TX0P

DPD_TX0N

DPD_TXCP

DPD_TXCN

2 3

1

2N7002E

Q1801

C1801 6.3V

0.1uF

C1802

0.1uF

C1805

0.1uF

C1806

0.1uF

C1807

0.1uF

C1808 6.3V

0.1uF

C1809

0.1uF

C1810

0.1uF

C1811

0.1uF

C1812

0.1uF

2 3

Q1802

2N7002E

1

C1829 6.3V

0.1uF

C1830

0.1uF

C1831 6.3V

0.1uF

C1832

0.1uF

C1833

0.1uF

C1834

0.1uF

C1835

0.1uF

C1836 6.3V

0.1uF

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

R1802

Q1800

MMBT3904

MMBT3904

2 3

499R

499R

499R

499R

499R

499R

499R

499R

+3.3V_BUS

Q1823

R1803

R1807

1

R1808 5%

R1801 5%

1%

1%

1%

1%

1%

1

2 3

N28404577

N62218298

R1829

R1828 5%

6.3V

6.3V

AUX1_BYPSS_EN

6.3V

6.3V

6.3V

6.3V

6.3V

+5V_VESA

R1830

R1831

2.2K

2.2K

5%

5%

DDC3DAT_HDMI

+12V_BUS +12V_BUS +3.3V_BUS

R1804

R1805

10K

10K

5%

MMBT3904

5%

N50484859

Q1803

2 3

1

Q1804

1

2 3

11,9

IN

2N7002E

HPD4

7

OUT

DTX2P

R1825 1%

DTX2N

R1824 1%

DTX1P

R1823

DTX1N

R1822

DTX0P

R1821

DTX0N

R1820

DTXCAP

R1819 1%

DTXCAN

R1818

DPD_GND

Q1820

DVI_EN

1

SI2304DS

2 3

HPD5

7

OUT

100K

100K

10K

10K

1M

DDC3CLK_HDMI

DDC3DAT_HDMI

DPC_0P

DPC_0N

DPC_1P

DPC_1N

DPC_2P

DPC_2N

DPC_3P

DPC_3N

AUX1P_DPC

5%

AUX1N_DPC

5%

+3.3V_BUS

HPD_DPC

5%

DPC_DONGLE_DET

R1806 5%

DTX2P

DTX2N

DTX1P

DTX1N

DTX0P

DTX0N

DTXCAP

DTXCAN

OUT

HPD_HDMI

10K

5%

10K

J1800

1

ML_Lane_0p

ML_Lane_0n

ML_Lane_1p

ML_Lane_1n

ML_Lane_2p

ML_Lane_2n

ML_Lane_3p

ML_Lane_3n

AUX_CHp

AUX_CHn

Hot_Det

CONFIG 1

CONFIG 2

DP_W/GASKET

DP_PWR

PWR_RTN

GND_2

MEC1

GND_0
GND_1

GND_3
GND_6

3
4
6
7

9
10
12
15
17

18

13

5.1M

14

DISPLAYPORT_PIN14

10

10

BI

+3.3V_DP

20

C1817

C1840

22uF

100uF

6.3V

6.3V

MEC1

19
X1

X1

X2

X2

X3

X3

X4

X4

2
5
8
11
16

+3.3V_BUS

F1800

12

1.5A

C C

OPTIONAL ESD PROTECTION DIODES

D1800

D6Y4

DPC_0P DPC_0P

5

C

4

GND

3

B

2

A

1

D6Y4

5

C

4

GND

3

B

2

A

1

RCLAMP0524P

D1802

RCLAMP0524P

Y3

7

GND1

8

Y2

9

Y1

10

Y3

7

GND1

8

Y2

9

Y1

10

D1809 ESD5V3U1U-02LRH

D1808 ESD5V3U1U-02LRH

D1805 ESD5V3U1U-02LRH

DPC_0N DPC_0N

DPC_1P DPC_1P
DPC_1N DPC_1N

DPC_2P DPC_2P
DPC_2N DPC_2N

DPC_3P DPC_3P
DPC_3N DPC_3N

D D

1

DTX2P DTX2P
DTX2N DTX2N

DTX1P DTX1P
DTX1N DTX1N

DTXCAN DTXCAN
DTXCAP DTXCAP

DTX0N DTX0N
DTX0P DTX0P

12
12

12

2

AUX1N_DPC

AUX1P_DPC

DPC_DONGLE_DET

D6Y4

5

C

4

GND

3

B

2

A

1

D6Y4

5

C

4

GND

3

B

2

A

1

D1850

Y3

GND1

Y2
Y1

D1851

Y3

GND1

Y2
Y1

RCLAMP0524P DNI

7
8
9
10

DNIRCLAMP0524P

7
8
9
10

D1852 ESD5V3U1U-02LRH

12

D1853

ESD5V3U1U-02LRH

12

3

DNI

DNI

DDC3CLK_HDMI

DDC3DAT_HDMI

4

5

6

7

HPD_HDMI

DDC3DAT_HDMI
DDC3CLK_HDMI

DTXCAN
DTXCAP

DTX0N

DTX0P

DTX1N

DTX1P

DTX2N

DTX2P

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

10 CURACAO TMDPCD DP HDMI

10 CURACAO TMDPCD DP HDMI

10 CURACAO TMDPCD DP HDMI

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

+5V_VESA

C1737

1uF

6.3V

J2501

19

HP_DET

18

+5V

17

GND

SHELL1

16

SDA

15

SCL

SHELL2

14

NC

13
12

11
10

MEC1

CE Remote
CK-

CK_Shield
CK+

9

D0-

8

D0_Shield

7

D0+

MEC2

6

D1-

5

D1_Shield

SHELL3

4

D1+

SHELL4

3

D2-

2

D2_Shield

1

D2+

HDMI19PSM_BLACK-RH-5

VVVV305

N5Y-19M0760-W06

MS-V305ci20313

MS-V305

MS-V305

Sheet of

Sheet of

Sheet of

8

X1
X2
MEC1

MEC2
X3
X4

10 23

10 23

10 23

10

10

10

1

2

3

4

5

6

7

8

(11) CURACAO LVTMDP E/F

U1L

PART 13 OF 18

BL49

RSVD_L3P

A A

L
V
T
M
D
P

E
/
F

B B

R1900 1%

DPEF_CALR

150R

BC48

DPEF_CALR

PITCAIRN

OPTIONAL ESD PROTECTION DIODES

DDC6DATA_DVI

DDC6CLK_DVI

EFTX2P

EFTX2M

EFTX1P

EFTX1M

EFTX0P

EFTX0M

EFTXCP

EFTXCM

EFTX5P

EFTX5M

EFTX4P

EFTX4M

EFTX3P

EFTX3M

D1900 ESD5V3U1U-02LRH

12

D1901 ESD5V3U1U-02LRH

12

D1902 ESD5V3U1U-02LRH

12

D1903 ESD5V3U1U-02LRH

C C

12

D1904 ESD5V3U1U-02LRH

12

D1905 ESD5V3U1U-02LRH

12

D1906 ESD5V3U1U-02LRH

12

D1907 ESD5V3U1U-02LRH

12

D1908 ESD5V3U1U-02LRH

12

D1909 ESD5V3U1U-02LRH

12

D1910 ESD5V3U1U-02LRH

12

D1911 ESD5V3U1U-02LRH

12

D1912 ESD5V3U1U-02LRH

12

D1913 ESD5V3U1U-02LRH

12

ESD8V0R1B-02LRH

D1503

12

ESD8V0R1B-02LRH

D1504

12

D D

RSVD_L3N

L2P_TX2P_DPE0P

L2N_TX2M_DPE0N

L1P_TX1P_DPE1P

L1N_TX1M_DPE1N

L0P_TX0P_DPE2P

L0N_TX0M_DPE2N

LP_TXCEP_DPE3P

LN_TXCEM_DPE3N

DDCCLK_AUX4P

DDCDATA_AUX4N

RSVD_U3P

RSVD_U3N

U2P_TX5P_DPF0P

U2N_TX5M_DPF0N

U1P_TX4P_DPF1P

U1N_TX4M_DPF1N

U0P_TX3P_DPF2P

U0N_TX3M_DPF2N

UP_TXCFP_DPF3P

UN_TXCFM_DPF3N

DDCCLK_AUX6P

DDCCLK_AUX6N

BN48
BJ48
BK47
BM47
BL46
BJ46
BK45
BM45
BL44

BJ34
BK33

BC52
BD51
BD49
BE50
BE52
BF51
BF49
BG50
BG52
BH53

BH49
BJ51

DPE_TX2P

DPE_TX2N

DPE_TX1P

DPE_TX1N

DPE_TX0P

DPE_TX0N

DPE_TXCAP

DPE_TXCAN

DPF_TX5P

DPF_TX5N

DPF_TX4P

DPF_TX4N

DPF_TX3P

DPF_TX3N

DDC6CLK_DVI

DDC6DATA_DVI

+5V_VESA

SINGLE DVI OPTION

C1904 6.3V

0.1uF

C1905 6.3V

0.1uF

C1906 6.3V

0.1uF

C1907 6.3V

0.1uF

C1908 6.3V

0.1uF

C1909 6.3V

0.1uF

C1910 6.3V

0.1uF

C1911

0.1uF

C1920 6.3V

0.1uF

C1921

0.1uF

C1922 6.3V

0.1uF

C1923 6.3V

0.1uF

EFTX4M

C1924 6.3V

0.1uF

C1925 6.3V

0.1uF

EFTX2M
EFTX2P

EFTX4M
EFTX4P
DDC6CLK_DVI
DDC6DATA_DVI
VSYNC_DAC_R
EFTX1M
EFTX1P

EFTX3M
EFTX3P
+5V_VESA

EFTX0M
EFTX0P

EFTX5M
EFTX5P

EFTXCP
EFTXCM

A_R_DAC_F
A_G_DAC_F
A_B_DAC_F

HSYNC_DAC_R

6.3V

6.3V

+5V_VESA

R1505

2.2K
5%

25

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C1
C2
C3
C4
C5
C6

26

R1506

2.2K
5%

CASE

TMDS_Data2­TMDS_Data2+
TMDS_Data2/4_Shield
TMDS_Data4­TMDS_Data4+
DDC_Clock
DDC_Data
Analog_VSYNC
TMDS_Data1­TMDS_Data1+
TMDS_Data1/3_Shield
TMDS_Data3­TMDS_Data3+
+5V_Power
GND_(for_+5V)
Hot_Plug_Detect
TMDS_Data0­TMDS_Data0+
TMDS_Data0/5_Shield
TMDS_Data5­TMDS_Data5+
TMDS_Clock_Shield
TMDS_Clock+
TMDS_Clock-

Analog_Red
Analog_Green
Analog_Blue
Analog_HYNC
Analog_GND
Analog_GND#C6

CASE#M2

EFTX5P

EFTX5M

MJ1900

DVI-I_BLACK

CASE#M3
CASE#M4
CASE#M5
CASE#M6

EFTX2P

R1901 1%

499R

R1903 1%

499R

EFTX2M

R1902 1%

499R

R1905

499R

1%

EFTX1M

EFTX0P

R1904 1%

499R

R1907 1%

499R

EFTX0M

R1906

499R

1%

EFTXCP

R1908 1%

499R

R1909 1%

499R

R1911 1%

499R

R1910

499R

1%

EFTX4P

R1913

499R

R1912 1%

1

C1917

0.1uF
16V

7

OUT

R1914 1%

Q1900

SI2304DS

2 3

+12V_BUS

R1917

100K
5%

DVI_EN

9,10

OUT

EFTX3M

27
28
29
30

1%

499R

499R

DPEF_GND

+3.3V_BUS +5V_VESA

Q1901

UNNAMED_11_NPN_I96_B

R1915

1

MMBT3904

HPD6HPD_EF_DVI

R1916

2 3

EFTX2P

EFTX2M

EFTX1P

EFTX1M

EFTX0P

EFTX0M

EFTXCP

EFTXCM

EFTX5P

EFTX5M

EFTX4P

EFTX4M

EFTX3P

EFTX3M

EFTX2P

EFTX2M

EFTX1P

EFTX1M

EFTX0P

EFTX0M

EFTXCP

EFTXCM

EFTX5P

EFTX5M

EFTX4P

EFTX4M

EFTX3P

EFTX3M

DDC6CLK_DVI

DDC6DATA_DVI

A_R_DAC_F

8

IN

A_G_DAC_F

8

IN

A_B_DAC_F

8

IN

HSYNC_DAC_R

8

IN

VSYNC_DAC_R

8

IN

10K

5%

HPD_EF_DVI

10K

5%

EFTX0M
EFTX0P
EFTX1M
EFTX1P
EFTX2M
EFTX2P

EFTX3M
EFTX3P
EFTX4M
EFTX4P
EFTX5M
EFTX5P
DDC6CLK_DVI
DDC6DATA_DVI

EFTXCM
EFTXCP
VSYNC_DAC_R
HPD_EF_DVI

A_R_DAC_F
A_G_DAC_F
A_B_DAC_F

HSYNC_DAC_R

SCREW1900

SCREW1901

C1926

1uF
16V

SHIELD2

2

SHIELD3

3

SHIELD4

4

TX0-

A17

TX0+

A18

TX1-

A9

TX1+

A10

TX2-

A1

TX2+

A2

SHLD24

A3

SHLD13

A11

SHLD05

A19

TX3-

A12

TX3+

A13

TX4-

A4

TX4+

A5

TX5-

A20

TX5+

A21

DDCC

A6

DDCD

A7

VDDC

A14

GND

A15

SHLDC

A22

TXC-

A24

TXC+

A23

VSYNC

A8

HPD

A16

R

C1

G

C2

B

C3

AGND1

C5

AGND2

C6

HSYNC

C4

SHIELD6

6

SHIELD8

8

SHIELD9

9

SHIELD10

10

SHIELD11

11

1/2 LOWER

17

24

C3

C5

C4

1

9

816

C1

C5A

C2

STACKED DVI - BOTTOM

J1900B

TOWS_multi_con_dvi_1

COMMON

VVVV305

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Date:

1

2

3

4

5

6

7

Date:

MS-V305

11 CURACAO LVTMDPEF dDVI Botto

11 CURACAO LVTMDPEF dDVI Botto

11 CURACAO LVTMDPEF dDVI Botto

Friday, August 16, 2013

Friday, August 16, 2013

Friday, August 16, 2013

Sheet of

Sheet of

Sheet of

8

11 23

11 23

11 23

10

10

10

1

2

3

4

5

6

7

8

(12) CURACAO POWER

+VDDC

POSCAP

12

+

C317

330uF

2V

A A

B B

C C

+VDDC +VDDC +MVDD

C1203

C1204

C1205

C1206

C1207

C1208

C1209

C1200

1uF

1uF

1uF

1uF

1uF

C1222

C1223

C1221

1uF

1uF

1uF

C1238

C1239

C1237

1uF

1uF

1uF

C1248

C1249

C1247

1uF

1uF

1uF

C1259

C1257

C1258

1uF

1uF

1uF

C1269

C1267

C1268

1uF

1uF

1uF

C1277

C1278

1uF

1uF

1uF

C1224

C1225

C1226

1uF

1uF

1uF

C1240

C1241

C1242

1uF

1uF

1uF

C1250

C1251

C1252

1uF

1uF

1uF

C1260

C1261

C1262

1uF

1uF

1uF

C1270

C1271

C1272

1uF

1uF

1uF

C1210

1uF

1uF

1uF

C1227

C1228

C1202

1uF

1uF

1uF

C1243

C1244

C1245

1uF

1uF

1uF

C1253

C1254

C1255

1uF

1uF

1uF

C1263

C1264

C1265

1uF

1uF

1uF

C1273

C1274

C1275

1uF

1uF

1uF

AA21
AA23
AA26
AA28

C1211

AA31
AA33
AB19
AB22
AB24

1uF

AB27
AB30
AB32
AB35
AC18
AC21
AC23
AC26

C1229

AC28
AC31
AC33
AC36
AD17

1uF

AD19
AD22
AD24
AD27
AD30
AD32
AD35
AD37
AD40

C1246

AF16
AF18
AF21
AF23

1uF

AF26
AF28
AF31
AF33
AF36
AF38
AG17
AG19
AG22

C1256

AG24
AG27
AG30
AG32

1uF

AG35
AG37

AH16
AH18
AH21
AH23
AH26

C1266

AH28
AH31
AH33
AH36
AH38

1uF

AK17
AK19
AK22
AK24
AK27
AK30
AK32

C1276

AK35
AK37

AL18
AL21

1uF

AL23
AL26
AL28
AL31
AL33
AL36

U1M

PART 14 OF 18

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

P

VDDC

O

VDDC

W

VDDC

E
R

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

PITCAIRN

FB_VDDC
FB_VSSC

AL38

VDDC

AM22

VDDC

AM24

VDDC

AM27

VDDC

AM30

VDDC

AM32

VDDC

AM35

VDDC

AM37

VDDC

AM40

VDDC

AN21

VDDC

AN23

VDDC

AN26

VDDC

AN28

VDDC

AN31

VDDC

AN33

VDDC

AN36

VDDC

AN38

VDDC

AN41

VDDC

AR22

VDDC

AR24

VDDC

AR27

VDDC

AR30

VDDC

AR32

VDDC

AR35

VDDC

AR37

VDDC

AR40

VDDC

AT23

VDDC

AT26

VDDC

AT28

VDDC

AT31

VDDC

AT33

VDDC

AT36

VDDC

AT38

VDDC

AT41

VDDC

AU24

VDDC

AU27

VDDC

AU30

VDDC

AU32

VDDC

AU35

VDDC

AU37

VDDC

AU40

VDDC

AV26

VDDC

AV28

VDDC

AV31

VDDC

AV33

VDDC

AV36

VDDC

AV38

VDDC

AV41

VDDC

AY24

VDDC

AY27

VDDC

AY30

VDDC

AY32

VDDC

AY35

VDDC

AY37

VDDC

AY40

VDDC

BA26

VDDC

BA28

VDDC

BA31

VDDC

BA33

VDDC

BA36

VDDC

BA38

VDDC

BB24

VDDC

BB27

VDDC

BB30

VDDC

BB32

VDDC

T26

VDDC

T28

VDDC

U24

VDDC

U27

VDDC

U30

VDDC

V23

VDDC

V26

VDDC

V28

VDDC

V31

VDDC

W22

VDDC

W24

VDDC

W27

VDDC

W30

VDDC

W32

VDDC

AF41
AG41

VDDC_VSEN

VDDC_VRTN

C1212

C1213

C1214

C1215

C1216

C1201

C1217

C1218

C1219

C1220

22uF

22uF

22uF

22uF

22uF

22uF

22uF

22uF

22uF

22uF

C1230

C1231

C1232

C1233

C1234

C1235

C1236

C1279

C1281

22uF

22uF

22uF

22uF

22uF

22uF

22uF

22uF

22uF

C1282

C1283

22uF

22uF

14,21

OUT

14,21

OUT

C1401

C1402

C1403

1uF

1uF

1uF

C1410

C1411

C1412

1uF

1uF

1uF

C1420

C1421

1uF

1uF

C1430

C1431

C1432

1uF

1uF

1uF

C1441

C1442

1uF

1uF

C1450

C1451

C1452

1uF

1uF

1uF

C1406

C1407

C1408

C1404

1uF

1uF

C1415

1uF

C1425

1uF

C1435

C1433

1uF

1uF

C1445

C1443

C1444

1uF

1uF

1uF

C1455

C1454

1uF

1uF

C1409

1uF

1uF

1uF

C1416

C1417

1uF

1uF

C1426

C1427

1uF

1uF

C1436

C1437

C1438

1uF

1uF

1uF

C1446

1uF

C1456

C1457

C1458

1uF

1uF

1uF

C1468

1uF

AA13

AA6
AB12
AC13

AE6

AJ6

AL13

AM12
AN13

AN6
AR14
AT13
AU14

AU6
AV13
AV16
AY14
AY17
BA18

BA6
BB19
BC11

BE6

BE9

BF8

BG7
BH13

BH9

F13

C1429

1uF

C1439

1uF

C1449

1uF

C1469

1uF

F17

F21

F25

F29

F33

F37

F41

F45

F9

G47

G7

H46

J45
J48

J6

L43
M12
M14
M22
M32
N13
N16
N18
N21
N23
N31
N33
N36
N38
N48

N6
P12
P14
P17
P19
P37
P40
T13
T18
T38
U14
U40

U6
V13
V16
V41

W14
W42

U1N

PART 15 OF 18

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

P

VDDR1

O

VDDR1

W

VDDR1

E
R

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

PITCAIRN

FB_VDDCI
FB_VSSCI

AA16

VDDCI

AA18

VDDCI

AA36

VDDCI

AA38

VDDCI

AA41

VDDCI

AB14

VDDCI

AB17

VDDCI

AB37

VDDCI

AB40

VDDCI

AB42

VDDCI

AC16

VDDCI

AC38

VDDCI

AC41

VDDCI

AD14

VDDCI

AF13

VDDCI

AG12

VDDCI

AG14

VDDCI

AH13

VDDCI

AK14

VDDCI

AL16

VDDCI

AM14

VDDCI

AM17

VDDCI

AN16

VDDCI

AR17

VDDCI

AT16

VDDCI

AT18

VDDCI

AT21

VDDCI

AU17

VDDCI

AU19

VDDCI

AU22

VDDCI

AV18

VDDCI

AV21

VDDCI

AV23

VDDCI

AY19

VDDCI

AY22

VDDCI

BA21

VDDCI

BA23

VDDCI

M27

VDDCI

N26

VDDCI

N28

VDDCI

P22

VDDCI

P24

VDDCI

P27

VDDCI

P30

VDDCI

P32

VDDCI

P35

VDDCI

T21

VDDCI

T23

VDDCI

T31

VDDCI

T33

VDDCI

T36

VDDCI

U19

VDDCI

U22

VDDCI

U32

VDDCI

U35

VDDCI

U37

VDDCI

V18

VDDCI

V21

VDDCI

V33

VDDCI

V36

VDDCI

V38

VDDCI

W17

VDDCI

W19

VDDCI

W35

VDDCI

W37

VDDCI

W40

VDDCI

BB22
BB23

VDDCI_SV

C1300

C1301

1uF

1uF

C1310

C1311

1uF

1uF

C1320

C1321

1uF

1uF

C1336

C1337

1uF

1uF

C1330

C1331

22uF

22uF

C1304

C1305

C1306

C1302

C1303

1uF

1uF

1uF

C1314

C1312

C1313

1uF

1uF

1uF

C1324

C1322

C1323

1uF

1uF

1uF

C1338

C1339

C1340

1uF

1uF

1uF

C1332

C1333

C1334

22uF

22uF

22uF

15

OUT

C1307

1uF

1uF

1uF

C1315

C1316

C1317

1uF

1uF

1uF

C1325

C1326

C1327

1uF

1uF

1uF

C1341

C1342

1uF

1uF

C1335

22uF

+VDDCI

C1308

C1309

1uF

1uF

C1318

1uF

C1328

C1329

1uF

1uF

D D

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

MS-V305

12 CURACAO POWER

12 CURACAO POWER

12 CURACAO POWER

Sheet of

Sheet of

Sheet of

8

12 23

12 23

12 23

10

10

10

1

2

3

4

5

6

7

8

(13) CURACAO GROUND

A48
AA10
AA14
AA17
AA19

AA2
AA22
AA24

A A

B B

C C

D D

1

2

AA27
AA30
AA32
AA35
AA37
AA40
AA42

AB13
AB16
AB18
AB21
AB23
AB26
AB28
AB31
AB33
AB36
AB38
AB41

AC10
AC14
AC17
AC19

AC22
AC24
AC27
AC30
AC32
AC35
AC37
AC40
AC42

AD13
AD16
AD18
AD21
AD23
AD26
AD28
AD31
AD33
AD36
AD38
AD41
AE11

AF10
AF14
AF17
AF19
AF22
AF24
AF27
AF30
AF32
AF35
AF37
AF40
AG13
AG16
AG18

AG21
AG23
AG26
AG28
AG31
AG33
AG36
AG38

AH14
AH17
AH19
AH22
AH24
AH27
AH30
AH32
AH35
AH37
AH40

AK13
AK16
AK18
AK21
AK23
AK26
AK28
AK31
AK33
AK36
AK38
AK41

AA8

AB9

AC2

AC6

AE2

AE8

AG2

AG6

AH9

AJ11

AJ2

AJ7

AL14
AL17
AL19

AL2

AL22
AL24
AL27
AL30
AL32
AL35
AL37
AL40

AL6

AL9

U1O

PART 16 OF 18

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G
N

VSS

D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

PITCAIRN

AM13

VSS

AM16

VSS

AM21

VSS

AM23

VSS

AM26

VSS

AM28

VSS

AM31

VSS

AM33

VSS

AM36

VSS

AM38

VSS

AM41

VSS

AM8

VSS

AN12

VSS

AN14

VSS

AN17

VSS

AN2

VSS

AN22

VSS

AN24

VSS

AN27

VSS

AN30

VSS

AN32

VSS

AN35

VSS

AN37

VSS

AN40

VSS

AN9

VSS

AR13

VSS

AR16

VSS

AR2

VSS

AR21

VSS

AR23

VSS

AR26

VSS

AR28

VSS

AR31

VSS

AR33

VSS

AR36

VSS

AR38

VSS

AR41

VSS

AR6

VSS

AR8

VSS

AT10

VSS

AT14

VSS

AT17

VSS

AT19

VSS

AT22

VSS

AT24

VSS

AT27

VSS

AT30

VSS

AT32

VSS

AT35

VSS

AT37

VSS

AT40

VSS

AT6

VSS

AU13

VSS

AU16

VSS

AU18

VSS

AU2

VSS

AU21

VSS

AU23

VSS

AU26

VSS

AU28

VSS

AU31

VSS

AU33

VSS

AU36

VSS

AU38

VSS

AU41

VSS

AU50

VSS

AU52

VSS

AV11

VSS

AV14

VSS

AV17

VSS

AV19

VSS

AV22

VSS

AV24

VSS

AV27

VSS

AV30

VSS

AV32

VSS

AV35

VSS

AV37

VSS

AV40

VSS

AV43

VSS

AV46

VSS

AV8

VSS

AW2

VSS

AW50

VSS

AW52

VSS

AW6

VSS

AW9

VSS

AY10

VSS

AY13

VSS

AY16

VSS

AY18

VSS

AY21

VSS

AY23

VSS

AY26

VSS

AY28

VSS

AY31

VSS

AY33

VSS

AY36

VSS

AY38

VSS

AY41

VSS

AY48

VSS

AY49

VSS

B11

VSS

B13

VSS

B15

VSS

B17

VSS

B19

VSS

B21

VSS

B23

VSS

B25

VSS

B27

VSS

B29

VSS

B31

VSS

B33

VSS

B35

VSS

B37

VSS

B39

VSS

B41

VSS

B43

VSS

B45

VSS

B47

VSS

B7

VSS

B9

VSS

BA14

VSS

3

BM11
BM13

BA17
BA19

BA22
BA24
BA27
BA30
BA32
BA35
BA37
BA40
BA41
BB11
BB16
BB18
BB21
BB26
BB28
BB31
BB33
BB48
BB49
BB51
BB53

BC16
BC19

BC23
BC33
BC40

BD15
BD18
BD29
BD38
BE12
BE18

BE25
BF14

BF16
BF19
BF21
BF26
BF32

BH11
BH12
BH14
BH15
BH38
BH39
BH40

BK15

BN42
BN16

BA2

BB8

BC2

BC6

BE2
BE8

BF9
BG2
BG6
BH1

BH7
BL42
BL16

BM7
BM9

F10

F11

F14

F15

F18

F19

F23

F27

F31

F35

F36

F39

F43

F47

F7

G2
G29
G48
G52

G6
H12
H16
H21
H25
H32
H35
H38
H42
H45

H9

J14
J18

J2
J22
J28
J31
J33
J39
J46
J52

J8

K15
K19
K21
K23
K26

K36
K40

K6
L16

L2
L25
L29
L38

U1P

PART 17 OF 18

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G
N

VSS

D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS

PITCAIRN

4

L42

VSS

L48

VSS

L52

VSS

L6

VSS

M13

VSS

M16

VSS

M33

VSS

M45

VSS

M48

VSS

M8

VSS

N12

VSS

N14

VSS

N17

VSS

N19

VSS

N2

VSS

N22

VSS

N24

VSS

N27

VSS

N30

VSS

N32

VSS

N35

VSS

N37

VSS

N40

VSS

N52

VSS

P13

VSS

P16

VSS

P18

VSS

P21

VSS

P23

VSS

P26

VSS

P28

VSS

P31

VSS

P33

VSS

P36

VSS

P38

VSS

P41

VSS

P46

VSS

P48

VSS

P6

VSS

P9

VSS

R10

VSS

R2

VSS

R44

VSS

R48

VSS

R50

VSS

R6

VSS

T11

VSS

T12

VSS

T14

VSS

T17

VSS

T19

VSS

T22

VSS

T24

VSS

T27

VSS

T30

VSS

T32

VSS

T35

VSS

T37

VSS

T40

VSS

T42

VSS

T43

VSS

T46

VSS

T53

VSS

T8

VSS

U13

VSS

U16

VSS

U18

VSS

U2

VSS

U21

VSS

U23

VSS

U26

VSS

U28

VSS

U31

VSS

U33

VSS

U36

VSS

U38

VSS

U41

VSS

V14

VSS

V17

VSS

V19

VSS

V22

VSS

V24

VSS

V27

VSS

V30

VSS

V32

VSS

V35

VSS

V37

VSS

V40

VSS

V42

VSS

V44

VSS

V6

VSS

V9

VSS

W10

VSS

W13

VSS

W16

VSS

W18

VSS

W2

VSS

W21

VSS

W23

VSS

W26

VSS

W28

VSS

W31

VSS

W33

VSS

W36

VSS

W38

VSS

W41

VSS

W48

VSS

W6

VSS

A4

VSS

A50

VSS

BK1

VSS

BK53

VSS

BL3

VSS

BL51

VSS

BN4

VSS

BN50

VSS

C3

VSS

C51

VSS

D1

VSS

D53

VSS

V53

VSS

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

5

6

7

Friday, August 16, 2013

MS-V305

13 CURACAO GND

13 CURACAO GND

13 CURACAO GND

Sheet of

Sheet of

Sheet of

8

13 23

13 23

13 23

10

10

10

1

2

3

4

5

6

7

8

+VDDC

12

12

12

+

C676

820uF

2.5V

12

+

+

C677

C678

820uF

820uF

2.5V

2.5V

12

+

+

C679

C680

820uF

820uF

2.5V

2.5V

12

12

+

+

C682

C681

820uF

820uF

2.5V

2.5V

A A

+VDDC

C686

C687

C684

C685

22uF

22uF

4V

4V

C693

C694

22uF

22uF

4V

4V

MC642

MC643

22uF

22uF

4V

4V

MC651

MC652

22uF

22uF

4V

4V

MC660

MC661

22uF

22uF

4V

B B

C C

BOOST3

PHASE3

BOOST2

PHASE2

D D

BOOST1

PHASE1

4V

MC669

MC670

0.015uF

0.015uF

10V

10V

High Frequency Decoupling - Place Last

+VDDC_PHASE3_SOURCE

D601

BAT54KFILM

1 2

R659

UNNAMED_26_CAP_I62_A

2.2R

5%

C651

0.22uF
25V

+VDDC_PHASE12_SOURCE

D602

BAT54KFILM

1 2

R660

UNNAMED_26_CAP_I66_A

2.2R

5%

C652

0.22uF
25V

+VDDC_PHASE12_SOURCE

D603

BAT54KFILM

1 2

R661

UNNAMED_26_CAP_I70_A

2.2R

5%

C653

0.22uF
25V

C688

22uF

22uF

22uF

4V

4V

4V

C695

C696

C697

22uF

22uF

22uF

4V

4V

4V

MC644

MC645

MC646

22uF

22uF

22uF

4V

4V

4V

MC653

MC654

MC655

22uF

22uF

22uF

4V

4V

4V

MC662

MC663

MC664

22uF

22uF

22uF

4V

4V

4V

MC672

MC673

MC671

0.015uF

0.015uF

0.015uF
10V

10V

10V

VDDC_VID1

19

IN

VDDC_VID2

19

IN

VDDC_VID3

19

IN

VDDC_VID4

19

IN

VDDC_VID5

19

IN

VDDC_VID6

19

IN

VDDC_VID7

19

IN

+5V

R642

1K

5%

VDDC_VSEN

12,21

IN

VDDC_VRTN

12,21

IN

1

C691

C689

C690

22uF

22uF

22uF

4V

4V

4V

MC640

C698

C699

22uF

22uF

22uF

4V

4V

4V

MC649

MC647

MC648

22uF

22uF

22uF

4V

4V

4V

MC658

MC656

MC657

22uF

22uF

22uF

4V

4V

4V

MC667

MC665

MC666

22uF

22uF

22uF

4V

4V

4V

MC674

MC675

0.015uF

0.015uF

10V

10V

+3.3V_BUS

R640

1K

C640

0.1uF

0R

R643

15K

1%

R699

1K

1%

C644

TR603

C643

0.1uF

0.1uF

0R

10V

10V

5%

2

+12V_BUS_SOURCE1

12

+

C683

820uF

2.5V

C692

22uF
4V

MC641

22uF
4V

MC650

22uF
4V

MC659

22uF
4V

MC668

22uF
4V

5%

UNNAMED_26_CAP_I51_B

6.3V

R641

5%

13K

12

+

+12V_BUS_SOURCE1

+VDDC_PHASE12_SOURCE

BOOST3

LGATE3_CTR

48

BST3

1

BG3

2

PSI

UNNAMED_26_NCP5395T_I1_VID0

3

VID0

4

VID1

5

VID2

6

VID3

7

VID4

8

VID5

9

VID6

10

VID7/AMD

R644

UNNAMED_26_NCP5395T_I1_ROSC

11

ROSC

1%

UNNAMED_26_NCP5395T_I1_ILIM

12

ILIM

IMON14VSP15VSN16DIFFOUT17COMP18VFB19VDRP20VDFB21CSSUM22DAC2312VMON24VCC

R645

IMON

13

100K

1%

C641

0.1uF

6.3V

VDDC_FBB

C645

R646

UNNAMED_26_CAP_I25_A

47R

5%

560pF

25V

R647

1K

1%

R650

47K

C656

270uF
16V

C660

10uF
16V

C668

10uF
16V

UGATE3_CTR

47

TG3

UNNAMED_26_NCP5395T_I1_IMON

C642

0.01uF
50V

R648

3.3K

0.0018uF

1 2

MC601

PHASE3

46

SWN3

5%

C661

10uF
16V

C669

10uF
16V

PWM4_EN

45

DRVON

C646

47pF

50V

+VDDC_PHASE3_SOURCE

C662

10uF
16V

C670

10uF
16V

BOOST2

UGATE2_CTR

43

44

TG2

BST2

VDDC_VFB

PR621

1K
1%

50V

R649

UNNAMED_26_RES_I364_A

1K

1%

R651

UNNAMED_26_RES_I365_A

1K

1%

12

+

C657

270uF
16V

C631

1uF
16V

PHASE2

42

SWN2

NCP5395TMNR2G

1K

+VDDC_PHASE12_SOURCE

12

+

+VDDC_PHASE3_SOURCE

C663

10uF
16V

C671

10uF
16V

VCCP

LGATE2_CTR

41

BG2

U601

C647

UNNAMED_26_CAP_I18_AUNNAMED_26_CAP_I18_BUNNAMED_26_CAP_I20_AUNNAMED_26_CAP_I20_B

22pF

R652

PHASE1

39

40

VCCP

SWN1

UNNAMED_26_NCP5395T_I1_CSSUMUNNAMED_26_NCP5395T_I1_DIFFOUT

R653

1K
1%

50V

1%

+VDDC_PHASE12_SOURCE

R698

2.2R
5%

BOOST1

UGATE1_CTR

37

38

TG1

BST1

UNNAMED_26_CAP_I15_A

C648

0.0047uF

UNNAMED_26_CAP_I15_B

50V

UNNAMED_26_CAP_I8_A

R654

1K

C650

1%

1uF
16V

UNNAMED_26_CAP_I12_A

C649

1uF
16V

C664

10uF
16V

C672

10uF
16V

+12V_EXT_A

57

AGND58AGND59AGND60AGND61AGND62AGND63AGND64AGND

AGND50AGND51AGND52AGND53AGND54AGND55AGND56AGND

49

3

+VDDC_PHASE12_SOURCE

12

C658

270uF
16V

C665

10uF
16V

C673

10uF
16V

R657

1.2K
5%

+

C659

270uF
16V

UGATE1_CTR

PHASE1

C666

C667

10uF

10uF

16V

16V

C674

C675

10uF

10uF

16V

16V

PWM4

LGATE1_CTR

36

BG1

35

G4

34

VR_RDY

33

EN

32

CS1N

31

CS1P

30

CS2N

29

CS2P

28

CS3N

27

CS3P

26

CS4N

25

CS4P

+5V

R655

2.2R

5%

+12V_EXT_A

R656

10K

1%

LGATE1_CTR

R658

1K
1%

VDDC_POK

VDDC_EN

CSN1

CSP1

CSN2

CSP2

CSN3

CSP3

CSN4

CSP4

+VDDC +5V

5%

TR604

0R

VDDC_VSEN

4

+VDDC_PHASE12_SOURCE

BSC120N03LS

56789

R601

4

0R

5%

NR601

10K
1%

123

56789

R603

UNNAMED_26_MOSN4D3STH_I92_G4 UNNAMED_26_MOSN4D3STH_I95_G4

4

0R

5%

MR603

10K
1%

123

19

OUT

19

IN

C632

0.1uF

6.3V
DNI

TR601

1K
1%

VDDC_VFB

1K

TR602

39A

Q601

93A

Q603

BSC042N03LS

1%

UGATE1_CTR

LGATE1_CTR

+VDDC_PHASE12_SOURCE

BSC120N03LS

56789

39A

Q602

UNNAMED_26_MOSN4D3STH_I403_G4UNNAMED_26_MOSN4D3STH_I404_G4

4

5%

R602

123

0R

56789

4

5%

R604

123

0R

+12V_BUS_SOURCE1

PWM4

PWM4_EN

Q604

BSC042N03LS

NR634

2.2R
5%

U602_VCC

C654

1uF
16V

R609

2.2R

93A

5%

UNNAMED_26_CAP_I100_A

C609

0.0022uF
50V

CSP1

CSN1

D604

12

BAT54KFILM

U602

1

4

BST

VCC

2

8

IN

DRVH

3

7

EN

SW

5

6

DRVL

PGND

NCP5359DR2G

5

U602_BST

NR620

2.2R
5%

L601

0.22uH

1 2

UNNAMED_26_NETSHORT_I396_N2

R605

10K

C605

1%

CSP1

0.1uF

50V

R606

100K

1%

UNNAMED_26_CAP_I81_A

C655

0.22uF
25V

UGATE4_CTR

PHASE4

LGATE4_CTR

6

UGATE2_CTR

+VDDC

CSN1

C606

0.1uF
16V

PHASE2

LGATE2_CTR

UGATE3_CTR

PHASE3

LGATE3_CTR

UGATE4_CTR

PHASE4

LGATE4_CTR

0R

NR611

10K
1%

0R

MR613

10K
1%

0R

NR621

10K
1%

0R

MR623

10K
1%

0R

NR631

10K
1%

0R

NR633

10K
1%

BSC120N03LS

56789

39A

R611

R613

R621

R623

R631

R633

Q611

UNNAMED_26_MOSN4D3STH_I399_G4 UNNAMED_26_MOSN4D3STH_I400_G4

4

5%

123

UGATE2_CTR

56789

93A

Q613

BSC042N03LS

4

5%

123

LGATE2_CTR

+VDDC_PHASE3_SOURCE

BSC120N03LS

56789

39A

Q621

UNNAMED_26_MOSN4D3STH_I401_G4

4

5%

123

UGATE3_CTR

56789

93A

Q623

BSC042N03LS

4

5%

123

LGATE3_CTR

+12V_BUS_SOURCE1

BSC120N03LS

56789

39A

Q631

UNNAMED_26_MOSN4D3STH_I270_G4

4

5%

123

UGATE4_CTR

56789

93A

Q633

BSC042N03LS

4

5%

123

LGATE4_CTR

7

BSC120N03LS

56789

39A

Q612

4

5%

R612

123

0R

56789

93A

Q614

BSC042N03LS

UNNAMED_26_MOSN4D3STH_I233_G4UNNAMED_26_MOSN4D3STH_I236_G4

4

5%

R614

123

0R

56789

39A

Q622

BSC120N03LS

UNNAMED_26_MOSN4D3STH_I243_G4

4

5%

R622

123

0R

56789

93A

Q624

BSC042N03LS

UNNAMED_26_MOSN4D3STH_I258_G4UNNAMED_26_MOSN4D3STH_I261_G4

4

5%

R624

123

0R

56789

39A

Q632

BSC120N03LS

4

5%

R632

123

0R

56789

93A

Q634

BSC042N03LS

UNNAMED_26_MOSN4D3STH_I283_G4UNNAMED_26_MOSN4D3STH_I286_G4

4

5%

R634

123

0R

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

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MSI

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Size Document Description Rev

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Size Document Description Rev

Custom

Custom

Custom

14 VDDC

14 VDDC

14 VDDC

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

R619

2.2R
5%

UNNAMED_26_CAP_I230_A

C619

0.0022uF
50V

R629

2.2R
5%

UNNAMED_26_CAP_I255_A

C629

0.0022uF
50V

R639

2.2R
5%

UNNAMED_26_CAP_I280_A

C639

0.0022uF
50V

CSP2

CSN2

CSP3

CSN3

CSP4

CSN4

L611

1 2

UNNAMED_26_NETSHORT_I394_N2

R615

10K
1%

L621

1 2

UNNAMED_26_NETSHORT_I392_N2

R625

10K
1%

L631

1 2

UNNAMED_26_NETSHORT_I390_N2

R635

10K
1%

CSP4

MS-V305ci20313

MS-V305

MS-V305

0.22uH

C615

CSP2

0.1uF

R616

100K

0.22uH

C625

CSP3

0.1uF

R626

100K

1%

0.22uH

C635

0.1uF

R636

100K

Sheet of

Sheet of

Sheet of

8

50V

1%

50V

50V

1%

+VDDC

CSN2

C616

0.1uF
16V

+VDDC

CSN3

C626

0.1uF
16V

+VDDC

CSN4

C636

0.1uF
16V

14 23

14 23

14 23

10

10

10

1

(15) VDDCI

2

3

4

5

6

7

8

UNNAMED_15_MOSN4D3STH_I69_G4

4

93A

U801

BOOT

UGATE

UNNAMED_15_APW7165A_I19_GND

GND

LGATE5VCC

GND
GND11GND

+VDDCI_COMP

C814

0.1uF

+VDDCI_FB

+VDDCI_SOURCE

C818

0.15uF

603

BSC120N03LS

56789

39A

Q801

TO252 DPAK PKG

123

R819

2.2R
5%

UNNAMED_15_CAP_I65_B

+VDDCI_VCC

C808

1.8NF

Place Rs and Cs across QL

12

19

+12V_BUS

R807

2.2R
5%

C807

100NF

56789

93A

Q804

BSC042N03LS

4

123

+PW_VDDCI_M

8

PHASE

+VDDCI_COMP

7

COMP

6

+VDDCI_FB

FB

+VDDCI_VCC

12

C803

GND

220NF

FILTERED SMPS VCC BOOT CIRCUIT

C820

10uF
1206

19

OUT

OUT

C821

10uF

1206

L801

1 2

+VDDCI_FB

Input Bulk CAPs

1uH

VDDCI_SV

R811

10K
1%

Place R1 and R4 close to

PWM and routed with

separate 20mil trace to

the ASIC

+VDDCI_B

12

+

R816

2.2R
5%

UNNAMED_15_CAP_I14_A

C805

100NF

C831

270uF

6.3x12.5
TH

+VDDCI

12

12

+

C825

820uF

2.5V

Output Bulk CAPs

+

C826

820uF

2.5V

C813

1.8NF

UNNAMED_15_CAP_I31_B

50V

R813

1.5K
1%

+VDDCI_B

+PW_VDDCI_M

Sense Point

UNNAMED_15_NETSHORT_I49_N2

R800

0R

NC

5%

C823

C824

C829

0.1uF

0.015uF

402

402

603

Output MLCC

22uF
4V

0805 6.3V

C830

22uF
4V

0805 6.3V

A A

+PW_VDDCI_HGD

+PW_VDDCI_M

B B

+PW_VDDCI_LGD

R821

0R

5%

56789

R822

0R

5%

R823

0R

5%

+PW_VDDCI_HGD

+PW_VDDCI_LGD

Q803

BSC042N03LS

UNNAMED_15_MOSN4D3STH_I70_G4 UNNAMED_15_MOSN4D3STH_I74_G4

4

123

+VDDCI_B

1
2

R805

3

33.2K

1%

R815

4

+PW_VDDCI_LGD

NC

3.48K

1%

9

10

COMPENSATION CIRCUIT

C C

+VDDCI_COMP

C811

2.7NF

UNNAMED_15_CAP_I5_B

50V

R812

20K
1%

NC

C812

33PF

UNNAMED_15_CAP_I6_B

50V

R814

0R

NC

5%

R809

0R
5%

share pad of R814,R809

D D

MICRO-STAR INT'L CO.,LTD

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MS-V305

MS-V305

MSI

MSI

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Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

15 VDDCI

15 VDDCI

15 VDDCI

MS-V305

Sheet of

Sheet of

Sheet of

8

15 23

15 23

15 23

10

10

10

1

(16) MVDD

2

3

4

5

6

7

8

A A

+PW_MVDDQ_HGD

R721

0R

+PW_MVDDQ_HGDR

5%

Layout guideline

1-Position the controller (U703) suc h that LGate(pin4) is the closet to gate

B B

C C

of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate
of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as
short and as wide as possible to reduce the trace inductance.

2-Place the bypass cap acitors for Vcc as well as Boost c aps as close to the
controller as possible. They are as follows;
Vcc bypass cap is C703, and Boost cap is C705.

3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place
the rest of the compensation network close to the pins 7 and 6. These are R710,
R711, R713, C713 and R712, C711 and C712.

+PW_MVDDQ_LGD

R722

0R

5%

+PW_MVDDQ_LGDR1

COMPENSATION CIRCUIT

C711

2.7NF

N49194738

10V

R712

24.9K
1%

NC

+MVDDQ_B

+PW_MVDDQ_HGD

3.48K

+PW_MVDDQ_LGD

R709

0R
5%

NC

C712

33PF
50V

N49194672

4

40.2K

R715

1%

+MVDDQ_COMP

share pad of R714,R709

+MVDD_SOURCE

12

R705

2.2R
5%

UNNAMED_16_CAP_I28_A

C705

100NF

N49194693

R713

1.5K
1%

+PW_MVDDQ_M

C713

2.7NF
50V

+MVDDQ_B

+

C732

270uF

6.3x12.5
TH

MVDDQ_FB_TRACE

R700

0R
5%

Sense Point

+MVDD

12

12

+

C723

C724

C729

0.1uF

0.015uF

402 402 0805 6.3V 0805 6.3V

603

Output MLCC Output Bulk CAPs

C730

22uF

22uF

4V

4V

+

C725

820uF

2.5V

6.3 x 9 mm, TH 6.3 x 9 mm, TH

C726

820uF

2.5V

C718

0.15uF

603

BSC120N03LS

56789

39A

Q701

4

C720

10uF
1206 1206

C721

10uF

Input Bulk CAPs

123

L701

+PW_MVDDQ_M

R719

1R

+PW_MVDDQ_M

+MVDDQ_COMP

5%

N49194432

C708

1.8NF

Place Rs and Cs across QL

19

19

OUT

56789

93A

Q702

BSC042N03LS

123

U701

1
2

R716

UNNAMED_16_APW7165A_I2_GND

3

1%

4
9

10

BOOT

UGATE

GND

LGATE5VCC

GND
GND11GND

8

PHASE

7

COMP

+MVDDQ_FB

6

FB

+MVDDQ_VCC

12

C703

GND

220NF

FILTERED SMPS VCC

+MVDDQ_VCC

+12V_BUS

R707

2.2R
5%

C707

100NF

C714

0.1uF

NC

R714

+MVDDQ_FB

0R

5%

1 2

+MVDDQ_FB

0.68uH

R711

10K
1%

Place R1 and R4 close to

PWM and routed with

separate 20mil trace to

the ASIC

BOOT CIRCUIT

MVDDQ_SV

+MVDDQ_B

D D

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

16 MVDD

16 MVDD

16 MVDD

MS-V305

Sheet of

Sheet of

Sheet of

8

16 23

16 23

16 23

10

10

10

1

2

3

4

5

6

7

8

(17) 0.95V

A A

+0.95_VIN

1

2

UNNAMED_25_MOSN2D1S_I514_G

8

UNNAMED_25_MOSN2D1S_I513_G

3

7

6

0.95V_PHASE

NTMD4903NFR2G

4 5

Q450A

NTMD4903NFR2G

Q450B

R419

1R
5%

UNNAMED_25_CAP_I507_B

C408

1.8NF

Place Rs and Cs across QL

R471

5%

0R

UNNAMED_25_CAP_I492_A

C455

1uF
16V

0R

+12V_BUS

5%

UNNAMED_25_NETSHORT_I523_N2

R473

5%

0R

C490

C491

10uF

10uF

16V

16V

12061206

0.95V_HGD

0.95V_LGD

0.95V_PHASE

12

L450

2.2uH

12

+

C480

C481

820uF

22uF

2.5V

4V

6.3x9mm TH

+0.95V

C482

C483

C484

22uF

22uF

22uF

4V

4V

4V

2021036600G
2020044100G

1 - Vin
2 - Vin
3 - LG
4 - Gnd
5 - Vx
6 - Vx
7 - Vx
8 - HG

B B

R455

UNNAMED_25_CAP_I488_A

C461

2.2NF
50V

R462

R461

UNNAMED_25_CAP_I482_A

2.2NF

0.95V_EN

20K

C462

UNNAMED_25_CAP_I485_A

33PF

50V

5%0RR459

50VC463

uP1529QSU8

COMP/EN

PHASE

GND4
GND3

UNNAMED_25_CAP_I480_B

FB

VCC

C456

100NF

25V

0.95V_PHASE

0.95V_PHASE

8
7

0.95V_FD

6
5
12

11

R460

16.9K
1%

R456

0R

5%

U450

0.95V_BOOT

1

BOOT

2

UGATE

3

OSC

4

LGATE

9

GND1

UNNAMED_25_RES_I477_A

10

R465

10K
1%

C C

NC

GND2

R483

40.2K
1%

19

IN

1%

R464

5%

0R

NC

1%

10K

1.5K

1%R463

D D

MICRO-STAR INT'L CO.,LTD

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MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

17 0.95V REG

17 0.95V REG

17 0.95V REG

MS-V305

Sheet of

Sheet of

Sheet of

8

17 23

17 23

17 23

10

10

10

1

2

3

4

5

6

7

8

(18) SMALL RAIL REGULATORS

A A

VIN = 3.0V TO 3.6V MAX IOUT = 1.3A RMS MAX

VOUT = +1.8V +/- 2%LDO #1:

PCB: 50 TO 70mm SQ. COPPER AREA FOR COOLING

REGULATOR FOR +5V RAILS

IOUT MAX = 150mA

+3.3V_BUS

1.8V_POK

R307

1.8R

Use 3x1.8R
1206 1/2W

1.8V_POK

1.8V_EN

1%

1.8R

1.8R

1%

1.8R

NC

C312

0.1uF

NC

6.3V

DNI

R306 1%

R305

R304 1%

19

OUT

19,1

IN

B B

C C

1.8V_EN
LDO1_VIN
+5V

+5V

LDO1_VIN
+5V

C305

C306

10uF

1uF

6.3V

10V

MU300

1

POK

2

EN

3

VIN

4

CNTL5NC

UP0104PDC8

OVERLAP U300 AND MU300

U300

1

POK

2

EN

3

VIN

4

CNTL5NC

GS7133SO-R

8

GND

LDO1_FB

7

FB

+1.8V

6

VOUT

9

GND

NC

R302

C304

12.7K

33pF

1%

8

GND

LDO1_FB

7

FB

+1.8V

6

VOUT

9

GND

50V

R5

R301

10K
1%

R4

VOUT = Vref x (1 + R5/R4)

+1.8V

C301

C300

C303

10uF

10uF

0.1uF

6.3V

6.3V

6.3V

NCNC

+12V_BUS +5V +5V_VESA

MC78M05CDT

REG1

1

IN

C400

1uF
16V

3

OUT

GND

TAB

C425

1uF

2

16V

4

F400

1 2

200mA

24V

C401

1uF

6.3V

D D

MICRO-STAR INT'L CO.,LTD

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MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

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Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

1

2

3

4

5

6

7

Friday, August 16, 2013

MS-V305

18 SMALL RAIL REGULATORS

18 SMALL RAIL REGULATORS

18 SMALL RAIL REGULATORS

Sheet of

Sheet of

Sheet of

8

18 23

18 23

18 23

10

10

10

1

2

3

4

5

6

7

8

5%

UNNAMED_17_CAP_I206_A

N54311143

+12V_BUS

1

C1011

1uF

6.3V

+12V_BUS

1

C1632

1uF

6.3V

+12V_EXT_A

+12V_EXT_A

+12V_BUS_SOURCE2

+12V_EXT_A_SOURCE2

R1009

10K
5%

R1010 5%

UNNAMED_17_NPN_I205_C

Q1013

MMBT3904

2 3

R1012 5%

2,20

IN BACO MODE
TURN OFF
VDDC, VDDCI AND MVDD

R1635

10K
5%

R1611

UNNAMED_17_NPN_I104_C

Q1604

MMBT3904

2 3

R1652 5%

+12V_EXT_A INPUT

DUAL
FOOTPRINT

1 2

L1082

1 2

L1086

R1092 5%

R1093

MR1092

MR1093

IN

5.1K

5.1K

5.1K

5.1K

0.47uH

0.47uH

0R

0R

0R

0R

UNNAMED_17_NPN_I196_B

1

UNNAMED_17_NPN_I212_B

1

PX_EN

UNNAMED_17_NPN_I90_B

5%

1

UNNAMED_17_NPN_I92_B

1

+12V_EXT_A_SOURCE1

+12V_EXT_A_SOURCE2

+MVDD_SOURCE

5%

5%

5%

0.95V_EN

Q1014

MMBT3904

2 3

+3.3V_BUS

R1013

10K
5%

VDDC_EN

Q1016

MMBT3904

2 3

10K

1%

+12V_EXT_A_SOURCE1

+12V_EXT_A_SOURCE1

UNNAMED_17_NPN_I145_B

1

R1015

10K
1%

DNI

+12V_BUS_SOURCE1

Q1017

MMBT3904

2 3

+MVDDQ_COMP

+VDDCI_COMP

R1094 5%

R1095 5%

MR1094 5%

MR1095 5%

R1096

R1097

R1014

Q1605

MMBT3904

2 3

Q1630

MMBT3904

2 3

OUT

OUT

OUT

OUT

0R

0R

0R

0R

0R

0R

17

14

16

15

+VDDC_PHASE3_SOURCE

PHASE-3

+VDDC_PHASE12_SOURCE

5%

5%

PHASE-12

(19) POWER MANAGEMENT

+3.3V_BUS

BUS 12V and AUX A POWER UP SEQ

A A

+12V_EXT_A

J1000

1

+12V

2

+12V

3

+12V

C1003

10uF
16V

4

GND

6

POWER_HEADER

GND

Sense

SENSE_EXTA

5

B B

+12V_BUS

R1002

11.3K
1%

R1004

1K
1%

C1004

47pF
50V

C1007

47pF
50V

+3.3V_BUS

R1019

2.32K
1%

R1020

1K
1%

+12V_EXT_A

12V_BUS_UP

R1030

11.3K
1%

12V_EXTA_UP

R1040

1K
1%

3.3V_BUS_UP

+3.3V_BUS

R1031

5.11K
1%

1

2 3

N32204028

1

2 3

+12V_BUS

R1042

10K
1%

N32204141

1

2 3

CTF_OUT_B

Q1010

MMBT3904

Q1007

MMBT3904

Q1009

MMBT3904

N36200648

1

Q1008

MMBT3904

C1009

2 3

0.1uF
16V

1

Q1012

MMBT3904

PLACE CLOSE

C1010

2 3

0.1uF

TO ITS CTLR

16V

MR223 5%

R223 5%

PLACE CLOSE
TO ITS CTLR

0R

0R

DNI

R1008

10K
1%

1.8V_EN 1.8V_POK

OUT

+1.8V: >2.0V
+0.935V: FLOAT
+BIF_VDDC: FLOAT
+VDDC: >0.7V
+VDDCI: 0.4V ~ 2V
+MVDD: FLOAT

1,18

BUS RAILS (3.3V/12V UP) -> +1.8V -> 0.935V

POWER UP SEQUENCE

18

BIF_VDDC
VDDC -> VDDCI

MVDD

14

IN

IN

INTERNAL CTF LATCH - 1.8V VDDCT REQUIRED

CTF_OUT

20,21

IN

R221 5%

UNNAMED_17_NPN_I21_B

2.2K

1

Q210

MMBT3904

PLACE CLOSE

2 3

TO ITS CTLR

C C

+VDDC SOURCE

VDDC VOLTAGE CONTROL

OUT

MVDD VOLTAGE

RESISTOR TO SET
+MVDD OUTPUT VOLTAGE

RFB2

R710

5.9K
1%

+MVDDQ_FB

+VDDCI_FB

R810

24K
1%

15

+3.3V_BUS

R4112

R4107

R4108

R4109

10K
5%

14

OUT

14

OUT

14

OUT

14

OUT

14

OUT

14

OUT

14

OUT

R4114

D D

10K
5%

R4110

10K

10K

10K

5%

5%

5%

R4115

R4116

R4117

10K

10K

10K

5%

5%

5%

R4113

R4111

10K

10K

10K

5%

5%

5%

VDDC_VID7

R4100

VDDC_VID6

R4101

VDDC_VID5

R4102

VDDC_VID4

R4103

VDDC_VID3

R4104

VDDC_VID2

R4105

VDDC_VID1

R4106

R4119

R4120

R4118

10K

10K

10K

5%

5%

5%

GPIO_30_VDDC_VID7

0R

5%

GPIO_29_VDDC_VID6

0R

5%

GPIO_13_VDDC_VID5

0R

5%

GPIO_12_VDDC_VID4

0R

5%

GPIO_14_VDDC_VID3

0R

5%

GPIO_20_VDDC_VID2

0R

5%

GPIO_15_VDDC_VID1

0R

5%

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

R4085

39.2K
1%

1

Q4085

2 3

OUT

VDDCI VOLTAGE CONTROL

R4084

59K
1%

VDDCI_FB_VID0VDDCI_FB_VID1

2N7002E

2 3

16

1

Q4084

2N7002E

GPIO_11_PWRCNTL_3

GPIO_0_PWRCNTL_4

+12V_BUS

+3.3V_BUS

7

IN

7

IN

R450 5%

0R

MR450 5%

0R

+VDDCI/+MVDD SOURCE

+0.95_VIN

+12V_BUS_SOURCE2

+12V_EXT_A_SOURCE2

VDDC_POK

+12V_BUS INPUT

+12V_BUS

L1080

+12V_BUS

L1084

+3.3V_BUS

R1006

10K
5%

+3.3V_BUS

R1627

10K
5%

DUAL
FOOTPRINT

1 2

0.47uH

1 2

0.47uH

R1090

0R

R1091 5%

0R

MR1090 5%

0R

MR1091

0R

R1007

+12V_BUS_SOURCE1

+12V_BUS_SOURCE2

+VDDCI_SOURCE

5%

5%

5.1K

R16931K5%

PHASE-4

TH
TOROID

VOUT = VREF * (1+RFB1/RFB2)

MSI

MSI

MSI

1

2

3

4

5

6

7

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

MS-V305

19 POWER MANAGEMENT

19 POWER MANAGEMENT

19 POWER MANAGEMENT

8

Sheet of

Sheet of

Sheet of

19 23

19 23

19 23

10

10

10

1

FM1

FM2

OPT

OPT

F_PAD_X

F_PAD_X

FM5

FM6

OPT

OPT

F_PAD_X

F_PAD_X

FM4

FM3

OPT

OPT

F_PAD_X

F_PAD_X

FM7

FM8

OPT

OPT

F_PAD_X

F_PAD_X

A A

(20) MECHANICAL AND THERMAL MANAGEMENT

+1.8V

B202

120R

B B

CRITICAL TEMPERATURE FAULT

IF CRITICAL TEMPERATURE IS REACHED THIS WILL FORCE THE FAN TO RUN AT FULL
SPEED WHILE POWER IS REMOVED
THIS IS AN OPEN COLLECTOR SIGNAL. ACTIVE LEVEL IS HARD PULL DOWN TO GROUND.

7

1,2,20

HEATSINKS

1 2

IN

IN

HF1

HDMI

$$$$$$

HDMI_FEE

Y01-RHDMI03-000
VVVV305

PCIE

SPECIAL MECHANIC

MECH_PEX_BREAKOFF_RETENTION_B
DNI

_

SS1

STRUCTURE STICK

GPIO_19_CTF

PERSTB_BUF

2

No connected mounting pins

+TSVDD

C200

1uF

6.3V

R236 5%

MEC8

MEC_SCREW_HEX_JACK
COMMON

MEC10

MEC_SCREW_HEX_JACK
COMMON

DPLUS

DMINUS

TS_FDO

20,21

IN

CTF_THERM

CTF_TRIP

R214

100K
5%

R222

CTF BYPASS

8

1

7

W47

W46

AA46

0R

23456

3

HDMISCREW

MEC_SCREW_PH1
COMMON

MEC9

MEC_SCREW_HEX_JACK
COMMON

MEC11

MEC_SCREW_HEX_JACK
COMMON

GPU_DPLUS

GPU_DMINUS

GPIO_28_TS_FDO

7

OUT

+3.3V_BUS

23

1

Q209

MMBT3906

R240

20K
5%

1

C210

1uF

6.3V

2.2K

5%

UNNAMED_20_OFFPAGE_I129_A

MT204

MT203

1

8

NA

23456

7

ASSY201

BRACKET
DUAL

8020056000G

DP, HDMI, Stacked-DVI

Curacao Bracket
8020056000G

ASSY202

SCREW

7020003300G

21

IN

C203

0.0022uF
50V

21

IN

+3.3V_BUS

R200

20K
5%

DNI

PWM

R248

20K

5%

21

OUT

IN CASE OF
INTERNAL PU

R241

20K
5%

DNI

N65064848

R266

R213 5%

0R

R233

20K
5%

Q215

MMBT3904

2 3

NA

2.2K

5%

R242

1K
5%

8

7

For HDMI Connector

PCB1

AMD
PCB

PCB(109-C44557-00)

_

For DVI Connector

U1Q

PART 18 OF 18

AY53

TSVDD

C213

0.1uF

6.3V

AY51

TSVSS

BC43

NC_TSVSSQ

T
S
S

F
D
O

PITCAIRN

21

IN

UNNAMED_20_RES_I15_B

4.7K

R239 5%

47K

D200

1 2

BAT54KFILM

MT202

SHROUD HOLE

1

NA

23456

R247

20K
5%

DNI

TO MAXIMIZE FAN OUTPUT

DURING CTF TRIGGER

2

34567

PITCAIRN SOCKET PN 6090035000G

TO PREVENT
FAN RUNNING
FULL SPEED AT
POWER UP

CTF_FAN

1

BRACKET MT HOLES

MT200

NA

2 3

4

9

8

Q4510

MMBT3904

DNI

1

D201

PERSTB_BUF

1 2

1,2,20

IN

BAT54KFILM

Q254

2 3

Q206

MMBT3904

5

PX_EN

MR257

2,21,19,20

IN

1,2,20

PWM_B

1

Q203

MMBT3904

2 3

UNNAMED_20_NPN_I342_B

2 3

R263 5%

20K

DNI

UNNAMED_20_NPN_I271_B

1

R4514

5%

20K

MMBT3904

+3.3V_BUS

20K

5%

PERSTB_BUF

IN

OUT

R4517

5%

Q_OUT

PX_EN

FOR 4-WIRE FAN

FOR 2-WIRE FAN

20K
DNI

+3.3V_BUS

+12V_EXT_A

21

DNI

MQ4503

UNNAMED_20_NPN_I388_B

1

MR4515

R244

5.1K
5%

R2341K5%

R216

2.61K
1%

2 3

MMBT3904

100K

MC4506

R217 5%

DNI

MR4502

100K
5%

FAN_EN_C

1

UNNAMED_20_CAP_I387_A

1uF
16V

UNNAMED_20_NPN_I308_B

1

6

FAN_EN

MR259

20K

5%

+3.3V_BUS

7PR8

MC252

0.1uF

MU200

6.3V

Q_OUT

20

2

5

D

Q

Vcc

QB_OUT

20

1

3

C

Q

G

CL

NC7SZ74K8X

4

6

MC4507

0.1uF

+12V_BUS

5%

MR4516

20K

DNI

MQ4509

2 3

MMBT3904

1

PX_EN

R257 5%

2,19

IN

+3.3V_BUS

R228

10K
5%

DNI

2 3

10K

20K

1,2,20

IN

GPIO_6_TACH

7,21

OUT

Q214

MMBT3904

+12V_EXT_A

N65424297

23

PFB

1

Q201

C208

R226

MMBT3906

1uF

1M

16V

5%

N65424189

R211

10K
5%

UNNAMED_20_MOSN_I393_G

PERSTB_BUF

R235

3.83K
1%

MQ4508

2 3

R2321%1K

R202

1K
5%

MR260 5%

MR261 5%

2N7002E

+3.3V_BUS

UNNAMED_20_NPN_I360_B

1

+12V_EXT_A

R229

10K
5%

23

1

Q202

MMBT3906

Q_OUT_R

20K

1M

UNNAMED_20_CAP_I401_A

MC253

10uF

6.3V

R4502

20K
5%

Q250

MMBT3904

2 3

C252

0.1uF

6.3V

1

A

2

B

3

CLR

4

GND5Q

SN74LVC1G123DCT

FANOUT_N

R208

1M
5%

23

4

1

FAN_EN

U200

Rext/Cext

OVERLAP MJ200 and J200

Q205

BCP68

7

12V_FAN

R256

10K
5%

23

UNNAMED_20_MOSP_I250_G

1

R255

10K
5%

UNNAMED_20_NPN_I257_C

Q251

CTF_BACO

1

1

MMBT3904

5%

1

Q4509

R2611M5%

1 2

Q256

2 3

2 3

MMBT3904

2 3

MMBT3904

+3.3V_BUS

BAV99

3

D222

FAN_PWM
TACH
FANOUT_P

FANOUT_P
FANOUT_N

C209

R246

1uF

0R

16V

5%

DNI

DNI

C251

0.1uF
10V

+3.3V_BUS

Q_OUT_R

R260

20K

8

VCC

UNNAMED_20_74VC1G123_I358_REXT

7
6

Cext

C253

Q2_OUT

6.3V

10uF

FANOUT_P

C205

10uF
16V

FANOUT_N

+12V_BUS +12V_EXT_A

Q252

AO3415L

R264

HEADER IS 2MM
IT DOES NOT FOLLOW

2.54MM SPACING AS 4-PIN
PWM FAN SPECIFICATION

12

220R

MB200

R253

0R
5%

DNI

2.2K
5%

HEADER_1X4_SHROUDED

HEADER_1X2_SHROUDED

8

12

B200

220R

MC209

10uF
16V

0805

CTF_OUT

J200

4
3
2
1

MJ200

1
2

C C

CYPRESS_PRO_HEATSINK

Barts Pro Channel Fansink

7120E87000G

HS2A

1234567

8

CYPRESS_PRO_HEATSINK

HS2B

9

1011121314

17

15

CYPRESS_PRO_HEATSINK

HS2C

16

1819202122

23

CYPRESS_PRO_HEATSINK

HS2D

25

24

2627282930

32

31

D D

1

2

J13

341

2

impedence

PCIE

3

+MVDD +MVDD

J14

341

2

impedence

MEM_CLK

4

X_PIN1*2

RGB

5

J11

J12

X_PIN1*2

MEM DATA Signal end

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

6

7

MS-V305

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

20 MECHANICAL AND THERMAL

20 MECHANICAL AND THERMAL

20 MECHANICAL AND THERMAL

Friday, August 16, 2013

Friday, August 16, 2013

Friday, August 16, 2013

Sheet ofDate:

20 23

Sheet ofDate:

20 23

Sheet ofDate:

20 23

8

10

10

10

1

2

3

4

5

6

7

8

(21) DEBUG CIRCUITS

A A

JTAG

U1R

PART 1 OF 18

J
T
A
G

FOR ALL BRING UP BOARDS DNI R4000 AND STUFF R4003
OTHERWISE THE TAPC WILL BE STUCK IN TEST-LOGIG-RESET

AND BE USELESS SINCE TRSTb IS NOT ON THE CONNECTOR

B B

PITCAIRN

JTAG_TDO

JTAG_TDI

JTAG_TMS

JTAG_TCK

TESTEN

JTAG_TRSTB

AW43
BA42
AY43
BB42
AW48
BB41

JTAG_TDO

JTAG_TDI

JTAG_TMS

JTAG_TCK

JTAG_TRSTB

J4004

HEADER_RECEPT_2X4

7 8
5 6
3 4
1 2

+3.3V_BUS

+3.3V_BUS

1K

5%R4003

DNI

1K

5%R4000

+3.3V_BUS

R4001

1K
5%

DNI

R4002

1K
5%

LM96163 FOR BACKUP THERMAL CONTROL

+3.3V_BUS

R38

4.7K
5%

7

IN

DDCVGADATA

7

BI

GPIO_6_TACH

20,7

IN

GPIO_17_THERM_INT

7

OUT

TP4003

TP4004

R39

R40

4.7K

10K

5%

5%

C4009

0.01uF
10V

DNI

TACH CONNECTION IS FOR TESTING
AND RPM MEASUREMENT ONLY

+3.3V_BUS

C4007

1uF

6.3V

U4003

10

SMBCLK

9

SMBDAT

8

TACH

THERM_INTB

0R

5%R43

7

ALERT

6

GND

LM96163CISD

TCRITBTESTEN

1

TCRIT

2

VDD

3

D+

4

D-

LM_PWM PWM

5

PWN

11

THMPAD

CTF_THERMDDCVGACLK

0R

5%R4016

GPU_DPLUS

GPU_DMINUS

33R

5%R4015

DNI

20

OUT

20

IN

20

IN

20

OUT

J4010

VDDC_VSEN

1

VDDC_VRTN

G1

2
3

G2

RF_CONN

12,14

IN

12,14

CTF_OUT

20,19

IN

PWM_B

20

IN

C C

LED GREEN "ON" SHOWS BACO MODE

2,21,19,20

IN

D D

1

2

SW4002A

1 4

Slide

SW4002B

2 3

Slide

PX_EN

R4025

BACO_LED_ON

5%

1K

BYPASS CTF

MAXIMIZE FAN

D4001

BACO_LED

1

Q4001

MMBT3904

2 3

3

1 2

GREEN

BACO_LED_PWR

+3.3V_BUS

1%

499R

R4026

4

IN

5

VDDCI_SV

IN

6

J4011

1

G1

2
3

G2

RF_CONN

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-V305

MS-V305

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, August 16, 2013

Date:

Friday, August 16, 2013

Date:

7

Friday, August 16, 2013

MS-V305

21 DEBUG CIRCUITS

21 DEBUG CIRCUITS

21 DEBUG CIRCUITS

Sheet of

Sheet of

Sheet of

8

21 23

21 23

21 23

10

10

10

1

8

8

8

2

7

7

7

3

6

6

6

4

5

6

345

345

345

7

2

2

2

8

1

1

1

MEMORY CHANNEL A&B

A A

GDDR5 4pcs 64M/32Mx32

MEMORY CHANNEL C&D

GDDR5 4pcs 64M/32Mx32

DD

DD

DD

EXTERNAL CONNECTOR

+12V_EXT_A

JTAG/I2C

DEBUG

1x

POWER REGULATORS

FROM +12V_BUS, +12V_EXT_A

+VDDC, +VDDCI, +MVDD, +5V, +0.935V, FAN

B B

C

C

C

C C

From +3.3V_BUS

+1.8V, +BIF_VDDC, +3.3V_DP, VDDR3

From +VDDC (SMPS)

VDDC

From +VDDCI (SMPS)

VDDCI

From +MVDD (SMPS)

VDDR1, MVDDQ/C

From +1.8V (LDO)

PCIE_VDDR, VDDR4, DPLL_PVDD, SPLL_PVDD
MPLL_PVDD, XTAL_VDDR, VDD1DI, AVDD
DP_VDDR, TSVDD

From +0.935V (SMPS)

PCIE_VDDC, DPLL_VDDC, SPLL_VDDC, DP_VDDC
BIF_VDDC

From +BIF_VDDC (SMPS)

BIF_VDDC

CROSS FIRE
INTERLINK

FAN

REGULATOR HOT

DYNAMIC POWER MANAGEMENT

POWER DELIVERY

STRAPS

VBIOS DVI-I

SPEED CONTROL

TEMPERATURE
SENSE

INTERRUPT

TEMP SENSING

BUILT-IN PWM

JTAG

CROSSFIRE

DVOCLK
DVPCNTL_[0..2]
DVPDATA[11:0]

GPIO[2]
GENERIC D

MLPS
GPIO

ROM

THERM

DDCVGA

GPIO17
GPIO6_TACH

D+/D-

TS_FDO

GPIO5

VDDC GPIO20/15
VDDCI GPIO11/0

CH A/B/C/D

TMDPC

DDC1 AUX1

HPD4

TMDPD

DDC2 AUX2

TMDPAB

DDC4

LVTMDPEF

CRTDAC

DDCAUX6

HPD5

HPD1

HPD6

AC COUPLING CAPS

AC COUPLING CAPS
TERMINATIONS

AC COUPLING CAPS
TERMINATIONS

AC COUPLING CAPS

TERMINATIONS

RGB FILTERS

DP

CONNECTOR

HDMI

CONNECTOR

+5V_VESA

CONNECTOR

DL-DVI

+5V_VESA

DVI-I

CONNECTOR

DL-DVI

+3.3V_DP

+5V_VESA

TOP

BOTTOM

C

C

C

BB

BB

BB

PITCAIRN

POWER SEQUENCING
CIRCUIT

BACO

CRITICAL TEMPERATURE

PX_EN

GPIO19_CTF

L3

XO_IN2

XO_IN

XTALIN

PCI-EXPRESS

XTALOUT

100MHz

CLOCK

27MHz

CRYSTAL

PCI-E Curacao PRO GDDR5 8pcs x32

DP HDMI SDVI FH 6L(CR)

+12V_BUS

+3.3V_BUS

A

A

A

D D

8

8

8

1

7

7

7

2

PCI-EXPRESS BUS

6

6

6

3

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

<ADDR1>

<ADDR1>

<ADDR1>
<ADDR2>

<ADDR2>

<ADDR2>
<ADDR3>

<ADDR3>

<ADDR3>

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

SHEET:

SHEET:

SHEET:

Wed Jul 24 07:55:42 2013 <REV>

Wed Jul 24 07:55:42 2013 <REV>

DATE:

DATE:

DATE:

SHEET NUMBER:

SHEET NUMBER:

SHEET NUMBER:

DOCUMENT NUMBER:

DOCUMENT NUMBER:

DOCUMENT NUMBER:

5

5

5

4

4

4

4

5

Wed Jul 24 07:55:42 2013 <REV>

22 23

22 23

22 23

OF

OF

OF

105_C630XX_01

105_C630XX_01

105_C630XX_01

3

3

3

6

REV:

REV:

REV:

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

<COPYRIGHT>

<COPYRIGHT>

<COPYRIGHT>

C

C

C

Advanced Micro Devices

Advanced Micro Devices

Advanced Micro Devices

This AMD Board schematic and design is the exclusive property of AMD, and

This AMD Board schematic and design is the exclusive property of AMD, and

This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD

is provided only to entities under a non-disclosure agreement with AMD

is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly

for evaluation purposes. Further distribution or disclosure is strictly

for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than

prohibited. Use of this schematic and design for any purpose other than

prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.

evaluation requires a Board Technology License Agreement with AMD.

evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this

AMD makes no representations or warranties of any kind regarding this

AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty

schematic and design, including, not limited to, any implied warranty

schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims

of merchantability or fitness for a particular purpose, and disclaims

of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the

responsibility for any consequences resulting from use of the

responsibility for any consequences resulting from use of the
information included herein.

information included herein.

information included herein.

TITLE:

TITLE:

TITLE:

2

2

2

7

<TITLE>

<TITLE>

<TITLE>

1

1

1

8

A

A

A

1

8

8

8

TITLE:

TITLE:

AMD

AMD

AMD

REVISION HISTORY

REVISION HISTORY

REVISION HISTORY

SCH

SCH

SCH

PCB

PCB

PCB

Date

Date

Date

Rev

Rev

Rev

Rev

Rev

Rev

A A

D D

D D

D D

0

00A

1 00B

200

01/07/2010

10/17/2012

05/31/2013

TITLE:

No schematic change. Just add mouse bit hole on PCB

No schematic change.

2

ENGINEER:

ENGINEER:

ENGINEER:

NOTES:

NOTES:

NOTES:

3

6

6

6

DOCUMENT NUMBER: SHEET NUMBER:

DOCUMENT NUMBER: SHEET NUMBER:

DOCUMENT NUMBER: SHEET NUMBER:

NOTEci20313

NOTE

NOTE

7

7

7

<TITLE>

<TITLE>

<TITLE>

<ENGINEER>

<ENGINEER>

<ENGINEER>

4

54332

54332

54332

105_C630XX_01

105_C630XX_01

105_C630XX_01

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD

This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD

This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than

for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than

for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this

evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this

evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims

schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims

schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the information included herein.

responsibility for any consequences resulting from use of the information included herein.

REVISION DESCRIPTON

REVISION DESCRIPTON

REVISION DESCRIPTON

responsibility for any consequences resulting from use of the information included herein.

5

DATE:

DATE:

DATE:

<COPYRIGHT>

<COPYRIGHT>

<COPYRIGHT>

C

C

C

Advanced Micro Devices

Advanced Micro Devices

Advanced Micro Devices

6

7

2323 Wed Jul 24 07:55:42 2013

2323 Wed Jul 24 07:55:42 2013

2323 Wed Jul 24 07:55:42 2013

OF

OF

OF

<ADDR1>

<ADDR1>

<ADDR1>
<ADDR2>

<ADDR2>

<ADDR2>
<ADDR3>

<ADDR3>

<ADDR3>

8

1

1

1

<REV>

<REV>

<REV>

REV:

REV:

REV:

B B

C

C

C

B B

B B

B B

C C

A

A

A

D D

C

C

C

A

A

A

8

8

8

1

76

76

76

2

3

5

5

5

4

4

4

4

5

6

2

2

2

7

1

1

1

8