MSI MS-V187 Schematic 10
A B C D E F G H
G94-P562-A00 - GDDR3, DVI/VGA + DVI/VGA
1
2
3
4
VARIANT ASSEMBLY
SKU
B
BASE
1
sku0000
2
<UNDEFINED
3
<UNDEFINED>
4
<UNDEFINED>
5
<UNDEFINED>
6
<UNDEFINED>
7
<UNDEFINED>
8
<UNDEFINED>
9
<UNDEFINED>
10
<UNDEFINED>
11
<UNDEFINED>
12
<UNDEFINED>
13
<UNDEFINED>
14
<UNDEFINED>
15
<UNDEFINED>
Table of Contents:
Page 1: Overview
Page 2: PCI Express
Page 3: MEMORY: GPU Partition A/B
Page 4: MEMORY: GPU Partition C/D
Page 5: FBA Partition
Page 6: FBA Partition Decoupling
Page 7: FBB Partition
Page 8: FBB Partion Decoupling
Page 9: FBC Partition
Page 10: FBC Partition Decoupling
Page 11: FBD Partition
Page 12: FBD Partition Decoupling
Page 13: FB Net Properties
Page 14: DACA Interface
Page 15: DACC Interface
Page 16: IFP A/B Interface -- DVI Connector South
Page 17: IFP C/D Interface -- DVI Connector MID
Page 18: IFP E/F Interface -- Unused
Page 19: DACB Unused
Page 20: MIO A/B Interface
Page 21: MISC: GPIO, I2C, ROM, HDCP, and XTAL
Page 22: Strap Configuration
Page 23: PWR and GND Signals
Page 24: NVVDD and FBVDDQ Decoupling
Page 25: SPDIF Input, Backdrive Protection, and IFP_IOVDD Power Supply
Page 26: PS I: 3V3, 12V, and 12V_EXT Power Supply Filter
Page 27: PS II: IFP_PLLVDD, 2V5, 5V, and DDC_5V Power Supply
Page 28: PS III: FBVDDQ Power Supply
Page 29: PS IV: NVVDDV
Page 30: BLANK
Page 31: Fan Connector
Page 32: Thermal, Mechanical, and Bracket
NVPN
600-10562-base-000
600-10562-0000-000
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
G94-400 625MHz/900MHz 512MB 16Mx32 BGA136 GDDR3, DVI-I-DL+DVI-I-DL
<UNDEFINED
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED><UNDEFINED>
<UNDEFINED>
REVISION HISTORY:
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Overview
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
5
PAGEID
DATE
30-DEC-2008
HFDBA
A B C D E F G H
Page2: PCI Express
12V
C799
C799
1UF
1UF
25V
25V
10%
10%
X7R
X7R
3V3
0805
0805
COMMON
COMMON
C785
C785
C784
1
C784
.1UF
.1UF
4.7UF
4.7UF
16V
16V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X7R
X7R
0603
0603
0402
0402
COMMON
COMMON
COMMON
COMMON
COMMON
GND
COMMON
2
GND
3V3_AUX
C40
.1UF
C40
.1UF
16V
0402
16V
0402
10%
10%
X7R
X7R
SNN_PE_PRSNT2_A
SNN_PE_RSVD1
SNN_PE_PRSNT2_B
SNN_PE_RSVD2
SNN_PE_RSVD3
SNN_PE_RSVD4
C798
C798
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
SNN_PE_PRSNT2_C
SNN_PE_RSVD5
3
PEX_PRSNT*
SNN_PE_RSVD6
SNN_PE_RSVD7
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
CN2
CN2
CON_X16
CON_X16
COMMON
COMMON
SMCLK
SMDAT
PERST
REFCLK
REFCLK
PERP0
PERN0
PETP0
PETN0
PERP1
PERN1
PETP1
PETN1
PERP2
PERN2
PETP2
PETN2
PERP3
PERN3
PETP3
PETN3
PERP4
PERN4
PETP4
PETN4
PERP5
PERN5
PETP5
PETN5
PERP6
PERN6
PETP6
PETN6
PERP7
PERN7
PETP7
PETN7
PERP8
PERN8
PETP8
PETN8
PERP9
PERN9
PETP9
PETN9
PERP10
PERN10
PETP10
PETN10
PERP11
PERN11
PETP11
PETN11
PERP12
PERN12
PETP12
PETN12
PERP13
PERN13
PETP13
PETN13
PERP14
PERN14
PETP14
PETN14
PERP15
PERN15
PETP15
PETN15
PEX_TRST*
B9
PEX_TCLK
A5
PEX_TDI
A6
PEX_TDO
A7
PEX_TMS
A8
PEX_SMCLK
B5
PEX_SMDAT
B6
SNN_PEX_WAKE*
B11
WAKE
PEX_RST*
A11
PEX_REFCLK
A13
PEX_REFCLK*
A14
PEX_TXX0
A16
PEX_TXX0*
A17
PEX_RX0
B14
PEX_RX0*
B15
PEX_TXX1
A21
PEX_TXX1*
A22
PEX_RX1
B19
PEX_RX1*
B20
PEX_TXX2
A25
PEX_TXX2*
A26
PEX_RX2
B23
PEX_RX2*
B24
PEX_TXX3
A29
PEX_TXX3*
A30
PEX_RX3
B27
PEX_RX3*
B28
PEX_TXX4
A35
PEX_TXX4*
A36
PEX_RX4
B33
PEX_RX4*
B34
PEX_TXX5
A39
PEX_TXX5*
A40
PEX_RX5
B37
PEX_RX5*
B38
PEX_TXX6
A43
PEX_TXX6*
A44
PEX_RX6
B41
PEX_RX6*
B42
PEX_TXX7
A47
PEX_TXX7*
A48
PEX_RX7
B45
PEX_RX7*
B46
PEX_TXX8
A52
PEX_TXX8*
A53
PEX_RX8
B50
PEX_RX8*
B51
PEX_TXX9
A56
PEX_TXX9*
A57
PEX_RX9
B54
PEX_RX9*
B55
PEX_TXX10
A60
PEX_TXX10*
A61
PEX_RX10
B58
PEX_RX10*
B59
PEX_TXX11
A64
PEX_TXX11*
A65
PEX_RX11
B62
PEX_RX11*
B63
PEX_TXX12
A68
PEX_TXX12*
A69
PEX_RX12
B66
PEX_RX12*
B67
PEX_TXX13
A72
PEX_TXX13*
A73
PEX_RX13
B70
PEX_RX13*
B71
PEX_TXX14
A76
PEX_TXX14*
A77
PEX_RX14
B74
PEX_RX14*
B75
PEX_TXX15
A80
PEX_TXX15*
A81
PEX_RX15
B78
PEX_RX15*
B79
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
OUT
OUT
C771
0402
0402
X7R
X7R
C761
0402
0402
X7R
X7R
C758 .1UF
C758 .1UF
0402
0402
X7R
X7R
C744
C744
0402
0402
X7R
X7R
C729
C729
0402
0402
X7R
X7R
C716
C716
X7R
X7R
C696
C696
0402
0402
X7R
X7R
C677
C677
0402
0402
X7R
X7R
C650
C650
0402
0402
X7R
X7R
C632
C632
0402
0402
X7R
X7R
C617
C617
0402
0402
X7R
X7R
C609
C609
0402
0402
X7R
X7R
C601
C601
0402
0402
X7R
X7R
C599
C599
0402
0402
X7R
X7R
C595
C595
0402
0402
X7R
X7R
C591
C591
0402
0402
X7R
X7R
R644
R644
0
0
5%
5%
0402
0402
COMMON
COMMON
21
21
OUT
.1UFC771
.1UF
C762
C762
16V
16V
10%
10%
0402
0402
.1UFC761
.1UF
C760
C760
16V
16V
10%
10%
C755
C755
16V
16V
10%
10%
.1UF
.1UF
C739
C739
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C725
C725
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C711
C711
16V0402
16V0402
10%
10%
0402
0402
.1UF
.1UF
C693
C693
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C667
C667
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C647
C647
16V
16V
10%
10%
.1UF
.1UF
C627
C627
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C615
C615
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C607
C607
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C600
C600
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C598
C598
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C594
C594
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C588
C588
16V
16V
10%
10%
0402
0402
B1
+12V
B2
+12V
A2
+12V
A3
+12V
B3
+12V/RSVD
B8
+3V3
A9
+3V3
A10
+3V3
B10
+3V3AUX
A1
PRSNT1
B17
PRSNT2
B12
RSVD
B4
GND
A4
GND
B7
GND
A12
GND
B13
GND
A15
GND
B16
GND
B18
GND
A18
GND
GND
B31
PRSNT2
A19
RSVD
B30
RSVD
A32
RSVD
A20
GND
B21
GND
B22
GND
A23
GND
A24
GND
B25
GND
B26
GND
A27
GND
A28
GND
B29
GND
A31
GND
B32
GND
B48
PRSNT2
A33
RSVD
A34
GND
B35
GND
B36
GND
A37
GND
A38
GND
B39
GND
B40
GND
A41
GND
A42
GND
B43
GND
B44
GND
A45
GND
A46
GND
B47
GND
B49
GND
A49
GND
GND
B81
PRSNT2
A50
RSVD
B82
RSVD
A51
GND
B52
GND
B53
GND
A54
GND
A55
GND
B56
GND
B57
GND
A58
GND
A59
GND
B60
GND
B61
GND
A62
GND
A63
GND
B64
GND
B65
GND
A66
GND
A67
GND
B68
GND
B69
GND
A70
GND
A71
GND
B72
GND
B73
GND
A74
GND
A75
GND
B76
GND
B77
GND
A78
GND
A79
GND
B80
GND
A82
GND
GND
END OF X1
END OF X1
END OF X4
END OF X4
END OF X8
END OF X8
END OF X16
END OF X16
TRST* JTAG1
TCLK JTAG2
TDI JTAG3
TDO JTAG4
TMS JTAG5
2,25
.1UF
.1UF
16V
16V
0402
0402
.1UF
.1UF
16V0402
16V0402
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V0402
16V0402
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
SNN_PEX_CLKREQ*
10%
10%
COMMON
COMMON
X7R
X7R
.1UF
.1UF
10%
10%
16V
16V
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
COMMON
COMMON
PEX_TX0
PEX_TX0*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
R639
0402 COMMON
0402 COMMON
R637
0402 COMMON
0402 COMMON
R643
0402 COMMON
0402 COMMON
R645
R645
0402
0402
R648 0
R648 0
0402
0402
PEX_TX1
PEX_TX1*
05%R639
0
JTAG_TRST*
5%
05%R637
0
JTAG_TCLK
5%
0R643
0
JTAG_TDI
5%
5%
0
0
JTAG_TDO
COMMON
COMMON
5%
5%
JTAG_TMS
COMMON
COMMON
5%
5%
G1A
G1A
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
1/19 PCI_EXPRESS
1/19 PCI_EXPRESS
AW10
PEX_RST
AY10
PEX_CLKREQ
AW11
PEX_REFCLK
AW12
PEX_REFCLK
AU13
PEX_TX0
AV13
PEX_TX0
AY12
PEX_RX0
BA12
PEX_RX0
AW13
PEX_TX1
AW14
PEX_TX1
BB12
PEX_RX1
BB13
PEX_RX1
AW15
PEX_TX2
AV15
PEX_TX2
BA13
PEX_RX2
AY13
PEX_RX2
AV16
PEX_TX3
AW16
PEX_TX3
AY15
PEX_RX3
BA15
PEX_RX3
AW17
PEX_TX4
AW18
PEX_TX4
BB15
PEX_RX4
BB16
PEX_RX4
AV18
PEX_TX5
AU18
PEX_TX5
BA16
PEX_RX5
AY16
PEX_RX5
AV19
PEX_TX6
AW19
PEX_TX6
AY18
PEX_RX6
BA18
PEX_RX6
AW20
PEX_TX7
AW21
PEX_TX7
BB18
PEX_RX7
BB19
PEX_RX7
AV21
PEX_TX8
AU21
PEX_TX8
BA19
PEX_RX8
AY19
PEX_RX8
AV22
PEX_TX9
AW22
PEX_TX9
AY21
PEX_RX9
BA21
PEX_RX9
AW23
PEX_TX10
AW24
PEX_TX10
BB21
PEX_RX10
BB22
PEX_RX10
AV24
PEX_TX11
AU24
PEX_TX11
BA22
PEX_RX11
AY22
PEX_RX11
AU25
PEX_TX12
AV25
PEX_TX12
AY24
PEX_RX12
BA24
PEX_RX12
AW25
PEX_TX13
AW26
PEX_TX13
BB24
PEX_RX13
BB25
PEX_RX13
AW27
PEX_TX14
AV27
PEX_TX14
BA25
PEX_RX14
AY25
PEX_RX14
AU27
PEX_TX15
AT27
PEX_TX15
AY27
PEX_RX15
BA27
PEX_RX15
C GE
3V3
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
VDD33
VDD33
VDD33
VDD33
VDD33
VDD_SENSE
GND_SENSE
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
PEX_PLLVDD
TESTMODE
PEX_CAL_PD_VDDQ
PEX_CAL_PU_GND
PEX_TERMP
ASSEMBLY
PAGE DETAIL
J501
J501
FEMALE
FEMALE
1.274MM
1.274MM
0
0
CON_HDR_002X004_TH
CON_HDR_002X004_TH
COMMON
COMMON
TMS2TRST*
1
TDI4GND
3
KEY
KEY
VCC
5
TDO8TCK
7
AT18
AT24
AT25
AU15
AU16
AU19
AU22
AM17
AM18
AM19
AM20
AM24
AM25
AM26
AM27
AM28
AP18
AP19
AP21
AP22
AP24
AP25
AP27
AR15
AR16
AR18
AR19
AR21
AR22
AR24
AR25
AR27
AT15
AT16
AT19
AT21
AT22
L11
L12
L13
M11
N11
NVVDD_SENSE_GPU
AJ22
SNN_NVVDD_GND_SENSE_GPU
AJ21
PEX_PLL_CLK_OUT
AP16
PEX_PLL_CLK_OUT*
AP17
12MIL
PEX_PLLVDD
AM16
GPU_TESTMODE
BB27
5MIL
PEX_CAL_PD_VDDQ
AM21
PEX_CAL_PU_GND
AM22
5MIL
PEX_TERMP
AM23
5MIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PCI Express
3V3
R642
R642
10K
10K
5%
5%
0402
0402
COMMON
COMMON
GND
Place near balls
C646
C646
C645
C645
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C657
C657
C673
C673
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
Matching Rule of Thumb
4 inch from Top of Gold Fingers to GPU
*2 inch Lane to Lane Skew
*No real Skew rule, but reducing the skew will minimize latency
Place near balls
R585
04025%COMMON
04025%COMMON
R587
R587
0402
0402
C710
C710
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
SHOULD BE PLACED ON THE BOTTOM LAYER
SHOULD BE PLACED ON THE BOTTOM LAYER
R592
R592
10KR585
10K
1%
1%
R649
R649
10K
10K
5%
5%
0402
0402
COMMON
COMMON
2.49K
2.49K
COMMON
COMMON
R638
R638
180
180
5%
5%
0402
0402
COMMON
COMMON
R636
R636
R635
R635
10K
10K
270
270
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND
C651
C651
C685
C685
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
C663
C663
C664
C664
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
VDD33
C699
C699
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
OUT
200
200
COMMON0402
COMMON0402
5%
5%
C675
C675
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R589 2.49K
R589 2.49K
COMMON0402
COMMON0402
1%
1%
R588
2.49KR588
2.49K
COMMON
0402
COMMON
0402
1%
1%
2,29
C687
C687
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
PEX_VDD
GND
JTAG
OUT
OUT
OUT
IN
OUT
C676
C676
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C690
C690
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C702
C702
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
GND
C666
C666
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C689
C689
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C662
C662
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
PEX_REFCLK
OUT
PEX_REFCLK*
OUT
2,21
2,21
2,21
2,21
2,21
PEX_VDD
3V3
C700
C700
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
PEX_VDD
LB505
10nHLB505
10nH
COMMONIND_SMD_0402
COMMONIND_SMD_0402
C669
C669
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
2,25
2,29
PEX_TXX0
OUT
PEX_TXX0*
OUT
PEX_TXX1
OUT
PEX_TXX1*
OUT
PEX_TXX2
OUT
PEX_TXX2*
OUT
PEX_TXX3
OUT
PEX_TXX3*
OUT
PEX_TXX4
OUT
PEX_TXX4*
OUT
PEX_TXX5
OUT
PEX_TXX5*
OUT
PEX_TXX6
OUT
PEX_TXX6*
OUT
PEX_TXX7
OUT
PEX_TXX7*
OUT
PEX_TXX8
OUT
PEX_TXX8*
OUT
PEX_TXX9
OUT
PEX_TXX9*
OUT
PEX_TXX10
OUT
PEX_TXX10*
OUT
PEX_TXX11
OUT
PEX_TXX11*
OUT
PEX_TXX12
OUT
PEX_TXX12*
OUT
PEX_TXX13
OUT
PEX_TXX13*
OUT
PEX_TXX14
OUT
PEX_TXX14*
OUT
PEX_TXX15
OUT
PEX_TXX15*
OUT
PEX_RX0
OUT
PEX_RX0*
OUT
PEX_RX1
OUT
PEX_RX1*
OUT
PEX_RX2
OUT
PEX_RX2*
OUT
PEX_RX3
OUT
PEX_RX3*
OUT
PEX_RX4
OUT
PEX_RX4*
OUT
PEX_RX5
OUT
PEX_RX5*
OUT
PEX_RX6
OUT
PEX_RX6*
OUT
PEX_RX7
OUT
PEX_RX7*
OUT
PEX_RX8
OUT
PEX_RX8*
OUT
PEX_RX9
OUT
PEX_RX9*
OUT
PEX_RX10
OUT
PEX_RX10*
OUT
PEX_RX11
OUT
PEX_RX11*
OUT
PEX_RX12
OUT
PEX_RX12*
OUT
PEX_RX13
OUT
PEX_RX13*
OUT
PEX_RX14
OUT
PEX_RX14*
OUT
PEX_RX15
OUT
PEX_RX15*
OUT
PEX_TX0
OUT
PEX_TX0*
OUT
PEX_TX1
OUT
PEX_TX1*
OUT
PEX_TX2
OUT
PEX_TX2*
OUT
PEX_TX3
OUT
PEX_TX3*
OUT
PEX_TX4
OUT
PEX_TX4*
OUT
PEX_TX5
OUT
PEX_TX5*
OUT
PEX_TX6
OUT
PEX_TX6*
OUT
PEX_TX7
OUT
PEX_TX7*
OUT
PEX_TX8
OUT
PEX_TX8*
OUT
PEX_TX9
OUT
PEX_TX9*
OUT
PEX_TX10
OUT
PEX_TX10*
OUT
PEX_TX11
OUT
PEX_TX11*
OUT
PEX_TX12
OUT
PEX_TX12*
OUT
PEX_TX13
OUT
PEX_TX13*
OUT
PEX_TX14
OUT
PEX_TX14*
OUT
PEX_TX15
OUT
PEX_TX15*
OUT
PEX_PLL_CLK_OUT
OUT
PEX_PLL_CLK_OUT*
OUT
PEX_RST*
OUT
PEX_PRSNT*
OUT
GPU_TESTMODE
OUT
NVVDD_SENSE_GPU
OUT
VOLTAGENET MAX_CURRENT
PEX_PLLVDD
IN
1.1V
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
NAME
NV_IMPEDANCE DIFFPAIRNV_CRITICALNET
1 PEX_REFCLK
90DIFF
1 PEX_REFCLK
90DIFF
1
90DIFF
90DIFF
1
90DIFF
1 PEX_TXX1
90DIFF
1 PEX_TXX2
90DIFF
1
90DIFF
1
90DIFF
1 PEX_TXX3
90DIFF
1
90DIFF
1 PEX_TXX4
90DIFF
1 PEX_TXX5
90DIFF
1
90DIFF
1 PEX_TXX6
90DIFF
1
90DIFF
1 PEX_TXX7
90DIFF
1 PEX_TXX7
90DIFF
1 PEX_TXX8
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1 PEX_TXX10
90DIFF
1
90DIFF
1
90DIFF
90DIFF
1 PEX_TXX12
90DIFF
1 PEX_TXX13
90DIFF
1 PEX_TXX13
90DIFF
1 PEX_TXX14
90DIFF
1
90DIFF
1 PEX_TXX15
90DIFF
1
90DIFF
1 PEX_RX0
90DIFF
1 PEX_RX0
90DIFF
1
90DIFF
1 PEX_RX1
90DIFF
1 PEX_RX2
90DIFF
1 PEX_RX2
90DIFF
1
90DIFF
1 PEX_RX3
90DIFF
1 PEX_RX4
90DIFF
1 PEX_RX4
90DIFF
1
90DIFF
1 PEX_RX5
90DIFF
1 PEX_RX6
90DIFF
1
90DIFF
1 PEX_RX7
90DIFF
1
90DIFF
1 PEX_RX8
90DIFF
1 PEX_RX8
90DIFF
1 PEX_RX9
90DIFF
90DIFF
1 PEX_RX10
90DIFF
90DIFF
1 PEX_RX11
90DIFF
1 PEX_RX11
90DIFF
1 PEX_RX12
90DIFF
1 PEX_RX12
90DIFF
1 PEX_RX13
90DIFF
1 PEX_RX13
90DIFF
1 PEX_RX14
90DIFF
1 PEX_RX14
90DIFF
1 PEX_RX15
90DIFF
1 PEX_RX15
90DIFF
1 PEX_TX0
90DIFF
1 PEX_TX0
90DIFF
1 PEX_TX1
90DIFF
1 PEX_TX1
90DIFF
1
90DIFF
1 PEX_TX2
90DIFF
1
90DIFF
1 PEX_TX3
90DIFF
1
90DIFF
1 PEX_TX4
90DIFF
1 PEX_TX5
90DIFF
1 PEX_TX5
90DIFF
90DIFF
90DIFF
1 PEX_TX7
90DIFF
1
90DIFF
1 PEX_TX8
90DIFF
90DIFF
1
90DIFF
1 PEX_TX9
90DIFF
90DIFF
1 PEX_TX10
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1 PEX_PLL_CLK_OUT
90DIFF
1
90DIFF
3
50OHM
3
50OHM
3
50OHM
5MIL
600-10562-base-000 A
PEX_TXX0
PEX_TXX01
PEX_TXX1
PEX_TXX2
PEX_TXX3
PEX_TXX4
PEX_TXX5
PEX_TXX6
PEX_TXX8
PEX_TXX9
PEX_TXX9
PEX_TXX10
PEX_TXX11
PEX_TXX11
PEX_TXX121
PEX_TXX14
PEX_TXX15
PEX_RX1
PEX_RX3
PEX_RX5
PEX_RX6
PEX_RX7
PEX_RX91
PEX_RX101
PEX_TX2
PEX_TX3
PEX_TX4
PEX_TX61
PEX_TX61
PEX_TX7
PEX_TX81
PEX_TX9
PEX_TX101
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX131
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15
PEX_PLL_CLK_OUT
MIN_WIDTH
12MIL0.16A
PAGEID
DATE
HFDBA
1
2
3
4
5
30-DEC-2008
www.vinafix.vn
A B C D E F G H
Page3: MEMORY: GPU Partition A/B
1
5,13
2
3
4
5
FBA_D[63..0]
BI
5,13
5,13
FBA_DQM[7..0]
OUT
FBA_DQS_WP[7..0]
OUT
5,13
FBA_DQS_RN[7..0]
IN
FBVDDQ
R572
R572
511
511
1%
1%
13
0402
0402
COMMON
COMMON
R573
R573
C603
C603
1.3K
1.3K
.1UF
.1UF
16V
16V
1%
1%
0402
0402
10%
10%
COMMON
COMMON
X7R
X7R
0402
0402
COMMON
COMMON
FBA_D0
0
FBA_D1
1
FBA_D2
2
FBA_D3
3
FBA_D4
4
FBA_D5
5
FBA_D6
6
FBA_D7
7
FBA_D8
8
FBA_D9
9
FBA_D10
10
FBA_D11
11
FBA_D12
12
FBA_D13
13
FBA_D14
14
FBA_D15
15
FBA_D16
16
FBA_D17
17
FBA_D18
18
FBA_D19
19
FBA_D20
20
FBA_D21
21
FBA_D22
22
FBA_D23
23
FBA_D24
24
FBA_D25
25
FBA_D26
26
FBA_D27
27
FBA_D28
28
FBA_D29
29
FBA_D30
30
FBA_D31
31
FBA_D32
32
FBA_D33
33
FBA_D34
34
FBA_D35
35
FBA_D36
36
FBA_D37
37
FBA_D38
38
FBA_D39
39
FBA_D40
40
FBA_D41
41
FBA_D42
42
FBA_D43
43
FBA_D44
44
FBA_D45
45
FBA_D46
46
FBA_D47
47
FBA_D48
48
FBA_D49
49
FBA_D50
50
FBA_D51
51
FBA_D52
52
FBA_D53
53
FBA_D54
54
FBA_D55
55
FBA_D56
56
FBA_D57
57
FBA_D58
58
FBA_D59
59
FBA_D60
60
FBA_D61
61
FBA_D62
62
FBA_D63
63
FBA_DQM0
0
FBA_DQM1
1
FBA_DQM2
2
FBA_DQM3
3
FBA_DQM4
4
FBA_DQM5
5
FBA_DQM6
6
FBA_DQM7
7
FBA_DQS_WP0
0
FBA_DQS_WP1
1
FBA_DQS_WP2
2
FBA_DQS_WP3
3
FBA_DQS_WP4
4
FBA_DQS_WP5
5
FBA_DQS_WP6
6
FBA_DQS_WP7
7
FBA_DQS_RN0
0
FBA_DQS_RN1
1
FBA_DQS_RN2
2
FBA_DQS_RN3
3
FBA_DQS_RN4
4
FBA_DQS_RN5
5
FBA_DQS_RN6
6
FBA_DQS_RN7
7
SNN_FBA_DBI<0>
SNN_FBA_DBI<1>
SNN_FBA_DBI<2>
SNN_FBA_DBI<3>
SNN_FBA_DBI<4>
SNN_FBA_DBI<5>
SNN_FBA_DBI<6>
SNN_FBA_DBI<7>
OUT
FB_VREF
AM34
AW33
AW36
AW28
AW31
AW29
AM39
AW32
AM36
AW34
AW35
AL34
AK35
AK36
AJ34
AH34
AH35
AJ36
AK37
AL39
AL41
AL42
AK42
AJ39
AH39
AH41
AH42
AN35
AP36
AP37
AR37
AL35
AL36
AL37
AP41
AP42
AN39
AN40
AN41
AN42
AR40
AT39
AR31
AP32
AR33
AT31
AT34
AU34
AU35
AU31
BB33
BA33
AY33
BA34
BB34
AY35
AU30
AP28
AP31
AR28
AP29
AR30
AT30
BA31
BB31
BB30
BB28
BA28
AY28
AJ37
AP35
AP40
AR34
AY34
AU29
AH36
AK41
AP38
AT33
AV34
AT28
AY30
AH37
AK40
AN36
AP39
AT32
AU28
BA30
AH38
AL38
AN38
AR39
AV33
AT29
AV31
L32
G1B
G1B
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
2/19 FBA
2/19 FBA
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7
FB_VREF
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_DEBUG
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBA_WCK0
FBA_WCK0
FBA_WCK1
FBA_WCK1
FBA_WCK2
FBA_WCK2
FBA_WCK3
FBA_WCK3
FB_DLLAVDD0
FB_PLLAVDD0
AA32
AB32
AC32
AD32
AD34
AE32
AF32
AG32
AG34
AK34
AN34
AP30
AP33
J10
J13
J16
J19
J24
J27
J30
AT40
AU38
AT38
BA39
AV37
BB39
AW38
AW42
AW39
AY41
AU39
AV36
BA40
AY39
AU40
BA37
AY36
AY37
AT37
AU36
AV39
AY38
AV40
AU42
AW40
AU41
AW41
BB37
AW37
AY42
BB40
AT36
AT41
AT42
BA36
BB36
AK38
AK39
AM37
AN37
AU32
AU33
AV30
AW30
AH32
AJ32
FBVDDQ
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
SNN_FBA_CMD<7>
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
SNN_FBA_CMD<26>
FBA_CMD27
SNN_FBA_CMD<28>
SNN_FBA_CMD<29>
SNN_FBA_CMD<30>
FBA_DEBUG
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
SNN_FBA_WDS0
SNN_FBA_WDS0*
SNN_FBA_WDS1
SNN_FBA_WDS1*
SNN_FBA_WDS2
SNN_FBA_WDS2*
SNN_FBA_WDS3
SNN_FBA_WDS3*
FB_PLLAVDD0
FBA_CMD[27..0]
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
5,13
OUT
5,13
OUT
5,13
OUT
5,13
OUT
C630
C630
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
GND
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
OUT
BGA136[31..0] BGA136[63..32] ADDR
CMD1 CMD1 RAS*
CMD10 CMD10 CAS*
CMD11 CMD11 WE*
CMD8 CMD8 CS0*
CMD19 CMD19 A<0>
CMD25 CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 CMD21 A<6>
CMD16 CMD16 A<7>
CMD23 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD9 CMD9 A<11>
CMD12 CMD12 BA0
CMD3 CMD3 BA1
CMD27 CMD27 BA2
CMD18 CMD18 CKE
CMD15 CMD15 RST
13
OUT
C629
C629
C626
C626
1UF
1UF
4.7UF
4.7UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0402
0402
COMMON
COMMON
COMMON
COMMON
ASSEMBLY
PAGE DETAIL
FBB_D[63..0]
BI
7,13
FBB_DQM[7..0]
OUT
FBB_DQS_WP[7..0]
7,13
OUT
7,13
FBB_DQS_RN[7..0]
IN
PEX_VDD
C637
C637
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
SNN_FBB_DBI<0>
SNN_FBB_DBI<1>
SNN_FBB_DBI<2>
SNN_FBB_DBI<3>
SNN_FBB_DBI<4>
SNN_FBB_DBI<5>
SNN_FBB_DBI<6>
SNN_FBB_DBI<7>
5,13
CMD-Addr Map
LB503
IND_SMD_0402COMMON
IND_SMD_0402COMMON
7,13
220R@100MHZLB503
220R@100MHZ
GND
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MEMORY: GPU Partition A/B
C40
E39
F37
H37
G38
G39
G40
H39
C41
D40
D41
C42
D42
H40
G41
G42
J37
K37
J38
J39
L36
M34
M35
M36
J40
J41
J42
K39
L39
M38
M39
M40
W35
W36
W37
W38
AA34
AA35
AA36
AA37
W40
AA40
AA41
AA42
AB40
AB41
AB42
AD40
AB34
AB35
AB36
AB37
AE35
AE36
AE37
AG36
AD41
AD42
AE38
AF39
AE42
AG40
AG41
AG42
G37
F41
L37
K42
AA38
AC39
AE34
AE41
F39
F40
K35
K41
Y39
AB39
AD36
AE40
F38
E40
K36
K40
W39
AB38
AD35
AE39
H36
F42
L34
K38
AA39
AD39
AG35
AG39
G1C
G1C
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
3/19 FBB
3/19 FBB
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
FBB_DBI0
FBB_DBI1
FBB_DBI2
FBB_DBI3
FBB_DBI4
FBB_DBI5
FBB_DBI6
FBB_DBI7
CALIBRATION PIN
FB_CALx_PD_VDDQ
FB_CALx_PU_GND
FB_CALx_TERM_GND 40
VREF RATIO
0.7 FBVDDQ
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
DDR3
60
40
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_DEBUG
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
FBB_WCK0
FBB_WCK0
FBB_WCK1
FBB_WCK1
FBB_WCK2
FBB_WCK2
FBB_WCK3
FBB_WCK3
FBVDDQ
J33
K34
K9
L17
L18
L19
L20
L23
L24
L25
L26
L27
FBB_CMD0
N41
FBB_CMD1
R39
FBB_CMD2
N42
FBB_CMD3
V37
FBB_CMD4
T41
FBB_CMD5
T42
FBB_CMD6
V38
SNN_FBB_CMD<7>
R38
FBB_CMD8
N40
FBB_CMD9
U39
FBB_CMD10
N39
FBB_CMD11
V40
FBB_CMD12
R41
FBB_CMD13
V39
FBB_CMD14
P39
FBB_CMD15
V36
FBB_CMD16
V41
FBB_CMD17
T39
FBB_CMD18
T38
FBB_CMD19
T35
FBB_CMD20
T36
FBB_CMD21
T40
FBB_CMD22
R37
FBB_CMD23
M41
FBB_CMD24
T37
FBB_CMD25
M42
SNN_FBB_CMD<26>
R36
FBB_CMD27
V35
SNN_FBB_CMD<28>
V42
SNN_FBB_CMD<29>
R42
SNN_FBB_CMD<30>
R40
FBB_DEBUG
R34
FBB_CLK0
N37
FBB_CLK0*
N38
FBB_CLK1
U34
FBB_CLK1*
V34
SNN_FBB_WDS0
J35
SNN_FBB_WDS0*
J36
SNN_FBB_WDS1
N35
SNN_FBB_WDS1*
N36
SNN_FBB_WDS2
W41
SNN_FBB_WDS2*
W42
SNN_FBB_WDS3
AD37
SNN_FBB_WDS3*
AD38
FB_CAL_PD_VDDQ
M32
FB_CAL_PU_GND
N32
FB_CAL_TERM_GND
P32
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
NAME
FBB_CMD[27..0]
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
TP502TP502TP501TP501
7,13
OUT
7,13
OUT
7,13
OUT
7,13
OUT
R583
R583
0402
0402
1%
1%
R579
R579
0402
0402
1%
1%
R578
R578
0402
0402
1%
1%
600-10562-base-000 A
54.9
54.9
COMMON
COMMON
40.2
40.2
COMMON
COMMON
40.2
40.2
COMMON
COMMON
HFDBA
OUT
FBVDDQ
GND
1
2
7,13
3
4
5
PAGEID
DATE
30-DEC-2008
www.vinafix.vn
A B C D E F G H
Page4: MEMORY: GPU Partition C/D
1
9,13
2
3
4
FBC_D[63..0]
BI
9,13
9,13
9,13
FBC_DQM[7..0]
OUT
FBC_DQS_WP[7..0]
OUT
FBC_DQS_RN[7..0]
IN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
SNN_FBC_DBI<0>
SNN_FBC_DBI<1>
SNN_FBC_DBI<2>
SNN_FBC_DBI<3>
SNN_FBC_DBI<4>
SNN_FBC_DBI<5>
SNN_FBC_DBI<6>
SNN_FBC_DBI<7>
5
G1D
G1D
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
J21
H21
G21
F21
F18
G18
H18
G16
B16
A16
B19
A19
D17
E18
A18
C16
H24
G24
F24
E24
J22
H22
G22
F22
C24
C22
B22
A22
C21
B21
A21
C19
F34
F33
E34
D34
G32
J31
H31
G31
C34
B34
A34
D33
D32
E31
D31
C31
D39
D38
G36
F35
E36
D36
C36
D35
B40
C39
B39
A40
A39
C35
B36
A36
J18
B18
E22
D20
F32
A33
F36
B37
G19
C18
D23
D21
H33
B33
D37
C37
H19
D18
D24
E21
G33
C33
E37
C38
H16
D16
D22
D19
J32
E33
G35
A37
4/19 FBC
4/19 FBC
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
FBC_DBI0
FBC_DBI1
FBC_DBI2
FBC_DBI3
FBC_DBI4
FBC_DBI5
FBC_DBI6
FBC_DBI7
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_DEBUG
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
FBC_WCK0
FBC_WCK0
FBC_WCK1
FBC_WCK1
FBC_WCK2
FBC_WCK2
FBC_WCK3
FBC_WCK3
FB_DLLAVDD1
FB_PLLAVDD1
FBVDDQ
N34
N9
R32
T32
T34
U32
V32
W32
W34
Y32
FBC_CMD0
C25
FBC_CMD1
A27
FBC_CMD2
E25
FBC_CMD3
D30
FBC_CMD4
D28
FBC_CMD5
E28
FBC_CMD6
G27
SNN_FBC_CMD<7>
D27
FBC_CMD8
C30
FBC_CMD9
B28
FBC_CMD10
B25
FBC_CMD11
A30
FBC_CMD12
D26
FBC_CMD13
F27
FBC_CMD14
F25
FBC_CMD15
B31
FBC_CMD16
B30
FBC_CMD17
D29
FBC_CMD18
A28
FBC_CMD19
E27
FBC_CMD20
C27
FBC_CMD21
G28
FBC_CMD22
B27
FBC_CMD23
G25
FBC_CMD24
H27
FBC_CMD25
H25
SNN_FBC_CMD<26>
A25
FBC_CMD27
A31
SNN_FBC_CMD<28>
F28
SNN_FBC_CMD<29>
C28
SNN_FBC_CMD<30>
D25
FBC_DEBUG
J28
FBC_CLK0
J26
FBC_CLK0*
J25
FBC_CLK1
F30
FBC_CLK1*
E30
SNN_FBC_WDS0
F19
SNN_FBC_WDS0*
E19
SNN_FBC_WDS1
B24
SNN_FBC_WDS1*
A24
SNN_FBC_WDS2
H30
SNN_FBC_WDS2*
G30
SNN_FBC_WDS3
H34
SNN_FBC_WDS3*
G34
FB_PLLAVDD1
L21
L22
FBC_CMD[27..0]
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
TP503TP503
9,13
OUT
9,13
OUT
9,13
OUT
9,13
OUT
C672
C672
C671
C671
.1UF
.1UF
1UF
1UF
16V
16V
6.3V
6.3V
10%
10%
10%
10%
X7R
X7R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
9,13
OUT
BGA136[31..0] BGA136[63..32] ADDR
CMD1 CMD1 RAS*
CMD10 CMD10 CAS*
CMD11 CMD11 WE*
CMD8 CMD8 CS0*
CMD19 CMD19 A<0>
CMD25 CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 CMD21 A<6>
CMD16 CMD16 A<7>
CMD23 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD9 CMD9 A<11>
CMD12 CMD12 BA0
CMD3 CMD3 BA1
CMD27 CMD27 BA2
CMD18 CMD18 CKE
CMD15 CMD15 RST
13
OUT
LB504
C660
C660
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
CMD-Addr Map
220R@100MHZLB504
220R@100MHZ
COMMONIND_SMD_0402
COMMONIND_SMD_0402
11,13
GND
11,13
11,13
11,13
PEX_VDD
GND
FBD_D[63..0]
BI
FBD_DQM[7..0]
OUT
FBD_DQS_WP[7..0]
OUT
FBD_DQS_RN[7..0]
IN
C649
C649
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63
FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7
FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7
FBD_DQS_RN0
FBD_DQS_RN1
FBD_DQS_RN2
FBD_DQS_RN3
FBD_DQS_RN4
FBD_DQS_RN5
FBD_DQS_RN6
FBD_DQS_RN7
SNN_FBD_DBI<0>
SNN_FBD_DBI<1>
SNN_FBD_DBI<2>
SNN_FBD_DBI<3>
SNN_FBD_DBI<4>
SNN_FBD_DBI<5>
SNN_FBD_DBI<6>
SNN_FBD_DBI<7>
M9
N8
N7
P9
R9
R8
P7
N6
M4
M2
M1
N1
P4
R4
R2
R1
K8
J7
J6
H6
L9
M8
M7
M6
J2
J1
K4
K3
K2
K1
H3
G4
H12
J11
H10
G12
G9
F9
F8
F12
A10
B10
C10
B9
A9
D10
D7
C8
F13
J15
J12
H15
D15
J14
H13
G13
D12
B12
A12
A13
D14
A15
B15
C15
P6
L4
J8
J3
H9
C9
F14
D11
R7
N2
L7
J5
G10
E9
G15
C13
R6
N3
K7
J4
G11
D9
F15
B13
R5
M5
K5
H4
E10
D8
G14
E12
G1E
G1E
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
5/19 FBD
5/19 FBD
FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63
FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7
FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7
FBD_DQS_RN0
FBD_DQS_RN1
FBD_DQS_RN2
FBD_DQS_RN3
FBD_DQS_RN4
FBD_DQS_RN5
FBD_DQS_RN6
FBD_DQS_RN7
FBD_DBI0
FBD_DBI1
FBD_DBI2
FBD_DBI3
FBD_DBI4
FBD_DBI5
FBD_DBI6
FBD_DBI7
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
FBD_CMD7
FBD_CMD8
FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25
FBD_CMD26
FBD_CMD27
FBD_CMD28
FBD_CMD29
FBD_CMD30
FBD_DEBUG
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
FBD_WCK0
FBD_WCK0
FBD_WCK1
FBD_WCK1
FBD_WCK2
FBD_WCK2
FBD_WCK3
FBD_WCK3
FB_VDDQ_SENSE
G3
F5
G5
B4
E6
A4
D5
D1
D4
C2
F4
E7
B3
C4
F3
B6
C7
C6
G6
F7
E4
C5
E3
F1
D3
F2
D2
A6
D6
C1
A3
G7
G1
G2
B7
A7
N5
N4
L6
K6
F11
F10
E13
D13
J34
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
SNN_FBD_CMD<7>
FBD_CMD8
FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25
SNN_FBD_CMD<26>
FBD_CMD27
SNN_FBD_CMD<28>
SNN_FBD_CMD<29>
SNN_FBD_CMD<30>
FBD_DEBUG
FBD_CLK0
FBD_CLK0*
FBD_CLK1
FBD_CLK1*
SNN_FBD_WDS0
SNN_FBD_WDS0*
SNN_FBD_WDS1
SNN_FBD_WDS1*
SNN_FBD_WDS2
SNN_FBD_WDS2*
SNN_FBD_WDS3
SNN_FBD_WDS3*
FBVDDQ_SENSE
FBD_CMD[27..0]
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
TP504TP504
11,13
OUT
11,13
OUT
11,13
OUT
11,13
OUT
OUT
OUT
28
1
2
11,13
3
4
5
ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
PAGE DETAIL
www.vinafix.vn
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MEMORY: GPU Partition C/D
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
PAGEID
DATE
30-DEC-2008
HFDBA
A B C D E F G H
Page5: FBA Partition
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
FBA_CMD[27..0]
R541
R541
0
0
5%
5%
0402
0402
COMMON
COMMON
GND
13
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
3,13
IN
1
FBA_CLK0_TERM
1.8V 1.8V
C552
C552
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R532
R532
R535
R535
121
121
121
COMMON
COMMON
121
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
IN
IN
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
GND
3,13
3,13
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
2
Minimize the stub length!!
3
3,13
4
3,13
3,13
3,13
FBA_D[63..0]
BI
FBA_DQM[7..0]
BI
FBA_DQS_RN[7..0]
BI
FBA_DQS_WP[7..0]
BI
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
IN
COMMON
COMMON
CMD7 CMD7 BA2
M6E
M6E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
C553
C553
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R537
R537
243
243
1%
1%
0402
0402
COMMON
COMMON
COMMON
H3
RAS
F4
CAS
H9
WE
F9
CS0
K4
A0
H2
A1
K3
A2
M4
A3
K9
A4
H11
A5
K10
A6
L9
A7
K11
A8/AP
M9
A9
K2
A10
L4
A11
G4
BA0
G9
BA1
H10
BA2
H4
CKE
J11
CLK
J10
CLK
J2
NC/RFU
J3
A12 (32Mx32)
V4
SEN (GND)
V9
RESET
A9
MF (GND)
A4
ZQ
K1
VDDA (VDD)
K12
VDDA (VDD)
J1
VSSA (GND)
J12
VSSA (GND)
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NONMIRRORED
NONMIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBA_CMD1 FBA_CMD1
1
FBA_CMD10 FBA_CMD10
10
FBA_CMD11 FBA_CMD11
11
8
FBA_CMD19 FBA_CMD19
19
FBA_CMD25 FBA_CMD25
25
FBA_CMD22
22
FBA_CMD24
24
FBA_CMD0
0
FBA_CMD2
2
FBA_CMD21 FBA_CMD21
21
FBA_CMD16 FBA_CMD16
16
FBA_CMD23 FBA_CMD23
23
FBA_CMD20 FBA_CMD20
20
FBA_CMD17 FBA_CMD17
17
FBA_CMD9 FBA_CMD9
9
FBA_CMD12 FBA_CMD12
12
FBA_CMD3 FBA_CMD3
3
FBA_CMD27 FBA_CMD27
27
FBA_CMD18 FBA_CMD18
18
FBA_CLK0
FBA_CLK0*
SNN_FBA0_NC1 SNN_FBA1_NC1
FBA_CMD14 FBA_CMD14
14
FBA_CMD_SENA0 FBA_CMD_SENA1
FBA_CMD15 FBA_CMD15
15
FBA_CMD15
FBA_ZQ0
FBA_CMD18
R543
R543
R528
R528
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
GND
GND GND GND
FBVDDQ
C568
C568
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
M6A
M6A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBA_D0
0
FBA_D1
1
FBA_D2
2
FBA_D3
3
FBA_D4
4
FBA_D5
5
FBA_D6
6
FBA_D7
7
FBA_DQM0
FBA_DQS_RN0
FBA_DQS_WP0
FBA_D32
32
FBA_D33
33
FBA_D34
34
FBA_D35
35
FBA_D36
36
FBA_D37
37
FBA_D38
38
FBA_D39
39
FBA_DQM4
FBA_DQS_RN4
FBA_DQS_WP4
G10
F11
E11
B10
B11
C11
C10
F10
E10
D10
D11
L3
N2
R3
M3
R2
T3
T2
M2
N3
P3
P2
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M7E
M7E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
FBA_D8
8
FBA_D9
9
FBA_D10
10
FBA_D11
11
FBA_D12
12
FBA_D13
13
FBA_D14
14
FBA_D15
15
FBA_DQM1
FBA_DQS_RN1
FBA_DQS_WP1
FBA_D40
40
FBA_D41
41
FBA_D42
42
FBA_D43
43
FBA_D44
44
FBA_D45
45
FBA_D46
46
FBA_D47
47
FBA_DQM5
FBA_DQS_RN5
FBA_DQS_WP5
FBVDDQ
GND
GND
FBA_VREF0
FBA_VREF2
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511 + 1.18K)
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
R558
R558
511
511
1%
1%
0402
0402
COMMON
COMMON
R557
R557
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
M6B
M6B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
G3
DQ0
F3
DQ1
F2
DQ2
E2
DQ3
C2
DQ4
C3
DQ5
B2
DQ6
B3
DQ7
E3
DQM
D3
RDQS
D2
WDQS
M7A
M7A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
M10
DQ0
M11
DQ1
L10
DQ2
N11
DQ3
R11
DQ4
T11
DQ5
T10
DQ6
R10
DQ7
N10
DQM
P10
RDQS
P11
WDQS
C GE
GND
3,13
3,13
R1
R2
FBA_CLK1_TERM
C561
C561
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
IN
IN
ASSEMBLY
PAGE DETAIL
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R536
R536
0
0
5%
5%
0402
0402
FBVDDQ
COMMON
COMMON
GND
13
IN
DDR3:
ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
FBVDDQ
R1
R2
C51
C51
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
COMMON
COMMON
R549
R549
R555
R555
121
121
121
121
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
13
OUT
C575
C575
.1UF
.1UF
16V
16V
10%
10%
FBVDDQ
X7R
X7R
0402
0402
COMMON
COMMON
R75
R75
511
511
1%
1%
0402
0402
COMMON
COMMON
R70
R70
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
M6C
M6C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBA_D16
16
FBA_D17
17
FBA_D18
18
FBA_D19
19
FBA_D20
20
FBA_D21
21
FBA_D22
22
FBA_D23
23
FBA_DQM2
FBA_DQS_RN2
FBA_DQS_WP2
FBA_D48
48
FBA_D49
49
FBA_D50
50
FBA_D51
51
FBA_D52
52
FBA_D53
53
FBA_D54
54
FBA_D55
55
FBA_DQM6
FBA_DQS_RN6
FBA_DQS_WP6
COMMON
R10
DQ0
T11
DQ1
T10
DQ2
R11
DQ3
N11
DQ4
L10
DQ5
M11
DQ6
M10
DQ7
N10
DQM
P10
RDQS
P11
WDQS
M7B
M7B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
E2
DQ0
C2
DQ1
G3
DQ2
C3
DQ3
B3
DQ4
B2
DQ5
F2
DQ6
F3
DQ7
E3
DQM
D3
RDQS
D2
WDQS
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA Partition
FBA_D24
24
FBA_D25
25
FBA_D26
26
FBA_D27
27
FBA_D28
28
FBA_D29
29
FBA_D30
30
FBA_D31
31
FBA_DQM3FBA_DQM4
FBA_DQS_RN3
FBA_DQS_WP3
FBA_D56
56
FBA_D57
57
FBA_D58
58
FBA_D59
59
FBA_D60
60
FBA_D61
61
FBA_D62
62
FBA_D63
63
FBA_DQM7
FBA_DQS_RN7
FBA_DQS_WP7
M7D
M7D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
1
10
11
8
19
25
FBA_CMD4
4
FBA_CMD6
6
FBA_CMD5
5
FBA_CMD13
13
21
16
23
20
17
9
12
3
27
18
FBA_CLK1
FBA_CLK1*
14
15
FBA_ZQ1
C571
C571
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
COMMON
H10
RAS
F9
CAS
H4
WE
F4
CS0
K9
A0
H11
A1
K10
A2
M9
A3
K4
A4
H2
A5
K3
A6
L4
A7
K2
A8/AP
M4
A9
K11
A10
L9
A11
G9
BA0
G4
BA1
H3
BA2
H9
CKE
J11
CLK
J10
CLK
J2
NC/RFU
J3
A12 (32Mx32)
V4
SEN (GND)
V9
RESET
A9
MF (GND)
A4
ZQ
R533
R533
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
K1
VDDA (VDD)
K12
VDDA (VDD)
C555
C555
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
J1
VSSA (GND)
J12
VSSA (GND)
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
MIRRORED
MIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
GND
G12
L12
FBA_VREF1
H1
FBA_VREF3
H12
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
FBVDDQ
R71
R71
511
511
1%
1%
0402
0402
COMMON
COMMON
R72
R72
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
FBA_CMD4
FBA_CMD6FBA_CMD8 FBA_CMD8
FBA_CMD5
FBA_CMD13
FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511 + 1.18K)
R2
C52
C52
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
R544 121
R544 121
0402
0402
1%
1%
R552
04021%COMMON
04021%COMMON
R538 121
R538 121
0402
0402
1%
1%
R530 121
R530 121
0402
0402
1%
1%
R546
R546
0402
0402
1%
1%
R553 121
R553 121
0402
0402
1%
1%
R534
1%
R529 121
R529 121
1%
1%
COMMON
COMMON
121R552
121
COMMON
COMMON
COMMON
COMMON
121
121
COMMON
COMMON
COMMON
COMMON
1211%R534
121
COMMON0402
COMMON0402
COMMON0402
COMMON0402
COMMON
COMMON
COMMON
COMMON
FBVDDQ
1
2
FBVDDQ
R559
R559
511
511
R1R1
1%
1%
0402
0402
R556
R556
1.3K
1.3K
R2
1%
1%
0402
0402
GND
C572
C572
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
3
GND
M6D
M6D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
R2
DQ0
N2
DQ1
L3
DQ2
T2
M2
M3
R3
T3
N3
P3
P2
M7C
M7C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
G10
F10
F11
E11
C11
B10
B11
C10
E10
D10
D11
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
PAGEID
DATE
30-DEC-2008
HFDBA
4
5
www.vinafix.vn
A B C D E F G H
Page6: FBA Partition Decoupling
1
2
Decoupling for FBA 31..0
FBVDDQ
C564
C564
C570
C570
C573
C573
C539
C539
.047UF
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C540
C540
C545
C545
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C538
C538
C565
C565
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
3
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C547
C547
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C536
C536
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C532
C532
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
Decoupling for FBA 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINSPLACE NEAR MEMORY FBVDDQ PINS
C566
C566
C556
C556
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C543
C543
C537
C537
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C563
C563
C557
C557
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C558
C558
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C549
C549
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C535
C535
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C550
C550
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C533
C533
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA Partition Decoupling
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
A B C D E F G H
Page7: FBB Partition
FBB_CMD[27..0]
3,13
IN
CMD-Addr Map
BGA136 ADDR
1
FBB_CLK0_TERM
1.8V
C587
C587
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R566
R566
R565
R565
121
121
121
1%
1%
0402
0402
COMMON
COMMON
IN
IN
DDR3: ZQ = 6x desired output
121
1%
1%
0402
0402
COMMON
COMMON
impedence of DQ drivers
GND
3,13
3,13
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
2
MEMORY pin!!
Minimize the stub length!!
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
GND
R561
R561
0
0
5%
5%
0402
0402
COMMON
COMMON
13
IN
GND
FBB_CMD1 FBB_CMD1
1
FBB_CMD10 FBB_CMD10
10
FBB_CMD11 FBB_CMD11
11
FBB_CMD8 FBB_CMD8
8
FBB_CMD19 FBB_CMD19
19
FBB_CMD25 FBB_CMD25
25
FBB_CMD22
22
FBB_CMD24
24
FBB_CMD0
0
FBB_CMD2
2
FBB_CMD21 FBB_CMD21
21
FBB_CMD16 FBB_CMD16
16
FBB_CMD23 FBB_CMD23
23
FBB_CMD20 FBB_CMD20
20
FBB_CMD17 FBB_CMD17
17
FBB_CMD9 FBB_CMD9
9
FBB_CMD12 FBB_CMD12
12
FBB_CMD3 FBB_CMD3
3
FBB_CMD27 FBB_CMD27
27
FBB_CMD18 FBB_CMD18
18
FBB_CLK0
FBB_CLK0*
SNN_FBB0_NC1 SNN_FBB1_NC1
FBB_CMD14 FBB_CMD14
14
FBB_CMD_SENB0 FBB_CMD_SENB1
FBB_CMD15 FBB_CMD15
15
FBB_CMD15
FBB_ZQ0
R548
R548
R560
R560
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND GND GND
FBVDDQ
C590
3
C590
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
3,13
4
3,13
3,13
3,13
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBB_D[63..0]
BI
0
1
2
3
FBB_DQM[7..0]
BI
FBB_DQS_RN[7..0]
BI
FBB_DQS_WP[7..0]
BI
FBB_DQM0
0
FBB_DQM1
1
FBB_DQM2
2
FBB_DQM3
3
4
FBB_DQM5
5
FBB_DQM6
6
FBB_DQM7
7
FBB_DQS_RN0
0
FBB_DQS_RN1
1
FBB_DQS_RN2
2
FBB_DQS_RN3
3
FBB_DQS_RN4
4
FBB_DQS_RN5
5
FBB_DQS_RN6
6
FBB_DQS_RN7
7
FBB_DQS_WP0
0
FBB_DQS_WP1
1
FBB_DQS_WP2
2
FBB_DQS_WP3
3
FBB_DQS_WP4
4
FBB_DQS_WP5
5
FBB_DQS_WP6
6
FBB_DQS_WP7
7
4
5
6
7
32
33
34
35
36
37
38
39
R568
R568
243
243
1%
1%
0402
0402
COMMON
COMMON
C586
C586
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_DQM0
FBB_DQS_RN0
FBB_DQS_WP0
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_DQM4
FBB_DQS_RN4
FBB_DQS_WP4
M5E
M5E
BGA_0136_P080_140X120
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
B10
C10
B11
G10
E11
F10
C11
F11
E10
D10
D11
T2
M2
T3
R3
L3
N2
R2
M3
N3
P3
P2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NONMIRRORED
NONMIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
M5A
M5A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M8E
M8E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBVDDQ
FBB_VREF0
FBB_VREF2
VREF = FBVDDQ * R2/(R1 + R2)
DDR3: VREF = 0.70 * FBVDDQ
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_DQM1
FBB_DQS_RN1
FBB_DQS_WP1
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_DQM5
FBB_DQS_RN5
FBB_DQS_WP5
GND
COMMON
COMMON
COMMON
COMMON
GND
1.26V = 1.8V * 1.18K/(511 + 1.18K)
F3
C2
B2
C3
B3
G3
F2
E2
E3
D3
D2
T10
R10
T11
R11
M11
M10
N11
L10
N10
P10
P11
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
R570
R570
511
511
1%
1%
0402
0402
R569
R569
1.3K
1.3K
1%
1%
0402
0402
GND
M5B
M5B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M8A
M8A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
C GE
GND
3,13
3,13
R1
R2
ASSEMBLY
PAGE DETAIL
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
R1
R2
ZQ = 6x desired output
DDR3:Impedence = 240 / 6 = 40 ohm
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R551
R551
0
0
5%
5%
0402
0402
FBVDDQ
COMMON
COMMON
GND
13
IN
13
OUT
C43
C43
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBB_CLK1_TERM
1.8V
C548
C548
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
IN
IN
C589
C589
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R542
R542
R540
R540
121
121
121
121
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
13
OUT
FBVDDQ
R52
R52
511
511
1%
1%
0402
0402
COMMON
COMMON
R53
R53
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
M5C
M5C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBB_D16
16
FBB_D17
17
FBB_D18
18
FBB_D19
19
FBB_D20
20
FBB_D21
21
FBB_D22
22
FBB_D23
23
FBB_DQM2
FBB_DQS_RN2
FBB_DQS_WP2
FBB_D48
48
FBB_D49
49
FBB_D50
50
FBB_D51
51
FBB_D52
52
FBB_D53
53
FBB_D54
54
FBB_D55
55
FBB_DQM6
FBB_DQS_RN6
FBB_DQS_WP6
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBB Partition
M10
N11
M11
L10
T10
R10
T11
R11
N10
P10
P11
M8B
M8B
E2
F3
F2
G3
C3
B2
B3
C2
E3
D3
D2
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
FBB_D24
24
FBB_D25
25
FBB_D26
26
FBB_D27
27
FBB_D28
28
FBB_D29
29
FBB_D30
30
FBB_D31
31
FBB_DQM3FBB_DQM4
FBB_DQS_RN3
FBB_DQS_WP3
FBB_D56
56
FBB_D57
57
FBB_D58
58
FBB_D59
59
FBB_D60
60
FBB_D61
61
FBB_D62
62
FBB_D63
63
FBB_DQM7
FBB_DQS_RN7
FBB_DQS_WP7
1
10
11
8
19
25
4
6
5
13
21
16
23
20
17
9
12
3
27
18
14
15
FBVDDQ
GND
FBB_CMD4
FBB_CMD6
FBB_CMD13
C569
C569
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
G10
F11
F10
C11
E11
B11
B10
C10
E10
D10
D11
FBB_CLK1
FBB_CLK1*
FBB_ZQ1
L3
M2
M3
N2
R2
T2
T3
R3
N3
P3
P2
R527
R527
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
C546
C546
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
M5D
M5D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M8C
M8C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
H10
F9
H4
F4
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
G9
G4
H3
H9
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
M8D
M8D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
M12
VDD
A1
VDDQ
C1
VDDQ
E1
VDDQ
N1
VDDQ
R1
VDDQ
V1
VDDQ
C4
VDDQ
E4
VDDQ
J4
VDDQ
N4
VDDQ
R4
VDDQ
C9
VDDQ
E9
VDDQ
J9
VDDQ
N9
VDDQ
R9
VDDQ
MIRRORED
MIRRORED
A12
VDDQ
C12
VDDQ
E12
VDDQ
N12
VDDQ
R12
VDDQ
V12
VDDQ
B1
VSSQ
D1
VSSQ
P1
VSSQ
T1
VSSQ
G2
VSSQ
L2
VSSQ
B4
VSSQ
D4
VSSQ
P4
VSSQ
T4
VSSQ
B9
VSSQ
D9
VSSQ
P9
VSSQ
T9
VSSQ
G11
VSSQ
L11
VSSQ
B12
VSSQ
D12
VSSQ
P12
VSSQ
T12
VSSQ
G1
VSS
L1
VSS
A3
VSS
V3
VSS
A10
VSS
V10
VSS
G12
VSS
L12
VSS
FBB_VREF1
H1
VREF
FBB_VREF3
H12
VREF
FBVDDQ
GND
GND
VREF = FBVDDQ * R2/(R1 + R2)
FBVDDQ
R67
R67
511
511
1%
1%
0402
0402
COMMON
COMMON
R68
R68
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
FBB_CMD4FBB_CMD5
FBB_CMD6
FBB_CMD5
FBB_CMD13
FBB_CMD22
FBB_CMD24
FBB_CMD0
FBB_CMD2
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
R1
OUT
C50
C50
.1UF
.1UF
R2
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
NAME
R545
R545
0402
0402
R554
R554
0402
0402
R539
R539
0402
0402
R531
0402 COMMON
0402 COMMON
R567
04021%COMMON
04021%COMMON
R564
04021%COMMON
04021%COMMON
R563
R563
0402
0402
R562
R562
0402
0402
R550
R550
COMMON
COMMON
13
COMMON
COMMON
R547
R547
600-10562-base-000 A
1
FBVDDQ
121
121
COMMON
COMMON
1%
1%
121
121
COMMON
COMMON
1%
1%
121
121
COMMON
COMMON
1%
1%
121R531
121
1%
1%
121R567
121
121R564
121
121
121
COMMON
COMMON
1%
1%
121
121
COMMON
COMMON
1%
1%
2
FBVDDQ
511
511
R1
1%
1%
0402
0402
1.3K
1.3K
R2
1%
1%
0402
0402
C560
C560
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
3
GND
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
www.vinafix.vn
A B C D E F G H
Page8: FBB Partition Decoupling
1
2
Decoupling for FBB 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C580
C580
C592
C592
C593
C593
C584
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C581
C581
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C576
C576
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C584
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C577
C577
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C578
C578
C579
C579
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C583
C583
C596
C596
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
3
X5R
X5R
0402
0402
COMMON
COMMON
10%
X5R
X5R
0402
0402
COMMON
COMMON
Decoupling for FBB 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C544
C544
C542
C542
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C554
C554
C562
C562
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C531
C531
C574
C574
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C567
C567
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C534
C534
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C551
C551
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C559
C559
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C541
C541
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBB Partion Decoupling
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
A B C D E F G H
Page9: FBC Partition
FBC_CMD[27..0]
4,13
IN
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
GND
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R594
R594
0
0
5%
5%
0402
0402
COMMON
COMMON
13
IN
1
FBC_CLK0_TERM
1.8V
C745
C745
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
4,13
IN
4,13
IN
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
2
MEMORY pin!!
Minimize the stub length!!
COMMON
COMMON
R611
R611
121
121
1%
1%
0402
0402
DDR3:
R612
R612
121
121
1%
1%
0402
0402
COMMON
COMMON
ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
GND
FBC_CMD1 FBC_CMD1
1
FBC_CMD10 FBC_CMD10
10
FBC_CMD11 FBC_CMD11
11
FBC_CMD8 FBC_CMD8
8
FBC_CMD19 FBC_CMD19
19
FBC_CMD25 FBC_CMD25
25
FBC_CMD22
22
FBC_CMD24
24
FBC_CMD0
0
FBC_CMD2
2
FBC_CMD21 FBC_CMD21
21
FBC_CMD16 FBC_CMD16
16
FBC_CMD23 FBC_CMD23
23
FBC_CMD20 FBC_CMD20
20
FBC_CMD17 FBC_CMD17
17
FBC_CMD9 FBC_CMD9
9
FBC_CMD12 FBC_CMD12
12
FBC_CMD3 FBC_CMD3
3
FBC_CMD27 FBC_CMD27
27
FBC_CMD18 FBC_CMD18
18
FBC_CLK0
FBC_CLK0*
SNN_FBC0_NC1 SNN_FBC1_NC1
FBC_CMD14 FBC_CMD14
14
FBC_CMD_SENC0 FBC_CMD_SENC1
FBC_CMD15 FBC_CMD15
15
FBC_CMD15
FBC_CMD18
R590
R590
R591
R591
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND GND GND
FBVDDQ
C730
3
C730
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
4,13
4
4,13
4,13
4,13
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBC_D[63..0]
BI
0
1
2
3
FBC_DQM[7..0]
BI
FBC_DQS_RN[7..0]
BI
FBC_DQS_WP[7..0]
BI
FBC_DQM0
0
FBC_DQM1
1
FBC_DQM2
2
FBC_DQM3
3
4
FBC_DQM5
5
FBC_DQM6
6
FBC_DQM7
7
FBC_DQS_RN0
0
FBC_DQS_RN1
1
FBC_DQS_RN2
2
FBC_DQS_RN3
3
FBC_DQS_RN4
4
FBC_DQS_RN5
5
FBC_DQS_RN6
6
FBC_DQS_RN7
7
FBC_DQS_WP0
0
FBC_DQS_WP1
1
FBC_DQS_WP2
2
FBC_DQS_WP3
3
FBC_DQS_WP4
4
FBC_DQS_WP5
5
FBC_DQS_WP6
6
FBC_DQS_WP7
7
4
5
6
7
32
33
34
35
36
37
38
39
FBC_ZQ0
R620
R620
243
243
1%
1%
0402
0402
COMMON
COMMON
C731
C731
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_DQM0
FBC_DQS_RN0
FBC_DQS_WP0
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_DQM4
FBC_DQS_RN4
FBC_DQS_WP4
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
M3E
M3E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
E11
F10
G10
F11
C10
B10
C11
B11
E10
D10
D11
L3
M3
M2
N2
R3
R2
T2
T3
N3
P3
P2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NONMIRRORED
NONMIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
M3A
M3A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M4E
M4E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBC_VREF0
H1
FBC_VREF2
H12
VREF = FBVDDQ * R2/(R1 + R2)
FBC_D8
8
FBC_D9
9
FBC_D10
10
FBC_D11
11
FBC_D12
12
FBC_D13
13
FBC_D14
14
FBC_D15
15
FBC_DQM1
FBC_DQS_RN1
FBC_DQS_WP1
FBC_D40
40
FBC_D41
41
FBC_D42
42
FBC_D43
43
FBC_D44
44
FBC_D45
45
FBC_D46
46
FBC_D47
47
FBC_DQM5
FBC_DQS_RN5
FBC_DQS_WP5
FBVDDQ
GND
GND
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511K + 1.18K)
C2
B2
G3
C3
E2
B3
E3
D3
D2
L10
M11
M10
N11
R11
T11
T10
R10
N10
P10
P11
GND
4,13
4,13
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
R607
R607
511
511
R1
1%
1%
0402
0402
COMMON
COMMON
R615
R615
1.3K
1.3K
R2
1%
1%
0402
0402
COMMON
COMMON
GND
M3B
M3B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
F2
DQ3
DQ4
F3
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M4A
M4A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
C GE
FBC_CLK1_TERM
1.8V
C610
C610
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
IN
IN
ASSEMBLY
PAGE DETAIL
M4D
M4D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
H10
RAS
F9
CAS
H4
WE
F4
CS0
K9
A0
H11
A1
K10
A2
M9
A3
K4
A4
H2
A5
K3
A6
L4
A7
K2
A8/AP
M4
A9
K11
A10
L9
A11
G9
BA0
G4
BA1
H3
BA2
H9
CKE
J11
CLK
J10
CLK
J2
NC/RFU
J3
A12 (32Mx32)
V4
SEN (GND)
V9
RESET
A9
MF (GND)
FBC_ZQ1
A4
ZQ
R571
R571
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
K1
VDDA (VDD)
K12
VDDA (VDD)
C619
C619
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
J1
VSSA (GND)
J12
VSSA (GND)
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
MIRRORED
MIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBC_VREF1
H1
FBC_VREF3
H12
FBVDDQ
R50
R50
511
511
1%
1%
0402
0402
COMMON
COMMON
R51
R51
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
GND
FBC_CMD4FBC_CMD5
FBC_CMD6
FBC_CMD5
FBC_CMD13
FBC_CMD22
FBC_CMD24
FBC_CMD0
FBC_CMD2
13
OUT
C42
C42
.1UF
.1UF
R2
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R581
121
R581
121
COMMON
COMMON
0402
0402
1%
1%
R584
121R584
121
COMMON0402
COMMON0402
1%
1%
R582
121R582
121
04021%COMMON
04021%COMMON
R577
121
R577
121
COMMON
COMMON
0402
0402
1%
1%
R605
121R605
121
04021%COMMON
04021%COMMON
R601
121R601
121
04021%COMMON
04021%COMMON
R599
121
R599
121
0402
0402
COMMON
COMMON
1%
1%
R608
121
R608
121
0402
COMMON
0402
COMMON
1%
1%
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511K + 1.18K)
FBVDDQ
R580
R580
511
511
R1R1
1%
1%
0402
0402
COMMON
COMMON
R574
R574
1.3K
1.3K
R2
1%
1%
0402
0402
COMMON
COMMON
GND
FBVDDQ
C612
C612
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
1
2
3
C742
C742
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R575
R575
121
121
1%
1%
0402
0402
COMMON
COMMON
OUT
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
R586
R586
0
0
5%
5%
0402
0402
COMMON
COMMON
CMD18 CKE
CMD15 RST
R576
R576
121
121
1%
1%
0402
0402
COMMON
COMMON
GND
DDR3:
ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
13
1
10
11
8
19
25
FBC_CMD4
4
FBC_CMD6
6
5
FBC_CMD13
13
21
16
23
20
17
9
12
3
27
18
FBC_CLK1
FBC_CLK1*
14
FBVDDQ
15
13
IN
FBVDDQ
FBVDDQ
C613
C613
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
COMMON
COMMON
COMMON
COMMON
R49
R49
511
511
R1
1%
1%
0402
0402
R48
R48
1.3K
1.3K
R2
1%
1%
0402
0402
C41
C41
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
GND
M3C
M3C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBC_D16
16
FBC_D17
17
FBC_D18
18
FBC_D19
19
FBC_D20
20
FBC_D21
21
FBC_D22
22
FBC_D23
23
FBC_DQM2
FBC_DQS_RN2
FBC_DQS_WP2
FBC_D48
48
FBC_D49
49
FBC_D50
50
FBC_D51
51
FBC_D52
52
FBC_D53
53
FBC_D54
54
FBC_D55
55
FBC_DQM6
FBC_DQS_RN6
FBC_DQS_WP6
COMMON
M11
DQ0
N11
DQ1
T11
DQ2
T10
DQ3
M10
DQ4
L10
DQ5
R11
DQ6
R10
DQ7
N10
DQM
P10
RDQS
P11
WDQS
M4B
M4B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
B2
DQ0
C2
DQ1
B3
DQ2
E2
DQ3
C3
DQ4
F2
DQ5
F3
DQ6
G3
DQ7
E3
DQM
D3
RDQS
D2
WDQS
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC Partition
FBC_D24
24
FBC_D25
25
FBC_D26
26
FBC_D27
27
FBC_D28
28
FBC_D29
29
FBC_D30
30
FBC_D31
31
FBC_DQM3FBC_DQM4
FBC_DQS_RN3
FBC_DQS_WP3
FBC_D56
56
FBC_D57
57
FBC_D58
58
FBC_D59
59
FBC_D60
60
FBC_D61
61
FBC_D62
62
FBC_D63
63
FBC_DQM7
FBC_DQS_RN7
FBC_DQS_WP7
M3D
M3D
T3
R3
T2
R2
M2
M3
N2
L3
N3
P3
P2
M4C
M4C
E11
C11
B10
C10
B11
G10
F10
F11
E10
D10
D11
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
www.vinafix.vn
A B C D E F G H
Page10: FBC Partition
1
2
3
Decoupling for FBC 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C752
C752
C753
C753
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C756
C756
C703
C703
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C750
C750
C721
C721
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C732
C732
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C726
C726
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C707
C707
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C741
C741
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C704
C704
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
Decoupling for FBC 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C642
C642
C605
C605
C602
C602
C639
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C634
C634
C653
C653
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C640
C640
C606
C606
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C608
C608
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C604
C604
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C639
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C621
C621
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC Partition Decoupling
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
A B C D E F G H
Page11: FBD Partition
FBD_CMD[27..0]
4,13
IN
CMD-Addr Map
BGA136 ADDR
1
FBD_CLK0_TERM
1.8V
C805
C805
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R691
R691
R688
R688
121
121
121
121
1%
1%
1%
0402
0402
COMMON
COMMON
DDR3: ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
COMMON
COMMON
1%
0402
0402
GND
4,13
IN
4,13
IN
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
2
MEMORY pin!!
Minimize the stub length!!
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R677
R677
0
0
5%
5%
0402
0402
COMMON
COMMON
GND
13
IN
GND
FBD_CMD1 FBD_CMD1
1
FBD_CMD10 FBD_CMD10
10
FBD_CMD11 FBD_CMD11
11
FBD_CMD8 FBD_CMD8
8
FBD_CMD19 FBD_CMD19
19
FBD_CMD25 FBD_CMD25
25
FBD_CMD22
22
FBD_CMD24
24
FBD_CMD0
0
FBD_CMD2
2
FBD_CMD21 FBD_CMD21
21
FBD_CMD16 FBD_CMD16
16
FBD_CMD23 FBD_CMD23
23
FBD_CMD20 FBD_CMD20
20
FBD_CMD17 FBD_CMD17
17
FBD_CMD9 FBD_CMD9
9
FBD_CMD12 FBD_CMD12
12
FBD_CMD3 FBD_CMD3
3
FBD_CMD27 FBD_CMD27
27
FBD_CMD18 FBD_CMD18
18
FBD_CMD18
FBD_CLK0
FBD_CLK0*
SNN_FBD0_NC1 SNN_FBD1_NC1
FBD_CMD14 FBD_CMD14
14
FBD_CMD_SEND0 FBD_CMD_SEND1
FBD_CMD15 FBD_CMD15
15
FBD_CMD15
FBD_ZQ0
R681
R681
R696
R696
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND GND GND
FBVDDQ
C783
3
C783
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
4,13
4
4,13
4,13
4,13
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBD_D[63..0]
BI
0
1
2
3
FBD_DQM[7..0]
BI
FBD_DQS_RN[7..0]
BI
FBD_DQS_WP[7..0]
BI
FBD_DQM0
0
FBD_DQM1
1
FBD_DQM2
2
FBD_DQM3
3
4
FBD_DQM5
5
FBD_DQM6
6
FBD_DQM7
7
FBD_DQS_RN0
0
FBD_DQS_RN1
1
FBD_DQS_RN2
2
FBD_DQS_RN3
3
FBD_DQS_RN4
4
FBD_DQS_RN5
5
FBD_DQS_RN6
6
FBD_DQS_RN7
7
FBD_DQS_WP0
0
FBD_DQS_WP1
1
FBD_DQS_WP2
2
FBD_DQS_WP3
3
FBD_DQS_WP4
4
FBD_DQS_WP5
5
FBD_DQS_WP6
6
FBD_DQS_WP7
7
4
5
6
7
32
33
34
35
36
37
38
39
R679
R679
243
243
1%
1%
0402
0402
COMMON
COMMON
C813
C813
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_DQM0
FBD_DQS_RN0
FBD_DQS_WP0
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_DQM4
FBD_DQS_RN4
FBD_DQS_WP4
M2E
M2E
BGA_0136_P080_140X120
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
B10
F11
F10
B11
C11
C10
E11
G10
E10
D10
D11
T3
T2
R2
M2
R3
M3
N2
L3
N3
P3
P2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NONMIRRORED
NONMIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
M2A
M2A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M1E
M1E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBD_VREF0
H1
FBD_VREF2
H12
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
FBD_D8
8
FBD_D9
9
FBD_D10
10
FBD_D11
11
FBD_D12
12
FBD_D13
13
FBD_D14
14
FBD_D15
15
FBD_DQM1
FBD_DQS_RN1
FBD_DQS_WP1
FBD_D40
40
FBD_D41
41
FBD_D42
42
FBD_D43
43
FBD_D44
44
FBD_D45
45
FBD_D46
46
FBD_D47
47
FBD_DQM5
FBD_DQS_RN5
FBD_DQS_WP5
FBVDDQ
GND
GND
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511 + 1.18K)
G3
F3
F2
E2
C2
B3
B2
C3
E3
D3
D2
N11
M11
M10
R11
T11
L10
T10
R10
N10
P10
P11
4,13
4,13
R650
R650
COMMON
COMMON
R661
R661
COMMON
COMMON
M2B
M2B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
M1A
M1A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
C GE
FBD_CLK1_TERM
1.8V
C792
C792
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
IN
IN
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
511
511
R1
1%
1%
0402
0402
1.3K
1.3K
R2
1%
1%
0402
0402
GND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
ASSEMBLY
PAGE DETAIL
CMD-Addr Map
C782
C782
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R666
R666
121
121
1%
1%
0402
0402
COMMON
COMMON
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
R669
R669
121
121
1%
1%
0402
0402
COMMON
COMMON
CMD18 CKE
CMD15 RST
R682
R682
0
0
5%
5%
0402
0402
COMMON
COMMON
GND
DDR3: ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
13
OUT
FBVDDQ
R31
R31
511
511
R1
1%
1%
0402
0402
COMMON
COMMON
COMMON
COMMON
R34
R34
1.3K
1.3K
R2
1%
1%
0402
0402
C31
C31
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
1
10
11
8
19
25
FBD_CMD4
4
FBD_CMD6
6
FBD_CMD5
5
FBD_CMD13
13
21
16
23
20
17
9
12
3
27
18
14
FBVDDQ
15
13
IN
FBVDDQ
C817
C817
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
GND
M2C
M2C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBD_D16
16
FBD_D17
17
FBD_D18
18
FBD_D19
19
FBD_D20
20
FBD_D21
21
FBD_D22
22
FBD_D23
23
FBD_DQM2
FBD_DQS_RN2
FBD_DQS_WP2
FBD_D48
48
FBD_D49
49
FBD_D50
50
FBD_D51
51
FBD_D52
52
FBD_D53
53
FBD_D54
54
FBD_D55
55
FBD_DQM6
FBD_DQS_RN6
FBD_DQS_WP6
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBD Partition
R10
R11
T10
T11
N11
L10
M11
M10
N10
P10
P11
E2
B3
C2
C3
B2
F3
G3
F2
E3
D3
D2
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M1B
M1B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
FBD_D24
24
FBD_D25
25
FBD_D26
26
FBD_D27
27
FBD_D28
28
FBD_D29
29
FBD_D30
30
FBD_D31
31
FBD_DQM3FBD_DQM4
FBD_DQS_RN3
FBD_DQS_WP3
FBD_D56
56
FBD_D57
57
FBD_D58
58
FBD_D59
59
FBD_D60
60
FBD_D61
61
FBD_D62
62
FBD_D63
63
FBD_DQM7
FBD_DQS_RN7
FBD_DQS_WP7
G10
F10
F11
E11
C11
B10
C10
B11
E10
D10
D11
FBD_CLK1
FBD_CLK1*
FBD_ZQ1
T2
R2
L3
M3
M2
N2
R3
T3
N3
P3
P2
R690
R690
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
C781
C781
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
M2D
M2D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M1C
M1C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
H10
F9
H4
F4
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
G9
G4
H3
H9
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
M1D
M1D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
M12
VDD
A1
VDDQ
C1
VDDQ
E1
VDDQ
N1
VDDQ
R1
VDDQ
V1
VDDQ
C4
VDDQ
E4
VDDQ
J4
VDDQ
N4
VDDQ
R4
VDDQ
C9
VDDQ
E9
VDDQ
J9
VDDQ
N9
VDDQ
R9
VDDQ
MIRRORED
MIRRORED
A12
VDDQ
C12
VDDQ
E12
VDDQ
N12
VDDQ
R12
VDDQ
V12
VDDQ
B1
VSSQ
D1
VSSQ
P1
VSSQ
T1
VSSQ
G2
VSSQ
L2
VSSQ
B4
VSSQ
D4
VSSQ
P4
VSSQ
T4
VSSQ
B9
VSSQ
D9
VSSQ
P9
VSSQ
T9
VSSQ
G11
VSSQ
L11
VSSQ
B12
VSSQ
D12
VSSQ
P12
VSSQ
T12
VSSQ
G1
VSS
L1
VSS
A3
VSS
V3
VSS
A10
VSS
V10
VSS
G12
VSS
L12
VSS
FBD_VREF1
H1
VREF
FBD_VREF3
H12
VREF
FBVDDQ
GND
GND
COMMON
COMMON
COMMON
COMMON
R33
R33
R32
R32
1.3K
1.3K
511
511
1%
1%
0402
0402
1%
1%
0402
0402
FBVDDQ
R1
R2
GND
FBD_CMD4
FBD_CMD6
FBD_CMD5
FBD_CMD13
FBD_CMD22
FBD_CMD24
FBD_CMD0
FBD_CMD2
VREF = FBVDDQ * R2/(R1 + R2)
DDR3: VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBVDDQ
R663
R663
511
511
1%
1%
0402
0402
COMMON
OUT
C30
C30
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
COMMON
R662
R662
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
600-10562-base-000 A
NAME
R674
04021%COMMON
04021%COMMON
R668
R668
0402
0402
1%
1%
R680
04021%COMMON
04021%COMMON
R692
04021%COMMON
04021%COMMON
R673
04021%COMMON
04021%COMMON
R667
R667
0402
0402
1%
1%
R689
04021%COMMON
04021%COMMON
R694
04021%COMMON
04021%COMMON
R1
13
R2
GND
121R674
121
121
121
COMMON
COMMON
121R680
121
121R692
121
121R673
121
121
121
COMMON
COMMON
121R689
121
121R694
121
HFDBA
FBVDDQ
C780
C780
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
1
2
13
OUT
3
4
5
PAGEID
DATE
30-DEC-2008
www.vinafix.vn
A B C D E F G H
Page12: FBD Partition Decoupling
1
2
3
Decoupling for FBD 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C796
C796
C788
C788
.047UF
.047UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C811
C811
C810
C810
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C815
C815
C814
C814
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C795
C795
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C806
C806
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C787
C787
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C807
C807
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C819
C819
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
Decoupling for FBD 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C812
C812
C794
C794
C797
C797
.1UF
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C809
C809
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C816
C816
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C808
C808
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C790
C790
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C804
C804
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C791
C791
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C803
C803
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C789
C789
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
1
2
3
4
5
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P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBD Partition Decoupling
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NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
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