Page 1
A B C D E F G H
G94-P562-A00 - GDDR3, DVI/VGA + DVI/VGA
1
2
3
4
VARIANT ASSEMBLY
SKU
B
BASE
1
sku0000
2
<UNDEFINED
3
<UNDEFINED>
4
<UNDEFINED>
5
<UNDEFINED>
6
<UNDEFINED>
7
<UNDEFINED>
8
<UNDEFINED>
9
<UNDEFINED>
10
<UNDEFINED>
11
<UNDEFINED>
12
<UNDEFINED>
13
<UNDEFINED>
14
<UNDEFINED>
15
<UNDEFINED>
Table of Contents:
Page 1: Overview
Page 2: PCI Express
Page 3: MEMORY: GPU Partition A/B
Page 4: MEMORY: GPU Partition C/D
Page 5: FBA Partition
Page 6: FBA Partition Decoupling
Page 7: FBB Partition
Page 8: FBB Partion Decoupling
Page 9: FBC Partition
Page 10: FBC Partition Decoupling
Page 11: FBD Partition
Page 12: FBD Partition Decoupling
Page 13: FB Net Properties
Page 14: DACA Interface
Page 15: DACC Interface
Page 16: IFP A/B Interface -- DVI Connector South
Page 17: IFP C/D Interface -- DVI Connector MID
Page 18: IFP E/F Interface -- Unused
Page 19: DACB Unused
Page 20: MIO A/B Interface
Page 21: MISC: GPIO, I2C, ROM, HDCP, and XTAL
Page 22: Strap Configuration
Page 23: PWR and GND Signals
Page 24: NVVDD and FBVDDQ Decoupling
Page 25: SPDIF Input, Backdrive Protection, and IFP_IOVDD Power Supply
Page 26: PS I: 3V3, 12V, and 12V_EXT Power Supply Filter
Page 27: PS II: IFP_PLLVDD, 2V5, 5V, and DDC_5V Power Supply
Page 28: PS III: FBVDDQ Power Supply
Page 29: PS IV: NVVDDV
Page 30: BLANK
Page 31: Fan Connector
Page 32: Thermal, Mechanical, and Bracket
NVPN
600-10562-base-000
600-10562-0000-000
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
G94-400 625MHz/900MHz 512MB 16Mx32 BGA136 GDDR3, DVI-I-DL+DVI-I-DL
<UNDEFINED
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED><UNDEFINED>
<UNDEFINED>
REVISION HISTORY:
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Overview
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 2
A B C D E F G H
Page2: PCI Express
12V
C799
C799
1UF
1UF
25V
25V
10%
10%
X7R
X7R
3V3
0805
0805
COMMON
COMMON
C785
C785
C784
1
C784
.1UF
.1UF
4.7UF
4.7UF
16V
16V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X7R
X7R
0603
0603
0402
0402
COMMON
COMMON
COMMON
COMMON
COMMON
GND
COMMON
2
GND
3V3_AUX
C40
.1UF
C40
.1UF
16V
0402
16V
0402
10%
10%
X7R
X7R
SNN_PE_PRSNT2_A
SNN_PE_RSVD1
SNN_PE_PRSNT2_B
SNN_PE_RSVD2
SNN_PE_RSVD3
SNN_PE_RSVD4
C798
C798
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
SNN_PE_PRSNT2_C
SNN_PE_RSVD5
3
PEX_PRSNT*
SNN_PE_RSVD6
SNN_PE_RSVD7
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
CN2
CN2
CON_X16
CON_X16
COMMON
COMMON
SMCLK
SMDAT
PERST
REFCLK
REFCLK
PERP0
PERN0
PETP0
PETN0
PERP1
PERN1
PETP1
PETN1
PERP2
PERN2
PETP2
PETN2
PERP3
PERN3
PETP3
PETN3
PERP4
PERN4
PETP4
PETN4
PERP5
PERN5
PETP5
PETN5
PERP6
PERN6
PETP6
PETN6
PERP7
PERN7
PETP7
PETN7
PERP8
PERN8
PETP8
PETN8
PERP9
PERN9
PETP9
PETN9
PERP10
PERN10
PETP10
PETN10
PERP11
PERN11
PETP11
PETN11
PERP12
PERN12
PETP12
PETN12
PERP13
PERN13
PETP13
PETN13
PERP14
PERN14
PETP14
PETN14
PERP15
PERN15
PETP15
PETN15
PEX_TRST*
B9
PEX_TCLK
A5
PEX_TDI
A6
PEX_TDO
A7
PEX_TMS
A8
PEX_SMCLK
B5
PEX_SMDAT
B6
SNN_PEX_WAKE*
B11
WAKE
PEX_RST*
A11
PEX_REFCLK
A13
PEX_REFCLK*
A14
PEX_TXX0
A16
PEX_TXX0*
A17
PEX_RX0
B14
PEX_RX0*
B15
PEX_TXX1
A21
PEX_TXX1*
A22
PEX_RX1
B19
PEX_RX1*
B20
PEX_TXX2
A25
PEX_TXX2*
A26
PEX_RX2
B23
PEX_RX2*
B24
PEX_TXX3
A29
PEX_TXX3*
A30
PEX_RX3
B27
PEX_RX3*
B28
PEX_TXX4
A35
PEX_TXX4*
A36
PEX_RX4
B33
PEX_RX4*
B34
PEX_TXX5
A39
PEX_TXX5*
A40
PEX_RX5
B37
PEX_RX5*
B38
PEX_TXX6
A43
PEX_TXX6*
A44
PEX_RX6
B41
PEX_RX6*
B42
PEX_TXX7
A47
PEX_TXX7*
A48
PEX_RX7
B45
PEX_RX7*
B46
PEX_TXX8
A52
PEX_TXX8*
A53
PEX_RX8
B50
PEX_RX8*
B51
PEX_TXX9
A56
PEX_TXX9*
A57
PEX_RX9
B54
PEX_RX9*
B55
PEX_TXX10
A60
PEX_TXX10*
A61
PEX_RX10
B58
PEX_RX10*
B59
PEX_TXX11
A64
PEX_TXX11*
A65
PEX_RX11
B62
PEX_RX11*
B63
PEX_TXX12
A68
PEX_TXX12*
A69
PEX_RX12
B66
PEX_RX12*
B67
PEX_TXX13
A72
PEX_TXX13*
A73
PEX_RX13
B70
PEX_RX13*
B71
PEX_TXX14
A76
PEX_TXX14*
A77
PEX_RX14
B74
PEX_RX14*
B75
PEX_TXX15
A80
PEX_TXX15*
A81
PEX_RX15
B78
PEX_RX15*
B79
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
OUT
OUT
C771
0402
0402
X7R
X7R
C761
0402
0402
X7R
X7R
C758 .1UF
C758 .1UF
0402
0402
X7R
X7R
C744
C744
0402
0402
X7R
X7R
C729
C729
0402
0402
X7R
X7R
C716
C716
X7R
X7R
C696
C696
0402
0402
X7R
X7R
C677
C677
0402
0402
X7R
X7R
C650
C650
0402
0402
X7R
X7R
C632
C632
0402
0402
X7R
X7R
C617
C617
0402
0402
X7R
X7R
C609
C609
0402
0402
X7R
X7R
C601
C601
0402
0402
X7R
X7R
C599
C599
0402
0402
X7R
X7R
C595
C595
0402
0402
X7R
X7R
C591
C591
0402
0402
X7R
X7R
R644
R644
0
0
5%
5%
0402
0402
COMMON
COMMON
21
21
OUT
.1UFC771
.1UF
C762
C762
16V
16V
10%
10%
0402
0402
.1UFC761
.1UF
C760
C760
16V
16V
10%
10%
C755
C755
16V
16V
10%
10%
.1UF
.1UF
C739
C739
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C725
C725
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C711
C711
16V0402
16V0402
10%
10%
0402
0402
.1UF
.1UF
C693
C693
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C667
C667
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C647
C647
16V
16V
10%
10%
.1UF
.1UF
C627
C627
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C615
C615
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C607
C607
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C600
C600
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C598
C598
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C594
C594
16V
16V
10%
10%
0402
0402
.1UF
.1UF
C588
C588
16V
16V
10%
10%
0402
0402
B1
+12V
B2
+12V
A2
+12V
A3
+12V
B3
+12V/RSVD
B8
+3V3
A9
+3V3
A10
+3V3
B10
+3V3AUX
A1
PRSNT1
B17
PRSNT2
B12
RSVD
B4
GND
A4
GND
B7
GND
A12
GND
B13
GND
A15
GND
B16
GND
B18
GND
A18
GND
GND
B31
PRSNT2
A19
RSVD
B30
RSVD
A32
RSVD
A20
GND
B21
GND
B22
GND
A23
GND
A24
GND
B25
GND
B26
GND
A27
GND
A28
GND
B29
GND
A31
GND
B32
GND
B48
PRSNT2
A33
RSVD
A34
GND
B35
GND
B36
GND
A37
GND
A38
GND
B39
GND
B40
GND
A41
GND
A42
GND
B43
GND
B44
GND
A45
GND
A46
GND
B47
GND
B49
GND
A49
GND
GND
B81
PRSNT2
A50
RSVD
B82
RSVD
A51
GND
B52
GND
B53
GND
A54
GND
A55
GND
B56
GND
B57
GND
A58
GND
A59
GND
B60
GND
B61
GND
A62
GND
A63
GND
B64
GND
B65
GND
A66
GND
A67
GND
B68
GND
B69
GND
A70
GND
A71
GND
B72
GND
B73
GND
A74
GND
A75
GND
B76
GND
B77
GND
A78
GND
A79
GND
B80
GND
A82
GND
GND
END OF X1
END OF X1
END OF X4
END OF X4
END OF X8
END OF X8
END OF X16
END OF X16
TRST* JTAG1
TCLK JTAG2
TDI JTAG3
TDO JTAG4
TMS JTAG5
2,25
.1UF
.1UF
16V
16V
0402
0402
.1UF
.1UF
16V0402
16V0402
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V0402
16V0402
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
.1UF
.1UF
16V
16V
SNN_PEX_CLKREQ*
10%
10%
COMMON
COMMON
X7R
X7R
.1UF
.1UF
10%
10%
16V
16V
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
10%
10%
COMMON
COMMON
X7R
X7R
COMMON
COMMON
PEX_TX0
PEX_TX0*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
R639
0402 COMMON
0402 COMMON
R637
0402 COMMON
0402 COMMON
R643
0402 COMMON
0402 COMMON
R645
R645
0402
0402
R648 0
R648 0
0402
0402
PEX_TX1
PEX_TX1*
05%R639
0
JTAG_TRST*
5%
05%R637
0
JTAG_TCLK
5%
0R643
0
JTAG_TDI
5%
5%
0
0
JTAG_TDO
COMMON
COMMON
5%
5%
JTAG_TMS
COMMON
COMMON
5%
5%
G1A
G1A
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
1/19 PCI_EXPRESS
1/19 PCI_EXPRESS
AW10
PEX_RST
AY10
PEX_CLKREQ
AW11
PEX_REFCLK
AW12
PEX_REFCLK
AU13
PEX_TX0
AV13
PEX_TX0
AY12
PEX_RX0
BA12
PEX_RX0
AW13
PEX_TX1
AW14
PEX_TX1
BB12
PEX_RX1
BB13
PEX_RX1
AW15
PEX_TX2
AV15
PEX_TX2
BA13
PEX_RX2
AY13
PEX_RX2
AV16
PEX_TX3
AW16
PEX_TX3
AY15
PEX_RX3
BA15
PEX_RX3
AW17
PEX_TX4
AW18
PEX_TX4
BB15
PEX_RX4
BB16
PEX_RX4
AV18
PEX_TX5
AU18
PEX_TX5
BA16
PEX_RX5
AY16
PEX_RX5
AV19
PEX_TX6
AW19
PEX_TX6
AY18
PEX_RX6
BA18
PEX_RX6
AW20
PEX_TX7
AW21
PEX_TX7
BB18
PEX_RX7
BB19
PEX_RX7
AV21
PEX_TX8
AU21
PEX_TX8
BA19
PEX_RX8
AY19
PEX_RX8
AV22
PEX_TX9
AW22
PEX_TX9
AY21
PEX_RX9
BA21
PEX_RX9
AW23
PEX_TX10
AW24
PEX_TX10
BB21
PEX_RX10
BB22
PEX_RX10
AV24
PEX_TX11
AU24
PEX_TX11
BA22
PEX_RX11
AY22
PEX_RX11
AU25
PEX_TX12
AV25
PEX_TX12
AY24
PEX_RX12
BA24
PEX_RX12
AW25
PEX_TX13
AW26
PEX_TX13
BB24
PEX_RX13
BB25
PEX_RX13
AW27
PEX_TX14
AV27
PEX_TX14
BA25
PEX_RX14
AY25
PEX_RX14
AU27
PEX_TX15
AT27
PEX_TX15
AY27
PEX_RX15
BA27
PEX_RX15
C GE
3V3
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
VDD33
VDD33
VDD33
VDD33
VDD33
VDD_SENSE
GND_SENSE
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
PEX_PLLVDD
TESTMODE
PEX_CAL_PD_VDDQ
PEX_CAL_PU_GND
PEX_TERMP
ASSEMBLY
PAGE DETAIL
J501
J501
FEMALE
FEMALE
1.274MM
1.274MM
0
0
CON_HDR_002X004_TH
CON_HDR_002X004_TH
COMMON
COMMON
TMS2TRST*
1
TDI4GND
3
KEY
KEY
VCC
5
TDO8TCK
7
AT18
AT24
AT25
AU15
AU16
AU19
AU22
AM17
AM18
AM19
AM20
AM24
AM25
AM26
AM27
AM28
AP18
AP19
AP21
AP22
AP24
AP25
AP27
AR15
AR16
AR18
AR19
AR21
AR22
AR24
AR25
AR27
AT15
AT16
AT19
AT21
AT22
L11
L12
L13
M11
N11
NVVDD_SENSE_GPU
AJ22
SNN_NVVDD_GND_SENSE_GPU
AJ21
PEX_PLL_CLK_OUT
AP16
PEX_PLL_CLK_OUT*
AP17
12MIL
PEX_PLLVDD
AM16
GPU_TESTMODE
BB27
5MIL
PEX_CAL_PD_VDDQ
AM21
PEX_CAL_PU_GND
AM22
5MIL
PEX_TERMP
AM23
5MIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PCI Express
3V3
R642
R642
10K
10K
5%
5%
0402
0402
COMMON
COMMON
GND
Place near balls
C646
C646
C645
C645
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C657
C657
C673
C673
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
Matching Rule of Thumb
4 inch from Top of Gold Fingers to GPU
*2 inch Lane to Lane Skew
*No real Skew rule, but reducing the skew will minimize latency
Place near balls
R585
04025%COMMON
04025%COMMON
R587
R587
0402
0402
C710
C710
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
SHOULD BE PLACED ON THE BOTTOM LAYER
SHOULD BE PLACED ON THE BOTTOM LAYER
R592
R592
10KR585
10K
1%
1%
R649
R649
10K
10K
5%
5%
0402
0402
COMMON
COMMON
2.49K
2.49K
COMMON
COMMON
R638
R638
180
180
5%
5%
0402
0402
COMMON
COMMON
R636
R636
R635
R635
10K
10K
270
270
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND
C651
C651
C685
C685
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
C663
C663
C664
C664
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
VDD33
C699
C699
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
OUT
200
200
COMMON0402
COMMON0402
5%
5%
C675
C675
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R589 2.49K
R589 2.49K
COMMON0402
COMMON0402
1%
1%
R588
2.49KR588
2.49K
COMMON
0402
COMMON
0402
1%
1%
2,29
C687
C687
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
PEX_VDD
GND
JTAG
OUT
OUT
OUT
IN
OUT
C676
C676
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C690
C690
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C702
C702
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
GND
C666
C666
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C689
C689
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C662
C662
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
PEX_REFCLK
OUT
PEX_REFCLK*
OUT
2,21
2,21
2,21
2,21
2,21
PEX_VDD
3V3
C700
C700
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
PEX_VDD
LB505
10nHLB505
10nH
COMMONIND_SMD_0402
COMMONIND_SMD_0402
C669
C669
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
2,25
2,29
PEX_TXX0
OUT
PEX_TXX0*
OUT
PEX_TXX1
OUT
PEX_TXX1*
OUT
PEX_TXX2
OUT
PEX_TXX2*
OUT
PEX_TXX3
OUT
PEX_TXX3*
OUT
PEX_TXX4
OUT
PEX_TXX4*
OUT
PEX_TXX5
OUT
PEX_TXX5*
OUT
PEX_TXX6
OUT
PEX_TXX6*
OUT
PEX_TXX7
OUT
PEX_TXX7*
OUT
PEX_TXX8
OUT
PEX_TXX8*
OUT
PEX_TXX9
OUT
PEX_TXX9*
OUT
PEX_TXX10
OUT
PEX_TXX10*
OUT
PEX_TXX11
OUT
PEX_TXX11*
OUT
PEX_TXX12
OUT
PEX_TXX12*
OUT
PEX_TXX13
OUT
PEX_TXX13*
OUT
PEX_TXX14
OUT
PEX_TXX14*
OUT
PEX_TXX15
OUT
PEX_TXX15*
OUT
PEX_RX0
OUT
PEX_RX0*
OUT
PEX_RX1
OUT
PEX_RX1*
OUT
PEX_RX2
OUT
PEX_RX2*
OUT
PEX_RX3
OUT
PEX_RX3*
OUT
PEX_RX4
OUT
PEX_RX4*
OUT
PEX_RX5
OUT
PEX_RX5*
OUT
PEX_RX6
OUT
PEX_RX6*
OUT
PEX_RX7
OUT
PEX_RX7*
OUT
PEX_RX8
OUT
PEX_RX8*
OUT
PEX_RX9
OUT
PEX_RX9*
OUT
PEX_RX10
OUT
PEX_RX10*
OUT
PEX_RX11
OUT
PEX_RX11*
OUT
PEX_RX12
OUT
PEX_RX12*
OUT
PEX_RX13
OUT
PEX_RX13*
OUT
PEX_RX14
OUT
PEX_RX14*
OUT
PEX_RX15
OUT
PEX_RX15*
OUT
PEX_TX0
OUT
PEX_TX0*
OUT
PEX_TX1
OUT
PEX_TX1*
OUT
PEX_TX2
OUT
PEX_TX2*
OUT
PEX_TX3
OUT
PEX_TX3*
OUT
PEX_TX4
OUT
PEX_TX4*
OUT
PEX_TX5
OUT
PEX_TX5*
OUT
PEX_TX6
OUT
PEX_TX6*
OUT
PEX_TX7
OUT
PEX_TX7*
OUT
PEX_TX8
OUT
PEX_TX8*
OUT
PEX_TX9
OUT
PEX_TX9*
OUT
PEX_TX10
OUT
PEX_TX10*
OUT
PEX_TX11
OUT
PEX_TX11*
OUT
PEX_TX12
OUT
PEX_TX12*
OUT
PEX_TX13
OUT
PEX_TX13*
OUT
PEX_TX14
OUT
PEX_TX14*
OUT
PEX_TX15
OUT
PEX_TX15*
OUT
PEX_PLL_CLK_OUT
OUT
PEX_PLL_CLK_OUT*
OUT
PEX_RST*
OUT
PEX_PRSNT*
OUT
GPU_TESTMODE
OUT
NVVDD_SENSE_GPU
OUT
VOLTAGENET MAX_CURRENT
PEX_PLLVDD
IN
1.1V
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
NAME
NV_IMPEDANCE DIFFPAIRNV_CRITICALNET
1 PEX_REFCLK
90DIFF
1 PEX_REFCLK
90DIFF
1
90DIFF
90DIFF
1
90DIFF
1 PEX_TXX1
90DIFF
1 PEX_TXX2
90DIFF
1
90DIFF
1
90DIFF
1 PEX_TXX3
90DIFF
1
90DIFF
1 PEX_TXX4
90DIFF
1 PEX_TXX5
90DIFF
1
90DIFF
1 PEX_TXX6
90DIFF
1
90DIFF
1 PEX_TXX7
90DIFF
1 PEX_TXX7
90DIFF
1 PEX_TXX8
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1 PEX_TXX10
90DIFF
1
90DIFF
1
90DIFF
90DIFF
1 PEX_TXX12
90DIFF
1 PEX_TXX13
90DIFF
1 PEX_TXX13
90DIFF
1 PEX_TXX14
90DIFF
1
90DIFF
1 PEX_TXX15
90DIFF
1
90DIFF
1 PEX_RX0
90DIFF
1 PEX_RX0
90DIFF
1
90DIFF
1 PEX_RX1
90DIFF
1 PEX_RX2
90DIFF
1 PEX_RX2
90DIFF
1
90DIFF
1 PEX_RX3
90DIFF
1 PEX_RX4
90DIFF
1 PEX_RX4
90DIFF
1
90DIFF
1 PEX_RX5
90DIFF
1 PEX_RX6
90DIFF
1
90DIFF
1 PEX_RX7
90DIFF
1
90DIFF
1 PEX_RX8
90DIFF
1 PEX_RX8
90DIFF
1 PEX_RX9
90DIFF
90DIFF
1 PEX_RX10
90DIFF
90DIFF
1 PEX_RX11
90DIFF
1 PEX_RX11
90DIFF
1 PEX_RX12
90DIFF
1 PEX_RX12
90DIFF
1 PEX_RX13
90DIFF
1 PEX_RX13
90DIFF
1 PEX_RX14
90DIFF
1 PEX_RX14
90DIFF
1 PEX_RX15
90DIFF
1 PEX_RX15
90DIFF
1 PEX_TX0
90DIFF
1 PEX_TX0
90DIFF
1 PEX_TX1
90DIFF
1 PEX_TX1
90DIFF
1
90DIFF
1 PEX_TX2
90DIFF
1
90DIFF
1 PEX_TX3
90DIFF
1
90DIFF
1 PEX_TX4
90DIFF
1 PEX_TX5
90DIFF
1 PEX_TX5
90DIFF
90DIFF
90DIFF
1 PEX_TX7
90DIFF
1
90DIFF
1 PEX_TX8
90DIFF
90DIFF
1
90DIFF
1 PEX_TX9
90DIFF
90DIFF
1 PEX_TX10
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1 PEX_PLL_CLK_OUT
90DIFF
1
90DIFF
3
50OHM
3
50OHM
3
50OHM
5MIL
600-10562-base-000 A
PEX_TXX0
PEX_TXX01
PEX_TXX1
PEX_TXX2
PEX_TXX3
PEX_TXX4
PEX_TXX5
PEX_TXX6
PEX_TXX8
PEX_TXX9
PEX_TXX9
PEX_TXX10
PEX_TXX11
PEX_TXX11
PEX_TXX121
PEX_TXX14
PEX_TXX15
PEX_RX1
PEX_RX3
PEX_RX5
PEX_RX6
PEX_RX7
PEX_RX91
PEX_RX101
PEX_TX2
PEX_TX3
PEX_TX4
PEX_TX61
PEX_TX61
PEX_TX7
PEX_TX81
PEX_TX9
PEX_TX101
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX131
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15
PEX_PLL_CLK_OUT
MIN_WIDTH
12MIL0.16A
PAGEID
DATE
HFDBA
1
2
3
4
5
30-DEC-2008
www.vinafix.vn
Page 3
A B C D E F G H
Page3: MEMORY: GPU Partition A/B
1
5,13
2
3
4
5
FBA_D[63..0]
BI
5,13
5,13
FBA_DQM[7..0]
OUT
FBA_DQS_WP[7..0]
OUT
5,13
FBA_DQS_RN[7..0]
IN
FBVDDQ
R572
R572
511
511
1%
1%
13
0402
0402
COMMON
COMMON
R573
R573
C603
C603
1.3K
1.3K
.1UF
.1UF
16V
16V
1%
1%
0402
0402
10%
10%
COMMON
COMMON
X7R
X7R
0402
0402
COMMON
COMMON
FBA_D0
0
FBA_D1
1
FBA_D2
2
FBA_D3
3
FBA_D4
4
FBA_D5
5
FBA_D6
6
FBA_D7
7
FBA_D8
8
FBA_D9
9
FBA_D10
10
FBA_D11
11
FBA_D12
12
FBA_D13
13
FBA_D14
14
FBA_D15
15
FBA_D16
16
FBA_D17
17
FBA_D18
18
FBA_D19
19
FBA_D20
20
FBA_D21
21
FBA_D22
22
FBA_D23
23
FBA_D24
24
FBA_D25
25
FBA_D26
26
FBA_D27
27
FBA_D28
28
FBA_D29
29
FBA_D30
30
FBA_D31
31
FBA_D32
32
FBA_D33
33
FBA_D34
34
FBA_D35
35
FBA_D36
36
FBA_D37
37
FBA_D38
38
FBA_D39
39
FBA_D40
40
FBA_D41
41
FBA_D42
42
FBA_D43
43
FBA_D44
44
FBA_D45
45
FBA_D46
46
FBA_D47
47
FBA_D48
48
FBA_D49
49
FBA_D50
50
FBA_D51
51
FBA_D52
52
FBA_D53
53
FBA_D54
54
FBA_D55
55
FBA_D56
56
FBA_D57
57
FBA_D58
58
FBA_D59
59
FBA_D60
60
FBA_D61
61
FBA_D62
62
FBA_D63
63
FBA_DQM0
0
FBA_DQM1
1
FBA_DQM2
2
FBA_DQM3
3
FBA_DQM4
4
FBA_DQM5
5
FBA_DQM6
6
FBA_DQM7
7
FBA_DQS_WP0
0
FBA_DQS_WP1
1
FBA_DQS_WP2
2
FBA_DQS_WP3
3
FBA_DQS_WP4
4
FBA_DQS_WP5
5
FBA_DQS_WP6
6
FBA_DQS_WP7
7
FBA_DQS_RN0
0
FBA_DQS_RN1
1
FBA_DQS_RN2
2
FBA_DQS_RN3
3
FBA_DQS_RN4
4
FBA_DQS_RN5
5
FBA_DQS_RN6
6
FBA_DQS_RN7
7
SNN_FBA_DBI<0>
SNN_FBA_DBI<1>
SNN_FBA_DBI<2>
SNN_FBA_DBI<3>
SNN_FBA_DBI<4>
SNN_FBA_DBI<5>
SNN_FBA_DBI<6>
SNN_FBA_DBI<7>
OUT
FB_VREF
AM34
AW33
AW36
AW28
AW31
AW29
AM39
AW32
AM36
AW34
AW35
AL34
AK35
AK36
AJ34
AH34
AH35
AJ36
AK37
AL39
AL41
AL42
AK42
AJ39
AH39
AH41
AH42
AN35
AP36
AP37
AR37
AL35
AL36
AL37
AP41
AP42
AN39
AN40
AN41
AN42
AR40
AT39
AR31
AP32
AR33
AT31
AT34
AU34
AU35
AU31
BB33
BA33
AY33
BA34
BB34
AY35
AU30
AP28
AP31
AR28
AP29
AR30
AT30
BA31
BB31
BB30
BB28
BA28
AY28
AJ37
AP35
AP40
AR34
AY34
AU29
AH36
AK41
AP38
AT33
AV34
AT28
AY30
AH37
AK40
AN36
AP39
AT32
AU28
BA30
AH38
AL38
AN38
AR39
AV33
AT29
AV31
L32
G1B
G1B
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
2/19 FBA
2/19 FBA
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7
FB_VREF
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_DEBUG
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBA_WCK0
FBA_WCK0
FBA_WCK1
FBA_WCK1
FBA_WCK2
FBA_WCK2
FBA_WCK3
FBA_WCK3
FB_DLLAVDD0
FB_PLLAVDD0
AA32
AB32
AC32
AD32
AD34
AE32
AF32
AG32
AG34
AK34
AN34
AP30
AP33
J10
J13
J16
J19
J24
J27
J30
AT40
AU38
AT38
BA39
AV37
BB39
AW38
AW42
AW39
AY41
AU39
AV36
BA40
AY39
AU40
BA37
AY36
AY37
AT37
AU36
AV39
AY38
AV40
AU42
AW40
AU41
AW41
BB37
AW37
AY42
BB40
AT36
AT41
AT42
BA36
BB36
AK38
AK39
AM37
AN37
AU32
AU33
AV30
AW30
AH32
AJ32
FBVDDQ
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
SNN_FBA_CMD<7>
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
SNN_FBA_CMD<26>
FBA_CMD27
SNN_FBA_CMD<28>
SNN_FBA_CMD<29>
SNN_FBA_CMD<30>
FBA_DEBUG
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
SNN_FBA_WDS0
SNN_FBA_WDS0*
SNN_FBA_WDS1
SNN_FBA_WDS1*
SNN_FBA_WDS2
SNN_FBA_WDS2*
SNN_FBA_WDS3
SNN_FBA_WDS3*
FB_PLLAVDD0
FBA_CMD[27..0]
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
5,13
OUT
5,13
OUT
5,13
OUT
5,13
OUT
C630
C630
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
GND
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
OUT
BGA136[31..0] BGA136[63..32] ADDR
CMD1 CMD1 RAS*
CMD10 CMD10 CAS*
CMD11 CMD11 WE*
CMD8 CMD8 CS0*
CMD19 CMD19 A<0>
CMD25 CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 CMD21 A<6>
CMD16 CMD16 A<7>
CMD23 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD9 CMD9 A<11>
CMD12 CMD12 BA0
CMD3 CMD3 BA1
CMD27 CMD27 BA2
CMD18 CMD18 CKE
CMD15 CMD15 RST
13
OUT
C629
C629
C626
C626
1UF
1UF
4.7UF
4.7UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0402
0402
COMMON
COMMON
COMMON
COMMON
ASSEMBLY
PAGE DETAIL
FBB_D[63..0]
BI
7,13
FBB_DQM[7..0]
OUT
FBB_DQS_WP[7..0]
7,13
OUT
7,13
FBB_DQS_RN[7..0]
IN
PEX_VDD
C637
C637
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
SNN_FBB_DBI<0>
SNN_FBB_DBI<1>
SNN_FBB_DBI<2>
SNN_FBB_DBI<3>
SNN_FBB_DBI<4>
SNN_FBB_DBI<5>
SNN_FBB_DBI<6>
SNN_FBB_DBI<7>
5,13
CMD-Addr Map
LB503
IND_SMD_0402COMMON
IND_SMD_0402COMMON
7,13
220R@100MHZLB503
220R@100MHZ
GND
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MEMORY: GPU Partition A/B
C40
E39
F37
H37
G38
G39
G40
H39
C41
D40
D41
C42
D42
H40
G41
G42
J37
K37
J38
J39
L36
M34
M35
M36
J40
J41
J42
K39
L39
M38
M39
M40
W35
W36
W37
W38
AA34
AA35
AA36
AA37
W40
AA40
AA41
AA42
AB40
AB41
AB42
AD40
AB34
AB35
AB36
AB37
AE35
AE36
AE37
AG36
AD41
AD42
AE38
AF39
AE42
AG40
AG41
AG42
G37
F41
L37
K42
AA38
AC39
AE34
AE41
F39
F40
K35
K41
Y39
AB39
AD36
AE40
F38
E40
K36
K40
W39
AB38
AD35
AE39
H36
F42
L34
K38
AA39
AD39
AG35
AG39
G1C
G1C
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
3/19 FBB
3/19 FBB
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
FBB_DBI0
FBB_DBI1
FBB_DBI2
FBB_DBI3
FBB_DBI4
FBB_DBI5
FBB_DBI6
FBB_DBI7
CALIBRATION PIN
FB_CALx_PD_VDDQ
FB_CALx_PU_GND
FB_CALx_TERM_GND 40
VREF RATIO
0.7 FBVDDQ
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
DDR3
60
40
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_DEBUG
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
FBB_WCK0
FBB_WCK0
FBB_WCK1
FBB_WCK1
FBB_WCK2
FBB_WCK2
FBB_WCK3
FBB_WCK3
FBVDDQ
J33
K34
K9
L17
L18
L19
L20
L23
L24
L25
L26
L27
FBB_CMD0
N41
FBB_CMD1
R39
FBB_CMD2
N42
FBB_CMD3
V37
FBB_CMD4
T41
FBB_CMD5
T42
FBB_CMD6
V38
SNN_FBB_CMD<7>
R38
FBB_CMD8
N40
FBB_CMD9
U39
FBB_CMD10
N39
FBB_CMD11
V40
FBB_CMD12
R41
FBB_CMD13
V39
FBB_CMD14
P39
FBB_CMD15
V36
FBB_CMD16
V41
FBB_CMD17
T39
FBB_CMD18
T38
FBB_CMD19
T35
FBB_CMD20
T36
FBB_CMD21
T40
FBB_CMD22
R37
FBB_CMD23
M41
FBB_CMD24
T37
FBB_CMD25
M42
SNN_FBB_CMD<26>
R36
FBB_CMD27
V35
SNN_FBB_CMD<28>
V42
SNN_FBB_CMD<29>
R42
SNN_FBB_CMD<30>
R40
FBB_DEBUG
R34
FBB_CLK0
N37
FBB_CLK0*
N38
FBB_CLK1
U34
FBB_CLK1*
V34
SNN_FBB_WDS0
J35
SNN_FBB_WDS0*
J36
SNN_FBB_WDS1
N35
SNN_FBB_WDS1*
N36
SNN_FBB_WDS2
W41
SNN_FBB_WDS2*
W42
SNN_FBB_WDS3
AD37
SNN_FBB_WDS3*
AD38
FB_CAL_PD_VDDQ
M32
FB_CAL_PU_GND
N32
FB_CAL_TERM_GND
P32
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
NAME
FBB_CMD[27..0]
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
TP502TP502TP501TP501
7,13
OUT
7,13
OUT
7,13
OUT
7,13
OUT
R583
R583
0402
0402
1%
1%
R579
R579
0402
0402
1%
1%
R578
R578
0402
0402
1%
1%
600-10562-base-000 A
54.9
54.9
COMMON
COMMON
40.2
40.2
COMMON
COMMON
40.2
40.2
COMMON
COMMON
HFDBA
OUT
FBVDDQ
GND
1
2
7,13
3
4
5
PAGEID
DATE
30-DEC-2008
www.vinafix.vn
Page 4
A B C D E F G H
Page4: MEMORY: GPU Partition C/D
1
9,13
2
3
4
FBC_D[63..0]
BI
9,13
9,13
9,13
FBC_DQM[7..0]
OUT
FBC_DQS_WP[7..0]
OUT
FBC_DQS_RN[7..0]
IN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
SNN_FBC_DBI<0>
SNN_FBC_DBI<1>
SNN_FBC_DBI<2>
SNN_FBC_DBI<3>
SNN_FBC_DBI<4>
SNN_FBC_DBI<5>
SNN_FBC_DBI<6>
SNN_FBC_DBI<7>
5
G1D
G1D
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
J21
H21
G21
F21
F18
G18
H18
G16
B16
A16
B19
A19
D17
E18
A18
C16
H24
G24
F24
E24
J22
H22
G22
F22
C24
C22
B22
A22
C21
B21
A21
C19
F34
F33
E34
D34
G32
J31
H31
G31
C34
B34
A34
D33
D32
E31
D31
C31
D39
D38
G36
F35
E36
D36
C36
D35
B40
C39
B39
A40
A39
C35
B36
A36
J18
B18
E22
D20
F32
A33
F36
B37
G19
C18
D23
D21
H33
B33
D37
C37
H19
D18
D24
E21
G33
C33
E37
C38
H16
D16
D22
D19
J32
E33
G35
A37
4/19 FBC
4/19 FBC
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
FBC_DBI0
FBC_DBI1
FBC_DBI2
FBC_DBI3
FBC_DBI4
FBC_DBI5
FBC_DBI6
FBC_DBI7
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_DEBUG
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
FBC_WCK0
FBC_WCK0
FBC_WCK1
FBC_WCK1
FBC_WCK2
FBC_WCK2
FBC_WCK3
FBC_WCK3
FB_DLLAVDD1
FB_PLLAVDD1
FBVDDQ
N34
N9
R32
T32
T34
U32
V32
W32
W34
Y32
FBC_CMD0
C25
FBC_CMD1
A27
FBC_CMD2
E25
FBC_CMD3
D30
FBC_CMD4
D28
FBC_CMD5
E28
FBC_CMD6
G27
SNN_FBC_CMD<7>
D27
FBC_CMD8
C30
FBC_CMD9
B28
FBC_CMD10
B25
FBC_CMD11
A30
FBC_CMD12
D26
FBC_CMD13
F27
FBC_CMD14
F25
FBC_CMD15
B31
FBC_CMD16
B30
FBC_CMD17
D29
FBC_CMD18
A28
FBC_CMD19
E27
FBC_CMD20
C27
FBC_CMD21
G28
FBC_CMD22
B27
FBC_CMD23
G25
FBC_CMD24
H27
FBC_CMD25
H25
SNN_FBC_CMD<26>
A25
FBC_CMD27
A31
SNN_FBC_CMD<28>
F28
SNN_FBC_CMD<29>
C28
SNN_FBC_CMD<30>
D25
FBC_DEBUG
J28
FBC_CLK0
J26
FBC_CLK0*
J25
FBC_CLK1
F30
FBC_CLK1*
E30
SNN_FBC_WDS0
F19
SNN_FBC_WDS0*
E19
SNN_FBC_WDS1
B24
SNN_FBC_WDS1*
A24
SNN_FBC_WDS2
H30
SNN_FBC_WDS2*
G30
SNN_FBC_WDS3
H34
SNN_FBC_WDS3*
G34
FB_PLLAVDD1
L21
L22
FBC_CMD[27..0]
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
TP503TP503
9,13
OUT
9,13
OUT
9,13
OUT
9,13
OUT
C672
C672
C671
C671
.1UF
.1UF
1UF
1UF
16V
16V
6.3V
6.3V
10%
10%
10%
10%
X7R
X7R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
9,13
OUT
BGA136[31..0] BGA136[63..32] ADDR
CMD1 CMD1 RAS*
CMD10 CMD10 CAS*
CMD11 CMD11 WE*
CMD8 CMD8 CS0*
CMD19 CMD19 A<0>
CMD25 CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 CMD21 A<6>
CMD16 CMD16 A<7>
CMD23 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD9 CMD9 A<11>
CMD12 CMD12 BA0
CMD3 CMD3 BA1
CMD27 CMD27 BA2
CMD18 CMD18 CKE
CMD15 CMD15 RST
13
OUT
LB504
C660
C660
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
CMD-Addr Map
220R@100MHZLB504
220R@100MHZ
COMMONIND_SMD_0402
COMMONIND_SMD_0402
11,13
GND
11,13
11,13
11,13
PEX_VDD
GND
FBD_D[63..0]
BI
FBD_DQM[7..0]
OUT
FBD_DQS_WP[7..0]
OUT
FBD_DQS_RN[7..0]
IN
C649
C649
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63
FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7
FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7
FBD_DQS_RN0
FBD_DQS_RN1
FBD_DQS_RN2
FBD_DQS_RN3
FBD_DQS_RN4
FBD_DQS_RN5
FBD_DQS_RN6
FBD_DQS_RN7
SNN_FBD_DBI<0>
SNN_FBD_DBI<1>
SNN_FBD_DBI<2>
SNN_FBD_DBI<3>
SNN_FBD_DBI<4>
SNN_FBD_DBI<5>
SNN_FBD_DBI<6>
SNN_FBD_DBI<7>
M9
N8
N7
P9
R9
R8
P7
N6
M4
M2
M1
N1
P4
R4
R2
R1
K8
J7
J6
H6
L9
M8
M7
M6
J2
J1
K4
K3
K2
K1
H3
G4
H12
J11
H10
G12
G9
F9
F8
F12
A10
B10
C10
B9
A9
D10
D7
C8
F13
J15
J12
H15
D15
J14
H13
G13
D12
B12
A12
A13
D14
A15
B15
C15
P6
L4
J8
J3
H9
C9
F14
D11
R7
N2
L7
J5
G10
E9
G15
C13
R6
N3
K7
J4
G11
D9
F15
B13
R5
M5
K5
H4
E10
D8
G14
E12
G1E
G1E
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
5/19 FBD
5/19 FBD
FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63
FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7
FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7
FBD_DQS_RN0
FBD_DQS_RN1
FBD_DQS_RN2
FBD_DQS_RN3
FBD_DQS_RN4
FBD_DQS_RN5
FBD_DQS_RN6
FBD_DQS_RN7
FBD_DBI0
FBD_DBI1
FBD_DBI2
FBD_DBI3
FBD_DBI4
FBD_DBI5
FBD_DBI6
FBD_DBI7
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
FBD_CMD7
FBD_CMD8
FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25
FBD_CMD26
FBD_CMD27
FBD_CMD28
FBD_CMD29
FBD_CMD30
FBD_DEBUG
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
FBD_WCK0
FBD_WCK0
FBD_WCK1
FBD_WCK1
FBD_WCK2
FBD_WCK2
FBD_WCK3
FBD_WCK3
FB_VDDQ_SENSE
G3
F5
G5
B4
E6
A4
D5
D1
D4
C2
F4
E7
B3
C4
F3
B6
C7
C6
G6
F7
E4
C5
E3
F1
D3
F2
D2
A6
D6
C1
A3
G7
G1
G2
B7
A7
N5
N4
L6
K6
F11
F10
E13
D13
J34
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
SNN_FBD_CMD<7>
FBD_CMD8
FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25
SNN_FBD_CMD<26>
FBD_CMD27
SNN_FBD_CMD<28>
SNN_FBD_CMD<29>
SNN_FBD_CMD<30>
FBD_DEBUG
FBD_CLK0
FBD_CLK0*
FBD_CLK1
FBD_CLK1*
SNN_FBD_WDS0
SNN_FBD_WDS0*
SNN_FBD_WDS1
SNN_FBD_WDS1*
SNN_FBD_WDS2
SNN_FBD_WDS2*
SNN_FBD_WDS3
SNN_FBD_WDS3*
FBVDDQ_SENSE
FBD_CMD[27..0]
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
TP504TP504
11,13
OUT
11,13
OUT
11,13
OUT
11,13
OUT
OUT
OUT
28
1
2
11,13
3
4
5
ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
PAGE DETAIL
www.vinafix.vn
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MEMORY: GPU Partition C/D
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
PAGEID
DATE
30-DEC-2008
HFDBA
Page 5
A B C D E F G H
Page5: FBA Partition
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
FBA_CMD[27..0]
R541
R541
0
0
5%
5%
0402
0402
COMMON
COMMON
GND
13
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
3,13
IN
1
FBA_CLK0_TERM
1.8V 1.8V
C552
C552
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R532
R532
R535
R535
121
121
121
COMMON
COMMON
121
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
IN
IN
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
GND
3,13
3,13
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
2
Minimize the stub length!!
3
3,13
4
3,13
3,13
3,13
FBA_D[63..0]
BI
FBA_DQM[7..0]
BI
FBA_DQS_RN[7..0]
BI
FBA_DQS_WP[7..0]
BI
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
IN
COMMON
COMMON
CMD7 CMD7 BA2
M6E
M6E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
C553
C553
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R537
R537
243
243
1%
1%
0402
0402
COMMON
COMMON
COMMON
H3
RAS
F4
CAS
H9
WE
F9
CS0
K4
A0
H2
A1
K3
A2
M4
A3
K9
A4
H11
A5
K10
A6
L9
A7
K11
A8/AP
M9
A9
K2
A10
L4
A11
G4
BA0
G9
BA1
H10
BA2
H4
CKE
J11
CLK
J10
CLK
J2
NC/RFU
J3
A12 (32Mx32)
V4
SEN (GND)
V9
RESET
A9
MF (GND)
A4
ZQ
K1
VDDA (VDD)
K12
VDDA (VDD)
J1
VSSA (GND)
J12
VSSA (GND)
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NONMIRRORED
NONMIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBA_CMD1 FBA_CMD1
1
FBA_CMD10 FBA_CMD10
10
FBA_CMD11 FBA_CMD11
11
8
FBA_CMD19 FBA_CMD19
19
FBA_CMD25 FBA_CMD25
25
FBA_CMD22
22
FBA_CMD24
24
FBA_CMD0
0
FBA_CMD2
2
FBA_CMD21 FBA_CMD21
21
FBA_CMD16 FBA_CMD16
16
FBA_CMD23 FBA_CMD23
23
FBA_CMD20 FBA_CMD20
20
FBA_CMD17 FBA_CMD17
17
FBA_CMD9 FBA_CMD9
9
FBA_CMD12 FBA_CMD12
12
FBA_CMD3 FBA_CMD3
3
FBA_CMD27 FBA_CMD27
27
FBA_CMD18 FBA_CMD18
18
FBA_CLK0
FBA_CLK0*
SNN_FBA0_NC1 SNN_FBA1_NC1
FBA_CMD14 FBA_CMD14
14
FBA_CMD_SENA0 FBA_CMD_SENA1
FBA_CMD15 FBA_CMD15
15
FBA_CMD15
FBA_ZQ0
FBA_CMD18
R543
R543
R528
R528
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
GND
GND GND GND
FBVDDQ
C568
C568
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
M6A
M6A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBA_D0
0
FBA_D1
1
FBA_D2
2
FBA_D3
3
FBA_D4
4
FBA_D5
5
FBA_D6
6
FBA_D7
7
FBA_DQM0
FBA_DQS_RN0
FBA_DQS_WP0
FBA_D32
32
FBA_D33
33
FBA_D34
34
FBA_D35
35
FBA_D36
36
FBA_D37
37
FBA_D38
38
FBA_D39
39
FBA_DQM4
FBA_DQS_RN4
FBA_DQS_WP4
G10
F11
E11
B10
B11
C11
C10
F10
E10
D10
D11
L3
N2
R3
M3
R2
T3
T2
M2
N3
P3
P2
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M7E
M7E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
FBA_D8
8
FBA_D9
9
FBA_D10
10
FBA_D11
11
FBA_D12
12
FBA_D13
13
FBA_D14
14
FBA_D15
15
FBA_DQM1
FBA_DQS_RN1
FBA_DQS_WP1
FBA_D40
40
FBA_D41
41
FBA_D42
42
FBA_D43
43
FBA_D44
44
FBA_D45
45
FBA_D46
46
FBA_D47
47
FBA_DQM5
FBA_DQS_RN5
FBA_DQS_WP5
FBVDDQ
GND
GND
FBA_VREF0
FBA_VREF2
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511 + 1.18K)
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
R558
R558
511
511
1%
1%
0402
0402
COMMON
COMMON
R557
R557
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
M6B
M6B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
G3
DQ0
F3
DQ1
F2
DQ2
E2
DQ3
C2
DQ4
C3
DQ5
B2
DQ6
B3
DQ7
E3
DQM
D3
RDQS
D2
WDQS
M7A
M7A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
M10
DQ0
M11
DQ1
L10
DQ2
N11
DQ3
R11
DQ4
T11
DQ5
T10
DQ6
R10
DQ7
N10
DQM
P10
RDQS
P11
WDQS
C GE
GND
3,13
3,13
R1
R2
FBA_CLK1_TERM
C561
C561
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
IN
IN
ASSEMBLY
PAGE DETAIL
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R536
R536
0
0
5%
5%
0402
0402
FBVDDQ
COMMON
COMMON
GND
13
IN
DDR3:
ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
FBVDDQ
R1
R2
C51
C51
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
COMMON
COMMON
R549
R549
R555
R555
121
121
121
121
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
13
OUT
C575
C575
.1UF
.1UF
16V
16V
10%
10%
FBVDDQ
X7R
X7R
0402
0402
COMMON
COMMON
R75
R75
511
511
1%
1%
0402
0402
COMMON
COMMON
R70
R70
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
M6C
M6C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBA_D16
16
FBA_D17
17
FBA_D18
18
FBA_D19
19
FBA_D20
20
FBA_D21
21
FBA_D22
22
FBA_D23
23
FBA_DQM2
FBA_DQS_RN2
FBA_DQS_WP2
FBA_D48
48
FBA_D49
49
FBA_D50
50
FBA_D51
51
FBA_D52
52
FBA_D53
53
FBA_D54
54
FBA_D55
55
FBA_DQM6
FBA_DQS_RN6
FBA_DQS_WP6
COMMON
R10
DQ0
T11
DQ1
T10
DQ2
R11
DQ3
N11
DQ4
L10
DQ5
M11
DQ6
M10
DQ7
N10
DQM
P10
RDQS
P11
WDQS
M7B
M7B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
E2
DQ0
C2
DQ1
G3
DQ2
C3
DQ3
B3
DQ4
B2
DQ5
F2
DQ6
F3
DQ7
E3
DQM
D3
RDQS
D2
WDQS
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA Partition
FBA_D24
24
FBA_D25
25
FBA_D26
26
FBA_D27
27
FBA_D28
28
FBA_D29
29
FBA_D30
30
FBA_D31
31
FBA_DQM3FBA_DQM4
FBA_DQS_RN3
FBA_DQS_WP3
FBA_D56
56
FBA_D57
57
FBA_D58
58
FBA_D59
59
FBA_D60
60
FBA_D61
61
FBA_D62
62
FBA_D63
63
FBA_DQM7
FBA_DQS_RN7
FBA_DQS_WP7
M7D
M7D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
1
10
11
8
19
25
FBA_CMD4
4
FBA_CMD6
6
FBA_CMD5
5
FBA_CMD13
13
21
16
23
20
17
9
12
3
27
18
FBA_CLK1
FBA_CLK1*
14
15
FBA_ZQ1
C571
C571
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
COMMON
H10
RAS
F9
CAS
H4
WE
F4
CS0
K9
A0
H11
A1
K10
A2
M9
A3
K4
A4
H2
A5
K3
A6
L4
A7
K2
A8/AP
M4
A9
K11
A10
L9
A11
G9
BA0
G4
BA1
H3
BA2
H9
CKE
J11
CLK
J10
CLK
J2
NC/RFU
J3
A12 (32Mx32)
V4
SEN (GND)
V9
RESET
A9
MF (GND)
A4
ZQ
R533
R533
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
K1
VDDA (VDD)
K12
VDDA (VDD)
C555
C555
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
J1
VSSA (GND)
J12
VSSA (GND)
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
MIRRORED
MIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
GND
G12
L12
FBA_VREF1
H1
FBA_VREF3
H12
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
FBVDDQ
R71
R71
511
511
1%
1%
0402
0402
COMMON
COMMON
R72
R72
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
FBA_CMD4
FBA_CMD6FBA_CMD8 FBA_CMD8
FBA_CMD5
FBA_CMD13
FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511 + 1.18K)
R2
C52
C52
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
R544 121
R544 121
0402
0402
1%
1%
R552
04021%COMMON
04021%COMMON
R538 121
R538 121
0402
0402
1%
1%
R530 121
R530 121
0402
0402
1%
1%
R546
R546
0402
0402
1%
1%
R553 121
R553 121
0402
0402
1%
1%
R534
1%
R529 121
R529 121
1%
1%
COMMON
COMMON
121R552
121
COMMON
COMMON
COMMON
COMMON
121
121
COMMON
COMMON
COMMON
COMMON
1211%R534
121
COMMON0402
COMMON0402
COMMON0402
COMMON0402
COMMON
COMMON
COMMON
COMMON
FBVDDQ
1
2
FBVDDQ
R559
R559
511
511
R1R1
1%
1%
0402
0402
R556
R556
1.3K
1.3K
R2
1%
1%
0402
0402
GND
C572
C572
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
3
GND
M6D
M6D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
R2
DQ0
N2
DQ1
L3
DQ2
T2
M2
M3
R3
T3
N3
P3
P2
M7C
M7C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
G10
F10
F11
E11
C11
B10
B11
C10
E10
D10
D11
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
PAGEID
DATE
30-DEC-2008
HFDBA
4
5
www.vinafix.vn
Page 6
A B C D E F G H
Page6: FBA Partition Decoupling
1
2
Decoupling for FBA 31..0
FBVDDQ
C564
C564
C570
C570
C573
C573
C539
C539
.047UF
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C540
C540
C545
C545
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C538
C538
C565
C565
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
3
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C547
C547
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C536
C536
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C532
C532
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
Decoupling for FBA 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINSPLACE NEAR MEMORY FBVDDQ PINS
C566
C566
C556
C556
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C543
C543
C537
C537
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C563
C563
C557
C557
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C558
C558
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C549
C549
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C535
C535
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C550
C550
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C533
C533
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA Partition Decoupling
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 7
A B C D E F G H
Page7: FBB Partition
FBB_CMD[27..0]
3,13
IN
CMD-Addr Map
BGA136 ADDR
1
FBB_CLK0_TERM
1.8V
C587
C587
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R566
R566
R565
R565
121
121
121
1%
1%
0402
0402
COMMON
COMMON
IN
IN
DDR3: ZQ = 6x desired output
121
1%
1%
0402
0402
COMMON
COMMON
impedence of DQ drivers
GND
3,13
3,13
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
2
MEMORY pin!!
Minimize the stub length!!
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
GND
R561
R561
0
0
5%
5%
0402
0402
COMMON
COMMON
13
IN
GND
FBB_CMD1 FBB_CMD1
1
FBB_CMD10 FBB_CMD10
10
FBB_CMD11 FBB_CMD11
11
FBB_CMD8 FBB_CMD8
8
FBB_CMD19 FBB_CMD19
19
FBB_CMD25 FBB_CMD25
25
FBB_CMD22
22
FBB_CMD24
24
FBB_CMD0
0
FBB_CMD2
2
FBB_CMD21 FBB_CMD21
21
FBB_CMD16 FBB_CMD16
16
FBB_CMD23 FBB_CMD23
23
FBB_CMD20 FBB_CMD20
20
FBB_CMD17 FBB_CMD17
17
FBB_CMD9 FBB_CMD9
9
FBB_CMD12 FBB_CMD12
12
FBB_CMD3 FBB_CMD3
3
FBB_CMD27 FBB_CMD27
27
FBB_CMD18 FBB_CMD18
18
FBB_CLK0
FBB_CLK0*
SNN_FBB0_NC1 SNN_FBB1_NC1
FBB_CMD14 FBB_CMD14
14
FBB_CMD_SENB0 FBB_CMD_SENB1
FBB_CMD15 FBB_CMD15
15
FBB_CMD15
FBB_ZQ0
R548
R548
R560
R560
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND GND GND
FBVDDQ
C590
3
C590
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
3,13
4
3,13
3,13
3,13
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBB_D[63..0]
BI
0
1
2
3
FBB_DQM[7..0]
BI
FBB_DQS_RN[7..0]
BI
FBB_DQS_WP[7..0]
BI
FBB_DQM0
0
FBB_DQM1
1
FBB_DQM2
2
FBB_DQM3
3
4
FBB_DQM5
5
FBB_DQM6
6
FBB_DQM7
7
FBB_DQS_RN0
0
FBB_DQS_RN1
1
FBB_DQS_RN2
2
FBB_DQS_RN3
3
FBB_DQS_RN4
4
FBB_DQS_RN5
5
FBB_DQS_RN6
6
FBB_DQS_RN7
7
FBB_DQS_WP0
0
FBB_DQS_WP1
1
FBB_DQS_WP2
2
FBB_DQS_WP3
3
FBB_DQS_WP4
4
FBB_DQS_WP5
5
FBB_DQS_WP6
6
FBB_DQS_WP7
7
4
5
6
7
32
33
34
35
36
37
38
39
R568
R568
243
243
1%
1%
0402
0402
COMMON
COMMON
C586
C586
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_DQM0
FBB_DQS_RN0
FBB_DQS_WP0
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_DQM4
FBB_DQS_RN4
FBB_DQS_WP4
M5E
M5E
BGA_0136_P080_140X120
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
B10
C10
B11
G10
E11
F10
C11
F11
E10
D10
D11
T2
M2
T3
R3
L3
N2
R2
M3
N3
P3
P2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NONMIRRORED
NONMIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
M5A
M5A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M8E
M8E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBVDDQ
FBB_VREF0
FBB_VREF2
VREF = FBVDDQ * R2/(R1 + R2)
DDR3: VREF = 0.70 * FBVDDQ
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_DQM1
FBB_DQS_RN1
FBB_DQS_WP1
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_DQM5
FBB_DQS_RN5
FBB_DQS_WP5
GND
COMMON
COMMON
COMMON
COMMON
GND
1.26V = 1.8V * 1.18K/(511 + 1.18K)
F3
C2
B2
C3
B3
G3
F2
E2
E3
D3
D2
T10
R10
T11
R11
M11
M10
N11
L10
N10
P10
P11
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
R570
R570
511
511
1%
1%
0402
0402
R569
R569
1.3K
1.3K
1%
1%
0402
0402
GND
M5B
M5B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M8A
M8A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
C GE
GND
3,13
3,13
R1
R2
ASSEMBLY
PAGE DETAIL
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
R1
R2
ZQ = 6x desired output
DDR3:Impedence = 240 / 6 = 40 ohm
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R551
R551
0
0
5%
5%
0402
0402
FBVDDQ
COMMON
COMMON
GND
13
IN
13
OUT
C43
C43
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBB_CLK1_TERM
1.8V
C548
C548
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
IN
IN
C589
C589
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R542
R542
R540
R540
121
121
121
121
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
13
OUT
FBVDDQ
R52
R52
511
511
1%
1%
0402
0402
COMMON
COMMON
R53
R53
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
M5C
M5C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBB_D16
16
FBB_D17
17
FBB_D18
18
FBB_D19
19
FBB_D20
20
FBB_D21
21
FBB_D22
22
FBB_D23
23
FBB_DQM2
FBB_DQS_RN2
FBB_DQS_WP2
FBB_D48
48
FBB_D49
49
FBB_D50
50
FBB_D51
51
FBB_D52
52
FBB_D53
53
FBB_D54
54
FBB_D55
55
FBB_DQM6
FBB_DQS_RN6
FBB_DQS_WP6
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBB Partition
M10
N11
M11
L10
T10
R10
T11
R11
N10
P10
P11
M8B
M8B
E2
F3
F2
G3
C3
B2
B3
C2
E3
D3
D2
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
FBB_D24
24
FBB_D25
25
FBB_D26
26
FBB_D27
27
FBB_D28
28
FBB_D29
29
FBB_D30
30
FBB_D31
31
FBB_DQM3FBB_DQM4
FBB_DQS_RN3
FBB_DQS_WP3
FBB_D56
56
FBB_D57
57
FBB_D58
58
FBB_D59
59
FBB_D60
60
FBB_D61
61
FBB_D62
62
FBB_D63
63
FBB_DQM7
FBB_DQS_RN7
FBB_DQS_WP7
1
10
11
8
19
25
4
6
5
13
21
16
23
20
17
9
12
3
27
18
14
15
FBVDDQ
GND
FBB_CMD4
FBB_CMD6
FBB_CMD13
C569
C569
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
G10
F11
F10
C11
E11
B11
B10
C10
E10
D10
D11
FBB_CLK1
FBB_CLK1*
FBB_ZQ1
L3
M2
M3
N2
R2
T2
T3
R3
N3
P3
P2
R527
R527
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
C546
C546
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
M5D
M5D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M8C
M8C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
H10
F9
H4
F4
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
G9
G4
H3
H9
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
M8D
M8D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
M12
VDD
A1
VDDQ
C1
VDDQ
E1
VDDQ
N1
VDDQ
R1
VDDQ
V1
VDDQ
C4
VDDQ
E4
VDDQ
J4
VDDQ
N4
VDDQ
R4
VDDQ
C9
VDDQ
E9
VDDQ
J9
VDDQ
N9
VDDQ
R9
VDDQ
MIRRORED
MIRRORED
A12
VDDQ
C12
VDDQ
E12
VDDQ
N12
VDDQ
R12
VDDQ
V12
VDDQ
B1
VSSQ
D1
VSSQ
P1
VSSQ
T1
VSSQ
G2
VSSQ
L2
VSSQ
B4
VSSQ
D4
VSSQ
P4
VSSQ
T4
VSSQ
B9
VSSQ
D9
VSSQ
P9
VSSQ
T9
VSSQ
G11
VSSQ
L11
VSSQ
B12
VSSQ
D12
VSSQ
P12
VSSQ
T12
VSSQ
G1
VSS
L1
VSS
A3
VSS
V3
VSS
A10
VSS
V10
VSS
G12
VSS
L12
VSS
FBB_VREF1
H1
VREF
FBB_VREF3
H12
VREF
FBVDDQ
GND
GND
VREF = FBVDDQ * R2/(R1 + R2)
FBVDDQ
R67
R67
511
511
1%
1%
0402
0402
COMMON
COMMON
R68
R68
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
FBB_CMD4FBB_CMD5
FBB_CMD6
FBB_CMD5
FBB_CMD13
FBB_CMD22
FBB_CMD24
FBB_CMD0
FBB_CMD2
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
R1
OUT
C50
C50
.1UF
.1UF
R2
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
NAME
R545
R545
0402
0402
R554
R554
0402
0402
R539
R539
0402
0402
R531
0402 COMMON
0402 COMMON
R567
04021%COMMON
04021%COMMON
R564
04021%COMMON
04021%COMMON
R563
R563
0402
0402
R562
R562
0402
0402
R550
R550
COMMON
COMMON
13
COMMON
COMMON
R547
R547
600-10562-base-000 A
1
FBVDDQ
121
121
COMMON
COMMON
1%
1%
121
121
COMMON
COMMON
1%
1%
121
121
COMMON
COMMON
1%
1%
121R531
121
1%
1%
121R567
121
121R564
121
121
121
COMMON
COMMON
1%
1%
121
121
COMMON
COMMON
1%
1%
2
FBVDDQ
511
511
R1
1%
1%
0402
0402
1.3K
1.3K
R2
1%
1%
0402
0402
C560
C560
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
3
GND
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
www.vinafix.vn
Page 8
A B C D E F G H
Page8: FBB Partition Decoupling
1
2
Decoupling for FBB 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C580
C580
C592
C592
C593
C593
C584
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C581
C581
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C576
C576
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C584
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C577
C577
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C578
C578
C579
C579
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C583
C583
C596
C596
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
3
X5R
X5R
0402
0402
COMMON
COMMON
10%
X5R
X5R
0402
0402
COMMON
COMMON
Decoupling for FBB 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C544
C544
C542
C542
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C554
C554
C562
C562
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C531
C531
C574
C574
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C567
C567
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C534
C534
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C551
C551
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C559
C559
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C541
C541
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBB Partion Decoupling
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 9
A B C D E F G H
Page9: FBC Partition
FBC_CMD[27..0]
4,13
IN
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
GND
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R594
R594
0
0
5%
5%
0402
0402
COMMON
COMMON
13
IN
1
FBC_CLK0_TERM
1.8V
C745
C745
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
4,13
IN
4,13
IN
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
2
MEMORY pin!!
Minimize the stub length!!
COMMON
COMMON
R611
R611
121
121
1%
1%
0402
0402
DDR3:
R612
R612
121
121
1%
1%
0402
0402
COMMON
COMMON
ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
GND
FBC_CMD1 FBC_CMD1
1
FBC_CMD10 FBC_CMD10
10
FBC_CMD11 FBC_CMD11
11
FBC_CMD8 FBC_CMD8
8
FBC_CMD19 FBC_CMD19
19
FBC_CMD25 FBC_CMD25
25
FBC_CMD22
22
FBC_CMD24
24
FBC_CMD0
0
FBC_CMD2
2
FBC_CMD21 FBC_CMD21
21
FBC_CMD16 FBC_CMD16
16
FBC_CMD23 FBC_CMD23
23
FBC_CMD20 FBC_CMD20
20
FBC_CMD17 FBC_CMD17
17
FBC_CMD9 FBC_CMD9
9
FBC_CMD12 FBC_CMD12
12
FBC_CMD3 FBC_CMD3
3
FBC_CMD27 FBC_CMD27
27
FBC_CMD18 FBC_CMD18
18
FBC_CLK0
FBC_CLK0*
SNN_FBC0_NC1 SNN_FBC1_NC1
FBC_CMD14 FBC_CMD14
14
FBC_CMD_SENC0 FBC_CMD_SENC1
FBC_CMD15 FBC_CMD15
15
FBC_CMD15
FBC_CMD18
R590
R590
R591
R591
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND GND GND
FBVDDQ
C730
3
C730
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
4,13
4
4,13
4,13
4,13
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBC_D[63..0]
BI
0
1
2
3
FBC_DQM[7..0]
BI
FBC_DQS_RN[7..0]
BI
FBC_DQS_WP[7..0]
BI
FBC_DQM0
0
FBC_DQM1
1
FBC_DQM2
2
FBC_DQM3
3
4
FBC_DQM5
5
FBC_DQM6
6
FBC_DQM7
7
FBC_DQS_RN0
0
FBC_DQS_RN1
1
FBC_DQS_RN2
2
FBC_DQS_RN3
3
FBC_DQS_RN4
4
FBC_DQS_RN5
5
FBC_DQS_RN6
6
FBC_DQS_RN7
7
FBC_DQS_WP0
0
FBC_DQS_WP1
1
FBC_DQS_WP2
2
FBC_DQS_WP3
3
FBC_DQS_WP4
4
FBC_DQS_WP5
5
FBC_DQS_WP6
6
FBC_DQS_WP7
7
4
5
6
7
32
33
34
35
36
37
38
39
FBC_ZQ0
R620
R620
243
243
1%
1%
0402
0402
COMMON
COMMON
C731
C731
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_DQM0
FBC_DQS_RN0
FBC_DQS_WP0
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_DQM4
FBC_DQS_RN4
FBC_DQS_WP4
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
M3E
M3E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
E11
F10
G10
F11
C10
B10
C11
B11
E10
D10
D11
L3
M3
M2
N2
R3
R2
T2
T3
N3
P3
P2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NONMIRRORED
NONMIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
M3A
M3A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M4E
M4E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBC_VREF0
H1
FBC_VREF2
H12
VREF = FBVDDQ * R2/(R1 + R2)
FBC_D8
8
FBC_D9
9
FBC_D10
10
FBC_D11
11
FBC_D12
12
FBC_D13
13
FBC_D14
14
FBC_D15
15
FBC_DQM1
FBC_DQS_RN1
FBC_DQS_WP1
FBC_D40
40
FBC_D41
41
FBC_D42
42
FBC_D43
43
FBC_D44
44
FBC_D45
45
FBC_D46
46
FBC_D47
47
FBC_DQM5
FBC_DQS_RN5
FBC_DQS_WP5
FBVDDQ
GND
GND
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511K + 1.18K)
C2
B2
G3
C3
E2
B3
E3
D3
D2
L10
M11
M10
N11
R11
T11
T10
R10
N10
P10
P11
GND
4,13
4,13
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
R607
R607
511
511
R1
1%
1%
0402
0402
COMMON
COMMON
R615
R615
1.3K
1.3K
R2
1%
1%
0402
0402
COMMON
COMMON
GND
M3B
M3B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
F2
DQ3
DQ4
F3
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M4A
M4A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
C GE
FBC_CLK1_TERM
1.8V
C610
C610
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
IN
IN
ASSEMBLY
PAGE DETAIL
M4D
M4D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
H10
RAS
F9
CAS
H4
WE
F4
CS0
K9
A0
H11
A1
K10
A2
M9
A3
K4
A4
H2
A5
K3
A6
L4
A7
K2
A8/AP
M4
A9
K11
A10
L9
A11
G9
BA0
G4
BA1
H3
BA2
H9
CKE
J11
CLK
J10
CLK
J2
NC/RFU
J3
A12 (32Mx32)
V4
SEN (GND)
V9
RESET
A9
MF (GND)
FBC_ZQ1
A4
ZQ
R571
R571
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
K1
VDDA (VDD)
K12
VDDA (VDD)
C619
C619
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
J1
VSSA (GND)
J12
VSSA (GND)
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
MIRRORED
MIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBC_VREF1
H1
FBC_VREF3
H12
FBVDDQ
R50
R50
511
511
1%
1%
0402
0402
COMMON
COMMON
R51
R51
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
GND
GND
FBC_CMD4FBC_CMD5
FBC_CMD6
FBC_CMD5
FBC_CMD13
FBC_CMD22
FBC_CMD24
FBC_CMD0
FBC_CMD2
13
OUT
C42
C42
.1UF
.1UF
R2
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R581
121
R581
121
COMMON
COMMON
0402
0402
1%
1%
R584
121R584
121
COMMON0402
COMMON0402
1%
1%
R582
121R582
121
04021%COMMON
04021%COMMON
R577
121
R577
121
COMMON
COMMON
0402
0402
1%
1%
R605
121R605
121
04021%COMMON
04021%COMMON
R601
121R601
121
04021%COMMON
04021%COMMON
R599
121
R599
121
0402
0402
COMMON
COMMON
1%
1%
R608
121
R608
121
0402
COMMON
0402
COMMON
1%
1%
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511K + 1.18K)
FBVDDQ
R580
R580
511
511
R1R1
1%
1%
0402
0402
COMMON
COMMON
R574
R574
1.3K
1.3K
R2
1%
1%
0402
0402
COMMON
COMMON
GND
FBVDDQ
C612
C612
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
1
2
3
C742
C742
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R575
R575
121
121
1%
1%
0402
0402
COMMON
COMMON
OUT
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
R586
R586
0
0
5%
5%
0402
0402
COMMON
COMMON
CMD18 CKE
CMD15 RST
R576
R576
121
121
1%
1%
0402
0402
COMMON
COMMON
GND
DDR3:
ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
13
1
10
11
8
19
25
FBC_CMD4
4
FBC_CMD6
6
5
FBC_CMD13
13
21
16
23
20
17
9
12
3
27
18
FBC_CLK1
FBC_CLK1*
14
FBVDDQ
15
13
IN
FBVDDQ
FBVDDQ
C613
C613
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
COMMON
COMMON
COMMON
COMMON
R49
R49
511
511
R1
1%
1%
0402
0402
R48
R48
1.3K
1.3K
R2
1%
1%
0402
0402
C41
C41
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
GND
M3C
M3C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBC_D16
16
FBC_D17
17
FBC_D18
18
FBC_D19
19
FBC_D20
20
FBC_D21
21
FBC_D22
22
FBC_D23
23
FBC_DQM2
FBC_DQS_RN2
FBC_DQS_WP2
FBC_D48
48
FBC_D49
49
FBC_D50
50
FBC_D51
51
FBC_D52
52
FBC_D53
53
FBC_D54
54
FBC_D55
55
FBC_DQM6
FBC_DQS_RN6
FBC_DQS_WP6
COMMON
M11
DQ0
N11
DQ1
T11
DQ2
T10
DQ3
M10
DQ4
L10
DQ5
R11
DQ6
R10
DQ7
N10
DQM
P10
RDQS
P11
WDQS
M4B
M4B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
B2
DQ0
C2
DQ1
B3
DQ2
E2
DQ3
C3
DQ4
F2
DQ5
F3
DQ6
G3
DQ7
E3
DQM
D3
RDQS
D2
WDQS
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC Partition
FBC_D24
24
FBC_D25
25
FBC_D26
26
FBC_D27
27
FBC_D28
28
FBC_D29
29
FBC_D30
30
FBC_D31
31
FBC_DQM3FBC_DQM4
FBC_DQS_RN3
FBC_DQS_WP3
FBC_D56
56
FBC_D57
57
FBC_D58
58
FBC_D59
59
FBC_D60
60
FBC_D61
61
FBC_D62
62
FBC_D63
63
FBC_DQM7
FBC_DQS_RN7
FBC_DQS_WP7
M3D
M3D
T3
R3
T2
R2
M2
M3
N2
L3
N3
P3
P2
M4C
M4C
E11
C11
B10
C10
B11
G10
F10
F11
E10
D10
D11
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
www.vinafix.vn
Page 10
A B C D E F G H
Page10: FBC Partition
1
2
3
Decoupling for FBC 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C752
C752
C753
C753
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C756
C756
C703
C703
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C750
C750
C721
C721
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C732
C732
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C726
C726
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C707
C707
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C741
C741
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C704
C704
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
Decoupling for FBC 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C642
C642
C605
C605
C602
C602
C639
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C634
C634
C653
C653
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C640
C640
C606
C606
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C608
C608
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C604
C604
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C639
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C621
C621
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC Partition Decoupling
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 11
A B C D E F G H
Page11: FBD Partition
FBD_CMD[27..0]
4,13
IN
CMD-Addr Map
BGA136 ADDR
1
FBD_CLK0_TERM
1.8V
C805
C805
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R691
R691
R688
R688
121
121
121
121
1%
1%
1%
0402
0402
COMMON
COMMON
DDR3: ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
COMMON
COMMON
1%
0402
0402
GND
4,13
IN
4,13
IN
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
2
MEMORY pin!!
Minimize the stub length!!
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R677
R677
0
0
5%
5%
0402
0402
COMMON
COMMON
GND
13
IN
GND
FBD_CMD1 FBD_CMD1
1
FBD_CMD10 FBD_CMD10
10
FBD_CMD11 FBD_CMD11
11
FBD_CMD8 FBD_CMD8
8
FBD_CMD19 FBD_CMD19
19
FBD_CMD25 FBD_CMD25
25
FBD_CMD22
22
FBD_CMD24
24
FBD_CMD0
0
FBD_CMD2
2
FBD_CMD21 FBD_CMD21
21
FBD_CMD16 FBD_CMD16
16
FBD_CMD23 FBD_CMD23
23
FBD_CMD20 FBD_CMD20
20
FBD_CMD17 FBD_CMD17
17
FBD_CMD9 FBD_CMD9
9
FBD_CMD12 FBD_CMD12
12
FBD_CMD3 FBD_CMD3
3
FBD_CMD27 FBD_CMD27
27
FBD_CMD18 FBD_CMD18
18
FBD_CMD18
FBD_CLK0
FBD_CLK0*
SNN_FBD0_NC1 SNN_FBD1_NC1
FBD_CMD14 FBD_CMD14
14
FBD_CMD_SEND0 FBD_CMD_SEND1
FBD_CMD15 FBD_CMD15
15
FBD_CMD15
FBD_ZQ0
R681
R681
R696
R696
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND GND GND
FBVDDQ
C783
3
C783
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
4,13
4
4,13
4,13
4,13
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBD_D[63..0]
BI
0
1
2
3
FBD_DQM[7..0]
BI
FBD_DQS_RN[7..0]
BI
FBD_DQS_WP[7..0]
BI
FBD_DQM0
0
FBD_DQM1
1
FBD_DQM2
2
FBD_DQM3
3
4
FBD_DQM5
5
FBD_DQM6
6
FBD_DQM7
7
FBD_DQS_RN0
0
FBD_DQS_RN1
1
FBD_DQS_RN2
2
FBD_DQS_RN3
3
FBD_DQS_RN4
4
FBD_DQS_RN5
5
FBD_DQS_RN6
6
FBD_DQS_RN7
7
FBD_DQS_WP0
0
FBD_DQS_WP1
1
FBD_DQS_WP2
2
FBD_DQS_WP3
3
FBD_DQS_WP4
4
FBD_DQS_WP5
5
FBD_DQS_WP6
6
FBD_DQS_WP7
7
4
5
6
7
32
33
34
35
36
37
38
39
R679
R679
243
243
1%
1%
0402
0402
COMMON
COMMON
C813
C813
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_DQM0
FBD_DQS_RN0
FBD_DQS_WP0
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_DQM4
FBD_DQS_RN4
FBD_DQS_WP4
M2E
M2E
BGA_0136_P080_140X120
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
B10
F11
F10
B11
C11
C10
E11
G10
E10
D10
D11
T3
T2
R2
M2
R3
M3
N2
L3
N3
P3
P2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NONMIRRORED
NONMIRRORED
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
M2A
M2A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M1E
M1E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBD_VREF0
H1
FBD_VREF2
H12
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
FBD_D8
8
FBD_D9
9
FBD_D10
10
FBD_D11
11
FBD_D12
12
FBD_D13
13
FBD_D14
14
FBD_D15
15
FBD_DQM1
FBD_DQS_RN1
FBD_DQS_WP1
FBD_D40
40
FBD_D41
41
FBD_D42
42
FBD_D43
43
FBD_D44
44
FBD_D45
45
FBD_D46
46
FBD_D47
47
FBD_DQM5
FBD_DQS_RN5
FBD_DQS_WP5
FBVDDQ
GND
GND
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511 + 1.18K)
G3
F3
F2
E2
C2
B3
B2
C3
E3
D3
D2
N11
M11
M10
R11
T11
L10
T10
R10
N10
P10
P11
4,13
4,13
R650
R650
COMMON
COMMON
R661
R661
COMMON
COMMON
M2B
M2B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
M1A
M1A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
C GE
FBD_CLK1_TERM
1.8V
C792
C792
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
IN
IN
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
511
511
R1
1%
1%
0402
0402
1.3K
1.3K
R2
1%
1%
0402
0402
GND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
ASSEMBLY
PAGE DETAIL
CMD-Addr Map
C782
C782
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R666
R666
121
121
1%
1%
0402
0402
COMMON
COMMON
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
R669
R669
121
121
1%
1%
0402
0402
COMMON
COMMON
CMD18 CKE
CMD15 RST
R682
R682
0
0
5%
5%
0402
0402
COMMON
COMMON
GND
DDR3: ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
13
OUT
FBVDDQ
R31
R31
511
511
R1
1%
1%
0402
0402
COMMON
COMMON
COMMON
COMMON
R34
R34
1.3K
1.3K
R2
1%
1%
0402
0402
C31
C31
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
13
OUT
1
10
11
8
19
25
FBD_CMD4
4
FBD_CMD6
6
FBD_CMD5
5
FBD_CMD13
13
21
16
23
20
17
9
12
3
27
18
14
FBVDDQ
15
13
IN
FBVDDQ
C817
C817
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
GND
M2C
M2C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
FBD_D16
16
FBD_D17
17
FBD_D18
18
FBD_D19
19
FBD_D20
20
FBD_D21
21
FBD_D22
22
FBD_D23
23
FBD_DQM2
FBD_DQS_RN2
FBD_DQS_WP2
FBD_D48
48
FBD_D49
49
FBD_D50
50
FBD_D51
51
FBD_D52
52
FBD_D53
53
FBD_D54
54
FBD_D55
55
FBD_DQM6
FBD_DQS_RN6
FBD_DQS_WP6
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBD Partition
R10
R11
T10
T11
N11
L10
M11
M10
N10
P10
P11
E2
B3
C2
C3
B2
F3
G3
F2
E3
D3
D2
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M1B
M1B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
FBD_D24
24
FBD_D25
25
FBD_D26
26
FBD_D27
27
FBD_D28
28
FBD_D29
29
FBD_D30
30
FBD_D31
31
FBD_DQM3FBD_DQM4
FBD_DQS_RN3
FBD_DQS_WP3
FBD_D56
56
FBD_D57
57
FBD_D58
58
FBD_D59
59
FBD_D60
60
FBD_D61
61
FBD_D62
62
FBD_D63
63
FBD_DQM7
FBD_DQS_RN7
FBD_DQS_WP7
G10
F10
F11
E11
C11
B10
C10
B11
E10
D10
D11
FBD_CLK1
FBD_CLK1*
FBD_ZQ1
T2
R2
L3
M3
M2
N2
R3
T3
N3
P3
P2
R690
R690
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
C781
C781
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
M2D
M2D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M1C
M1C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
H10
F9
H4
F4
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
G9
G4
H3
H9
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
M1D
M1D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
RAS
CAS
WE
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
BA2
CKE
CLK
CLK
NC/RFU
A12 (32Mx32)
SEN (GND)
RESET
MF (GND)
ZQ
VDDA (VDD)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
M12
VDD
A1
VDDQ
C1
VDDQ
E1
VDDQ
N1
VDDQ
R1
VDDQ
V1
VDDQ
C4
VDDQ
E4
VDDQ
J4
VDDQ
N4
VDDQ
R4
VDDQ
C9
VDDQ
E9
VDDQ
J9
VDDQ
N9
VDDQ
R9
VDDQ
MIRRORED
MIRRORED
A12
VDDQ
C12
VDDQ
E12
VDDQ
N12
VDDQ
R12
VDDQ
V12
VDDQ
B1
VSSQ
D1
VSSQ
P1
VSSQ
T1
VSSQ
G2
VSSQ
L2
VSSQ
B4
VSSQ
D4
VSSQ
P4
VSSQ
T4
VSSQ
B9
VSSQ
D9
VSSQ
P9
VSSQ
T9
VSSQ
G11
VSSQ
L11
VSSQ
B12
VSSQ
D12
VSSQ
P12
VSSQ
T12
VSSQ
G1
VSS
L1
VSS
A3
VSS
V3
VSS
A10
VSS
V10
VSS
G12
VSS
L12
VSS
FBD_VREF1
H1
VREF
FBD_VREF3
H12
VREF
FBVDDQ
GND
GND
COMMON
COMMON
COMMON
COMMON
R33
R33
R32
R32
1.3K
1.3K
511
511
1%
1%
0402
0402
1%
1%
0402
0402
FBVDDQ
R1
R2
GND
FBD_CMD4
FBD_CMD6
FBD_CMD5
FBD_CMD13
FBD_CMD22
FBD_CMD24
FBD_CMD0
FBD_CMD2
VREF = FBVDDQ * R2/(R1 + R2)
DDR3: VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBVDDQ
R663
R663
511
511
1%
1%
0402
0402
COMMON
OUT
C30
C30
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
COMMON
R662
R662
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
600-10562-base-000 A
NAME
R674
04021%COMMON
04021%COMMON
R668
R668
0402
0402
1%
1%
R680
04021%COMMON
04021%COMMON
R692
04021%COMMON
04021%COMMON
R673
04021%COMMON
04021%COMMON
R667
R667
0402
0402
1%
1%
R689
04021%COMMON
04021%COMMON
R694
04021%COMMON
04021%COMMON
R1
13
R2
GND
121R674
121
121
121
COMMON
COMMON
121R680
121
121R692
121
121R673
121
121
121
COMMON
COMMON
121R689
121
121R694
121
HFDBA
FBVDDQ
C780
C780
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
1
2
13
OUT
3
4
5
PAGEID
DATE
30-DEC-2008
www.vinafix.vn
Page 12
A B C D E F G H
Page12: FBD Partition Decoupling
1
2
3
Decoupling for FBD 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C796
C796
C788
C788
.047UF
.047UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C811
C811
C810
C810
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C815
C815
C814
C814
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C795
C795
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C806
C806
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C787
C787
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C807
C807
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C819
C819
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
Decoupling for FBD 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C812
C812
C794
C794
C797
C797
.1UF
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C809
C809
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C816
C816
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C808
C808
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C790
C790
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C804
C804
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C791
C791
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C803
C803
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C789
C789
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBD Partition Decoupling
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 13
A B C D E F G H
Page13: FB Net Properties
1
NET RULES for FBA and FBB
NET
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
2
3,5
3,7
3,7
3,7
3,7
3,7
3,7
3,7
3,7
3,7
FBA_CLK0
OUT
FBA_CLK0*
OUT
FBA_CLK1
OUT
FBA_CLK1*
OUT
FBA_CMD[27..0]
OUT
FBA_DQS_WP[7..0]
OUT
FBA_DQS_RN[7..0]
IN
FBA_DQM[7..0]
OUT
FBA_D[63..0]
BI
NET DIFFPAIR
FBB_CLK0
OUT
FBB_CLK0*
OUT
FBB_CLK1
OUT
FBB_CLK1*
OUT
NET
FBB_CMD[27..0]
OUT
FBB_DQS_WP[7..0]
OUT
FBB_DQS_RN[7..0]
IN
FBB_DQM[7..0]
OUT
FBB_D[63..0]
BI
1
1
1
NV_CRITICAL_NET
1
1
1
1
1
NV_CRITICAL_NET
1
1
1 FBB_CLK1
1
NV_CRITICAL_NET
1
1
1
1
1
IMPEDANCENV_CRITICAL_NET
IMPEDANCENET
IMPEDANCE
IMPEDANCE
DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
FBA_CLK01
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBB_CLK0
FBB_CLK0
FBB_CLK1
NET RULES for FBC and FBD
NV_CRITICAL_NETNET
FBC_CLK0
4,9
OUT
FBC_CLK0*
4,9
OUT
FBC_CLK1
4,9
OUT
FBC_CLK1*
4,9
OUT
NET
NV_CRITICAL_NET
FBC_CMD[27..0]
4,9
OUT
FBC_DQS_WP[7..0]
4,9
OUT
FBC_DQS_RN[7..0]
4,9
IN
FBC_DQM[7..0]
4,9
OUT
4,9
4,11
FBC_D[63..0]
BI
NV_CRITICAL_NET
NET
FBD_CLK0
4,11
OUT
FBD_CLK0*
4,11
OUT
FBD_CLK1
4,11
OUT
FBD_CLK1*
4,11
OUT
NV_CRITICAL_NET
NET
FBD_CMD[27..0]
4,11
OUT
FBD_DQS_WP[7..0]
4,11
OUT
FBD_DQS_RN[7..0]
4,11
IN
FBD_DQM[7..0]
4,11
OUT
FBD_D[63..0]
BI
1 FBC_CLK0
1
1 FBC_CLK1
1 FBC_CLK1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IMPEDANCE
IMPEDANCE
IMPEDANCE
IMPEDANCE
DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
FBC_CLK0
DIFFPAIR
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
3
MIN_LINE_WIDTH
3
3
5
5
5
5
5
5
7
7
7
7
7
4
7
FB_PLLAVDD0
BI
FB_VREF
BI
FBA_VREF0
BI
FBA_VREF1
BI
FBA_VREF2
BI
FBA_VREF3
BI
FBA_ZQ0
BI
FBA_ZQ1
BI
FBB_VREF0
BI
FBB_VREF1
BI
FBB_VREF2
BI
FBB_VREF3
BI
FBB_ZQ0
BI
FBB_ZQ1
BI
12MIL
5MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
VOLTAGE NV_NET_MAX_CURRENTNET
1.1V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
0.04A 12MIL
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A12MIL
0.02A12MIL
0.02A
4
BI
9
BI
9
BI
9
BI
9
BI
9
BI
9
BI
11
BI
11
BI
11
BI
11
BI
11
BI
11
BI
NET
FB_PLLAVDD1
FBC_VREF0
FBC_VREF1
FBC_VREF2
FBC_VREF3
FBC_ZQ0
FBC_ZQ1
FBD_VREF0
FBD_VREF1
FBD_VREF2
FBD_VREF3
FBD_ZQ0
FBD_ZQ1
MIN_LINE_WIDTH VOLTAGE
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
1.1V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
NV_NET_MAX_CURRENT
0.04A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FB Net Properties
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 14
A B C D E F G H
Page14: DACA Interface
1
2
14,15
OUT
3V3
LB507
220R@100MHZ
LB507
220R@100MHZ
COMMON
IND_SMD_0402
COMMON
IND_SMD_0402
VVVV18701S
VVVV18701S
C738
C738
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
3
GND
C11-1057322-T04
C11-1057322-T04
4
14,15
14,16
14,16
14,16
5
14,16
14,16
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C737
C737
4.7UF
4.7UF
L02-2218022-SG0
L02-2218022-SG0
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-4757013-T04
C11-4757013-T04
GND
NET
DACA_VDD
IN
DACA_VREF
IN
DACA_RSET
IN
NET
DACA_RED
BI
DACA_GREEN
BI
DACA_BLUE
BI
DACA_RED_C
BI
DACA_GREEN_C
BI
DACA_BLUE_C
BI
DACA_HSYNC
BI
DACA_HS_BUF
BI
DACA_HS_BUF_R
BI
DACA_HS_C
BI
DACA_VSYNC
BI
DACA_VS_BUF
BI
DACA_VS_BUF_R
BI
DACA_VS_C
BI
C736
C736
C713
C713
1UF
1UF
.1UF
.1UF
6.3V
6.3V
16V
16V
10%
10%
10%
10%
X5R
X5R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
VVVV18701S
VVVV18701S
VVVV18701S
VVVV18701S
C11-1057322-T04
C11-1057322-T04
C11-1042542-T04
C11-1042542-T04
12MIL
12MIL
NV_CRITICAL_NET
1 75OHM
1 75OHM
1 75OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
DACA_VDD
DACA_VREF
DACA_RSET
C748
C748
R603
R603
.1UF
.1UF
124
124
16V
16V
1%
1%
0402
0402
10%
10%
COMMON
COMMON
X7R
X7R
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
VVVV18701S
VVVV18701S
R11-1240T12-Y01
R11-1240T12-Y01
C11-1042542-T04
C11-1042542-T04
VOLTAGEMIN_LINE_WIDTH
IMPEDANCE
75OHM1
75OHM1
75OHM1
G1F
G1F
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
6/19 DACA
6/19 DACA
AM12
DACA_VDD
AP10
DACA_VREF
AP11
DACA_RSET
VVVV18701S
VVVV18701S
B03-00G94A5-N08
B03-00G94A5-N08
NV_NET_MAX_CURRENT
0.100A3.3V12MIL
MIN_LINE_WIDTH
I2CA_SCL
I2CA_SDA
DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_GREEN
DACA_BLUE
C GE
I2CA_SDA
AA4
DACA_HSYNC
AU12
DACA_VSYNC
AT12
DACA_RED
AU10
DACA_GREEN
AU11
DACA_BLUE
AT10
R596
R596
150
150
1%
1%
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
R11-0151T12-W08
R11-0151T12-W08
R593
R593
150
150
1%
1%
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
R11-0151T12-W08
R11-0151T12-W08
R595
R595
150
150
1%
1%
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
R11-0151T12-W08
R11-0151T12-W08
I2CA_SCL
AA1
R12
R12
040233COMMON
040233COMMON
VVVV18701S
VVVV18701S
R11-0330032-Y01
R11-0330032-Y01
R11
R11
VVVV18701S
VVVV18701S
R11-0330032-Y01
R11-0330032-Y01
4
5
10
9
ASSEMBLY
PAGE DETAIL
DACA RGB-FILTER
I2CA_SDA_T
5%
5%
I2CA_SCL_T
33
33
COMMON0402
COMMON0402
5%
5%
5V
U504B
U504B
DACA_VS_BUF
6
SO14_I335X150
SO14_I335X150
COMMON
COMMON
7 14
VVVV18701S
VVVV18701S
T32-0740803-F01
T32-0740803-F01
5V
U504C
U504C
DACA_HS_BUF
8
SO14_I335X150
SO14_I335X150
COMMON
COMMON
7 14
VVVV18701S
VVVV18701S
T32-0740803-F01
T32-0740803-F01
PLACE NEAR SYNC BUFFER
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
DACA Interface
R702 33
R702 33
0402
0402
5%
5%
VVVV18701S
VVVV18701S
R11-0330032-Y01
R11-0330032-Y01
R710 33
R710 33
VVVV18701S
VVVV18701S
5V
R11-0330032-Y01
R11-0330032-Y01
C829
C829
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-1042542-T04
C11-1042542-T04
3V3
D503
D503
SOT23
SOT23
3
100V
100V
100MA
100MA
COMMON
COMMON
1 2
VVVV18701S
VVVV18701S
GND
D01-BAV9929-D07
D01-BAV9929-D07
3V3
D502
D502
SOT23
SOT23
3
100V
100V
100MA
100MA
COMMON
COMMON
1 2
VVVV18701S
VVVV18701S
GND
D01-BAV9929-D07
D01-BAV9929-D07
3V3
D501
D501
SOT23
SOT23
3
100V
100V
100MA
100MA
COMMON
COMMON
1 2
VVVV18701S
VVVV18701S
GND
D01-BAV9929-D07
D01-BAV9929-D07
COMMON
COMMON
COMMON0402
COMMON0402
5%
5%
R708
R708
150
150
1%
1%
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
R11-0151T12-W08
R11-0151T12-W08
R707
R707
150
150
1%
1%
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
R11-0151T12-W08
R11-0151T12-W08
R706
R706
150
150
1%
1%
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
R11-0151T12-W08
R11-0151T12-W08
5V
VVVV18701S
VVVV18701S
R11-0222012-W08
R11-0222012-W08
VVVV18701S
VVVV18701S
R11-0222012-W08
R11-0222012-W08
DACA_VS_BUF_R
3
DACA_HS_BUF_R
3
L506 33NH
L506 33NH
C828
C828
1.8PF
1.8PF
50V
50V
+/-0.25PF
+/-0.25PF
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-18A1012-W08
C11-18A1012-W08
L504 33NH
L504 33NH
C826
C826
1.8PF
1.8PF
50V
50V
+/-0.25PF
+/-0.25PF
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-18A1012-W08
C11-18A1012-W08
L505 33NH
L505 33NH
C827
C827
1.8PF
1.8PF
50V
50V
+/-0.25PF
+/-0.25PF
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-18A1012-W08
C11-18A1012-W08
R4
R4
2.2K
2.2K
5%
5%
0402
0402
COMMON
COMMON
R3
R3
2.2K
2.2K
5%
5%
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
D01-BAV9929-D07
D01-BAV9929-D07
VVVV18701S
VVVV18701S
D01-BAV9929-D07
D01-BAV9929-D07
5V
D6
D6
SOT23
SOT23
100V
100V
100MA
100MA
COMMON
COMMON
1 2
5V
D7
D7
SOT23
SOT23
100V
100V
100MA
100MA
COMMON
COMMON
1 2
IND_SMD_0402COMMON
IND_SMD_0402COMMON
XXXV18701S
XXXV18701S
<New PN>
<New PN>
IND_SMD_0402COMMON
IND_SMD_0402COMMON
XXXV18701S
XXXV18701S
<New PN>
<New PN>
IND_SMD_0402COMMON
IND_SMD_0402COMMON
XXXV18701S
XXXV18701S
<New PN>
<New PN>
LB6
27NH
LB6
27NH
IND_SMD_0402
COMMON
IND_SMD_0402
COMMON
VVVV18701S
VVVV18701S
L01-27CA022-T04
L01-27CA022-T04
LB5 27NH
LB5 27NH
COMMONIND_SMD_0402
COMMONIND_SMD_0402
VVVV18701S
VVVV18701S
L01-27CA022-T04
L01-27CA022-T04
L3 27NH
L3 27NH
COMMONIND_SMD_0402
COMMONIND_SMD_0402
VVVV18701S
VVVV18701S
L01-27CA022-T04
L01-27CA022-T04
L4
27NH
L4
27NH
COMMON
IND_SMD_0402
COMMON
IND_SMD_0402
VVVV18701S
VVVV18701S
L01-27CA022-T04
L01-27CA022-T04
DACA_RED_C
C837
C837
5.6PF
5.6PF
50V
50V
+/-0.5PF
+/-0.5PF
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-56A1022-W08
C11-56A1022-W08
DACA_GREEN_C
C834
C834
5.6PF
5.6PF
50V
50V
+/-0.5PF
+/-0.5PF
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-56A1022-W08
C11-56A1022-W08
DACA_BLUE_C
C836
C836
5.6PF
5.6PF
50V
50V
+/-0.5PF
+/-0.5PF
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-56A1022-W08
C11-56A1022-W08
C4
C4
22PF
22PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-2201012-W08
C11-2201012-W08
C3
C3
22PF
22PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-2201012-W08
C11-2201012-W08
C7
C7
15PF
15PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-1501012-W08
C11-1501012-W08
C8
C8
15PF
15PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
VVVV18701S
VVVV18701S
C11-1501012-W08
C11-1501012-W08
14,16
OUT
14,16
OUT
14,16
OUT
SNN_A_MON_ID2
OUT
OUT
OUT
DACA_VS_C
OUT
DACA_HS_C
DDC_5V
14,16
14,16
14,14,16
14,14,16
SHIELD
16
GND-R
6
R
1
GND-G
7
G
2
GND_B
8
B
3
5V
9
ID2
4
GND
10
GND
5
SHIELD
17
SOUTH
J2
J2
CON_DSUB_015_TH_RA_F_HD_L068_B
CON_DSUB_015_TH_RA_F_HD_L068_B
COMMON
COMMON
ID0
SNN_A_MON_ID0
11
1611
1611
SDA
I2CA_SDA_C
12
HSYNC
13
VSYNC
14
SCL
I2CA_SCL_C
15
15105
15105
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
1
2
3
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
www.vinafix.vn
Page 15
A B C D E F G H
Page15: DACC Interface
1
2
14,14
IN
DACA_VDD
C705
C705
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
C722
C722
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
DACC_VREF
DACC_RSET
R604
R604
124
124
1%
1%
0402
0402
COMMON
COMMON
GND
3
4
NET
MIN_LINE_WIDTH VOLTAGE
DACC_VREF
IN
DACC_RSET
IN
NET
DACC_RED
BI
DACC_GREEN
BI
DACC_BLUE
BI
15,17
15,17
15,17
5
15,17
15,17
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
DACC_RED_C
BI
DACC_GREEN_C
BI
DACC_BLUE_C
BI
DACC_HSYNC
BI
DACC_HS_BUF
BI
DACC_HS_BUF_R
BI
DACC_HS_C
BI
DACC_VSYNC
BI
DACC_VS_BUF
BI
DACC_VS_BUF_R
BI
DACC_VS_C
BI
12MIL
12MIL
NV_CRITICAL_NET
1 75OHM
1 75OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
2 50OHM
G1G
G1G
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
8/19 DACC
8/19 DACC
AM11
DACC_VDD
AW8
DACC_VREF
AV7
DACC_RSET
NV_NET_MAX_CURRENT
IMPEDANCE MIN_LINE_WIDTH
75OHM1
75OHM1
75OHM1
75OHM1
I2CB_SCL
I2CB_SDA
DACC_HSYNC
DACC_VSYNC
DACC_RED
DACC_GREEN
DACC_BLUE
I2CB_SDA
AA2
DACC_HSYNC
AU7
DACC_VSYNC
AU8
AT6
AT7
DACC_BLUE
AT8
DACC_RED
R609
R609
150
150
1%
1%
0402
0402
COMMON
COMMON
DACC_GREEN
R606
R606
150
150
1%
1%
0402
0402
COMMON
COMMON
R600
R600
150
150
1%
1%
0402
0402
COMMON
COMMON
I2CB_SCL
AA3
C GE
DACC RGB-FILTER
I2CB_SDA_T
R10 33
R10 33
0402 COMMON
0402 COMMON
5%
5%
I2CB_SCL_T
R9
33
R9
33
0402
COMMON
0402
COMMON
5%
5%
5V
U504A
U504A
1
2
5V
13
12
ASSEMBLY
PAGE DETAIL
DACC_VS_BUF
3
SO14_I335X150
SO14_I335X150
COMMON
COMMON
7 14
U504D
U504D
DACC_HS_BUF
11
SO14_I335X150
SO14_I335X150
COMMON
COMMON
7 14
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
DACC Interface
R701
04025%COMMON
04025%COMMON
R709
3V3
D506
D506
SOT23
SOT23
3
100V
100V
100MA
100MA
COMMON
COMMON
1 2
GND
3V3
D505
D505
SOT23
SOT23
3
100V
100V
100MA
100MA
COMMON
COMMON
1 2
GND
3V3
D504
D504
SOT23
SOT23
3
100V
100V
100MA
100MA
COMMON
COMMON
1 2
GND
LB4
IND_SMD_0402COMMON
LB3
L1
L2
IND_SMD_0402COMMON
IND_SMD_0402COMMON
IND_SMD_0402COMMON
IND_SMD_0402COMMON
IND_SMD_0402COMMON
IND_SMD_0402COMMON
IND_SMD_0402COMMON
R2
R2
2.2K
2.2K
5V
5%
5%
0402
0402
COMMON
COMMON
R1
R1
2.2K
2.2K
5%
5%
0402
0402
COMMON
COMMON
DACC_VS_BUF_R
33R701
33
33R709
33
COMMON0402
COMMON0402
5%
5%
DACC_HS_BUF_R
5V
D3
D3
SOT23
SOT23
3
100V
100V
100MA
100MA
COMMON
COMMON
1 2
5V
D4
D4
SOT23
SOT23
3
100V
100V
100MA
100MA
COMMON
COMMON
1 2
OUT
27NHLB4
27NH
C2
C2
22PF
22PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
OUT
27NHLB3
27NH
C1
C1
22PF
22PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
OUT
27NHL1
27NH
C5
C5
15PF
15PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
OUT
27NHL2
27NH
C6
C6
15PF
15PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
15,17
15,17
15,15,17
1
2
15,15,17
3
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
15,17
OUT
15,17
OUT
15,17
L503
33NHL503
33NH
DACC_RED_C
COMMONIND_SMD_0402
R705
R705
150
150
1%
1%
0402
0402
R704
R704
150
150
1%
1%
0402
0402
R703
R703
150
150
1%
1%
0402
0402
C825
C825
1.8PF
1.8PF
50V
50V
+/-0.25PF
+/-0.25PF
C0G
C0G
0402
0402
COMMON
COMMON
C824
C824
1.8PF
1.8PF
50V
50V
+/-0.25PF
+/-0.25PF
C0G
C0G
0402
0402
COMMON
COMMON
C823
C823
1.8PF
1.8PF
50V
50V
+/-0.25PF
+/-0.25PF
C0G
C0G
0402
0402
COMMON
COMMON
L502
L501
COMMONIND_SMD_0402
IND_SMD_0402COMMON
IND_SMD_0402COMMON
IND_SMD_0402COMMON
IND_SMD_0402COMMON
C832
C832
5.6PF
5.6PF
50V
50V
+/-0.5PF
+/-0.5PF
C0G
C0G
0402
0402
COMMON
COMMON
33NHL502
33NH
DACC_GREEN_C
C831
C831
5.6PF
5.6PF
50V
50V
+/-0.5PF
+/-0.5PF
C0G
C0G
0402
0402
COMMON
COMMON
33NHL501
33NH
DACC_BLUE_C
C830
C830
5.6PF
5.6PF
50V
50V
+/-0.5PF
+/-0.5PF
C0G
C0G
0402
0402
COMMON
COMMON
OUT
SNN_C_MON_ID2
DDC_5V
16
6
1
7
2
8
3
9
4
10
5
17
SHIELD
GND-R
R
GND-G
G
GND_B
B
5V
ID2
GND
GND
SHIELD
J1
J1
CON_DSUB_015_TH_RA_F_HD_L068_B
CON_DSUB_015_TH_RA_F_HD_L068_B
COMMON
COMMON
11
1611
1611
SDA
12
HSYNC
13
VSYNC
14
SCL
15
15105
15105
ID0
SNN_C_MON_ID0
I2CB_SDA_C
DACC_HS_C
DACC_VS_C
I2CB_SCL_C
4
5
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
PAGEID
DATE
30-DEC-2008
HFDBA
www.vinafix.vn
Page 16
A B C D E F G H
Page16: IFP A/B Interface --
NET
MIN_LINE_WIDTH
IFPAB_IOVDD
BI
IFPAB_RSET
BI
12MIL 0.145A3.3V
5MIL
NV_NET_MAX_CURRENTVOLTAGE
1
1
DDC_5V
C853
C853
.1UF
.1UF
16V
G1H
G1H
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
C851
C851
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
COMMON
9/19 IFPAB
9/19 IFPAB
AR10
IFPAB_RSET
AK11
IFPAB_PLLVDD
AP8
IFPA_IOVDD
AP9
IFPB_IOVDD
B03-00G94A5-N08
B03-00G94A5-N08
VVVV18701S
VVVV18701S
IFPA_TXC
IFPA_TXC
IFPA_TXD0
IFPA_TXD0
IFPA_TXD1
IFPA_TXD1
IFPA_TXD2
IFPA_TXD2
IFPA_TXD3
IFPA_TXD3
IFPB_TXC
IFPB_TXC
IFPB_TXD4
IFPB_TXD4
IFPB_TXD5
IFPB_TXD5
IFPB_TXD6
IFPB_TXD6
IFPB_TXD7
IFPB_TXD7
IFPAB_TXC*
AT9
IFPAB_TXC
AR9
IFPAB_TXD0*
AY6
IFPAB_TXD0
AW7
IFPAB_TXD1*
AY7
IFPAB_TXD1
AY8
IFPAB_TXD2*
AW9
IFPAB_TXD2
AY9
SNN_IFPAB_ATXD3*
AV9
SNN_IFPAB_ATXD3
AU9
SNN_IFPAB_BTXC*
BA10
SNN_IFPAB_BTXC
BB10
IFPAB_TXD4*
BA4
IFPAB_TXD4
AY5
IFPAB_TXD5*
BB6
IFPAB_TXD5
BA6
IFPAB_TXD6*
BB7
IFPAB_TXD6
BA7
SNN_IFPAB_TXD7*
BA9
SNN_IFPAB_TXD7
BB9
IFPAB_TXC
IFPAB_TXC
IFPAB_TXD0
IFPAB_TXD0
IFPAB_TXD1
IFPAB_TXD1
IFPAB_TXD2
IFPAB_TXD2
IFPAB_TXD4
IFPAB_TXD4
IFPAB_TXD5
IFPAB_TXD5
IFPAB_TXD6
IFPAB_TXD6
1 90DIFF
1 90DIFF
1
1
1 90DIFF
1 90DIFF
1 90DIFF
1 90DIFF
1 90DIFF
1 90DIFF
1 90DIFF
1 90DIFF
1 90DIFF
1 90DIFF
90DIFF
90DIFF
14
IN
14
IN
14,14
IN
14,14
IN
14,14
IN
14,14
IN
14,14
IN
2
IFPAB_RSET
IFPABCD_PLLVDD
17
R610
R610
1K
1K
1%
1%
0402
0402
COMMON
COMMON
R11-0102T12-Y01
R11-0102T12-Y01
VVVV18701S
VVVV18701S
IFP_IOVDD
LB512
220R@100MHZ
LB512
220R@100MHZ
IND_SMD_0402
COMMON
IND_SMD_0402
C848
C848
1UF
1UF
6.3V
6.3V
10%
3
10%
X5R
X5R
0402
0402
COMMON
COMMON
C11-1057322-T04
C11-1057322-T04
GND
VVVV18701S
VVVV18701S
COMMON
L02-2218022-SG0
L02-2218022-SG0
VVVV18701S
VVVV18701S
GND
C852
C852
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C11-4757013-T04
C11-4757013-T04
VVVV18701S
VVVV18701S
IN
C849
C849
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C11-1057322-T04
C11-1057322-T04
VVVV18701S
VVVV18701S
C11-1042542-T04
C11-1042542-T04
VVVV18701S
VVVV18701S
IFPAB_IOVDD
C850
C850
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C11-1042542-T04
C11-1042542-T04
GND
VVVV18701S
VVVV18701S
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C11-1042542-T04
C11-1042542-T04
GND
VVVV18701S
VVVV18701S
I2CA_SCL_C
I2CA_SDA_C
DACA_VS_C
GPIO0_DVI_A_HPD_C
DACA_RED_C
DACA_GREEN_C
DACA_BLUE_C
DACA_HS_C
SHIELD1
25
SHIELD2
26
SHIELD3
27
SHIELD4
28
TX0-
17
TX0+
18
TX1-
9
TX1+
10
TX2-
1
TX2+
2
SHLD24
3
SHLD13
11
SHLD05
19
TX3-
12
TX3+
13
TX4-
4
TX4+
5
TX5-
20
TX5+
21
DDCC
6
DDCD
7
VDDC
14
GND
15
SHLDC
22
TXC-
24
TXC+
23
VSYNC
8
HPD
16
R
C1
G
C2
B
C3
AGND1
C5
AGND2
C5A
HSYNC
C4
SHIELD5
29
SHIELD6
30
SHIELD7
31
SHIELD8
32
N5B-30F0321-H06
N5B-30F0321-H06
GND
VVVV18701S
VVVV18701S
2
J8
J8
17 9
1
17 9
1
DVI_I_(SLIM_)SHLD_M
DVI_I_(SLIM_)SHLD_M
MULTI_CON_DVII_030_TH
MULTI_CON_DVII_030_TH
COMMON
COMMON
24
16 8
24
16 8
C3
C1
C3
C1
C5
C5A
C5
C5A
C4
C2
C4
C2
3
4
DVIAB Hotplug Detection
GPIO0_DVI_A_HPD
21
OUT
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
GPIO0_DVI_A_HPD_R
R79 10K
R79 10K
0402 COMMON
0402 COMMON
5%
D11
D11
SOT23
SOT23
100V
100V
100MA
100MA
COMMON
COMMON
1 2
5%
R11-0103012-Y01
R11-0103012-Y01
3V3
VVVV18701S
VVVV18701S
C75
C75
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0603
0603
COMMON
COMMON
GND
C11-1042013-W08
C11-1042013-W08
VVVV18701S
VVVV18701S
R78
R78
100K
100K
5%
5%
0402
0402
COMMON
COMMON
IFP A/B Interface -- DVI Connector South
3V3
3
R11-0104042-W08
R11-0104042-W08
VVVV18701S
VVVV18701S
D01-BAV9929-D07
D01-BAV9929-D07
GND
VVVV18701S
VVVV18701S
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
C76
C76
220PF
220PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
C11-2211042-T04
C11-2211042-T04
GND
VVVV18701S
VVVV18701S
LB2
180R@100MHz
LB2
180R@100MHz
COMMON
IND_SMD_0603
COMMON
IND_SMD_0603
L02-1818023-T34
L02-1818023-T34
VVVV18701S
VVVV18701S
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 17
A B C D E F G H
Page17: IFP C/D Interface -- HDMI
NET
MIN_LINE_WIDTH VOLTAGE NV_NET_MAX_CURRENT
IFPCD_PLLVDD
BI
IFPCD_IOVDD
BI
IFPCD_RSET
BI
12MIL 1.8V 0.035A
12MIL 1.1V 0.800A
5MIL
1
GPIO17_HDMI_CEC
16
BI
3
<New PN>
<New PN>
GND
2
IFPC_TXC*
IFPC_TXC
IFPC_TXD0*
IFPC_TXD0
IFPC_TXD1*
IFPC_TXD1
SNN_IFPC_AUX*
SNN_IFPC_AUX
IFPC_TXC*
IFPC_TXC
IFPC_TXD0*
IFPC_TXD0
IFPC_TXD1*
IFPC_TXD1
IFPC_TXD2*
IFPC_TXD2
SNN_IFPD_AUX*
SNN_IFPD_AUX
SNN_IFPD_L3*
SNN_IFPD_L3
SNN_IFPD_TXD4*
SNN_IFPD_TXD4
SNN_IFPD_TXD5*
SNN_IFPD_TXD5
SNN_IFPD_TXD6*
SNN_IFPD_TXD6
IFPC_TXD2*
IFPC_TXD2
3
G1I
G1I
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
10/19 IFPCD
10/19 IFPCD
IFPCD_RSET
R613
1K
R613
0402
0402
1%
1%
R11-0102T12-Y01
R11-0102T12-Y01
16
OUT
12MIL
C735
C735
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C11-4757013-T04
C11-4757013-T04
C724
C724
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C11-1057322-T04
C11-1057322-T04
1K
COMMON
COMMON
IFPABCD_PLLVDD
IFPCD_IOVDD
C11-1042542-T04
C11-1042542-T04
LB508
LB508
COMMONIND_SMD_0402
COMMONIND_SMD_0402
L02-2218022-SG0
L02-2218022-SG0
LB509
LB509
IND_SMD_0402COMMON
IND_SMD_0402COMMON
L02-2218022-SG0
L02-2218022-SG0
GND
220R@100MHZ
220R@100MHZ
220R@100MHZ
220R@100MHZ
C727
C727
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C11-4757013-T04
C11-4757013-T04
C747
C747
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C11-4757013-T04
C11-4757013-T04
IFP_PLLVDD
C746
C746
1UF
1UF
6.3V
6.3V
10%
10%
X5R
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
X5R
0402
0402
COMMON
COMMON
C11-1057322-T04
C11-1057322-T04
GND
PEX_VDD
C749
C749
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C11-1057322-T04
C11-1057322-T04
GND
C714
C714
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C11-1042542-T04
C11-1042542-T04
GND
C719
C719
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
AN5
IFPCD_RSET
AJ11
IFPCD_PLLVDD
AN8
IFPC_IOVDD
AN9
IFPD_IOVDD
B03-00G94A5-N08
B03-00G94A5-N08
IFPC
IFPC
AV6
AUX
AU6
AUX
AV3
DPL3_TXC
AU4
DPL3_TXC
AW3
DPL2_TXD0
AV4
DPL2_TXD0
AY4
DPL1_TXD1
AW4
DPL1_TXD1
AW5
DPL0_TXD2
AW6
DPL0_TXD2
IFPD
IFPD
AT5
AUX
AU5
AUX
AW2
DPL3_TXC
AW1
DPL3_TXC
AY1
DPL2_TXD0
AY2
DPL2_TXD0
AY3
DPL1_TXD1
BA3
DPL1_TXD1
BB3
DPL0_TXD2
BB4
DPL0_TXD2
C GE
D14
D14
INS3261510
INS3261510
SOT23
SOT23
100V
100V
100MA
100MA
COMMON
COMMON
1 2
COMMON
COMMON
COMMON 16V
COMMON 16V
3V3
<New PN>
<New PN>
C856 .1UF
C856 .1UF
C846 .1UF
C846 .1UF
C845
C845
C835
C835
ASSEMBLY
PAGE DETAIL
R778
R778
27K
27K
5%
5%
NO STUFF
0402
0402
COMMON
COMMON
R779
33
R779
33
0402
0402
COMMON
COMMON
5%
5%
NO STUFF
<New PN>
<New PN>
NO STUFF
C905 .1UF
C905 .1UF
16VCOMMON
16VCOMMON
COMMON 16V
COMMON 16V
C11-1047512-T34
C11-1047512-T34
C855 .1UF
C855 .1UF
16VCOMMON
16VCOMMON
C11-1047512-T34
C11-1047512-T34
COMMON 16V
COMMON 16V
.1UF
.1UF
C11-1047512-T34
C11-1047512-T34
C854
C854
16V
16V
C11-1047512-T34
C11-1047512-T34
.1UF
.1UF
C11-1047512-T34
C11-1047512-T34
C847 .1UF
C847 .1UF
C11-1047512-T34
C11-1047512-T34
C11-1047512-T34
C11-1047512-T34
C11-1047512-T34
C11-1047512-T34
12V
1G1D1S
1G1D1S
Q518
Q518
G
1
D
NO STUFF
SOT23_1G1D1S
COMMON
SOT23_1G1D1S
COMMON
INS3261724
INS3261724
2S3
HDMI_CEC_R
+/-20V
0.36W@25C
0.88A
3.5R
50V
0.22A@31C
+/-20V
0.36W@25C
0.88A
3.5R
50V
0.22A@31C
NO STUFF
600R@100MHZ
600R@100MHZ
HDMI_CEC_L
LB520
LB520
BEAD_0603 COMMON
BEAD_0603 COMMON
<New PN>
<New PN>
HDMI_CEC
29
CTXC*
CTXC
CTXD0*
CTXD0
CTXD1*
.1UF
.1UF
CTXD1
16VCOMMON
16VCOMMON
CTXD2*
CTXD2
16VCOMMON
16VCOMMON
R781
R781
300
300
0402
0402
COMMON
COMMON
5%
5%
R11-0301012-Y01
R11-0301012-Y01
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
IFP C/D Interface -- DVI Connector MID
10
IN
R11-0222012-W08
R11-0222012-W08
GPIO10_HDMI_TERM
HDMI_CEC
R776
R776
300
300
0402
0402
COMMON
COMMON
5%
5%
R11-0301012-Y01
R11-0301012-Y01
16
OUT
3V3
C11-1011032-M09
C11-1011032-M09
GND
GPIO1_HDMI_C_HPD
C77
C77
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
3V3
R782
R782
2.2K
2.2K
5%
5%
0402
0402
COMMON
COMMON
1G1D1S
1G1D1S
R783
R783
2.2K
2.2K
5%
5%
0402
0402
COMMON
COMMON
<New PN>
<New PN>
GND
R777
R777
300
300
0402
0402
COMMON
COMMON
5%
5%
R11-0301012-Y01
R11-0301012-Y01
R11-0103012-Y01
R11-0103012-Y01
GND
D
G
1
S
D03-0013809-F01
D03-0013809-F01
R80
R80
10K
10K
5%
5%
0402
0402
COMMON
COMMON
Q15
Q15
SOT23
SOT23
COMMON
COMMON
3
2
GND
3
IFP_TERM_PD
R128
R128
0402
0402
R135
R135
R11-4990T12-R01
R11-4990T12-R01
0402
0402
R11-4990T12-R01
R11-4990T12-R01
R1331%499
R1331%499
R132
R132
R11-4990T12-R01
R11-4990T12-R01
0402
0402
R11-4990T12-R01
R11-4990T12-R01
R134
R134
0402
0402
R1311%499
R1311%499
R11-4990T12-R01
R11-4990T12-R01
R11-4990T12-R01
R11-4990T12-R01
R130
R130
R129
R129
R11-4990T12-R01
R11-4990T12-R01
0402
0402
R11-4990T12-R01
R11-4990T12-R01
R780
R780
300
300
0402
0402
COMMON
COMMON
5%
5%
R11-0301012-Y01
R11-0301012-Y01
499
499
COMMON
COMMON
1%
1%
499
499
COMMON
COMMON
1%
1%
COMMON0402
COMMON0402
499
499
COMMON
COMMON
1%
1%
499
499
COMMON
COMMON
1%
1%
COMMON0402
COMMON0402
499
499
COMMON0402
COMMON0402
1%
1%
499
499
COMMON
COMMON
1%
1%
Hotplug Detection
R13
1K
R13
1K
GPIO1_HDMI_HPD_R
COMMON
COMMON
0402
0402
5%
5%
R11-0102032-W08
R11-0102032-W08
3V33V3
C14
D13
D13
SOT23
SOT23
100V
100V
?
?
COMMON
COMMON
1 2
D01-BAV9929-D07
D01-BAV9929-D07
GND GND
C14
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0603
0603
COMMON
COMMON
C11-1042013-W08
C11-1042013-W08
CTXC
CTXD0
CTXD1
CTXD2
CTXD0*
CTXD1*
CTXD2*
CTXC*
21
21
IND_SMD_0603
IND_SMD_0603
LINK C:
HDMI CEC USE GPIO 17
HPD GPIO 1
TERM GPIO 10
DDC_5V
I2CD_SDA_R
IN
I2CD_SCL_R
IN
SNN_HDMI_RESERV
LB10
LB10
L02-1818023-T34
L02-1818023-T34
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
NAME
GPIO1_HDMI_HPD_C
180R@100MHz
180R@100MHz
COMMON
COMMON
C11-2211042-T04
C11-2211042-T04
GND
600-10562-base-000 A
GND
C78
C78
220PF
220PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
MIDDLE
J9
J9
SHELL2
19
HP DET
18
GND
+5V
17
GND
16
DDC DATA
15
DDC CLK
14
NC
13
CE Remote
12
CK-
11
CK Shield
10
CK+
MEC1
9
D0-
8
D0 Shield
7
D0+
6
D1-
5
D1 Shield
4
D1+
3
D2-
2
GND
D2 Shield
1
D2+
SHELL1
STARTAKE_19P-1
STARTAKE_19P-1
N5Y-19M0061-L06
N5Y-19M0061-L06
PAGEID
DATE
HFDBA
21
23
MEC1
22
20
30-DEC-2008
1
2
3
4
5
www.vinafix.vn
Page 18
A B C D E F G H
Page18: IFP E/F Interface -- HDMI
1
G1J
AM9
AH11
AN6
AN7
G1J
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
11/19 IFPEF
11/19 IFPEF
IFPEF_RSET
IFPEF_PLLVDD
IFPE_IOVDD
IFPF_IOVDD
IFPE
IFPE
IFPF
IFPF
DPL3_TXC
DPL3_TXC
DPL2_TXD0
DPL2_TXD0
DPL1_TXD1
DPL1_TXD1
DPL0_TXD2
DPL0_TXD2
DPL3_TXC
DPL3_TXC
DPL2_TXD0
DPL2_TXD0
DPL1_TXD1
DPL1_TXD1
DPL0_TXD2
DPL0_TXD2
SNN_IFPE_AUX*
AR7
AUX
SNN_IFPE_AUX
AR6
AUX
SNN_IFPE_TXC*
AP7
SNN_IFPE_TXC
AP6
SNN_IFPE_L2*
AP5
SNN_IFPE_L2
AP4
SNN_IFPE_L1*
AP3
SNN_IFPE_L1
AR3
SNN_IFPE_L0*
AU3
SNN_IFPE_L0
AT3
SNN_IFPF_AUX*
AT4
AUX
SNN_IFPF_AUX
AR4
AUX
SNN_IFPF_L3*
AN2
SNN_IFPF_L3
AN1
SNN_IFPF_L2*
AP1
SNN_IFPF_L2
AP2
SNN_IFPF_L1*
AT2
SNN_IFPF_L1
AT1
SNN_IFPF_L0*
AU1
SNN_IFPF_L0
AU2
2
SNN_IFPEF_RSET
GND
3
GND
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
NET
MIN_LINE_WIDTH
VOLTAGE NV_NET_MAX_CURRENT
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
IFP E/F Interface -- Unused
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 19
A B C D E F G H
Page19: DACB Unused
1
2
G1K
G1K
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
3
SNN_DACB_VREF
SNN_DACB_RSET
GND
COMMON
7/19 DACB(TV)
7/19 DACB(TV)
AL11
DACB_VDD
AN3
DACB_VREF
AL3
DACB_RSET
DACB_CSYNC
DACB_GREEN
DACB_BLUE
DACB_RED
AK2
AK1
AL1
AL2
SNN_DACB_CSYNC
SNN_DACB_COUT
SNN_DACB_YOUT
SNN_DACB_PBOUT
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
DACB Unused
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 20
A B C D E F G H
Page20: MIO A/B Interface
1
G1M
G1M
BGA_1504_P080_350X350
2V5
C712
C712
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C11-4757013-T04
C11-4757013-T04
GND
2
3
C757
C757
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C11-4757013-T04
C11-4757013-T04
C723
C723
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C11-1042542-T04
C11-1057322-T04
C11-1057322-T04
C11-1042542-T04
C715
C715
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R622
R622
0402
0402
1%
1%
R616 49.9
R616 49.9
R11-499AT12-R01
R11-499AT12-R01
1%
1%
R11-499AT12-R01
R11-499AT12-R01
GND
C11-1042542-T04
C11-1042542-T04
GND
49.9
49.9
COMMON
COMMON
COMMON0402
COMMON0402
R11-0102T12-Y01
R11-0102T12-Y01
C718
C718
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R11-0102T12-Y01
R11-0102T12-Y01
MIOA_CAL_PD_VDDQ
MIOA_CAL_PU_GND
R621
R621
1K
1K
1%
1%
0402
0402
COMMON
COMMON
MIOA_VREF
R619
R619
1K
1K
1%
1%
0402
0402
COMMON
COMMON
SNN_MIOB_CAL_PD_VDDQ
SNN_MIOB_CAL_PU_GND
SNN_MIOB_VREF
3V3
BGA_1504_P080_350X350
COMMON
COMMON
12/19 MIOA
12/19 MIOA
AB11
MIOA_VDDQ
AC11
MIOA_VDDQ
AC9
MIOA_VDDQ
AD11
MIOA_VDDQ
AD7
MIOACAL_PD_VDDQ
AE7
MIOACAL_PU_GND
AG8
MIOA_VREF
B03-00G94A5-N08
B03-00G94A5-N08
G1L
G1L
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
13/19 MIOB
13/19 MIOB
AE11
MIOB_VDDQ
AF11
MIOB_VDDQ
AF9
MIOB_VDDQ
AG9
MIOB_VDDQ
AH6
MIOBCAL_PD_VDDQ
AL8
MIOBCAL_PU_GND
AL7
MIOB_VREF
MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8
MIOAD9
MIOAD10
MIOAD11
MIOAD12
MIOAD13
MIOAD14
MIOA_CTL3
MIOA_HSYNC
MIOA_VSYNC
MIOA_DE
MIOA_CLKOUT
MIOA_CLKOUT
MIOA_CLKIN
MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11
MIOBD12
MIOBD13
MIOBD14
MIOBD15
MIOBD16
MIOBD17
MIOA_D0 MIOA_D0
AE1
MIOA_D1 MIOA_D1
AE2
MIOA_D2 MIOA_D2
AE3
MIOA_D3 MIOA_D3
AG3
MIOA_D4 MIOA_D4
AG2
MIOA_D5 MIOA_D5
AG1
MIOA_D6 MIOA_D6
AF4
MIOA_D7 MIOA_D7
AF6
MIOA_D8 MIOA_D8
AG4
MIOA_D9 MIOA_D9
AG5
MIOA_D10 MIOA_D10
AG6
MIOA_D11 MIOA_D11
AG7
SNN_MIOA_D12
AD8
SNN_MIOA_D13
AE9
SNN_MIOA_D14
AD9
MIOA_D12
AD4
MIOA_D13
AD6
MIOA_D14
AD5
MIOA_DE
AE4
MIOA_CLKOUT
AE6
SNN_MIOA_CLKOUT*
AE5
MIOA_CLKIN
AE8
SNN_MIOB_D0
AH4
SNN_MIOB_D1
AH1
SNN_MIOB_D2
AH2
SNN_MIOB_D3
AH3
SNN_MIOB_D4
AK3
SNN_MIOB_D5
AL4
SNN_MIOB_D6
AK5
SNN_MIOB_D7
AM6
SNN_MIOB_D8
AL6
SNN_MIOB_D9
AL5
SNN_MIOB_D10
AM4
SNN_MIOB_D11
AN4
SNN_MIOB_D12
AK8
SNN_MIOB_D13
AJ6
SNN_MIOB_D14
AK7
MIOB_D15_STRAP0
AJ9
MIOB_D16_STRAP1
AK9
MIOB_D17_STRAP2
AL9
MIO Feature Connector
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OUT
OUT
OUT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
21
BI
21
BI
22
22
22
MIOA_D[14..0]
MIOA_D12
MIOA_D13
MIOA_D14
GPIO11_SLI_SYNC1
GPIO22_SWAPRDY_A
20
IN
CN1
CN1
CON_FINGER_MIO_026_D
CON_FINGER_MIO_026_D
COMMON
COMMON
SLI - EMI SHIELD
SLI - EMI SHIELD
A2
B4
A4
A5
B6
A6
A8
B9
B10
A10
B12
A12
A13
B5
A9
B13
B8
A1
B1
B2
DR<0>
DR<1>
DR<2>
DR<3>
DR<4>
DR<5>
DR<6>
DR<7>
DR<8>
DR<9>
DR<10>
DR<11>
DR<12>
DR<13>
DR<14>
DR_CMD
DR_CLK
RASTER_SYNC
SWAP_RDY
EXT_REFCLK
B3
GND
B7
GND
B11
GND
A3
GND
A7
GND
A11
GND
GND
1
GND
2
GND
3
GND
4
GND
1
2
GND
3
4
NV_CRITICAL_NET
NET
20
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
MIOA_D[14..0]
IN
MIOA_CLKIN
IN
MIOA_CLKOUT
IN
MIOA_DE
IN
NET
MIOA_VREF
IN
MIOA_CAL_PD_VDDQ
IN
MIOA_CAL_PU_GND
IN
MIN_LINE_WIDTH
1
1
1
1
5MIL
12MIL
12MIL
IMPEDANCE
VOLTAGE NV_NET_MAX_CURRENT
1.65V
2.5V
0.0V
DIFFPAIR
50OHM
50OHM
50OHM
50OHM
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
MIOB_CTL3
MIOB_HSYNC
MIOB_VSYNC
MIOB_DE
MIOB_CLKOUT
MIOB_CLKOUT
MIOB_CLKIN
AH7
AH9
AH5
AJ4
AK4
AK6
SNN_MIOB_HSYNC
SNN_MIOB_VSYNC
SNN_MIOB_DE
SNN_MIOB_CLKOUT
SNN_MIOB_CLKOUT*
MIOB_CLKIN
R614
10K
R614
10K
COMMON
0402
COMMON
0402
5%
5%
SNN_MIOB_CTL3
AH8
GND
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MIO A/B Interface
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 21
A B C D E F G H
Page21: MISC: GPIO, I2C, ROM, HDCP, and XTAL
1
2
SNN_BBIASN
SNN_BBIASP
SNN_HDSA_BCLK
HDA_RST*
SNN_HDA_SDI
R602
R602
SNN_HDA_SDO
10K
10K
SNN_HDA_SYNC
5%
5%
0402
0402
COMMON
COMMON
Binary Production Strap Mode:
STRAP_CALPD_MIOB = 40.2K 1%
STRAP_CALPD_MISC = NO STUFF
3
GND
R598
R598
0402
0402
1%
1%
R597 40.2K
R597 40.2K
1%
1%
40.2K
40.2K
COMMON
COMMON
COMMON0402
COMMON0402
STRAP_CALPD_MISC
STRAP_CALPD_MIOB
GND
SNN_THERMDN
SNN_THERMDP
4
2
2
2
2
2
JTAG_TCLK
IN
JTAG_TMS
IN
JTAG_TDI
IN
JTAG_TDO
OUT
JTAG_TRST*
IN
T1
T2
AP12
AR12
AR13
AP13
AP14
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
L31
L30
T6
V7
U6
T7
V6
Y11
W11
G1N
G1N
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
14/19 MISC1
14/19 MISC1
THERMDN
THERMDP
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST
G1O
G1O
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
15/19 MISC2
15/19 MISC2
BBIASN_NC
BBIASP_NC
HDA_BCLK
HDA_RST
HDA_SDI
HDA_SDO
HDA_SYNC
STRAP_REF_MISC
STRAP_REF_MIOB
I2CS_SCL
I2CS_SDA
I2CC_SCL
I2CC_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
ROM_SCLK
PGOOD_OUT
W2
W1
W3
W4
Y4
AA5
W6
W5
AB1
AB2
AB3
AD1
AD2
AD3
AB4
AB5
AB6
AB7
AB8
AB9
AC4
AC6
AA8
T9
U9
V9
W9
Y9
AA9
W7
W8
AA7
22
OUT
22
OUT
22
OUT
ROM_CS*
T4
ROM_CS
ROM_SI
ROM_SO
I2CH_SCL
I2CH_SDA
BUFRST
RFU_GND
SPDIF
ROM_SI
V4
ROM_SO
U4
ROM_SCLK
T5
Y6
AA6
SPDIF
V5
SNN_BUFRST*
V8
SNN_PGOOD_OUT*
T8
L15
RFU
AP15
25,25
IN
GND
3V3 3V3
I2CS_SCL
I2CS_SDA
SNN_I2CC_SCL
SNN_I2CC_SDA
I2CD_SCL
I2CD_SDA
SNN_I2CE_SCL
SNN_I2CE_SDA
GPIO0_DVI_A_HPD
GPIO1_HDMI_C_HPD
SNN_GPIO2
SNN_GPIO3
GPIO4_FAN_TACH
GPIO5_VSEL0
GPIO6_NVVDD_PHASE
SNN_GPIO7
GPIO8_GPU_SLOW*
GPIO9_FAN_PWM
GPIO11_SLI_SYNC1
SNN_GPIO12
SNN_GPIO13
SNN_GPIO14
SNN_GPIO15
SNN_GPIO16
SNN_GPIO18
SNN_GPIO19
SNN_GPIO20
SNN_GPIO21
GPIO22_SWAPRDY_A
SNN_GPIO23_STEREO
R660
R660
47K
47K
5%
5%
0402
0402
COMMON
COMMON
R658
R658
47K
47K
5%
5%
0402
0402
COMMON
COMMON
3V3 3V3
R726
R726
47K
47K
5%
5%
0402
0402
COMMON
COMMON
R727
R727
47K
47K
5%
5%
0402
0402
COMMON
COMMON
R665 33
R665 33
04025%COMMON
04025%COMMON
16
IN
17
IN
31
OUT
29
OUT
29
OUT
25
OUT
31
OUT
GPIO10_HDMI_TERM
20
OUT
GPIO17_HDMI_CEC
PUT THE 2 RESISTER NEAR PEX FINGER
R659
R657
33
R657
33
04025%COMMON
04025%COMMON
0402
0402
COMMON
COMMON
5%
5%
R664 33
R664 33
C GE
5%
5%
33R659
33
COMMON0402
COMMON0402
ASSEMBLY
PAGE DETAIL
3V3
U502
R646
R646
10K
10K
5%
5%
0402
0402
COMMON
COMMON
7
3
1
5
2
6
U502
SO08_I190X150
SO08_I190X150
SO8
SO8
COMMON
COMMON
HOLD8VCC
WP
CS
SI
SO
SCK
3V3
C779
C779
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
4
GND
COMMON
COMMON
GND
5V 5V
R676
R676
R675
R675
2.2K
2.2K
2.2K
2.2K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
PEX_SMCLK
PEX_SMDAT
I2CD_SCL_R
I2CD_SDA_R
2
IN
2
IN
OUT
OUT
PEX_VDD
LB506 220R@100MHZ
LB506 220R@100MHZ
IND_SMD_0402COMMON
IND_SMD_0402COMMON
C678
C678
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
3V3
R39
R39
1K
1K
1%
1%
0402
0402
COMMON
COMMON
OUT
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MISC: GPIO, I2C, ROM, HDCP, and XTAL
GND
20
GPIO TABLE
I/O
GPIO
0
IN
1
IN
2
N/A
3
N/A
N/A4
5
OUT
OUT
6
N/A
7
IN
8
9 OUT
10
N/A
11 N/A
IN12
13 OUT
IN14
15
IN
IN16
IN
17
IN
19
IN
IN
20
21
IN
22
IN
OUT
23
3V3
R671
R671
2K
2K
5%
5%
0402
0402
COMMON
COMMON
R672
R672
10K
10K
5%
5%
0402
0402
COMMON
COMMON
GND
Function
DVI HOTPLUG DET A
HDMI HOTPLUG DET E
SWAPREADY
NVVDD PHASE CONTROL
PWM TACH SIGNAL
VOLTAGE SELECT 0
VOLTAGE SELECT 1
FBVVDQ VOLTAGE CONTROL
GPU_SLOW*
PWM FAN CONTROL
UNUSED
SLI_RASTERY_SYNC
EXT_12V DETECT
UNUSED
UNUSED
UNUSED
DP_MODE
HDMI_EF
UNUSED18
HDMI_CEC
DP HOTPLUG DET F
UNUSED
SWAPREADY_A
UNUSED
C680
C680
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
R670
R670
2K
2K
5%
5%
0402
0402
COMMON
COMMON
C686
C686
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
R678 0
R678 0
0402 COMMON
0402 COMMON
5%
5%
C706
C706
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
I2CH_SCL
I2CH_SDA_R
GND
R693
R693
0
0
5%
5%
0402
0402
COMMON
COMMON
GND
GPU_PLLVDD
R618
R618
COMMON
COMMON
C697
C697
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
10K
10K
5%
5%
0402
0402
U503
U503
SO08_I190X150
SO08_I190X150
COMMON
COMMON
6
SCL
SDA
5
3
SDA
2
NC
GND GND
NET
XTALSSIN
IN
XTALIN
IN
XTALOUT
IN
XTALOUTBUFF
IN
NET
GPU_PLLVDD
IN
NV_CRITICAL
1 50OHM
1 50OHM
1 50OHM
1.1V
NV_IMPEDANCE DIFFPAIR
50OHM1
MAX_CURRENT
0.03A
MIN_WIDTHVOLTAGE
12MIL
1
2
3V3
8
VCC
7
VCC
GND
GND
C802
C802
.1UF
.1UF
16V
16V
4
10%
10%
1
X7R
X7R
0402
0402
COMMON
COMMON
GND
3
G1P
G1P
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
C39
C39
22PF
22PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
XTALIN
COMMON
16/19 XTAL_PLL
16/19 XTAL_PLL
AM13
PLLVDD
AM15
VID_PLLVDD
AM14
SP_PLLVDD
XTALOUT
XTALOUT
XTALOUTBUFFXTALSSIN
T3
V2
C38
C38
22PF
22PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
GND GND
PAGEID
DATE
30-DEC-2008
HFDBA
V3
XTALSSIN
V1
XTALIN
Y1
Y1
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
27MHZ_TV
27MHZ_TV
+/-10PPMXTAL_SMD_2_120X047
+/-10PPMXTAL_SMD_2_120X047
COMMON
COMMON
XTALOUTBUFF
NAME
R617
R617
330
330
5%
5%
0402
0402
COMMON
COMMON
4
5
www.vinafix.vn
Page 22
A B C D E F G H
Page22: Strap Configuration
1
2
3
21
IN
21
IN
21
IN
20
IN
ROM_SI
ROM_SO
ROM_SCLK
MIOB_D15_STRAP0
G1Q
G1Q
BGA_1504_P080_350X350
AC34
AC36
AC37
AC7
AF34
AF36
AF37
AF7
AG37
AG38
AH40
AJ7
AK32
AL32
AL40
AM29
AM30
AM31
AM32
AM7
AP34
AR36
AT11
AT13
AT35
AU14
AU17
AU20
AU23
AU26
AV10
AV12
AV28
AY31
C12
E15
E16
F16
F17
F20
F23
F31
G17
G20
G23
G26
G29
G8
H28
H7
J17
J20
J23
J29
J9
L14
L16
L28
L29
M3
M37
P11
P34
P36
R11
R3
R35
T11
U11
U36
U7
Y34
Y36
Y37
Y7
BGA_1504_P080_350X350
COMMON
COMMON
19/19 NC
19/19 NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
3V3
R640
R640
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
R647
R647
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
STRAP PIN
ROM_SI
STRAP NAME
PCI_DEVID_EXT
GND
3V3
R634
R634
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
R624
R624
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
STRAP PIN
ROM_SO SLOT_CLK_CFG
STRAP NAME
GND
3V3
R633
R633
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
R623
R623
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
STRAP PIN
ROM_SCLK PCI_DEVID[3]
STRAP NAME
GND
3V3
R42
R42
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
R45
R45
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
STRAP PIN
STRAP0
STRAP NAME
RAMCFG0
3V3 GND
15K
SNN_NC<1>
0
SNN_NC<2>
SNN_NC<3>
SNN_NC<4>
SNN_NC<5>
SNN_NC<6>
SNN_NC<7>
SNN_NC<8>
SNN_NC<9>
SNN_NC<10>
SNN_NC<11>
SNN_NC<12>
SNN_NC<13>
SNN_NC<14>
SNN_NC<15>
SNN_NC<16>
SNN_NC<17>
SNN_NC<18>
SNN_NC<19>
SNN_NC<20>
SNN_NC<21>
SNN_NC<22>
SNN_NC<23>
SNN_NC<24>
SNN_NC<25>
SNN_NC<26>
SNN_NC<27>
SNN_NC<28>
SNN_NC<29>
SNN_NC<30>
SNN_NC<31>
SNN_NC<32>
SNN_NC<33>
SNN_NC<34>
SNN_NC<35>
SNN_NC<36>
SNN_NC<37>
SNN_NC<38>
SNN_NC<39>
SNN_NC<40>
SNN_NC<41>
SNN_NC<42>
SNN_NC<43>
SNN_NC<44>
SNN_NC<45>
SNN_NC<46>
SNN_NC<47>
SNN_NC<48>
SNN_NC<49>
SNN_NC<50>
SNN_NC<51>
SNN_NC<52>
SNN_NC<53>
SNN_NC<54>
SNN_NC<55>
SNN_NC<56>
SNN_NC<57>
SNN_NC<58>
SNN_NC<59>
SNN_NC<60>
SNN_NC<61>
SNN_NC<62>
SNN_NC<63>
SNN_NC<64>
SNN_NC<65>
SNN_NC<66>
SNN_NC<67>
SNN_NC<68>
SNN_NC<69>
SNN_NC<70>
SNN_NC<71>
SNN_NC<72>
SNN_NC<73>
SNN_NC<74>
SNN_NC<75>
GND
3V3
R43
R43
4.99K
4
MIOB_D16_STRAP1
20
IN
4.99K
1%
1%
0402
0402
COMMON
COMMON
R46
R46
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
STRAP PIN
STRAP1
STRAP NAME
RAMCFG1
RAMCFG[2:0]
*
256MB (8Mx32)
101 --- 256-bit Qimonda
110 --- 256-bit Hynix
111 --- 256-bit Samsung
* VBIOS will be defined on a per SKU basis.
GND
3V3
R44
R44
4.99K
4.99K
1%
1%
0402
0402
COMMON
MIOB_D17_STRAP2
20
IN
5
COMMON
R47
R47
4.99K
4.99K
1%
1%
0402
0402
COMMON
COMMON
STRAP PIN
STRAP2
STRAP NAME
RAMCFG2
GND
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
512MB (16Mx32)
001 --- 256-bit Qimonda
010 --- 256-bit Hynix
011 --- 256-bit Samsung
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Strap Configuration
1024MB (32Mx32)
101 --- 256-bit Hynix
110 --- 256-bit Hynix
111 --- 256-bit Samsung
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 23
A B C D E F G H
Page23: PWR and GND Signals
G1R
AA13
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AC13
AA14
AC15
AC17
AC19
AC21
AC23
AC25
AC27
AC29
AD13
AD14
AA15
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AA16
AD25
AD26
AD27
AD28
AD29
AD30
AE14
AE16
AE18
AE20
AA17
AE22
AE24
AE26
AE28
AE30
AG13
AA18
AA19
AA20
AA21
P20
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG29
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
Y27
Y29
G1R
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
18/19 NVVDD
18/19 NVVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
1
2
3
4
NVVDD
N23
VDD
N24
VDD
N25
VDD
N26
VDD
N27
VDD
N28
VDD
N29
VDD
N30
VDD
P14
VDD
P16
VDD
P18
VDD
N22
VDD
AH28
VDD
N21
VDD
AH29
VDD
AH30
VDD
AJ14
VDD
AJ16
VDD
AJ18
VDD
AJ20
VDD
AJ24
VDD
AJ26
VDD
AJ28
VDD
AJ30
VDD
N20
VDD
N13
VDD
N14
VDD
N15
VDD
N16
VDD
N17
VDD
N18
VDD
N19
VDD
P22
VDD
P24
VDD
P26
VDD
P28
VDD
P30
VDD
T13
VDD
T15
VDD
T17
VDD
T19
VDD
T21
VDD
T23
VDD
T25
VDD
T27
VDD
T29
VDD
U13
VDD
U14
VDD
U15
VDD
U16
VDD
U17
VDD
U18
VDD
U19
VDD
U20
VDD
U21
VDD
U22
VDD
U23
VDD
U24
VDD
U25
VDD
U26
VDD
U27
VDD
U28
VDD
U29
VDD
U30
VDD
V14
VDD
V16
VDD
V18
VDD
V20
VDD
V22
VDD
V24
VDD
V26
VDD
V28
VDD
V30
VDD
Y13
VDD
Y15
VDD
Y17
VDD
Y19
VDD
Y21
VDD
Y23
VDD
Y25
VDD
G1S
G1S
BGA_1504_P080_350X350
BGA_1504_P080_350X350
COMMON
COMMON
AF16
AF15
AF14
AF13
AE29
AE27
AE25
AE23
GND
GND
GND
GND
GND
GND
GND
GND
17/19 GND
17/19 GND
GND
GND
GND
GND
GND
GND
GND
GND
AB27
AB26
AB25
AB24
AB23
AB22
AB21
AA11
GND
AF23
AF22
AF21
AF20
AF2
AF19
AB16
AF18
AF17
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AC2
AB13
AB30
AB29
AB28
AC20
AC18
AC16
AC14
AF35
AF30
AF29
AF28
AB17
AF27
AF26
AF25
AF24
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AB14
AC41
AC38
AC35
AC30
AC28
AC26
AC24
AC22
AG20
AG18
AG16
AB18
AG14
AG11
AF8
AF5
AF41
AF38
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AC8
AC5
AK22
AK21
AB15
AE21
AE19
AE17
AE15
AE13
AJ17
AB19
AJ15
AJ13
AG30
AG28
AG26
AG24
AG22
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AM2
AK30
AK29
AK28
AK27
AK26
AK25
AK24
AK23
BA26
BA23
BA20
BA2
BA17
BA14
BA11
AB20
GND
GND
GND
GND
GND
GND
GNDB8GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AM8
AM5
AP26
AP23
AP20
AR11
AM41
AM38
AM35
E11
BA8
BA5
BA41
BA38
BA35
BA32
BA29
GNDC3GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AR2
AR35
AR32
AR29
AR26
AR23
AR20
AR17
AR14
E35
E32
E29
E26
E23
E20
E17
E14
GND
GND
GND
GND
GND
GNDE2GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AR8
AR5
AT26
AT23
AT20
AT17
AT14
AR41
AR38
AJ35
AJ29
AJ27
AJ25
AJ23
AJ2
AJ19
E41
E38
GND
GND
GND
GND
GND
GNDE5GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AV2
AV32
AV29
AV26
AV23
AV20
AV17
AV14
AV11
AU37
AK17
AK16
AK15
AK14
AK13
AJ8
AJ5
AJ41
AJ38
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B17
B14
B11
AV8
AV5
AY40
AV41
AV38
AV35
H14
H11
F29
F26
AK20
AK19
AK18
GND
GND
GND
GND
GNDF6GND
GND
GNDE8GND
GND
GND
GND
GND
GND
GND
GND
GNDB2GND
B41
B38
B35
B32
B29
B26
B23
B20
H41
H38
H35
H32
H29
H26
H23
H20
H17
GND
GND
GND
GND
GND
GND
GND
GNDH2GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDB5GND
R24
T18
T16
T14
R30
R29
R28
R27
R26
R25
P15
P13
L41
L38
L35
GND
GNDL8GNDL5GND
GND
GND
GNDL2GNDH8GNDH5GND
GND
GNDU2GND
GND
GND
GND
GND
GND
GND
T30
T28
T26
T24
T22
T20
U37
U35
P35
P29
P27
P25
P23
P21
P19
P17
GND
GND
GND
GND
GND
GNDP2GND
GND
GND
GND
GND
GND
GND
GNDU8GNDU5GND
GND
GND
V19
V17
V15
V13
V11
U41
U38
R16
R15
R14
R13
P41
P38
P37
GND
GND
GND
GNDP8GNDP5GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V29
V27
V25
V23
V21
W16
W15
W14
W13
Y14
W30
R23
R22
R21
R20
R19
R18
R17
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
W25
W24
W23
W22
W21
W20
W19
W18
W17
Y8
Y41
Y38
Y24
Y22
Y20
Y18
Y16
GNDY5GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDY2GND
GND
GND
GND
GND
Y35
Y30
Y28
Y26
W29
W28
W27
W26
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PWR and GND Signals
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 24
A B C D E F G H
Page24: NVVDD and FBVDDQ Decoupling
1
NVVDD
2
3
C695
C695
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C679
C679
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C684
C684
.22UF
.22UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C692
C692
.22UF
.22UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C668
C668
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C659
C659
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
NVVDD
Place under GPU
C633
C633
C681
C681
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C654
C654
C674
C674
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C698
C698
C661
C661
.22UF
.22UF
.22UF
.22UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C643
C643
C635
C635
.22UF
.22UF
.22UF
.22UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C683
C683
C644
C644
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C636
C636
C688
C688
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C638
C638
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C665
C665
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C656
C656
.22UF
.22UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C652
C652
.22UF
.22UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C648
C648
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C734
C734
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C682
C682
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C623
C623
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C631
C631
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
FBVDDQ
Place near BGA
C740
C740
C694
C694
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C616
C616
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C618
C618
C733
C733
.47UF
.47UF
.47UF
.47UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C611
C611
C720
C720
.47UF
.47UF
.47UF
.47UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C691
C691
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C624
C624
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
GND
GND
NVVDD
Place close to GPU
NVVDD
C743
C743
C614
C701
C701
C641
C641
10UF
10UF
10UF
10UF
6.3V
6.3V
6.3V
6.3V
20%
20%
20%
20%
X5R
X5R
X5R
X5R
0805
0805
0805
0805
COMMON
COMMON
COMMON
COMMON
C582
C582
C585
GND
GND
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C655
C655
22UF
22UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C585
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C658
C658
22UF
22UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
GND
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C597
C597
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C670
C670
22UF
22UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C614
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
GND
GND
GND
FBVDDQ
GND
GND
C625
C625
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
GND
GND
0402
COMMON
COMMON
C622
C622
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C709
C709
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C708
C708
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C620
C620
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C628
C628
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
1
2
3
GND
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
NVVDD and FBVDDQ Decoupling
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 25
A B C D E F G H
Page25: SPDIF Input, Thermal Protection, and IFP_IOVDD Power Supply
1
IN
IN
IN
IN
IN
21,25 SPDIF
IN
NET
SPDIF_IN_C
SPDIF_IN_R
SPDIF_IN_COMP2_D
SPDIF_IN_COMP2_Q
SPDIF_IN
IMPEDANCE
56OHM 1
NV_CRITICAL_NET
156OHM
156OHM
156OHM
156OHM
175OHM
1
Thermal Protection
3V3
R698
R698
2K
2K
5%
5%
0402
0402
COMMON
2
PEX_RST*
2,2
IN
3
4
COMMON
R11-0202012-Y01
R11-0202012-Y01
THERM_N_EN1
1G1D1S
1G1D1S
G
1
R699 1K
R699 1K
PEX_RST_R*
COMMON
0402
COMMON
0402
5%
5%
R11-0102032-W08
R11-0102032-W08
IFP_IOVDD Backdrive Prevention
THERM_N_EN1_R
1G1D1S
1G1D1S
3
D
Q512
G
1
3
D
Q513
Q513
D03-0700239-O05
D03-0700239-O05
SOT23
SOT23
COMMON
COMMON
S
2
60V
60V
0.115A
0.115A
7.5R
7.5R
0.8A
0.8A
0.2W
0.2W
20V
20V
D03-0700239-O05
D03-0700239-O05
GND
C821
C821
100PF
100PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
C11-1011032-M09
C11-1011032-M09
GND
Q512
SOT23
SOT23
COMMON
COMMON
S
2
60V
60V
0.115A
0.115A
7.5R
7.5R
0.8A
0.8A
0.2W
0.2W
20V
20V
GND
1G1D1S
1G1D1S
G
1
D03-0700239-O05
D03-0700239-O05
D
S
Q510
Q510
SOT23
SOT23
COMMON
COMMON
3
2
60V
60V
0.115A
0.115A
7.5R
7.5R
0.8A
0.8A
0.2W
0.2W
20V
20V
SOT23
SOT23
COMMON
COMMON
R683
R683
33K
33K
5%
5%
0402
0402
COMMON
COMMON
R11-0333012-R01
R11-0333012-R01
GND
3V3_TMDS_IOVDD_EN
R695 10K
R695 10K
3V3
R697
R697
2K
2K
5%
5%
0402
0402
COMMON
COMMON
1B1C1E
1B1C1E
2
E
Q509
Q509
R11-0202012-Y01
R11-0202012-Y01
B
1
C
3
THERM_N_EN3
D02-0440319-O05
D02-0440319-O05
1G1D1S
1G1D1S
0402
0402
5%
5%
COMMON
COMMON
R11-0103012-Y01
R11-0103012-Y01
21
C11-1042542-T04
C11-1042542-T04
R685
10K
R685
10K
04025%COMMON
04025%COMMON
R11-0103012-Y01
R11-0103012-Y01
R684
10K
R684
10K
0402
COMMON
0402
COMMON
5%
5%
R11-0103012-Y01
R11-0103012-Y01
3V3
3
D
Q511
Q511
SOT23
SOT23
G
1
COMMON
COMMON
S
-8V
-8V
2
-2.8A@70C
-2.8A@70C
52mR
52mR
-6A
-6A
0.8W@70C
0.8W@70C
+/-8V
+/-8V
D03-0230519-V02
D03-0230519-V02
GPIO8_GPU_SLOW*
IN
C801
C801
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
THERM_N_EN2
COMMON
COMMON
THERM_N_EN3_R1
C11-1022032-T04
C11-1022032-T04
THERM_N_EN3_R2
GND
C11-1022032-T04
C11-1022032-T04
C800
C800
1000PF
1000PF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C786
C786
1000PF
1000PF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
1B1C1E
1B1C1E
R687
R687
2K
2K
5%
5%
0402
0402
COMMON
COMMON
R11-0202012-Y01
R11-0202012-Y01
R686
R686
2K
2K
5%
5%
0402
0402
COMMON
COMMON
3
R11-0202012-Y01
R11-0202012-Y01
C
Q507
Q507
B
1
SOT23
SOT23
COMMON
COMMON
E
2
D02-2222A49-D07
D02-2222A49-D07
GND
1B1C1E
1B1C1E
B
1
C820
C820
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
NVVDD_EN
3
C
Q508
Q508
SOT23
SOT23
COMMON
COMMON
E
2
D02-2222A49-D07
D02-2222A49-D07
GND
0.2A
16MIL
OUT
C793
C793
1000PF
1000PF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
C11-1022032-T04
C11-1022032-T04
IFP_IOVDD
C818
C818
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C11-1042542-T04
C11-1042542-T04
GND
SPDIF Input
3V3
D9
D9
SOT23
SOT23
3
100V
100V
100MA
100MA
COMMON
COMMON
3V3
R20
R20
33K
33K
5%
5%
0402
0402
COMMON
COMMON
R25
R25
0402
0402
C17
C17
R11-0103012-Y01
R11-0103012-Y01
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
1 2
D01-BAV9929-D07
D01-BAV9929-D07
GND
10K
10K
COMMON
COMMON
5%
5%
SPDIF_IN_R
1B1C1E
1B1C1E
B
1
C
E
D02-2222A49-D07
D02-2222A49-D07
Black, RA, 2.0mm, SPDIF connector
29
J7
J7
1
2
MALE
MALE
2.0MM
2.0MM
90
90
CON_WAFER232_002_TH_RA_P020
CON_WAFER232_002_TH_RA_P020
COMMON
COMMON
N32-1020941-H06
N32-1020941-H06
1
75OHM
SPDIF_IN
SPDIF_GND
16MIL
0V
12
F501
F501
R700
R700
350MA
350MA
0
0
1206
1206
5%
5%
COMMON
COMMON
0402
0402
POLYSWITCH
POLYSWITCH
COMMON
COMMON
R11-0000012-W08
R11-0000012-W08
GND
short circuit protection
if 3.3V connects to GND.
C15
.01UF
C15
.01UF
0402 16V
0402 16V
10%
10%
X7R
X7R
COMMON
COMMON
C11-1032012-T34
C11-1032012-T34
R19
2.2K
R19
2.2K
COMMON
COMMON
0402
0402
5%
5%
R11-0222012-W08
R11-0222012-W08
1
56OHM
SPDIF
SPDIF_IN_C
R11-0333012-R01
R11-0333012-R01
C11-1042542-T04
C11-1042542-T04
GND
12V
R27
R27
10K
10K
5%
5%
0402
0402
COMMON
COMMON
R11-0103012-Y01
R11-0103012-Y01
SPDIF_IN_COMP2_D
3
Q4
Q4
SOT23
SOT23
COMMON
COMMON
2
GND
3V3
R22
R22
180K
180K
5%
5%
0402
0402
COMMON
COMMON
R21
R21
180K
180K
5%
5%
0402
0402
COMMON
COMMON
R11-0184012-Y01
R11-0184012-Y01
GND
C23
C23
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C11-1032012-T34
C11-1032012-T34
GND
SPDIF_IN_COMP2_Q
1G1D1S
1G1D1S
D
G
1
S
D03-0700239-O05
D03-0700239-O05
21,25
OUT
R26
R26
75
75
1%
1%
0603
0603
COMMON
COMMON
R11-0750T13-Y01
R11-0750T13-Y01
3
Q5
Q5
SOT23
SOT23
COMMON
COMMON
2
60V
60V
0.115A
0.115A
7.5R
7.5R
0.8A
0.8A
0.2W
0.2W
20V
20V
GND
2
3
4
GND
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
SPDIF Input, Backdrive Protection, and IFP_IOVDD Power Supply
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 26
A B C D E F G H
Page26: PS I: 3V3, 12V, and 12V_EXT Power Supply Filter
1
NET MIN_WIDTHMAX_CURRENTVOLTAGE
12V
12V
GND
GND
12V
0V
5.5A 16MIL
28A 16MIL
1
2
12V Power Supply Filter
2
12V_F = 12V @ 5.5A
12V
C67
C67
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
3
4
L11 1UH
L11 1UH
6.84A
6.84A
8.4M OHMS
8.4M OHMS
LB502
IND_SMD_0805COMMON
IND_SMD_0805COMMON
LB7
IND_SMD_0805COMMON
IND_SMD_0805COMMON
LB8
LB501
LB501
IND_SMD_0805
IND_SMD_0805
COMMONIND_NONRKO_SMD_076X076
COMMONIND_NONRKO_SMD_076X076
600R@100MHZLB502
600R@100MHZ
600R@100MHZLB7
600R@100MHZ
600R@100MHZLB8
600R@100MHZ
COMMONIND_SMD_0805
COMMONIND_SMD_0805
600R@100MHZ
600R@100MHZ
COMMON
COMMON
12V_F
12V
5.5A
16MIL
C72
C72
1UF
1UF
25V
25V
10%
10%
X7R
X7R
0805
0805
COMMON
COMMON
GND
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PS I: 3V3, 12V, and 12V_EXT Power Supply Filter
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 27
A B C D E F G H
Page27: PS II: IFP_PLLVDD, 2V5, 5V, and DDC_5V Power Supply
1
2
3
12V
D10
D10
R28
R28
0
0
DIODE_SMD_SMA
DIODE_SMD_SMA
5%
5%
40V
40V
0603
0603
3A
3A
U1
COMMON
COMMON
PS_5V_VCC
C26
C26
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0603
0603
COMMON
COMMON
U1
ADJ_VR=1.25V
ADJ_VR=1.25V
GOI,IGOI,TO263
GOI,IGOI,TO263
MULTI_STD_SOT223_DPAK
MULTI_STD_SOT223_DPAK
COMMON
COMMON
OUT3IN
TAB
GND/ADJ
1
C16
C16
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
2
4
COMMON
COMMON
1 2
C20
C20
1UF
1UF
25V
25V
10%
10%
X7R
4
X7R
0805
0805
COMMON
COMMON
GND
2V5 Power Supply
3V3
12V
R30
R30
1.4K
1.4K
1%
1%
0402
0402
COMMON
COMMON
R36
R36
1K
1K
5%
5%
0402
0402
COMMON
COMMON
GND
5V and DDC_5V Power Supply
DDC_5V = 5V @ 200mA
LAYOUT NOTE:
PS_5V_ADJ
ADD MIN 200MM^2 COPPER AROUND THIS DPAK FOR HEAT DISSIPATION
R24
R24
124
124
Rt
1%
1%
0402
0402
COMMON
COMMON
R23
R23
383
383
Rb
1%
1%
0402
0402
COMMON
COMMON
GND
GND
Vref=1.256V
Vo_Typ=1.256*(1+383/124)+60uA*383=5.16V
C19
C19
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
1
3V3
C29
C29
C28
C28
1UF
1UF
1UF
1UF
6.3V
6.3V
25V
25V
10%
10%
10%
10%
X5R
X5R
X7R
X7R
0402
0402
0805
0805
COMMON
COMMON
COMMON
C33
C33
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
COMMON
GND
PS_2V5_VDD
SNN_2V5_PGOOD
GND
GND
12MIL
U3
U3
SO08_I190X150_TI118X102
SO08_I190X150_TI118X102
COMMON
COMMON
3
VIN
VOUT
NC
4
VDD
EN
2
1
PGOOD
ADJ
GND
8
THERMGND
9
GND
Vout=Vref*(1+Rt/Rb)
2.52=0.8*(1+22.6/10.5)
6
SNN_2V5_NC
5
7
PS_2V5_ADJ
12MIL
C36
C36
1000PF
1000PF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R41
R41
0
0
5%
5%
0805
0805
COMMON
COMMON
GND
R40
R40
22.6K
22.6K
1%
1%
0402
0402
COMMON
COMMON
R38
R38
10.5K
10.5K
1%
1%
0402
0402
COMMON
COMMON
2.5V
1A
16MIL
C37
C37
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
GND GND
2V5
C35
C35
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
2
3
IFP_PLLVDD Power Supply
IFP_PLLVDD = 1.8V @ 200mA
FBVDDQ
R29
R29
0
0
5%
5%
0402
0402
COMMON
COMMON
5
C32
C32
.1UF
.1UF
Rt
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
PS_1V8_ADJ
Rb
1.8V
IFP_PLLVDD
20MIL
0.2A
R35
R35
1K
1K
1%
1%
C27
C27
0402
0402
10UF
10UF
COMMON
COMMON
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
R37
R37
COMMON
COMMON
806
806
1%
1%
0402
0402
COMMON
COMMON
GND
GND
4
5V
C18
C18
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
U2
F502
F502
200mA
200mA
1206
1206
5V
COMMON
COMMON
0.2A
16MIL
1 2
POLYSWITCH
POLYSWITCH
DDC_5V
5V
0.2A
16MIL
C838
C838
220PF
220PF
50V
50V
5%
5%
C0G
C0G
0603
0603
COMMON
COMMON
GND
3V3
C34
C34
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
U2
ADJ_VR=0.8V
ADJ_VR=0.8V
SOT23-5
SOT23-5
SOT23_5
SOT23_5
COMMON
COMMON
1
IN
3
EN4ADJ
Vref=0.8V
Vo_Typ=0.8*(1+1/0.806)=1.793V
OUT
GND
2
GND
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PS II: IFP_PLLVDD, 2V5, 5V, and DDC_5V Power Supply
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 28
A B C D E F G H
Page28: PS III: FBVDDQ Power Supply
1
C22
C22
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
FBVDDQ
MULTI_STD_SOT223
MULTI_STD_SOT223
0.100R
0.100R
50W@25C
50W@25C
30V
30V
12A
12A
30A
30A
20V
20V
COMMON
COMMON
4
2
D
Q333
Q333
S
3
2
3
PEXVDD Power Supply
PEXVDD = 1.1V @ 3A
PEX_VDD
GND
C21
C21
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
NET
MIN_LINE_WIDTH VOLTAGE NV_NET_MAX_CURRENT
FBVDDQ
FBVDDQ
PS_FB_BOOT
IN
PS_FB_UGATE
IN
PS_FB_UGATE_R
IN
PS_FB_PHASE
IN
PS_FB_LGATE
IN
PS_FB_COMP
IN
PS_FB_FB
IN
PS_FB_RC
IN
PS_FB_RBOT
IN
PS_FB_SNUB
IN
FBVDDQ_SENSE_R
IN
PEX_VDD
PEX_VDD
PS_FB_PVCC5
IN
PS_FB_VCC5
IN
PS_1V1_DR
IN
PS_1V1_FB
IN
PS_1V1_CP
IN
PS_FBVDDQ_FS
C69
C69
270UF
270UF
COMMON
COMMON
20%
20%
16V
16V
FPCAP
FPCAP
5A@105C
5A@105C
0.008R
0.008R
CAP_TH_D080P035
CAP_TH_D080P035
ALTERNATES
L6 0.60UH
L6 0.60UH
COMMON
IND_NONRKO_TH_115X115
COMMON
IND_NONRKO_TH_115X115
L5
L5
COMMON
IND_NONRKO_TH_115X115_B
COMMON
IND_NONRKO_TH_115X115_B
0.68UH
0.68UH
IN
FBVDDQ Power Supply
FBVDDQ = 1.8 V@ 12A
FBVDDQ = 2.0 V@ 12A
12V
12V_F
D
Q11
Q11
DFET_SMD_DPAK_VIAS
DFET_SMD_DPAK_VIAS
COMMON
COMMON
S
D
Q8
Q8
DFET_SMD_DPAK_VIAS
DFET_SMD_DPAK_VIAS
COMMON
COMMON
S
GND
2
3
2
3
Irms = 4.5A @ 2.0V/12A
Irms = 4.5A @ 1.8V/12A
C514 1UF
C514 1UF
0603
0603
25V
25V
11.3A@25C
11.3A@25C
9.3M@10V
9.3M@10V
98A
98A
1.95W@25C
1.95W@25C
+/-20V
+/-20V
PS_FB_PHASE
25V
25V
14A@25C
14A@25C
0.0052R@10V
0.0052R@10V
146A
146A
2W@25C
2W@25C
+/-20V
+/-20V
16V
16V
10%
10%
X5R
X5R
COMMON
COMMON
C519
C519
680PF
680PF
50V
50V
5%
5%
C0G
C0G
0603
0603
COMMON
COMMON
C517
C517
C68
C68
10UF
10UF
10UF
10UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
1206
1206
1206
1206
COMMON
COMMON
COMMON
COMMON
GND
C527
C527
2200PF
2200PF
50V
50V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
PS_FB_SNUB
R523
R523
1
1
5%
5%
1206
1206
COMMON
COMMON
GND
0.000842R
0.000842R
42A
42A
32A
32A
0.001R
0.001R
50A
50A
30A
30A
GND
R73 2.2
R73 2.2
0603
0603
5%
5%
COMMON
COMMON
C53
C53
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
COMMON
COMMON
VCC12
PVCC5
UGATE
PHASE
LGATE
SW_FB
COMP
BOOT
8
10
1
14
13
11
4
3
PS_FB_RC_CP
GND
PS_FB_PVCC5
GND
PS_FB_BOOT
PS_FB_UGATE
PS_FB_LGATE
PS_FB_FB
PS_FB_COMP
C54
C54
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
R58
R58
1.69K
1.69K
1%
1%
0402
0402
COMMON
COMMON
C45
C45
.022UF
.022UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
PS_FB_VCC12
1G1D1S
1G1D1S
C47
C47
330PF
330PF
50V
50V
5%
5%
C0G
C0G
0402
0402
COMMON
COMMON
PS_FB_UGATE_R
R74
0
R74
0
COMMON
COMMON
0402
0402
5%
5%
C49
C49
0402
0402
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
COMMON
COMMON
G
1
D03-008030B-N03
D03-008030B-N03
1G1D1S
1G1D1S
G
1
C528
C528
1000PF
1000PF
16V
16V
10%
10%
D03-004030B-N03
D03-004030B-N03
X7R
X7R
0402
0402
COMMON
COMMON
R69
10
R69
10
0402
0402
5%
PS_FB_VCC5
9
5
6
2
12
7
U4
U4
VR_SW=0.8V
VR_SW=0.8V
SO14_I335X150
SO14_I335X150
SO14
SO14
COMMON
COMMON
VCC5
LDO_DR
LDO_FB
FS_DIS
PGND
GND
80.6K ~400KHz
97.6K ~300KHz
5%
C25
C25
C24
C24
1UF
1UF
10UF
10UF
16V
16V
6.3V
6.3V
10%
10%
20%
20%
X5R
X5R
X5R
X5R
0805
0805
0603
0603
COMMON
COMMON
COMMON
COMMON
GND
0402 COMMON
0402 COMMON
1%
1%
Near Mosfet
R17
0
R17
0
COMMON
COMMON
0402
0402
5%
5%
R61
R61
2.61K
2.61K
1%
1%
0402
0402
COMMON
COMMON
PS_1V1_CP
R60
R60
200
200
5%
5%
0402
0402
COMMON
COMMON
C46
C46
1000PF
1000PF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
1G2D1S
1G2D1S
PS_1V1_DR_R
G
1
C12
C12
1000PF
1000PF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
R63 1.05K
R63 1.05K
GND
PS_1V1_DR
PS_1V1_FB
PS_FBVDDQ_FS
R59
R59
80.6K
80.6K
1%
1%
0402
0402
COMMON
COMMON
C55
C55
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
GND
Vout = Vref * (1+Rtop/Rbot)
1.12V = 0.8V * (1+1.05k/2.61k)
GND
C530
C530
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
16MIL
16MIL
16MIL
16MIL
5MIL
5MIL
5MIL
5MIL
16MIL
5MIL
16MIL
16MIL
12MIL
5MIL
5MIL
5MIL
C60
C529
C529
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C60
560UF
560UF
COMMON
COMMON
20%
20%
2.5V
2.5V
XCON
XCON
4.18A@105C
4.18A@105C
0.007R
0.007R
CAP_TH_D050P020
CAP_TH_D050P020
C59
C59
820UF
820UF
COMMON
COMMON
20%
20%
2.5V
2.5V
NPCAP
NPCAP
6.1A@105C
6.1A@105C
0.007R
0.007R
CAP_TH_D080P035
CAP_TH_D080P035
GND
16A <<OCC_ONLY>>2.0V20MIL
16A16MIL
2A <<OCC_ONLY>>1.1V20MIL
1
2
FBVDDQ
3
4
C48
C48
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
12V
R64
R64
10K
10K
5%
5%
0402
0402
COMMON
COMMON
1G1D1S
1G1D1S
3
D
Q6
Q6
SOT23
PS_FB_EN*
3
C
Q7
Q7
B
1
SOT23
SOT23
COMMON
COMMON
E
2
SOT23
G
1
COMMON
COMMON
S
60V
60V
2
0.115A
0.115A
7.5R
7.5R
0.8A
0.8A
0.2W
0.2W
20V
20V
GND
NVVDD
R65
R65
10K
10K
5%
5%
0402
0402
COMMON
COMMON
PS_FB_EN
R66
R66
30K
30K
5%
5%
0402
0402
COMMON
COMMON
1B1C1E
1B1C1E
5
GND
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
R56
R56
0402
0402
R62
R62
1.24K
Rbot
1.24K
1%
1%
0402
0402
COMMON
COMMON
PS_FB_RC
280
280
COMMON
COMMON
1%
1%
R54
1.54K
R54
1.54K
COMMON
0402
COMMON
0402
1%
1%
Rtop
GND
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PS III: FBVDDQ Power Supply
C44
.01UF
C44
.01UF
0402
0402
16V
16V
10%
10%
X7R
X7R
COMMON
COMMON
FBVDDQ_SENSE_R
FBVDDQ = VREF * (1 + (Rtop / Rbot1))
2.0V = 0.8V * (1 + (1.54K/ 1.02K))
1.8V = 0.8V * (1 + (1.54K/ 1.24K))
R55
R55
0402
0402
R57
R57
OPTIONAL
100
100
COMMON
COMMON
0402
0402
5%
5%
0
0
5%
5MIL
FBVDDQ_SENSE
COMMON
COMMON
5%
4
IN
4
5
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
PAGEID
DATE
30-DEC-2008
HFDBA
Page 29
A B C D E F G H
Page29: PS IV: NVVDD
Irms = 6.52A@1.0V/35A
MIN_LINE_WIDTH
NVVDD
NVVDD
1
PS_NVVDD_RC_CP
C525
.01UFC525
.01UF
16V
0402
16V
0402
10%
10%
X7R
X7R
COMMON
COMMON
C518
47PFC518
47PF
50V
50V
0402
0402
5%
5%
C0G
C0G
COMMON
R508
R508
1K
1K
5%
5%
0402
0402
COMMON
COMMON
GPIO6_NVVDD_PHASE_R
R507 1K
R507 1K
04025%COMMON
04025%COMMON
COMMON
2
3V3
GND
21
IN
GPIO6_NVVDD_PHASE
3
NVVDD ENABLE
NVVDD_EN
25
IN
3V3
R522
R522
15K
15K
5%
5%
0402
0402
COMMON
COMMON
R520
R520
C523
C523
10K
10K
.1UF
.1UF
5%
5%
16V
16V
0402
0402
10%
10%
COMMON
COMMON
X7R
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
X7R
0402
0402
COMMON
COMMON
GND
12V
R525
R525
12.7K
12.7K
1%
1%
0402
0402
COMMON
COMMON
PS_NVVDD_EN
R526
R526
1K
1K
1%
1%
0402
0402
COMMON
COMMON
R514 8.45K
R514 8.45K
1%
1%
1G1D1S
1G1D1S
GND
1B1C1E
1B1C1E
1B1C1E
1B1C1E
C526
C526
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
COMMON0402
COMMON0402
C513
C513
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
G
1
C
B
1
E
C
B
1
E
VOLTAGENET
1.0V30MIL 35A
PS1_NVVDD_SUS_R
3
D
Q501
Q501
SOT23
SOT23
COMMON
COMMON
S
2
60V
60V
0.115A
0.115A
7.5R
7.5R
0.8A
0.8A
0.2W
0.2W
20V
20V
GND
PS_NVVDD_EN*
3
Q502
Q502
SOT23
SOT23
COMMON
COMMON
2
PS_NVVDD_EN_AND
3
Q503
Q503
SOT23
SOT23
COMMON
COMMON
2
GND
NV_NET_MAX_CURRENT
C502
C502
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
350KHz Per Phase
R515
R515
16.5K
16.5K
1%
1%
0402
0402
COMMON
COMMON
SS =3.08mS
12V
R517
R517
10K
10K
5%
5%
0402
0402
COMMON
COMMON
R502
0402
0402
PS_NVVDD_PVCC9
1G1D1S
1G1D1S
Put the cap near Vreg pin
2.2R502
2.2
COMMON
COMMON
5%
5%
R511
1K
R511
1K
0402
COMMON
0402
COMMON
5%
5%
C515
C515
.022UF
.022UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
D
Q504
Q504
SOT23
SOT23
G
1
COMMON
COMMON
S
GND
PS_NVVDD_VCC9
GND
3
2
60V
60V
0.115A
0.115A
7.5R
7.5R
0.8A
0.8A
0.2W
0.2W
20V
20V
C501
C501
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
PS_NVVDD_CP
PS_NVVDD_FB
PS_NVVDD_SUS
PS1_NVVDD_FS
PS1_NVVDD_SS
SNN_NVVDD_VREF
AGND should have
low impedance
GND
12V
R501
U501
U501
VR_SW=0.6V
VR_SW=0.6V
QFN024Q_P050_I0179_TI108X108
QFN024Q_P050_I0179_TI108X108
COMMON
COMMON
21
VCC9
22
PVCC9
10
COMP
11
FB
MODE
7
9
RT
14
SS
6
REFIN
5
AGND
2
PGND1
17
PGND2
25
PGND3
2.25%R501
2.2
COMMON0603
COMMON0603
5%
C503
C503
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
0
0
COMMON
COMMON
5%
GND
5%
R504
R504
0402
0402
PS_NVVDD_DRVH1_R
C512 .1UF
C512 .1UF
PS_NVVDD_VCC
2 PHASE PWM
2 PHASE PWM
NC
1
SNN_NVVDD_NC1
SNN_NVVDD_NC2
20
VCC12
PS_NVVDD_DRVH1
3
UGATE1
PS_NVVDD_BOOT1
4
BOOT1
PS_NVVDD_PH1
24
PHASE1
PS_NVVDD_DRVL1
23
LGATE1
PS_NVVDD_DRVH2
16
UGATE2
PS_NVVDD_BOOT2
15
BOOT2
PS_NVVDD_PH2
18
PHASE2
19
LGATE2
8
IMAX
NC
12NC13
PS_NVVDD_OC
PS_NVVDD_DRVL2
R516
R516
30.1K
SNN_NVVDD_NC3
30.1K
1%
1%
0402
0402
COMMON
COMMON
R503
R503
0
0
5%
5%
PS_NVVDD_DRVH2_R
0402
0402
COMMON
COMMON
C511 .1UF
C511 .1UF
GND
Imax total= 70A
3V3
R518
R518
10K
10K
5%
5%
0402
0402
COMMON
COMMON
NVVDD_VSEL0
R5195%10K
GPIO5_VSEL0
21
IN
R5195%10K
COMMON0402
COMMON0402
C GE
16V0603
16V0603
10%
10%
X7R
X7R
COMMON
COMMON
16V0603
16V0603
10%
10%
X7R
X7R
COMMON
COMMON
1G1D1S
1G1D1S
GND
ASSEMBLY
PAGE DETAIL
12V_F
C504
C504
C510
C510
1UF
1UF
10UF
10UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
1206
1206
COMMON
COMMON
COMMON
GND
C507
C507
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C508
C508
680PF
680PF
50V
50V
5%
5%
C0G
C0G
0603
0603
COMMON
COMMON
C509
C509
680PF
680PF
50V
50V
5%
5%
C0G
C0G
0603
0603
COMMON
COMMON
COMMON
C506
C506
10UF
10UF
16V
16V
10%
10%
X5R
X5R
1206
1206
COMMON
COMMON
GND
1G1D1S
1G1D1S
1G1D1S
1G1D1S
C505
C505
1000PF
1000PF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
1G1D1S
1G1D1S
1G1D1S
1G1D1S
C516
C516
1000PF
1000PF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
G
1
G
1
G
1
G
1
D
Q12
Q12
DFET_SMD_DPAK_VIAS
DFET_SMD_DPAK_VIAS
COMMON
COMMON
S
D
Q10
Q10
DFET_SMD_DPAK_VIAS
DFET_SMD_DPAK_VIAS
COMMON
COMMON
S
12V_F
D
Q13
Q13
DFET_SMD_DPAK_VIAS
DFET_SMD_DPAK_VIAS
COMMON
COMMON
S
D
Q9
Q9
DFET_SMD_DPAK_VIAS
DFET_SMD_DPAK_VIAS
COMMON
COMMON
S
2
3
25V
25V
11.3A@25C
11.3A@25C
9.3M@10V
9.3M@10V
98A
98A
1.95W@25C
1.95W@25C
+/-20V
+/-20V
2
3
25V
25V
14A@25C
14A@25C
0.0052R@10V
0.0052R@10V
146A
146A
2W@25C
2W@25C
+/-20V
+/-20V
GND
2
3
25V
25V
11.3A@25C
11.3A@25C
9.3M@10V
9.3M@10V
98A
98A
1.95W@25C
1.95W@25C
+/-20V
+/-20V
2
3
25V
25V
14A@25C
14A@25C
0.0052R@10V
0.0052R@10V
146A
146A
2W@25C
2W@25C
+/-20V
+/-20V
GND
PS_NVVDD_FB
R524
R524
Rbot1
8.25K
8.25K
1%
1%
0402
0402
COMMON
COMMON
NVVDD_RBOT1
3
D
Q505
Q505
SOT23
SOT23
G
1
COMMON
COMMON
S
2
60V
60V
0.115A
0.115A
7.5R
7.5R
C522
C522
0.8A
0.8A
1000PF
1000PF
0.2W
0.2W
20V
20V
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PS IV: NVVDDV
R510
R510
Rbot
2.32K
2.32K
1%
1%
0402
0402
COMMON
COMMON
GND
GND
C71
C71
270UF
270UF
COMMON
COMMON
20%
20%
16V
16V
FPCAP
FPCAP
5A@105C
5A@105C
0.008R
0.008R
CAP_TH_D080P035
CAP_TH_D080P035
PS_NVVDD_RC1
R505
R505
1
1
5%
5%
1206
1206
COMMON
COMMON
GND
C70
C70
270UF
270UF
COMMON
COMMON
20%
20%
16V
16V
FPCAP
FPCAP
5A@105C
5A@105C
0.008R
0.008R
CAP_TH_D080P035
CAP_TH_D080P035
C521
C521
2200PF
2200PF
50V
50V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
PS_NVVDD_RC2
R506
R506
1
1
5%
5%
1206
1206
COMMON
COMMON
R513
C524
0402
0402
C520
C520
2200PF
2200PF
50V
50V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
0402 COMMON
0402 COMMON
1%
1%
.01UFC524
.01UF
16V
16V
10%
10%
X7R
X7R
COMMON
COMMON
1.54KR513
1.54K
Rtop
PS_NVVDD_RC
0.000842R
0.000842R
50A
50A
35A
35A
PS_NVVDD_VSEN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0.000842R
0.000842R
50A
50A
35A
35A
ALTERNATES
0.0009R
0.0009R
50A
50A
30A
30A
L8
L8
PS_NVVDD_VCC9
PS_NVVDD_BOOT1
PS_NVVDD_SUS
PS_NVVDD_DRVH1
PS_NVVDD_DRVH1_R
PS_NVVDD_PH1
PS_NVVDD_DRVL1
PS_NVVDD_CP
PS_NVVDD_RC_CP
PS_NVVDD_FB
PS1_NVVDD_FS
PS1_NVVDD_SS
ALTERNATES
L9
L9
0.0009R
0.0009R
50A
50A
30A
30A
L10 0.47UH
L10 0.47UH
L7 0.47UH
L7 0.47UH
COMMONIND_NONRKO_TH_115X115
COMMONIND_NONRKO_TH_115X115
0.47UH
0.47UH
IND_NONRKO_TH_115X115COMMON
IND_NONRKO_TH_115X115COMMON
R521 10.2
R521 10.2
0402
0402
1%
1%
0.47UH
0.47UH
COMMON
IND_NONRKO_TH_115X115_B
COMMON
IND_NONRKO_TH_115X115_B
COMMON
COMMON
IND_NONRKO_TH_115X115
IND_NONRKO_TH_115X115
COMMON
COMMON
16MIL
16MIL
5MIL
16MIL
16MIL
16MIL 25A
16MIL
5MIL
5MIL
5MIL
5MIL
5MIL
NVVDD Power Supply
R512
R512
100
100
5%
5%
0402
0402
COMMON
COMMON
R509
0R509
0
04025%COMMON
04025%COMMON
NVVDD 1.0V (DEFAULT)
NVVDD = 0.6 * (1 + Rtop/Rbot)
1.0V = 0.6 * (1 + 1.54K/2.32K)
NVVDD = 1.0V @ 35A
C58
C58
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C57
C57
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C56
C56
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
Connect to GPU pin 11
NVVDD_SENSE_GPU
PS_NVVDD_PVCC9
IN
PS_NVVDD_VCC
IN
PS_NVVDD_RC1
IN
PS_NVVDD_BOOT2
IN
PS_NVVDD_DRVH2
IN
PS_NVVDD_DRVH2_R
IN
PS_NVVDD_PH2
IN
PS_NVVDD_DRVL2
IN
PS_NVVDD_RC2
IN
PS_NVVDD_VSEN
IN
PS_NVVDD_RC
IN
C62
C62
560UF
560UF
COMMON
COMMON
20%
20%
2.5V
2.5V
XCON
XCON
4.18A@105C
4.18A@105C
0.007R
0.007R
CAP_TH_D050P020
CAP_TH_D050P020
C65
C65
820UF
820UF
COMMON
COMMON
20%
20%
2.5V
2.5V
NPCAP
NPCAP
6.1A@105C
6.1A@105C
0.007R
0.007R
CAP_TH_D080P035
CAP_TH_D080P035
C63
C63
820UF
820UF
COMMON
COMMON
20%
20%
2.5V
2.5V
NPCAP
NPCAP
6.1A@105C
6.1A@105C
0.007R
0.007R
CAP_TH_D080P035
CAP_TH_D080P035
2,2
IN
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
5MIL
5MIL
C61
C61
820UF
820UF
COMMON
COMMON
20%
20%
2.5V
2.5V
NPCAP
NPCAP
6.1A@105C
6.1A@105C
0.007R
0.007R
CAP_TH_D080P035
CAP_TH_D080P035
GND
C66
C66
560UF
560UF
COMMON
COMMON
20%
20%
2.5V
2.5V
XCON
XCON
4.18A@105C
4.18A@105C
0.007R
0.007R
CAP_TH_D050P020
CAP_TH_D050P020
C64
C64
560UF
560UF
COMMON
COMMON
20%
20%
2.5V
2.5V
XCON
XCON
4.18A@105C
4.18A@105C
0.007R
0.007R
CAP_TH_D050P020
CAP_TH_D050P020
GND
NVVDD
0.1A12V <<OCC_ONLY>>16MIL
25A16MIL
1
2
GND
3
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
www.vinafix.vn
Page 30
A B C D E F G H
Page30: BLANK
1
2
1
2
BLANK
3
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
BLANK
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 31
A B C D E F G H
Page31: Thermal Diode and Fan Control
1
3V3 3V3
D8
D8
3
25V
25V
200MA
200MA
SOT23
SOT23
COMMON
COMMON
1
21
21 GPIO4_FAN_TACH
GPIO9_FAN_PWM
IN
OUT
2
2
3
R15
05%R15
0
0402 COMMON
0402 COMMON
5%
1B1C1E
1B1C1E
B
1
C11
C11
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
3V3
D1
D1
25V
25V
200MA
200MA
SOT23
SOT23
COMMON
COMMON
C822
C822
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
GPIO9_FAN_ON
FAN
J6
J6
1
2
MALE
MALE
2.0MM
2.0MM
3
N/A
N/A
4
CON_WAFER232_004_TH_ST_P020
CON_WAFER232_004_TH_ST_P020
COMMON
COMMON
J5
J5
1
2
MALE
MALE
2.5MM
2.5MM
0
0
CON_HDR_001X002_TH
CON_HDR_001X002_TH
COMMON
COMMON
R8
R8
0
0
5%
5%
0402
0402
COMMON
COMMON
GND
R18
R18
R16
R16
10K
10K
10K
5%
5%
0402
0402
COMMON
COMMON
10K
5%
5%
0402
0402
COMMON
COMMON
12V
GND
3
12V
R5
R5
10K
10K
5%
5%
0402
0402
COMMON
COMMON
GPIO9_FAN_PWM_R
3
C
Q2
Q2
SOT23
SOT23
COMMON
COMMON
E
2
1
2
1G1D1S
1G1D1S
3
D
Q1
Q1
SOT23
SOT23
G
1
COMMON
COMMON
S
2
50V
50V
0.2A@25C
0.2A@25C
3.5R
3.5R
0.8A
0.8A
0.225W@25C
0.225W@25C
+/-20V
+/-20V
GND
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
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ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Fan Connector
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
4
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 32
A B C D E F G H
Page32: Thermal, Mechanical, and Bracket
1
2
3
Thermal Bracket
MEC10
MEC10
MEC_THM_HOLE_141C_B355C98P
MEC_THM_HOLE_141C_B355C98P
COMMON
COMMON
1
MEC12
MEC12
MEC_THM_HOLE_141C_B355C98P
MEC_THM_HOLE_141C_B355C98P
COMMON
COMMON
1
GND
GND
MEC11
MEC11
MEC_THM_HOLE_141C_B355C98P
MEC_THM_HOLE_141C_B355C98P
COMMON
COMMON
1
MEC9
MEC9
MEC_THM_HOLE_141C_B355C98P
MEC_THM_HOLE_141C_B355C98P
COMMON
COMMON
1
MEC8
MEC8
MEC_THM_HOLE_141C_B355C125P
MEC_THM_HOLE_141C_B355C125P
COMMON
COMMON
1
MEC13
MEC13
MEC_THM_HOLE_141C_B355C125P
MEC_THM_HOLE_141C_B355C125P
X
X
COMMON
COMMON
1
GND
4
Mechanical
BOARD STIFFENER
BOARD STIFFENER
1
GND
SPECIAL MECHANIC
SPECIAL MECHANIC
No connected mounting pins
No connected mounting pins
FM1
FM1
OPT
OPT
F_PAD_X
F_PAD_X
<New PN>
<New PN>
X
X
FM5
FM5
OPT
OPT
F_PAD_X
F_PAD_X
<New PN>
<New PN>
X
X
2 connected mounting pins
2 connected mounting pins
2
FM2
FM2
OPT
OPT
F_PAD_X
F_PAD_X
<New PN>
<New PN>
X
X
FM6
FM6
OPT
OPT
F_PAD_X
F_PAD_X
<New PN>
<New PN>
X
X
FM3
FM3
OPT
OPT
F_PAD_X
F_PAD_X
<New PN>
<New PN>
X
X
FM7
FM7
OPT
OPT
F_PAD_X
F_PAD_X
<New PN>
<New PN>
X
X
MEC6
MEC6
EDGE_STIFF_PEX_I07800
EDGE_STIFF_PEX_I07800
COMMON
COMMON
MEC7
MEC7
MECH_PEX_BREAKOFF_RETENTION
MECH_PEX_BREAKOFF_RETENTION
COMMON
COMMON
FM4
FM4
OPT
OPT
F_PAD_X
F_PAD_X
<New PN>
<New PN>
X
X
FM8
FM8
OPT
OPT
F_PAD_X
F_PAD_X
<New PN>
<New PN>
X
X
PCB
PCB
PCB
PCB
V187-10
V187-10
P80-0V18710-E48
P80-0V18710-E48
FM9
FM9
OPT
OPT
F_PAD_X
F_PAD_X
<New PN>
<New PN>
X
X
BKT1
BKT1
BRKT_ATX_1TAB_1_DVI
BRKT_ATX_1TAB_1_DVI
COMMON
COMMON
1
MECH. MOUNTING TOP
MECH. MOUNTING TOP
GND
J14
J14
X_PIN1*2
X_PIN1*2
GND GND
GND
4.63 mil / 50 Ohm5.38 mil / 50 Ohm
X_PIN1*2
X_PIN1*2
MEC5
MEC5
HDMI_SCREW_PH1
HDMI_SCREW_PH1
COMMON
COMMON
MEC100
MEC100
HDMI_SCREW_PH1
HDMI_SCREW_PH1
COMMON
COMMON
J12
J12
X_PIN1*2
X_PIN1*2
6.1mil /75 Ohm
REF X
MEC1
MEC1
MEC_SCREW_HEX_JACK
MEC_SCREW_HEX_JACK
COMMON
COMMON
MEC2
MEC2
MEC_SCREW_HEX_JACK
MEC_SCREW_HEX_JACK
COMMON
COMMON
MEC3
MEC3
MEC_SCREW_HEX_JACK
MEC_SCREW_HEX_JACK
COMMON
COMMON
MEC4
MEC4
MEC_SCREW_HEX_JACK
MEC_SCREW_HEX_JACK
COMMON
COMMON
J15
J15
J11
J11
341
2
impedence
impedence
GNDGND
4.5 mil / 5.84 mil
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
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ASSEMBLY
PAGE DETAIL
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Thermal, Mechanical, and Bracket
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
NAME
5
PAGEID
DATE
30-DEC-2008
HFDBA
Page 33
A B C D E F G H
Title: Basenet Report
Design: p562_a00
Date: Dec 24 11:33:24 2008
Base nets and synonyms for
p562_a00_lib.P562_A00(@p562_a00_lib.p562
_a00(sch_1))
Base Signal Location([Zone][dir])
1
3V3_TMDS_IOVDD_EN 25.4B
12V 26.1G
DACA_BLUE 14.3C 14.5A<> 14.5D
DACA_BLUE_C 14.3F> 14.5A<> 16.3G<
DACA_GREEN 14.3C 14.4D 14.5A<>
DACA_GREEN_C 14.3F> 14.5A<> 16.3G<
DACA_HSYNC 14.3C 14.5A<>
DACA_HS_BUF 14.3D 14.5A<>
DACA_HS_BUF_R 14.3E 14.5A<>
DACA_HS_C 14.2G> 14.2G> 14.5A<>
16.3G<
DACA_RED 14.3C 14.3D 14.5A<>
DACA_RED_C 14.3F> 14.5A<> 16.3G<
DACA_RSET 14.3B 14.5A<
DACA_VDD 14.2B> 14.4A< 15.2A<
DACA_VREF 14.3B 14.5A<
DACA_VSYNC 14.3C 14.5A<>
DACA_VS_BUF 14.2D 14.5A<>
DACA_VS_BUF_R 14.2E 14.5A<>
DACA_VS_C 14.2G> 14.2G> 14.5A<>
2
16.3G<
DACC_BLUE 15.3C 15.5A<> 15.5D
DACC_BLUE_C 15.3F> 15.5A<> 17.3G<
DACC_GREEN 15.3C 15.4D 15.5A<>
DACC_GREEN_C 15.3F> 15.5A<> 17.3G<
DACC_HSYNC 15.3C 15.5A<>
DACC_HS_BUF 15.2D 15.5A<>
DACC_HS_BUF_R 15.2E 15.5A<>
DACC_HS_C 15.2G> 15.2G> 15.5A<>
17.3G<
DACC_RED 15.3C 15.3D 15.5A<>
DACC_RED_C 15.3F> 15.5A<> 17.3G<
DACC_RSET 15.3B 15.5A<
DACC_VREF 15.2B 15.4A<
DACC_VSYNC 15.3C 15.5A<>
DACC_VS_BUF 15.2D 15.5A<>
DACC_VS_BUF_R 15.2E 15.5A<>
DACC_VS_C 15.2G> 15.2G> 15.5A<>
17.3G<
FBA_CLK0 3.4D> 5.2A< 13.1B>
FBA_CLK0* 3.4D> 5.2A< 13.1B>
FBA_CLK0_TERM 5.1A
3
FBA_CLK1 3.4D> 5.2D< 13.2B>
FBA_CLK1* 3.4D> 5.2D< 13.2B>
FBA_CLK1_TERM 5.1D
FBA_CMD<0> 3.2C 5.1B 5.1G
FBA_CMD<27..0> 3.2D> 5.1B< 13.2B>
FBA_CMD<1> 3.2C 5.1B 5.1E
FBA_CMD<2> 3.2C 5.1B 5.1G
FBA_CMD<3> 3.2C 5.2B 5.2E
FBA_CMD<4> 3.2C 5.1E 5.1G
FBA_CMD<5> 3.2C 5.1E 5.1G
FBA_CMD<6> 3.3C 5.1E 5.1G
FBA_CMD<8> 3.3C 5.1B 5.1E
FBA_CMD<9> 3.3C 5.1B 5.1E
FBA_CMD<10> 3.3C 5.1B 5.1E
FBA_CMD<11> 3.3C 5.1B 5.1E
FBA_CMD<12> 3.3C 5.2B 5.2E
FBA_CMD<13> 3.3C 5.1E 5.1G
FBA_CMD<14> 3.3C 5.2B 5.2E
FBA_CMD<15> 3.3C 5.2B 5.2E
FBA_CMD<16> 3.3C 5.1B 5.1E
FBA_CMD<17> 3.3C 5.1B 5.1E
FBA_CMD<18> 3.3C 5.2B 5.2E
4
FBA_CMD<19> 3.3C 5.1B 5.1E
FBA_CMD<20> 3.3C 5.1B 5.1E
FBA_CMD<21> 3.3C 5.1B 5.1E
FBA_CMD<22> 3.3C 5.1B 5.1G
FBA_CMD<23> 3.3C 5.1B 5.1E
FBA_CMD<24> 3.3C 5.1B 5.1G
FBA_CMD<25> 3.3C 5.1B 5.1E
FBA_CMD<27> 3.3C 5.2B 5.2E
FBA_CMD_SENA0 5.2B
FBA_CMD_SENA1 5.2E
FBA_D<0> 3.1B 5.4C
FBA_D<63..0> 3.1A<> 5.4A<> 13.2B<>
FBA_D<1> 3.1B 5.4C
FBA_D<2> 3.1B 5.4C
FBA_D<3> 3.1B 5.4C
FBA_D<4> 3.1B 5.4C
FBA_D<5> 3.1B 5.4C
FBA_D<6> 3.1B 5.4C
FBA_D<7> 3.1B 5.4C
FBA_D<8> 3.1B 5.4C
FBA_D<9> 3.2B 5.4C
FBA_D<10> 3.2B 5.4C
5
FBA_D<11> 3.2B 5.4C
FBA_D<12> 3.2B 5.4C
FBA_D<13> 3.2B 5.4C
FBA_D<14> 3.2B 5.4C
FBA_D<15> 3.2B 5.4C
FBA_D<16> 3.2B 5.4D
FBA_D<17> 3.2B 5.4D
FBA_D<18> 3.2B 5.4D
FBA_D<19> 3.2B 5.4D
FBA_D<20> 3.2B 5.4D
FBA_D<21> 3.2B 5.4D
FBA_D<22> 3.2B 5.4D
FBA_D<23> 3.2B 5.4D
FBA_D<24> 3.2B 5.4E
FBA_D<25> 3.2B 5.4E
FBA_D<26> 3.2B 5.4E
FBA_D<27> 3.2B 5.4E
FBA_D<28> 3.2B 5.4E
FBA_D<29> 3.2B 5.4E
FBA_D<30> 3.2B 5.4E
FBA_D<31> 3.2B 5.4E
FBA_D<32> 3.2B 5.5C
FBA_D<33> 3.2B 5.5C
FBA_D<34> 3.2B 5.5C
FBA_D<35> 3.2B 5.5C
FBA_D<36> 3.2B 5.5C
FBA_D<37> 3.2B 5.5C
FBA_D<38> 3.2B 5.5C
FBA_D<39> 3.3B 5.5C
FBA_D<40> 3.3B 5.5C
FBA_D<41> 3.3B 5.5C
FBA_D<42> 3.3B 5.5C
FBA_D<43> 3.3B 5.5C
FBA_D<44> 3.3B 5.5C
FBA_D<45> 3.3B 5.5C
FBA_D<46> 3.3B 5.5C
FBA_D<47> 3.3B 5.5C
FBA_D<48> 3.3B 5.5D
FBA_D<49> 3.3B 5.5D
FBA_D<50> 3.3B 5.5D
FBA_D<51> 3.3B 5.5D
FBA_D<52> 3.3B 5.5D
FBA_D<53> 3.3B 5.5D
FBA_D<54> 3.3B 5.5D
FBA_D<55> 3.3B 5.5D
FBA_D<56> 3.3B 5.5E
FBA_D<57> 3.3B 5.5E
FBA_D<58> 3.3B 5.5E
FBA_D<59> 3.3B 5.5E
FBA_D<60> 3.3B 5.5E
FBA_D<61> 3.3B 5.5E
FBA_D<62> 3.3B 5.5E
FBA_D<63> 3.3B 5.5E
FBA_DEBUG 3.4C
FBA_DQM<0> 3.3B 5.4B 5.4C
FBA_DQM<7..0> 3.3A> 5.4A<> 13.2B>
FBA_DQM<1> 3.3B 5.4B 5.4C
FBA_DQM<2> 3.3B 5.4B 5.4D
FBA_DQM<3> 3.4B 5.4B 5.4E
FBA_DQM<4> 3.4B 5.4B 5.5C
FBA_DQM<5> 3.4B 5.4B 5.5C
FBA_DQM<6> 3.4B 5.4B 5.5D
FBA_DQM<7> 3.4B 5.4B 5.5E
FBA_DQS_RN<0> 3.4B 5.4B 5.4C
FBA_DQS_RN<7..0> 3.4A< 5.4A<> 13.2B<
FBA_DQS_RN<1> 3.4B 5.4B 5.4C
FBA_DQS_RN<2> 3.4B 5.4B 5.4D
FBA_DQS_RN<3> 3.4B 5.4B 5.4E
FBA_DQS_RN<4> 3.4B 5.4B 5.5C
FBA_DQS_RN<5> 3.4B 5.5B 5.5C
FBA_DQS_RN<6> 3.4B 5.5B 5.5D
FBA_DQS_RN<7> 3.4B 5.5B 5.5E
FBA_DQS_WP<0> 3.4B 5.4C 5.5B
FBA_DQS_WP<7..0> 3.4A> 5.5A<> 13.2B>
FBA_DQS_WP<1> 3.4B 5.4C 5.5B
FBA_DQS_WP<2> 3.4B 5.4D 5.5B
FBA_DQS_WP<3> 3.4B 5.4E 5.5B
FBA_DQS_WP<4> 3.4B 5.5B 5.5C
FBA_DQS_WP<5> 3.4B 5.5B 5.5C
FBA_DQS_WP<6> 3.4B 5.5B 5.5D
FBA_DQS_WP<7> 3.4B 5.5B 5.5E
FBA_VREF0 5.3D> 13.3B<>
FBA_VREF1 5.3G> 13.4B<>
FBA_VREF2 5.3E> 13.4B<>
FBA_VREF3 5.3H> 13.4B<>
FBA_ZQ0 5.2B< 13.4B<>
FBA_ZQ1 5.2E< 13.4B<>
FBB_CLK0 3.4H> 7.2A< 13.2B>
FBB_CLK0* 3.4H> 7.2A< 13.2B>
FBB_CLK0_TERM 7.1A
FBB_CLK1 3.4H> 7.2D< 13.2B>
FBB_CLK1* 3.4H> 7.2D< 13.2B>
FBB_CLK1_TERM 7.1D
FBB_CMD<0> 3.2G 7.1B 7.2G
FBB_CMD<27..0> 3.2H> 7.1B< 13.3B>
FBB_CMD<1> 3.2G 7.1B 7.1E
FBB_CMD<2> 3.2G 7.1B 7.2G
FBB_CMD<3> 3.2G 7.2B 7.2E
FBB_CMD<4> 3.2G 7.1E 7.1G
FBB_CMD<5> 3.2G 7.1E 7.1G
FBB_CMD<6> 3.3G 7.1E 7.1G
FBB_CMD<8> 3.3G 7.1B 7.1E
FBB_CMD<9> 3.3G 7.1B 7.1E
FBB_CMD<10> 3.3G 7.1B 7.1E
FBB_CMD<11> 3.3G 7.1B 7.1E
FBB_CMD<12> 3.3G 7.2B 7.2E
FBB_CMD<13> 3.3G 7.1E 7.1G
FBB_CMD<14> 3.3G 7.2B 7.2E
FBB_CMD<15> 3.3G 7.2B 7.2E
FBB_CMD<16> 3.3G 7.1B 7.1E
FBB_CMD<17> 3.3G 7.1B 7.1E
FBB_CMD<18> 3.3G 7.2B 7.2E
FBB_CMD<19> 3.3G 7.1B 7.1E
FBB_CMD<20> 3.3G 7.1B 7.1E
FBB_CMD<21> 3.3G 7.1B 7.1E
FBB_CMD<22> 3.3G 7.1B 7.2G
FBB_CMD<23> 3.3G 7.1B 7.1E
FBB_CMD<24> 3.3G 7.1B 7.2G
FBB_CMD<25> 3.3G 7.1B 7.1E
FBB_CMD<27> 3.3G 7.2B 7.2E
FBB_CMD_SENB0 7.2B
FBB_CMD_SENB1 7.2E
FBB_D<0> 3.1F 7.4C
FBB_D<63..0> 3.1E<> 7.4A<> 13.3B<>
FBB_D<1> 3.1F 7.4C
FBB_D<2> 3.1F 7.4C
FBB_D<3> 3.1F 7.4C
FBB_D<4> 3.1F 7.4C
FBB_D<5> 3.1F 7.4C
FBB_D<6> 3.1F 7.4C
FBB_D<7> 3.1F 7.4C
FBB_D<8> 3.1F 7.4C
FBB_D<9> 3.2F 7.4C
FBB_D<10> 3.2F 7.4C
FBB_D<11> 3.2F 7.4C
FBB_D<12> 3.2F 7.4C
FBB_D<13> 3.2F 7.4C
FBB_D<14> 3.2F 7.4C
FBB_D<15> 3.2F 7.4C
FBB_D<16> 3.2F 7.4D
FBB_D<17> 3.2F 7.4D
FBB_D<18> 3.2F 7.4D
FBB_D<19> 3.2F 7.4D
FBB_D<20> 3.2F 7.4D
FBB_D<21> 3.2F 7.4D
FBB_D<22> 3.2F 7.4D
FBB_D<23> 3.2F 7.4D
FBB_D<24> 3.2F 7.4E
FBB_D<25> 3.2F 7.4E
FBB_D<26> 3.2F 7.4E
FBB_D<27> 3.2F 7.4E
FBB_D<28> 3.2F 7.4E
FBB_D<29> 3.2F 7.4E
FBB_D<30> 3.2F 7.4E
FBB_D<31> 3.2F 7.4E
FBB_D<32> 3.2F 7.5C
FBB_D<33> 3.2F 7.5C
FBB_D<34> 3.2F 7.5C
FBB_D<35> 3.2F 7.5C
FBB_D<36> 3.2F 7.5C
FBB_D<37> 3.2F 7.5C
FBB_D<38> 3.2F 7.5C
FBB_D<39> 3.3F 7.5C
FBB_D<40> 3.3F 7.5C
FBB_D<41> 3.3F 7.5C
FBB_D<42> 3.3F 7.5C
FBB_D<43> 3.3F 7.5C
FBB_D<44> 3.3F 7.5C
FBB_D<45> 3.3F 7.5C
FBB_D<46> 3.3F 7.5C
FBB_D<47> 3.3F 7.5C
FBB_D<48> 3.3F 7.5D
FBB_D<49> 3.3F 7.5D
FBB_D<50> 3.3F 7.5D
FBB_D<51> 3.3F 7.5D
FBB_D<52> 3.3F 7.5D
FBB_D<53> 3.3F 7.5D
FBB_D<54> 3.3F 7.5D
FBB_D<55> 3.3F 7.5D
FBB_D<56> 3.3F 7.5E
FBB_D<57> 3.3F 7.5E
FBB_D<58> 3.3F 7.5E
FBB_D<59> 3.3F 7.5E
FBB_D<60> 3.3F 7.5E
FBB_D<61> 3.3F 7.5E
FBB_D<62> 3.3F 7.5E
FBB_D<63> 3.3F 7.5E
FBB_DEBUG 3.4G
FBB_DQM<0> 3.3F 7.4B 7.4C
FBB_DQM<7..0> 3.3E> 7.4A<> 13.3B>
FBB_DQM<1> 3.3F 7.4B 7.4C
FBB_DQM<2> 3.3F 7.4B 7.4D
FBB_DQM<3> 3.4F 7.4B 7.4E
FBB_DQM<4> 3.4F 7.4B 7.5C
FBB_DQM<5> 3.4F 7.4B 7.5C
FBB_DQM<6> 3.4F 7.4B 7.5D
FBB_DQM<7> 3.4F 7.4B 7.5E
FBB_DQS_RN<0> 3.4F 7.4B 7.4C
FBB_DQS_RN<7..0> 3.4E< 7.4A<> 13.3B<
FBB_DQS_RN<1> 3.4F 7.4B 7.4C
FBB_DQS_RN<2> 3.4F 7.4B 7.4D
FBB_DQS_RN<3> 3.4F 7.4B 7.4E
FBB_DQS_RN<4> 3.4F 7.5B 7.5C
FBB_DQS_RN<5> 3.4F 7.5B 7.5C
FBB_DQS_RN<6> 3.4F 7.5B 7.5D
FBB_DQS_RN<7> 3.4F 7.5B 7.5E
FBB_DQS_WP<0> 3.4F 7.4C 7.5B
FBB_DQS_WP<7..0> 3.4E> 7.5A<> 13.3B>
FBB_DQS_WP<1> 3.4F 7.4C 7.5B
FBB_DQS_WP<2> 3.4F 7.4D 7.5B
FBB_DQS_WP<3> 3.4F 7.4E 7.5B
FBB_DQS_WP<4> 3.4F 7.5B 7.5C
FBB_DQS_WP<5> 3.4F 7.5B 7.5C
FBB_DQS_WP<6> 3.4F 7.5B 7.5D
FBB_DQS_WP<7> 3.4F 7.5B 7.5E
FBB_VREF0 7.3D> 13.4B<>
FBB_VREF1 7.3G> 13.4B<>
FBB_VREF2 7.3E> 13.4B<>
FBB_VREF3 7.3H> 13.4B<>
FBB_ZQ0 7.2B< 13.4B<>
FBB_ZQ1 7.2E< 13.4B<>
FBC_CLK0 4.4D> 9.2A< 13.1E>
FBC_CLK0* 4.4D> 9.2A< 13.1E>
FBC_CLK0_TERM 9.1A
FBC_CLK1 4.4D> 9.2D< 13.2E>
FBC_CLK1* 4.4D> 9.2D< 13.2E>
FBC_CLK1_TERM 9.1D
FBC_CMD<0> 4.2C 9.1B 9.2G
FBC_CMD<27..0> 4.2D> 9.1B< 13.2E>
FBC_CMD<1> 4.2C 9.1B 9.1E
FBC_CMD<2> 4.2C 9.1B 9.2G
FBC_CMD<3> 4.2C 9.2B 9.2E
FBC_CMD<4> 4.2C 9.1E 9.1G
FBC_CMD<5> 4.2C 9.1E 9.1G
FBC_CMD<6> 4.3C 9.1E 9.1G
FBC_CMD<8> 4.3C 9.1B 9.1E
FBC_CMD<9> 4.3C 9.1B 9.1E
FBC_CMD<10> 4.3C 9.1B 9.1E
FBC_CMD<11> 4.3C 9.1B 9.1E
FBC_CMD<12> 4.3C 9.2B 9.2E
FBC_CMD<13> 4.3C 9.1E 9.1G
FBC_CMD<14> 4.3C 9.2B 9.2E
FBC_CMD<15> 4.3C 9.2B 9.2E
FBC_CMD<16> 4.3C 9.1B 9.1E
FBC_CMD<17> 4.3C 9.1B 9.1E
FBC_CMD<18> 4.3C 9.2B 9.2E
FBC_CMD<19> 4.3C 9.1B 9.1E
FBC_CMD<20> 4.3C 9.1B 9.1E
FBC_CMD<21> 4.3C 9.1B 9.1E
FBC_CMD<22> 4.3C 9.1B 9.2G
FBC_CMD<23> 4.3C 9.1B 9.1E
FBC_CMD<24> 4.3C 9.1B 9.2G
FBC_CMD<25> 4.3C 9.1B 9.1E
FBC_CMD<27> 4.3C 9.2B 9.2E
FBC_CMD_SENC0 9.2B
FBC_CMD_SENC1 9.2E
FBC_D<0> 4.1B 9.4C
FBC_D<63..0> 4.1A<> 9.4A<> 13.2E<>
FBC_D<1> 4.1B 9.4C
FBC_D<2> 4.1B 9.4C
FBC_D<3> 4.1B 9.4C
FBC_D<4> 4.1B 9.4C
FBC_D<5> 4.1B 9.4C
FBC_D<6> 4.1B 9.4C
FBC_D<7> 4.1B 9.4C
FBC_D<8> 4.1B 9.4C
FBC_D<9> 4.2B 9.4C
FBC_D<10> 4.2B 9.4C
FBC_D<11> 4.2B 9.4C
FBC_D<12> 4.2B 9.4C
FBC_D<13> 4.2B 9.4C
FBC_D<14> 4.2B 9.4C
FBC_D<15> 4.2B 9.4C
FBC_D<16> 4.2B 9.4D
FBC_D<17> 4.2B 9.4D
FBC_D<18> 4.2B 9.4D
FBC_D<19> 4.2B 9.4D
FBC_D<20> 4.2B 9.4D
FBC_D<21> 4.2B 9.4D
FBC_D<22> 4.2B 9.4D
FBC_D<23> 4.2B 9.4D
FBC_D<24> 4.2B 9.4E
FBC_D<25> 4.2B 9.4E
FBC_D<26> 4.2B 9.4E
FBC_D<27> 4.2B 9.4E
FBC_D<28> 4.2B 9.4E
FBC_D<29> 4.2B 9.4E
FBC_D<30> 4.2B 9.4E
FBC_D<31> 4.2B 9.4E
FBC_D<32> 4.2B 9.5C
FBC_D<33> 4.2B 9.5C
FBC_D<34> 4.2B 9.5C
FBC_D<35> 4.2B 9.5C
FBC_D<36> 4.2B 9.5C
FBC_D<37> 4.2B 9.5C
FBC_D<38> 4.2B 9.5C
FBC_D<39> 4.3B 9.5C
FBC_D<40> 4.3B 9.5C
FBC_D<41> 4.3B 9.5C
FBC_D<42> 4.3B 9.5C
FBC_D<43> 4.3B 9.5C
FBC_D<44> 4.3B 9.5C
FBC_D<45> 4.3B 9.5C
FBC_D<46> 4.3B 9.5C
FBC_D<47> 4.3B 9.5C
FBC_D<48> 4.3B 9.5D
FBC_D<49> 4.3B 9.5D
FBC_D<50> 4.3B 9.5D
FBC_D<51> 4.3B 9.5D
FBC_D<52> 4.3B 9.5D
FBC_D<53> 4.3B 9.5D
FBC_D<54> 4.3B 9.5D
FBC_D<55> 4.3B 9.5D
FBC_D<56> 4.3B 9.5E
FBC_D<57> 4.3B 9.5E
FBC_D<58> 4.3B 9.5E
FBC_D<59> 4.3B 9.5E
FBC_D<60> 4.3B 9.5E
FBC_D<61> 4.3B 9.5E
FBC_D<62> 4.3B 9.5E
FBC_D<63> 4.3B 9.5E
FBC_DEBUG 4.4C
FBC_DQM<0> 4.3B 9.4B 9.4C
FBC_DQM<7..0> 4.3A> 9.4A<> 13.2E>
FBC_DQM<1> 4.3B 9.4B 9.4C
FBC_DQM<2> 4.3B 9.4B 9.4D
FBC_DQM<3> 4.4B 9.4B 9.4E
FBC_DQM<4> 4.4B 9.4B 9.5C
FBC_DQM<5> 4.4B 9.4B 9.5C
FBC_DQM<6> 4.4B 9.4B 9.5D
FBC_DQM<7> 4.4B 9.4B 9.5E
FBC_DQS_RN<0> 4.4B 9.4B 9.4C
FBC_DQS_RN<7..0> 4.4A< 9.4A<> 13.2E<
FBC_DQS_RN<1> 4.4B 9.4B 9.4C
FBC_DQS_RN<2> 4.4B 9.4B 9.4D
FBC_DQS_RN<3> 4.4B 9.4B 9.4E
FBC_DQS_RN<4> 4.4B 9.5B 9.5C
FBC_DQS_RN<5> 4.4B 9.5B 9.5C
FBC_DQS_RN<6> 4.4B 9.5B 9.5D
FBC_DQS_RN<7> 4.4B 9.5B 9.5E
FBC_DQS_WP<0> 4.4B 9.4C 9.5B
FBC_DQS_WP<7..0> 4.4A> 9.5A<> 13.2E>
FBC_DQS_WP<1> 4.4B 9.4C 9.5B
FBC_DQS_WP<2> 4.4B 9.4D 9.5B
FBC_DQS_WP<3> 4.4B 9.4E 9.5B
FBC_DQS_WP<4> 4.4B 9.5B 9.5C
FBC_DQS_WP<5> 4.4B 9.5B 9.5C
FBC_DQS_WP<6> 4.4B 9.5B 9.5D
FBC_DQS_WP<7> 4.4B 9.5B 9.5E
FBC_VREF0 9.3D> 13.3E<>
FBC_VREF1 9.3G> 13.4E<>
FBC_VREF2 9.3E> 13.4E<>
FBC_VREF3 9.3H> 13.4E<>
FBC_ZQ0 9.2B< 13.4E<>
FBC_ZQ1 9.2E< 13.4E<>
FBD_CLK0 4.4H> 11.2A< 13.2E>
FBD_CLK0* 4.4H> 11.2A< 13.2E>
FBD_CLK0_TERM 11.1A
FBD_CLK1 4.4H> 11.2D< 13.2E>
FBD_CLK1* 4.4H> 11.2D< 13.2E>
FBD_CLK1_TERM 11.1D
FBD_CMD<0> 4.2G 11.1B 11.2G
FBD_CMD<27..0> 4.2H> 11.1B< 13.3E>
FBD_CMD<1> 4.2G 11.1C 11.1F
FBD_CMD<2> 4.2G 11.1B 11.2G
FBD_CMD<3> 4.2G 11.2C 11.2F
FBD_CMD<4> 4.2G 11.1E 11.1G
FBD_CMD<5> 4.2G 11.1E 11.1G
FBD_CMD<6> 4.3G 11.1E 11.1G
FBD_CMD<8> 4.3G 11.1C 11.1F
FBD_CMD<9> 4.3G 11.1C 11.1F
FBD_CMD<10> 4.3G 11.1C 11.1F
FBD_CMD<11> 4.3G 11.1C 11.1F
FBD_CMD<12> 4.3G 11.2C 11.2F
FBD_CMD<13> 4.3G 11.1E 11.2G
FBD_CMD<14> 4.3G 11.2C 11.2F
FBD_CMD<15> 4.3G 11.2C 11.2F
FBD_CMD<16> 4.3G 11.1C 11.1F
FBD_CMD<17> 4.3G 11.1C 11.1F
FBD_CMD<18> 4.3G 11.2C 11.2F
FBD_CMD<19> 4.3G 11.1C 11.1F
FBD_CMD<20> 4.3G 11.1C 11.1F
FBD_CMD<21> 4.3G 11.1C 11.1F
FBD_CMD<22> 4.3G 11.1B 11.2G
FBD_CMD<23> 4.3G 11.1C 11.1F
FBD_CMD<24> 4.3G 11.1B 11.2G
FBD_CMD<25> 4.3G 11.1C 11.1F
FBD_CMD<27> 4.3G 11.2C 11.2F
FBD_CMD_SEND0 11.2C
FBD_CMD_SEND1 11.2F
FBD_D<0> 4.1F 11.4C
FBD_D<63..0> 4.1E<> 11.4A<>
13.3E<>
FBD_D<1> 4.1F 11.4C
FBD_D<2> 4.1F 11.4C
FBD_D<3> 4.1F 11.4C
FBD_D<4> 4.1F 11.4C
FBD_D<5> 4.1F 11.4C
FBD_D<6> 4.1F 11.4C
FBD_D<7> 4.1F 11.4C
FBD_D<8> 4.1F 11.4D
FBD_D<9> 4.2F 11.4D
FBD_D<10> 4.2F 11.4D
FBD_D<11> 4.2F 11.4D
FBD_D<12> 4.2F 11.4D
FBD_D<13> 4.2F 11.4D
FBD_D<14> 4.2F 11.4D
FBD_D<15> 4.2F 11.4D
FBD_D<16> 4.2F 11.4D
FBD_D<17> 4.2F 11.4D
FBD_D<18> 4.2F 11.4D
FBD_D<19> 4.2F 11.4D
FBD_D<20> 4.2F 11.4D
FBD_D<21> 4.2F 11.4D
FBD_D<22> 4.2F 11.4D
FBD_D<23> 4.2F 11.4D
FBD_D<24> 4.2F 11.4E
FBD_D<25> 4.2F 11.4E
FBD_D<26> 4.2F 11.4E
FBD_D<27> 4.2F 11.4E
FBD_D<28> 4.2F 11.4E
FBD_D<29> 4.2F 11.4E
FBD_D<30> 4.2F 11.4E
FBD_D<31> 4.2F 11.4E
FBD_D<32> 4.2F 11.5C
FBD_D<33> 4.2F 11.5C
FBD_D<34> 4.2F 11.5C
FBD_D<35> 4.2F 11.5C
FBD_D<36> 4.2F 11.5C
FBD_D<37> 4.2F 11.5C
FBD_D<38> 4.2F 11.5C
FBD_D<39> 4.3F 11.5C
FBD_D<40> 4.3F 11.5D
FBD_D<41> 4.3F 11.5D
FBD_D<42> 4.3F 11.5D
FBD_D<43> 4.3F 11.5D
FBD_D<44> 4.3F 11.5D
FBD_D<45> 4.3F 11.5D
FBD_D<46> 4.3F 11.5D
FBD_D<47> 4.3F 11.5D
FBD_D<48> 4.3F 11.5D
FBD_D<49> 4.3F 11.5D
FBD_D<50> 4.3F 11.5D
FBD_D<51> 4.3F 11.5D
FBD_D<52> 4.3F 11.5D
FBD_D<53> 4.3F 11.5D
FBD_D<54> 4.3F 11.5D
FBD_D<55> 4.3F 11.5D
FBD_D<56> 4.3F 11.5E
FBD_D<57> 4.3F 11.5E
FBD_D<58> 4.3F 11.5E
FBD_D<59> 4.3F 11.5E
FBD_D<60> 4.3F 11.5E
FBD_D<61> 4.3F 11.5E
FBD_D<62> 4.3F 11.5E
FBD_D<63> 4.3F 11.5E
FBD_DEBUG 4.4G
FBD_DQM<0> 4.3F 11.4B 11.4C
FBD_DQM<7..0> 4.3E> 11.4A<> 13.3E>
FBD_DQM<1> 4.3F 11.4B 11.4D
FBD_DQM<2> 4.3F 11.4B 11.4D
FBD_DQM<3> 4.4F 11.4B 11.4E
FBD_DQM<4> 4.4F 11.4B 11.5C
FBD_DQM<5> 4.4F 11.4B 11.5D
FBD_DQM<6> 4.4F 11.4B 11.5D
FBD_DQM<7> 4.4F 11.4B 11.5E
FBD_DQS_RN<0> 4.4F 11.4B 11.4C
FBD_DQS_RN<7..0> 4.4E< 11.4A<> 13.3E<
FBD_DQS_RN<1> 4.4F 11.4B 11.4D
FBD_DQS_RN<2> 4.4F 11.4B 11.4D
FBD_DQS_RN<3> 4.4F 11.4B 11.4E
FBD_DQS_RN<4> 4.4F 11.5B 11.5C
FBD_DQS_RN<5> 4.4F 11.5B 11.5D
FBD_DQS_RN<6> 4.4F 11.5B 11.5D
FBD_DQS_RN<7> 4.4F 11.5B 11.5E
FBD_DQS_WP<0> 4.4F 11.4C 11.5B
FBD_DQS_WP<7..0> 4.4E> 11.5A<> 13.3E>
FBD_DQS_WP<1> 4.4F 11.4D 11.5B
FBD_DQS_WP<2> 4.4F 11.4D 11.5B
FBD_DQS_WP<3> 4.4F 11.4E 11.5B
FBD_DQS_WP<4> 4.4F 11.5B 11.5C
FBD_DQS_WP<5> 4.4F 11.5B 11.5D
FBD_DQS_WP<6> 4.4F 11.5B 11.5D
FBD_DQS_WP<7> 4.4F 11.5B 11.5E
FBD_VREF0 11.3D> 13.4E<>
FBD_VREF1 11.3G> 13.4E<>
FBD_VREF2 11.3E> 13.4E<>
FBD_VREF3 11.3H> 13.4E<>
FBD_ZQ0 11.2B< 13.4E<>
FBD_ZQ1 11.2E< 13.4E<>
FBVDDQ 28.1G
FBVDDQ_SENSE 4.5H> 28.4H<
FBVDDQ_SENSE_R 28.1G< 28.4F
FB_CAL_PD_VDDQ 3.4G
FB_CAL_PU_GND 3.5G
FB_CAL_TERM_GND 3.5G
FB_PLLAVDD0 3.5D> 13.3B<>
FB_PLLAVDD1 4.5D> 13.3E<>
FB_VREF 3.5A> 13.3B<>
GPIO0_DVI_A_HPD 16.4C> 21.3D<
GPIO0_DVI_A_HPD_C 16.3G
GPIO0_DVI_A_HPD_R 16.4E
GPIO1_DVI_C_HPD 17.4D> 21.3D<
GPIO1_DVI_C_HPD_C 17.3G
GPIO1_DVI_C_HPD_R 17.4E
GPIO4_FAN_TACH 21.3D> 31.2C>
GPIO5_VSEL0 21.3D> 29.4C<
GPIO6_NVVDD_PHASE 21.3D> 29.2A<
GPIO6_NVVDD_PHASE_ 29.2A
R
GPIO8_GPU_SLOW* 21.3D> 25.2C<
GPIO9_FAN_ON 31.3E
GPIO9_FAN_PWM 21.3D> 31.2C<
GPIO9_FAN_PWM_R 31.3E
GPIO11_SLI_SYNC1 20.2E<> 21.3D>
GPIO22_SWAPRDY_A 20.2E<> 21.4E>
GPU_PLLVDD 21.1G< 21.4F
GPU_TESTMODE 2.5D 2.5G>
HDA_RST* 21.1A
HDMI_PD 17.1F
HDMI_PD_EN 17.2F
I2CA_SCL 14.3C
I2CA_SCL_C 14.1G> 14.1G> 16.3G<
I2CA_SCL_T 14.1D
I2CA_SDA 14.3C
I2CA_SDA_C 14.1G> 14.1G> 16.3G<
I2CA_SDA_T 14.1D
I2CB_SCL 15.2C
I2CB_SCL_C 15.1G> 15.1G> 17.3G<
I2CB_SCL_T 15.1D
I2CB_SDA 15.2C
I2CB_SDA_C 15.1G> 15.1G> 17.3G<
I2CB_SDA_T 15.1D
I2CC_SCL 21.2C
I2CC_SCL_R 21.3E>
I2CC_SDA 21.3C
I2CC_SDA_R 21.3E>
I2CH_SCL 21.2C 21.2F
I2CH_SDA 21.2C 21.2F
I2CH_SDA_R 21.2F
I2CS_SCL 21.2C
I2CS_SDA 21.2C
IFPABCD_PLLVDD 16.3B< 17.2B>
IFPAB_IOVDD 16.1G<> 16.3B
IFPAB_RSET 16.1G<> 16.2B
IFPAB_TXC 16.2D
IFPAB_TXC* 16.2D
IFPAB_TXD0 16.2D
IFPAB_TXD0* 16.2D
IFPAB_TXD1 16.3D
IFPAB_TXD1* 16.2D
IFPAB_TXD2 16.3D
IFPAB_TXD2* 16.3D
IFPAB_TXD4 16.3D
IFPAB_TXD4* 16.3D
IFPAB_TXD5 16.3D
IFPAB_TXD5* 16.3D
IFPAB_TXD6 16.3D
IFPAB_TXD6* 16.3D
IFPCD_IOVDD 17.1G<> 17.3B
IFPCD_PLLVDD 17.1G<>
IFPCD_RSET 17.1G<> 17.2B
IFPCD_TXC 17.1E 17.2E
IFPCD_TXC* 17.1E 17.2E
IFPCD_TXD0 17.1E 17.2E
IFPCD_TXD0* 17.1E 17.2E
IFPCD_TXD1 17.1E 17.2E
IFPCD_TXD1* 17.1E 17.2E
IFPCD_TXD2 17.1E 17.2E
IFPCD_TXD2* 17.1E 17.2E
IFPCD_TXD4 17.1E 17.2G 17.3E
IFPCD_TXD4* 17.1E 17.2G 17.3E
IFPCD_TXD5 17.1E 17.3E 17.3G
IFPCD_TXD5* 17.1E 17.3E 17.3G
IFPCD_TXD6 17.1E 17.3E 17.3G
IFPCD_TXD6* 17.1E 17.3E 17.3G
IFPC_TXC 17.2C
1
2
3
4
5
ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
PAGE DETAIL
www.vinafix.vn
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
<edit here to insert page detail>
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10562-base-000 A
<ENGINEER>
NAME
PAGEID
DATE
30-DEC-2008
HFDBA
Page 34
A B
C D
E
F
G
H
IFPC_TXC* 17.2C
IFPC_TXD0 17.2C
IFPC_TXD0* 17.2C
IFPC_TXD1 17.2C
IFPC_TXD1* 17.2C
IFPC_TXD2 17.2C
IFPC_TXD2* 17.2C
IFPD_TXD4 17.3C
1
IFPD_TXD4* 17.3C
IFPD_TXD5 17.3C
IFPD_TXD5* 17.3C
IFPD_TXD6 17.3C
IFPD_TXD6* 17.3C
JTAG_TCLK 2.1F> 2.1F> 21.3A<
JTAG_TDI 2.1F> 2.1F> 21.3A<
JTAG_TDO 2.1F< 2.1F< 21.3A>
JTAG_TMS 2.1F> 2.1F> 21.3A<
JTAG_TRST* 2.1F> 2.1F> 21.3A<
MIOA_CAL_PD_VDDQ 20.2C 20.5A<
MIOA_CAL_PU_GND 20.2C 20.5A<
MIOA_CLKIN 20.2E 20.5A<
MIOA_CLKOUT 20.2E 20.5A<
MIOA_D0 20.1E 20.1F
20.1F< 20.5A<
MIOA_D1 20.1E 20.1F
20.1F< 20.5A<
MIOA_D2 20.1E 20.1F
20.1F< 20.5A<
MIOA_D3 20.1E 20.1F
2
20.1F< 20.5A<
MIOA_D4 20.1E 20.1F
20.1F< 20.5A<
MIOA_D5 20.1E 20.1F
20.1F< 20.5A<
MIOA_D6 20.2E 20.2F
20.1F< 20.5A<
MIOA_D7 20.2E 20.2F
20.1F< 20.5A<
MIOA_D8 20.2E 20.2F
20.1F< 20.5A<
MIOA_D9 20.2E 20.2F
20.1F< 20.5A<
MIOA_D10 20.2E 20.2F
20.1F< 20.5A<
MIOA_D11 20.2E 20.2F
20.1F< 20.5A<
MIOA_D12 20.2E 20.2F
20.1F< 20.5A<
MIOA_D13 20.2E 20.2F
20.1F< 20.5A<
MIOA_D14 20.2E 20.2F
3
20.1F< 20.5A<
MIOA_DE 20.2E 20.5A<
MIOA_VREF 20.2C 20.5A<
MIOB_CLKIN 20.4E
MIOB_D15_STRAP0 20.4E> 22.3A<
MIOB_D16_STRAP1 20.4E> 22.4A<
MIOB_D17_STRAP2 20.4E> 22.5A<
NVVDD 29.1A
NVVDD_EN 25.3D> 29.3A<
NVVDD_RBOT1 29.4D
NVVDD_SENSE_GPU 2.4E> 2.5G> 29.4G<
NVVDD_VSEL0 29.4D
PEX_CAL_PD_VDDQ 2.5D
PEX_CAL_PU_GND 2.5D
PEX_PLLVDD 2.4D 2.5G<
PEX_PLL_CLK_OUT 2.4D 2.4G>
PEX_PLL_CLK_OUT* 2.4D 2.4G>
PEX_PRSNT* 2.1A 2.4A 2.4G>
PEX_REFCLK 2.1G> 2.2B
PEX_REFCLK* 2.1G> 2.2B
PEX_RST* 2.2C> 2.4G> 25.3A<
PEX_RST_R* 25.3A
4
PEX_RX0 2.2B 2.2G>
PEX_RX0* 2.2B 2.2G>
PEX_RX1 2.2B 2.2G>
PEX_RX1* 2.2B 2.2G>
PEX_RX2 2.2B 2.2G>
PEX_RX2* 2.2B 2.2G>
PEX_RX3 2.2G> 2.3B
PEX_RX3* 2.2G> 2.3B
PEX_RX4 2.2G> 2.3B
PEX_RX4* 2.2G> 2.3B
PEX_RX5 2.2G> 2.3B
PEX_RX5* 2.2G> 2.3B
PEX_RX6 2.2G> 2.3B
PEX_RX6* 2.2G> 2.3B
PEX_RX7 2.2G> 2.3B
PEX_RX7* 2.3B 2.3G>
PEX_RX8 2.3G> 2.4B
PEX_RX8* 2.3G> 2.4B
PEX_RX9 2.3G> 2.4B
PEX_RX9* 2.3G> 2.4B
PEX_RX10 2.3G> 2.4B
PEX_RX10* 2.3G> 2.4B
5
PEX_RX11 2.3G> 2.4B
PEX_RX11* 2.3G> 2.4B
PEX_RX12 2.3G> 2.4B
PEX_RX12* 2.3G> 2.4B
PEX_RX13 2.3G> 2.5B
PEX_RX13* 2.3G> 2.5B
PEX_RX14 2.3G> 2.5B
PEX_RX14* 2.3G> 2.5B
PEX_RX15 2.3G> 2.5B
PEX_RX15* 2.3G> 2.5B
PEX_SMCLK 2.1C> 21.2E<
PEX_SMDAT 2.1C> 21.2E<
PEX_TCLK 2.1B
PEX_TDI 2.1B
PEX_TDO 2.1B
PEX_TERMP 2.5D
PEX_TMS 2.1B
PEX_TRST* 2.1B
PEX_TX0 2.2C 2.3G>
PEX_TX0* 2.2C 2.3G>
PEX_TX1 2.2C 2.3G>
PEX_TX1* 2.2C 2.3G>
PEX_TX2 2.2C 2.3G>
PEX_TX2* 2.2C 2.3G>
PEX_TX3 2.2C 2.3G>
PEX_TX3* 2.2C 2.3G>
PEX_TX4 2.3C 2.3G>
PEX_TX4* 2.3C 2.3G>
PEX_TX5 2.3C 2.3G>
PEX_TX5* 2.3C 2.3G>
PEX_TX6 2.3C 2.4G>
PEX_TX6* 2.3C 2.4G>
PEX_TX7 2.3C 2.4G>
PEX_TX7* 2.3C 2.4G>
PEX_TX8 2.3C 2.4G>
PEX_TX8* 2.3C 2.4G>
PEX_TX9 2.4C 2.4G>
PEX_TX9* 2.4C 2.4G>
PEX_TX10 2.4C 2.4G>
PEX_TX10* 2.4C 2.4G>
PEX_TX11 2.4C 2.4G>
PEX_TX11* 2.4C 2.4G>
PEX_TX12 2.4C 2.4G>
PEX_TX12* 2.4C 2.4G>
PEX_TX13 2.4C 2.4G>
PEX_TX13* 2.4C 2.4G>
PEX_TX14 2.4G> 2.5C
PEX_TX14* 2.4G> 2.5C
PEX_TX15 2.4G> 2.5C
PEX_TX15* 2.4G> 2.5C
PEX_TXX0 2.1G> 2.2B
PEX_TXX0* 2.1G> 2.2B
PEX_TXX1 2.1G> 2.2B
PEX_TXX1* 2.1G> 2.2B
PEX_TXX2 2.1G> 2.2B
PEX_TXX2* 2.1G> 2.2B
PEX_TXX3 2.1G> 2.2B
PEX_TXX3* 2.1G> 2.2B
PEX_TXX4 2.1G> 2.3B
PEX_TXX4* 2.1G> 2.3B
PEX_TXX5 2.1G> 2.3B
PEX_TXX5* 2.1G> 2.3B
PEX_TXX6 2.1G> 2.3B
PEX_TXX6* 2.1G> 2.3B
PEX_TXX7 2.1G> 2.3B
PEX_TXX7* 2.1G> 2.3B
PEX_TXX8 2.1G> 2.3B
PEX_TXX8* 2.1G> 2.3B
PEX_TXX9 2.2G> 2.4B
PEX_TXX9* 2.2G> 2.4B
PEX_TXX10 2.2G> 2.4B
PEX_TXX10* 2.2G> 2.4B
PEX_TXX11 2.2G> 2.4B
PEX_TXX11* 2.2G> 2.4B
PEX_TXX12 2.2G> 2.4B
PEX_TXX12* 2.2G> 2.4B
PEX_TXX13 2.2G> 2.4B
PEX_TXX13* 2.2G> 2.4B
PEX_TXX14 2.2G> 2.5B
PEX_TXX14* 2.2G> 2.5B
PEX_TXX15 2.2G> 2.5B
PEX_TXX15* 2.2G> 2.5B
PEX_VDD 28.1G
PS1_NVVDD_FS 29.1F< 29.2B
PS1_NVVDD_SS 29.1F< 29.2B
PS1_NVVDD_SUS_R 29.2B
PS_1V1_CP 28.1G< 28.3B
PS_1V1_DR 28.1G< 28.3C
PS_1V1_FB 28.1G< 28.3C
PS_1V8_ADJ 27.4F
PS_2V5_ADJ 27.2D
PS_2V5_VDD 27.2D
PS_5V_ADJ 27.4B
PS_FBVDDQ_FS 28.2G< 28.3C
PS_FB_BOOT 28.1G< 28.3D
PS_FB_COMP 28.1G< 28.3D
PS_FB_EN 28.5B
PS_FB_EN* 28.5C
PS_FB_FB 28.1G< 28.3D
PS_FB_LGATE 28.1G< 28.3D
PS_FB_PHASE 28.1G< 28.3E
PS_FB_PVCC5 28.1G< 28.2D
PS_FB_RBOT 28.1G<
PS_FB_RC 28.1G< 28.4E
PS_FB_RC_CP 28.3D
PS_FB_SNUB 28.1G< 28.3F
PS_FB_UGATE 28.1G< 28.3D
PS_FB_UGATE_R 28.1G< 28.2E
PS_FB_VCC5 28.1G< 28.2C
PS_FB_VCC12 28.2D
PS_NVVDD_BOOT1 29.1F< 29.2C
PS_NVVDD_BOOT2 29.1G< 29.2C
PS_NVVDD_CP 29.1F< 29.2B
PS_NVVDD_DRVH1 29.1F< 29.2C
PS_NVVDD_DRVH1_R 29.1D 29.1F<
PS_NVVDD_DRVH2 29.1G< 29.2C
PS_NVVDD_DRVH2_R 29.1G< 29.2D
PS_NVVDD_DRVL1 29.1F< 29.2C
PS_NVVDD_DRVL2 29.1G< 29.3C
PS_NVVDD_EN 29.5A
PS_NVVDD_EN* 29.4B
PS_NVVDD_EN_AND 29.4B
PS_NVVDD_FB 29.1F< 29.2B 29.4D
PS_NVVDD_OC 29.3C
PS_NVVDD_PH1 29.1F< 29.2C
PS_NVVDD_PH2 29.1G< 29.2C
PS_NVVDD_PVCC9 29.1G< 29.2B
PS_NVVDD_RC 29.1G< 29.4F
PS_NVVDD_RC1 29.1G< 29.2E
PS_NVVDD_RC2 29.1G< 29.3E
PS_NVVDD_RC_CP 29.1F< 29.2A
PS_NVVDD_SUS 29.1F< 29.2B
PS_NVVDD_VCC 29.1G< 29.2C
PS_NVVDD_VCC9 29.1F< 29.2B
PS_NVVDD_VSEN 29.1G< 29.4F
ROM_CS* 21.1C
ROM_SCLK 21.1D> 22.3A<
ROM_SI 21.1D> 22.1A<
ROM_SO 21.1D> 22.2A<
SNN_2V5_NC 27.2D
SNN_2V5_PGOOD 27.2D
SNN_A_MON_ID0 14.3H
SNN_A_MON_ID2 14.4F
SNN_BBIASN 21.1A
SNN_BBIASP 21.1A
SNN_BUFRST* 21.2C
SNN_C_MON_ID0 15.3H
SNN_C_MON_ID2 15.4F
SNN_DACB_COUT 19.3C
SNN_DACB_CSYNC 19.3C
SNN_DACB_PBOUT 19.3C
SNN_DACB_RSET 19.3B
SNN_DACB_VREF 19.3B
SNN_DACB_YOUT 19.3C
SNN_FBA0_NC1 5.2B
SNN_FBA1_NC1 5.2E
SNN_FBA_CMD<7> 3.3C
SNN_FBA_CMD<26> 3.3C
SNN_FBA_CMD<28> 3.3C
SNN_FBA_CMD<29> 3.3C
SNN_FBA_CMD<30> 3.3C
SNN_FBA_DBI<0> 3.4B
SNN_FBA_DBI<1> 3.4B
SNN_FBA_DBI<2> 3.5B
SNN_FBA_DBI<3> 3.5B
SNN_FBA_DBI<4> 3.5B
SNN_FBA_DBI<5> 3.5B
SNN_FBA_DBI<6> 3.5B
SNN_FBA_DBI<7> 3.5B
SNN_FBA_WDS0 3.4C
SNN_FBA_WDS0* 3.4C
SNN_FBA_WDS1 3.4C
SNN_FBA_WDS1* 3.4C
SNN_FBA_WDS2 3.4C
SNN_FBA_WDS2* 3.4C
SNN_FBA_WDS3 3.4C
SNN_FBA_WDS3* 3.4C
SNN_FBB0_NC1 7.2B
SNN_FBB1_NC1 7.2E
SNN_FBB_CMD<7> 3.3G
SNN_FBB_CMD<26> 3.3G
SNN_FBB_CMD<28> 3.3G
SNN_FBB_CMD<29> 3.3G
SNN_FBB_CMD<30> 3.3G
SNN_FBB_DBI<0> 3.4F
SNN_FBB_DBI<1> 3.4F
SNN_FBB_DBI<2> 3.5F
SNN_FBB_DBI<3> 3.5F
SNN_FBB_DBI<4> 3.5F
SNN_FBB_DBI<5> 3.5F
SNN_FBB_DBI<6> 3.5F
SNN_FBB_DBI<7> 3.5F
SNN_FBB_WDS0 3.4G
SNN_FBB_WDS0* 3.4G
SNN_FBB_WDS1 3.4G
SNN_FBB_WDS1* 3.4G
SNN_FBB_WDS2 3.4G
SNN_FBB_WDS2* 3.4G
SNN_FBB_WDS3 3.4G
SNN_FBB_WDS3* 3.4G
SNN_FBC0_NC1 9.2B
SNN_FBC1_NC1 9.2E
SNN_FBC_CMD<7> 4.3C
SNN_FBC_CMD<26> 4.3C
SNN_FBC_CMD<28> 4.3C
SNN_FBC_CMD<29> 4.3C
SNN_FBC_CMD<30> 4.3C
SNN_FBC_DBI<0> 4.4B
SNN_FBC_DBI<1> 4.4B
SNN_FBC_DBI<2> 4.5B
SNN_FBC_DBI<3> 4.5B
SNN_FBC_DBI<4> 4.5B
SNN_FBC_DBI<5> 4.5B
SNN_FBC_DBI<6> 4.5B
SNN_FBC_DBI<7> 4.5B
SNN_FBC_WDS0 4.4C
SNN_FBC_WDS0* 4.4C
SNN_FBC_WDS1 4.4C
SNN_FBC_WDS1* 4.4C
SNN_FBC_WDS2 4.4C
SNN_FBC_WDS2* 4.4C
SNN_FBC_WDS3 4.4C
SNN_FBC_WDS3* 4.4C
SNN_FBD0_NC1 11.2C
SNN_FBD1_NC1 11.2F
SNN_FBD_CMD<7> 4.3G
SNN_FBD_CMD<26> 4.3G
SNN_FBD_CMD<28> 4.3G
SNN_FBD_CMD<29> 4.3G
SNN_FBD_CMD<30> 4.3G
SNN_FBD_DBI<0> 4.4F
SNN_FBD_DBI<1> 4.4F
SNN_FBD_DBI<2> 4.5F
SNN_FBD_DBI<3> 4.5F
SNN_FBD_DBI<4> 4.5F
SNN_FBD_DBI<5> 4.5F
SNN_FBD_DBI<6> 4.5F
SNN_FBD_DBI<7> 4.5F
SNN_FBD_WDS0 4.4G
SNN_FBD_WDS0* 4.4G
SNN_FBD_WDS1 4.4G
SNN_FBD_WDS1* 4.4G
SNN_FBD_WDS2 4.4G
SNN_FBD_WDS2* 4.4G
SNN_FBD_WDS3 4.4G
SNN_FBD_WDS3* 4.4G
SNN_GPIO2 21.3C
SNN_GPIO3 21.3C
SNN_GPIO7 21.3C
SNN_GPIO10 21.3C
SNN_GPIO12 21.3C
SNN_GPIO13 21.3C
SNN_GPIO14 21.3C
SNN_GPIO15 21.3C
SNN_GPIO16 21.3C
SNN_GPIO17 21.3C
SNN_GPIO18 21.3C
SNN_GPIO19 21.3C
SNN_GPIO20 21.3C
SNN_GPIO21 21.3C
SNN_GPIO23_STEREO 21.4C
SNN_HDA_SDI 21.1A
SNN_HDA_SDO 21.2A
SNN_HDA_SYNC 21.2A
SNN_HDSA_BCLK 21.1A
SNN_I2CD_SCL 21.3C
SNN_I2CD_SDA 21.3C
SNN_I2CE_SCL 21.3C
SNN_I2CE_SDA 21.3C
SNN_IFPAB_ATXD3 16.3D
SNN_IFPAB_ATXD3* 16.3D
SNN_IFPAB_BTXC 16.3D
SNN_IFPAB_BTXC* 16.3D
SNN_IFPAB_TXD7 16.3D
SNN_IFPAB_TXD7* 16.3D
SNN_IFPC_AUX 17.2C
SNN_IFPC_AUX* 17.2C
SNN_IFPD_AUX 17.3C
SNN_IFPD_AUX* 17.3C
SNN_IFPD_L3 17.3C
SNN_IFPD_L3* 17.3C
SNN_IFPEF_RSET 18.3B
SNN_IFPE_AUX 18.3D
SNN_IFPE_AUX* 18.3D
SNN_IFPE_L0 18.3D
SNN_IFPE_L0* 18.3D
SNN_IFPE_L1 18.3D
SNN_IFPE_L1* 18.3D
SNN_IFPE_L2 18.3D
SNN_IFPE_L2* 18.3D
SNN_IFPE_TXC 18.3D
SNN_IFPE_TXC* 18.3D
SNN_IFPF_AUX 18.4D
SNN_IFPF_AUX* 18.4D
SNN_IFPF_L0 18.4D
SNN_IFPF_L0* 18.4D
SNN_IFPF_L1 18.4D
SNN_IFPF_L1* 18.4D
SNN_IFPF_L2 18.4D
SNN_IFPF_L2* 18.4D
SNN_IFPF_L3 18.4D
SNN_IFPF_L3* 18.4D
SNN_MIOA_CLKOUT* 20.2E
SNN_MIOA_D12 20.2E
SNN_MIOA_D13 20.2E
SNN_MIOA_D14 20.2E
SNN_MIOB_CAL_PD_VD 20.4C
DQ
SNN_MIOB_CAL_PU_GN 20.4C
D
SNN_MIOB_CLKOUT 20.4E
SNN_MIOB_CLKOUT* 20.4E
SNN_MIOB_CTL3 20.4E
SNN_MIOB_D0 20.3E
SNN_MIOB_D1 20.3E
SNN_MIOB_D2 20.3E
SNN_MIOB_D3 20.3E
SNN_MIOB_D4 20.3E
SNN_MIOB_D5 20.3E
SNN_MIOB_D6 20.3E
SNN_MIOB_D7 20.3E
SNN_MIOB_D8 20.3E
SNN_MIOB_D9 20.3E
SNN_MIOB_D10 20.3E
SNN_MIOB_D11 20.4E
SNN_MIOB_D12 20.4E
SNN_MIOB_D13 20.4E
SNN_MIOB_D14 20.4E
SNN_MIOB_DE 20.4E
SNN_MIOB_HSYNC 20.4E
SNN_MIOB_VREF 20.4C
SNN_MIOB_VSYNC 20.4E
SNN_NC<1> 22.1G
SNN_NC<2> 22.1G
SNN_NC<3> 22.1G
SNN_NC<4> 22.1G
SNN_NC<5> 22.1G
SNN_NC<6> 22.1G
SNN_NC<7> 22.1G
SNN_NC<8> 22.1G
SNN_NC<9> 22.1G
SNN_NC<10> 22.1G
SNN_NC<11> 22.1G
SNN_NC<12> 22.1G
SNN_NC<13> 22.1G
SNN_NC<14> 22.1G
SNN_NC<15> 22.1G
SNN_NC<16> 22.1G
SNN_NC<17> 22.1G
SNN_NC<18> 22.1G
SNN_NC<19> 22.1G
SNN_NC<20> 22.1G
SNN_NC<21> 22.2G
SNN_NC<22> 22.2G
SNN_NC<23> 22.2G
SNN_NC<24> 22.2G
SNN_NC<25> 22.2G
SNN_NC<26> 22.2G
SNN_NC<27> 22.2G
SNN_NC<28> 22.2G
SNN_NC<29> 22.2G
SNN_NC<30> 22.2G
SNN_NC<31> 22.2G
SNN_NC<32> 22.2G
SNN_NC<33> 22.2G
SNN_NC<34> 22.2G
SNN_NC<35> 22.2G
SNN_NC<36> 22.2G
SNN_NC<37> 22.2G
SNN_NC<38> 22.2G
SNN_NC<39> 22.2G
SNN_NC<40> 22.2G
SNN_NC<41> 22.2G
SNN_NC<42> 22.2G
SNN_NC<43> 22.2G
SNN_NC<44> 22.2G
SNN_NC<45> 22.2G
SNN_NC<46> 22.2G
SNN_NC<47> 22.2G
SNN_NC<48> 22.2G
SNN_NC<49> 22.2G
SNN_NC<50> 22.2G
SNN_NC<51> 22.3G
SNN_NC<52> 22.3G
SNN_NC<53> 22.3G
SNN_NC<54> 22.3G
SNN_NC<55> 22.3G
SNN_NC<56> 22.3G
SNN_NC<57> 22.3G
SNN_NC<58> 22.3G
SNN_NC<59> 22.3G
SNN_NC<60> 22.3G
SNN_NC<61> 22.3G
SNN_NC<62> 22.3G
SNN_NC<63> 22.3G
SNN_NC<64> 22.3G
SNN_NC<65> 22.3G
SNN_NC<66> 22.3G
SNN_NC<67> 22.3G
SNN_NC<68> 22.3G
SNN_NC<69> 22.3G
SNN_NC<70> 22.3G
SNN_NC<71> 22.3G
SNN_NC<72> 22.3G
SNN_NC<73> 22.3G
SNN_NC<74> 22.3G
SNN_NC<75> 22.3G
SNN_NVVDD_GND_SENS 2.4D
E_GPU
SNN_NVVDD_NC1 29.3C
SNN_NVVDD_NC2 29.3C
SNN_NVVDD_NC3 29.3C
SNN_NVVDD_VREF 29.2B
SNN_PEX_CLKREQ* 2.2C
SNN_PEX_WAKE* 2.2B
SNN_PE_PRSNT2_A 2.1A
SNN_PE_PRSNT2_B 2.2A
SNN_PE_PRSNT2_C 2.3A
SNN_PE_RSVD1 2.1A
SNN_PE_RSVD2 2.2A
SNN_PE_RSVD3 2.2A
SNN_PE_RSVD4 2.2A
SNN_PE_RSVD5 2.3A
SNN_PE_RSVD6 2.4A
SNN_PE_RSVD7 2.4A
SNN_PGOOD_OUT* 21.2C
SNN_THERMDN 21.3A
SNN_THERMDP 21.3A
SPDIF 21.2D< 25.1G< 25.2H>
SPDIF_GND 25.2E
SPDIF_IN 25.1G< 25.2E
SPDIF_IN_C 25.1G< 25.3F
SPDIF_IN_COMP2_D 25.1G< 25.3G
SPDIF_IN_COMP2_Q 25.1G< 25.3H
SPDIF_IN_R 25.1G< 25.3F
STRAP_CALPD_MIOB 21.2A
STRAP_CALPD_MISC 21.2A
THERM_N_EN1 25.2A
THERM_N_EN1_R 25.2B
THERM_N_EN2 25.2C
THERM_N_EN3 25.2B
THERM_N_EN3_R1 25.2C
THERM_N_EN3_R2 25.3C
XTALIN 21.1G< 21.5F
XTALOUT 21.1G< 21.5G
XTALOUTBUFF 21.1G< 21.4H
XTALSSIN 21.1G< 21.4F
1
2
3
4
5
ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
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P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
<edit here to insert page detail>
E
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
ID
NAME
G
600-10562-base-000 A
<ENGINEER>
PAGE
DATE
30-DEC-2008
HFD
Page 35
A B
C D
E
F
G
H
Title: Netsbypage Report
Design: p562_a00
Date: Dec 24 11:33:24 2008
Page wise report of nets and their base nets
Net Name Location([Zone][dir])
GPU_TESTMODE 2.5D 2.5G>
1
GPU_TESTMODE 2.5D 2.5G>
JTAG_TCLK 2.1F> 2.1F> 21.3A<
JTAG_TCLK 2.1F> 2.1F> 21.3A<
JTAG_TDI 2.1F> 2.1F> 21.3A<
JTAG_TDI 2.1F> 2.1F> 21.3A<
JTAG_TDO 2.1F< 2.1F< 21.3A>
JTAG_TDO 2.1F< 2.1F< 21.3A>
JTAG_TMS 2.1F> 2.1F> 21.3A<
JTAG_TMS 2.1F> 2.1F> 21.3A<
JTAG_TRST* 2.1F> 2.1F> 21.3A<
JTAG_TRST* 2.1F> 2.1F> 21.3A<
NVVDD_SENSE_GPU 2.4E> 2.5G> 29.4G<
NVVDD_SENSE_GPU 2.4E> 2.5G> 29.4G<
PEX_CAL_PD_VDDQ 2.5D
PEX_CAL_PU_GND 2.5D
PEX_PLLVDD 2.4D 2.5G<
PEX_PLLVDD 2.4D 2.5G<
PEX_PLL_CLK_OUT 2.4D 2.4G>
PEX_PLL_CLK_OUT 2.4D 2.4G>
PEX_PLL_CLK_OUT* 2.4D 2.4G>
PEX_PLL_CLK_OUT* 2.4D 2.4G>
2
PEX_PRSNT* 2.1A 2.4A 2.4G>
PEX_PRSNT* 2.1A 2.4A 2.4G>
PEX_PRSNT* 2.1A 2.4A 2.4G>
PEX_REFCLK 2.1G> 2.2B
PEX_REFCLK 2.1G> 2.2B
PEX_REFCLK* 2.1G> 2.2B
PEX_REFCLK* 2.1G> 2.2B
PEX_RST* 2.2C> 2.4G> 25.3A<
PEX_RST* 2.2C> 2.4G> 25.3A<
PEX_RX0 2.2B 2.2G>
PEX_RX0 2.2B 2.2G>
PEX_RX0* 2.2B 2.2G>
PEX_RX0* 2.2B 2.2G>
PEX_RX1 2.2B 2.2G>
PEX_RX1 2.2B 2.2G>
PEX_RX1* 2.2B 2.2G>
PEX_RX1* 2.2B 2.2G>
PEX_RX2 2.2B 2.2G>
PEX_RX2 2.2B 2.2G>
PEX_RX2* 2.2B 2.2G>
PEX_RX2* 2.2B 2.2G>
PEX_RX3 2.2G> 2.3B
3
PEX_RX3 2.2G> 2.3B
PEX_RX3* 2.2G> 2.3B
PEX_RX3* 2.2G> 2.3B
PEX_RX4 2.2G> 2.3B
PEX_RX4 2.2G> 2.3B
PEX_RX4* 2.2G> 2.3B
PEX_RX4* 2.2G> 2.3B
PEX_RX5 2.2G> 2.3B
PEX_RX5 2.2G> 2.3B
PEX_RX5* 2.2G> 2.3B
PEX_RX5* 2.2G> 2.3B
PEX_RX6 2.2G> 2.3B
PEX_RX6 2.2G> 2.3B
PEX_RX6* 2.2G> 2.3B
PEX_RX6* 2.2G> 2.3B
PEX_RX7 2.2G> 2.3B
PEX_RX7 2.2G> 2.3B
PEX_RX7* 2.3B 2.3G>
PEX_RX7* 2.3B 2.3G>
PEX_RX8 2.3G> 2.4B
PEX_RX8 2.3G> 2.4B
PEX_RX8* 2.3G> 2.4B
4
PEX_RX8* 2.3G> 2.4B
PEX_RX9 2.3G> 2.4B
PEX_RX9 2.3G> 2.4B
PEX_RX9* 2.3G> 2.4B
PEX_RX9* 2.3G> 2.4B
PEX_RX10 2.3G> 2.4B
PEX_RX10 2.3G> 2.4B
PEX_RX10* 2.3G> 2.4B
PEX_RX10* 2.3G> 2.4B
PEX_RX11 2.3G> 2.4B
PEX_RX11 2.3G> 2.4B
PEX_RX11* 2.3G> 2.4B
PEX_RX11* 2.3G> 2.4B
PEX_RX12 2.3G> 2.4B
PEX_RX12 2.3G> 2.4B
PEX_RX12* 2.3G> 2.4B
PEX_RX12* 2.3G> 2.4B
PEX_RX13 2.3G> 2.5B
PEX_RX13 2.3G> 2.5B
PEX_RX13* 2.3G> 2.5B
PEX_RX13* 2.3G> 2.5B
PEX_RX14 2.3G> 2.5B
5
PEX_RX14 2.3G> 2.5B
PEX_RX14* 2.3G> 2.5B
PEX_RX14* 2.3G> 2.5B
PEX_RX15 2.3G> 2.5B
PEX_RX15 2.3G> 2.5B
PEX_RX15* 2.3G> 2.5B
PEX_RX15* 2.3G> 2.5B
PEX_SMCLK 2.1C> 21.2E<
PEX_SMDAT 2.1C> 21.2E<
PEX_TCLK 2.1B
PEX_TDI 2.1B
PEX_TDO 2.1B
PEX_TERMP 2.5D
PEX_TMS 2.1B
PEX_TRST* 2.1B
PEX_TX0 2.2C 2.3G>
PEX_TX0 2.2C 2.3G>
PEX_TX0* 2.2C 2.3G>
PEX_TX0* 2.2C 2.3G>
PEX_TX1 2.2C 2.3G>
PEX_TX1 2.2C 2.3G>
PEX_TX1* 2.2C 2.3G>
PEX_TX1* 2.2C 2.3G>
PEX_TX2 2.2C 2.3G>
PEX_TX2 2.2C 2.3G>
PEX_TX2* 2.2C 2.3G>
PEX_TX2* 2.2C 2.3G>
PEX_TX3 2.2C 2.3G>
PEX_TX3 2.2C 2.3G>
PEX_TX3* 2.2C 2.3G>
PEX_TX3* 2.2C 2.3G>
PEX_TX4 2.3C 2.3G>
PEX_TX4 2.3C 2.3G>
PEX_TX4* 2.3C 2.3G>
PEX_TX4* 2.3C 2.3G>
PEX_TX5 2.3C 2.3G>
PEX_TX5 2.3C 2.3G>
PEX_TX5* 2.3C 2.3G>
PEX_TX5* 2.3C 2.3G>
PEX_TX6 2.3C 2.4G>
PEX_TX6 2.3C 2.4G>
PEX_TX6* 2.3C 2.4G>
PEX_TX6* 2.3C 2.4G>
PEX_TX7 2.3C 2.4G>
PEX_TX7 2.3C 2.4G>
PEX_TX7* 2.3C 2.4G>
PEX_TX7* 2.3C 2.4G>
PEX_TX8 2.3C 2.4G>
PEX_TX8 2.3C 2.4G>
PEX_TX8* 2.3C 2.4G>
PEX_TX8* 2.3C 2.4G>
PEX_TX9 2.4C 2.4G>
PEX_TX9 2.4C 2.4G>
PEX_TX9* 2.4C 2.4G>
PEX_TX9* 2.4C 2.4G>
PEX_TX10 2.4C 2.4G>
PEX_TX10 2.4C 2.4G>
PEX_TX10* 2.4C 2.4G>
PEX_TX10* 2.4C 2.4G>
PEX_TX11 2.4C 2.4G>
PEX_TX11 2.4C 2.4G>
PEX_TX11* 2.4C 2.4G>
PEX_TX11* 2.4C 2.4G>
PEX_TX12 2.4C 2.4G>
PEX_TX12 2.4C 2.4G>
PEX_TX12* 2.4C 2.4G>
PEX_TX12* 2.4C 2.4G>
PEX_TX13 2.4C 2.4G>
PEX_TX13 2.4C 2.4G>
PEX_TX13* 2.4C 2.4G>
PEX_TX13* 2.4C 2.4G>
PEX_TX14 2.4G> 2.5C
PEX_TX14 2.4G> 2.5C
PEX_TX14* 2.4G> 2.5C
PEX_TX14* 2.4G> 2.5C
PEX_TX15 2.4G> 2.5C
PEX_TX15 2.4G> 2.5C
PEX_TX15* 2.4G> 2.5C
PEX_TX15* 2.4G> 2.5C
PEX_TXX0 2.1G> 2.2B
PEX_TXX0 2.1G> 2.2B
PEX_TXX0* 2.1G> 2.2B
PEX_TXX0* 2.1G> 2.2B
PEX_TXX1 2.1G> 2.2B
PEX_TXX1 2.1G> 2.2B
PEX_TXX1* 2.1G> 2.2B
PEX_TXX1* 2.1G> 2.2B
PEX_TXX2 2.1G> 2.2B
PEX_TXX2 2.1G> 2.2B
PEX_TXX2* 2.1G> 2.2B
PEX_TXX2* 2.1G> 2.2B
PEX_TXX3 2.1G> 2.2B
PEX_TXX3 2.1G> 2.2B
PEX_TXX3* 2.1G> 2.2B
PEX_TXX3* 2.1G> 2.2B
PEX_TXX4 2.1G> 2.3B
PEX_TXX4 2.1G> 2.3B
PEX_TXX4* 2.1G> 2.3B
PEX_TXX4* 2.1G> 2.3B
PEX_TXX5 2.1G> 2.3B
PEX_TXX5 2.1G> 2.3B
PEX_TXX5* 2.1G> 2.3B
PEX_TXX5* 2.1G> 2.3B
PEX_TXX6 2.1G> 2.3B
PEX_TXX6 2.1G> 2.3B
PEX_TXX6* 2.1G> 2.3B
PEX_TXX6* 2.1G> 2.3B
PEX_TXX7 2.1G> 2.3B
PEX_TXX7 2.1G> 2.3B
PEX_TXX7* 2.1G> 2.3B
PEX_TXX7* 2.1G> 2.3B
PEX_TXX8 2.1G> 2.3B
PEX_TXX8 2.1G> 2.3B
PEX_TXX8* 2.1G> 2.3B
PEX_TXX8* 2.1G> 2.3B
PEX_TXX9 2.2G> 2.4B
PEX_TXX9 2.2G> 2.4B
PEX_TXX9* 2.2G> 2.4B
PEX_TXX9* 2.2G> 2.4B
PEX_TXX10 2.2G> 2.4B
PEX_TXX10 2.2G> 2.4B
PEX_TXX10* 2.2G> 2.4B
PEX_TXX10* 2.2G> 2.4B
PEX_TXX11 2.2G> 2.4B
PEX_TXX11 2.2G> 2.4B
PEX_TXX11* 2.2G> 2.4B
PEX_TXX11* 2.2G> 2.4B
PEX_TXX12 2.2G> 2.4B
PEX_TXX12 2.2G> 2.4B
PEX_TXX12* 2.2G> 2.4B
PEX_TXX12* 2.2G> 2.4B
PEX_TXX13 2.2G> 2.4B
PEX_TXX13 2.2G> 2.4B
PEX_TXX13* 2.2G> 2.4B
PEX_TXX13* 2.2G> 2.4B
PEX_TXX14 2.2G> 2.5B
PEX_TXX14 2.2G> 2.5B
PEX_TXX14* 2.2G> 2.5B
PEX_TXX14* 2.2G> 2.5B
PEX_TXX15 2.2G> 2.5B
PEX_TXX15 2.2G> 2.5B
PEX_TXX15* 2.2G> 2.5B
PEX_TXX15* 2.2G> 2.5B
SNN_NVVDD_GND_SENSE_GP 2.4D
U
SNN_PEX_CLKREQ* 2.2C
SNN_PEX_WAKE* 2.2B
SNN_PE_PRSNT2_A 2.1A
SNN_PE_PRSNT2_B 2.2A
SNN_PE_PRSNT2_C 2.3A
SNN_PE_RSVD1 2.1A
SNN_PE_RSVD2 2.2A
SNN_PE_RSVD3 2.2A
SNN_PE_RSVD4 2.2A
SNN_PE_RSVD5 2.3A
SNN_PE_RSVD6 2.4A
SNN_PE_RSVD7 2.4A
FBA_CLK0 3.4D> 5.2A< 13.1B>
FBA_CLK0* 3.4D> 5.2A< 13.1B>
FBA_CLK1 3.4D> 5.2D< 13.2B>
FBA_CLK1* 3.4D> 5.2D< 13.2B>
FBA_CMD<0> 3.2C 5.1B 5.1G
FBA_CMD<27..0> 3.3C 5.2B 5.2E
FBA_CMD<1> 3.2C 5.1B 5.1E
FBA_CMD<2> 3.2C 5.1B 5.1G
FBA_CMD<3> 3.2C 5.2B 5.2E
FBA_CMD<4> 3.2C 5.1E 5.1G
FBA_CMD<5> 3.2C 5.1E 5.1G
FBA_CMD<6> 3.3C 5.1E 5.1G
FBA_CMD<8> 3.3C 5.1B 5.1E
FBA_CMD<9> 3.3C 5.1B 5.1E
FBA_CMD<10> 3.3C 5.1B 5.1E
FBA_CMD<11> 3.3C 5.1B 5.1E
FBA_CMD<12> 3.3C 5.2B 5.2E
FBA_CMD<13> 3.3C 5.1E 5.1G
FBA_CMD<14> 3.3C 5.2B 5.2E
FBA_CMD<15> 3.3C 5.2B 5.2E
FBA_CMD<16> 3.3C 5.1B 5.1E
FBA_CMD<17> 3.3C 5.1B 5.1E
FBA_CMD<18> 3.3C 5.2B 5.2E
FBA_CMD<19> 3.3C 5.1B 5.1E
FBA_CMD<20> 3.3C 5.1B 5.1E
FBA_CMD<21> 3.3C 5.1B 5.1E
FBA_CMD<22> 3.3C 5.1B 5.1G
FBA_CMD<23> 3.3C 5.1B 5.1E
FBA_CMD<24> 3.3C 5.1B 5.1G
FBA_CMD<25> 3.3C 5.1B 5.1E
FBA_CMD<27> 3.3C 5.2B 5.2E
FBA_D<0> 3.1B 5.4C
FBA_D<63..0> 3.3B 5.5E
FBA_D<1> 3.1B 5.4C
FBA_D<2> 3.1B 5.4C
FBA_D<3> 3.1B 5.4C
FBA_D<4> 3.1B 5.4C
FBA_D<5> 3.1B 5.4C
FBA_D<6> 3.1B 5.4C
FBA_D<7> 3.1B 5.4C
FBA_D<8> 3.1B 5.4C
FBA_D<9> 3.2B 5.4C
FBA_D<10> 3.2B 5.4C
FBA_D<11> 3.2B 5.4C
FBA_D<12> 3.2B 5.4C
FBA_D<13> 3.2B 5.4C
FBA_D<14> 3.2B 5.4C
FBA_D<15> 3.2B 5.4C
FBA_D<16> 3.2B 5.4D
FBA_D<17> 3.2B 5.4D
FBA_D<18> 3.2B 5.4D
FBA_D<19> 3.2B 5.4D
FBA_D<20> 3.2B 5.4D
FBA_D<21> 3.2B 5.4D
FBA_D<22> 3.2B 5.4D
FBA_D<23> 3.2B 5.4D
FBA_D<24> 3.2B 5.4E
FBA_D<25> 3.2B 5.4E
FBA_D<26> 3.2B 5.4E
FBA_D<27> 3.2B 5.4E
FBA_D<28> 3.2B 5.4E
FBA_D<29> 3.2B 5.4E
FBA_D<30> 3.2B 5.4E
FBA_D<31> 3.2B 5.4E
FBA_D<32> 3.2B 5.5C
FBA_D<33> 3.2B 5.5C
FBA_D<34> 3.2B 5.5C
FBA_D<35> 3.2B 5.5C
FBA_D<36> 3.2B 5.5C
FBA_D<37> 3.2B 5.5C
FBA_D<38> 3.2B 5.5C
FBA_D<39> 3.3B 5.5C
FBA_D<40> 3.3B 5.5C
FBA_D<41> 3.3B 5.5C
FBA_D<42> 3.3B 5.5C
FBA_D<43> 3.3B 5.5C
FBA_D<44> 3.3B 5.5C
FBA_D<45> 3.3B 5.5C
FBA_D<46> 3.3B 5.5C
FBA_D<47> 3.3B 5.5C
FBA_D<48> 3.3B 5.5D
FBA_D<49> 3.3B 5.5D
FBA_D<50> 3.3B 5.5D
FBA_D<51> 3.3B 5.5D
FBA_D<52> 3.3B 5.5D
FBA_D<53> 3.3B 5.5D
FBA_D<54> 3.3B 5.5D
FBA_D<55> 3.3B 5.5D
FBA_D<56> 3.3B 5.5E
FBA_D<57> 3.3B 5.5E
FBA_D<58> 3.3B 5.5E
FBA_D<59> 3.3B 5.5E
FBA_D<60> 3.3B 5.5E
FBA_D<61> 3.3B 5.5E
FBA_D<62> 3.3B 5.5E
FBA_D<63> 3.3B 5.5E
FBA_DEBUG 3.4C
FBA_DQM<0> 3.3B 5.4B 5.4C
FBA_DQM<7..0> 3.4B 5.4B 5.5E
FBA_DQM<1> 3.3B 5.4B 5.4C
FBA_DQM<2> 3.3B 5.4B 5.4D
FBA_DQM<3> 3.4B 5.4B 5.4E
FBA_DQM<4> 3.4B 5.4B 5.5C
FBA_DQM<5> 3.4B 5.4B 5.5C
FBA_DQM<6> 3.4B 5.4B 5.5D
FBA_DQM<7> 3.4B 5.4B 5.5E
FBA_DQS_RN<0> 3.4B 5.4B 5.4C
FBA_DQS_RN<7..0> 3.4B 5.5B 5.5E
FBA_DQS_RN<1> 3.4B 5.4B 5.4C
FBA_DQS_RN<2> 3.4B 5.4B 5.4D
FBA_DQS_RN<3> 3.4B 5.4B 5.4E
FBA_DQS_RN<4> 3.4B 5.4B 5.5C
FBA_DQS_RN<5> 3.4B 5.5B 5.5C
FBA_DQS_RN<6> 3.4B 5.5B 5.5D
FBA_DQS_RN<7> 3.4B 5.5B 5.5E
FBA_DQS_WP<0> 3.4B 5.4C 5.5B
FBA_DQS_WP<7..0> 3.4B 5.5B 5.5E
FBA_DQS_WP<1> 3.4B 5.4C 5.5B
FBA_DQS_WP<2> 3.4B 5.4D 5.5B
FBA_DQS_WP<3> 3.4B 5.4E 5.5B
FBA_DQS_WP<4> 3.4B 5.5B 5.5C
FBA_DQS_WP<5> 3.4B 5.5B 5.5C
FBA_DQS_WP<6> 3.4B 5.5B 5.5D
FBA_DQS_WP<7> 3.4B 5.5B 5.5E
FBB_CLK0 3.4H> 7.2A< 13.2B>
FBB_CLK0* 3.4H> 7.2A< 13.2B>
FBB_CLK1 3.4H> 7.2D< 13.2B>
FBB_CLK1* 3.4H> 7.2D< 13.2B>
FBB_CMD<0> 3.2G 7.1B 7.2G
FBB_CMD<27..0> 3.3G 7.2B 7.2E
FBB_CMD<1> 3.2G 7.1B 7.1E
FBB_CMD<2> 3.2G 7.1B 7.2G
FBB_CMD<3> 3.2G 7.2B 7.2E
FBB_CMD<4> 3.2G 7.1E 7.1G
FBB_CMD<5> 3.2G 7.1E 7.1G
FBB_CMD<6> 3.3G 7.1E 7.1G
FBB_CMD<8> 3.3G 7.1B 7.1E
FBB_CMD<9> 3.3G 7.1B 7.1E
FBB_CMD<10> 3.3G 7.1B 7.1E
FBB_CMD<11> 3.3G 7.1B 7.1E
FBB_CMD<12> 3.3G 7.2B 7.2E
FBB_CMD<13> 3.3G 7.1E 7.1G
FBB_CMD<14> 3.3G 7.2B 7.2E
FBB_CMD<15> 3.3G 7.2B 7.2E
FBB_CMD<16> 3.3G 7.1B 7.1E
FBB_CMD<17> 3.3G 7.1B 7.1E
FBB_CMD<18> 3.3G 7.2B 7.2E
FBB_CMD<19> 3.3G 7.1B 7.1E
FBB_CMD<20> 3.3G 7.1B 7.1E
FBB_CMD<21> 3.3G 7.1B 7.1E
FBB_CMD<22> 3.3G 7.1B 7.2G
FBB_CMD<23> 3.3G 7.1B 7.1E
FBB_CMD<24> 3.3G 7.1B 7.2G
FBB_CMD<25> 3.3G 7.1B 7.1E
FBB_CMD<27> 3.3G 7.2B 7.2E
FBB_D<0> 3.1F 7.4C
FBB_D<63..0> 3.3F 7.5E
FBB_D<1> 3.1F 7.4C
FBB_D<2> 3.1F 7.4C
FBB_D<3> 3.1F 7.4C
FBB_D<4> 3.1F 7.4C
FBB_D<5> 3.1F 7.4C
FBB_D<6> 3.1F 7.4C
FBB_D<7> 3.1F 7.4C
FBB_D<8> 3.1F 7.4C
FBB_D<9> 3.2F 7.4C
FBB_D<10> 3.2F 7.4C
FBB_D<11> 3.2F 7.4C
FBB_D<12> 3.2F 7.4C
FBB_D<13> 3.2F 7.4C
FBB_D<14> 3.2F 7.4C
FBB_D<15> 3.2F 7.4C
FBB_D<16> 3.2F 7.4D
FBB_D<17> 3.2F 7.4D
FBB_D<18> 3.2F 7.4D
FBB_D<19> 3.2F 7.4D
FBB_D<20> 3.2F 7.4D
FBB_D<21> 3.2F 7.4D
FBB_D<22> 3.2F 7.4D
FBB_D<23> 3.2F 7.4D
FBB_D<24> 3.2F 7.4E
FBB_D<25> 3.2F 7.4E
FBB_D<26> 3.2F 7.4E
FBB_D<27> 3.2F 7.4E
FBB_D<28> 3.2F 7.4E
FBB_D<29> 3.2F 7.4E
FBB_D<30> 3.2F 7.4E
FBB_D<31> 3.2F 7.4E
FBB_D<32> 3.2F 7.5C
FBB_D<33> 3.2F 7.5C
FBB_D<34> 3.2F 7.5C
FBB_D<35> 3.2F 7.5C
FBB_D<36> 3.2F 7.5C
FBB_D<37> 3.2F 7.5C
FBB_D<38> 3.2F 7.5C
FBB_D<39> 3.3F 7.5C
FBB_D<40> 3.3F 7.5C
FBB_D<41> 3.3F 7.5C
FBB_D<42> 3.3F 7.5C
FBB_D<43> 3.3F 7.5C
FBB_D<44> 3.3F 7.5C
FBB_D<45> 3.3F 7.5C
FBB_D<46> 3.3F 7.5C
FBB_D<47> 3.3F 7.5C
FBB_D<48> 3.3F 7.5D
FBB_D<49> 3.3F 7.5D
FBB_D<50> 3.3F 7.5D
FBB_D<51> 3.3F 7.5D
FBB_D<52> 3.3F 7.5D
FBB_D<53> 3.3F 7.5D
FBB_D<54> 3.3F 7.5D
FBB_D<55> 3.3F 7.5D
FBB_D<56> 3.3F 7.5E
FBB_D<57> 3.3F 7.5E
FBB_D<58> 3.3F 7.5E
FBB_D<59> 3.3F 7.5E
FBB_D<60> 3.3F 7.5E
FBB_D<61> 3.3F 7.5E
FBB_D<62> 3.3F 7.5E
FBB_D<63> 3.3F 7.5E
FBB_DEBUG 3.4G
FBB_DQM<0> 3.3F 7.4B 7.4C
FBB_DQM<7..0> 3.4F 7.4B 7.5E
FBB_DQM<1> 3.3F 7.4B 7.4C
FBB_DQM<2> 3.3F 7.4B 7.4D
FBB_DQM<3> 3.4F 7.4B 7.4E
FBB_DQM<4> 3.4F 7.4B 7.5C
FBB_DQM<5> 3.4F 7.4B 7.5C
FBB_DQM<6> 3.4F 7.4B 7.5D
FBB_DQM<7> 3.4F 7.4B 7.5E
FBB_DQS_RN<0> 3.4F 7.4B 7.4C
FBB_DQS_RN<7..0> 3.4F 7.5B 7.5E
FBB_DQS_RN<1> 3.4F 7.4B 7.4C
FBB_DQS_RN<2> 3.4F 7.4B 7.4D
FBB_DQS_RN<3> 3.4F 7.4B 7.4E
FBB_DQS_RN<4> 3.4F 7.5B 7.5C
FBB_DQS_RN<5> 3.4F 7.5B 7.5C
FBB_DQS_RN<6> 3.4F 7.5B 7.5D
FBB_DQS_RN<7> 3.4F 7.5B 7.5E
FBB_DQS_WP<0> 3.4F 7.4C 7.5B
FBB_DQS_WP<7..0> 3.4F 7.5B 7.5E
FBB_DQS_WP<1> 3.4F 7.4C 7.5B
FBB_DQS_WP<2> 3.4F 7.4D 7.5B
FBB_DQS_WP<3> 3.4F 7.4E 7.5B
FBB_DQS_WP<4> 3.4F 7.5B 7.5C
FBB_DQS_WP<5> 3.4F 7.5B 7.5C
FBB_DQS_WP<6> 3.4F 7.5B 7.5D
FBB_DQS_WP<7> 3.4F 7.5B 7.5E
FB_CAL_PD_VDDQ 3.4G
FB_CAL_PU_GND 3.5G
FB_CAL_TERM_GND 3.5G
FB_PLLAVDD0 3.5D> 13.3B<>
FB_VREF 3.5A> 13.3B<>
SNN_FBA_CMD<7> 3.3C
SNN_FBA_CMD<26> 3.3C
SNN_FBA_CMD<28> 3.3C
SNN_FBA_CMD<29> 3.3C
SNN_FBA_CMD<30> 3.3C
SNN_FBA_DBI<0> 3.4B
SNN_FBA_DBI<1> 3.4B
SNN_FBA_DBI<2> 3.5B
SNN_FBA_DBI<3> 3.5B
SNN_FBA_DBI<4> 3.5B
SNN_FBA_DBI<5> 3.5B
SNN_FBA_DBI<6> 3.5B
SNN_FBA_DBI<7> 3.5B
SNN_FBA_WDS0 3.4C
SNN_FBA_WDS0* 3.4C
SNN_FBA_WDS1 3.4C
SNN_FBA_WDS1* 3.4C
SNN_FBA_WDS2 3.4C
SNN_FBA_WDS2* 3.4C
SNN_FBA_WDS3 3.4C
SNN_FBA_WDS3* 3.4C
SNN_FBB_CMD<7> 3.3G
SNN_FBB_CMD<26> 3.3G
SNN_FBB_CMD<28> 3.3G
SNN_FBB_CMD<29> 3.3G
SNN_FBB_CMD<30> 3.3G
SNN_FBB_DBI<0> 3.4F
SNN_FBB_DBI<1> 3.4F
SNN_FBB_DBI<2> 3.5F
SNN_FBB_DBI<3> 3.5F
SNN_FBB_DBI<4> 3.5F
SNN_FBB_DBI<5> 3.5F
SNN_FBB_DBI<6> 3.5F
SNN_FBB_DBI<7> 3.5F
SNN_FBB_WDS0 3.4G
SNN_FBB_WDS0* 3.4G
SNN_FBB_WDS1 3.4G
SNN_FBB_WDS1* 3.4G
SNN_FBB_WDS2 3.4G
SNN_FBB_WDS2* 3.4G
SNN_FBB_WDS3 3.4G
SNN_FBB_WDS3* 3.4G
FBC_CLK0 4.4D> 9.2A< 13.1E>
FBC_CLK0* 4.4D> 9.2A< 13.1E>
FBC_CLK1 4.4D> 9.2D< 13.2E>
FBC_CLK1* 4.4D> 9.2D< 13.2E>
FBC_CMD<0> 4.2C 9.1B 9.2G
FBC_CMD<27..0> 4.3C 9.2B 9.2E
FBC_CMD<1> 4.2C 9.1B 9.1E
FBC_CMD<2> 4.2C 9.1B 9.2G
FBC_CMD<3> 4.2C 9.2B 9.2E
FBC_CMD<4> 4.2C 9.1E 9.1G
FBC_CMD<5> 4.2C 9.1E 9.1G
FBC_CMD<6> 4.3C 9.1E 9.1G
FBC_CMD<8> 4.3C 9.1B 9.1E
FBC_CMD<9> 4.3C 9.1B 9.1E
FBC_CMD<10> 4.3C 9.1B 9.1E
FBC_CMD<11> 4.3C 9.1B 9.1E
FBC_CMD<12> 4.3C 9.2B 9.2E
FBC_CMD<13> 4.3C 9.1E 9.1G
FBC_CMD<14> 4.3C 9.2B 9.2E
FBC_CMD<15> 4.3C 9.2B 9.2E
FBC_CMD<16> 4.3C 9.1B 9.1E
FBC_CMD<17> 4.3C 9.1B 9.1E
FBC_CMD<18> 4.3C 9.2B 9.2E
FBC_CMD<19> 4.3C 9.1B 9.1E
FBC_CMD<20> 4.3C 9.1B 9.1E
FBC_CMD<21> 4.3C 9.1B 9.1E
FBC_CMD<22> 4.3C 9.1B 9.2G
FBC_CMD<23> 4.3C 9.1B 9.1E
FBC_CMD<24> 4.3C 9.1B 9.2G
1
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ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
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E
NVIDIA CORPORATION
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SANTA CLARA, CA 95050, USA
NV_PN
ID
NAME
G
600-10562-base-000 A
<ENGINEER>
PAGE
DATE
30-DEC-2008
HFD
Page 36
A B
C D
E
F
G
H
FBC_CMD<25> 4.3C 9.1B 9.1E
FBC_CMD<27> 4.3C 9.2B 9.2E
FBC_D<0> 4.1B 9.4C
FBC_D<63..0> 4.3B 9.5E
FBC_D<1> 4.1B 9.4C
FBC_D<2> 4.1B 9.4C
FBC_D<3> 4.1B 9.4C
FBC_D<4> 4.1B 9.4C
1
FBC_D<5> 4.1B 9.4C
FBC_D<6> 4.1B 9.4C
FBC_D<7> 4.1B 9.4C
FBC_D<8> 4.1B 9.4C
FBC_D<9> 4.2B 9.4C
FBC_D<10> 4.2B 9.4C
FBC_D<11> 4.2B 9.4C
FBC_D<12> 4.2B 9.4C
FBC_D<13> 4.2B 9.4C
FBC_D<14> 4.2B 9.4C
FBC_D<15> 4.2B 9.4C
FBC_D<16> 4.2B 9.4D
FBC_D<17> 4.2B 9.4D
FBC_D<18> 4.2B 9.4D
FBC_D<19> 4.2B 9.4D
FBC_D<20> 4.2B 9.4D
FBC_D<21> 4.2B 9.4D
FBC_D<22> 4.2B 9.4D
FBC_D<23> 4.2B 9.4D
FBC_D<24> 4.2B 9.4E
FBC_D<25> 4.2B 9.4E
2
FBC_D<26> 4.2B 9.4E
FBC_D<27> 4.2B 9.4E
FBC_D<28> 4.2B 9.4E
FBC_D<29> 4.2B 9.4E
FBC_D<30> 4.2B 9.4E
FBC_D<31> 4.2B 9.4E
FBC_D<32> 4.2B 9.5C
FBC_D<33> 4.2B 9.5C
FBC_D<34> 4.2B 9.5C
FBC_D<35> 4.2B 9.5C
FBC_D<36> 4.2B 9.5C
FBC_D<37> 4.2B 9.5C
FBC_D<38> 4.2B 9.5C
FBC_D<39> 4.3B 9.5C
FBC_D<40> 4.3B 9.5C
FBC_D<41> 4.3B 9.5C
FBC_D<42> 4.3B 9.5C
FBC_D<43> 4.3B 9.5C
FBC_D<44> 4.3B 9.5C
FBC_D<45> 4.3B 9.5C
FBC_D<46> 4.3B 9.5C
FBC_D<47> 4.3B 9.5C
3
FBC_D<48> 4.3B 9.5D
FBC_D<49> 4.3B 9.5D
FBC_D<50> 4.3B 9.5D
FBC_D<51> 4.3B 9.5D
FBC_D<52> 4.3B 9.5D
FBC_D<53> 4.3B 9.5D
FBC_D<54> 4.3B 9.5D
FBC_D<55> 4.3B 9.5D
FBC_D<56> 4.3B 9.5E
FBC_D<57> 4.3B 9.5E
FBC_D<58> 4.3B 9.5E
FBC_D<59> 4.3B 9.5E
FBC_D<60> 4.3B 9.5E
FBC_D<61> 4.3B 9.5E
FBC_D<62> 4.3B 9.5E
FBC_D<63> 4.3B 9.5E
FBC_DEBUG 4.4C
FBC_DQM<0> 4.3B 9.4B 9.4C
FBC_DQM<7..0> 4.4B 9.4B 9.5E
FBC_DQM<1> 4.3B 9.4B 9.4C
FBC_DQM<2> 4.3B 9.4B 9.4D
FBC_DQM<3> 4.4B 9.4B 9.4E
4
FBC_DQM<4> 4.4B 9.4B 9.5C
FBC_DQM<5> 4.4B 9.4B 9.5C
FBC_DQM<6> 4.4B 9.4B 9.5D
FBC_DQM<7> 4.4B 9.4B 9.5E
FBC_DQS_RN<0> 4.4B 9.4B 9.4C
FBC_DQS_RN<7..0> 4.4B 9.5B 9.5E
FBC_DQS_RN<1> 4.4B 9.4B 9.4C
FBC_DQS_RN<2> 4.4B 9.4B 9.4D
FBC_DQS_RN<3> 4.4B 9.4B 9.4E
FBC_DQS_RN<4> 4.4B 9.5B 9.5C
FBC_DQS_RN<5> 4.4B 9.5B 9.5C
FBC_DQS_RN<6> 4.4B 9.5B 9.5D
FBC_DQS_RN<7> 4.4B 9.5B 9.5E
FBC_DQS_WP<0> 4.4B 9.4C 9.5B
FBC_DQS_WP<7..0> 4.4B 9.5B 9.5E
FBC_DQS_WP<1> 4.4B 9.4C 9.5B
FBC_DQS_WP<2> 4.4B 9.4D 9.5B
FBC_DQS_WP<3> 4.4B 9.4E 9.5B
FBC_DQS_WP<4> 4.4B 9.5B 9.5C
FBC_DQS_WP<5> 4.4B 9.5B 9.5C
FBC_DQS_WP<6> 4.4B 9.5B 9.5D
FBC_DQS_WP<7> 4.4B 9.5B 9.5E
5
FBD_CLK0 4.4H> 11.2A< 13.2E>
FBD_CLK0* 4.4H> 11.2A< 13.2E>
FBD_CLK1 4.4H> 11.2D< 13.2E>
FBD_CLK1* 4.4H> 11.2D< 13.2E>
FBD_CMD<0> 4.2G 11.1B 11.2G
FBD_CMD<27..0> 4.3G 11.2C 11.2F
FBD_CMD<1> 4.2G 11.1C 11.1F
FBD_CMD<2> 4.2G 11.1B 11.2G
FBD_CMD<3> 4.2G 11.2C 11.2F
FBD_CMD<4> 4.2G 11.1E 11.1G
FBD_CMD<5> 4.2G 11.1E 11.1G
FBD_CMD<6> 4.3G 11.1E 11.1G
FBD_CMD<8> 4.3G 11.1C 11.1F
FBD_CMD<9> 4.3G 11.1C 11.1F
FBD_CMD<10> 4.3G 11.1C 11.1F
FBD_CMD<11> 4.3G 11.1C 11.1F
FBD_CMD<12> 4.3G 11.2C 11.2F
FBD_CMD<13> 4.3G 11.1E 11.2G
FBD_CMD<14> 4.3G 11.2C 11.2F
FBD_CMD<15> 4.3G 11.2C 11.2F
FBD_CMD<16> 4.3G 11.1C 11.1F
FBD_CMD<17> 4.3G 11.1C 11.1F
FBD_CMD<18> 4.3G 11.2C 11.2F
FBD_CMD<19> 4.3G 11.1C 11.1F
FBD_CMD<20> 4.3G 11.1C 11.1F
FBD_CMD<21> 4.3G 11.1C 11.1F
FBD_CMD<22> 4.3G 11.1B 11.2G
FBD_CMD<23> 4.3G 11.1C 11.1F
FBD_CMD<24> 4.3G 11.1B 11.2G
FBD_CMD<25> 4.3G 11.1C 11.1F
FBD_CMD<27> 4.3G 11.2C 11.2F
FBD_D<0> 4.1F 11.4C
FBD_D<63..0> 4.3F 11.5E
FBD_D<1> 4.1F 11.4C
FBD_D<2> 4.1F 11.4C
FBD_D<3> 4.1F 11.4C
FBD_D<4> 4.1F 11.4C
FBD_D<5> 4.1F 11.4C
FBD_D<6> 4.1F 11.4C
FBD_D<7> 4.1F 11.4C
FBD_D<8> 4.1F 11.4D
FBD_D<9> 4.2F 11.4D
FBD_D<10> 4.2F 11.4D
FBD_D<11> 4.2F 11.4D
FBD_D<12> 4.2F 11.4D
FBD_D<13> 4.2F 11.4D
FBD_D<14> 4.2F 11.4D
FBD_D<15> 4.2F 11.4D
FBD_D<16> 4.2F 11.4D
FBD_D<17> 4.2F 11.4D
FBD_D<18> 4.2F 11.4D
FBD_D<19> 4.2F 11.4D
FBD_D<20> 4.2F 11.4D
FBD_D<21> 4.2F 11.4D
FBD_D<22> 4.2F 11.4D
FBD_D<23> 4.2F 11.4D
FBD_D<24> 4.2F 11.4E
FBD_D<25> 4.2F 11.4E
FBD_D<26> 4.2F 11.4E
FBD_D<27> 4.2F 11.4E
FBD_D<28> 4.2F 11.4E
FBD_D<29> 4.2F 11.4E
FBD_D<30> 4.2F 11.4E
FBD_D<31> 4.2F 11.4E
FBD_D<32> 4.2F 11.5C
FBD_D<33> 4.2F 11.5C
FBD_D<34> 4.2F 11.5C
FBD_D<35> 4.2F 11.5C
FBD_D<36> 4.2F 11.5C
FBD_D<37> 4.2F 11.5C
FBD_D<38> 4.2F 11.5C
FBD_D<39> 4.3F 11.5C
FBD_D<40> 4.3F 11.5D
FBD_D<41> 4.3F 11.5D
FBD_D<42> 4.3F 11.5D
FBD_D<43> 4.3F 11.5D
FBD_D<44> 4.3F 11.5D
FBD_D<45> 4.3F 11.5D
FBD_D<46> 4.3F 11.5D
FBD_D<47> 4.3F 11.5D
FBD_D<48> 4.3F 11.5D
FBD_D<49> 4.3F 11.5D
FBD_D<50> 4.3F 11.5D
FBD_D<51> 4.3F 11.5D
FBD_D<52> 4.3F 11.5D
FBD_D<53> 4.3F 11.5D
FBD_D<54> 4.3F 11.5D
FBD_D<55> 4.3F 11.5D
FBD_D<56> 4.3F 11.5E
FBD_D<57> 4.3F 11.5E
FBD_D<58> 4.3F 11.5E
FBD_D<59> 4.3F 11.5E
FBD_D<60> 4.3F 11.5E
FBD_D<61> 4.3F 11.5E
FBD_D<62> 4.3F 11.5E
FBD_D<63> 4.3F 11.5E
FBD_DEBUG 4.4G
FBD_DQM<0> 4.3F 11.4B 11.4C
FBD_DQM<7..0> 4.4F 11.4B 11.5E
FBD_DQM<1> 4.3F 11.4B 11.4D
FBD_DQM<2> 4.3F 11.4B 11.4D
FBD_DQM<3> 4.4F 11.4B 11.4E
FBD_DQM<4> 4.4F 11.4B 11.5C
FBD_DQM<5> 4.4F 11.4B 11.5D
FBD_DQM<6> 4.4F 11.4B 11.5D
FBD_DQM<7> 4.4F 11.4B 11.5E
FBD_DQS_RN<0> 4.4F 11.4B 11.4C
FBD_DQS_RN<7..0> 4.4F 11.5B 11.5E
FBD_DQS_RN<1> 4.4F 11.4B 11.4D
FBD_DQS_RN<2> 4.4F 11.4B 11.4D
FBD_DQS_RN<3> 4.4F 11.4B 11.4E
FBD_DQS_RN<4> 4.4F 11.5B 11.5C
FBD_DQS_RN<5> 4.4F 11.5B 11.5D
FBD_DQS_RN<6> 4.4F 11.5B 11.5D
FBD_DQS_RN<7> 4.4F 11.5B 11.5E
FBD_DQS_WP<0> 4.4F 11.4C 11.5B
FBD_DQS_WP<7..0> 4.4F 11.5B 11.5E
FBD_DQS_WP<1> 4.4F 11.4D 11.5B
FBD_DQS_WP<2> 4.4F 11.4D 11.5B
FBD_DQS_WP<3> 4.4F 11.4E 11.5B
FBD_DQS_WP<4> 4.4F 11.5B 11.5C
FBD_DQS_WP<5> 4.4F 11.5B 11.5D
FBD_DQS_WP<6> 4.4F 11.5B 11.5D
FBD_DQS_WP<7> 4.4F 11.5B 11.5E
FBVDDQ_SENSE 4.5H> 28.4H<
FB_PLLAVDD1 4.5D> 13.3E<>
SNN_FBC_CMD<7> 4.3C
SNN_FBC_CMD<26> 4.3C
SNN_FBC_CMD<28> 4.3C
SNN_FBC_CMD<29> 4.3C
SNN_FBC_CMD<30> 4.3C
SNN_FBC_DBI<0> 4.4B
SNN_FBC_DBI<1> 4.4B
SNN_FBC_DBI<2> 4.5B
SNN_FBC_DBI<3> 4.5B
SNN_FBC_DBI<4> 4.5B
SNN_FBC_DBI<5> 4.5B
SNN_FBC_DBI<6> 4.5B
SNN_FBC_DBI<7> 4.5B
SNN_FBC_WDS0 4.4C
SNN_FBC_WDS0* 4.4C
SNN_FBC_WDS1 4.4C
SNN_FBC_WDS1* 4.4C
SNN_FBC_WDS2 4.4C
SNN_FBC_WDS2* 4.4C
SNN_FBC_WDS3 4.4C
SNN_FBC_WDS3* 4.4C
SNN_FBD_CMD<7> 4.3G
SNN_FBD_CMD<26> 4.3G
SNN_FBD_CMD<28> 4.3G
SNN_FBD_CMD<29> 4.3G
SNN_FBD_CMD<30> 4.3G
SNN_FBD_DBI<0> 4.4F
SNN_FBD_DBI<1> 4.4F
SNN_FBD_DBI<2> 4.5F
SNN_FBD_DBI<3> 4.5F
SNN_FBD_DBI<4> 4.5F
SNN_FBD_DBI<5> 4.5F
SNN_FBD_DBI<6> 4.5F
SNN_FBD_DBI<7> 4.5F
SNN_FBD_WDS0 4.4G
SNN_FBD_WDS0* 4.4G
SNN_FBD_WDS1 4.4G
SNN_FBD_WDS1* 4.4G
SNN_FBD_WDS2 4.4G
SNN_FBD_WDS2* 4.4G
SNN_FBD_WDS3 4.4G
SNN_FBD_WDS3* 4.4G
FBA_CLK0 3.4D> 5.2A< 13.1B>
FBA_CLK0* 3.4D> 5.2A< 13.1B>
FBA_CLK0_TERM 5.1A
FBA_CLK1 3.4D> 5.2D< 13.2B>
FBA_CLK1* 3.4D> 5.2D< 13.2B>
FBA_CLK1_TERM 5.1D
FBA_CMD<0> 3.2C 5.1B 5.1G
FBA_CMD<0> 3.2C 5.1B 5.1G
FBA_CMD<27..0> 3.3C 5.2B 5.2E
FBA_CMD<1> 3.2C 5.1B 5.1E
FBA_CMD<1> 3.2C 5.1B 5.1E
FBA_CMD<2> 3.2C 5.1B 5.1G
FBA_CMD<2> 3.2C 5.1B 5.1G
FBA_CMD<3> 3.2C 5.2B 5.2E
FBA_CMD<3> 3.2C 5.2B 5.2E
FBA_CMD<4> 3.2C 5.1E 5.1G
FBA_CMD<4> 3.2C 5.1E 5.1G
FBA_CMD<5> 3.2C 5.1E 5.1G
FBA_CMD<5> 3.2C 5.1E 5.1G
FBA_CMD<6> 3.3C 5.1E 5.1G
FBA_CMD<6> 3.3C 5.1E 5.1G
FBA_CMD<8> 3.3C 5.1B 5.1E
FBA_CMD<8> 3.3C 5.1B 5.1E
FBA_CMD<9> 3.3C 5.1B 5.1E
FBA_CMD<9> 3.3C 5.1B 5.1E
FBA_CMD<10> 3.3C 5.1B 5.1E
FBA_CMD<10> 3.3C 5.1B 5.1E
FBA_CMD<11> 3.3C 5.1B 5.1E
FBA_CMD<11> 3.3C 5.1B 5.1E
FBA_CMD<12> 3.3C 5.2B 5.2E
FBA_CMD<12> 3.3C 5.2B 5.2E
FBA_CMD<13> 3.3C 5.1E 5.1G
FBA_CMD<13> 3.3C 5.1E 5.1G
FBA_CMD<14> 3.3C 5.2B 5.2E
FBA_CMD<14> 3.3C 5.2B 5.2E
FBA_CMD<15> 3.3C 5.2B 5.2E
FBA_CMD<15> 3.3C 5.2B 5.2E
FBA_CMD<16> 3.3C 5.1B 5.1E
FBA_CMD<16> 3.3C 5.1B 5.1E
FBA_CMD<17> 3.3C 5.1B 5.1E
FBA_CMD<17> 3.3C 5.1B 5.1E
FBA_CMD<18> 3.3C 5.2B 5.2E
FBA_CMD<18> 3.3C 5.2B 5.2E
FBA_CMD<19> 3.3C 5.1B 5.1E
FBA_CMD<19> 3.3C 5.1B 5.1E
FBA_CMD<20> 3.3C 5.1B 5.1E
FBA_CMD<20> 3.3C 5.1B 5.1E
FBA_CMD<21> 3.3C 5.1B 5.1E
FBA_CMD<21> 3.3C 5.1B 5.1E
FBA_CMD<22> 3.3C 5.1B 5.1G
FBA_CMD<22> 3.3C 5.1B 5.1G
FBA_CMD<23> 3.3C 5.1B 5.1E
FBA_CMD<23> 3.3C 5.1B 5.1E
FBA_CMD<24> 3.3C 5.1B 5.1G
FBA_CMD<24> 3.3C 5.1B 5.1G
FBA_CMD<25> 3.3C 5.1B 5.1E
FBA_CMD<25> 3.3C 5.1B 5.1E
FBA_CMD<27> 3.3C 5.2B 5.2E
FBA_CMD<27> 3.3C 5.2B 5.2E
FBA_CMD_SENA0 5.2B
FBA_CMD_SENA1 5.2E
FBA_D<0> 3.1B 5.4C
FBA_D<63..0> 3.3B 5.5E
FBA_D<1> 3.1B 5.4C
FBA_D<2> 3.1B 5.4C
FBA_D<3> 3.1B 5.4C
FBA_D<4> 3.1B 5.4C
FBA_D<5> 3.1B 5.4C
FBA_D<6> 3.1B 5.4C
FBA_D<7> 3.1B 5.4C
FBA_D<8> 3.1B 5.4C
FBA_D<9> 3.2B 5.4C
FBA_D<10> 3.2B 5.4C
FBA_D<11> 3.2B 5.4C
FBA_D<12> 3.2B 5.4C
FBA_D<13> 3.2B 5.4C
FBA_D<14> 3.2B 5.4C
FBA_D<15> 3.2B 5.4C
FBA_D<16> 3.2B 5.4D
FBA_D<17> 3.2B 5.4D
FBA_D<18> 3.2B 5.4D
FBA_D<19> 3.2B 5.4D
FBA_D<20> 3.2B 5.4D
FBA_D<21> 3.2B 5.4D
FBA_D<22> 3.2B 5.4D
FBA_D<23> 3.2B 5.4D
FBA_D<24> 3.2B 5.4E
FBA_D<25> 3.2B 5.4E
FBA_D<26> 3.2B 5.4E
FBA_D<27> 3.2B 5.4E
FBA_D<28> 3.2B 5.4E
FBA_D<29> 3.2B 5.4E
FBA_D<30> 3.2B 5.4E
FBA_D<31> 3.2B 5.4E
FBA_D<32> 3.2B 5.5C
FBA_D<33> 3.2B 5.5C
FBA_D<34> 3.2B 5.5C
FBA_D<35> 3.2B 5.5C
FBA_D<36> 3.2B 5.5C
FBA_D<37> 3.2B 5.5C
FBA_D<38> 3.2B 5.5C
FBA_D<39> 3.3B 5.5C
FBA_D<40> 3.3B 5.5C
FBA_D<41> 3.3B 5.5C
FBA_D<42> 3.3B 5.5C
FBA_D<43> 3.3B 5.5C
FBA_D<44> 3.3B 5.5C
FBA_D<45> 3.3B 5.5C
FBA_D<46> 3.3B 5.5C
FBA_D<47> 3.3B 5.5C
FBA_D<48> 3.3B 5.5D
FBA_D<49> 3.3B 5.5D
FBA_D<50> 3.3B 5.5D
FBA_D<51> 3.3B 5.5D
FBA_D<52> 3.3B 5.5D
FBA_D<53> 3.3B 5.5D
FBA_D<54> 3.3B 5.5D
FBA_D<55> 3.3B 5.5D
FBA_D<56> 3.3B 5.5E
FBA_D<57> 3.3B 5.5E
FBA_D<58> 3.3B 5.5E
FBA_D<59> 3.3B 5.5E
FBA_D<60> 3.3B 5.5E
FBA_D<61> 3.3B 5.5E
FBA_D<62> 3.3B 5.5E
FBA_D<63> 3.3B 5.5E
FBA_DQM<0> 3.3B 5.4B 5.4C
FBA_DQM<0> 3.3B 5.4B 5.4C
FBA_DQM<7..0> 3.4B 5.4B 5.5E
FBA_DQM<1> 3.3B 5.4B 5.4C
FBA_DQM<1> 3.3B 5.4B 5.4C
FBA_DQM<2> 3.3B 5.4B 5.4D
FBA_DQM<2> 3.3B 5.4B 5.4D
FBA_DQM<3> 3.4B 5.4B 5.4E
FBA_DQM<3> 3.4B 5.4B 5.4E
FBA_DQM<4> 3.4B 5.4B 5.5C
FBA_DQM<4> 3.4B 5.4B 5.5C
FBA_DQM<5> 3.4B 5.4B 5.5C
FBA_DQM<5> 3.4B 5.4B 5.5C
FBA_DQM<6> 3.4B 5.4B 5.5D
FBA_DQM<6> 3.4B 5.4B 5.5D
FBA_DQM<7> 3.4B 5.4B 5.5E
FBA_DQM<7> 3.4B 5.4B 5.5E
FBA_DQS_RN<0> 3.4B 5.4B 5.4C
FBA_DQS_RN<0> 3.4B 5.4B 5.4C
FBA_DQS_RN<7..0> 3.4B 5.5B 5.5E
FBA_DQS_RN<1> 3.4B 5.4B 5.4C
FBA_DQS_RN<1> 3.4B 5.4B 5.4C
FBA_DQS_RN<2> 3.4B 5.4B 5.4D
FBA_DQS_RN<2> 3.4B 5.4B 5.4D
FBA_DQS_RN<3> 3.4B 5.4B 5.4E
FBA_DQS_RN<3> 3.4B 5.4B 5.4E
FBA_DQS_RN<4> 3.4B 5.4B 5.5C
FBA_DQS_RN<4> 3.4B 5.4B 5.5C
FBA_DQS_RN<5> 3.4B 5.5B 5.5C
FBA_DQS_RN<5> 3.4B 5.5B 5.5C
FBA_DQS_RN<6> 3.4B 5.5B 5.5D
FBA_DQS_RN<6> 3.4B 5.5B 5.5D
FBA_DQS_RN<7> 3.4B 5.5B 5.5E
FBA_DQS_RN<7> 3.4B 5.5B 5.5E
FBA_DQS_WP<0> 3.4B 5.4C 5.5B
FBA_DQS_WP<0> 3.4B 5.4C 5.5B
FBA_DQS_WP<7..0> 3.4B 5.5B 5.5E
FBA_DQS_WP<1> 3.4B 5.4C 5.5B
FBA_DQS_WP<1> 3.4B 5.4C 5.5B
FBA_DQS_WP<2> 3.4B 5.4D 5.5B
FBA_DQS_WP<2> 3.4B 5.4D 5.5B
FBA_DQS_WP<3> 3.4B 5.4E 5.5B
FBA_DQS_WP<3> 3.4B 5.4E 5.5B
FBA_DQS_WP<4> 3.4B 5.5B 5.5C
FBA_DQS_WP<4> 3.4B 5.5B 5.5C
FBA_DQS_WP<5> 3.4B 5.5B 5.5C
FBA_DQS_WP<5> 3.4B 5.5B 5.5C
FBA_DQS_WP<6> 3.4B 5.5B 5.5D
FBA_DQS_WP<6> 3.4B 5.5B 5.5D
FBA_DQS_WP<7> 3.4B 5.5B 5.5E
FBA_DQS_WP<7> 3.4B 5.5B 5.5E
FBA_VREF0 5.3D> 13.3B<>
FBA_VREF1 5.3G> 13.4B<>
FBA_VREF2 5.3E> 13.4B<>
FBA_VREF3 5.3H> 13.4B<>
FBA_ZQ0 5.2B< 13.4B<>
FBA_ZQ1 5.2E< 13.4B<>
SNN_FBA0_NC1 5.2B
SNN_FBA1_NC1 5.2E
FBB_CLK0 3.4H> 7.2A< 13.2B>
FBB_CLK0* 3.4H> 7.2A< 13.2B>
FBB_CLK0_TERM 7.1A
FBB_CLK1 3.4H> 7.2D< 13.2B>
FBB_CLK1* 3.4H> 7.2D< 13.2B>
FBB_CLK1_TERM 7.1D
FBB_CMD<0> 3.2G 7.1B 7.2G
FBB_CMD<0> 3.2G 7.1B 7.2G
FBB_CMD<27..0> 3.3G 7.2B 7.2E
FBB_CMD<1> 3.2G 7.1B 7.1E
FBB_CMD<1> 3.2G 7.1B 7.1E
FBB_CMD<2> 3.2G 7.1B 7.2G
FBB_CMD<2> 3.2G 7.1B 7.2G
FBB_CMD<3> 3.2G 7.2B 7.2E
FBB_CMD<3> 3.2G 7.2B 7.2E
FBB_CMD<4> 3.2G 7.1E 7.1G
FBB_CMD<4> 3.2G 7.1E 7.1G
FBB_CMD<5> 3.2G 7.1E 7.1G
FBB_CMD<5> 3.2G 7.1E 7.1G
FBB_CMD<6> 3.3G 7.1E 7.1G
FBB_CMD<6> 3.3G 7.1E 7.1G
FBB_CMD<8> 3.3G 7.1B 7.1E
FBB_CMD<8> 3.3G 7.1B 7.1E
FBB_CMD<9> 3.3G 7.1B 7.1E
FBB_CMD<9> 3.3G 7.1B 7.1E
FBB_CMD<10> 3.3G 7.1B 7.1E
FBB_CMD<10> 3.3G 7.1B 7.1E
FBB_CMD<11> 3.3G 7.1B 7.1E
FBB_CMD<11> 3.3G 7.1B 7.1E
FBB_CMD<12> 3.3G 7.2B 7.2E
FBB_CMD<12> 3.3G 7.2B 7.2E
FBB_CMD<13> 3.3G 7.1E 7.1G
FBB_CMD<13> 3.3G 7.1E 7.1G
FBB_CMD<14> 3.3G 7.2B 7.2E
FBB_CMD<14> 3.3G 7.2B 7.2E
FBB_CMD<15> 3.3G 7.2B 7.2E
FBB_CMD<15> 3.3G 7.2B 7.2E
FBB_CMD<16> 3.3G 7.1B 7.1E
FBB_CMD<16> 3.3G 7.1B 7.1E
FBB_CMD<17> 3.3G 7.1B 7.1E
FBB_CMD<17> 3.3G 7.1B 7.1E
FBB_CMD<18> 3.3G 7.2B 7.2E
FBB_CMD<18> 3.3G 7.2B 7.2E
FBB_CMD<19> 3.3G 7.1B 7.1E
FBB_CMD<19> 3.3G 7.1B 7.1E
FBB_CMD<20> 3.3G 7.1B 7.1E
FBB_CMD<20> 3.3G 7.1B 7.1E
FBB_CMD<21> 3.3G 7.1B 7.1E
FBB_CMD<21> 3.3G 7.1B 7.1E
FBB_CMD<22> 3.3G 7.1B 7.2G
FBB_CMD<22> 3.3G 7.1B 7.2G
FBB_CMD<23> 3.3G 7.1B 7.1E
FBB_CMD<23> 3.3G 7.1B 7.1E
FBB_CMD<24> 3.3G 7.1B 7.2G
FBB_CMD<24> 3.3G 7.1B 7.2G
FBB_CMD<25> 3.3G 7.1B 7.1E
FBB_CMD<25> 3.3G 7.1B 7.1E
FBB_CMD<27> 3.3G 7.2B 7.2E
FBB_CMD<27> 3.3G 7.2B 7.2E
FBB_CMD_SENB0 7.2B
FBB_CMD_SENB1 7.2E
FBB_D<0> 3.1F 7.4C
FBB_D<63..0> 3.3F 7.5E
FBB_D<1> 3.1F 7.4C
FBB_D<2> 3.1F 7.4C
FBB_D<3> 3.1F 7.4C
FBB_D<4> 3.1F 7.4C
FBB_D<5> 3.1F 7.4C
FBB_D<6> 3.1F 7.4C
FBB_D<7> 3.1F 7.4C
FBB_D<8> 3.1F 7.4C
FBB_D<9> 3.2F 7.4C
FBB_D<10> 3.2F 7.4C
FBB_D<11> 3.2F 7.4C
FBB_D<12> 3.2F 7.4C
FBB_D<13> 3.2F 7.4C
FBB_D<14> 3.2F 7.4C
FBB_D<15> 3.2F 7.4C
FBB_D<16> 3.2F 7.4D
FBB_D<17> 3.2F 7.4D
FBB_D<18> 3.2F 7.4D
FBB_D<19> 3.2F 7.4D
FBB_D<20> 3.2F 7.4D
FBB_D<21> 3.2F 7.4D
FBB_D<22> 3.2F 7.4D
FBB_D<23> 3.2F 7.4D
FBB_D<24> 3.2F 7.4E
FBB_D<25> 3.2F 7.4E
FBB_D<26> 3.2F 7.4E
FBB_D<27> 3.2F 7.4E
FBB_D<28> 3.2F 7.4E
FBB_D<29> 3.2F 7.4E
FBB_D<30> 3.2F 7.4E
FBB_D<31> 3.2F 7.4E
FBB_D<32> 3.2F 7.5C
FBB_D<33> 3.2F 7.5C
FBB_D<34> 3.2F 7.5C
FBB_D<35> 3.2F 7.5C
FBB_D<36> 3.2F 7.5C
FBB_D<37> 3.2F 7.5C
FBB_D<38> 3.2F 7.5C
FBB_D<39> 3.3F 7.5C
FBB_D<40> 3.3F 7.5C
FBB_D<41> 3.3F 7.5C
FBB_D<42> 3.3F 7.5C
FBB_D<43> 3.3F 7.5C
FBB_D<44> 3.3F 7.5C
FBB_D<45> 3.3F 7.5C
FBB_D<46> 3.3F 7.5C
FBB_D<47> 3.3F 7.5C
FBB_D<48> 3.3F 7.5D
FBB_D<49> 3.3F 7.5D
FBB_D<50> 3.3F 7.5D
FBB_D<51> 3.3F 7.5D
FBB_D<52> 3.3F 7.5D
FBB_D<53> 3.3F 7.5D
FBB_D<54> 3.3F 7.5D
FBB_D<55> 3.3F 7.5D
FBB_D<56> 3.3F 7.5E
FBB_D<57> 3.3F 7.5E
FBB_D<58> 3.3F 7.5E
FBB_D<59> 3.3F 7.5E
FBB_D<60> 3.3F 7.5E
FBB_D<61> 3.3F 7.5E
FBB_D<62> 3.3F 7.5E
FBB_D<63> 3.3F 7.5E
FBB_DQM<0> 3.3F 7.4B 7.4C
FBB_DQM<0> 3.3F 7.4B 7.4C
1
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ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
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<edit here to insert page detail>
E
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
ID
NAME
G
600-10562-base-000 A
<ENGINEER>
PAGE
DATE
30-DEC-2008
HFD
Page 37
A B
C D
E
F
G
H
FBB_DQM<7..0> 3.4F 7.4B 7.5E
FBB_DQM<1> 3.3F 7.4B 7.4C
FBB_DQM<1> 3.3F 7.4B 7.4C
FBB_DQM<2> 3.3F 7.4B 7.4D
FBB_DQM<2> 3.3F 7.4B 7.4D
FBB_DQM<3> 3.4F 7.4B 7.4E
FBB_DQM<3> 3.4F 7.4B 7.4E
FBB_DQM<4> 3.4F 7.4B 7.5C
1
FBB_DQM<4> 3.4F 7.4B 7.5C
FBB_DQM<5> 3.4F 7.4B 7.5C
FBB_DQM<5> 3.4F 7.4B 7.5C
FBB_DQM<6> 3.4F 7.4B 7.5D
FBB_DQM<6> 3.4F 7.4B 7.5D
FBB_DQM<7> 3.4F 7.4B 7.5E
FBB_DQM<7> 3.4F 7.4B 7.5E
FBB_DQS_RN<0> 3.4F 7.4B 7.4C
FBB_DQS_RN<0> 3.4F 7.4B 7.4C
FBB_DQS_RN<7..0> 3.4F 7.5B 7.5E
FBB_DQS_RN<1> 3.4F 7.4B 7.4C
FBB_DQS_RN<1> 3.4F 7.4B 7.4C
FBB_DQS_RN<2> 3.4F 7.4B 7.4D
FBB_DQS_RN<2> 3.4F 7.4B 7.4D
FBB_DQS_RN<3> 3.4F 7.4B 7.4E
FBB_DQS_RN<3> 3.4F 7.4B 7.4E
FBB_DQS_RN<4> 3.4F 7.5B 7.5C
FBB_DQS_RN<4> 3.4F 7.5B 7.5C
FBB_DQS_RN<5> 3.4F 7.5B 7.5C
FBB_DQS_RN<5> 3.4F 7.5B 7.5C
FBB_DQS_RN<6> 3.4F 7.5B 7.5D
2
FBB_DQS_RN<6> 3.4F 7.5B 7.5D
FBB_DQS_RN<7> 3.4F 7.5B 7.5E
FBB_DQS_RN<7> 3.4F 7.5B 7.5E
FBB_DQS_WP<0> 3.4F 7.4C 7.5B
FBB_DQS_WP<0> 3.4F 7.4C 7.5B
FBB_DQS_WP<7..0> 3.4F 7.5B 7.5E
FBB_DQS_WP<1> 3.4F 7.4C 7.5B
FBB_DQS_WP<1> 3.4F 7.4C 7.5B
FBB_DQS_WP<2> 3.4F 7.4D 7.5B
FBB_DQS_WP<2> 3.4F 7.4D 7.5B
FBB_DQS_WP<3> 3.4F 7.4E 7.5B
FBB_DQS_WP<3> 3.4F 7.4E 7.5B
FBB_DQS_WP<4> 3.4F 7.5B 7.5C
FBB_DQS_WP<4> 3.4F 7.5B 7.5C
FBB_DQS_WP<5> 3.4F 7.5B 7.5C
FBB_DQS_WP<5> 3.4F 7.5B 7.5C
FBB_DQS_WP<6> 3.4F 7.5B 7.5D
FBB_DQS_WP<6> 3.4F 7.5B 7.5D
FBB_DQS_WP<7> 3.4F 7.5B 7.5E
FBB_DQS_WP<7> 3.4F 7.5B 7.5E
FBB_VREF0 7.3D> 13.4B<>
FBB_VREF1 7.3G> 13.4B<>
3
FBB_VREF2 7.3E> 13.4B<>
FBB_VREF3 7.3H> 13.4B<>
FBB_ZQ0 7.2B< 13.4B<>
FBB_ZQ1 7.2E< 13.4B<>
SNN_FBB0_NC1 7.2B
SNN_FBB1_NC1 7.2E
FBC_CLK0 4.4D> 9.2A< 13.1E>
FBC_CLK0* 4.4D> 9.2A< 13.1E>
FBC_CLK0_TERM 9.1A
FBC_CLK1 4.4D> 9.2D< 13.2E>
FBC_CLK1* 4.4D> 9.2D< 13.2E>
FBC_CLK1_TERM 9.1D
FBC_CMD<0> 4.2C 9.1B 9.2G
FBC_CMD<0> 4.2C 9.1B 9.2G
FBC_CMD<27..0> 4.3C 9.2B 9.2E
FBC_CMD<1> 4.2C 9.1B 9.1E
FBC_CMD<1> 4.2C 9.1B 9.1E
FBC_CMD<2> 4.2C 9.1B 9.2G
FBC_CMD<2> 4.2C 9.1B 9.2G
FBC_CMD<3> 4.2C 9.2B 9.2E
FBC_CMD<3> 4.2C 9.2B 9.2E
FBC_CMD<4> 4.2C 9.1E 9.1G
4
FBC_CMD<4> 4.2C 9.1E 9.1G
FBC_CMD<5> 4.2C 9.1E 9.1G
FBC_CMD<5> 4.2C 9.1E 9.1G
FBC_CMD<6> 4.3C 9.1E 9.1G
FBC_CMD<6> 4.3C 9.1E 9.1G
FBC_CMD<8> 4.3C 9.1B 9.1E
FBC_CMD<8> 4.3C 9.1B 9.1E
FBC_CMD<9> 4.3C 9.1B 9.1E
FBC_CMD<9> 4.3C 9.1B 9.1E
FBC_CMD<10> 4.3C 9.1B 9.1E
FBC_CMD<10> 4.3C 9.1B 9.1E
FBC_CMD<11> 4.3C 9.1B 9.1E
FBC_CMD<11> 4.3C 9.1B 9.1E
FBC_CMD<12> 4.3C 9.2B 9.2E
FBC_CMD<12> 4.3C 9.2B 9.2E
FBC_CMD<13> 4.3C 9.1E 9.1G
FBC_CMD<13> 4.3C 9.1E 9.1G
FBC_CMD<14> 4.3C 9.2B 9.2E
FBC_CMD<14> 4.3C 9.2B 9.2E
FBC_CMD<15> 4.3C 9.2B 9.2E
FBC_CMD<15> 4.3C 9.2B 9.2E
FBC_CMD<16> 4.3C 9.1B 9.1E
5
FBC_CMD<16> 4.3C 9.1B 9.1E
FBC_CMD<17> 4.3C 9.1B 9.1E
FBC_CMD<17> 4.3C 9.1B 9.1E
FBC_CMD<18> 4.3C 9.2B 9.2E
FBC_CMD<18> 4.3C 9.2B 9.2E
FBC_CMD<19> 4.3C 9.1B 9.1E
FBC_CMD<19> 4.3C 9.1B 9.1E
FBC_CMD<20> 4.3C 9.1B 9.1E
FBC_CMD<20> 4.3C 9.1B 9.1E
FBC_CMD<21> 4.3C 9.1B 9.1E
FBC_CMD<21> 4.3C 9.1B 9.1E
FBC_CMD<22> 4.3C 9.1B 9.2G
FBC_CMD<22> 4.3C 9.1B 9.2G
FBC_CMD<23> 4.3C 9.1B 9.1E
FBC_CMD<23> 4.3C 9.1B 9.1E
FBC_CMD<24> 4.3C 9.1B 9.2G
FBC_CMD<24> 4.3C 9.1B 9.2G
FBC_CMD<25> 4.3C 9.1B 9.1E
FBC_CMD<25> 4.3C 9.1B 9.1E
FBC_CMD<27> 4.3C 9.2B 9.2E
FBC_CMD<27> 4.3C 9.2B 9.2E
FBC_CMD_SENC0 9.2B
FBC_CMD_SENC1 9.2E
FBC_D<0> 4.1B 9.4C
FBC_D<63..0> 4.3B 9.5E
FBC_D<1> 4.1B 9.4C
FBC_D<2> 4.1B 9.4C
FBC_D<3> 4.1B 9.4C
FBC_D<4> 4.1B 9.4C
FBC_D<5> 4.1B 9.4C
FBC_D<6> 4.1B 9.4C
FBC_D<7> 4.1B 9.4C
FBC_D<8> 4.1B 9.4C
FBC_D<9> 4.2B 9.4C
FBC_D<10> 4.2B 9.4C
FBC_D<11> 4.2B 9.4C
FBC_D<12> 4.2B 9.4C
FBC_D<13> 4.2B 9.4C
FBC_D<14> 4.2B 9.4C
FBC_D<15> 4.2B 9.4C
FBC_D<16> 4.2B 9.4D
FBC_D<17> 4.2B 9.4D
FBC_D<18> 4.2B 9.4D
FBC_D<19> 4.2B 9.4D
FBC_D<20> 4.2B 9.4D
FBC_D<21> 4.2B 9.4D
FBC_D<22> 4.2B 9.4D
FBC_D<23> 4.2B 9.4D
FBC_D<24> 4.2B 9.4E
FBC_D<25> 4.2B 9.4E
FBC_D<26> 4.2B 9.4E
FBC_D<27> 4.2B 9.4E
FBC_D<28> 4.2B 9.4E
FBC_D<29> 4.2B 9.4E
FBC_D<30> 4.2B 9.4E
FBC_D<31> 4.2B 9.4E
FBC_D<32> 4.2B 9.5C
FBC_D<33> 4.2B 9.5C
FBC_D<34> 4.2B 9.5C
FBC_D<35> 4.2B 9.5C
FBC_D<36> 4.2B 9.5C
FBC_D<37> 4.2B 9.5C
FBC_D<38> 4.2B 9.5C
FBC_D<39> 4.3B 9.5C
FBC_D<40> 4.3B 9.5C
FBC_D<41> 4.3B 9.5C
FBC_D<42> 4.3B 9.5C
FBC_D<43> 4.3B 9.5C
FBC_D<44> 4.3B 9.5C
FBC_D<45> 4.3B 9.5C
FBC_D<46> 4.3B 9.5C
FBC_D<47> 4.3B 9.5C
FBC_D<48> 4.3B 9.5D
FBC_D<49> 4.3B 9.5D
FBC_D<50> 4.3B 9.5D
FBC_D<51> 4.3B 9.5D
FBC_D<52> 4.3B 9.5D
FBC_D<53> 4.3B 9.5D
FBC_D<54> 4.3B 9.5D
FBC_D<55> 4.3B 9.5D
FBC_D<56> 4.3B 9.5E
FBC_D<57> 4.3B 9.5E
FBC_D<58> 4.3B 9.5E
FBC_D<59> 4.3B 9.5E
FBC_D<60> 4.3B 9.5E
FBC_D<61> 4.3B 9.5E
FBC_D<62> 4.3B 9.5E
FBC_D<63> 4.3B 9.5E
FBC_DQM<0> 4.3B 9.4B 9.4C
FBC_DQM<0> 4.3B 9.4B 9.4C
FBC_DQM<7..0> 4.4B 9.4B 9.5E
FBC_DQM<1> 4.3B 9.4B 9.4C
FBC_DQM<1> 4.3B 9.4B 9.4C
FBC_DQM<2> 4.3B 9.4B 9.4D
FBC_DQM<2> 4.3B 9.4B 9.4D
FBC_DQM<3> 4.4B 9.4B 9.4E
FBC_DQM<3> 4.4B 9.4B 9.4E
FBC_DQM<4> 4.4B 9.4B 9.5C
FBC_DQM<4> 4.4B 9.4B 9.5C
FBC_DQM<5> 4.4B 9.4B 9.5C
FBC_DQM<5> 4.4B 9.4B 9.5C
FBC_DQM<6> 4.4B 9.4B 9.5D
FBC_DQM<6> 4.4B 9.4B 9.5D
FBC_DQM<7> 4.4B 9.4B 9.5E
FBC_DQM<7> 4.4B 9.4B 9.5E
FBC_DQS_RN<0> 4.4B 9.4B 9.4C
FBC_DQS_RN<0> 4.4B 9.4B 9.4C
FBC_DQS_RN<7..0> 4.4B 9.5B 9.5E
FBC_DQS_RN<1> 4.4B 9.4B 9.4C
FBC_DQS_RN<1> 4.4B 9.4B 9.4C
FBC_DQS_RN<2> 4.4B 9.4B 9.4D
FBC_DQS_RN<2> 4.4B 9.4B 9.4D
FBC_DQS_RN<3> 4.4B 9.4B 9.4E
FBC_DQS_RN<3> 4.4B 9.4B 9.4E
FBC_DQS_RN<4> 4.4B 9.5B 9.5C
FBC_DQS_RN<4> 4.4B 9.5B 9.5C
FBC_DQS_RN<5> 4.4B 9.5B 9.5C
FBC_DQS_RN<5> 4.4B 9.5B 9.5C
FBC_DQS_RN<6> 4.4B 9.5B 9.5D
FBC_DQS_RN<6> 4.4B 9.5B 9.5D
FBC_DQS_RN<7> 4.4B 9.5B 9.5E
FBC_DQS_RN<7> 4.4B 9.5B 9.5E
FBC_DQS_WP<0> 4.4B 9.4C 9.5B
FBC_DQS_WP<0> 4.4B 9.4C 9.5B
FBC_DQS_WP<7..0> 4.4B 9.5B 9.5E
FBC_DQS_WP<1> 4.4B 9.4C 9.5B
FBC_DQS_WP<1> 4.4B 9.4C 9.5B
FBC_DQS_WP<2> 4.4B 9.4D 9.5B
FBC_DQS_WP<2> 4.4B 9.4D 9.5B
FBC_DQS_WP<3> 4.4B 9.4E 9.5B
FBC_DQS_WP<3> 4.4B 9.4E 9.5B
FBC_DQS_WP<4> 4.4B 9.5B 9.5C
FBC_DQS_WP<4> 4.4B 9.5B 9.5C
FBC_DQS_WP<5> 4.4B 9.5B 9.5C
FBC_DQS_WP<5> 4.4B 9.5B 9.5C
FBC_DQS_WP<6> 4.4B 9.5B 9.5D
FBC_DQS_WP<6> 4.4B 9.5B 9.5D
FBC_DQS_WP<7> 4.4B 9.5B 9.5E
FBC_DQS_WP<7> 4.4B 9.5B 9.5E
FBC_VREF0 9.3D> 13.3E<>
FBC_VREF1 9.3G> 13.4E<>
FBC_VREF2 9.3E> 13.4E<>
FBC_VREF3 9.3H> 13.4E<>
FBC_ZQ0 9.2B< 13.4E<>
FBC_ZQ1 9.2E< 13.4E<>
SNN_FBC0_NC1 9.2B
SNN_FBC1_NC1 9.2E
FBD_CLK0 4.4H> 11.2A< 13.2E>
FBD_CLK0* 4.4H> 11.2A< 13.2E>
FBD_CLK0_TERM 11.1A
FBD_CLK1 4.4H> 11.2D< 13.2E>
FBD_CLK1* 4.4H> 11.2D< 13.2E>
FBD_CLK1_TERM 11.1D
FBD_CMD<0> 4.2G 11.1B 11.2G
FBD_CMD<0> 4.2G 11.1B 11.2G
FBD_CMD<27..0> 4.3G 11.2C 11.2F
FBD_CMD<1> 4.2G 11.1C 11.1F
FBD_CMD<1> 4.2G 11.1C 11.1F
FBD_CMD<2> 4.2G 11.1B 11.2G
FBD_CMD<2> 4.2G 11.1B 11.2G
FBD_CMD<3> 4.2G 11.2C 11.2F
FBD_CMD<3> 4.2G 11.2C 11.2F
FBD_CMD<4> 4.2G 11.1E 11.1G
FBD_CMD<4> 4.2G 11.1E 11.1G
FBD_CMD<5> 4.2G 11.1E 11.1G
FBD_CMD<5> 4.2G 11.1E 11.1G
FBD_CMD<6> 4.3G 11.1E 11.1G
FBD_CMD<6> 4.3G 11.1E 11.1G
FBD_CMD<8> 4.3G 11.1C 11.1F
FBD_CMD<8> 4.3G 11.1C 11.1F
FBD_CMD<9> 4.3G 11.1C 11.1F
FBD_CMD<9> 4.3G 11.1C 11.1F
FBD_CMD<10> 4.3G 11.1C 11.1F
FBD_CMD<10> 4.3G 11.1C 11.1F
FBD_CMD<11> 4.3G 11.1C 11.1F
FBD_CMD<11> 4.3G 11.1C 11.1F
FBD_CMD<12> 4.3G 11.2C 11.2F
FBD_CMD<12> 4.3G 11.2C 11.2F
FBD_CMD<13> 4.3G 11.1E 11.2G
FBD_CMD<13> 4.3G 11.1E 11.2G
FBD_CMD<14> 4.3G 11.2C 11.2F
FBD_CMD<14> 4.3G 11.2C 11.2F
FBD_CMD<15> 4.3G 11.2C 11.2F
FBD_CMD<15> 4.3G 11.2C 11.2F
FBD_CMD<16> 4.3G 11.1C 11.1F
FBD_CMD<16> 4.3G 11.1C 11.1F
FBD_CMD<17> 4.3G 11.1C 11.1F
FBD_CMD<17> 4.3G 11.1C 11.1F
FBD_CMD<18> 4.3G 11.2C 11.2F
FBD_CMD<18> 4.3G 11.2C 11.2F
FBD_CMD<19> 4.3G 11.1C 11.1F
FBD_CMD<19> 4.3G 11.1C 11.1F
FBD_CMD<20> 4.3G 11.1C 11.1F
FBD_CMD<20> 4.3G 11.1C 11.1F
FBD_CMD<21> 4.3G 11.1C 11.1F
FBD_CMD<21> 4.3G 11.1C 11.1F
FBD_CMD<22> 4.3G 11.1B 11.2G
FBD_CMD<22> 4.3G 11.1B 11.2G
FBD_CMD<23> 4.3G 11.1C 11.1F
FBD_CMD<23> 4.3G 11.1C 11.1F
FBD_CMD<24> 4.3G 11.1B 11.2G
FBD_CMD<24> 4.3G 11.1B 11.2G
FBD_CMD<25> 4.3G 11.1C 11.1F
FBD_CMD<25> 4.3G 11.1C 11.1F
FBD_CMD<27> 4.3G 11.2C 11.2F
FBD_CMD<27> 4.3G 11.2C 11.2F
FBD_CMD_SEND0 11.2C
FBD_CMD_SEND1 11.2F
FBD_D<0> 4.1F 11.4C
FBD_D<63..0> 4.3F 11.5E
FBD_D<1> 4.1F 11.4C
FBD_D<2> 4.1F 11.4C
FBD_D<3> 4.1F 11.4C
FBD_D<4> 4.1F 11.4C
FBD_D<5> 4.1F 11.4C
FBD_D<6> 4.1F 11.4C
FBD_D<7> 4.1F 11.4C
FBD_D<8> 4.1F 11.4D
FBD_D<9> 4.2F 11.4D
FBD_D<10> 4.2F 11.4D
FBD_D<11> 4.2F 11.4D
FBD_D<12> 4.2F 11.4D
FBD_D<13> 4.2F 11.4D
FBD_D<14> 4.2F 11.4D
FBD_D<15> 4.2F 11.4D
FBD_D<16> 4.2F 11.4D
FBD_D<17> 4.2F 11.4D
FBD_D<18> 4.2F 11.4D
FBD_D<19> 4.2F 11.4D
FBD_D<20> 4.2F 11.4D
FBD_D<21> 4.2F 11.4D
FBD_D<22> 4.2F 11.4D
FBD_D<23> 4.2F 11.4D
FBD_D<24> 4.2F 11.4E
FBD_D<25> 4.2F 11.4E
FBD_D<26> 4.2F 11.4E
FBD_D<27> 4.2F 11.4E
FBD_D<28> 4.2F 11.4E
FBD_D<29> 4.2F 11.4E
FBD_D<30> 4.2F 11.4E
FBD_D<31> 4.2F 11.4E
FBD_D<32> 4.2F 11.5C
FBD_D<33> 4.2F 11.5C
FBD_D<34> 4.2F 11.5C
FBD_D<35> 4.2F 11.5C
FBD_D<36> 4.2F 11.5C
FBD_D<37> 4.2F 11.5C
FBD_D<38> 4.2F 11.5C
FBD_D<39> 4.3F 11.5C
FBD_D<40> 4.3F 11.5D
FBD_D<41> 4.3F 11.5D
FBD_D<42> 4.3F 11.5D
FBD_D<43> 4.3F 11.5D
FBD_D<44> 4.3F 11.5D
FBD_D<45> 4.3F 11.5D
FBD_D<46> 4.3F 11.5D
FBD_D<47> 4.3F 11.5D
FBD_D<48> 4.3F 11.5D
FBD_D<49> 4.3F 11.5D
FBD_D<50> 4.3F 11.5D
FBD_D<51> 4.3F 11.5D
FBD_D<52> 4.3F 11.5D
FBD_D<53> 4.3F 11.5D
FBD_D<54> 4.3F 11.5D
FBD_D<55> 4.3F 11.5D
FBD_D<56> 4.3F 11.5E
FBD_D<57> 4.3F 11.5E
FBD_D<58> 4.3F 11.5E
FBD_D<59> 4.3F 11.5E
FBD_D<60> 4.3F 11.5E
FBD_D<61> 4.3F 11.5E
FBD_D<62> 4.3F 11.5E
FBD_D<63> 4.3F 11.5E
FBD_DQM<0> 4.3F 11.4B 11.4C
FBD_DQM<0> 4.3F 11.4B 11.4C
FBD_DQM<7..0> 4.4F 11.4B 11.5E
FBD_DQM<1> 4.3F 11.4B 11.4D
FBD_DQM<1> 4.3F 11.4B 11.4D
FBD_DQM<2> 4.3F 11.4B 11.4D
FBD_DQM<2> 4.3F 11.4B 11.4D
FBD_DQM<3> 4.4F 11.4B 11.4E
FBD_DQM<3> 4.4F 11.4B 11.4E
FBD_DQM<4> 4.4F 11.4B 11.5C
FBD_DQM<4> 4.4F 11.4B 11.5C
FBD_DQM<5> 4.4F 11.4B 11.5D
FBD_DQM<5> 4.4F 11.4B 11.5D
FBD_DQM<6> 4.4F 11.4B 11.5D
FBD_DQM<6> 4.4F 11.4B 11.5D
FBD_DQM<7> 4.4F 11.4B 11.5E
FBD_DQM<7> 4.4F 11.4B 11.5E
FBD_DQS_RN<0> 4.4F 11.4B 11.4C
FBD_DQS_RN<0> 4.4F 11.4B 11.4C
FBD_DQS_RN<7..0> 4.4F 11.5B 11.5E
FBD_DQS_RN<1> 4.4F 11.4B 11.4D
FBD_DQS_RN<1> 4.4F 11.4B 11.4D
FBD_DQS_RN<2> 4.4F 11.4B 11.4D
FBD_DQS_RN<2> 4.4F 11.4B 11.4D
FBD_DQS_RN<3> 4.4F 11.4B 11.4E
FBD_DQS_RN<3> 4.4F 11.4B 11.4E
FBD_DQS_RN<4> 4.4F 11.5B 11.5C
FBD_DQS_RN<4> 4.4F 11.5B 11.5C
FBD_DQS_RN<5> 4.4F 11.5B 11.5D
FBD_DQS_RN<5> 4.4F 11.5B 11.5D
FBD_DQS_RN<6> 4.4F 11.5B 11.5D
FBD_DQS_RN<6> 4.4F 11.5B 11.5D
FBD_DQS_RN<7> 4.4F 11.5B 11.5E
FBD_DQS_RN<7> 4.4F 11.5B 11.5E
FBD_DQS_WP<0> 4.4F 11.4C 11.5B
FBD_DQS_WP<0> 4.4F 11.4C 11.5B
FBD_DQS_WP<7..0> 4.4F 11.5B 11.5E
FBD_DQS_WP<1> 4.4F 11.4D 11.5B
FBD_DQS_WP<1> 4.4F 11.4D 11.5B
FBD_DQS_WP<2> 4.4F 11.4D 11.5B
FBD_DQS_WP<2> 4.4F 11.4D 11.5B
FBD_DQS_WP<3> 4.4F 11.4E 11.5B
FBD_DQS_WP<3> 4.4F 11.4E 11.5B
FBD_DQS_WP<4> 4.4F 11.5B 11.5C
FBD_DQS_WP<4> 4.4F 11.5B 11.5C
FBD_DQS_WP<5> 4.4F 11.5B 11.5D
FBD_DQS_WP<5> 4.4F 11.5B 11.5D
FBD_DQS_WP<6> 4.4F 11.5B 11.5D
FBD_DQS_WP<6> 4.4F 11.5B 11.5D
FBD_DQS_WP<7> 4.4F 11.5B 11.5E
FBD_DQS_WP<7> 4.4F 11.5B 11.5E
FBD_VREF0 11.3D> 13.4E<>
FBD_VREF1 11.3G> 13.4E<>
FBD_VREF2 11.3E> 13.4E<>
FBD_VREF3 11.3H> 13.4E<>
FBD_ZQ0 11.2B< 13.4E<>
FBD_ZQ1 11.2E< 13.4E<>
SNN_FBD0_NC1 11.2C
SNN_FBD1_NC1 11.2F
FBA_CLK0 3.4D> 5.2A< 13.1B>
FBA_CLK0* 3.4D> 5.2A< 13.1B>
FBA_CLK1 3.4D> 5.2D< 13.2B>
FBA_CLK1* 3.4D> 5.2D< 13.2B>
FBA_CMD<27..0> 3.3C 5.2B 5.2E
FBA_D<63..0> 3.3B 5.5E
FBA_DQM<7..0> 3.4B 5.4B 5.5E
FBA_DQS_RN<7..0> 3.4B 5.5B 5.5E
FBA_DQS_WP<7..0> 3.4B 5.5B 5.5E
FBA_VREF0 5.3D> 13.3B<>
FBA_VREF1 5.3G> 13.4B<>
FBA_VREF2 5.3E> 13.4B<>
FBA_VREF3 5.3H> 13.4B<>
FBA_ZQ0 5.2B< 13.4B<>
FBA_ZQ1 5.2E< 13.4B<>
FBB_CLK0 3.4H> 7.2A< 13.2B>
FBB_CLK0* 3.4H> 7.2A< 13.2B>
FBB_CLK1 3.4H> 7.2D< 13.2B>
FBB_CLK1* 3.4H> 7.2D< 13.2B>
FBB_CMD<27..0> 3.3G 7.2B 7.2E
FBB_D<63..0> 3.3F 7.5E
FBB_DQM<7..0> 3.4F 7.4B 7.5E
FBB_DQS_RN<7..0> 3.4F 7.5B 7.5E
FBB_DQS_WP<7..0> 3.4F 7.5B 7.5E
FBB_VREF0 7.3D> 13.4B<>
FBB_VREF1 7.3G> 13.4B<>
FBB_VREF2 7.3E> 13.4B<>
FBB_VREF3 7.3H> 13.4B<>
FBB_ZQ0 7.2B< 13.4B<>
FBB_ZQ1 7.2E< 13.4B<>
FBC_CLK0 4.4D> 9.2A< 13.1E>
FBC_CLK0* 4.4D> 9.2A< 13.1E>
FBC_CLK1 4.4D> 9.2D< 13.2E>
FBC_CLK1* 4.4D> 9.2D< 13.2E>
FBC_CMD<27..0> 4.3C 9.2B 9.2E
FBC_D<63..0> 4.3B 9.5E
FBC_DQM<7..0> 4.4B 9.4B 9.5E
FBC_DQS_RN<7..0> 4.4B 9.5B 9.5E
FBC_DQS_WP<7..0> 4.4B 9.5B 9.5E
FBC_VREF0 9.3D> 13.3E<>
FBC_VREF1 9.3G> 13.4E<>
FBC_VREF2 9.3E> 13.4E<>
FBC_VREF3 9.3H> 13.4E<>
FBC_ZQ0 9.2B< 13.4E<>
FBC_ZQ1 9.2E< 13.4E<>
FBD_CLK0 4.4H> 11.2A< 13.2E>
FBD_CLK0* 4.4H> 11.2A< 13.2E>
FBD_CLK1 4.4H> 11.2D< 13.2E>
FBD_CLK1* 4.4H> 11.2D< 13.2E>
FBD_CMD<27..0> 4.3G 11.2C 11.2F
FBD_D<63..0> 4.3F 11.5E
FBD_DQM<7..0> 4.4F 11.4B 11.5E
FBD_DQS_RN<7..0> 4.4F 11.5B 11.5E
FBD_DQS_WP<7..0> 4.4F 11.5B 11.5E
FBD_VREF0 11.3D> 13.4E<>
FBD_VREF1 11.3G> 13.4E<>
FBD_VREF2 11.3E> 13.4E<>
FBD_VREF3 11.3H> 13.4E<>
FBD_ZQ0 11.2B< 13.4E<>
FBD_ZQ1 11.2E< 13.4E<>
FB_PLLAVDD0 3.5D> 13.3B<>
FB_PLLAVDD1 4.5D> 13.3E<>
FB_VREF 3.5A> 13.3B<>
DACA_BLUE 14.3C 14.5A<> 14.5D
DACA_BLUE 14.3C 14.5A<> 14.5D
DACA_BLUE 14.3C 14.5A<> 14.5D
DACA_BLUE_C 14.3F> 14.5A<> 16.3G<
DACA_BLUE_C 14.3F> 14.5A<> 16.3G<
DACA_GREEN 14.3C 14.4D 14.5A<>
DACA_GREEN 14.3C 14.4D 14.5A<>
DACA_GREEN 14.3C 14.4D 14.5A<>
DACA_GREEN_C 14.3F> 14.5A<> 16.3G<
DACA_GREEN_C 14.3F> 14.5A<> 16.3G<
DACA_HSYNC 14.3C 14.5A<>
DACA_HSYNC 14.3C 14.5A<>
DACA_HS_BUF 14.3D 14.5A<>
DACA_HS_BUF 14.3D 14.5A<>
DACA_HS_BUF_R 14.3E 14.5A<>
DACA_HS_BUF_R 14.3E 14.5A<>
DACA_HS_C 14.2G> 14.2G> 14.5A<>
16.3G<
DACA_HS_C 14.2G> 14.2G> 14.5A<>
16.3G<
DACA_HS_C 14.2G> 14.2G> 14.5A<>
16.3G<
DACA_RED 14.3C 14.3D 14.5A<>
DACA_RED 14.3C 14.3D 14.5A<>
DACA_RED 14.3C 14.3D 14.5A<>
DACA_RED_C 14.3F> 14.5A<> 16.3G<
DACA_RED_C 14.3F> 14.5A<> 16.3G<
DACA_RSET 14.3B 14.5A<
DACA_RSET 14.3B 14.5A<
DACA_VDD 14.2B> 14.4A< 15.2A<
DACA_VDD 14.2B> 14.4A< 15.2A<
DACA_VREF 14.3B 14.5A<
DACA_VREF 14.3B 14.5A<
DACA_VSYNC 14.3C 14.5A<>
DACA_VSYNC 14.3C 14.5A<>
DACA_VS_BUF 14.2D 14.5A<>
DACA_VS_BUF 14.2D 14.5A<>
DACA_VS_BUF_R 14.2E 14.5A<>
DACA_VS_BUF_R 14.2E 14.5A<>
DACA_VS_C 14.2G> 14.2G> 14.5A<>
16.3G<
DACA_VS_C 14.2G> 14.2G> 14.5A<>
16.3G<
DACA_VS_C 14.2G> 14.2G> 14.5A<>
16.3G<
I2CA_SCL 14.3C
I2CA_SCL_C 14.1G> 14.1G> 16.3G<
I2CA_SCL_C 14.1G> 14.1G> 16.3G<
I2CA_SCL_T 14.1D
I2CA_SDA 14.3C
I2CA_SDA_C 14.1G> 14.1G> 16.3G<
I2CA_SDA_C 14.1G> 14.1G> 16.3G<
I2CA_SDA_T 14.1D
SNN_A_MON_ID0 14.3H
SNN_A_MON_ID2 14.4F
DACA_VDD 14.2B> 14.4A< 15.2A<
DACC_BLUE 15.3C 15.5A<> 15.5D
DACC_BLUE 15.3C 15.5A<> 15.5D
DACC_BLUE 15.3C 15.5A<> 15.5D
DACC_BLUE_C 15.3F> 15.5A<> 17.3G<
DACC_BLUE_C 15.3F> 15.5A<> 17.3G<
DACC_GREEN 15.3C 15.4D 15.5A<>
DACC_GREEN 15.3C 15.4D 15.5A<>
DACC_GREEN 15.3C 15.4D 15.5A<>
DACC_GREEN_C 15.3F> 15.5A<> 17.3G<
DACC_GREEN_C 15.3F> 15.5A<> 17.3G<
DACC_HSYNC 15.3C 15.5A<>
DACC_HSYNC 15.3C 15.5A<>
DACC_HS_BUF 15.2D 15.5A<>
DACC_HS_BUF 15.2D 15.5A<>
DACC_HS_BUF_R 15.2E 15.5A<>
DACC_HS_BUF_R 15.2E 15.5A<>
DACC_HS_C 15.2G> 15.2G> 15.5A<>
17.3G<
DACC_HS_C 15.2G> 15.2G> 15.5A<>
17.3G<
DACC_HS_C 15.2G> 15.2G> 15.5A<>
17.3G<
DACC_RED 15.3C 15.3D 15.5A<>
DACC_RED 15.3C 15.3D 15.5A<>
DACC_RED 15.3C 15.3D 15.5A<>
DACC_RED_C 15.3F> 15.5A<> 17.3G<
DACC_RED_C 15.3F> 15.5A<> 17.3G<
DACC_RSET 15.3B 15.5A<
DACC_RSET 15.3B 15.5A<
DACC_VREF 15.2B 15.4A<
1
2
3
4
5
ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
BA
C
PAGE DETAIL
www.vinafix.vn
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
<edit here to insert page detail>
E
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
ID
NAME
G
600-10562-base-000 A
<ENGINEER>
PAGE
DATE
30-DEC-2008
HFD
Page 38
A B
C D
E
F
G
H
DACC_VREF 15.2B 15.4A<
DACC_VSYNC 15.3C 15.5A<>
DACC_VSYNC 15.3C 15.5A<>
DACC_VS_BUF 15.2D 15.5A<>
DACC_VS_BUF 15.2D 15.5A<>
DACC_VS_BUF_R 15.2E 15.5A<>
DACC_VS_BUF_R 15.2E 15.5A<>
DACC_VS_C 15.2G> 15.2G> 15.5A<>
1
17.3G<
DACC_VS_C 15.2G> 15.2G> 15.5A<>
17.3G<
DACC_VS_C 15.2G> 15.2G> 15.5A<>
17.3G<
I2CB_SCL 15.2C
I2CB_SCL_C 15.1G> 15.1G> 17.3G<
I2CB_SCL_C 15.1G> 15.1G> 17.3G<
I2CB_SCL_T 15.1D
I2CB_SDA 15.2C
I2CB_SDA_C 15.1G> 15.1G> 17.3G<
I2CB_SDA_C 15.1G> 15.1G> 17.3G<
I2CB_SDA_T 15.1D
SNN_C_MON_ID0 15.3H
SNN_C_MON_ID2 15.4F
DACA_BLUE_C 14.3F> 14.5A<> 16.3G<
DACA_GREEN_C 14.3F> 14.5A<> 16.3G<
DACA_HS_C 14.2G> 14.2G> 14.5A<>
16.3G<
DACA_RED_C 14.3F> 14.5A<> 16.3G<
DACA_VS_C 14.2G> 14.2G> 14.5A<>
2
16.3G<
GPIO0_DVI_A_HPD 16.4C> 21.3D<
GPIO0_DVI_A_HPD_C 16.3G
GPIO0_DVI_A_HPD_R 16.4E
I2CA_SCL_C 14.1G> 14.1G> 16.3G<
I2CA_SDA_C 14.1G> 14.1G> 16.3G<
IFPABCD_PLLVDD 16.3B< 17.2B>
IFPAB_IOVDD 16.1G<> 16.3B
IFPAB_IOVDD 16.1G<> 16.3B
IFPAB_RSET 16.1G<> 16.2B
IFPAB_RSET 16.1G<> 16.2B
IFPAB_TXC 16.2D
IFPAB_TXC* 16.2D
IFPAB_TXD0 16.2D
IFPAB_TXD0* 16.2D
IFPAB_TXD1 16.3D
IFPAB_TXD1* 16.2D
IFPAB_TXD2 16.3D
IFPAB_TXD2* 16.3D
IFPAB_TXD4 16.3D
IFPAB_TXD4* 16.3D
IFPAB_TXD5 16.3D
3
IFPAB_TXD5* 16.3D
IFPAB_TXD6 16.3D
IFPAB_TXD6* 16.3D
SNN_IFPAB_ATXD3 16.3D
SNN_IFPAB_ATXD3* 16.3D
SNN_IFPAB_BTXC 16.3D
SNN_IFPAB_BTXC* 16.3D
SNN_IFPAB_TXD7 16.3D
SNN_IFPAB_TXD7* 16.3D
DACC_BLUE_C 15.3F> 15.5A<> 17.3G<
DACC_GREEN_C 15.3F> 15.5A<> 17.3G<
DACC_HS_C 15.2G> 15.2G> 15.5A<>
17.3G<
DACC_RED_C 15.3F> 15.5A<> 17.3G<
DACC_VS_C 15.2G> 15.2G> 15.5A<>
17.3G<
GPIO1_DVI_C_HPD 17.4D> 21.3D<
GPIO1_DVI_C_HPD_C 17.3G
GPIO1_DVI_C_HPD_R 17.4E
HDMI_PD 17.1F
HDMI_PD_EN 17.2F
I2CB_SCL_C 15.1G> 15.1G> 17.3G<
4
I2CB_SDA_C 15.1G> 15.1G> 17.3G<
IFPABCD_PLLVDD 16.3B< 17.2B>
IFPCD_IOVDD 17.1G<> 17.3B
IFPCD_IOVDD 17.1G<> 17.3B
IFPCD_PLLVDD 17.1G<>
IFPCD_RSET 17.1G<> 17.2B
IFPCD_RSET 17.1G<> 17.2B
IFPCD_TXC 17.1E 17.2E
IFPCD_TXC 17.1E 17.2E
IFPCD_TXC* 17.1E 17.2E
IFPCD_TXC* 17.1E 17.2E
IFPCD_TXD0 17.1E 17.2E
IFPCD_TXD0 17.1E 17.2E
IFPCD_TXD0* 17.1E 17.2E
IFPCD_TXD0* 17.1E 17.2E
IFPCD_TXD1 17.1E 17.2E
IFPCD_TXD1 17.1E 17.2E
IFPCD_TXD1* 17.1E 17.2E
IFPCD_TXD1* 17.1E 17.2E
IFPCD_TXD2 17.1E 17.2E
IFPCD_TXD2 17.1E 17.2E
IFPCD_TXD2* 17.1E 17.2E
5
IFPCD_TXD2* 17.1E 17.2E
IFPCD_TXD4 17.1E 17.2G 17.3E
IFPCD_TXD4 17.1E 17.2G 17.3E
IFPCD_TXD4 17.1E 17.2G 17.3E
IFPCD_TXD4* 17.1E 17.2G 17.3E
IFPCD_TXD4* 17.1E 17.2G 17.3E
IFPCD_TXD4* 17.1E 17.2G 17.3E
IFPCD_TXD5 17.1E 17.3E 17.3G
IFPCD_TXD5 17.1E 17.3E 17.3G
IFPCD_TXD5 17.1E 17.3E 17.3G
IFPCD_TXD5* 17.1E 17.3E 17.3G
IFPCD_TXD5* 17.1E 17.3E 17.3G
IFPCD_TXD5* 17.1E 17.3E 17.3G
IFPCD_TXD6 17.1E 17.3E 17.3G
IFPCD_TXD6 17.1E 17.3E 17.3G
IFPCD_TXD6 17.1E 17.3E 17.3G
IFPCD_TXD6* 17.1E 17.3E 17.3G
IFPCD_TXD6* 17.1E 17.3E 17.3G
IFPCD_TXD6* 17.1E 17.3E 17.3G
IFPC_TXC 17.2C
IFPC_TXC* 17.2C
IFPC_TXD0 17.2C
IFPC_TXD0* 17.2C
IFPC_TXD1 17.2C
IFPC_TXD1* 17.2C
IFPC_TXD2 17.2C
IFPC_TXD2* 17.2C
IFPD_TXD4 17.3C
IFPD_TXD4* 17.3C
IFPD_TXD5 17.3C
IFPD_TXD5* 17.3C
IFPD_TXD6 17.3C
IFPD_TXD6* 17.3C
SNN_IFPC_AUX 17.2C
SNN_IFPC_AUX* 17.2C
SNN_IFPD_AUX 17.3C
SNN_IFPD_AUX* 17.3C
SNN_IFPD_L3 17.3C
SNN_IFPD_L3* 17.3C
SNN_IFPEF_RSET 18.3B
SNN_IFPE_AUX 18.3D
SNN_IFPE_AUX* 18.3D
SNN_IFPE_L0 18.3D
SNN_IFPE_L0* 18.3D
SNN_IFPE_L1 18.3D
SNN_IFPE_L1* 18.3D
SNN_IFPE_L2 18.3D
SNN_IFPE_L2* 18.3D
SNN_IFPE_TXC 18.3D
SNN_IFPE_TXC* 18.3D
SNN_IFPF_AUX 18.4D
SNN_IFPF_AUX* 18.4D
SNN_IFPF_L0 18.4D
SNN_IFPF_L0* 18.4D
SNN_IFPF_L1 18.4D
SNN_IFPF_L1* 18.4D
SNN_IFPF_L2 18.4D
SNN_IFPF_L2* 18.4D
SNN_IFPF_L3 18.4D
SNN_IFPF_L3* 18.4D
SNN_DACB_COUT 19.3C
SNN_DACB_CSYNC 19.3C
SNN_DACB_PBOUT 19.3C
SNN_DACB_RSET 19.3B
SNN_DACB_VREF 19.3B
SNN_DACB_YOUT 19.3C
GPIO11_SLI_SYNC1 20.2E<> 21.3D>
GPIO22_SWAPRDY_A 20.2E<> 21.4E>
MIOA_CAL_PD_VDDQ 20.2C 20.5A<
MIOA_CAL_PD_VDDQ 20.2C 20.5A<
MIOA_CAL_PU_GND 20.2C 20.5A<
MIOA_CAL_PU_GND 20.2C 20.5A<
MIOA_CLKIN 20.2E 20.5A<
MIOA_CLKIN 20.2E 20.5A<
MIOA_CLKOUT 20.2E 20.5A<
MIOA_CLKOUT 20.2E 20.5A<
MIOA_D0 20.1E 20.1F
MIOA_D0 20.1E 20.1F
MIOA_D1 20.1E 20.1F
MIOA_D1 20.1E 20.1F
MIOA_D2 20.1E 20.1F
MIOA_D2 20.1E 20.1F
MIOA_D3 20.1E 20.1F
MIOA_D3 20.1E 20.1F
MIOA_D4 20.1E 20.1F
MIOA_D4 20.1E 20.1F
MIOA_D5 20.1E 20.1F
MIOA_D5 20.1E 20.1F
MIOA_D6 20.2E 20.2F
MIOA_D6 20.2E 20.2F
MIOA_D7 20.2E 20.2F
MIOA_D7 20.2E 20.2F
MIOA_D8 20.2E 20.2F
MIOA_D8 20.2E 20.2F
MIOA_D9 20.2E 20.2F
MIOA_D9 20.2E 20.2F
MIOA_D10 20.2E 20.2F
MIOA_D10 20.2E 20.2F
MIOA_D11 20.2E 20.2F
MIOA_D11 20.2E 20.2F
MIOA_D12 20.2E 20.2F
MIOA_D12 20.2E 20.2F
MIOA_D13 20.2E 20.2F
MIOA_D13 20.2E 20.2F
MIOA_D14 20.2E 20.2F
MIOA_D14 20.2E 20.2F
MIOA_DE 20.2E 20.5A<
MIOA_DE 20.2E 20.5A<
MIOA_VREF 20.2C 20.5A<
MIOA_VREF 20.2C 20.5A<
MIOB_CLKIN 20.4E
MIOB_D15_STRAP0 20.4E> 22.3A<
MIOB_D16_STRAP1 20.4E> 22.4A<
MIOB_D17_STRAP2 20.4E> 22.5A<
SNN_MIOA_CLKOUT* 20.2E
SNN_MIOA_D12 20.2E
SNN_MIOA_D13 20.2E
SNN_MIOA_D14 20.2E
SNN_MIOB_CAL_PD_VDDQ 20.4C
SNN_MIOB_CAL_PU_GND 20.4C
SNN_MIOB_CLKOUT 20.4E
SNN_MIOB_CLKOUT* 20.4E
SNN_MIOB_CTL3 20.4E
SNN_MIOB_D0 20.3E
SNN_MIOB_D1 20.3E
SNN_MIOB_D2 20.3E
SNN_MIOB_D3 20.3E
SNN_MIOB_D4 20.3E
SNN_MIOB_D5 20.3E
SNN_MIOB_D6 20.3E
SNN_MIOB_D7 20.3E
SNN_MIOB_D8 20.3E
SNN_MIOB_D9 20.3E
SNN_MIOB_D10 20.3E
SNN_MIOB_D11 20.4E
SNN_MIOB_D12 20.4E
SNN_MIOB_D13 20.4E
SNN_MIOB_D14 20.4E
SNN_MIOB_DE 20.4E
SNN_MIOB_HSYNC 20.4E
SNN_MIOB_VREF 20.4C
SNN_MIOB_VSYNC 20.4E
GPIO0_DVI_A_HPD 16.4C> 21.3D<
GPIO1_DVI_C_HPD 17.4D> 21.3D<
GPIO4_FAN_TACH 21.3D> 31.2C>
GPIO5_VSEL0 21.3D> 29.4C<
GPIO6_NVVDD_PHASE 21.3D> 29.2A<
GPIO8_GPU_SLOW* 21.3D> 25.2C<
GPIO9_FAN_PWM 21.3D> 31.2C<
GPIO11_SLI_SYNC1 20.2E<> 21.3D>
GPIO22_SWAPRDY_A 20.2E<> 21.4E>
GPU_PLLVDD 21.1G< 21.4F
GPU_PLLVDD 21.1G< 21.4F
HDA_RST* 21.1A
I2CC_SCL 21.2C
I2CC_SCL_R 21.3E>
I2CC_SDA 21.3C
I2CC_SDA_R 21.3E>
I2CH_SCL 21.2C 21.2F
I2CH_SCL 21.2C 21.2F
I2CH_SDA 21.2C 21.2F
I2CH_SDA 21.2C 21.2F
I2CH_SDA_R 21.2F
I2CS_SCL 21.2C
I2CS_SDA 21.2C
JTAG_TCLK 2.1F> 2.1F> 21.3A<
JTAG_TDI 2.1F> 2.1F> 21.3A<
JTAG_TDO 2.1F< 2.1F< 21.3A>
JTAG_TMS 2.1F> 2.1F> 21.3A<
JTAG_TRST* 2.1F> 2.1F> 21.3A<
PEX_SMCLK 2.1C> 21.2E<
PEX_SMDAT 2.1C> 21.2E<
ROM_CS* 21.1C
ROM_SCLK 21.1D> 22.3A<
ROM_SI 21.1D> 22.1A<
ROM_SO 21.1D> 22.2A<
SNN_BBIASN 21.1A
SNN_BBIASP 21.1A
SNN_BUFRST* 21.2C
SNN_GPIO2 21.3C
SNN_GPIO3 21.3C
SNN_GPIO7 21.3C
SNN_GPIO10 21.3C
SNN_GPIO12 21.3C
SNN_GPIO13 21.3C
SNN_GPIO14 21.3C
SNN_GPIO15 21.3C
SNN_GPIO16 21.3C
SNN_GPIO17 21.3C
SNN_GPIO18 21.3C
SNN_GPIO19 21.3C
SNN_GPIO20 21.3C
SNN_GPIO21 21.3C
SNN_GPIO23_STEREO 21.4C
SNN_HDA_SDI 21.1A
SNN_HDA_SDO 21.2A
SNN_HDA_SYNC 21.2A
SNN_HDSA_BCLK 21.1A
SNN_I2CD_SCL 21.3C
SNN_I2CD_SDA 21.3C
SNN_I2CE_SCL 21.3C
SNN_I2CE_SDA 21.3C
SNN_PGOOD_OUT* 21.2C
SNN_THERMDN 21.3A
SNN_THERMDP 21.3A
SPDIF 21.2D< 25.1G< 25.2H>
STRAP_CALPD_MIOB 21.2A
STRAP_CALPD_MISC 21.2A
XTALIN 21.1G< 21.5F
XTALIN 21.1G< 21.5F
XTALOUT 21.1G< 21.5G
XTALOUT 21.1G< 21.5G
XTALOUTBUFF 21.1G< 21.4H
XTALOUTBUFF 21.1G< 21.4H
XTALSSIN 21.1G< 21.4F
XTALSSIN 21.1G< 21.4F
MIOB_D15_STRAP0 20.4E> 22.3A<
MIOB_D16_STRAP1 20.4E> 22.4A<
MIOB_D17_STRAP2 20.4E> 22.5A<
ROM_SCLK 21.1D> 22.3A<
ROM_SI 21.1D> 22.1A<
ROM_SO 21.1D> 22.2A<
SNN_NC<1> 22.1G
SNN_NC<2> 22.1G
SNN_NC<3> 22.1G
SNN_NC<4> 22.1G
SNN_NC<5> 22.1G
SNN_NC<6> 22.1G
SNN_NC<7> 22.1G
SNN_NC<8> 22.1G
SNN_NC<9> 22.1G
SNN_NC<10> 22.1G
SNN_NC<11> 22.1G
SNN_NC<12> 22.1G
SNN_NC<13> 22.1G
SNN_NC<14> 22.1G
SNN_NC<15> 22.1G
SNN_NC<16> 22.1G
SNN_NC<17> 22.1G
SNN_NC<18> 22.1G
SNN_NC<19> 22.1G
SNN_NC<20> 22.1G
SNN_NC<21> 22.2G
SNN_NC<22> 22.2G
SNN_NC<23> 22.2G
SNN_NC<24> 22.2G
SNN_NC<25> 22.2G
SNN_NC<26> 22.2G
SNN_NC<27> 22.2G
SNN_NC<28> 22.2G
SNN_NC<29> 22.2G
SNN_NC<30> 22.2G
SNN_NC<31> 22.2G
SNN_NC<32> 22.2G
SNN_NC<33> 22.2G
SNN_NC<34> 22.2G
SNN_NC<35> 22.2G
SNN_NC<36> 22.2G
SNN_NC<37> 22.2G
SNN_NC<38> 22.2G
SNN_NC<39> 22.2G
SNN_NC<40> 22.2G
SNN_NC<41> 22.2G
SNN_NC<42> 22.2G
SNN_NC<43> 22.2G
SNN_NC<44> 22.2G
SNN_NC<45> 22.2G
SNN_NC<46> 22.2G
SNN_NC<47> 22.2G
SNN_NC<48> 22.2G
SNN_NC<49> 22.2G
SNN_NC<50> 22.2G
SNN_NC<51> 22.3G
SNN_NC<52> 22.3G
SNN_NC<53> 22.3G
SNN_NC<54> 22.3G
SNN_NC<55> 22.3G
SNN_NC<56> 22.3G
SNN_NC<57> 22.3G
SNN_NC<58> 22.3G
SNN_NC<59> 22.3G
SNN_NC<60> 22.3G
SNN_NC<61> 22.3G
SNN_NC<62> 22.3G
SNN_NC<63> 22.3G
SNN_NC<64> 22.3G
SNN_NC<65> 22.3G
SNN_NC<66> 22.3G
SNN_NC<67> 22.3G
SNN_NC<68> 22.3G
SNN_NC<69> 22.3G
SNN_NC<70> 22.3G
SNN_NC<71> 22.3G
SNN_NC<72> 22.3G
SNN_NC<73> 22.3G
SNN_NC<74> 22.3G
SNN_NC<75> 22.3G
3V3_TMDS_IOVDD_EN 25.4B
GPIO8_GPU_SLOW* 21.3D> 25.2C<
NVVDD_EN 25.3D> 29.3A<
PEX_RST* 2.2C> 2.4G> 25.3A<
PEX_RST_R* 25.3A
SPDIF 21.2D< 25.1G< 25.2H>
SPDIF 21.2D< 25.1G< 25.2H>
SPDIF_GND 25.2E
SPDIF_IN 25.1G< 25.2E
SPDIF_IN 25.1G< 25.2E
SPDIF_IN_C 25.1G< 25.3F
SPDIF_IN_C 25.1G< 25.3F
SPDIF_IN_COMP2_D 25.1G< 25.3G
SPDIF_IN_COMP2_D 25.1G< 25.3G
SPDIF_IN_COMP2_Q 25.1G< 25.3H
SPDIF_IN_COMP2_Q 25.1G< 25.3H
SPDIF_IN_R 25.1G< 25.3F
SPDIF_IN_R 25.1G< 25.3F
THERM_N_EN1 25.2A
THERM_N_EN1_R 25.2B
THERM_N_EN2 25.2C
THERM_N_EN3 25.2B
THERM_N_EN3_R1 25.2C
THERM_N_EN3_R2 25.3C
12V 26.1G
PS_1V8_ADJ 27.4F
PS_2V5_ADJ 27.2D
PS_2V5_VDD 27.2D
PS_5V_ADJ 27.4B
SNN_2V5_NC 27.2D
SNN_2V5_PGOOD 27.2D
FBVDDQ 28.1G
FBVDDQ_SENSE 4.5H> 28.4H<
FBVDDQ_SENSE_R 28.1G< 28.4F
FBVDDQ_SENSE_R 28.1G< 28.4F
PEX_VDD 28.1G
PS_1V1_CP 28.1G< 28.3B
PS_1V1_CP 28.1G< 28.3B
PS_1V1_DR 28.1G< 28.3C
PS_1V1_DR 28.1G< 28.3C
PS_1V1_FB 28.1G< 28.3C
PS_1V1_FB 28.1G< 28.3C
PS_FBVDDQ_FS 28.2G< 28.3C
PS_FBVDDQ_FS 28.2G< 28.3C
PS_FB_BOOT 28.1G< 28.3D
PS_FB_BOOT 28.1G< 28.3D
PS_FB_COMP 28.1G< 28.3D
PS_FB_COMP 28.1G< 28.3D
PS_FB_EN 28.5B
PS_FB_EN* 28.5C
PS_FB_FB 28.1G< 28.3D
PS_FB_FB 28.1G< 28.3D
PS_FB_LGATE 28.1G< 28.3D
PS_FB_LGATE 28.1G< 28.3D
PS_FB_PHASE 28.1G< 28.3E
PS_FB_PHASE 28.1G< 28.3E
PS_FB_PVCC5 28.1G< 28.2D
PS_FB_PVCC5 28.1G< 28.2D
PS_FB_RBOT 28.1G<
PS_FB_RC 28.1G< 28.4E
PS_FB_RC 28.1G< 28.4E
PS_FB_RC_CP 28.3D
PS_FB_SNUB 28.1G< 28.3F
PS_FB_SNUB 28.1G< 28.3F
PS_FB_UGATE 28.1G< 28.3D
PS_FB_UGATE 28.1G< 28.3D
PS_FB_UGATE_R 28.1G< 28.2E
PS_FB_UGATE_R 28.1G< 28.2E
PS_FB_VCC5 28.1G< 28.2C
PS_FB_VCC5 28.1G< 28.2C
PS_FB_VCC12 28.2D
GPIO5_VSEL0 21.3D> 29.4C<
GPIO6_NVVDD_PHASE 21.3D> 29.2A<
GPIO6_NVVDD_PHASE_R 29.2A
NVVDD 29.1A
NVVDD_EN 25.3D> 29.3A<
NVVDD_RBOT1 29.4D
NVVDD_SENSE_GPU 2.4E> 2.5G> 29.4G<
NVVDD_VSEL0 29.4D
PS1_NVVDD_FS 29.1F< 29.2B
PS1_NVVDD_FS 29.1F< 29.2B
PS1_NVVDD_SS 29.1F< 29.2B
PS1_NVVDD_SS 29.1F< 29.2B
PS1_NVVDD_SUS_R 29.2B
PS_NVVDD_BOOT1 29.1F< 29.2C
PS_NVVDD_BOOT1 29.1F< 29.2C
PS_NVVDD_BOOT2 29.1G< 29.2C
PS_NVVDD_BOOT2 29.1G< 29.2C
PS_NVVDD_CP 29.1F< 29.2B
PS_NVVDD_CP 29.1F< 29.2B
PS_NVVDD_DRVH1 29.1F< 29.2C
PS_NVVDD_DRVH1 29.1F< 29.2C
PS_NVVDD_DRVH1_R 29.1D 29.1F<
PS_NVVDD_DRVH1_R 29.1D 29.1F<
PS_NVVDD_DRVH2 29.1G< 29.2C
PS_NVVDD_DRVH2 29.1G< 29.2C
PS_NVVDD_DRVH2_R 29.1G< 29.2D
PS_NVVDD_DRVH2_R 29.1G< 29.2D
PS_NVVDD_DRVL1 29.1F< 29.2C
PS_NVVDD_DRVL1 29.1F< 29.2C
PS_NVVDD_DRVL2 29.1G< 29.3C
PS_NVVDD_DRVL2 29.1G< 29.3C
PS_NVVDD_EN 29.5A
PS_NVVDD_EN* 29.4B
PS_NVVDD_EN_AND 29.4B
PS_NVVDD_FB 29.1F< 29.2B 29.4D
PS_NVVDD_FB 29.1F< 29.2B 29.4D
PS_NVVDD_FB 29.1F< 29.2B 29.4D
PS_NVVDD_OC 29.3C
PS_NVVDD_PH1 29.1F< 29.2C
PS_NVVDD_PH1 29.1F< 29.2C
PS_NVVDD_PH2 29.1G< 29.2C
PS_NVVDD_PH2 29.1G< 29.2C
PS_NVVDD_PVCC9 29.1G< 29.2B
PS_NVVDD_PVCC9 29.1G< 29.2B
PS_NVVDD_RC 29.1G< 29.4F
PS_NVVDD_RC 29.1G< 29.4F
PS_NVVDD_RC1 29.1G< 29.2E
PS_NVVDD_RC1 29.1G< 29.2E
PS_NVVDD_RC2 29.1G< 29.3E
PS_NVVDD_RC2 29.1G< 29.3E
PS_NVVDD_RC_CP 29.1F< 29.2A
PS_NVVDD_RC_CP 29.1F< 29.2A
PS_NVVDD_SUS 29.1F< 29.2B
PS_NVVDD_SUS 29.1F< 29.2B
PS_NVVDD_VCC 29.1G< 29.2C
PS_NVVDD_VCC 29.1G< 29.2C
PS_NVVDD_VCC9 29.1F< 29.2B
PS_NVVDD_VCC9 29.1F< 29.2B
PS_NVVDD_VSEN 29.1G< 29.4F
PS_NVVDD_VSEN 29.1G< 29.4F
SNN_NVVDD_NC1 29.3C
SNN_NVVDD_NC2 29.3C
SNN_NVVDD_NC3 29.3C
SNN_NVVDD_VREF 29.2B
GPIO4_FAN_TACH 21.3D> 31.2C>
GPIO9_FAN_ON 31.3E
GPIO9_FAN_PWM 21.3D> 31.2C<
GPIO9_FAN_PWM_R 31.3E
1
2
3
4
5
ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
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P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
<edit here to insert page detail>
E
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
ID
NAME
G
600-10562-base-000 A
<ENGINEER>
PAGE
DATE
30-DEC-2008
HFD
Page 39
A B
C D
E
F
G
H
1
2
3
4
5
Title: Cref Part
Report
Design: p562_a00
Date: Dec 24
11:33:24 2008
BKT1 [32.3F]
C1 [15.1F]
C2 [15.1F]
C3 [17.4F]
C4 [14.1F]
C5 [14.1F]
C6 [16.5F]
C7 [15.2F]
C8 [15.3F]
C9 [14.2F]
C10 [14.3F]
C11 [31.4D]
C12 [16.5E]
C13 [17.4E]
C14 [25.2F]
C15 [25.3F]
C16 [27.4B]
C17 [27.4C]
C18 [27.4C]
C19 [25.3G]
C20 [11.3E]
C21 [27.4A]
C22 [27.4A]
C23 [27.4G]
C24 [27.1D]
C25 [27.1C]
C26 [27.4F]
C27 [27.2C]
C28 [27.4E]
C29 [27.2F]
C30 [6.3C]
C31 [27.2E]
C32 [27.2E]
C33 [2.1A]
C34 [11.3G]
C35 [17.3A]
C36 [28.3F]
C37 [21.5H]
C38 [29.2E]
C39 [6.3E]
C40 [8.3C]
C41 [21.5F]
C42 [9.3E]
C43 [9.3G]
C44 [7.3E]
C45 [7.3G]
C46 [5.3E]
C47 [5.3G]
C48 [29.3E]
C49 [28.3H]
C50 [28.3B]
C51 [29.3G]
C53 [28.3A]
C54 [29.2E]
C55 [28.2C]
C56 [29.2H]
C57 [28.3H]
C58 [28.2B]
C59 [28.3F]
C60 [29.5A]
C61 [29.1E]
C62 [29.1E]
C63 [29.1E]
C65 [29.2G]
C66 [28.2F]
C67 [29.3E]
C68 [28.2F]
C69 [29.3G]
C70 [29.2G]
C71 [29.2H]
C72 [29.2E]
C73 [26.2C]
C74 [29.3H]
C75 [29.2E]
C76 [28.2F]
C77 [8.3E]
C78 [10.3C]
C79 [10.3E]
C80 [12.3C]
C81 [12.3E]
C505 [28.2F]
C506 [26.2D]
C507 [29.3D]
C508 [28.3G]
C509 [28.3G]
C511 [29.4A]
C512 [28.3E]
C513 [29.3B]
C514 [29.3D]
C516 [29.2G]
C517 [29.2E]
C519 [29.4F]
C520 [29.1C]
C521 [29.2A]
C522 [29.2B]
C523 [29.2A]
C524 [29.2B]
C525 [29.4D]
C526 [28.2D]
C527 [28.2C]
C528 [28.2D]
C530 [29.2A]
C531 [29.1D]
C532 [28.3E]
C533 [29.2D]
C535 [29.2G]
C536 [28.3D]
C537 [28.3C]
C538 [28.3D]
C539 [28.4F]
C541 [28.5B]
C542 [8.3E]
C543 [8.3E]
C544 [6.3C]
C545 [6.3E]
C546 [6.3C]
C547 [6.3E]
C548 [6.2C]
C549 [5.3C]
C550 [6.3C]
C551 [8.2C]
C552 [8.2E]
C553 [6.3E]
C554 [8.2E]
C555 [6.3C]
C556 [7.3F]
C557 [5.1A]
C558 [6.3E]
C559 [6.3C]
C560 [7.1D]
C561 [6.2E]
C562 [8.3E]
C563 [8.3E]
C564 [5.3F]
C565 [6.2E]
C566 [6.3E]
C567 [6.2E]
C568 [8.2E]
C569 [7.3H]
C570 [5.1D]
C571 [8.3E]
C572 [6.3E]
C573 [6.2C]
C574 [6.3C]
C575 [5.3B]
C576 [6.2E]
C577 [8.2E]
C578 [7.3E]
C579 [6.2C]
C580 [5.3E]
C581 [5.3H]
C582 [6.2C]
C583 [8.3E]
C584 [5.3D]
C585 [8.3C]
C586 [8.3C]
C587 [8.3C]
C588 [8.2C]
C589 [8.3C]
C590 [24.2D]
C591 [8.3C]
C592 [24.2D]
C593 [7.3C]
C594 [7.1A]
C595 [7.3D]
C596 [7.3B]
C597 [8.2C]
C598 [8.2C]
C599 [24.2D]
C600 [8.3C]
C601 [2.5C]
C602 [24.2D]
C603 [2.5C]
C604 [2.5C]
C605 [2.5C]
C606 [2.5C]
C607 [10.2E]
C608 [2.4C]
C609 [10.3E]
C610 [10.2E]
C611 [10.3E]
C612 [10.3E]
C613 [3.5A]
C614 [2.4C]
C617 [2.4C]
C618 [9.1D]
C619 [24.2F]
C620 [9.3H]
C621 [9.3E]
C622 [24.2D]
C623 [24.2F]
C624 [2.4C]
C625 [2.4C]
C626 [9.3F]
C627 [24.3F]
C628 [24.2F]
C629 [24.3E]
C630 [24.2E]
C631 [24.2F]
C632 [24.3E]
C633 [3.5E]
C634 [24.3F]
C635 [3.5D]
C636 [3.5D]
C637 [24.2E]
C638 [2.4C]
C639 [24.2A]
C640 [10.3E]
C641 [24.2A]
C642 [2.4C]
C644 [3.5D]
C645 [24.2A]
C646 [10.2E]
C647 [10.3E]
C648 [24.2D]
C649 [10.2E]
C650 [2.2F]
C651 [2.2F]
C652 [24.3A]
C653 [2.2E]
C654 [2.5F]
C656 [2.2E]
C657 [24.3A]
C658 [4.5D]
C659 [2.2E]
C660 [24.2A]
C661 [2.4C]
C662 [10.3E]
C664 [24.2A]
C665 [2.4C]
C666 [2.2E]
C667 [24.2A]
C668 [2.2E]
C670 [17.3B]
C671 [24.3A]
C674 [24.3A]
C675 [4.5E]
C676 [24.2A]
C677 [24.3A]
C678 [24.2D]
C679 [17.3A]
C680 [21.4D]
C681 [2.2E]
C682 [2.2E]
C683 [24.2A]
C684 [24.2A]
C685 [24.3A]
C686 [2.4C]
C687 [4.5D]
C688 [4.5D]
C689 [2.2E]
C690 [2.5F]
C692 [21.4F]
C693 [2.2F]
C694 [24.2A]
C695 [2.5E]
C696 [2.3C]
C698 [2.5E]
C699 [24.2A]
C700 [24.2A]
C701 [24.2E]
C702 [24.3A]
C703 [24.2A]
C704 [21.4F]
C705 [21.4E]
C706 [2.3C]
C708 [2.2F]
C709 [24.2A]
C710 [24.1F]
C711 [21.4E]
C712 [24.2A]
C714 [2.3C]
C715 [24.2A]
C716 [2.3E]
C718 [2.3F]
C719 [15.3A]
C720 [16.3C]
C721 [14.3A]
C722 [10.3C]
C723 [2.3F]
C724 [10.3C]
C726 [2.3C]
C727 [24.3F]
C728 [24.3F]
C729 [24.1F]
C734 [2.3C]
C735 [20.2C]
C736 [17.3B]
C737 [24.2F]
C738 [20.1B]
C739 [17.2B]
C740 [10.3C]
C741 [2.3C]
C742 [15.3A]
C743 [20.1B]
C744 [10.3C]
C745 [2.3C]
C746 [16.3B]
C747 [9.3B]
C748 [9.3C]
C749 [10.2C]
C750 [24.2F]
C751 [24.1E]
C756 [2.3C]
C757 [24.1F]
C759 [10.2C]
C760 [9.3D]
C761 [2.3C]
C762 [24.2D]
C763 [14.3A]
C764 [9.1A]
C765 [14.3B]
C766 [17.2A]
C767 [14.3A]
C768 [2.3E]
C769 [14.3A]
C770 [10.3C]
C771 [10.2C]
C772 [10.2C]
C773 [2.3C]
C774 [17.2A]
C776 [16.3B]
C777 [17.2B]
C778 [2.2C]
C779 [10.3C]
C781 [16.3B]
C782 [2.2C]
C783 [16.3A]
C784 [2.2C]
C786 [17.2E]
C787 [17.2E]
C788 [17.2E]
C789 [17.2E]
C790 [17.2E]
C791 [17.2E]
C792 [17.2E]
C793 [17.2E]
C794 [2.2C]
C795 [2.2C]
C796 [2.2C]
C797 [12.3E]
C798 [11.3H]
C800 [2.2C]
C801 [12.2E]
C802 [11.1D]
C803 [11.3F]
C804 [17.3E]
C805 [17.3E]
C806 [17.3E]
C807 [17.3E]
C808 [17.3E]
C809 [17.3E]
C810 [12.3E]
C811 [12.2E]
C812 [24.2D]
C813 [12.2C]
C814 [21.1E]
C815 [12.3E]
C816 [25.3D]
C817 [25.3C]
C818 [12.3E]
C819 [12.3E]
C820 [17.2G]
C821 [11.3E]
C822 [20.1A]
C823 [2.1A]
C824 [2.1A]
C825 [12.3E]
C826 [12.3E]
C827 [25.3C]
C828 [25.2C]
C829 [21.2G]
C830 [11.3B]
C831 [20.1B]
C832 [24.2D]
C833 [12.2C]
C834 [2.1A]
C836 [2.1A]
C837 [12.2C]
C838 [12.3C]
C839 [11.3D]
C840 [25.4D]
C841 [25.3C]
C842 [12.3C]
C843 [12.3C]
C844 [25.3B]
C845 [12.3C]
C846 [12.2E]
C847 [11.1A]
C848 [11.3C]
C849 [12.3C]
C850 [12.3C]
C851 [12.3C]
C855 [31.2E]
C856 [15.5E]
C857 [15.4E]
C858 [15.3E]
C859 [14.4E]
C860 [14.5E]
C864 [14.4E]
C865 [14.3E]
C869 [15.5F]
C870 [15.4F]
C871 [15.3F]
C872 [16.2G]
C873 [14.4F]
C874 [17.2G]
C875 [14.5F]
C876 [14.4F]
C877 [27.4D]
CN1 [20.2G]
CN2 [2.3B]
D1 [31.3E]
D2 [17.4E]
D3 [15.2E]
D4 [15.3E]
D5 [16.5E]
D6 [14.2E]
D7 [14.3E]
D8 [31.2D]
D9 [25.2G]
D504 [14.5E]
D505 [14.4E]
D506 [14.4E]
D507 [15.5E]
D508 [15.4E]
D509 [15.4E]
F501 [25.2E]
F502 [27.4D]
G1 [2.3D]
G1 [3.3C 3.3G]
G1 [4.3C 4.3G]
G1 [14.3C]
G1 [15.3C]
G1 [16.3C]
G1 [17.3C]
G1 [18.4C]
G1 [19.3C]
G1 [20.4D 20.2D]
G1 [21.2B 21.4G
21.3B]
G1 [22.2H]
G1 [23.3E 23.3A]
J1 [15.3G]
J2 [14.4G]
J4 [17.3H]
J5 [16.3H]
J6 [31.3F]
J7 [31.2F]
J8 [25.2E]
J501 [2.1D]
L1 [15.2F]
L2 [15.2F]
L3 [14.2F]
L4 [14.3F]
L5 [29.2F]
L6 [29.1F]
L7 [29.3F]
L8 [29.3F]
L9 [28.3G]
L10 [28.3G]
L11 [26.2C]
L12 [28.2G]
L13 [29.3F]
L14 [29.2F]
L505 [15.5E]
L506 [15.4E]
L507 [15.3E]
L508 [14.4F]
L509 [14.5F]
L510 [14.3F]
LB1 [15.1F]
LB2 [15.1F]
LB3 [14.1F]
LB4 [14.1F]
LB5 [17.4F]
LB6 [16.4F]
LB7 [26.3C]
LB8 [26.3C]
LB9 [26.3C]
LB10 [26.3C]
LB501 [3.5E]
LB502 [2.4F]
LB503 [17.3A]
LB504 [4.5D]
LB505 [21.4E]
LB508 [14.3A]
LB509 [17.2A]
LB511 [16.3A]
M1 [11.4D 11.4E
11.4F 11.4C
11.2C]
M2 [11.5E 11.5C
11.5F 11.2F
11.5D]
M3 [9.4F 9.4E 9.4D
9.2C 9.4C]
M4 [9.2F 9.5D 9.5E
9.5F 9.5C]
M5 [7.4C 7.4E 7.4D
7.2C 7.4F]
M6 [5.4E 5.4C 5.2C
5.4F 5.4D]
M7 [5.2F 5.5E 5.5F
5.5C 5.5D]
M8 [7.2F 7.5C 7.5D
7.5E 7.5F]
MEC1 [32.3G]
MEC2 [32.3G]
MEC3 [32.3G]
MEC4 [32.3G]
MEC5 [32.3F]
MEC6 [32.3D]
MEC7 [32.2D]
Q1 [31.3E]
Q2 [25.3G]
Q3 [25.3H]
Q4 [28.3B]
Q5 [29.5A]
Q6 [29.2D]
Q7 [29.1D]
Q8 [31.3D]
Q9 [28.3E]
Q11 [29.3D]
Q12 [28.2E]
Q14 [29.3D]
Q503 [29.4B]
Q504 [29.4A]
Q506 [29.4D]
Q507 [29.2B]
Q508 [28.5C]
Q509 [28.5B]
Q511 [17.2F]
Q512 [25.2C]
Q513 [25.3C]
Q514 [25.2B]
Q515 [25.4B]
Q516 [25.4C]
Q517 [25.2B]
Q518 [25.2B]
R1 [15.1E]
R2 [15.1E]
R3 [14.1E]
R4 [14.1E]
R5 [17.4E]
R6 [16.4E]
R7 [31.3F]
R8 [15.1D]
R9 [15.1D]
R10 [14.1D]
R11 [14.1D]
R12 [17.4E]
R13 [16.5D]
R14 [31.2E]
R15 [31.2E]
R16 [25.3F]
R17 [25.3F]
R18 [25.2G]
R19 [25.2G]
R20 [25.3F]
R21 [27.2E]
R22 [25.3H]
R23 [27.4C]
R24 [27.4C]
R25 [25.3G]
R26 [11.3E]
R27 [11.3E]
R28 [27.4F]
R29 [29.4A]
R30 [27.2C]
R31 [27.4G]
R32 [27.2C]
R33 [27.4G]
R34 [21.3D]
R35 [29.5A]
R36 [29.2A]
R37 [27.2E]
R38 [11.3G]
R39 [27.2E]
R40 [11.3G]
R41 [31.3D]
R42 [31.3E]
R45 [22.3B]
R46 [22.4B]
R47 [22.5B]
R48 [22.3B]
R49 [22.4B]
R50 [22.5B]
R51 [9.3D]
R52 [9.3D]
R53 [9.3G]
R54 [9.3G]
R55 [7.3E]
R56 [7.3E]
R57 [7.3G]
R58 [7.3G]
R59 [5.3E]
R60 [5.3E]
R61 [5.3G]
R62 [5.3G]
R63 [28.3B]
R64 [28.3B]
R65 [29.2E]
R66 [28.3F]
R67 [29.3E]
R507 [29.4A]
R508 [29.4A]
R509 [29.2D]
R510 [29.4B]
R512 [29.3G]
R513 [29.4G]
R514 [29.4F]
R515 [29.1C]
R516 [29.4F]
R517 [29.4E]
R519 [29.2B]
R521 [29.4D]
R522 [29.2A]
R524 [29.2B]
R525 [29.3C]
R526 [28.2D]
R527 [29.4D]
R528 [28.3E]
R530 [29.2B]
R532 [29.1C]
R533 [28.2D]
R534 [29.4C]
R535 [29.2A]
R536 [28.4E]
R537 [28.3C]
R538 [28.3C]
R539 [28.4D]
R540 [28.4E]
R541 [28.4G]
R542 [28.4E]
R543 [28.4G]
R547 [28.4C]
R548 [28.4B]
R549 [28.5B]
R550 [7.2F]
R551 [5.2B]
R552 [5.1H]
R553 [5.1H]
R554 [7.1H]
R555 [5.2A]
R556 [5.2F]
R557 [5.1H]
R558 [5.2A]
R559 [5.2E]
R560 [5.2C]
R561 [5.1H]
R562 [7.1H]
R565 [7.2E]
R566 [5.2B]
R567 [7.2D]
R568 [5.2B]
R569 [5.1H]
R570 [7.1H]
R571 [5.1H]
R572 [7.3H]
R573 [7.2B]
R574 [5.2D]
R575 [7.3H]
R576 [7.2E]
R577 [5.1H]
R578 [5.1H]
R579 [5.2D]
R581 [7.1H]
R582 [5.3H]
R583 [5.3D]
R584 [5.3D]
R585 [5.3H]
R586 [7.2B]
R587 [7.2B]
R588 [7.2H]
R589 [7.2H]
R590 [7.2H]
R591 [7.2A]
R592 [7.2A]
R594 [7.2H]
R595 [7.3D]
R596 [7.2C]
R597 [7.3D]
R598 [3.5A]
R599 [9.2F]
R600 [3.5A]
R603 [9.3H]
R604 [9.2D]
R605 [9.2D]
R606 [9.1H]
R607 [3.5H]
R608 [3.5H]
R610 [9.3H]
R611 [9.1H]
R612 [9.1H]
R613 [3.5H]
R614 [9.1H]
R616 [2.5E]
R617 [9.2E]
R618 [2.5E]
R619 [2.5E]
R620 [2.5E]
R621 [9.2B]
R622 [9.2B]
R623 [2.4E]
R625 [14.4D]
R626 [9.2B]
R628 [14.5D]
R629 [14.4D]
R630 [21.2A]
R631 [21.2A]
R633 [9.2H]
R634 [9.2H]
R635 [21.2A]
R636 [15.5D]
R637 [15.3B]
R639 [15.4D]
R640 [9.2H]
R641 [9.3D]
R642 [9.2H]
R643 [16.3B]
R644 [15.3D]
R645 [17.2B]
R646 [9.2A]
R647 [9.2A]
R648 [20.4E]
R651 [9.3D]
R655 [20.2C]
R656 [21.5H]
R657 [21.5F]
R659 [14.3B]
R660 [20.2C]
R662 [9.2C]
R663 [20.2C]
R664 [20.2C]
R668 [22.1B]
R669 [22.3B]
R670 [22.2B]
R671 [17.1E]
R672 [17.1E]
R673 [17.1E]
R674 [17.1E]
R675 [17.1E]
R676 [17.1E]
R677 [17.1E]
R678 [17.1E]
R679 [22.2B]
R680 [22.2B]
R681 [22.1B]
R682 [11.3H]
R684 [11.3H]
R685 [11.2D]
R686 [11.2F]
R687 [2.1E]
R688 [11.2D]
R689 [21.1D]
R690 [2.1E]
R691 [2.1C]
R692 [21.3D]
R693 [21.3D]
R694 [11.1H]
R695 [11.1H]
R696 [17.1E]
R697 [17.1E]
R698 [17.1E]
R699 [17.1E]
R700 [17.1E]
R701 [17.1E]
R702 [2.1E]
R703 [2.1C]
R704 [11.2H]
R705 [11.2H]
R706 [21.2D]
R707 [21.2E]
R708 [21.2G]
R709 [21.2F]
R710 [2.1E]
R711 [2.1C]
R712 [2.1C]
R713 [2.1C]
R714 [2.1C]
R715 [2.1E]
R716 [21.1F]
R717 [11.2E]
R718 [17.1G]
R719 [21.1F]
R720 [21.2F]
R721 [21.2D]
R722 [21.2D]
R723 [11.2B]
R724 [25.3B]
R725 [25.3C]
R726 [25.2C]
R727 [25.2C]
R728 [25.2C]
R729 [21.2C]
R730 [21.2D]
R731 [11.2B]
R732 [11.2B]
R733 [11.2H]
R734 [11.3D]
R735 [25.4B]
R736 [11.3D]
R737 [11.2H]
R738 [25.2B]
R739 [25.2A]
R740 [11.2H]
R741 [25.3A]
R742 [11.2B]
R744 [11.2A]
R745 [11.2H]
R746 [11.2C]
R747 [25.2E]
R749 [15.2E]
R751 [14.2E]
R752 [15.5E]
R753 [15.4E]
R754 [15.3E]
R758 [14.5E]
R759 [14.4E]
R760 [14.4E]
R762 [15.2E]
R764 [14.3E]
TP1 [3.4D]
TP2 [3.4H]
TP3 [4.4D]
TP4 [4.4H]
U1 [27.4B]
U2 [27.4F]
U3 [27.2D]
U501 [29.2C]
U502 [28.3D]
U503 [21.1E]
U504 [21.2G]
U505 [14.3D 14.2D]
U505 [15.2D 15.2D]
Y1 [21.5G]
1
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ASSEMBLY
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NVIDIA CORPORATION
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NV_PN
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NAME
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DATE
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HFD
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