Page 1
8
7
6
5
4
3
2
1
RV710
+3.3V
GPIO_4(3)
GPIO_3(3)
D D
C C
+12V_BUS
CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX
+12V_BUS+12V_BUS
C21
C21
C20
C20
150nF_16V
150nF_16V
150nF_16V
150nF_16V
LF CAP CER 150NF 10% 16V X7R (0603)
LF CAP CER 150NF 10% 16V X7R (0603)
+3.3V_BUS
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
B B
+3.3V_BUS
C33
C33
C34
C34
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
Place these caps last,
ideally as close to the bus
connector as possible
DNIDNI
C35
C35
10nF
10nF
+3.3V_BUS
DNI , To Bypass U3
PETn0_GFXRn0(2)
PETp1_GFXRp1(2)
PETn1_GFXRn1(2)
PETp2_GFXRp2(2)
PETn2_GFXRn2(2)
PETp3_GFXRp3(2)
PETn3_GFXRn3(2)
PETp4_GFXRp4(2)
PETn4_GFXRn4(2)
PETp5_GFXRp5(2)
PETn5_GFXRn5(2)
PETp6_GFXRp6(2)
PETn6_GFXRn6(2)
PETp7_GFXRp7(2)
PETn7_GFXRn7(2)
PETp8_GFXRp8(2)
PETn8_GFXRn8(2)
PETp9_GFXRp9(2)
PETn9_GFXRn9(2)
PETp10_GFXRp10(2)
PETn10_GFXRn10(2)
PETp11_GFXRp11(2)
PETn11_GFXRn11(2)
PETp12_GFXRp12(2)
PETn12_GFXRn12(2)
PETp13_GFXRp13(2)
PETn13_GFXRn13(2)
PETp14_GFXRp14(2)
PETn14_GFXRn14(2)
PETp15_GFXRp15(2)
PETn15_GFXRn15(2)
+3.3V
TP5 35milTP5 35mil
SMCLK
SMDAT
PRESENCE
PCI-EXPRESS EDGE CONNECTOR
+12V_BUS
PRESENCE
+3.3V_BUS
PERp0
PERn0
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PERp4
PERn4
PERp5
PERn5
PERp6
PERn6
PERp7
PERn7
PERp8
PERn8
PERp9
PERn9
PERp10
PERn10
PERp11
PERn11
PERp12
PERn12
PERp13
PERn13
PERp14
PERn14
PERp15
PERn15
R67 0RR67 0R
JTRST
+12V_BUS+3.3V_BUS
x16 PCIe
x16 PCIe
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
+12V#B1
+12V#B2
+12V#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1
3.3Vaux
WAKE#
RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82
Mechanical Key
Mechanical Key
PRSNT1#A1
+12V#A2
+12V#A3
GND#A4
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V#A9
+3.3V#A10
PERST#
GND#A12
REFCLK+
REFCLKGND#A15
PERp0
PERn0
GND#A18
RSVD#A19
GND#A20
PERp1
PERn1
GND#A23
GND#A24
PERp2
PERn2
GND#A27
GND#A28
PERp3
PERn3
GND#A31
RSVD#A32
RSVD#A33
GND#A34
PERp4
PERn4
GND#A37
GND#A38
PERp5
PERn5
GND#A41
GND#A42
PERp6
PERn6
GND#A45
GND#A46
PERp7
PERn7
GND#A49
RSVD#A50
GND#A51
PERp8
PERn8
GND#A54
GND#A55
PERp9
PERn9
GND#A58
GND#A59
PERp10
PERn10
GND#A62
GND#A63
PERp11
PERn11
GND#A66
GND#A67
PERp12
PERn12
GND#A70
GND#A71
PERp13
PERn13
GND#A74
GND#A75
PERp14
PERn14
GND#A78
GND#A79
PERp15
PERn15
GND#A82
MPCIE1
MPCIE1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
C3
100nFC3100nF
C5
100nFC5100nF
C7
100nFC7100nF
C10
C10
100nF
100nF
C12
C12
100nF
100nF
C15
C15
100nF
100nF
C17
C17
100nF
100nF
C19
C19
100nF
100nF
C23
C23
100nF
100nF
C25
C25
100nF
100nF
C28
C28
100nF
100nF
C30
C30
100nF
100nF
C32
C32
100nF
100nF
C37
C37
100nF
100nF
C39
C39
100nF
100nF
C41
C41
100nF
100nF
C4
100nFC4100nF
C6
100nFC6100nF
C9
100nFC9100nF
C11
C11
100nF
100nF
C13
C13
100nF
100nF
C16
C16
100nF
100nF
C18
C18
100nF
100nF
C22
C22
100nF
100nF
C24
C24
100nF
100nF
C26
C26
100nF
100nF
C29
C29
100nF
100nF
C31
C31
100nF
100nF
C36
C36
100nF
100nF
C38
C38
100nF
100nF
C40
C40
100nF
100nF
C42
C42
100nF
100nF
JTCK
JTDI
JTDO
JTMS
TP1
TP1
35mil
35mil
TP2
TP2
35mil
35mil
TP4
TP4
TP3
TP3
35mil
35mil
35mil
35mil
PERST#
PCIE_REFCLKP (2)
PCIE_REFCLKN (2)PETp0_GFXRp0(2)
GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)
GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)
GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)
GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)
GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)
GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)
GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)
GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)
GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)
GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)
GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)
GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)
GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)
GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)
GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)
GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)
PWR_GOOD(4,13,14)
TVO + DMS-59
Overlap
BUF_PWR
DNI
R64 0RR64 0R
+3.3V +3.3V_BUS
DNI
53
1
2
U4
U4
NC7SZ08P5X_NL
NC7SZ08P5X_NL
Overlap
R630RR63
0R
C8
100nFC8100nF
4
PERST#_buf (2,19)
Stitching caps.
+12V_BUS
C43
C43
100nF
A A
100nF
+VDDC_Source
C47
C47
100nF
100nF
C44
C44
100nF
100nF
C48
C48
100nF
100nF
8
+3.3V_BUS +3.3V
C45
C45
100nF_6.3V
100nF_6.3V
C46
C46
100nF_6.3V
100nF_6.3V
+VDDC
C49
C49
100nF_6.3V
100nF_6.3V
7
+VDDC+12V_BUS
+VDDC+1.1V
6
5
4
3
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
122
of
122
of
122
SYMBOL LEGEND
DNI
#
Doc No.
Doc No.
Doc No.
102-B88901-00A
102-B88901-00A
102-B88901-00A
1
DO NOT
INSTALL
ACTIVE
LOW
DIGITAL
GROUND
ANALOG
GROUND
RevDate:
RevDate:
RevDate:
01
01
01
www.vinafix.vn
Page 2
5
D D
NOTE: some of the PCIE testpoints will
be available through via on traces.
PETp0_GFXRp0(1)
PETn0_GFXRn0(1)
PETp1_GFXRp1(1)
PETn1_GFXRn1(1)
PETp2_GFXRp2(1)
PETn2_GFXRn2(1)
PETp3_GFXRp3(1)
PETn3_GFXRn3(1)
PETp4_GFXRp4(1)
PETn4_GFXRn4(1)
PETp5_GFXRp5(1)
PETn5_GFXRn5(1)
PETp6_GFXRp6(1)
C C
B B
PETn6_GFXRn6(1)
PETp7_GFXRp7(1)
PETn7_GFXRn7(1)
PETp8_GFXRp8(1)
PETn8_GFXRn8(1)
PETp9_GFXRp9(1)
PETn9_GFXRn9(1)
PETp10_GFXRp10(1)
PETn10_GFXRn10(1)
PETp11_GFXRp11(1)
PETn11_GFXRn11(1)
PETp12_GFXRp12(1)
PETn12_GFXRn12(1)
PETp13_GFXRp13(1)
PETn13_GFXRn13(1)
PETp14_GFXRp14(1)
PETn14_GFXRn14(1)
PETp15_GFXRp15(1)
PETn15_GFXRn15(1)
PCIE_REFCLKP(1)
PCIE_REFCLKN(1)
DNI DNI
402 402
4
U1A
U1A
TP7TP7
TP8TP8
TP9TP9
TP10TP10
TP11TP11
TP12TP12
TP13TP13
TP15TP15
TP14TP14
TP16TP16
TP17TP17
TP18TP18
TP19TP19
TP20TP20
TP21TP21
TP22TP22
TP23TP23
TP24TP24
TP25TP25
TP27TP27
TP26TP26
TP28TP28
PERST#_buf(1,19)
AF30
AE31
AE29
AD28
AD30
AC31
AC29
AB28
AB30
AA31
AA29
Y28
Y30
W31
W29
V28
V30
U31
U29
T28
T30
R31
R29
P28
P30
N31
N29
M28
M30
L31
L29
K30
AK30
AK32
AL27
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_REFCLKP
PCIE_REFCLKN
PERSTB
PART 1 OF 10
PART 1 OF 10
PCI-EXPRESS INTERFACE
PCI-EXPRESS INTERFACE
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_CALRN
PCIE_CALRP
3
AH30
AG31
AG29
AF28
AF27
AF26
AD27
AD26
AC25
AB25
Y23
Y24
AB27
AB26
Y27
Y26
W24
W23
V27
U26
U24
U23
T26
T27
T24
T23
P27
P26
P24
P23
M27
N26
+1.1V
AA22
Y22
PCIE_CALRN
PCIE_CALRP
402
R82.0K R82.0K
402
R91.27K R91.27K
2
GFXTp0_PERp0 (1)
GFXTn0_PERn0 (1)
GFXTp1_PERp1 (1)
GFXTn1_PERn1 (1)
GFXTp2_PERp2 (1)
GFXTn2_PERn2 (1)
GFXTp3_PERp3 (1)
GFXTn3_PERn3 (1)
GFXTp4_PERp4 (1)
GFXTn4_PERn4 (1)
GFXTp5_PERp5 (1)
GFXTn5_PERn5 (1)
GFXTp6_PERp6 (1)
GFXTn6_PERn6 (1)
GFXTp7_PERp7 (1)
GFXTn7_PERn7 (1)
GFXTp8_PERp8 (1)
GFXTn8_PERn8 (1)
GFXTp9_PERp9 (1)
GFXTn9_PERn9 (1)
GFXTp10_PERp10 (1)
GFXTn10_PERn10 (1)
GFXTp11_PERp11 (1)
GFXTn11_PERn11 (1)
GFXTp12_PERp12 (1)
GFXTn12_PERn12 (1)
GFXTp13_PERp13 (1)
GFXTn13_PERn13 (1)
GFXTp14_PERp14 (1)
GFXTn14_PERn14 (1)
GFXTp15_PERp15 (1)
GFXTn15_PERn15 (1)
1
For Tektronix LA only
Place close
to ASIC
A A
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
5
4
3
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
222
of
222
of
222
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 3
5
D D
GPIO_0(10)
GPIO_1(10)
GPIO_2(10)
GPIO_3(1)
C C
TP43TP43
B B
GPIO_4(1)
GPIO_5(10)
TP48TP48
GPIO_7(10)
GPIO_8
GPIO_9
GPIO_10
GPIO_22
R13 33RR13 33R
R14 33RR14 33R
R15 33RR15 33R
R16 33RR16 33R
+1.8V
R621KR62
1K
TP30TP30
TP44 35milTP44 35mil
TP45 35milTP45 35mil
TP46 35milTP46 35mil
TP47 35milTP47 35mil
GPIO_8(10)
GPIO_9(10)
GPIO_11(10)
GPIO_12(10)
GPIO_13(10)
HPD2(18)
PWRCNTL_0(14)
GPIO_16(10)
ThermINT(19)
CTF(19)
PWRCNTL_1(14)
TP50TP50
GENERICA(17)
GENERICB(10)
TP41TP41
GENERICD(10)
TP49TP49
HPD1(18)
+1.8V
DNI
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
PWRCNTL_2
GPIO_7
GPIO8_SO
GPIO9_SI
GPIO10_SCK
GPIO_11
GPIO_12
GPIO_13
HPD2
PWRCNTL_0
GPIO_16
ThermINT
HPD3
CTF
PWRCNTL_1
GPIO21_BB_ENA
GPIO_22_CS
GPIO_23
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
HPD4
HPD1
R21 221RR21 221R
R22 110RR22 110R
C53 100nFC53 100nF
PWR_GOOD_GPU
DNI
R351KR35
A A
4
U1B
VREFG
U1B
U1
DVPCLK
AC7
DVPCNTL_0
Y2
DVPCNTL_1
U5
DVPCNTL_2
AA1
DVPCNTL_MVP_0
Y4
DVPCNTL_MVP_1
Y7
DVPDATA_0
V2
DVPDATA_1
Y8
DVPDATA_2
V4
DVPDATA_3
AB7
DVPDATA_4
W1
DVPDATA_5
AB8
DVPDATA_6
W3
DVPDATA_7
AB9
DVPDATA_8
W5
DVPDATA_9
AC6
DVPDATA_10
W6
DVPDATA_11
AD7
DVPDATA_12
AA3
DVPDATA_13
AC8
DVPDATA_14
AA5
DVPDATA_15
AE8
DVPDATA_16
AA6
DVPDATA_17
AE9
DVPDATA_18
AB4
DVPDATA_19
AD9
DVPDATA_20
AB2
DVPDATA_21
AC10
DVPDATA_22
AC5
DVPDATA_23
U6
GPIO_0
U10
GPIO_1
T10
GPIO_2
U8
GPIO_3_SMBDATA
U7
GPIO_4_SMBCLK
T9
GPIO_5_AC_BATT
T8
GPIO_6_TACH
T7
GPIO_7_BLON
P10
GPIO_8_ROMSO
P4
GPIO_9_ROMSI
P2
GPIO_10_ROMSCK
N6
GPIO_11
N5
GPIO_12
N3
GPIO_13
Y9
GPIO_14_HPD2
N1
GPIO_15_PWRCNTL_0
M4
GPIO_16_SSIN
R6
GPIO_17_THERMAL_INT
W10
GPIO_18_HPD3
M2
GPIO_19_CTF
P8
GPIO_20_PWRCNTL_1
P7
GPIO_21_BB_EN
N8
GPIO_22_ROMCSB
N7
GPIO_23_CLKREQB
L6
JTAG_TRSTB
L5
JTAG_TDI
L3
JTAG_TCK
L1
JTAG_TMS
K4
JTAG_TDO
AB13
GENERICA
W8
GENERICB
W9
GENERICC
W7
GENERICD
AD10
GENERICE_HPD4
AC14
HPD1
AC16
VREFG
N10
NC_PWRGOOD
AB22
RSVD#8
AC22
RSVD#9
L9
NC#1
N9
NC#2
AB16
RSVD#3
AB12
RSVD#2
AB11
RSVD#1
AF24
TESTEN
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
PART 2 OF 10
PART 2 OF 10
DVP PORT DAC1
DVP PORT DAC1
I/O
I/O
RESERVED
RESERVED
DAC2
DAC2
HSYNC
VSYNC
AVDD
AVSSQ
VDD1DI
VSS1DI
RSET
H2SYNC
V2SYNC
COMP
A2VDD
A2VDDQ
A2VSSQ
VDD2DI
VSS2DI
R2SET
AM26
R
AK26
RB
AL25
G
AJ25
GB
AH24
B
AG25
BB
AH26
AJ27
AG24
AE22
AE23
AD23
RSET
AD22
AM12
R2
AK12
R2B
AL11
G2
AJ11
G2B
AK10
B2
AL9
B2B
AL13
AJ13
AH12
C
AM10
Y
AJ9
+A2VDD
AE20
+A2VDDQ
AE17
AE19
+VDD2DI
AD19
AC19
R2SET
AG13
1K
+AVDD
+VDD1DI
R12 499RR12 499R
R23 715RR23 715R
3
A_R_DAC1 (16)
A_RB_DAC1 (16)
A_G_DAC1 (16)
A_GB_DAC1 (16)
A_B_DAC1 (16)
A_BB_DAC1 (16)
A_HSYNC_DAC1 (10,16)
A_VSYNC_DAC1 (10,16)
C1050
C1050
C1051
C1051
100nF
100nF
10nF
10nF
10V X5R
10V X7R
402
402 10%
10%
C1053
C1053
C1054
C1054
100nF
100nF
10nF
10nF
10V
X7R 10V X5R
402 10%
402 10%
Place very close to ASIC balls.
A_R_DAC2 (17)
A_RB_DAC2 (17)
A_G_DAC2 (17)
A_GB_DAC2 (17)
A_B_DAC2 (17)
A_BB_DAC2 (17)
A_HSYNC_DAC2 (10,17)
A_VSYNC_DAC2 (10,17)
DAC2_C (17)
DAC2_Y (17)
DAC2_COMP (17)
C2052
C2052
100nF
100nF
C2054
C2054
10nF
10nF
Place very close to ASIC balls.
C1052
C1052
1uF_6.3V
1uF_6.3V
6.3V
402 10%
C1055
C1055
1uF_6.3V
1uF_6.3V
6.3V X5R
402 10%
C2058
C2058
10nF
10nF
X5R
C2051
C2051
100nF
100nF
C2053
C2053
1uF_6.3V
1uF_6.3V
C2055
C2055
100nF
100nF
B1 BLM15BD121SN1B1 BLM15BD121SN1
C1056
C1056
4.7uF_6.3V
4.7uF_6.3V
B2 BLM15BD121SN1B2 BLM15BD121SN1
C2050
C2050
1uF_6.3V
1uF_6.3V
C2056
C2056
1uF_6.3V
1uF_6.3V
B3 120R_300mAB3 120R_300mA
C2057
C2057
4.7uF_6.3V
4.7uF_6.3V
B4
B4
BLM15BD121SN1
BLM15BD121SN1
B5
B5
BLM15BD121SN1
BLM15BD121SN1
2
+1.8V
+3.3V
+1.8V
+1.8V
GPIO_22
GPIO_8
+3.3V
ROM_WP
+3.3V
R241KR24
1K
U2
U2
1
CE#
2
SO
3
WP#
GND4SI
PM25LV512A-100SCE
PM25LV512A-100SCE
HOLD#
1
+3.3V
8
VCC
7
GPIO_10
6
SCK
GPIO_9
5
C57
C57
100nF
100nF
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
5
4
3
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
322
of
322
of
322
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 4
5
RV710: Do not install B6, C60, C61, C62, C58.
D D
+3.3V_BUS
R25
R25
5.1K
5.1K
PWR_GOOD(1,13,14)
C82
C82
12pF_50V
12pF_50V
C83
C83
12pF_50V
12pF_50V
RV810: Install B6, C60, C61, C62, C58..
+1.8V
NS6 NS_VIANS6 NS_VIA
1 2
+1.1V
+VDDC
RV710: Install B10, do not install B9
RV810: Install B9, do not install B10
2 1
XTALOUT_S
Y2
Y2
27.000MHz_10PPM
27.000MHz_10PPM
Overlap
B10
B10
BLM15BD121SN1
BLM15BD121SN1
4
C69
C69
1uF_6.3V
1uF_6.3V
XTALIN_S
XTALOUT_S
C70
C70
1uF_6.3V
1uF_6.3V
GND_SPVSS
C71
C71
100nF
100nF
R30 0RR30 0R
R311MR31
1M
R32 0RR32 0R
3
U1J
U1J
Part 10 of 10
Part 10 of 10
XTAL / PLL
+SPV18
GND_SPVSS
+SPV10
C72
C72
10nF
10nF
XTALINXTALIN_S
AM28
XTALOUT
AK28
XTAL / PLL
H7
NC_SPV18
J7
SPVSS
H8
SPV10
XTALIN
XTALOUT
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
DPLL_PVDD
DPLL_PVSS
DPLL_VDDC
PCIE_PVDD
NC_MPV18
AF14
AE14
AD14
AM30
L8
+DPLL_PVDD
+DPLL_VDDC
+PCIE_PVDD
+MPVDD
GND_PVSS
C73
C73
1uF_6.3V
1uF_6.3V
2
C59
C59
10nF
10nF
GND_PVSS
C65
C65
10nF
10nF
C74
C74
10nF
10nF
C66
C66
100nF
100nF
100nF
100nF
C64
C64
100nF
100nF
10uF_X6S
10uF_X6S
C67
C67
1uF_6.3V
1uF_6.3V
Overlap
C75
C75
Overlap Overlap
C88
MC89
MC89
C88
10uF_X6S
10uF_X6S
C63
C63
Overlap
C68
C68
10uF_X6S
10uF_X6S
4.7uF_6.3V
4.7uF_6.3V
B8
B8
BLM15BD121SN1
BLM15BD121SN1
B11
B11
BLM15BD121SN1
BLM15BD121SN1
1
B7
B7
BLM15BD121SN1
BLM15BD121SN1
+1.1V
+1.8V
+1.8V
+1.8V
NS5NS_VIA NS5NS_VIA
12
C C
RV710: Do not install B12, C77, C79, C80, C81.
RV810: Install B12, C77, C79, C80, C81.
+3.3V
R36
SCL
SDA
C4021
C4021
100nF
100nF
+3.3V
R36
4.7K
4.7K
R33
R33
4.7K
4.7K
+TSVDD
GND
DDC6 BUS:
I2C Address Function Device
B B
A A
5
0x98 LM63 - External
SCL / SDA BUS:
I2C Address Function Device
N/A N/A N/A
Temperature Sensor
LM63
+1.8V
4
B4002
B4002
BLM15BD121SN1
BLM15BD121SN1
DDC6CLK(19)
DDC6DATA(19)
C4020
C4020
1uF_6.3V
1uF_6.3V
R37
R37
4.7K
4.7K
AC1
AC3
R34
R34
4.7K
4.7K
R1
R3
AD17
AC17
U1H
U1H
Part 8 of 10
Part 8 of 10
I2C / DDC / AUX
I2C / DDC / AUX
DDC6CLK
DDC6DATA
SCL
SDA
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
U1I
U1I
Part 9 of 10
Part 9 of 10
TSS FDO
TSS FDO
TSVDD
TSVSS
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
3
AUX1P
AUX1N
DDC1CLK
DDC1DATA
AUX2P
AUX2N
TMDP / DAC1LVTMDP / DAC2
TMDP / DAC1LVTMDP / DAC2
DDC2CLK
DDC2DATA
DDCCLK_AUX5P
DDCDATA_AUX5N
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N
TS_FDO
DPLUS
DMINUS
R5
T4
T2
AD2
AD4
AE6
AE5
AD13
AD11
AC11
AC13
AE16
AD16
AD20
AC20
TS_FDO
GPU_DPLUS
GPU_DMINUS
DDC1CLK (17)
DDC1DATA (17)
DDCAUX5P (16)
DDCAUX5N (16)
DDCAUX7P (17)
DDCAUX7N (17)
TS_FDO (19)
GPU_DPLUS (19)
GPU_DMINUS (19)
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
RH LP RV710 DDR3 TVO DMS-59
Overlap
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
422
of
422
of
422
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 5
5
4
3
2
1
TMDP INTERFACE
U1F
AG8
AG7
AF11
AE11
AF6
AF7
AG10
AG11
AE13
AF13
U1F
DPA_PVDD
DPA_PVSS
NC_DPA_VDD18#2
NC_DPA_VDD18#1
DPA_VDD10#1
DPA_VDD10#2
DPB_PVDD
DPB_PVSS
NC_DPB_VDD18#1
NC_DPB_VDD18#2
D D
C C
+1.8V
+1.8V
B2503
B2503
BLM15BD121SN1
BLM15BD121SN1
C2509
C2509
4.7uF_6.3V
4.7uF_6.3V
C2510
C2510
1uF_6.3V
1uF_6.3V
C2501
C2501
1uF_6.3V
1uF_6.3V
+DPB_PVDD
C2511
C2511
100nF
100nF
+DPB_VDD18
PART 6 OF 10
PART 6 OF 10
DPA
DPA
DPB
DPB
TX2P_DPA0P
TX2M_DPA0N
TX1P_DPA1P
TX1M_DPA1N
TX0P_DPA2P
TX0M_DPA2N
TXCAP_DPA3P
TXCAM_DPA3N
DPA_VSSR#5
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#2
DPA_VSSR#1
TX5P_DPB0P
TX5M_DPB0N
TX4P_DPB1P
TX4M_DPB1N
TX3P_DPB2P
TX3M_DPB2N
TXCBP_DPB3P
TXCBM_DPB3N
DPB_VSSR#5
DPB_VSSR#2
DPB_VSSR#1
DPB_VSSR#4
DPB_VSSR#3
AK3
AK1
AH3
AH1
AG3
AG5
AF2
AF4
AH5
AG1
AG6
AE3
AE1
AK8
AL7
AJ7
AH6
AK6
AM5
AK5
AM3
AM8
AG9
AF10
AM6
AH8
TX2P (18)
TX2M (18)
TX1P (18)
TX1M (18)
TX0P (18)
TX0M (18)
TXCAP (18)
TXCAM (18)
CALIBRATION
+1.1V
C2507
C2507
1uF_6.3V
1uF_6.3V
+DPB_VDD10
C2517
C2517
100nF
100nF
4
B2505
B B
A A
B2505
30R_1A
30R_1A
C2516
C2515
C2515
4.7uF_6.3V
4.7uF_6.3V
5
C2516
1uF_6.3V
1uF_6.3V
AF8
DPB_VDD10#1
AF9
DPB_VDD10#2
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
CALIBRATION
3
DPAB_CALR
AE10
DPAB_CALR
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
R2500150R R2500150R
1%
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
522
of
522
of
522
Doc No.
Doc No.
Doc No.
102-B88901-00A
102-B88901-00A
102-B88901-00A
1
RevDate:
RevDate:
RevDate:
01
01
01
www.vinafix.vn
Page 6
5
4
3
2
1
LVTMDP INTERFACE
D D
C C
+1.8V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
C1507
C1507
1uF_6.3V
1uF_6.3V
C1501
C1501
C1504
C1504
+DPE_PVDD
C1509
C1509
1uF_6.3V
1uF_6.3V
+DPE_VDD18
C1510
C1510
1uF_6.3V
1uF_6.3V
+DPE_VDD10
C1511
C1511
1uF_6.3V
1uF_6.3V
C1502
C1502
100nF
100nF
C1505
C1505
100nF
100nF
C1508
C1508
100nF
100nF
B1500
B1500
BLM15BD121SN1
BLM15BD121SN1
+1.8V
B1501
B1501
BLM15BD121SN1
BLM15BD121SN1
B B
+1.1V
B1502 30R_1AB1502 30R_1A
C1500
C1500
4.7uF_6.3V
4.7uF_6.3V
C1503
C1503
4.7uF_6.3V
4.7uF_6.3V
C1506
C1506
4.7uF_6.3V
4.7uF_6.3V
U1G
U1G
AG19
NC_DPF_PVDD
AF20
NC_DPF_PVSS
AG17
DPF_VDD18#2
AF16
DPF_VDD18#1
AG22
DPF_VDD10#2
AF22
DPF_VDD10#1
AG18
DPE_PVDD
AF19
DPE_PVSS
AG16
DPE_VDD18#2
AG15
DPE_VDD18#1
AG21
DPE_VDD10#2
AG20
DPE_VDD10#1
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
Part 7 of 10
Part 7 of 10
DPF
DPF
DPE
DPE
CALIBRATION
CALIBRATION
RSVD#6
RSVD#4
T2X5P_DPF0P
T2X5M_DPF0N
T2X4P_DPF1P
T2X4M_DPF1N
T2X3P_DPF2P
T2X3M_DPF2N
T2XCFP_DPF3P
T2XCFM_DPF3N
DPF_VSSR#4
DPF_VSSR#5
DPF_VSSR#2
DPF_VSSR#1
DPF_VSSR#3
RSVD#7
RSVD#5
T2X2P_DPE0P
T2X2M_DPE0N
T2X1P_DPE1P
T2X1M_DPE1N
T2X0P_DPE2P
T2X0M_DPE2N
T2XCEP_DPE3P
T2XCEM_DPE3N
DPE_VSSR#3
DPE_VSSR#2
DPE_VSSR#1
DPE_VSSR#4
DPE_VSSR#5
DPEF_CALR
AK24
AJ23
AL23
AK22
AH22
AJ21
AL21
AK20
AH20
AJ19
AM22
AM24
AG23
AF23
AM20
AL19
AK18
AH18
AJ17
AL17
AK16
AH16
AJ15
AL15
AK14
AM14
AH14
AG14
AM16
AM18
AF17
DPEF_CALR
T2X2P (18)
T2X2M (18)
T2X1P (18)
T2X1M (18)
T2X0P (18)
T2X0M (18)
T2XCEP (18)
T2XCEM (18)
R1500150R R1500150R
1%
A A
5
4
3
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
622
of
622
of
622
Doc No.
Doc No.
Doc No.
102-B88901-00A
102-B88901-00A
102-B88901-00A
1
RevDate:
RevDate:
RevDate:
01
01
01
www.vinafix.vn
Page 7
5
4
3
2
1
MEMORY INTERFACE
M_MDA[63..0](15)
U1C
U1C
D D
Stitching caps.
Place where memory transitions from L6 to any other layer.
+MVDD
C201
C201
C200
C200
100nF
100nF
C205
C205
100nF
100nF
+MVDD
C C
B B
C210
C210
100nF
100nF
C215
C215
100nF
100nF
100nF
100nF
C206
C206
100nF
100nF
C211
C211
100nF
100nF
C216
C216
100nF
100nF
+MVDD
C202
C202
100nF
100nF
C207
C207
100nF
100nF
C212
C212
100nF
100nF
C217
C217
100nF
100nF
R293
R293
100R
100R
R294
R294
100R
100R
+MVDD
R291
R291
100R
100R
R292
R292
100R
100R
MVREFS_A
C203
C203
100nF
100nF
C208
C208
100nF
100nF
C213
C213
100nF
100nF
C218
C218
100nF
100nF
MVREFD_A
C297
C297
100nF
100nF
C204
C204
100nF
100nF
C209
C209
100nF
100nF
C214
C214
100nF
100nF
C219
C219
100nF
100nF
C295
C295
100nF
100nF
C298
C298
10nF
10nF
C296
C296
10nF
10nF
+MVDD
R296
R296
4.7K
4.7K
R297
R297
4.7K
4.7K
MEMTEST
R298
R298
243R
243R
M_MAA[14..0](15)
M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
M_MDA5
M_MDA6
M_MDA7
M_MDA8
M_MDA9
M_MDA10
M_MDA11
M_MDA12
M_MDA13
M_MDA14
M_MDA15
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
M_MDA21
M_MDA22
M_MDA23
M_MDA24
M_MDA25
M_MDA26
M_MDA27
M_MDA28
M_MDA29
M_MDA30
M_MDA31
M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA63
CLKTESTA
CLKTESTB
M_MAA13
M_MAA14
K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5
K26
J26
K8
L7
J8
G20
G14
K7
K25
J25
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
MVREFDA
MVREFSA
CLKTESTA
CLKTESTB
MEM_CALRP1
NC_MAA_13
NC_MAA_14
NC_MEM_CALRN1
NC_MEM_CALRP0
NC_MEM_CALRN0
PART 3 OF 10
PART 3 OF 10
MEMORY
MEMORY
INTERFACE
INTERFACE
READ STROBE
READ STROBE
WRITE STROBE
WRITE STROBE
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_BA0
MAA_BA1
MAA_12
MAA_BA2
DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B
ODTA0
ODTA1
CLKA0
CLKA1
CLKA0B
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
CKEA0
CKEA1
WEA0B
WEA1B
DRAM_RST
M_MAA0
K17
M_MAA1
J20
M_MAA2
H23
M_MAA3
G23
M_MAA4
G24
M_MAA5
H24
M_MAA6
J19
M_MAA7
K19
M_MAA8
J14
M_MAA9
K14
M_MAA10
J11
M_MAA11
J13
J16
BA0 (15)
L15
BA1 (15)
M_MAA12
H11
G11
BA2 (15)
M_DQMA#0
E32
M_DQMA#1
E30
M_DQMA#2
A21
M_DQMA#3
C21
M_DQMA#4
E13
M_DQMA#5
D12
M_DQMA#6
E3
M_DQMA#7
F4
M_QSA0
H28
M_QSA1
C27
M_QSA2
A23
M_QSA3
E19
M_QSA4
E15
M_QSA5
D10
M_QSA6
D6
M_QSA7
G5
M_QSA#0
H27
M_QSA#1
A27
M_QSA#2
C23
M_QSA#3
C19
M_QSA#4
C15
M_QSA#5
E9
M_QSA#6
C5
M_QSA#7
H4
L18
K16
H26
G9
H25
H9
G22
G17
G19
G16
H22
J22
G13
K13
K20
J17
G25
H10
L10
ODTA0 (15)
ODTA1 (15)
CLKA0 (15)
CLKA1 (15)
CLKA#0 (15)
CLKA#1 (15)
RASA#0 (15)
RASA#1 (15)
CASA#0 (15)
CASA#1 (15)
CSA#0_0 (15)
CSA#1_0 (15)
CKEA0 (15)
CKEA1 (15)
WEA#0 (15)
WEA#1 (15)
M_MAA[14..0] (15)
M_DQMA#[7..0] (15)
M_QSA[7..0] (15)
M_QSA#[7..0] (15)
+MVDD
MR295
MR295
4.7K
4.7K
DRAM_RST (15)
Overlap
A A
5
DIVIDER RESISTORS DDR3
MVREF TO 1.8V
MVREF TO GND
100R
100R
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
4
3
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
722
of
722
of
722
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 8
5
+MVDD
C123
C123
C122
C121
C121
10nF
10nF
C134
C134
1uF_6.3V
1uF_6.3V
MC132
MC132
4.7uF_6.3V
4.7uF_6.3V
C122
10nF
10nF
C135
C135
1uF_6.3V
1uF_6.3V
MC133
MC133
4.7uF_6.3V
4.7uF_6.3V
Overlap
MC159
MC159
4.7uF_6.3V
4.7uF_6.3V
+3.3V
+1.8V
NS11 NS_VIANS11 NS_VIA
C120
C120
10nF
10nF
D D
C C
B B
Overlap cap footprints (0805 with 0603).
MC130
MC130
MC131
MC131
4.7uF_6.3V
4.7uF_6.3V
4.7uF_6.3V
4.7uF_6.3V
+1.8V
B26
B26
BLM15BD121SN1
BLM15BD121SN1
+MVDD
B27 BLM15BD121SN1B27 BLM15BD121SN1
10nF
10nF
C136
C136
1uF_6.3V
1uF_6.3V
+MVDD
C178
C178
1uF_6.3V
1uF_6.3V
C191
C191
1uF_6.3V
1uF_6.3V
12
GND_VSSRH1
C164
C164
1uF_6.3V
1uF_6.3V
C124
C124
10nF
10nF
C137
C137
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
C160
C160
100nF
100nF
C179
C179
100nF
100nF
C192
C192
C125
C125
100nF
100nF
C138
C138
1uF_6.3V
1uF_6.3V
C165
C165
1uF_6.3V
1uF_6.3V
C161
C161
1uF_6.3V
1uF_6.3V
C180
C180
1uF_6.3V
1uF_6.3V
4
C126
C126
100nF
100nF
C139
C139
1uF_6.3V
1uF_6.3V
+VDD_CT
C166
C166
100nF
100nF
C127
C127
100nF
100nF
C140
C140
1uF_6.3V
1uF_6.3V
C162
C162
1uF_6.3V
1uF_6.3V
C167
C167
100nF
100nF
C181
C181
100nF
100nF
+VDDRH1
GND_VSSRH1
C163
C163
100nF
100nF
C128
C128
100nF
100nF
C141
C141
100nF
100nF
+MVDD
C129
C129
100nF
100nF
C142
C142
100nF
100nF
AA20
AA21
AB20
AB21
AA17
AA18
AB17
AB18
AA11
AA12
H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22
Y11
Y12
U11
U12
V11
V12
L17
L16
U1D
U1D
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#4
VDDR5#1
VDDR5#2
VDDR5#3
VDDR5#4
VDDRHA
VSSRHA
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
PART 4 OF 10
PART 4 OF 10
POWER
POWER
3
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26
L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22
AA15
M11
M12
N15
N17
R13
R16
R18
R21
T12
T15
T17
T20
U13
U16
U18
U21
V15
V17
V20
V21
Y13
Y16
Y18
Y21
M13
M15
M16
M17
M18
M20
M21
N20
C143
C143
1uF_6.3V
1uF_6.3V
+VDDC
C86
C86
100nF
100nF
C144
C144
1uF_6.3V
1uF_6.3V
C150
C150
1uF_6.3V
1uF_6.3V
+VDDCI+VDDCI
C87
C87
100nF
100nF
C145
C145
1uF_6.3V
1uF_6.3V
C151
C151
1uF_6.3V
1uF_6.3V
C193
C193
100nF
100nF
C146
C146
1uF_6.3V
1uF_6.3V
C152
C152
1uF_6.3V
1uF_6.3V
C168
C168
1uF_6.3V
1uF_6.3V
C194
C194
1uF_6.3V
1uF_6.3V
C149
C149
100nF
100nF
C153
C153
1uF_6.3V
1uF_6.3V
C169
C169
1uF_6.3V
1uF_6.3V
C195
C195
1uF_6.3V
1uF_6.3V
2
C148
C148
10nF
10nF
C154
C154
1uF_6.3V
1uF_6.3V
C170
C170
1uF_6.3V
1uF_6.3V
+1.8V
Overlap
C155
C155
1uF_6.3V
1uF_6.3V
C171
C171
1uF_6.3V
1uF_6.3V
Overlap
MC196
MC196
4.7uF_6.3V
4.7uF_6.3V
C156
C156
1uF_6.3V
1uF_6.3V
C172
C172
1uF_6.3V
1uF_6.3V
MC147
MC147
4.7uF_6.3V
4.7uF_6.3V
+1.1V
C157
C157
1uF_6.3V
1uF_6.3V
Overlap
B28 220R_2AB28 220R_2A
C173
C173
1uF_6.3V
1uF_6.3V
Overlap
+VDDC
C85
C85
1uF_6.3V
1uF_6.3V
MC158
MC158
4.7uF_6.3V
4.7uF_6.3V
+VDDC
1
C188
C184
C184
C185
C183
C183
C182
C182
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
Overlap cap footprints (0805 with 0603).
C174
C174
C175
C175
10uF_X6S
10uF_X6S
10uF_X6S
10uF_X6S
A A
5
4
3
2
C185
C186
1uF_6.3V
1uF_6.3V
C176
C176
10uF_X6S
10uF_X6S
C186
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
C177
C177
10uF_X6S
10uF_X6S
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
+VDDC
C187
C187
1uF_6.3V
1uF_6.3V
C188
1uF_6.3V
1uF_6.3V
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Sheet
Sheet
Sheet
C189
C189
C190
C190
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
of
822
of
822
of
822
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 9
5
U1E
U1E
AA27
PCIE_VSS#1
AB24
PCIE_VSS#2
AB32
D D
C C
B B
PCIE_VSS#3
AC24
PCIE_VSS#4
AC26
PCIE_VSS#5
AC27
PCIE_VSS#6
AD25
PCIE_VSS#7
AD32
PCIE_VSS#8
AE27
PCIE_VSS#9
AF32
PCIE_VSS#10
AG27
PCIE_VSS#11
AH32
PCIE_VSS#12
K28
PCIE_VSS#13
K32
PCIE_VSS#14
L27
PCIE_VSS#15
M32
PCIE_VSS#16
N25
PCIE_VSS#17
N27
PCIE_VSS#18
P25
PCIE_VSS#19
P32
PCIE_VSS#20
R27
PCIE_VSS#21
T25
PCIE_VSS#22
T32
PCIE_VSS#23
U25
PCIE_VSS#24
U27
PCIE_VSS#25
V32
PCIE_VSS#26
W25
PCIE_VSS#27
W26
PCIE_VSS#28
W27
PCIE_VSS#29
Y25
PCIE_VSS#30
Y32
PCIE_VSS#31
A3
GND#1
A30
GND#2
AA13
GND#3
AA16
GND#4
AB10
GND#5
AB15
GND#6
AB6
GND#7
AC9
GND#8
AD6
GND#9
AD8
GND#10
AE7
GND#11
AG12
GND#12
AH10
GND#13
AH28
GND#14
B10
GND#15
B12
GND#16
B14
GND#17
B16
GND#18
B18
GND#19
B20
GND#20
B22
GND#21
B24
GND#22
B26
GND#23
B6
GND#24
B8
GND#25
C1
GND#26
C32
GND#27
E28
GND#28
F10
GND#29
F12
GND#30
F14
GND#31
F16
GND#32
RV710 A12 HF MVE SLT BIN1
RV710 A12 HF MVE SLT BIN1
4
PART 5 OF 10
PART 5 OF 10
GND
GND
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U3
U9
V13
V16
V18
V6
Y10
Y15
Y17
Y20
Y6
T11
R11
A32
AM1
AM32
3
2
1
A A
5
4
3
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
922
of
922
of
922
Doc No.
Doc No.
Doc No.
102-B88901-00A
102-B88901-00A
102-B88901-00A
1
RevDate:
RevDate:
RevDate:
01
01
01
www.vinafix.vn
Page 10
5
4
3
2
1
PIN BASED STRAPS
DNI
D D
Pull-Down Resistors are for BU until built-in pull-downs are verified.
Overlap pads to save space
and to prevent assembly of
both resistors.
DNI
DNI
DNI
+3.3V
DNI
DNI
R45 10KR45 10K
R46 10KR46 10K
Layout
DNI
High logic voltageGround
C C
B B
Signal
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
R49 10KR49 10K
R51 10KR51 10K
R55 10KR55 10K
PIN BASED STRAPS
A_VSYNC_DAC2 (3,17)
GPIO_9
GPIO_9 (3)
GPIO_0
GPIO_0 (3)
GPIO_1
GPIO_1 (3)
GPIO_2
GPIO_2 (3)
GPIO_11
GPIO_11 (3)
GPIO_13
GPIO_13 (3)
GPIO_12
GPIO_12 (3)
A_VSYNC_DAC1 (3,16)
A_HSYNC_DAC1 (3,16)
GPIO_8
GPIO_8 (3)
GPIO_5
GPIO_5 (3)
GPIO_16
GPIO_16 (3)
GENERICB
GENERICD
GENERICB (3)
GENERICD (3)
VIP_DEVICE_STRAP_EN
0: Driver would ignore the value sampled on VHAD_0 during reset
1: Driver would use the value sampled at reset from VHAD_0 to determine
whether or not a VIP slave device (e.g. Theater chip) is connected
(i.e. 0 indicates yes, 1 indicates no).
VGA DISABLE : 1 for disable (set to 0 for normal operation)
GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)
GPIO(2) - BIF_GEN2_EN (5.0 GT/s Enable)
0 : Default. (Driver Controlled Gen2)
1 : Strap Controlled Gen2
GPIO(13, 12,11) - CONFIG[2..0]
CONFIG[2]
CONFIG[1]
CONFIG[0]
AUD[0]
AUD[1]
BIF_CLK_PM_EN
0 - Disable CLKREQ# power management capability
1 - Enable CLKREQ# power management capability
100 - 512Kbit M25P05A (ST)
101 - 1Mbit M25P10A (ST)
101 - 2Mbit M25P20 (ST)
101 - 4Mbit M25P40 (ST)
101 - 8Mbit M25P80 (ST)
100 - 512Kbit Pm25LV512 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)
[GPIO_5 : GPIO_16]
Quimonda [0:0]
Hynix [0:1]
Samsung [1:0]
GenericB and GenericD will be
used for additional memory vendor
straps.
DNI
NTSC
R57 10KR57 10K
A A
5
4
3
GPIO_7
A_HSYNC_DAC2 (3,17)
GPIO_7 (3)
RESERVED :Internal use only. Other logic must not affect this signal
during RESET.
1 - NTSC TVO0 - PAL TVO TV OUT STANDARD
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
10 22
of
10 22
of
10 22
Doc No.
Doc No.
Doc No.
102-B88901-00A
102-B88901-00A
102-B88901-00A
1
RevDate:
RevDate:
RevDate:
01
01
01
www.vinafix.vn
Page 11
8
7
6
5
4
3
2
1
+12V_BUS
C695
C695
100uF
C630
C630
10UF_16V
10UF_16V
1206 1206
C643
C643
10UF_16V
10UF_16V
100uF
SM 6.3mm Dia
C634
C634
10UF_16V
10UF_16V
1206 1206
Mirrored on PCB
C645
C645
10UF_16V
10UF_16V
+VDDC_Source
C636
C636
470UF_16V
470UF_16V
TH 8mm Dia
L622
MULTI FOOTPRINT
+PW_VDDC_HGD +PW_VDDC_HGDR
D D
SSO-8 PKG
R621 0RR621 0R
QH
402
C633
C633
150nF_16V
150nF_16V
603
805
Mirrored on PCB Mirrored on PCB
L622
IND_0.47uH_7A
IND_0.47uH_7A
Overlap
805
1206 1206
Mirrored on PCB
Y5V
6.3V 1206
+VDDC
C632
C632
Y5V
10uf
10uf
6.3V1206
MLCC
C625
C625
820uF_2.5V
820uF_2.5V
8 x 8 mm, TH
Bulk Cap
+VDDC
+VDDC
C627
C627
100nF
100nF
402 603402
C628
C628
15nF
15nF
C635
C635
390pF
390pF
+PW_VDDC_M
QL
+PW_VDDC_LGDR1
R6220RR622
603
0R
C C
+PW_VDDC_LGD
VDDC_FB(14)
+VDDC_B
U603
U603
1
+PW_VDDC_HGD
+PW_VDDC_LGD
R615
R615
42.2K
42.2K
place R615
B B
close to IC pin4
BOOT
2
UGATE
3
GND
LGATE4VCC
uP6101BU8-A
uP6101BU8-A
PHASE
COMP
+PW_VDDC_M
8
VDDC_COMP
7
VDDC_FB
6
FB
5
+VDD_VCC
C603
C603
0.22uF
0.22uF
VDD_EN (14,19)
402
+PW_VDDC_HGDR
+VDDC_Source
2
1
3
NQ601
NQ601
IPD135N03L G
IPD135N03L G
MULTI FOOTPRINT
Rs
Cs
Place Rs and Cs across QL
RC snubber values shown
are for reference only,
tuning is required
+PW_VDDC_LGDR1
TO252 DPAK PKG
2
NQ602
NQ602
1
IPD040N03L G
IPD040N03L G
3
TH 1108
L601 1.0uHL601 1.0uH
1210
1%
402
X7R
25V
VDDC_FB
12
NS600
NS600
NS_VIA
NS_VIA
Sense Point
VDDC_FB_TRACE
R6590RR659
0R
Reserve for
603
Loop Measurement
VDDC_SV
C613
C613
2.7nF_50V_5%
2.7nF_50V_5%
16V
402
X7R
10%
Rt2
RFB1
R611
R611
10K
10K
402
0.8V Ref
R4 = (R1 x 0.8V) / (Vout1 - 0.8V)
R6131KR613
1K
402
5%1%
Place R1 and
R4 close to
PWM and
routed with
separate
20mil trace to
the ASIC
C623
C623
Y5V
10uf
10uf
6.3V
Mirrored on PCB
C624
C624
10uf
10uf
1206
C629
C629
Y5V
10uf
10uf
6.3V1206
Mirrored on PCB
+PW_VDDC_M
FILTERED SMPS VCCCOMPENSATION CIRCUIT
BOOT CIRCUIT
+12V_BUS
+VDD_VCC
+12V_BUS
R607
R607
2.2R
2.2R
603
X7R
C607
C607
5%
100nF
100nF
7
C605
C605
100nF
100nF
5%
6
+VDDC_B
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
X7R603
16V
+PW_VDDC_M
5
4
3
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
11 22
of
11 22
of
11 22
Doc No.
Doc No.
Doc No.
1
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
402
VDDC_COMP
C612
C612
C611
C611
47pF_50V
47pF_50V
8.2nF_25V
8.2nF_25V
10V
603
A A
402
X7R
R612
R612
12.1K
12.1K
402
1%
NPO
10%
R6090RR609
0R
8
10V
40250V
5%
10%
X5R
VDDC_FB
share pad of R1314,R1309
www.vinafix.vn
Page 12
8
7
6
5
4
3
2
1
+VDDC_Source
Over Lap
R7020RR702
0R
1
2
3
4
+MVDDC_S
+MVDDC_B
+PW_MVDDC_HGD
+PW_MVDDC_LGD
C718
C718
150nF_16V
150nF_16V
603
+PW_MVDDC_M
R715
R715
42.2K
42.2K
4
C719
C717
C717
4.7uF_16V
4.7uF_16V
805 805
C719
4.7uF_16V
4.7uF_16V
Mirrored on PCB
L701 3.3uHL701 3.3uH
1210
1%
402
X7R
25V
Place Rs and Cs across QL
RC snubber values shown
are for reference only,
tuning is required
MVDDC_FB(14)
C720
C720
10UF
10UF
1206
Mirrored on PCB
TH 1108
1206
1206
Mirrored on PCB
12
NS700
NS700
NS_VIA
NS_VIA
Sense Point
MVDD_FB_TRACE
Rs
Reserve for
C713
C713
3.9nF
3.9nF
402
10%
R7131KR713
1K
402
5%
16V
X7R
R7160RR716
0R
603
Loop Measurement
Cs
R1
RFB1
R711
R711
10K
10K
402
1%
Place R1 and R4 close to PWM
and routed with separate 20mil
trace to the ASIC
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
3
C721
C721
10UF
10UF
1206
C723
C723
10uf
10uf
1206 1206
MLCC
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Sheet
Sheet
Sheet
2
C724
C724
10uf
10uf
overlap
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
of
12 22
of
12 22
of
12 22
TH 8mm Dia
Bulk Cap
Doc No.
Doc No.
Doc No.
102-B88901-00A
102-B88901-00A
102-B88901-00A
+MVDD
1
MC725
MC725
470uF_10V
470uF_10V
TH 10mm Dia
overlap
RevDate:
RevDate:
RevDate:
01
01
01
D D
Q701
C C
+PW_MVDDC_HGD +PW_MVDDC_HGDR
+PW_MVDDC_LGD +PW_MVDDC_LGDR
R721 0RR721 0R
R722 0RR722 0R
603
Q701
1
2
78
3
6
5
4
AO4940
AO4940
SO-8 Dual-FET
U703
B B
MVDD_EN(14,19)
402
+PW_MVDDC_M
MVDDC_COMP
MVDDC_FB
+MVDD_VCC
C703
C703
0.22uF
0.22uF
COMPENSATION CIRCUIT
402
C711
C711
10nF_25V
10nF_25V
402
X7R
R712
R712
8.66K
8.66K
402
A A
1%
10V
10%
C712
C712
56pF_50V
56pF_50V
603
NPO
R7090RR709
0R
8
50V
5%
MVDDC_COMP
402
X5R
MVDDC_FB
FILTERED SMPS VCC BOOT CIRCUIT
10V
10%
+MVDD_VCC
603
X7R
5%
+12V_BUS
7
R706
R706
2.2R
2.2R
C707
C707
100nF
100nF
C705
C705
100nF
100nF
603 X7R
16V
5%
+12V_BUS
+MVDDC_B
+PW_MVDDC_M
6
8
7
6
5
1-Position the controller (U703) such that LGate(pin4) is the closet to gate
of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate
of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as
short and as wide as possible to reduce the trace inductance.
2-Place the bypass capacitors for Vcc as well as Boost caps as close to the
controller as possible. They are as follows;
Vcc bypass cap is C703, and Boost cap is C705.
3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place
the rest of the compensation network close to the pins 7 and 6. These are R710,
R711, R713, C713 and R712, C711 and C712.
U703
BOOT
PHASE
UGATE
COMP
GND
FB
LGATE
VCC
uP6101BU8-A
uP6101BU8-A
Layout guideline
5
www.vinafix.vn
Page 13
5
4
3
2
1
LDO #2: Vout = +1.8V +/- 2%
PCB: 50 to 70mm sq. copper area for cooling
D D
Overlap 1206 / 1210
+3.3V_BUS
footprints.
PWR_GOOD(1,4,14)
LDO2-3_EN(14)
C C
Vin = 2.1V to 3.6V MAX Iout = 0.8A (TBV) RMS MAX
+12V_BUS
R8611KR861
1K
+5V_SHUNT
D861
D861
BZT52C5V1
BZT52C5V1
2 1
R871 0.50RR871 0.50R
+5V_SHUNT
10uF_X6S
10uF_X6S
C866
C866
TP861TP861
PWR_GOOD
LDO2-3_EN
LDO2_VIN
C868
C868
1uF_6.3V
1uF_6.3V
U861
U861
1
POK
2
EN
3
VIN
CNTL4REFIN
uP7706U8
uP7706U8
GND#8
VOUT
GND#9
+1.8V_LDO2
R865
R865
12K4
8
7
FB
6
5
DNI
9
LDO2_FB
12K4
R864
R864
10K
10K
0.1%
R5
R4
C865
C865
33pF_50V
33pF_50V
C3
VOUT = Vref x (1 + R5/R4)
DNI
+5V_SHUNT
+MVDD
0805
C861
C861
10uF_X6S
10uF_X6S
Overlap
C864
C864
100nF
100nF
0805
R880 0RR880 0R
+1.8V
+12V_BUS
Regulators for +5V_VESA
F812
F812
nanoSMDC020F
nanoSMDC020F
1206
C810
C810
100nF
100nF
0603
16V
0805
1/8W
5%
+VESA_IN
Vout(V) = Vref (1+R2/R1)
U810
U810
1
VIN
5
NC
8
NC#8
ADJ4VOUT
LM317LCDR
LM317LCDR
VESA_FB
VOUT#2
VOUT#3
VOUT#6
+5V_VESA
2
3
R813
R813
6
499R
499R
7
0402
R1
1uF_6.3V
1uF_6.3V
R814
R814
1.5K
1.5K
0402
R2
C811
C811
C812
C812
10uF_10V
10uF_10V
TEST
LDO #3: Vout = +1.1V +/- 2.5%
Vin = +1.4V to 2.087VMAX
Iout = 1.4A (TBV) RMS MAX
PCB: 50 to 70mm sq. copper area for cooling
C856
C856
10uF_X6S
10uF_X6S
PWR_GOOD(1,4,14)
R8600RR860
0R
C854
C854
100nF
100nF
3
LDO2-3_EN
LDO3_VIN
C858
C858
1uF_6.3V
1uF_6.3V
U851
U851
1
POK
2
EN
3
VIN
CNTL4REFIN
uP7706U8
uP7706U8
GND#8
VOUT
GND#9
LDO3_OUT
C851
C855
R5
R4
C855
33pF_50V
33pF_50V
C3
R855
R855
3.92K
8
7
FB
6
5
DNI
9
LDO3_FB
3.92K
R854
R854
10K
10K
C851
10uF_X6S
10uF_X6S
DNI
VOUT = Vref x (1 + R5/R4)
4
B B
+5V_SHUNT
A A
+MVDD
5
1210
1/2W
R858 1R_1210R858 1R_1210
R872 1R_1210R872 1R_1210
R873 1R_1210R873 1R_1210
R874 1R_1210R874 1R_1210
+1.1V
Overlap
+VDDC
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
13 22
of
13 22
of
13 22
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 14
5
4
3
2
1
Power Play
VDDC Voltage Settings Using GPIOs
PWRCNTL_1 PWRCNTL_0
D D
+12V_BUS+3.3V_BUS +12V_BUS
R857
R857
Node 1
4.7K
4.7K
5%
1
1
+12V_BUS
1
Q850
Q850
MMBT3904
MMBT3904
2 3
Q851
Q851
MMBT3904
MMBT3904
2 3
2 3
PSEQ_N1
R843
R843
5.1K
5.1K
5%
Q840
Q840
MMBT3904
MMBT3904
PSEQ_VDDCUP2
R852
R850
R850
475R
475R
1%
R852
1.62K
1.62K
1%
PSEQ_N3
Node 3
PSEQ_N2
Node 2
R853
+VDDC
R853
200R
200R
1%
R841
R841
4.75K
4.75K
PSEQ_VDDCUP
C841
C841
100nF_6.3V
100nF_6.3V
R851
R851
200R
200R
1%
C C
Power up/down Sequencing
PSEQ_OUT
R839 0RR839 0R
Q852
Q852
1
MMBT3904
MMBT3904
2 3
+3.3V_BUS
PSEQ_EN23
R844 5.1KR844 5.1K
R846 5.1KR846 5.1K
5%
5%
PSEQ_ENM
1
2 3
1
Power Sequence Circuit to ensure SMPS_EN is released after
+12V_BUS and +3.3V_BUS are both in regulation.
VDD_EN (11,19)
Node 1
When +3.3V_BUS gets close to regulation, one of the two
Node 2
conditions of releasing SMPS_EN is active
Target ~ 900mV when +3.3 at min regulation (worse case)
Typical trigger when +3.3V ramps above 2.2V (650mV)
Node 3 When +12V gets close to regulation, one of the two
conditions of releasing SMPS_EN is active
Target ~ 1.25V when +12 at min regulation (worse case)
Typical trigger when +12V ramps above 10V (1.1V)
When +12V_BUS ramps above min Vbe, SMPS_EN will be held low
5.1K
5.1K
R845
R845
Q841
Q841
MMBT3904
MMBT3904
Q842
Q842
MMBT3904
MMBT3904
2 3
LDO2-3_EN (13)
MVDD_EN (12,19)
0
1
PWRCNTL_0(3)
PWRCNTL_1(3)
Rf1=
Rf2=
GPIO_15GPIO_20
0
10
01
1
+3.3V
+3.3V
R1241
R1241
10K
10K
011
MR1240
MR1240
10K
10K
Output Voltage (V)
Rf1=
Rf2=
PWRCNTL_0
DNI
PWRCNTL_1
DNI
32
1
Rf1=
Rf2=
VDDC_CNTL_OUT
Rf1 Rf2
R1226
R1226
78.7K
78.7K
1% 1%
32
BSH111
BSH111
Q1200
Q1200
1
R1225
R1225
40.2K
40.2K
BSH111
BSH111
Q1201
Q1201
Power-up Default
R1221 0RR1221 0R
VDDC_FB (11)
R610
R610
78.7K
78.7K
Place close to
R611 in the VDDC
section.
R4
RFB2
R710
R710
7.87K
7.87K
Place close to
R711 in the MVDD
section.
MVDDC_FB (12)
Test cct for low VDDC voltage.
DNI
+MVDD
B B
A A
PWR_GOOD(1,4,13)
+12V_BUS
+12V_BUS
R848
R848
100K
+MVDD
PWR_GOOD(1,4,13)
5
R847 5.1KR847 5.1K
5%
C844
C844
1uF_6.3V
1uF_6.3V
100K
Q843
Q843
1
MMBT3904
MMBT3904
2 3
R897 0RR897 0R
4
R849
R849
10K
10K
Q844
Q844
1
MMBT3904
MMBT3904
2 3
+3.3V_BUS +3.3V
C842
C842
10uF_X6S
10uF_X6S
ALL_RAILS_UP
402
X5R
16V
C843
C843
100NF
100NF
PWR_GOOD (1,4,13)
Q845
Q845
SI2304DS
SI2304DS
3 2
1
DNI
3
R840
R840
100K
100K
ALL_RAILS_UP (18)
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
14 22
of
14 22
of
14 22
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 15
5
4
3
2
1
M_MDA[63..0](7)
D D
C C
M_MAA[14..0](7)
M_DQMA#[7..0](7)
B B
M_QSA[7..0](7)
M_QSA#[7..0](7)
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_QSA#0
M_QSA#1
M_QSA#2
M_QSA#3
M_QSA#4
M_QSA#5
M_QSA#6
M_QSA#7
M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
M_MDA5
M_MDA6
M_MDA7
M_MDA8
M_MDA9
M_MDA10
M_MDA11
M_MDA12
M_MDA13
M_MDA14
M_MDA15
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
M_MDA21
M_MDA22
M_MDA23
M_MDA24
M_MDA25
M_MDA26
M_MDA27
M_MDA28
M_MDA29
M_MDA30
M_MDA31
M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA63
U201
VREFC_U201
VREFD_U201
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14
BA0(7)
BA1(7)
BA2(7)
CLKA0(7)
CLKA#0(7)
CKEA0(7)
ODTA0(7) ODTA0(7)
CSA#0_0(7)
RASA#0(7)
CASA#0(7)
WEA#0(7)
M_QSA3
M_DQMA#1
M_DQMA#3
M_QSA#1
M_QSA#3
DRAM_RST(7) DRAM_RST(7) DRAM_RST(7)
R217
Should be 240
Ohms +-1%
R217
243R
243R
U201
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
VDDQ#A1
ODT
CS
VDDQ#A8
RAS
VDDQ#C1
CAS
VDDQ#C9
WE
VDDQ#D2
VDDQ#E9
VDDQ#F1
DQSL
VDDQ#H2
DQSU
VDDQ#H9
DML
DMU
DQSL
DQSU
RESET
ZQ
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
NC#J1
VSSQ#E8
NC#L1
VSSQ#F9
NC#J9
VSSQ#G1
VSSQ#G9
NC#L9
100-BALL
100-BALL
SDRAM DDR3
SDRAM DDR3
23E21147ST12
23E21147ST12
+MVDD
R201
R201
4.99K
4.99K
R202
R202
4.99K
4.99K
+MVDD
R209
R209
4.99K
4.99K
R210
R210
4.99K
4.99K
+MVDD +MVDD
C301 1uF_6.3VC301 1uF_6.3V
C300 1uF_6.3VC300 1uF_6.3V
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
C302 1uF_6.3VC302 1uF_6.3V
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
VREFC_U201
VREFC_U201
C413
C413
100nF
100nF
VREFD_U201
VREFD_U201
C486
C486
100nF
100nF
C303 1uF_6.3VC303 1uF_6.3V
C304 1uF_6.3VC304 1uF_6.3V
M_MDA9
M_MDA14
M_MDA10
M_MDA15
M_MDA11
M_MDA12
M_MDA8
M_MDA13
M_MDA28
M_MDA26
M_MDA31
M_MDA27
M_MDA30
M_MDA24
M_MDA29
M_MDA25
C305 1uF_6.3VC305 1uF_6.3V
C306 1uF_6.3VC306 1uF_6.3V
C307 1uF_6.3VC307 1uF_6.3V
CHANNEL A: 256MB/512MB DDR3
VREFC_U202
VREFD_U202
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14
BA0(7)
BA1(7)
BA2(7)
CLKA0(7)
CLKA#0(7)
CKEA0(7)
CSA#0_0(7)
RASA#0(7)
CASA#0(7)
WEA#0(7)
M_QSA2M_QSA1
M_QSA0
M_DQMA#2
M_DQMA#0
M_QSA#2
M_QSA#0
R218
C311 1uF_6.3VC311 1uF_6.3V
C312 1uF_6.3VC312 1uF_6.3V
C313 1uF_6.3VC313 1uF_6.3V
R218
243R
243R
C314 1uF_6.3VC314 1uF_6.3V
Should be 240
Ohms +-1%
C309 1uF_6.3VC309 1uF_6.3V
C308 1uF_6.3VC308 1uF_6.3V
C310 1uF_6.3VC310 1uF_6.3V
C316 1uF_6.3VC316 1uF_6.3V
C315 1uF_6.3VC315 1uF_6.3V
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
+MVDD
+MVDD
C317 1uF_6.3VC317 1uF_6.3V
C318 1uF_6.3VC318 1uF_6.3V
U202
U202
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
100-BALL
SDRAM DDR3
SDRAM DDR3
23E21147ST12
23E21147ST12
R203
R203
4.99K
4.99K
R204
R204
4.99K
4.99K
R211
R211
4.99K
4.99K
R212
R212
4.99K
4.99K
C319 1uF_6.3VC319 1uF_6.3V
C320 1uF_6.3VC320 1uF_6.3V
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
VREFC_U202
C438
C438
100nF
100nF
VREFD_U202
C487
C487
100nF
100nF
C322 1uF_6.3VC322 1uF_6.3V
C321 1uF_6.3VC321 1uF_6.3V
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
C323 1uF_6.3VC323 1uF_6.3V
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
C324 1uF_6.3VC324 1uF_6.3V
M_MDA21
M_MDA19
M_MDA22
M_MDA18
M_MDA20
M_MDA16
M_MDA23
M_MDA17
M_MDA2
M_MDA4
M_MDA0
M_MDA7
M_MDA3
M_MDA6
M_MDA1
M_MDA5
+MVDD +MVDD+MVDD
+MVDD
Should be 240
Ohms +-1%
C326 1uF_6.3VC326 1uF_6.3V
C325 1uF_6.3VC325 1uF_6.3V
C327 1uF_6.3VC327 1uF_6.3V
VREFC_U401
VREFD_U401
C328 1uF_6.3VC328 1uF_6.3V
C329 1uF_6.3VC329 1uF_6.3V
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14
CLKA1(7)
CLKA#1(7)
CKEA1(7)
ODTA1(7)
CSA#1_0(7)
RASA#1(7)
CASA#1(7)
WEA#1(7)
R219
R219
243R
243R
BA0(7)
BA1(7)
BA2(7)
M_QSA7
M_QSA6
M_DQMA#7
M_DQMA#6
M_QSA#7
M_QSA#6
+MVDD
+MVDD
C331 1uF_6.3VC331 1uF_6.3V
C330 1uF_6.3VC330 1uF_6.3V
R205
R205
4.99K
4.99K
R206
R206
4.99K
4.99K
R213
R213
4.99K
4.99K
R214
R214
4.99K
4.99K
C332 1uF_6.3VC332 1uF_6.3V
U401
U401
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
23E21147ST12
23E21147ST12
VREFC_U401
VREFD_U401
C333 1uF_6.3VC333 1uF_6.3V
C334 1uF_6.3VC334 1uF_6.3V
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
100-BALL
SDRAM DDR3
SDRAM DDR3
C463
C463
100nF
100nF
C488
C488
100nF
100nF
C335 1uF_6.3VC335 1uF_6.3V
C336 1uF_6.3VC336 1uF_6.3V
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
C337 1uF_6.3VC337 1uF_6.3V
C338 1uF_6.3VC338 1uF_6.3V
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
C339 1uF_6.3VC339 1uF_6.3V
M_MDA56
M_MDA62
M_MDA58
M_MDA61
M_MDA57
M_MDA63
M_MDA59
M_MDA60
M_MDA55
M_MDA49
M_MDA52
M_MDA51
M_MDA53
M_MDA48
M_MDA54
M_MDA50
C341 1uF_6.3VC341 1uF_6.3V
C340 1uF_6.3VC340 1uF_6.3V
C342 1uF_6.3VC342 1uF_6.3V
C343 1uF_6.3VC343 1uF_6.3V
C344 1uF_6.3VC344 1uF_6.3V
+MVDD
Should be 240
Ohms +-1%
C346 1uF_6.3VC346 1uF_6.3V
C345 1uF_6.3VC345 1uF_6.3V
C347 1uF_6.3VC347 1uF_6.3V
DRAM_RST(7)
C348 1uF_6.3VC348 1uF_6.3V
VREFC_U402
VREFD_U402
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14
BA0(7)
BA1(7)
BA2(7)
CLKA1(7)
CLKA#1(7)
CKEA1(7)
ODTA1(7)
CSA#1_0(7)
RASA#1(7)
CASA#1(7)
WEA#1(7)
M_QSA5
M_QSA4
M_DQMA#5
M_DQMA#4
M_QSA#5
M_QSA#4
R220
R220
243R
243R
C350 1uF_6.3VC350 1uF_6.3V
C349 1uF_6.3VC349 1uF_6.3V
C351 1uF_6.3VC351 1uF_6.3V
C352 1uF_6.3VC352 1uF_6.3V
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
C353 1uF_6.3VC353 1uF_6.3V
U402
U402
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
100-BALL
SDRAM DDR3
SDRAM DDR3
23E21147ST12
23E21147ST12
C354 1uF_6.3VC354 1uF_6.3V
+MVDD
+MVDD
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
R207
R207
4.99K
4.99K
R208
R208
4.99K
4.99K
R215
R215
4.99K
4.99K
R216
R216
4.99K
4.99K
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
VREFC_U402
C448
C448
100nF
100nF
VREFD_U402
C489
C489
100nF
100nF
+MVDD
C385 1uF_6.3VC385 1uF_6.3V
C384 1uF_6.3VC384 1uF_6.3V
M_MDA44
M_MDA41
M_MDA45
M_MDA43
M_MDA47
M_MDA42
M_MDA46
M_MDA40
M_MDA35
M_MDA37
M_MDA32
M_MDA39
M_MDA34
M_MDA38
M_MDA33
M_MDA36
C386 1uF_6.3VC386 1uF_6.3V
+MVDD
+MVDD+MVDD
CLKA0(7)
CLKA#0(7)
A A
CLKA1(7)
CLKA#1(7)
R221
R221
56R
56R
402
R222
R222
56R
56R
402
R223
R223
56R
56R
402
R224
R224
56R
56R
402
C499
C499
10nF
10nF
402
+MVDD
C358 100nFC358 100nF
C359 100nFC359 100nF
C356 100nFC356 100nF
C357 100nFC357 100nF
C355 100nFC355 100nF
C500
C500
10nF
10nF
402
5
C360 100nFC360 100nF
C361 100nFC361 100nF
C362 100nFC362 100nF
C363 100nFC363 100nF
Overlap 0805 / 0603 footprints.
+MVDD
4
+MVDD +MVDD
MC364 4.7uF_6.3VMC364 4.7uF_6.3V
MC365 4.7uF_6.3VMC365 4.7uF_6.3V
MC366 4.7uF_6.3VMC366 4.7uF_6.3V
MC368 4.7uF_6.3VMC368 4.7uF_6.3V
MC367 4.7uF_6.3VMC367 4.7uF_6.3V
MC369 4.7uF_6.3VMC369 4.7uF_6.3V
+MVDD
C370 100nFC370 100nF
C371 100nFC371 100nF
3
C372 100nFC372 100nF
C373 100nFC373 100nF
C374 100nFC374 100nF
C375 100nFC375 100nF
C376 100nFC376 100nF
+MVDD
C377 100nFC377 100nF
MC379 4.7uF_6.3VMC379 4.7uF_6.3V
MC378 4.7uF_6.3VMC378 4.7uF_6.3V
MC380 4.7uF_6.3VMC380 4.7uF_6.3V
MC381 4.7uF_6.3VMC381 4.7uF_6.3V
MC383 4.7uF_6.3VMC383 4.7uF_6.3V
MC382 4.7uF_6.3VMC382 4.7uF_6.3V
2
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
15 22
of
15 22
of
15 22
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 16
5
4
3
2
1
DAC 1 OUTPUT
Place close to Connector
D D
C C
B B
Place close to Connector
Pseudo differential RGB signals should be routed from the ASIC to the display connector without switching reference plane or running over split plane
Resistors are footprint options for the inductors. Footprints should be overlapped. (R1024-26)
A_R_DAC1(3)
A_RB_DAC1(3)
A_G_DAC1(3)
A_GB_DAC1(3)
A_B_DAC1(3)
A_BB_DAC1(3)
R1003
R1003
75R
R1029
R1029
37.4R
37.4R
A_HSYNC_DAC1(3,10)
A_VSYNC_DAC1(3,10)
SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane
DDCAUX5N(4)
DDCAUX5P(4)
C1999 100nFC1999 100nF
R1028
R1028
37.4R
37.4R
+5V_VESA
14
2 3
7
5 6
U1999A
U1999A
74AHCT125
74AHCT125
1
U1999B
U1999B
4
74AHCT125
74AHCT125
R1027
R1027
37.4R
37.4R
75R
A_HSYNC_DAC1_B
A_VSYNC_DAC1_B
R1001
R1001
R1002
R1002
75R
75R
75R
75R
+5V_VESA
R1005
R1005
2.2K
2.2K
402
+5V_VESA
R1008
R1008
2.2K
2.2K
402 402
A_R_DAC1_M
A_G_DAC1_M
A_B_DAC1_M
R1006 33RR1006 33R
R1009 33RR1009 33R
R1010
R1010
R1011
R1011
DNI
DNI
DNI
L1001 16NH_500MAL1001 16NH_500MA
L1002 16NH_500MAL1002 16NH_500MA
L1003 16NH_500MAL1003 16NH_500MA
OVERLAP
402
DDCDATA_DAC1_R
DDCCLK_DAC1_R
402
A_HSYNC_DAC1_R
24R
24R
402
A_VSYNC_DAC1_R
24R
24R
Optional ESD Protection Diodes
+3.3V_BUS
A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F
ALLOW FOR A LOW INDUCTANCE PATH TO PIN 5
+5V_VESA
DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
A_R_DAC1_F (18)
A_G_DAC1_F (18)
A_B_DAC1_F (18)
DDCDATA_DAC1_R (18)
DDCCLK_DAC1_R (18)
A_HSYNC_DAC1_R (18)
A_VSYNC_DAC1_R (18)
To DMS-59 Connector
A A
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
5
4
3
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
16 22
of
16 22
of
16 22
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 17
5
4
3
2
1
DAC 2 OUTPUT
Optional ESD Protection Diods
D D
C C
B B
Place close to Connector
Pseudo differential RGB signals should be routed from the ASIC to the display connector without switching reference plane or running over split plane
A_R_DAC2(3)
A_RB_DAC2(3)
A_G_DAC2(3)
A_GB_DAC2(3)
A_B_DAC2(3)
A_BB_DAC2(3)
R2028
R2029
R2029
37.4R
37.4R
A_HSYNC_DAC2(3,10)
A_VSYNC_DAC2(3,10)
SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane
R2028
37.4R
37.4R
DDCAUX7N(4)
DDC1DATA(4)
DDCAUX7P(4)
DDC1CLK(4)
+3.3V
+3.3V
9 8
10
13
12 11
R2027
R2027
37.4R
37.4R
U1999C
U1999C
74AHCT125
74AHCT125
U1999D
U1999D
74AHCT125
74AHCT125
R2016 0RR2016 0R
R2003
R2003
75R
75R
R2014 0RR2014 0R
A_HSYNC_DAC2_B
A_VSYNC_DAC2_B
R2002
R2002
75R
75R
Overlap
Overlap
R2001
R2001
75R
75R
+5V_VESA
R2005
R2005
2.2K
2.2K
402
+5V_VESA
R2008
R2008
2.2K
2.2K
402
DNI
DNI
DNI
A_R_DAC2_M
L2001 16NH_500MAL2001 16NH_500MA
A_G_DAC2_M
L2002 16NH_500MAL2002 16NH_500MA
A_B_DAC2_M
L2003 16NH_500MAL2003 16NH_500MA
OVERLAP
RV710: DDC1 is 5V tolerant. Do not install level shifter.
--> Do not install R2013, R2015, Q2001, Q2002. Install R2014, R2016.
RV810: DDC1 is NOT 5V tolerant. Install level shifter.
--> Do not install R2014, R2016. Install R2013, R2015, Q2001, Q2002.
402
24R
24R
402
402
24R
24R
DDCDATA_DAC2_RDDCDATA_DAC2_L
DDCCLK_DAC2_RDDCCLK_DAC2_L
A_HSYNC_DAC2_R
402
A_VSYNC_DAC2_R
R2006 33RR2006 33R
R2009 33RR2009 33R
R2010
R2010
R2011
R2011
+3.3V_BUS
A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F
DDCDATA_DAC2_R
DDCCLK_DAC2_R
A_HSYNC_DAC2_R
A_VSYNC_DAC2_R
Place close to Connector
ALLOW FOR A LOW INDUCTANCE PATH TO PIN 5
+5V_VESA
A_R_DAC2_F (18)
A_G_DAC2_F (18)
A_B_DAC2_F (18)
DDCDATA_DAC2_R (18)
DDCCLK_DAC2_R (18)
A_HSYNC_DAC2_R (18)
A_VSYNC_DAC2_R (18)
To DMS-59 Connector
TVO
DAC2_Y(3)
R3001
R3001
75R
75R
DAC2_C(3)
R3002
R3002
75R
75R
A A
DAC2_COMP(3)
R3003
R3003
75R
75R
5
L3001 470nH_250mAL3001 470nH_250mA
C3001
C3001
47pF_50V
47pF_50V
L3002 470nH_250mAL3002 470nH_250mA
C3002
C3002
47pF_50V
47pF_50V
L3003 470nH_250mAL3003 470nH_250mA
C3003
C3003
47pF_50V
47pF_50V
DAC2_Y_F
C3004
C3004
47pF_50V
47pF_50V
DAC2_C_F
C3005
C3005
47pF_50V
47pF_50V
DAC2_COMP_F
C3006
C3006
47pF_50V
47pF_50V
DAC2_COMP_F
4
402
GENERICA(3)
R3006 0RR3006 0R
DNI for Dell
Install for Dell
+3.3V
Install for Dell
R3008
R3008
10K
10K
DAC2_Y_DINDAC2_Y_F
DAC2_C_DINDAC2_C_F
DAC2_COMP_DIN
402
STV/HDTV#_DET PIN6
402
DNI for Dell
R3009 0RR3009 0R
Install for Dell only when it's needed for EMI
402
R30070RR3007
0R
402402 402
DNI for Dell
DNI for Dell
3
TV Out
J3001
J3001
6
HDTV_OUT_DET#
3
Y-OUT
4
C-OUT
7
Comp_out
CompIn
5
SYNC
1
GND
2
GND#2
8
Rpin5
CASE
9
CASE#9
10
CASE#10
Conn_DIN_Mini_Circular_7_Pin_with_O_Ring
Conn_DIN_Mini_Circular_7_Pin_with_O_Ring
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
17 22
of
17 22
of
17 22
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 18
5
4
3
2
1
DMS-59 DPB / DPE OUTPUT
+5V_VESA
+3.3V
HPD1_IN
Q1603
Q1603
MMBT3904
MMBT3904
D D
T2XCEP(6)
T2XCEM(6)
T2X0P(6)
T2X0M(6)
T2X1P(6)
T2X1M(6)
T2X2P(6)
T2X2M(6)
C C
TXCAP(5)
TXCAM(5)
TX0P(5)
TX0M(5)
TX1P(5)
TX1M(5)
TX2P(5)
TX2M(5)
HPD1(3)
C1601 100nF_6.3VC1601 100nF_6.3V
C1603 100nF_6.3VC1603 100nF_6.3V
C1605 100nF_6.3VC1605 100nF_6.3V
C1607 100nF_6.3VC1607 100nF_6.3V
Q1604
Q1604
MMBT3904
MMBT3904
HPD2(3)
C1609 100nF_6.3VC1609 100nF_6.3V
C1611 100nF_6.3VC1611 100nF_6.3V
C1613 100nF_6.3VC1613 100nF_6.3V
C1615 100nF_6.3VC1615 100nF_6.3V
2 3
+3.3V
2 3
1
R1617
R1617
10K
10K
C1602 100nF_6.3VC1602 100nF_6.3V
C1604 100nF_6.3VC1604 100nF_6.3V
C1606 100nF_6.3VC1606 100nF_6.3V
C1608 100nF_6.3VC1608 100nF_6.3V
ALL_RAILS_UP(14)
HPD2_IN
1
R1619
R1619
10K
10K
C1610 100nF_6.3VC1610 100nF_6.3V
C1612 100nF_6.3VC1612 100nF_6.3V
C1614 100nF_6.3VC1614 100nF_6.3V
C1616 100nF_6.3VC1616 100nF_6.3V
ALL_RAILS_UP(14)
R1618 10KR1618 10K
R1601 499RR1601 499R
R1603 499RR1603 499R
R1605 499RR1605 499R
R1607 499RR1607 499R
R1620 10KR1620 10K
R1609 499RR1609 499R
R1611 499RR1611 499R
R1613 499RR1613 499R
R1615 499RR1615 499R
A_R_DAC1_F(16)
A_G_DAC1_F(16)
A_B_DAC1_F(16)
A_HSYNC_DAC1_R(16)
A_VSYNC_DAC1_R(16)
DDCCLK_DAC1_R(16)
DDCDATA_DAC1_R(16)
R1602 499RR1602 499R
R1604 499RR1604 499R
R1606 499RR1606 499R
R1608 499RR1608 499R
DVI1_BIAS_GND
32
U1601
U1601
1
SI2304DS
SI2304DS
A_R_DAC2_F(17)
A_G_DAC2_F(17)
A_B_DAC2_F(17)
A_HSYNC_DAC2_R(17)
A_VSYNC_DAC2_R(17)
DDCCLK_DAC2_R(17)
DDCDATA_DAC2_R(17)
R1610 499RR1610 499R
R1612 499RR1612 499R
R1614 499RR1614 499R
R1616 499RR1616 499R
DVI2_BIAS_GND
32
U1602
U1602
1
SI2304DS
SI2304DS
A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
DDCCLK_DAC1_R
DDCDATA_DAC1_R
DVI1_HPD
T2XCEP_C
T2XCEM_C
T2X0P_C
T2X0M_C
T2X1P_C
T2X1M_C
T2X2P_C
T2X2M_C
+5V_VESA
A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F
A_HSYNC_DAC2_R
A_VSYNC_DAC2_R
DDCCLK_DAC2_R
DDCDATA_DAC2_R
DVI2_HPD
TXCAP_C
TXCAM_C
TX0P_C
TX0M_C
TX1P_C
TX1M_C
TX2P_C
TX2M_C
C2011
C2011
1uF_10V
1uF_10V
C1011
C1011
1uF_10V
1uF_10V
5
+5V1
2
VGA1_RED
1
RED1_GND
58
VGA1_GREEN
59
GREEN1_GND
3
VGA1_BLUE
4
BLUE1_GND
56
VGA1_HSYNC
55
VGA1_VSYNC
54
SYNCS1
6
DVI1_COC_CLOCK
7
DVI1_COC_DATA
36
DVI1_HPD
31
DVI1_TXC+
32
DVI1_TXC-
57
DVI1_TXC RTN
29
DVI1_TX0+
30
DVI1_TX0-
33
DVI1_TX0 RTN
27
DVI1_TX1+
28
DVI1_TX1-
34
DVI1_TX1 RTN
25
DVI1_TX2+
26
DVI1_TX2-
35
DVI1_TX2 RTN
8
GND1
22
GND2
24
GND3
38
GND4
23
NC1
37
NC2
39
NC3
48
NC4
53
NC5
11
+5V2
14
VGA2_RED
15
RED2_GND
47
VGA2_GREEN
46
GREEN2_GND
13
VGA2_BLUE
12
BLUE2_GND
50
VGA2_HSYNC
51
VGA2_VSYNC
52
SYNCS2
10
DVI2_COC_CLOCK
9
DVI2_COC_DATA
40
DVI2_HPD
45
DVI2_TXC+
44
DVI2_TXC-
49
DVI2_TXC RTN
16
DVI2_TX0+
17
DVI2_TX0-
43
DVI2_TX0 RTN
18
DVI2_TX1+
19
DVI2_TX1-
42
DVI2_TX1 RTN
20
DVI2_TX2+
21
DVI2_TX2-
41
DVI2_TX2 RTN
CASE1
SHIELD1
SHIELD2
CASE2
DMS59_SHIELDED
DMS59_SHIELDED
J1601
J1601
61
62
63
60
B B
Optional ESD protection diodes
T2X2P_C
T2X2M_C
T2X1P_C
T2X1M_C
T2X0M_C
T2XCEP_C
T2XCEM_C T2XCEM_C
A A
5
DNI DNI
DNI
4
T2X2P_C
T2X2M_C
T2X1P_C
T2X1M_C
T2X0P_CT2X0P_C
T2X0M_C
T2XCEP_C
TX2P_C
TX2M_C
TX1P_C
TX1M_C
TX0M_C
TX0P_C
TXCAM_C
TX2P_C
TX2M_C
TX1P_C
TX1M_C
TX0M_C
TX0P_C
TXCAM_C
DNI
TXCAP_CTXCAP_C
3
Connector 1
Signals Mapping
VGA: DAC1
DVI:
Internal TMDP2
HPD: HPD1
DDC: DDC1
5V: +5V_VESA
Connector 2
Signals Mapping
VGA: DAC2 (TVDAC)
DVI: Internal LVTMDS1
HPD: HPD2
DDC: DDC5
5V: +5V_VESA
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
18 22
of
18 22
of
18 22
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 19
5
4
3
2
1
THERMAL MANAGEMENT
Remote Temperature Sensor
+3.3V
D D
DDC6CLK(4)
DDC6DATA(4)
ThermINT(3)
R4003
R4003
10K
10K
R4001 100RR4001 100R
R4002 100RR4002 100R
DNIDNI
DNI
INTERFACE INFO: SMBUS SLAVE
Clock: Min 10kHz - Max 100kHz
7 bit address: 100 1100
SCL_R
402
SDA_R
402
C4005
C4005
C4006
C4006
56pF_50V
56pF_50V
56pF_50V
56pF_50V
402
402
NPO
NPO
+3.3V
C4001
C4001
10uF
10uF
8
7
6
C4002
C4002
1uF_6.3V
1uF_6.3V
U4001
U4001
SMCLK
SMDATA
ALERT
GND5FAN
LM63CIMAX
LM63CIMAX
C4003
C4003
100pF_50V
100pF_50V
VDD
D+
D-
1
2
3
PWM
4
Remote diode temp sensor is for
RV710 BU, until internal thermal
sensor is calibrated.
R4004
R4004
10K
10K
GPU_DPLUS
C4004
C4004
2.2nF_50V
2.2nF_50V
402
50V
X7R
GPU_DMINUSTACH
GPU_DPLUS (4)
GPU_DMINUS (4)
Critial Temperature Fault
+12V_BUS
R4055
R4055
20K
1
1
Q4013
Q4013
MMBT3904
MMBT3904
2 3
+3.3V_BUS
2 3
20K
R4040
R4040
5.1K
5.1K
Q4006
Q4006
MMBT3904
MMBT3904
C C
1%
R4054 1KR4054 1K
CTF_TRIP
R40391KR4039
1K
1%
PERST#_buf(1,2)
CTF SHOULD BE ACTIVE HI.
R4038 2.2KR4038 2.2K
CTF(3)
B B
1
Q4016
Q4016
2 3
MMBT3904
MMBT3904
R4056 3.9RR4056 3.9R
32
2N7002E
2N7002E
Q4014
Q4014
R4060 5.1KR4060 5.1K
1
CTF_GATED2
Q4007
Q4007
MMBT3904
MMBT3904
CTF_SET2
2 3
C4013
C4013
1uF_6.3V
1uF_6.3V
R4044 1KR4044 1K
1
C4014
C4014
1uF_6.3V
1uF_6.3V
R4043
R4043
470K
470K
CTF_SET3
1
CTF_FB_CNTL
Q4009
Q4009
MMBT3904
MMBT3904
2 3
DNI
+3.3V_BUS
1
23
Q4008
Q4008
MMBT3906
MMBT3906
R4045
R4045
10K
10K
CTF
TEST CIRCUIT
R4047
R4047
100K
100K
R4046 5.1KR4046 5.1K
CTF_VCNTL
DNI
R4051 1KR4051 1K
Use on RV810 if low-voltage VDDC latch is used
on power sequencing.
VDD_EN
VDD_EN (11,14)
Q4010
Q4010
1
MMBT3904
MMBT3904
2 3
DNI
MVDD_EN (12,14)
FAN_PWM_INV
To maximize fan output
during CTF trigger.
DNI
3
Alternate to Q4103.
FAN_OUT_N
Vdiff
FAN_VE
JU4001JU4001
1
2
WARNING!
Be cautious when using a 3-wire fan with
this fan control circuit. The negative pin will not always
be ground. Some 3-wire fans with tachometers will only
work if the negative pin of the fan is ground.
Warning: TS_FDO is not 5V
tolerant. MAX sink current
1.65mA
+3.3V
R4100
R4100
2.61K
2.61K
R4101 10KR4101 10K
TS_FDO(4)
A A
5
TS_FDO_B
Q4100
Q4100
MMBT3904
MMBT3904
+12V_BUS
1
2 3
R41021KR4102
1K
FAN_PWM_INV
R4103 22KR4103 22K
Fan Control
DNI
Q4101
Q4101
Pfb
1
MMBT3906
MMBT3906
C4100
C4100
100nF
100nF
C4102
C4102
1uF
1uF
DNI
+12V_BUS
23
R41061KR4106
1K
+12V_BUS
B4001
B4001
26R_600mA
26R_600mA
R41051KR4105
1K
CUR_SRC
23
Q4102
Q4102
Nfb
R4107 820RR4107 820R
1
MMBT3906
MMBT3906
DNI
Vdiff
1
Q4103
Q4103
3 2
PBSS4350Z
PBSS4350Z
FAN_VE
R41100RR4110
0R
4
C4008
C4008
1uF
1uF
805
16V
Y5V
FAN_OUT_P
FAN_OUT_N
4
FAN_OUT_P
C4103
C4103
1uF_16V
1uF_16V
FAN_OUT_N
Alternate to Q4101 and Q4102.
CUR_SRC
Pfb Nfb
Vdiff
This circuit provides a minimum voltage for the fan,
independent of PWM input.
Pfb
+12V_BUS
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
19 22
of
19 22
of
19 22
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 20
5
D D
H3
H3
C C
HEATSINK
HEATSINK
MT1
MT1
MT_Hole_0.136_in.
MT_Hole_0.136_in.
4
3
2
1
B B
A A
5
4
3
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
20 22
of
20 22
of
20 22
Doc No.
Doc No.
Doc No.
102-B88901-00A
102-B88901-00A
102-B88901-00A
1
RevDate:
RevDate:
RevDate:
01
01
01
www.vinafix.vn
Page 21
5
4
3
2
1
MEMORY CHANNEL A
DDR3 4pcs 64Mx16 (4x128MB)
D D
RANK0 RANK1
DAC2
Debug
POWER REGULATORS
From +12V
+VDDC, VDDCI,
SPV10, +MVDD
From +12V LINEAR:
C C
+5V, +5V_VESA,
From +12V DIRECT:
FAN
From +MVDD Linear (1.1V):
PCIE_VDDC, DPLL_VDDC,
DPx_VDD10
From +3.3V Direct:
VDDR3,
From 3.3V Linear (1.8V)
VDDR4, VDDR5, VDD_CT,
TSVDD, PCIE_VDDR,
PCIE_PVDD, DPLL_PVDD,
VDD1DI, AVDD, DPx_PVDD
CrossFire
Interlink
Header
FAN
Connector
Straps
BIOS
Speed control
& temperature
sense
Built-in PWM
INTERRUPT
Temp. Sensing
Dynamic VDDC
CrossFire
DVOCLK
DVPCNTL_[0..2]
DVPDATA[23:0]
DVP_MVP_CNTL[1:0]
GPIO[2:1]
GENERICB, C, D
GPIO
ROM
Thermal
GPIO17, GPIO6
D+/D-
TS_FDO
GPIO15, GPIO20
POWER DELIVERY
+PCIE_SOURCE
B B
+3.3V
3.3V_BUS
delayed circuit
SMPS Enable
Circuit
+12V_BUS
Temperature Critical
RV710
CTF
PCI-Express
TVO
TMDP
DPB
Clock
Data
DAC2
CRT
H/VSync
HPD2
DDC1
DDCAUX7
LVTMDP
DPE
Clock
Data
DAC1
CRT
H/VSync
HPD1
DDCAUX5
XTALIN
XTALOUT
SL-TMDS
SL-TMDS
Resistor Option
By default, DDC1 is connected
XTAL
TVO Filters
RBG Filters
RBG Filters
AC Coupling Caps
AC Coupling Caps
TVO
Connector
DMS-59 Connector
(2 singlelink DVI-I)
+3.3V_BUS
+12V_BUS
PCI-Express Bus
RH PCIE RV710 DDR3
DVI + DMS-59
REV 09
6 Layer PCB without Dummy Core
A A
5
4
3
(2-2-2 Stackup)
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.
from use of the information included herein.
from use of the information included herein.
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59
RH LP RV710 DDR3 TVO DMS-59
2
RH LP RV710 DDR3 TVO DMS-59
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
Advanced Micro Devices Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Thursday, December 11, 2008
Thursday, December 11, 2008
Thursday, December 11, 2008
Sheet
Sheet
Sheet
of
21 22
of
21 22
of
21 22
1
Doc No.
Doc No.
Doc No.
RevDate:
RevDate:
RevDate:
01
01
01
102-B88901-00A
102-B88901-00A
102-B88901-00A
www.vinafix.vn
Page 22
5
Title
Title
Title
RH LP RV710 DDR3 TVO DMS-59 Thursday, December 11, 2008
RH LP RV710 DDR3 TVO DMS-59 Thursday, December 11, 2008
RH LP RV710 DDR3 TVO DMS-59 Thursday, December 11, 2008
REVISION HISTORY
REVISION HISTORY
REVISION HISTORY
D D
Sch
Sch
Sch
Rev
Rev
Rev
PCB
PCB
PCB
Rev
Rev
Rev
00A01
Date
Date
Date
2008.11.11
RV710
INITIAL RELEASE OF B889 BOARD. BASED ON B754 Rev 90.
4
NOTE:
NOTE:
NOTE:
3
102-B88901-00A
102-B88901-00A
102-B88901-00A
This schematic represents the PCB, it does not represent any specific SKU.
This schematic represents the PCB, it does not represent any specific SKU.
This schematic represents the PCB, it does not represent any specific SKU.
For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.
For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.
For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.
Please contact AMD representative to obtain latest BOM closest to the application desired.
Please contact AMD representative to obtain latest BOM closest to the application desired.
Please contact AMD representative to obtain latest BOM closest to the application desired.
REVISION DESCRIPTION
REVISION DESCRIPTION
REVISION DESCRIPTION
2
Date:Schematic No.
Date:Schematic No.
Date:Schematic No.
1
Rev
Rev
Rev
01
01
01
02 00A
03 00A
00A04
00A05
C C
B B
06
07
08
09
00A
00A
00A
00A
2008.11.12
2008.11.13
2008.11.19
2008.11.19
2008.11.19
2008.11.24
2008.11.25
2008.12.01
ADD R67 AS OPTION TO SHORT JTAG IO
REMOVE MT2
REMOVE MVDD GPIO VOLTAGE CONTROL OPTION
REMOVE LED AND PWR_GOOD CONNECTIONS TO CTF CIRCUIT
REMOVE MC625, PL601, NL601, ML601, R58 AND PROVIDE OPTION TO SHORT CTF TO CTF_VCNTL BY R4062
CHANGE DAC INDUCTORS TO 0603 PART, REMOVE C1001-C1003 and C2001-C2003
REMOVE R26, CHANGE MVDD FET SYMBOL
CHANGE PIN ASSIGNMENT OF D2001 AND REG1603 FOR LAYOUT
A A
5
4
3
2
1
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