Page 1
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
ASSEMBLYNVPNVARIANT
B
1
2
SKU
3
4
5
6
12
13
14
7
8
9
10
11
15
G94-P547-A00 - GDDR3, DVI/VGA + DVI/VGA + HDTV/SDTV-Out
BASE
sku0011
<UNDEFINED
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
600-10547-base-000
600-10547-0011-000
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
P547 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
G94-400 650MHz/900MHz 512MB 16Mx32 BGA136 GDDR3, DVI-I-DL+DVI-I-DL
<UNDEFINED
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
Table of Contents:
Page 1: Overview
Page 2: PCI Express
Page 3: MEMORY: GPU Partition A/B
Page 4: MEMORY: GPU Partition C/D
Page 5: FBA Partition
Page 6: FBA Partition Decoupling
REVISION HISTORY:
Page 7: FBB Partition
Page 8: FBB Partion Decoupling
Page 9: FBC Partition
Page 10: FBC Partition Decoupling
Page 11: FBD Partition
Page 12: FBD Partition Decoupling
Page 13: FB Net Properties
Page 14: DACA Interface
Page 15: DACC Interface
Page 16: IFP A/B Interface -- DVI Connector South
Page 17: IFP C/D Interface -- DVI Connector MID
Page 18: IFP E/F Interface -- Unused
Page 19: DACB and HDTV/SDTV-Out
Page 20: MIO A/B Interface
Page 21: MISC: GPIO, I2C, ROM, HDCP, and XTAL
Page 22: Strap Configuration
Page 23: PWR and GND Signals
Page 24: NVVDD and FBVDDQ Decoupling
Page 25: SPDIF Input, Backdrive Protection, and IFP_IOVDD Power Supply
Page 26: PS I: 12V and 12V_EXT Power Supply Filter
Page 27: PS II: IFP_PLLVDD, 2V5, 5V, and DDC_5V Power Supply
Page 28: PS III: FBVDDQ Power Supply
Page 29: PS IV: NVVDD Power Supply
Page 30: BLANK
Page 31: Fan Connector
Page 32: Thermal, Mechanical, and Bracket
Overview
www.vinafix.vn
600-10547-0011-000 A
design
rachen
1 OF 32
07-AUG-2008
Page 2
J501
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTINOUT
OUTINOUT
OUT
KEY
TRST*
TCK
GND
TMS
TDO
VCC
TDI
OUT
1/19 PCI_EXPRESS
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
VDD33
VDD33
VDD33
VDD33
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
VDD33
GND_SENSE
VDD_SENSE
PEX_PLLVDD
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
PEX_CAL_PU_GND
PEX_TERMP
TESTMODE
PEX_CAL_PD_VDDQ
PEX_TX0
PEX_CLKREQ
PEX_REFCLK
PEX_REFCLK
PEX_RST
PEX_TX0
PEX_TX3
PEX_TX3
PEX_TX2
PEX_TX2
PEX_TX1
PEX_TX1
PEX_RX3
PEX_RX3
PEX_RX2
PEX_RX2
PEX_RX1
PEX_RX1
PEX_RX0
PEX_RX0
PEX_TX7
PEX_TX6
PEX_TX6
PEX_TX5
PEX_TX5
PEX_TX4
PEX_TX4
PEX_RX6
PEX_RX6
PEX_RX5
PEX_RX5
PEX_RX4
PEX_RX4
PEX_TX7
PEX_TX10
PEX_TX10
PEX_TX9
PEX_TX9
PEX_TX8
PEX_TX8
PEX_RX10
PEX_RX9
PEX_RX9
PEX_RX8
PEX_RX8
PEX_RX7
PEX_RX7
PEX_TX13
PEX_TX13
PEX_TX12
PEX_TX12
PEX_TX11
PEX_TX11
PEX_RX13
PEX_RX13
PEX_RX12
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_TX14
PEX_TX15
PEX_TX15
PEX_TX14
PEX_RX15
PEX_RX15
PEX_RX14
PEX_RX14
OUT
OUT
OUT
END OF X8
END OF X16
END OF X1
END OF X4
TCLK JTAG2
TMS JTAG5
TDO JTAG4
TDI JTAG3
WAKE
SMDAT
SMCLK
PERN0
PERP0
REFCLK
PERST
REFCLK
PETN1
PERP2
PETN0
PERP1
PERN1
PETP0
PETP1
PERN3
PETP3
PETN3
PETP2
PERP3
PETN2
PERN2
PERP4
PERN4
PETN4
PERP5
PETP4
PERN5
PETP5
PETP6
PERN6
PERP6
PETN5
PERP7
PETN6
PERN7
PETN8
PETP8
PERP8
PETN7
PETP7
PERN8
PERN9
PERP9
PERP10
PERN10
PETP10
PETP9
PETN9
PETN10
PETN11
PERP12
PERN12
PERP11
PERN11
PETP11
PETN12
PETP12
PETN13
PERP13
PERN13
PETP13
PERP14
PERN15
PETP15
PETN15
PERN14
PETN14
PETP14
PERP15
TRST* JTAG1+12V
+12V/RSVD
+3V3AUX
+12V
+12V
+12V
+3V3
+3V3
+3V3
PRSNT2
PRSNT1
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
GND
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
1
3
5
7
HDR_2F4
FEMALE
1.274MM
0
KEY6_JTAG_SMALL
NO STUFF
AT18
AT24
AT25
AU15
AU16
AU19
AU22
AM17
AM18
AM19
AM20
AM24
AM25
AM26
AM27
AM28
AP18
AP19
AP21
AP22
AP24
AP25
AP27
AR15
AR16
AR18
AR19
AR21
AR22
AR24
AR25
AR27
AT15
AT16
AT19
AT21
AT22
L11
L12
L13
M11
N11AW21
NVVDD_SENSE_GPU
AJ22
NVVDD_GND_SENSE_GPU
AJ21
PEX_PLL_CLK_OUT
AP16
PEX_PLL_CLK_OUT*
AP17
12MIL
PEX_PLLVDD
AM16
GPU_TESTMODE
BB27
12MIL
PEX_CAL_PD_VDDQ
AM21
PEX_CAL_PU_GND
AM22
12MIL
PEX_TERMP
AM23
12MIL
PCI Express
2
4
8
Place near balls
Place near balls
3V3
www.vinafix.vn
.1UF
10V
10%
.1UF
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UFC696
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
21>
21>
C796
0402
C782
0402
C773
0402
C756
0402
C741
0402
C726
0402 10V
C706
C686
0402
C661
0402
C638
0402
C624
0402
C614
0402
C604
0402
C601
25<
2>
SNN_PEX_CLKREQ*
.1UF
10%
10V0402
X5R
.1UF
10V
.1UF
10%
10V
X5R
.1UF
10%
10V
X5R
.1UF
10%
10V
X5R
.1UF
10%
10V
X5R
.1UF
10%
X5R
.1UF
10%
10V0402
X5R
.1UF
10%
10V
X5R
.1UF
10%
10V
X5R
.1UF
10%
10V
X5R
.1UF
10%
10V
X5R
.1UF
10%
10V0402
X5R
.1UFC606
10%
10V
X5R
.1UF
10%
10V
X5R
.1UF
10%
10V0402
X5R
R703
0402
R691
0402
R711
0402
R713
0402
R714
0402
PEX_TX0
PEX_TX0*
COMMON
PEX_TX1
PEX_TX1* AW14
10%
COMMON
X5R
PEX_TX2
PEX_TX2*
COMMON
PEX_TX3
PEX_TX3*
COMMON
PEX_TX4
PEX_TX4*
COMMON
PEX_TX5
PEX_TX5*
COMMON
PEX_TX6
PEX_TX6*
COMMON
PEX_TX7
PEX_TX7*
COMMON
PEX_TX8 AV21
PEX_TX8*
COMMON
PEX_TX9
PEX_TX9*
COMMON
PEX_TX10
PEX_TX10*
COMMON
PEX_TX11
PEX_TX11*
COMMON
PEX_TX12
PEX_TX12*
COMMON
PEX_TX13
PEX_TX13*
COMMON
PEX_TX14
PEX_TX14*
COMMON
PEX_TX15
PEX_TX15*
COMMON
5%
5%
5%
5%
5%
0
NO STUFF
0
NO STUFF
0
NO STUFF
0
NO STUFF
0
NO STUFF
AW10
AY10
AW11
AW12
AU13
AV13
AY12
BA12
AW13
BB12
BB13
AW15
AV15
BA13
AY13
AV16
AW16
AY15
BA15
AW17
AW18
BB15
BB16
AV18
AU18
BA16
AY16
AV19
AW19
AY18
BA18
AW20
BB18
BB19
AU21
BA19
AY19
AV22
AW22
AY21
BA21
AW23
AW24
BB21
BB22
AV24
AU24
BA22
AY22
AU25
AV25
AY24
BA24
AW25
AW26
BB24
BB25
AW27
AV27
BA25
AY25
AU27
AT27
AY27
BA27
JTAG_TRST*
JTAG_TCLK
JTAG_TDI
JTAG_TDO
JTAG_TMS
G1
G94-400-A1
BGA1504
COMMON
C834
4.7UF
16V
10%
X7R
1206
COMMON
C823
.1UF
16V
10%
X7R
0402
COMMON
C33
0402
NO STUFF
C835
4.7UF
16V
10%
X7R
1206
COMMON
GND
3V3_AUX
.1UF
10V
10%
X5R
PEX_PRSNT*
SNN_PE_PRSNT2_A
SNN_PE_RSVD1
SNN_PE_PRSNT2_B
SNN_PE_RSVD2
SNN_PE_RSVD3
SNN_PE_RSVD4
GND
SNN_PE_PRSNT2_C
SNN_PE_RSVD5
PEX_PRSNT*
SNN_PE_RSVD6
SNN_PE_RSVD7
C836
.1UF
16V
10%
X7R
0402
COMMON
CN2
CON_X16
NO STUFF
CON_PCIEXP_X16_EDGE
B1
B2
A2
A3
B3
B8
A9
A10
B10
A1
B17
B12
B4
A4
B7
A12
B13
A15
B16
B18
A18
GND
B31
A19
B30
A32
A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32
B48
A33
A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49
GND
B81
A50
B82
A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82
GND
B9
A5
A6
A7
A8
B5
B6
B11
A11
A13
A14
A16
A17
B14
B15
A21
A22
B19
B20
A25
A26
B23
B24
A29
A30
B27
B28
A35
A36
B33
B34
A39
A40
B37
B38
A43
A44
B41
B42
A47
A48
B45
B46
A52
A53
B50
B51
A56
A57
B54
B55
A60
A61
B58
B59
A64
A65
B62
B63
A68
A69
B66
B67
A72
A73
B70
B71
A76
A77
B74
B75
A80
A81
B78
B79
PEX_TRST*
PEX_TCLK
PEX_TDI
PEX_TDO
PEX_TMS
PEX_SMCLK
PEX_SMDAT
SNN_PEX_WAKE*
PEX_RST*
PEX_REFCLK
PEX_REFCLK*
PEX_TXX0
PEX_TXX0*
PEX_RX0
PEX_RX0*
PEX_TXX1
PEX_TXX1*
PEX_RX1
PEX_RX1*
PEX_TXX2
PEX_TXX2*
PEX_RX2
PEX_RX2*
PEX_TXX3
PEX_TXX3*
PEX_RX3
PEX_RX3*
PEX_TXX4
PEX_TXX4*
PEX_RX4
PEX_RX4*
PEX_TXX5
PEX_TXX5*
PEX_RX5
PEX_RX5*
PEX_TXX6
PEX_TXX6*
PEX_RX6
PEX_RX6*
PEX_TXX7
PEX_TXX7*
PEX_RX7
PEX_RX7*
PEX_TXX8
PEX_TXX8*
PEX_RX8
PEX_RX8*
PEX_TXX9
PEX_TXX9*
PEX_RX9
PEX_RX9*
PEX_TXX10
PEX_TXX10*
PEX_RX10
PEX_RX10*
PEX_TXX11
PEX_TXX11*
PEX_RX11
PEX_RX11*
PEX_TXX12
PEX_TXX12*
PEX_RX12
PEX_RX12*
PEX_TXX13
PEX_TXX13*
PEX_RX13
PEX_RX13*
PEX_TXX14
PEX_TXX14*
PEX_RX14
PEX_RX14*
PEX_TXX15
PEX_TXX15*
PEX_RX15
PEX_RX15*
C800
0402
COMMON
X5R
C795
0402 10V C794
COMMON
X5R
C784
0402
COMMON
X5R
C778
0402
COMMON
X5R
C761
0402
COMMON
X5R
C745
0402
COMMON
X5R
C734
0402
COMMON
X5R
C714
0402
COMMON
X5R
0402
COMMON
X5R
C665
0402
COMMON
X5R
C642
0402
COMMON
X5R
C625
0402
COMMON
X5R
C617
0402
COMMON
X5R
C608
0402
COMMON
X5R
C605
0402
COMMON
X5R
C603
0402
COMMON
X5R
R712
0
5%
0402
NO STUFF
Page2: PCI Express
12V
3V3
C824
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
3V3
R690
R715
GND
C656
.1UF
10V
10%
X5R
0402
COMMON
C668
10V
10%
X5R
0402
COMMON
R710
10K
5%
0402
COMMON
C682
.1UF
10V
10%
X5R
0402
COMMON
C689
.1UF.1UF
10V
10%
X5R
0402
COMMON
10K
5%
0402
COMMON
R702
10K
5%
0402
COMMON
GND
C666
1UF
6.3V
10%
X5R
0603
COMMON
C681
1UF
6.3V
10%
X5R
0603
COMMON
180
5%
0402
COMMON
R687
270
5%
0402
COMMON
JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
C659
1UF
6.3V
10%
X5R
0603
C653
6.3V
10%
X5R
0603
Matching Rule of Thumb
4 inch from Top of Gold Fingers to GPU
*2 inch Lane to Lane Skew
*No real Skew rule, but reducing the skew will minimize latency
VDD33
R620
0402
R619
0402
C725
.47UF
6.3V
10%
X5R
0402
COMMON
C673
.1UF
10V
10%
X5R
0402
COMMON
1%
1%
2.49K
COMMON
2.49K
COMMON
C716
.47UF
6.3V
10%
X5R
0402
COMMON
C718
1UF
6.3V
10%
X5R
0402
COMMON
SHOULD BE PLACED ON THE BOTTOM LAYER
R623
0402
10K
R616
COMMON
0402
5%
R618
0402
C768
.1UF
10V
10%
X5R
0402
COMMON
200
COMMON
5%
2.49K
COMMON
1%
C698
.1UF
6.3V
10%
X7R
0402
COMMON
PEX_VDD
JTAG
C693
4.7UF
6.3V
10%
X5R
0603
COMMONCOMMON
C708
4.7UF1UF
6.3V
10%
X5R
0603
COMMONCOMMON
C717
1UF
6.3V
10%
X5R
0402
COMMON
GND
C669
1UF
6.3V
10%
X5R
0402
COMMON
GND
GND
L501
2>
2>
2>
2<
2>
C731
.1UF
10V
10%
X5R
0402
COMMON
2>
0402
21<
21<
21<
21>
21<
C650
10UF
10V
10%
X5R
0805
COMMON
C651
10UF
10V
10%
X5R
0805
COMMON
29<
LB502
C690
1UF
6.3V
10%
X5R
0402
COMMON
2>
2>
2>
2<
2>
PEX_VDD
3V3
C723
1UF
6.3V
10%
X5R
0603
COMMON
GND
10nH
NO STUFF
0402 COMMON
21<
21<
21<
21>
21<
1V1_PLL
GND
10nH
C695
4.7UF
6.3V
10%
X5R
0603
NO STUFF
PEX_VDD
GND
C654
4.7UF
6.3V
10%
X5R
0603
COMMON
2> 25<
29< 2>
PEX_REFCLK
PEX_REFCLK*
PEX_TXX0
PEX_TXX0*
PEX_TXX1
PEX_TXX1*
PEX_TXX2
PEX_TXX2*
PEX_TXX3
PEX_TXX3*
PEX_TXX4
PEX_TXX4*
PEX_TXX5
PEX_TXX5*
PEX_TXX6
PEX_TXX6*
PEX_TXX7
PEX_TXX7*
PEX_TXX8
PEX_TXX8*
PEX_TXX9
PEX_TXX9*
PEX_TXX10
PEX_TXX10*
PEX_TXX11
PEX_TXX11*
PEX_TXX12
PEX_TXX12*
PEX_TXX13
PEX_TXX13*
PEX_TXX14
PEX_TXX14*
PEX_TXX15
PEX_TXX15*
PEX_RX0
PEX_RX0*
PEX_RX1
PEX_RX1*
PEX_RX2
PEX_RX2*
PEX_RX3
PEX_RX3*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_RX14
PEX_RX14*
PEX_RX15
PEX_RX15*
PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*
PEX_RST*
PEX_PRSNT*
GPU_TESTMODE
NVVDD_SENSE_GPU
PEX_PLLVDD
90DIFF1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 90DIFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 90DIFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
1.1V
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
50OHM
50OHM
50OHM
0.16A
600-10547-0011-000 A
design
rachen
DIFFPAIRNV_IMPEDANCENV_CRITICALNET
PEX_REFCLK
PEX_REFCLK
PEX_TXX0
PEX_TXX0
PEX_TXX1
PEX_TXX1
PEX_TXX2
PEX_TXX2
PEX_TXX3
PEX_TXX3
PEX_TXX4
PEX_TXX4
PEX_TXX5
PEX_TXX5
PEX_TXX6
PEX_TXX6
PEX_TXX7
PEX_TXX7
PEX_TXX8
PEX_TXX8
PEX_TXX9
PEX_TXX9
PEX_TXX10
PEX_TXX10
PEX_TXX11
PEX_TXX11
PEX_TXX12
PEX_TXX12
PEX_TXX13
PEX_TXX13
PEX_TXX14
PEX_TXX14
PEX_TXX15
PEX_TXX15
PEX_RX0
PEX_RX0
PEX_RX1
PEX_RX1
PEX_RX2
PEX_RX2
PEX_RX3
PEX_RX3
PEX_RX4
PEX_RX4
PEX_RX5
PEX_RX5
PEX_RX6
PEX_RX6
PEX_RX7
PEX_RX7
PEX_RX8
PEX_RX8
PEX_RX9
PEX_RX9
PEX_RX10
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_RX12
PEX_RX13
PEX_RX13
PEX_RX14
PEX_RX14
PEX_RX15
PEX_RX15
PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT
MIN_WIDTHMAX_CURRENTVOLTAGENET
12MIL
2 OF 32
07-AUG-2008
Page 3
Page3: MEMORY: GPU Partition A/B
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
3/19 FBB
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD30
FBB_CMD29
FBB_CMD28
FBB_CMD27
FBB_CMD26
FBB_CMD25
FBB_CLK0
FBB_CLK0
FBB_WCK3
FBB_WCK2
FBB_WCK2
FBB_WCK1
FBB_WCK1
FBB_WCK0
FBB_WCK0
FBB_DEBUG
FBB_CLK1
FBB_CLK1
FBB_WCK3
FB_CAL_TERM_GND
FB_CAL_PU_GND
FB_CAL_PD_VDDQ
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_DQS_RN7
FBB_DBI0
FBB_DBI1
FBB_DBI2
FBB_DBI3
FBB_DBI4
FBB_DBI5
FBB_DBI6
FBB_DBI7
BI
OUT
OUT
OUTINOUT
OUT
OUT
OUT
OUT
OUT
BI
2/19 FBA
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBA_CMD0
FBA_CMD1
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBA_CMD21
FBA_CMD20
FBA_CMD19
FBA_CMD18
FBA_CMD17
FBA_CMD16
FBA_CMD15
FBA_CMD14
FBA_CMD13
FBA_CMD12
FBA_CMD11
FBA_CMD10
FBA_CMD9
FBA_CMD8
FBA_CMD7
FBA_CMD6
FBA_CMD5
FBA_CMD4
FBA_CMD3
FBA_CMD2
FBA_CMD22
FBA_DEBUG
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_WCK3
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBA_WCK0
FBA_WCK0
FBA_WCK1
FBA_WCK1
FBA_WCK2
FBA_WCK2
FBA_WCK3
FB_DLLAVDD0
FB_PLLAVDD0
FBA_D13
FBA_D12
FBA_D11
FBA_D10
FBA_D9
FBA_D8
FBA_D7
FBA_D6
FBA_D5
FBA_D4
FBA_D3
FBA_D2
FBA_D1
FBA_D0
FBA_D14
FBA_D34
FBA_D33
FBA_D32
FBA_D31
FBA_D30
FBA_D29
FBA_D28
FBA_D27
FBA_D26
FBA_D25
FBA_D24
FBA_D23
FBA_D22
FBA_D21
FBA_D20
FBA_D19
FBA_D18
FBA_D17
FBA_D16
FBA_D15
FBA_D54
FBA_D53
FBA_D52
FBA_D51
FBA_D50
FBA_D49
FBA_D48
FBA_D47
FBA_D46
FBA_D45
FBA_D44
FBA_D43
FBA_D42
FBA_D41
FBA_D40
FBA_D39
FBA_D38
FBA_D37
FBA_D36
FBA_D35
FBA_D55
FBA_DQM7
FBA_DQM6
FBA_DQM5
FBA_DQM4
FBA_DQM3
FBA_DQM2
FBA_DQM1
FBA_DQM0
FBA_D63
FBA_D62
FBA_D61
FBA_D60
FBA_D59
FBA_D58
FBA_D57
FBA_D56
FBA_DQS_WP7
FBA_DQS_WP6
FBA_DQS_WP5
FBA_DQS_WP4
FBA_DQS_WP3
FBA_DQS_WP2
FBA_DQS_WP1
FBA_DQS_WP0
FBA_DQS_RN7
FBA_DQS_RN6
FBA_DQS_RN5
FBA_DQS_RN4
FBA_DQS_RN3
FBA_DQS_RN2
FBA_DQS_RN1
FBA_DQS_RN0
FBA_DBI7
FBA_DBI6
FBA_DBI5
FBA_DBI4
FBA_DBI3
FBA_DBI2
FBA_DBI1
FBA_DBI0
FB_VREF
IN
OUT
OUT
OUT
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
G1
G94-400-A1
BGA1504
13<> 5<>
13> 5<>
13> 5<>
13<
5<>
FBA_D<63..0>
FBA_DQM<7..0>
FBA_DQS_WP<7..0>
FBA_DQS_RN<7..0>
FBVDDQ
R598
511
1%
0402
COMMON
R600
1.3K
1%
0402
COMMON
GND
13<>
C613
.1UF
6.3V
10%
X7R
0402
COMMON
FBA_D<0>
0
FBA_D<1>
1
FBA_D<2>
2
FBA_D<3>
3
FBA_D<4>
4
FBA_D<5>
5
FBA_D<6>
6
FBA_D<7>
7
FBA_D<8>
8
FBA_D<9>
9
FBA_D<10>
10
FBA_D<11>
11
FBA_D<12>
12
FBA_D<13>
13
FBA_D<14>
14
FBA_D<15>
15
FBA_D<16>
16
FBA_D<17>
17
FBA_D<18>
18
FBA_D<19>
19
FBA_D<20>
20
FBA_D<21>
21
FBA_D<22>
22
FBA_D<23>
23
FBA_D<24>
24
FBA_D<25>
25
FBA_D<26> AN39
26
FBA_D<27>
27
FBA_D<28>
28
FBA_D<29>
29
FBA_D<30>
30
FBA_D<31>
31
FBA_D<32>
32
FBA_D<33>
33
FBA_D<34>
34
FBA_D<35>
35
FBA_D<36>
36
FBA_D<37>
37
FBA_D<38>
38
FBA_D<39>
39
FBA_D<40>
40
FBA_D<41>
41
FBA_D<42>
42
FBA_D<43>
43
FBA_D<44>
44
FBA_D<45>
45
FBA_D<46>
46
FBA_D<47>
47
FBA_D<48>
48
FBA_D<49>
49
FBA_D<50>
50
FBA_D<51>
51
FBA_D<52>
52
FBA_D<53>
53
FBA_D<54>
54
FBA_D<55>
55
FBA_D<56>
56
FBA_D<57>
57
FBA_D<58>
58
FBA_D<59>
59
FBA_D<60>
60
FBA_D<61>
61
FBA_D<62>
62
FBA_D<63>
63
FBA_DQM<0>
0
FBA_DQM<1> AM39
1
FBA_DQM<2>
2
FBA_DQM<3>
3
FBA_DQM<4>
4
FBA_DQM<5>
5
FBA_DQM<6>
6
FBA_DQM<7>
7
FBA_DQS_WP<0>
0
FBA_DQS_WP<1>
1
FBA_DQS_WP<2>
2
FBA_DQS_WP<3>
3
FBA_DQS_WP<4>
4
FBA_DQS_WP<5>
5
FBA_DQS_WP<6>
6
FBA_DQS_WP<7>
7
0
FBA_DQS_RN<1>
1
FBA_DQS_RN<2>
2
FBA_DQS_RN<3>
3
FBA_DQS_RN<4>
4
FBA_DQS_RN<5>
5
FBA_DQS_RN<6>
6
FBA_DQS_RN<7>
7
SNN_FBA_DBI<0>
SNN_FBA_DBI<1>
SNN_FBA_DBI<2>
SNN_FBA_DBI<3>
SNN_FBA_DBI<4>
SNN_FBA_DBI<5>
SNN_FBA_DBI<6>
SNN_FBA_DBI<7>
AL34
AK35
AK36
AJ34
AH34
AH35
AJ36
AK37
AL39
AL41
AL42
AK42
AJ39
AH39
AH41
AH42
AN35
AP36
AP37
AR37
AM34
AL35
AL36
AL37
AP41
AP42
AN40
AN41
AN42
AR40
AT39
AR31
AP32
AR33
AT31
AT34
AU34
AU35
AU31
BB33
BA33
AY33
BA34
BB34
AW33
AW36
AY35
AU30
AP28
AP31
AR28
AW28
AP29
AR30
AT30
AW31
BA31
BB31
BB30
AW29
BB28
BA28
AY28
AJ37
AP35
AP40
AR34
AY34
AU29
AW32
AH36
AK41
AM36
AP38
AT33
AV34
AT28
AY30
AH37FBA_DQS_RN<0>
AK40
AN36
AP39
AT32
AW34
AU28
BA30
AH38
AL38
AN38
AR39
AV33
AW35
AT29
AV31
L32FB_VREF
COMMON
AA32
AB32
AC32
AD32
AD34
AE32
AF32
AG32
AG34
AK34
AN34
AP30
AP33
J10
J13
J16
J19
J24
J27
J30
AT40
AU38
AT38
BA39
AV37
BB39
AW38
AW42
AW39
AY41
AU39
AV36
BA40
AY39
AU40
BA37
AY36
AY37
AT37
AU36
AV39
AY38
AV40
AU42
AW40
AU41
AW41
BB37
AW37
AY42
BB40
AT36
AT41
AT42
BA36
BB36
AK38
AK39
AM37
AN37
AU32
AU33
AV30
AH32
AJ32
FBVDDQ
FBA_CMD<0>
FBA_CMD<1>
FBA_CMD<2>
FBA_CMD<3>
FBA_CMD<4>
FBA_CMD<5>
FBA_CMD<6>
SNN_FBA_CMD<7>
FBA_CMD<8>
FBA_CMD<9>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<12>
FBA_CMD<13>
FBA_CMD<14>
FBA_CMD<15>
FBA_CMD<16>
FBA_CMD<17>
FBA_CMD<18>
FBA_CMD<19>
FBA_CMD<20>
FBA_CMD<21>
FBA_CMD<22>
FBA_CMD<23>
FBA_CMD<24>
FBA_CMD<25>
SNN_FBA_CMD<26>
FBA_CMD<27>
SNN_FBA_CMD<28>
SNN_FBA_CMD<29>
SNN_FBA_CMD<30>
FBA_DEBUG
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
SNN_FBA_WDS0
SNN_FBA_WDS0*
SNN_FBA_WDS1
SNN_FBA_WDS1*
SNN_FBA_WDS2
SNN_FBA_WDS2*
SNN_FBA_WDS3
SNN_FBA_WDS3*AW30
FB_PLLAVDD0
7<> 13<>
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
FBA_CMD<27..0>
BGA136[31..0] BGA136[63..32] ADDR
CMD1 CMD1 RAS*
13>
5<
CMD-Addr Map
CMD10 CMD10 CAS*
CMD11 CMD11 WE*
CMD8 CMD8 CS0*
CMD19 CMD19 A<0>
CMD25 CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 CMD21 A<6>
CMD16 CMD16 A<7>
CMD23 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD9 CMD9 A<11>
CMD12 CMD12 BA0
CMD3 CMD3 BA1
CMD27 CMD27 BA2
CMD18 CMD18 CKE
CMD15 CMD15 RST
7<> 13>
FBVDDQ
60.4
R601
NO STUFF
0402
1%
13>
5<
13>
5<
13>
5<
13>
5<
13>
7<>
7<> 13<
PEX_VDD
GND
GND
.1UF
6.3V
10%
X7R
0402
C635C636
1UF
6.3V
10%
X5R
0402
13<>
C633
1UF
6.3V
10%
X5R
0402
COMMONCOMMONCOMMON
LB501
BEAD_0402
120R@100MHz
COMMON
MEMORY: GPU Partition A/B
www.vinafix.vn
FBB_D<63..0>
FBB_DQM<7..0>
FBB_DQS_WP<7..0>
FBB_DQS_RN<7..0>
C644
4.7UF
6.3V
10%
X5R
0603
COMMON
FBB_D<0>
0
FBB_D<1>
1
FBB_D<2>
2
FBB_D<3>
3
FBB_D<4>
4
FBB_D<5>
5
FBB_D<6>
6
FBB_D<7>
7
FBB_D<8>
8
FBB_D<9>
9
FBB_D<10>
10
FBB_D<11>
11
FBB_D<12>
12
FBB_D<13>
13
FBB_D<14>
14
FBB_D<15>
15
FBB_D<16>
16
FBB_D<17>
17
FBB_D<18>
18
FBB_D<19>
19
FBB_D<20>
20
FBB_D<21>
21
FBB_D<22>
22
FBB_D<23>
23
FBB_D<24>
24
FBB_D<25>
25
FBB_D<26>
26
FBB_D<27>
27
FBB_D<28>
28
FBB_D<29>
29
FBB_D<30>
30
FBB_D<31>
31
FBB_D<32>
32
FBB_D<33>
33
FBB_D<34>
34
FBB_D<35>
35
FBB_D<36>
36
FBB_D<37>
37
FBB_D<38>
38
FBB_D<39>
39
FBB_D<40>
40
FBB_D<41>
41
FBB_D<42>
42
FBB_D<43>
43
FBB_D<44>
44
FBB_D<45>
45
FBB_D<46>
46
FBB_D<47>
47
FBB_D<48>
48
FBB_D<49>
49
FBB_D<50>
50
FBB_D<51>
51
FBB_D<52>
52
FBB_D<53>
53
FBB_D<54>
54
FBB_D<55>
55
FBB_D<56>
56
FBB_D<57>
57
FBB_D<58>
58
FBB_D<59>
59
FBB_D<60>
60
FBB_D<61>
61
FBB_D<62>
62
FBB_D<63>
63
FBB_DQM<0>
0
FBB_DQM<1>
1
FBB_DQM<2>
2
FBB_DQM<3>
3
FBB_DQM<4>
4
FBB_DQM<5>
5
FBB_DQM<6>
6
FBB_DQM<7>
7
FBB_DQS_WP<0>
0
FBB_DQS_WP<1>
1
FBB_DQS_WP<2>
2
FBB_DQS_WP<3>
3
FBB_DQS_WP<4>
4
FBB_DQS_WP<5>
5
FBB_DQS_WP<6>
6
FBB_DQS_WP<7>
7
FBB_DQS_RN<0>
0
FBB_DQS_RN<1>
1
FBB_DQS_RN<2>
2
FBB_DQS_RN<3>
3
FBB_DQS_RN<4>
4
FBB_DQS_RN<5>
5
FBB_DQS_RN<6>
6
FBB_DQS_RN<7>
7
SNN_FBB_DBI<0>
SNN_FBB_DBI<1>
SNN_FBB_DBI<2>
SNN_FBB_DBI<3>
SNN_FBB_DBI<4>
SNN_FBB_DBI<5>
SNN_FBB_DBI<6>
SNN_FBB_DBI<7>
C40
E39
F37
H37
G38
G39
H39
C41
D40
D41
C42
D42
H40
G41
G42
J37
K37
J38
J39
L36
M34
M35
M36
J40
J41
J42
K39
L39
M38
M39
M40
W35
W36
W37
W38
AA34
AA35
AA36
AA37
W40
AA40
AA41
AA42
AB40
AB41
AB42
AD40
AB34
AB35
AB36
AB37
AE35
AE36
AE37
AG36
AD41
AD42
AE38
AF39
AE42
AG40
AG41
AG42
G37
F41
L37
K42
AA38
AC39
AE34
AE41
F39
F40
K35
K41
Y39
AB39
AD36
AE40
F38
E40
K36
K40
W39
AB38
AD35
AE39
H36
F42
L34
K38
AA39
AD39
AG35
AG39
G1
G94-400-A1
BGA1504
COMMON
CALIBRATION PIN
FB_CALx_PD_VDDQ
FB_CALx_PU_GND
FB_CALx_TERM_GND
VREF RATIO
DDR3
60
40
40
0.7 FBVDDQ
FBVDDQ
J33
K34
K9
L17
L18
L19
L20G40
L23
L24
L25
L26
L27
R609
0402
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
0
1
2
3
4
5
6
8
9
1%
FBB_CMD<27..0>
60.4
NO STUFF
FBB_CMD<0>
N41
FBB_CMD<1>
R39
FBB_CMD<2>
N42
FBB_CMD<3>
V37
FBB_CMD<4>
T41
FBB_CMD<5>
T42
FBB_CMD<6>
V38
SNN_FBB_CMD<7>
R38
FBB_CMD<8>
N40
FBB_CMD<9>
U39
FBB_CMD<10>
N39
FBB_CMD<11>
V40
FBB_CMD<12>
R41
FBB_CMD<13>
V39
FBB_CMD<14>
P39
FBB_CMD<15>
V36
FBB_CMD<16>
V41
FBB_CMD<17>
T39
FBB_CMD<18>
T38
FBB_CMD<19>
T35
FBB_CMD<20>
T36
FBB_CMD<21>
T40
FBB_CMD<22>
R37
FBB_CMD<23>
M41
FBB_CMD<24>
T37
FBB_CMD<25>
M42
SNN_FBB_CMD<26>
R36
FBB_CMD<27>
V35
SNN_FBB_CMD<28>
V42
SNN_FBB_CMD<29>
R42
SNN_FBB_CMD<30>
R40
FBB_DEBUG
R34
FBB_CLK0
N37
FBB_CLK0*
N38
FBB_CLK1
U34
FBB_CLK1*
V34
SNN_FBB_WDS0
J35
SNN_FBB_WDS0*
J36
SNN_FBB_WDS1
N35
SNN_FBB_WDS1*
N36
SNN_FBB_WDS2
W41
SNN_FBB_WDS2*
W42
SNN_FBB_WDS3
AD37
SNN_FBB_WDS3*
AD38
FB_CAL_PD_VDDQ
M32
FB_CAL_PU_GND
N32
FB_CAL_TERM_GND
P32
600-10547-0011-000 A
design
rachen
7<
7<
7<
7<
R613
R608
R607
0402
0402
0402
FBVDDQ
13>
13>
13>
13>
13> 7<
FBVDDQ
54.9
COMMON
1%
40.2
COMMON
1%
40.2
COMMON
1%
GND
3 OF 32
07-AUG-2008
Page 4
Page4: MEMORY: GPU Partition C/D
OUT
OUT
OUT
OUT
OUT
OUT
OUT
5/19 FBD
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
FBD_CMD7
FBD_CMD8
FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD30
FBD_CMD29
FBD_CMD28
FBD_CMD27
FBD_CMD26
FBD_CMD25
FBD_CLK0
FBD_CLK0
FBD_WCK3
FBD_WCK2
FBD_WCK2
FBD_WCK1
FBD_WCK1
FBD_WCK0
FBD_WCK0
FBD_DEBUG
FBD_CLK1
FBD_CLK1
FBD_WCK3
FB_VDDQ_SENSE
FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63
FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7
FBD_DQS_RN0
FBD_DQS_RN1
FBD_DQS_RN2
FBD_DQS_RN3
FBD_DQS_RN4
FBD_DQS_RN5
FBD_DQS_RN6
FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7
FBD_DQS_RN7
FBD_DBI0
FBD_DBI1
FBD_DBI2
FBD_DBI3
FBD_DBI4
FBD_DBI5
FBD_DBI6
FBD_DBI7
BI
OUT
OUT
OUTINOUT
OUT
OUT
OUT
OUT
OUT
BI
4/19 FBC
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD30
FBC_CMD29
FBC_CMD28
FBC_CMD27
FBC_CMD26
FBC_CMD25
FBC_CLK0
FBC_CLK0
FBC_WCK3
FBC_WCK2
FBC_WCK2
FBC_WCK1
FBC_WCK1
FBC_WCK0
FBC_WCK0
FBC_DEBUG
FBC_CLK1
FBC_CLK1
FBC_WCK3
FB_PLLAVDD1
FB_DLLAVDD1
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
FBC_DQS_RN7
FBC_DBI0
FBC_DBI1
FBC_DBI2
FBC_DBI3
FBC_DBI4
FBC_DBI5
FBC_DBI6
FBC_DBI7
OUT
OUT
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
G1
G94-400-A1
BGA1504
13<> 9<>
13>
13>
13<
9<>
9<>
9<>
FBC_D<63..0>
FBC_DQM<7..0>
FBC_DQS_WP<7..0>
FBC_DQS_RN<7..0>
FBC_D<0>
0
FBC_D<1>
1
FBC_D<2>
2
FBC_D<3>
3
FBC_D<4>
4
5
FBC_D<6>
6
FBC_D<7>
7
FBC_D<8>
8
FBC_D<9>
9
FBC_D<10>
10
FBC_D<11>
11
FBC_D<12>
12
FBC_D<13>
13
FBC_D<14>
14
FBC_D<15>
15
FBC_D<16>
16
FBC_D<17>
17
FBC_D<18>
18
FBC_D<19>
19
FBC_D<20>
20
FBC_D<21>
21
FBC_D<22>
22
FBC_D<23>
23
FBC_D<24>
24
FBC_D<25>
25
FBC_D<26> B22
26
FBC_D<27>
27
FBC_D<28>
28
FBC_D<29>
29
FBC_D<30>
30
FBC_D<31>
31
FBC_D<32>
32
FBC_D<33>
33
FBC_D<34>
34
FBC_D<35>
35
FBC_D<36>
36
FBC_D<37>
37
FBC_D<38>
38
FBC_D<39>
39
FBC_D<40>
40
FBC_D<41>
41
FBC_D<42>
42
FBC_D<43>
43
FBC_D<44>
44
FBC_D<45>
45
FBC_D<46>
46
FBC_D<47>
47
FBC_D<48>
48
FBC_D<49>
49
FBC_D<50>
50
FBC_D<51>
51
FBC_D<52>
52
FBC_D<53>
53
FBC_D<54>
54
FBC_D<55>
55
FBC_D<56>
56
FBC_D<57>
57
FBC_D<58>
58
FBC_D<59>
59
FBC_D<60>
60
FBC_D<61>
61
FBC_D<62>
62
FBC_D<63>
63
FBC_DQM<0>
0
FBC_DQM<1> B18
1
FBC_DQM<2>
2
FBC_DQM<3>
3
FBC_DQM<4>
4
FBC_DQM<5>
5
FBC_DQM<6>
6
FBC_DQM<7>
7
FBC_DQS_WP<0>
0
FBC_DQS_WP<1>
1
FBC_DQS_WP<2>
2
FBC_DQS_WP<3>
3
FBC_DQS_WP<4>
4
FBC_DQS_WP<5>
5
FBC_DQS_WP<6>
6
FBC_DQS_WP<7>
7
FBC_DQS_RN<0>
0
FBC_DQS_RN<1>
1
FBC_DQS_RN<2>
2
FBC_DQS_RN<3>
3
FBC_DQS_RN<4>
4
FBC_DQS_RN<5>
5
FBC_DQS_RN<6>
6
FBC_DQS_RN<7>
7
SNN_FBC_DBI<0>
SNN_FBC_DBI<1>
SNN_FBC_DBI<2>
SNN_FBC_DBI<3>
SNN_FBC_DBI<4>
SNN_FBC_DBI<5>
SNN_FBC_DBI<6>
SNN_FBC_DBI<7>
J21
H21
G21
F21
F18
G18FBC_D<5>
H18
G16
B16
A16
B19
A19
D17
E18
A18
C16
H24
G24
F24
E24
J22
H22
G22
F22
C24
C22
A22
C21
B21
A21
C19
F34
F33
E34
D34
G32
J31
H31
G31
C34
B34
A34
D33
D32
E31
D31
C31
D39
D38
G36
F35
E36
D36
C36
D35
B40
C39
B39
A40
A39
C35
B36
A36
J18
E22
D20
F32
A33
F36
B37
G19
C18
D23
D21
H33
B33
D37
C37
H19
D18
D24
E21
G33
C33
E37
C38
H16
D16
D22
D19
J32
E33
G35
A37
COMMON
N34
N9
R32
T32
T34
U32
V32
W32
W34
Y32
C25
A27
E25
D30
D28
E28
G27
D27
C30
B28
B25
A30
D26
F27
F25
B31
B30
D29
A28
E27
C27
G28
B27
G25
H27
H25
A25
A31
F28
C28
D25
J28
J26
J25
F30
E30
F19
E19
B24
A24
H30
G30
H34
G34
L21
L22
FBVDDQ
FBC_CMD<0>
FBC_CMD<1>
FBC_CMD<2>
FBC_CMD<3>
FBC_CMD<4>
FBC_CMD<5>
FBC_CMD<6>
SNN_FBC_CMD<7>
FBC_CMD<8>
FBC_CMD<9>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<12>
FBC_CMD<13>
FBC_CMD<14>
FBC_CMD<15>
FBC_CMD<16>
FBC_CMD<17>
FBC_CMD<18>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<21>
FBC_CMD<22>
FBC_CMD<23>
FBC_CMD<24>
FBC_CMD<25>
SNN_FBC_CMD<26>
FBC_CMD<27>
SNN_FBC_CMD<28>
SNN_FBC_CMD<29>
SNN_FBC_CMD<30>
FBC_DEBUG
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
SNN_FBC_WDS0
SNN_FBC_WDS0*
SNN_FBC_WDS1
SNN_FBC_WDS1*
SNN_FBC_WDS2
SNN_FBC_WDS2*
SNN_FBC_WDS3
SNN_FBC_WDS3*
FB_PLLAVDD1
11<> 13<>
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
FBC_CMD<27..0>
BGA136[31..0] BGA136[63..32] ADDR
13> 9<
CMD-Addr Map
CMD1 CMD1 RAS*
CMD10 CMD10 CAS*
CMD11 CMD11 WE*
CMD8 CMD8 CS0*
CMD19 CMD19 A<0>
CMD25 CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 CMD21 A<6>
CMD16 CMD16 A<7>
CMD23 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD9 CMD9 A<11>
CMD12 CMD12 BA0
CMD3 CMD3 BA1
CMD27 CMD27 BA2
CMD18 CMD18 CKE
CMD15 CMD15 RST
11<> 13>
FBVDDQ
60.4
R615
NO STUFF
0402
1%
13>
9<
13>
9<
13>
9<
13>
9<
13>
11<>
11<> 13<
PEX_VDD
GND
C658
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C688
.1UF
6.3V
10%
X7R
0402
C687
1UF
6.3V
10%
X5R
0402
C675
1UF
6.3V
10%
X5R
0402
COMMONCOMMONCOMMON
LB504
BEAD_0402
13<>
120R@100MHz
COMMON
MEMORY: GPU Partition C/D
www.vinafix.vn
FBD_D<63..0>
FBD_DQM<7..0>
FBD_DQS_WP<7..0>
FBD_DQS_RN<7..0>
FBD_D<0>
0
FBD_D<1>
1
FBD_D<2>
2
FBD_D<3>
3
FBD_D<4>
4
FBD_D<5>
5
FBD_D<6>
6
FBD_D<7>
7
FBD_D<8>
8
FBD_D<9>
9
FBD_D<10>
10
FBD_D<11>
11
FBD_D<12>
12
FBD_D<13>
13
FBD_D<14>
14
FBD_D<15>
15
FBD_D<16>
16
FBD_D<17>
17
FBD_D<18>
18
FBD_D<19>
19
FBD_D<20>
20
FBD_D<21>
21
FBD_D<22>
22
FBD_D<23>
23
FBD_D<24>
24
FBD_D<25>
25
FBD_D<26>
26
FBD_D<27>
27
FBD_D<28>
28
FBD_D<29>
29
FBD_D<30>
30
FBD_D<31>
31
FBD_D<32>
32
FBD_D<33>
33
FBD_D<34>
34
FBD_D<35>
35
FBD_D<36>
36
FBD_D<37>
37
FBD_D<38>
38
FBD_D<39>
39
FBD_D<40>
40
FBD_D<41>
41
FBD_D<42>
42
FBD_D<43>
43
FBD_D<44>
44
FBD_D<45>
45
FBD_D<46>
46
FBD_D<47>
47
FBD_D<48>
48
FBD_D<49>
49
FBD_D<50>
50
FBD_D<51>
51
FBD_D<52>
52
FBD_D<53>
53
FBD_D<54>
54
FBD_D<55>
55
FBD_D<56>
56
FBD_D<57>
57
FBD_D<58>
58
FBD_D<59>
59
FBD_D<60>
60
FBD_D<61>
61
FBD_D<62>
62
FBD_D<63>
63
FBD_DQM<0>
0
FBD_DQM<1>
1
FBD_DQM<2>
2
FBD_DQM<3>
3
FBD_DQM<4>
4
FBD_DQM<5>
5
FBD_DQM<6>
6
FBD_DQM<7>
7
FBD_DQS_WP<0>
0
FBD_DQS_WP<1>
1
FBD_DQS_WP<2>
2
FBD_DQS_WP<3>
3
FBD_DQS_WP<4>
4
FBD_DQS_WP<5>
5
FBD_DQS_WP<6>
6
FBD_DQS_WP<7>
7
FBD_DQS_RN<0>
0
FBD_DQS_RN<1>
1
FBD_DQS_RN<2>
2
FBD_DQS_RN<3>
3
FBD_DQS_RN<4>
4
FBD_DQS_RN<5>
5
FBD_DQS_RN<6>
6
FBD_DQS_RN<7>
7
SNN_FBD_DBI<0>
SNN_FBD_DBI<1>
SNN_FBD_DBI<2>
SNN_FBD_DBI<3>
SNN_FBD_DBI<4>
SNN_FBD_DBI<5>
SNN_FBD_DBI<6>
SNN_FBD_DBI<7>
H12
J11
H10
G12
F12
A10
B10
C10
D10
F13
J15
J12
H15
D15
J14
H13
G13
D12
B12
A12
A13
D14
A15
B15
C15
F14
D11
G10
G15
C13
G11
F15
B13
E10
G14
E12
M9
N8
N7
P9
R9
R8
P7
N6
M4
M2
M1
N1
P4
R4
R2
R1
K8
J7
J6
H6
L9
M8
M7
M6
J2
J1
K4
K3
K2
K1
H3
G4
G9
F9
F8
B9
A9
D7
C8
P6
L4
J8
J3
H9
C9
R7
N2
L7
J5
E9
R6
N3
K7
J4
D9
R5
M5
K5
H4
D8
G1
G94-400-A1
BGA1504
COMMON
R627
0402
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
1%
FBD_CMD<27..0>
60.4
NO STUFF
FBD_CMD<0>
G3
FBD_CMD<1>
F5
FBD_CMD<2>
G5
FBD_CMD<3>
B4
FBD_CMD<4>
E6
FBD_CMD<5>
A4
FBD_CMD<6>
D5
SNN_FBD_CMD<7>
D1
FBD_CMD<8>
D4
FBD_CMD<9>
C2
FBD_CMD<10>
F4
FBD_CMD<11>
E7
FBD_CMD<12>
B3
FBD_CMD<13>
C4
FBD_CMD<14>
F3
FBD_CMD<15>
B6
FBD_CMD<16>
C7
FBD_CMD<17>
C6
FBD_CMD<18>
G6
FBD_CMD<19>
F7
FBD_CMD<20>
E4
FBD_CMD<21>
C5
FBD_CMD<22>
E3
FBD_CMD<23>
F1
FBD_CMD<24>
D3
FBD_CMD<25>
F2
SNN_FBD_CMD<26>
D2
FBD_CMD<27>
A6
SNN_FBD_CMD<28>
D6
SNN_FBD_CMD<29>
C1
SNN_FBD_CMD<30>
A3
FBD_DEBUG
G7
FBD_CLK0
G1
FBD_CLK0*
G2
FBD_CLK1
B7
FBD_CLK1*
A7
SNN_FBD_WDS0
N5
SNN_FBD_WDS0*
N4
SNN_FBD_WDS1
L6
SNN_FBD_WDS1*
K6
SNN_FBD_WDS2
F11
SNN_FBD_WDS2*
F10
SNN_FBD_WDS3
E13
SNN_FBD_WDS3*
D13
FBVDDQ_SENSE
J34
600-10547-0011-000 A
design
rachen
FBVDDQ
13> 11<
13> 11<
13> 11<
13> 11<
28<
4 OF 32
07-AUG-2008
13> 11<
Page 5
OUT
OUTINOUTININ
OUT
MIRRORED
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
VSSA (GND)
VSSA (GND)
VDDA (VDD)
VDDA (VDD)
A12 (32Mx32)
RAS
CS0
CAS
A0
WE
A3
A2
A1
A5
A4
A11
A10
A8/AP
BA1
BA0
A9
A6
A7
BA2
CLK
CLK
NC/RFU
SEN (GND)
CKE
MF (VDDQ)
RESET
ZQ
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
ININOUTININ
NONMIRRORED
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSSQ
VSS
VSS
VSS
VSS
VSS
VREF
VREF
A12 (32Mx32)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
VDDA (VDD)
RAS
CAS
CS0
WE
A0
A2
A3
A4
A5
A1
BA1
A11
A10
A8/AP
BA0
A9
A7
A6
BA2
NC/RFU
SEN (GND)
CLK
CLK
CKE
RESET
MF (GND)
ZQ
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
Page5: FBA Partition
13> 3>
CMD-Addr Map
FBVDDQ
R564
0
FBA_CLK0_TERM
1%
R558
121
0402
COMMON
5%
0402
NO STUFF
1%
13>
C557
.01UF
16V
10%
X7R
0402
COMMON
R555
121
GND
0402
COMMON
3>
13>
3>
13>
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
Minimize the stub length!!
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
13<>
13>
13<
13>
3<>
3>
3<
3>
FBA_D<63..0>
FBA_DQM<7..0>
FBA_DQS_RN<7..0>
FBA_DQS_WP<7..0>
FBA_CMD<27..0>
R566
0
5%
0402
COMMON
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
13<> GND
FBA_DQM<0>
FBA_DQM<1>
FBA_DQM<2>
FBA_DQM<3>
FBA_DQM<4>
FBA_DQM<5>
FBA_DQM<6>
FBA_DQM<7>
FBA_DQS_RN<0>
FBA_DQS_RN<1>
FBA_DQS_RN<2>
FBA_DQS_RN<3>
FBA_DQS_RN<4>
FBA_DQS_RN<5>
FBA_DQS_RN<6>
FBA_DQS_RN<7>
FBA_DQS_WP<0>
FBA_DQS_WP<1>
FBA_DQS_WP<2>
FBA_DQS_WP<3>
FBA_DQS_WP<4>
FBA_DQS_WP<5>
FBA_DQS_WP<6>
FBA_DQS_WP<7>
R568
10K
0402
COMMON
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
27
18
14
15
5%
GND
FBVDDQ
GND
CMD7 CMD7 BA2
FBA_CMD<1>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<8>
FBA_CMD<19>
FBA_CMD<25>
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
FBA_CMD<21>
FBA_CMD<16>
FBA_CMD<23>
FBA_CMD<20>
FBA_CMD<17>
FBA_CMD<9>
FBA_CMD<12>
FBA_CMD<3>
FBA_CMD<27>
FBA_CMD<18>
FBA_CLK0
FBA_CLK0*
SNN_FBA0_NC1
FBA_CMD<14>
FBA_CMD_SENA0
FBA_CMD<15>
FBA_ZQ0
R551
10K
5%
0402
COMMON
GND
C575
.047UF
16V
10%
X7R
0402
COMMON
0
1
2
3
4
5
6
7
32
33
34
35
36
37
38
39
M6
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
R560
243
1%
0603
COMMON
GNDGND
K1
K12
C549
.047UF
16V
10%
X7R
0402
COMMON
J1
J12
FBA_D<0>
FBA_D<1>
FBA_D<2>
FBA_D<3>
FBA_D<4>
FBA_D<5>
FBA_D<6>
FBA_DQM<0>
FBA_DQS_RN<0>
FBA_DQS_WP<0>
FBA_D<32>
FBA_D<33>
FBA_D<34> R3
FBA_D<35>
FBA_D<36>
FBA_D<37>
FBA_D<38>
FBA_D<39>
FBA_DQM<4>
FBA_DQS_RN<4>
FBA_DQS_WP<4>
G10
F11
E11
B10
B11
C11
C10
F10FBA_D<7>
E10
D10
D11
M6
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
L3
N2
M3
R2
T3
T2
M2
N3
P3
P2
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
GND
GND
FBA_VREF0
FBA_VREF2
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQ
DDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBA_D<8>
FBA_D<9>
FBA_D<10>
FBA_D<11>
FBA_D<12>
FBA_D<13>
FBA_D<14>
FBA_D<15>
FBA_DQM<1>
FBA_DQS_RN<1>
FBA_DQS_WP<1>
FBA_D<40>
FBA_D<41>
FBA_D<42>
FBA_D<43>
FBA_D<44>
FBA_D<45>
FBA_D<46>
FBA_D<47>
FBA_DQM<5>
FBA_DQS_RN<5>
FBA_DQS_WP<5>
FBVDDQ
R580
0
FBA_CLK1_TERM
1%
R579
121
0402
COMMON
5%
0402
NO STUFF
1%
13>
C570
.01UF
16V
10%
X7R
0402
COMMON
R574
121
GND
0402
COMMON
3>
13>
3>
13>
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
R584
511
R1
1%
0402
COMMON
13<>
C584R583
1.3K
0402
COMMON
R2
1%
GND
.1UF
10V
10%
X5R
0402
COMMON
R60
511
0402
COMMON
R59
1.3K
0402
COMMON
FBVDDQ
1%
1%
R1
R2
GND
M6
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
M10
M11
L10
N11
R11
T11
T10
R10
N10
P10
P11
G3
F3
F2
E2
C2
C3
B2
B3
E3
D3
D2
COMMON
M7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBA_D<16>
FBA_D<17>
FBA_D<18>
FBA_D<19>
FBA_D<20>
FBA_D<21>
FBA_D<22>
FBA_D<23>
FBA_DQM<2>
FBA_DQS_RN<2>
FBA_DQS_WP<2>
FBA_D<48>
FBA_D<49>
FBA_D<50>
FBA_D<51>
FBA_D<52>
FBA_D<53>
FBA_D<54>
FBA_D<55>
FBA_DQM<6>
FBA_DQS_RN<6>
FBA_DQS_WP<6>
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
GND
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
C46
.1UF
10V
10%
X5R
0402
COMMON
M6
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
R10
T11
T10
R11
N11
L10
M11
M10
N10
P10
P11
M7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
E2
C2
G3
C3
B3
B2
F2
F3
E3
D3
D2
R559
0
5%
0402
COMMON
13<>
24
25
26
27
28
29
30
31
56
57
58
59
60
61
62
63
13<>
1
10
11
8
19
25
FBA_CMD<4>
4
FBA_CMD<6>
6
FBA_CMD<5>
5
FBA_CMD<13>
13
21
16
23
20
17
9
12
3
27
18
14
15
FBVDDQ
FBVDDQ
C580
.047UF
16V
10%
X7R
0402
COMMON
GND
FBA_D<24>
FBA_D<25>
FBA_D<26>
FBA_D<27>
FBA_D<28>
FBA_D<29>
FBA_D<30>
FBA_D<31>
FBA_DQM<3>
FBA_DQS_RN<3>
FBA_DQS_WP<3>
FBA_D<56>
FBA_D<57>
FBA_D<58> F11
FBA_D<59>
FBA_D<60>
FBA_D<61>
FBA_D<62>
FBA_D<63>
FBA_DQM<7>
FBA_DQS_RN<7>
FBA_DQS_WP<7>
FBA_CMD<1>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<8>
FBA_CMD<19>
FBA_CMD<25>
FBA_CMD<21>
FBA_CMD<16>
FBA_CMD<23>
FBA_CMD<20>
FBA_CMD<17>
FBA_CMD<9>
FBA_CMD<12>
FBA_CMD<3>
FBA_CMD<27>
FBA_CLK1
FBA_CLK1* J10
SNN_FBA1_NC1
FBA_CMD<14>
FBA_CMD_SENA1
FBA_CMD<15>
FBA_ZQ1
R556
243
1%
0603
COMMON
GND
C564
.047UF
16V
10%
X7R
0402
COMMON
M6
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
R2
N2
L3
T2
M2
M3
R3
T3
N3
P3
P2
M7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
G10
F10
E11
C11
B10
B11
C10
E10
D10
D11
H10
H11
K10
K11
J11
K12
J12
F9
H4
F4
K9
M9
K4
H2
K3
L4
K2
M4
L9
G9
G4
H3
H9FBA_CMD<18>
J2
J3
V4
V9
A9
A4
K1
J1
M7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBA_VREF1
FBA_VREF3
FBVDDQ
GND
GND
FBA_CMD<4>
FBA_CMD<6>
FBA_CMD<5>
FBA_CMD<13>
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBVDDQ
R61
511
R1
1%
0402
COMMON
1.3K
1%
0402
COMMON
GND
121
R569
COMMON
0402
1%
121
R577
COMMON
0402
1%
121
R561
COMMON
0402
1%
121
R553
COMMON
0402
1%
121
R571
COMMON
0402
1%
121
R578
COMMON
0402
1%
121
R557
COMMON
0402
1%
121
R552
COMMON
0402
1%
R585
511
0402
COMMON
13<>
C47 C581R62 R582
.1UF
10V
10%
X5R
0402
COMMON
1.3K
0402
COMMON
FBVDDQ
1%
1%
GND
FBVDDQ
R1
R2R2
.1UF
10V
10%
X5R
0402
COMMON
13<>
FBA Partition
www.vinafix.vn
600-10547-0011-000 A
design
rachen
5 OF 32
07-AUG-2008
Page 6
Page6: FBA Partition Decoupling
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
Decoupling for FBA 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS PLACE NEAR MEMORY FBVDDQ PINS
C573
.1UF
16V
10%
X7R
0402
COMMON
C555
.1UF
16V
10%
0402
COMMON
C574
1UF
6.3V
10%
X5R
0603
COMMON
C579
.1UF
16V
10%
X7R
0402
COMMON
C550
.1UF
16V
10%
X7RX7R
0402
COMMON
C544
1UF
6.3V
10%
X5R
0603
COMMON
C582
.1UF
16V
10%
X7R
0402
COMMON
C559
.1UF
16V
10%
X7R
0402
COMMON
C546
1UF
6.3V
10%
X5R
0603
COMMON
C548
.047UF
16V
10%
X7R
0402
COMMON
GND
Decoupling for FBA 63..32
FBVDDQ
C576
.1UF
16V
10%
X7R
0402
COMMON
C553
.1UF
16V
10%
0402
COMMON
C572
1UF
6.3V
10%
X5R
0603
COMMON
C565
.1UF
16V
10%
X7R
0402
COMMON
C547
.1UF
16V
10%
X7RX7R X7R
0402
COMMON
C566
1UF
6.3V
10%
X5R
0603
COMMON
C567
.1UF
16V
10%
X7R
0402
COMMON
C558
.1UF
16V
10%
0402
COMMON
C545
1UF
6.3V
10%
X5R
0603
COMMON
C561
.047UF
16V
10%
X7R
0402
COMMON
GND
FBA Partition Decoupling
www.vinafix.vn
600-10547-0011-000 A
design
rachen
6 OF 32
07-AUG-2008
Page 7
Page7: FBB Partition
OUT
OUT
MIRRORED
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
VSSA (GND)
VSSA (GND)
VDDA (VDD)
VDDA (VDD)
A12 (32Mx32)
RAS
CS0
CAS
A0
WE
A3
A2
A1
A5
A4
A11
A10
A8/AP
BA1
BA0
A9
A6
A7
BA2
CLK
CLK
NC/RFU
SEN (GND)
CKE
MF (VDDQ)
RESET
ZQ
IN
OUTININ
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
ININOUTININ
NONMIRRORED
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSSQ
VSS
VSS
VSS
VSS
VSS
VREF
VREF
A12 (32Mx32)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
VDDA (VDD)
RAS
CAS
CS0
WE
A0
A2
A3
A4
A5
A1
BA1
A11
A10
A8/AP
BA0
A9
A7
A6
BA2
NC/RFU
SEN (GND)
CLK
CLK
CKE
RESET
MF (GND)
ZQ
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
13>
C594
.01UF
16V
10%
X7R
0402
COMMON
GND
3>
13>
3>
13>
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
FBB_CLK0_TERM
R591
R592
121
1%
0402
COMMON
COMMON
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
3<>
13<>
3>
13>
3<
13<
3>
13>
R593
0
5%
0402
NO STUFF
121
1%
0402
3>
13>
FBB_D<63..0>
FBB_DQM<7..0>
FBB_DQS_RN<7..0>
FBB_DQS_WP<7..0>
FBB_CMD<27..0>
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R587
0
5%
0402
COMMON
13<> GND
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
GND
FBB_DQM<0>
FBB_DQM<1>
FBB_DQM<2>
FBB_DQM<3>
FBB_DQM<4>
FBB_DQM<5>
FBB_DQM<6>
FBB_DQM<7>
FBB_DQS_RN<0>
FBB_DQS_RN<1>
FBB_DQS_RN<2>
FBB_DQS_RN<3>
FBB_DQS_RN<4>
FBB_DQS_RN<5>
FBB_DQS_RN<6>
FBB_DQS_RN<7>
FBB_DQS_WP<0>
FBB_DQS_WP<1>
FBB_DQS_WP<2>
FBB_DQS_WP<3>
FBB_DQS_WP<4>
FBB_DQS_WP<5>
FBB_DQS_WP<6>
FBB_DQS_WP<7>
R586
10K
5%
0402
COMMON
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
27
18
14
15
FBVDDQ
GND
FBB_CMD<1>
FBB_CMD<10>
FBB_CMD<11>
FBB_CMD<8>
FBB_CMD<19>
FBB_CMD<25>
FBB_CMD<22>
FBB_CMD<24>
FBB_CMD<0>
FBB_CMD<2>
FBB_CMD<21>
FBB_CMD<16>
FBB_CMD<23>
FBB_CMD<20>
FBB_CMD<17>
FBB_CMD<9>
FBB_CMD<12>
FBB_CMD<3>
FBB_CMD<27>
FBB_CMD<18>
FBB_CLK0
FBB_CLK0*
SNN_FBB0_NC1
FBB_CMD<14>
FBB_CMD_SENB0
FBB_CMD<15> V9
FBB_ZQ0
R573
10K
5%
0402
COMMON
GNDGND
C596
.047UF
16V
10%
X7R
0402
COMMON
0
1
2
3
4
5
6
7
32
33
34
35
36
37
38
39
M5
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
A9
A4
R596
243
1%
0603
COMMON
GND
K1
K12
C593
.047UF
16V
10%
X7R
0402
COMMON
J1
J12
FBB_D<0>
FBB_D<1>
FBB_D<2>
FBB_D<3>
FBB_D<4>
FBB_D<5>
FBB_D<6>
FBB_DQM<0>
FBB_DQS_RN<0>
FBB_DQS_WP<0>
FBB_D<33> M2
FBB_D<34>
FBB_D<35>
FBB_D<36>
FBB_D<37>
FBB_D<38>
FBB_D<39>
FBB_DQM<4>
FBB_DQS_RN<4>
B10
C10
B11
G10
E11
F10
C11
F11FBB_D<7>
E10
D10
D11
M5
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M8
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
T2FBB_D<32>
T3
R3
L3
N2
R2
M3
N3
P3
P2FBB_DQS_WP<4>
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
GND
GND
FBB_VREF0
FBB_VREF2H12
VREF = FBVDDQ * R2/(R1 + R2)
FBB_D<8>
FBB_D<9>
FBB_D<10>
FBB_D<11>
FBB_D<12>
FBB_D<13>
FBB_D<14>
FBB_D<15>
FBB_DQM<1>
FBB_DQS_RN<1>
FBB_DQS_WP<1>
FBB_D<40>
FBB_D<41>
FBB_D<42>
FBB_D<43>
FBB_D<44>
FBB_D<45>
FBB_D<46>
FBB_D<47>
FBB_DQM<5>
FBB_DQS_RN<5>
13>
C560
.01UF
16V
10%
X7R
0402
COMMON
GND
3>
13>
3>
13>
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
R597
511
R1
1%
0402
COMMON
R595
1.3K
R2
1%
0402
COMMON
GND
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
M5
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
F3
C2
B2
C3
B3
G3
F2
E2
E3
D3
D2
M8
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
T10
R10
T11
R11
M11
M10
N11
L10
N10
P10
P11FBB_DQS_WP<5>
FBB_CLK1_TERM
C595
.1UF
10V
10%
X5R
0402
COMMON
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBVDDQ
R563
0
5%
0402
NO STUFF
R567
121
1%
0402
COMMON
13<>
R55
511
0402
COMMON
R56
1.3K
0402
COMMON
FBB_D<16>
FBB_D<17>
FBB_D<18>
FBB_D<19>
FBB_D<20>
FBB_D<21>
FBB_D<22>
FBB_D<23>
FBB_DQM<2>
FBB_DQS_RN<2>
FBB_DQS_WP<2>
FBB_D<48>
FBB_D<49>
FBB_D<50>
FBB_D<51>
FBB_D<52>
FBB_D<53>
FBB_D<54>
FBB_D<55>
FBB_DQM<6>
FBB_DQS_RN<6>
FBB_DQS_WP<6>
FBVDDQ
1%
1%
GND
R565
121
1%
0402
COMMON
R1
R2
M10
N11
M11
L10
T10
R10
T11
R11
N10
P10
P11
E2
F3
F2
G3
C3
B2
B3
C2
E3
D3
D2
DDR3:
M5
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M8
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R576
0
5%
0402
COMMON
GND
ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
FBVDDQ
13<>
13<>
C44
.1UF
10V
10%
X5R
0402
COMMON
24
25
26
27
28
29
30
31
56
57
58
59
60
61
62
63
1
10
11
8
19
25
FBB_CMD<4>
4
FBB_CMD<6>
6
FBB_CMD<5>
5
FBB_CMD<13>
13
21
16
23
20
17
9
12
3
27
18
14
15
FBVDDQ
C578
.047UF
16V
10%
X7R
0402
COMMON
GND
FBB_D<24>
FBB_D<25>
FBB_D<26>
FBB_D<27>
FBB_D<28>
FBB_D<29>
FBB_D<30>
FBB_D<31>
FBB_DQM<3>
FBB_DQS_RN<3>
FBB_DQS_WP<3>
FBB_D<57> F11
FBB_D<59>
FBB_D<60>
FBB_D<61>
FBB_D<62>
FBB_D<63>
FBB_DQM<7>
FBB_DQS_RN<7>
FBB_DQS_WP<7>
G10FBB_D<56>
F10FBB_D<58>
C11
E11
B11
B10
C10
E10
D10
D11
FBB_CMD<1>
FBB_CMD<10>
FBB_CMD<11>
FBB_CMD<8>
FBB_CMD<19>
FBB_CMD<25>
FBB_CMD<21>
FBB_CMD<16>
FBB_CMD<23>
FBB_CMD<20>
FBB_CMD<17>
FBB_CMD<9>
FBB_CMD<12>
FBB_CMD<3>
FBB_CMD<27>
FBB_CMD<18>
FBB_CLK1
FBB_CLK1*
SNN_FBB1_NC1
FBB_CMD<14>
FBB_CMD_SENB1
FBB_CMD<15>
FBB_ZQ1
GND
M5
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
L3
M2
M3
N2
R2
T2
T3
R3
N3
P3
P2
M8
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
R550
243
1%
0603
COMMON
C556
.047UF
16V
10%
X7R
0402
COMMON
H10
H11
K10
K11
J11
J10
K12
J12
F9
H4
F4
K9
M9
K4
H2
K3
L4
K2
M4
L9
G9
G4
H3
H9
J2
J3
V4
V9
A9
A4
K1
J1
M8
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBB_VREF1
FBB_VREF3
FBVDDQ
GND
GND
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBVDDQ
R57
511
R1
1%
0402
COMMON
R58
1.3K
1%
0402
COMMON
GND
FBB_CMD<4>
FBB_CMD<6>
FBB_CMD<5>
FBB_CMD<13>
FBB_CMD<22>
FBB_CMD<24>
FBB_CMD<0>
FBB_CMD<2>
C45
.1UF
10V
10%
X5R
0402
COMMON
13<>
R570
0402
R581
0402
R562
0402
R554
0402
R594
0402
R590
0402
R589
0402
R588
0402
R575
511
0402
COMMON
R572
1.3K
0402
COMMON
1%
1%
1%
1%
1%
1%
1%
1%
FBVDDQ
1%
1%
GND
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
R1
R2R2
FBVDDQ
C569
.1UF
10V
10%
X5R
0402
COMMON
13<>
FBB Partition
www.vinafix.vn
600-10547-0011-000 A
design
rachen
7 OF 32
07-AUG-2008
Page 8
Page8: FBB Partition Decoupling
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
Decoupling for FBB 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS PLACE NEAR MEMORY FBVDDQ PINS
C588
.1UF
16V
10%
X7R
0402
COMMON
C586
.1UF
16V
10%
X7R
0402
COMMON
C591
1UF
6.3V
10%
X5R
0603 0603
COMMON
C597
.1UF
16V
10%
X7R
0402
COMMON
C587
.1UF
16V
10%
X7R
0402
COMMON
C600
1UF
6.3V
10%
X5R
COMMON
C598
.1UF
16V
10%
X7R
0402
COMMON
C589
.1UF
16V
10%
X7R
0402
COMMON
C585
1UF
6.3V
10%
X5R
0603
COMMON
C551
.047UF
16V
10%
X7R
0402
COMMON
Decoupling for FBB 63..32
FBVDDQ
C554
.1UF
16V
10%
X7R
0402
COMMON
C563
.1UF
16V
10%
X7R
0402
COMMON
C542
1UF
6.3V
10%
X5R
0603
COMMON
C552
.1UF
16V 16V
10% 10%
X7R
0402
COMMON
C571
.1UF
16V
10%
X7R
0402
COMMON
C583
1UF
6.3V
10%
X5R
0603
COMMON
C577
.1UF
X7R
0402
COMMON
C543
.1UF
16V
10%
X7R
0402
COMMON
C562
1UF
6.3V
10%
X5R
0603
COMMON
C568
.047UF
16V
10%
X7R
0402
COMMON
GND
GND
FBB Partion Decoupling
www.vinafix.vn
600-10547-0011-000 A
design
rachen
8 OF 32
07-AUG-2008
Page 9
Page9: FBC Partition
OUT
OUTINOUTININ
MIRRORED
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
VSSA (GND)
VSSA (GND)
VDDA (VDD)
VDDA (VDD)
A12 (32Mx32)
RAS
CS0
CAS
A0
WE
A3
A2
A1
A5
A4
A11
A10
A8/AP
BA1
BA0
A9
A6
A7
BA2
CLK
CLK
NC/RFU
SEN (GND)
CKE
MF (VDDQ)
RESET
ZQ
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
ININOUTININ
NONMIRRORED
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSSQ
VSS
VSS
VSS
VSS
VSS
VREF
VREF
A12 (32Mx32)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
VDDA (VDD)
RAS
CAS
CS0
WE
A0
A2
A3
A4
A5
A1
BA1
A11
A10
A8/AP
BA0
A9
A7
A6
BA2
NC/RFU
SEN (GND)
CLK
CLK
CKE
RESET
MF (GND)
ZQ
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
13>
C764
.01UF
16V
10%
X7R
0402
COMMON
R646
GND
13> 4>
13> 4>
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
121
0402
COMMON
Minimize the stub length!!
13<> 4<>
13> 4>
13< 4<
13> 4>
FBVDDQ
R652
0
5%
0402
NO STUFF
FBC_CLK0_TERM
R647
121
1%
DDR3:
1%
0402
COMMON
ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
13> 4>
FBC_D<63..0>
FBC_DQM<7..0>
FBC_DQS_RN<7..0>
FBC_DQS_WP<7..0>
FBC_CMD<27..0>
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R626
0
5%
0402
COMMON
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
13<> GND
FBC_DQM<0>
FBC_DQM<1>
FBC_DQM<2>
FBC_DQM<3>
FBC_DQM<4>
FBC_DQM<5>
FBC_DQM<6>
FBC_DQM<7>
FBC_DQS_RN<0>
FBC_DQS_RN<1>
FBC_DQS_RN<2>
FBC_DQS_RN<3>
FBC_DQS_RN<4>
FBC_DQS_RN<5>
FBC_DQS_RN<6>
FBC_DQS_RN<7>
FBC_DQS_WP<0>
FBC_DQS_WP<1>
FBC_DQS_WP<2>
FBC_DQS_WP<3>
FBC_DQS_WP<4>
FBC_DQS_WP<5>
FBC_DQS_WP<6>
FBC_DQS_WP<7>
GND
R622
10K
5%
0402
COMMON
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
27
18
14
15
FBVDDQ
GND
FBC_CMD<1>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<8>
FBC_CMD<19>
FBC_CMD<25>
FBC_CMD<22>
FBC_CMD<24>
FBC_CMD<0>
FBC_CMD<2>
FBC_CMD<21>
FBC_CMD<16>
FBC_CMD<23>
FBC_CMD<20>
FBC_CMD<17>
FBC_CMD<9>
FBC_CMD<12>
FBC_CMD<3>
FBC_CMD<27>
FBC_CMD<18>
FBC_CLK0 J11
FBC_CLK0*
SNN_FBC0_NC1
FBC_CMD<14>
FBC_CMD_SENC0 V4
FBC_CMD<15> V9
R621
10K
5%
0402
COMMON
GND
C747
.047UF
16V
10%
X7R
0402
COMMON
0
1
2
3
4
5
6
7
32
33
34
35
36
37
38
39
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J10
J2
J3
A9
A4
FBC_ZQ0
R662
243
1%
0603
COMMON
GNDGND
K1
K12
C748
.047UF
16V
10%
X7R
0402
COMMON
J1
J12
FBC_D<0>
FBC_D<1>
FBC_D<2>
FBC_D<3>
FBC_D<4>
FBC_D<5>
FBC_D<6>
FBC_D<7>
FBC_DQM<0>
FBC_DQS_RN<0>
FBC_DQS_WP<0>
FBC_D<32>
FBC_D<33> M3
FBC_D<34>
FBC_D<35>
FBC_D<36>
FBC_D<37>
FBC_D<38>
FBC_D<39>
FBC_DQM<4>
FBC_DQS_RN<4>
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
E11
F10
G10
F11
C10
B10
C11
B11
E10
D10
D11
M4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
L3
M2
N2
R3
R2
T2
T3
N3
P3
P2FBC_DQS_WP<4>
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
VREF = FBVDDQ * R2/(R1 + R2)
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
GND
GND
FBC_VREF0
FBC_VREF2
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511K + 1.18K)
FBC_D<8>
FBC_D<9>
FBC_D<10>
FBC_D<11>
FBC_D<12>
FBC_D<13>
FBC_D<14>
FBC_D<15>
FBC_DQM<1>
FBC_DQS_RN<1>
FBC_DQS_WP<1>
FBC_D<40>
FBC_D<41>
FBC_D<42>
FBC_D<43>
FBC_D<44>
FBC_D<45>
FBC_D<46>
FBC_D<47>
FBC_DQM<5>
FBC_DQS_RN<5>
FBC_DQS_WP<5>
FBVDDQ
13>
C618
.01UF
16V
10%
X7R
FBC_CLK1_TERM
0402
COMMON
R604
GND
13> 4>
13> 4>
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
121
1%
0402
COMMON
Minimize the stub length!!
FBVDDQ
R641
511
R1
1%
0402
COMMON
R651
1.3K
0402
COMMON
R2
1%
C760
.1UF
10V
10%
X5R
0402
COMMON
GND
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
C2
B2
G3
F2
C3
F3
E2
B3
E3
D3
D2
M4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
L10
M11
M10
N11
R11
T11
T10
R10
N10
P10
P11
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBC_D<16>
FBC_D<17>
FBC_D<18>
FBC_D<19>
FBC_D<20>
FBC_D<21>
FBC_D<22>
FBC_D<23>
FBC_DQM<2>
FBC_DQS_RN<2>
FBC_DQS_WP<2>
FBC_D<48>
FBC_D<49>
FBC_D<50>
FBC_D<51>
FBC_D<52>
FBC_D<53>
FBC_D<54>
FBC_D<55>
FBC_DQM<6>
FBC_DQS_RN<6>
FBC_DQS_WP<6>
R602
0
5%
0402
NO STUFF
13<>
COMMON
1.3K
COMMON
R52
511
0402
R51
0402
R605
121
1%
0402
COMMON
FBVDDQ
1%
1%
GND
ZQ = 6x desired outputDDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
R1
C42
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M11
N11
T11
T10
M10
L10
R11
R10
N10
P10
P11
M4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
B2
C2
B3
E2
C3
F2
F3
G3
E3
D3
D2
.1UF
10V
10%
X5R
0402
COMMON
R2
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R617
0
5%
0402
COMMON
13<>
24
25
26
27
28
29
30
31
56
57
58
59
60
61
62
63
FBVDDQ
13<> GND
FBVDDQ
FBC_D<24>
FBC_D<25>
FBC_D<26>
FBC_D<27>
FBC_D<28>
FBC_D<29>
FBC_D<30>
FBC_D<31>
FBC_DQM<3>
FBC_DQS_RN<3>
FBC_DQS_WP<3>
FBC_D<56>
FBC_D<57>
FBC_D<58>
FBC_D<59>
FBC_D<60>
FBC_D<61>
FBC_D<62>
FBC_D<63>
FBC_DQM<7>
FBC_DQS_RN<7>
1
10
11
8
19
25
4
6
5
13
21
16
23
20
17
9
12
3
27
18
14
15
GND
FBC_CMD<4>
FBC_CMD<6>
FBC_CMD<5>
FBC_CMD<13>
C621
.047UF
16V
10%
X7R
0402
COMMON
FBC_CMD<1>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<8>
FBC_CMD<19>
FBC_CMD<25>
FBC_CMD<21>
FBC_CMD<16>
FBC_CMD<23>
FBC_CMD<20>
FBC_CMD<17>
FBC_CMD<9>
FBC_CMD<12>
FBC_CMD<3>
FBC_CMD<27>
FBC_CMD<18>
FBC_CLK1
FBC_CLK1*
SNN_FBC1_NC1
FBC_CMD<14>
FBC_CMD_SENC1
FBC_CMD<15> V9
FBC_ZQ1
R599
243
1%
0603
COMMON
GND
C626
.047UF
16V
10%
X7R
0402
COMMON
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
T3
R3
T2
R2
M2
M3
N2
L3
N3
P3
P2
M4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
E11
C11
B10
C10
B11
G10
F10
F11
E10
D10
D11FBC_DQS_WP<7>
M4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
H10
F9
H4
F4
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
G9
G4
H3
H9
J11
J10
J2
J3
V4
A9
A4
K1
K12
J1
J12
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBC_VREF1
FBC_VREF3
FBVDDQ
GND
GND
R53
511
0402
COMMON
R54
1.3K
0402
COMMON
FBVDDQ
1%
1%
GND
FBC_CMD<4>
FBC_CMD<6>
FBC_CMD<5>
FBC_CMD<13>
FBC_CMD<22>
FBC_CMD<24>
FBC_CMD<0>
FBC_CMD<2>
C43
.1UF
10V
10%
X5R
0402
COMMON
13<>
FBVDDQ
121
R611
COMMON
0402
1%
121
R614
COMMON
0402
1%
121
R612
COMMON
0402
1%
121
R606
COMMON
0402
1%
121
R640
COMMON
0402
1%
121
R634
COMMON
0402
1%
121
R633
COMMON
0402
1%
121
R642
0402 COMMON
1%
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQ
DDR3:
1.26V = 1.8V * 1.18K/(511K + 1.18K)
FBVDDQ
R610
511
R1R1
1%
0402
COMMON
R603
1.3K
R2R2
1%
0402
COMMON
GND
C620
.1UF
10V
10%
X5R
0402
COMMON
13<>
FBC Partition
www.vinafix.vn
600-10547-0011-000 A
design
rachen
9 OF 32
07-AUG-2008
Page 10
Page10: FBC Partition
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
Decoupling for FBC 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS PLACE NEAR MEMORY FBVDDQ PINS
C771
.1UF
16V
10%
X7R
0402 0402
COMMON
C779
.1UF
16V
10%
X7R
0402
COMMON
C770
1UF
6.3V
10%
X5R
0603 0603
COMMON
C772
.1UF
16V
10%
X7R
COMMON
C722
.1UF
16V
10%
X7R
0402
COMMON
C740
1UF
6.3V
10%
X5R
COMMON
C749
.1UF
16V
10%
X7R
0402
COMMON
C744
.1UF
16V
10%
X7R
0402
COMMON
C724
1UF
6.3V
10%
X5R
0603
COMMON
C759
.047UF
16V
10%
X7R
0402
COMMON
GND
Decoupling for FBC 63..32
FBVDDQ
C649
.1UF
16V
10%
X7R
0402
COMMON
C640
.1UF
16V
10%
X7R
0402
COMMON
C647
1UF
6.3V
10%
X5R
0603
COMMON
C610
.1UF
16V
10%
X7R
0402
COMMON
C662
.1UF
16V
10%
X7R
0402
COMMON
C611
1UF
6.3V
10%
X5R
0603
COMMON
C607
.1UF
16V
10%
X7R
0402
COMMON
C612
.1UF
16V
10%
X7R
0402
COMMON
C609
1UF
6.3V
10%
X5R
0603
COMMON
C646
.047UF
16V
10%
X7R
0402
COMMON
GND
FBC Partition Decoupling
www.vinafix.vn
600-10547-0011-000 A
design
rachen
10 OF 32
07-AUG-2008
Page 11
Page11: FBD Partition
OUT
OUT
MIRRORED
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
VSSA (GND)
VSSA (GND)
VDDA (VDD)
VDDA (VDD)
A12 (32Mx32)
RAS
CS0
CAS
A0
WE
A3
A2
A1
A5
A4
A11
A10
A8/AP
BA1
BA0
A9
A6
A7
BA2
CLK
CLK
NC/RFU
SEN (GND)
CKE
MF (VDDQ)
RESET
ZQ
IN
OUTININ
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
ININOUTININ
NONMIRRORED
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSSQ
VSS
VSS
VSS
VSS
VSS
VREF
VREF
A12 (32Mx32)
VDDA (VDD)
VSSA (GND)
VSSA (GND)
VDDA (VDD)
RAS
CAS
CS0
WE
A0
A2
A3
A4
A5
A1
BA1
A11
A10
A8/AP
BA0
A9
A7
A6
BA2
NC/RFU
SEN (GND)
CLK
CLK
CKE
RESET
MF (GND)
ZQ
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
13>
C847
.01UF
16V
10%
X7R
0402
COMMON
GND
4>
13>
4>
13>
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
Minimize the stub length!!
FBVDDQ
FBD_CLK0_TERM
R744
121
1%
0402
COMMON
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
4<>
13<>
4> 13>
4<
13<
4> 13>
R742
121
0402
COMMON
R743
0
5%
0402
NO STUFF
1%
FBD_D<63..0>
FBD_DQM<7..0>
FBD_DQS_RN<7..0>
FBD_DQS_WP<7..0>
4> 13>
CMD-Addr Map
BGA136 ADDR
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R732
0
5%
0402
COMMON
FBD_CMD<27..0>
13<> GND
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
GND
FBD_DQM<0>
FBD_DQM<1>
FBD_DQM<2>
FBD_DQM<3>
FBD_DQM<4>
FBD_DQM<5>
FBD_DQM<6>
FBD_DQM<7>
FBD_DQS_RN<0>
FBD_DQS_RN<1>
FBD_DQS_RN<2>
FBD_DQS_RN<3>
FBD_DQS_RN<4>
FBD_DQS_RN<5>
FBD_DQS_RN<6>
FBD_DQS_RN<7>
FBD_DQS_WP<0>
FBD_DQS_WP<1>
FBD_DQS_WP<2>
FBD_DQS_WP<3>
FBD_DQS_WP<4>
FBD_DQS_WP<5>
FBD_DQS_WP<6>
FBD_DQS_WP<7>
R723
10K
5%
0402
COMMON
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
27
18
14
15
FBVDDQ
GND
FBD_CMD<1>
FBD_CMD<10>
FBD_CMD<11>
FBD_CMD<8>
FBD_CMD<19>
FBD_CMD<25>
FBD_CMD<22>
FBD_CMD<24>
FBD_CMD<0>
FBD_CMD<2>
FBD_CMD<21>
FBD_CMD<16>
FBD_CMD<23>
FBD_CMD<20>
FBD_CMD<17>
FBD_CMD<9>
FBD_CMD<12>
FBD_CMD<3>
FBD_CMD<27>
FBD_CMD<18>
FBD_CLK0
FBD_CLK0*
SNN_FBD0_NC1
FBD_CMD<14>
FBD_CMD_SEND0
FBD_CMD<15> V9
FBD_ZQ0
R731
10K
5%
0402
COMMON
GND
GND
C830
.047UF
16V
10%
X7R
0402
COMMON
0
1
2
3
4
5
6
7
32
33
34
35
36
37
38
39
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
A9
A4
R746
243
1%
0603
COMMON
GND
K1
K12
C848
.047UF
16V
10%
X7R
0402
COMMON
J1
J12
FBD_D<0>
FBD_D<1>
FBD_D<2>
FBD_D<3>
FBD_D<4>
FBD_D<5>
FBD_D<6>
FBD_D<7>
FBD_DQM<0>
FBD_DQS_RN<0>
FBD_DQS_WP<0>
FBD_D<32>
FBD_D<33>
FBD_D<34>
FBD_D<35>
FBD_D<36>
FBD_D<37>
FBD_D<38>
FBD_D<39>
FBD_DQM<4>
FBD_DQS_RN<4>
FBD_DQS_WP<4>
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
B10
F11
F10
B11
C11
C10
E11
G10
E10
D10
D11
T3
T2
R2
M2
R3
M3
N2
L3
N3
P3
P2
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
GND
GND
FBD_VREF0
FBD_VREF2
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQ
DDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBD_D<8>
FBD_D<9>
FBD_D<10>
FBD_D<11>
FBD_D<12>
FBD_D<13>
FBD_D<14>
FBD_D<15>
FBD_DQM<1>
FBD_DQS_RN<1>
FBD_DQS_WP<1>
FBD_D<40>
FBD_D<41>
FBD_D<42>
FBD_D<43>
FBD_D<44>
FBD_D<45>
FBD_D<46>
FBD_D<47>
FBD_DQM<5>
FBD_DQS_RN<5>
FBD_DQS_WP<5>
13>
C802
.01UF
16V
10%
X7R
0402
COMMON
FBD_CLK1_TERM
R685
GND
13>
4>
13>
MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!
121
1%
0402
COMMON
Minimize the stub length!!
FBVDDQ
R734
511
R1
1%
0402
COMMON
R736
1.3K
0402
COMMON
R2
1%
C839
.1UF
10V
10%
X5R
0402
COMMON
GND
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
G3
F3
F2
E2
C2
B3
B2
C3
E3
D3
D2
M2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
N11
M11
M10
R11
T11
L10
T10
R10
N10
P10
P11
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBVDDQ
R683
0
5%
0402
NO STUFF
FBD_D<16>
FBD_D<17>
FBD_D<18>
FBD_D<19>
FBD_D<20>
FBD_D<21>
FBD_D<22>
FBD_D<23>
FBD_DQM<2>
FBD_DQS_RN<2>
FBD_DQS_WP<2>
FBD_D<48>
FBD_D<49>
FBD_D<50>
FBD_D<51>
FBD_D<52>
FBD_D<53>
FBD_D<54>
FBD_D<55>
FBD_DQM<6>
FBD_DQS_RN<6>
FBD_DQS_WP<6>
13<>
COMMON
COMMON
R688
121
1%
0402
COMMON
R27
511
0402
R26
1.3K
0402
FBVDDQ
1%
1%
GND
CMD-Addr Map
BGA136 ADDR
GND
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
R1
C20
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
R10
R11
T10
T11
N11
L10
M11
M10
N10
P10
P11
M2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
E2
B3
C2
C3
B2
F3
G3
F2
E3
D3
D2
.1UF
10V
10%
X5R
0402
COMMON
R2
CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST
R717
0
5%
0402
COMMON
13<>
FBVDDQ
13<>
FBD_D<24>
24
FBD_D<25>
25
FBD_D<26>
26
FBD_D<27>
27
FBD_D<28>
28
FBD_D<29>
29
FBD_D<30>
30
FBD_D<31>
31
FBD_DQM<3>
FBD_DQS_RN<3>
FBD_DQS_WP<3>
FBD_D<56>
56
FBD_D<57> F10
57
FBD_D<58>
58
FBD_D<59>
59
FBD_D<60>
60
FBD_D<61>
61
FBD_D<62>
62
FBD_D<63>
63
FBD_DQM<7>
FBD_DQS_RN<7>
1
10
11
8
19
25
4
6
5
13
21
16
23
20
17
9
12
3
27
18
14
15
FBVDDQ
GND
FBD_CMD<1>
FBD_CMD<10>
FBD_CMD<11>
FBD_CMD<8>
FBD_CMD<19>
FBD_CMD<25>
FBD_CMD<4>
FBD_CMD<6>
FBD_CMD<5>
FBD_CMD<13>
FBD_CMD<21>
FBD_CMD<16>
FBD_CMD<23>
FBD_CMD<20>
FBD_CMD<17>
FBD_CMD<9>
FBD_CMD<12>
FBD_CMD<3>
FBD_CMD<27>
FBD_CMD<18>
FBD_CLK1
FBD_CLK1*
SNN_FBD1_NC1
FBD_CMD<14>
FBD_CMD_SEND1
FBD_CMD<15>
FBD_ZQ1
C821
.047UF
16V
10%
X7R
0402
COMMON
T2
R2
L3
M3
M2
N2
R3
T3
N3
P3
P2
G10
F11
E11
C11
B10
C10
B11
E10
D10
D11FBD_DQS_WP<7>
H10
H11
K10
K11
J11
J10
R686
243
1%
0603
COMMON
GND
K12
C803
.047UF
16V
10%
X7R
0402
COMMON
J12
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
F9
H4
F4
K9
M9
K4
H2
K3
L4
K2
L9
G9
G4
H3
H9
J2
J3
V4
V9
A9
A4
K1
J1
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1M4
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBD_VREF1
FBD_VREF3
FBVDDQ
GND
GND
R38
511
0402
COMMON
R40
1.3K
0402
COMMON
FBVDDQ
1%
1%
GND
VREF = FBVDDQ * R2/(R1 + R2)
R1
C34
.1UF
10V
10%
X5R
0402
COMMON
FBD_CMD<4>
FBD_CMD<6>
FBD_CMD<5>
FBD_CMD<13>
FBD_CMD<22>
FBD_CMD<24>
FBD_CMD<0>
FBD_CMD<2>
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
R695
0402
R694
0402
R705
0402
R704
0402
R737
0402
R733
0402
R740
0402
R745
0402
1%
1%
1%
1%
1%
1%
1%
1%
FBVDDQ
R684
511
R1
1%
0402
COMMON
13<>
R682
1.3K
R2R2
1%
0402
COMMON
GND
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
FBVDDQ
C798
.1UF
10V
10%
X5R
0402
COMMON
13<>
FBD Partition
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600-10547-0011-000 A
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rachen
11 OF 32
07-AUG-2008
Page 12
Page12: FBD Partition Decoupling
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
Decoupling for FBD 31..0
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C813
.047UF
16V
10%
X7R
0402
COMMON
C849
.1UF
16V
10%
X7R
0402
COMMON
C845
1UF
6.3V
10%
X5R
0603
COMMON
C837
.1UF
16V
10%
X7R
0402
COMMON
C843
.1UF
16V
10%
X7R
0402
COMMON
C851
1UF
6.3V
10%
X5R
0603
COMMON
C833
.1UF
16V
10%
X7R
0402
COMMON
C838
.1UF
16V
10%
X7R
0402
COMMON
C842
1UF
6.3V
10%
X5R
0603
COMMON
C850
.1UF
16V
10%
X7R
0402
COMMON
GND
Decoupling for FBD 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C846
.047UF
16V
10%
X7R
0402
COMMON
C819
.1UF
16V
10%
X7R
0402
COMMON
C815
1UF
6.3V
10%
X5R
0603
COMMON
C811
.1UF
16V
10%
X7R
0402
COMMON
C818
.1UF
16V
10%
X7R
0402
COMMON
C826
1UF
6.3V
10%
X5R
0603
COMMON
C801
.1UF
16V
10%
X7R
0402
COMMON
C825
.1UF
16V
10%
X7R
0402
COMMON
C797
1UF
6.3V
10%
X5R
0603
COMMON
C810
.1UF
16V
10%
X7R
0402
COMMON
GND
FBD Partition Decoupling
www.vinafix.vn
600-10547-0011-000 A
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rachen
12 OF 32
07-AUG-2008
Page 13
Page13: FB Net Properties
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
BIBIBIBIBIBIBIBIBIBIBIBIBIBIOUTBIIN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIOUTINOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUTINOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTINOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NET RULES for FBA and FBB
NET
5<
5<
5<
5<
3>
3>
5>
3>
3>
5>
FBA_CLK0
FBA_CLK0*
FBA_CLK0_TERM
FBA_CLK1
FBA_CLK1*
FBA_CLK1_TERM
NET
FBA_CMD<27..0>
FBA_DQS_WP<7..0>
FBA_DQS_RN<7..0>
FBA_DQM<7..0>
FBA_D<63..0> 1
5<>
5<>
5<>
5<>
5<
3<>
3>
3>
3<
3>
NET
7<
7<
7<
7<
3>
3>
7>
3>
3>
7>
FBB_CLK0
FBB_CLK0*
FBB_CLK0_TERM
FBB_CLK1
FBB_CLK1*
FBB_CLK1_TERM
NET
7<>
7<>
7<> 3>
7<>
7<
3<>
3>
3>
3<
FBB_CMD<27..0>
FBB_DQS_WP<7..0>
FBB_DQS_RN<7..0>
FBB_DQM<7..0>
FBB_D<63..0>
NV_CRITICAL_NET
1
1
1
1
1
1
NV_CRITICAL_NET
1
1
1
1
NV_CRITICAL_NET
1
1
1
1
1
1
NV_CRITICAL_NET
1
1
1
1
1
IMPEDANCE DIFFPAIR
80DIFF
80DIFF
40OHM
80DIFF
80DIFF
40OHM
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
IMPEDANCE
40OHM
40OHM
40OHM
40OHM
40OHM
IMPEDANCE
80DIFF
80DIFF
40OHM
80DIFF
80DIFF
40OHM
DIFFPAIR
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
IMPEDANCE
40OHM
40OHM
40OHM
40OHM
40OHM
NET RULES for FBC and FBD
9<>
11<>
11<>
11<>
11<>
9<
9<
9<
9<
9<
9<>
9<>
9<>
11<
11<
11<
11<
11<
4<>
11>
11>
4<>
4>
4>
9>
4>
4>
9>
4>
4>
4<
4>
4>
4>
4>
4>
4>
4>
4<
4>
NET
FBC_CLK0
FBC_CLK0*
FBC_CLK0_TERM
FBC_CLK1
FBC_CLK1*
FBC_CLK1_TERM
NET
FBC_CMD<27..0>
FBC_DQS_WP<7..0>
FBC_DQS_RN<7..0>
FBC_DQM<7..0>
FBC_D<63..0>
NET
FBD_CLK0
FBD_CLK0*
FBD_CLK0_TERM
FBD_CLK1
FBD_CLK1*
FBD_CLK1_TERM
NET
FBD_CMD<27..0>
FBD_DQS_WP<7..0>
FBD_DQS_RN<7..0>
FBD_DQM<7..0>
FBD_D<63..0>
NV_CRITICAL_NET
1
1
1
1
1
1
NV_CRITICAL_NET
1
1
1
1
1
NV_CRITICAL_NET
1
1
1
1
1
1
NV_CRITICAL_NET
1
1
1
1
1
IMPEDANCE DIFFPAIR
80DIFF
80DIFF
40OHM
80DIFF
80DIFF
40OHM
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
IMPEDANCE
40OHM
40OHM
40OHM
40OHM
40OHM
IMPEDANCE DIFFPAIR
80DIFF
80DIFF
40OHM
80DIFF
80DIFF
40OHM
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
IMPEDANCE
40OHM
40OHM
40OHM
40OHM
40OHM
NET
3>
3>
5>
5>
5>
5>
5<
5<
7>
7>
7>
7>
7<
7<
FB_PLLAVDD0 12MIL
FB_VREF
FBA_VREF1
FBA_VREF2
FBA_VREF3
FBA_ZQ0
FBA_ZQ1
FBB_VREF0
FBB_VREF1
FBB_VREF2
FBB_VREF3
FBB_ZQ0
FBB_ZQ1
MIN_LINE_WIDTH
12MIL
12MILFBA_VREF0
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
VOLTAGE NV_NET_MAX_CURRENT NET
1.1V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
0.04A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
11>
11>
11>
11>
11<
11<
4>
9>
9>
9>
9>
9<
9<
FB_PLLAVDD1
FBC_VREF0
FBC_VREF1
FBC_VREF2
FBC_VREF3
FBC_ZQ0
FBC_ZQ1
FBD_VREF0
FBD_VREF1
FBD_VREF2
FBD_VREF3
FBD_ZQ0
FBD_ZQ1
MIN_LINE_WIDTH
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
VOLTAGE NV_NET_MAX_CURRENT
1.1V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
0.04A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
FB Net Properties
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600-10547-0011-000 A
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13 OF 32
07-AUG-2008
Page 14
Page14: DACA Interface
OUT
OUT
OUT
OUT
11
15
10
6
1
5
SDA
ID0
SCL
VSYNC
HSYNC
GND_B
GND-R
SHIELD
GND-G
R
G
SHIELD
GND
GND
B
5V
ID2
OUT
OUT
OUT
6/19 DACA
I2CA_SCL
I2CA_SDA
DACA_VSYNC
DACA_HSYNC
DACA_RED
DACA_GREEN
DACA_BLUE
DACA_VREF
DACA_VDD
DACA_RSET
INBIBIBIININBIBIBIBIBIBIBIBIBIBIBI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
DACA RGB-FILTER
16< 16< 14>
14>
I2CA_SDA_T
33
R11
COMMON
0402
5%
I2CA_SCL_T
33
R10
COMMON
0402
5%
R4
2.2K
5V
5%
0402
COMMON
R3
2.2K
5%
0402
COMMON
SYNC_BUFFER BYPASS
33
R750
NO STUFF
0402
5V
5%
LB4
LB3
27nH
COMMON0402
27nH
COMMON0402
C5
22PF
50V
5%
C0G
0402
COMMON
C4
22PF
50V
5%
C0G
0402
COMMON
I2CA_SDA_C
I2CA_SCL_C
14>
16< 16< 14>
14
4
5
G1
G94-400-A1
AM12
AP10
AP11
BGA1504
COMMON
AA1
AA4
AU12
AT12
AU10
AU11
AT10
I2CA_SCL
I2CA_SDA
DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_GREEN
DACA_BLUE
R629
150
1%
0402
COMMON
10
9
DACA_RED
3V3
C765
.1UF
10%
X5R
0402
COMMON
DACA_VDD
DACA_VREF
DACA_RSET
R659
124
1%6.3V 6.3V 10V6.3V
0402
COMMON
LB508
BEAD_0402
C763
4.7UF
10%
X5R
0603
COMMON
GND
240R@100MHz
COMMON
C767
C769
1UF
4.7UF
10%
10%
X5R
X5R
0402
0603
COMMON
COMMON
GND
C721
.1UF
6.3V
10%
X7R
0402
COMMON
GND
U505
74ACT08
DACA_VS_BUF6
74ACT_SO
COMMON
7
5V
14
U505
74ACT08
DACA_HS_BUF8
74ACT_SO
COMMON
7
PLACE NEAR SYNC BUFFER
SYNC_BUFFER BYPASS
5V
3V3
2
D506
BAV99
3
SOT23
100V
100MA
COMMON
1
R751
C865
.1UF
16V
10%
X7R
0402
COMMON
0402
R763
R764
0402
0402
5%
33
NO STUFF
5%
DACA_HS_BUF_R
33
COMMON
5%
R760
150
1%
0402
COMMON
3
3
C864
18PF
50V
5%
C0G
0402
COMMON
5V
2
D6
BAV99
SOT23
100V
100MA
COMMON
1
5V
2
D7
BAV99
SOT23
100V
100MA
COMMON
1
68nHL510
COMMON0402
DACA_VS_BUF_R
33
COMMON
L3
L4
DACA_RED_C
C876
4.7PF
50V
+/-0.25PF
COG
0402
COMMON
27nH
COMMON0402
27nH
COMMON0402
C9
15PF
50V
5%
C0G
0603
COMMON
C10
15PF
50V
5%
C0G
0603
COMMON
SNN_A_MON_ID2
DACA_VS_C
DACA_HS_C
16< 14<>
16< 14<>
16< 14<>
14>
14>
DDC_5V
14>
16< 14<>
14>
16< 14<>
16
6
1
7
2
8
3
9
4
10
5
17
16< 14<>
16< 14<>
SOUTH
J2
CON_DSUB15HD
VGA_SLIM
NO STUFF
11
12
13
14
15
SNN_A_MON_ID0
I2CA_SDA_C
DACA_HS_C
DACA_VS_C
I2CA_SCL_C
GND
DACA_GREEN
NET
DACA_VDD
DACA_VREF
DACA_RSET
NET
DACA_RED
DACA_GREEN
DACA_BLUE
16< 14>
14>
16<
14>
16<
14>
16<
14>
16<
DACA_GREEN_C
DACA_BLUE_C
DACA_HSYNC
DACA_HS_BUF
DACA_HS_BUF_R
DACA_HS_C
DACA_VSYNC
DACA_VS_BUF
DACA_VS_BUF_R
DACA_VS_C
MIN_LINE_WIDTH
12MIL
12MIL
12MIL
NV_CRITICAL_NET
1
1
1
1DACA_RED_C
1
1
2
2
2
2
2
2
2
2
VOLTAGE
3.3V
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
NV_NET_MAX_CURRENT
0.100A
MIN_LINE_WIDTHIMPEDANCE
R625
150
1%
0402
COMMON
DACA_BLUE
R628
150
1%
0402
COMMON
DACA Interface
www.vinafix.vn
3V3
2
D505
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
3V3
2
D504
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
R759
150 18PF
1%
0402
COMMON
R758
150
1%
0402
COMMON
L508
C859
50V
5%
C0G
0402
COMMON
L509
C860
18PF
50V
5%
C0G
0402
COMMON
COMMON0402
68nH
COMMON0402
C873
4.7PF
50V
+/-0.25PF
COG
0402
COMMON
DACA_BLUE_C
C875
4.7PF
50V
+/-0.25PF
COG
0402
COMMON
DACA_GREEN_C
68nH
600-10547-0011-000 A
design
rachen
14 OF 32
07-AUG-2008
Page 15
Page15: DACC Interface
OUT
OUT
OUT
OUT
11
15
10
6
1
5
SDA
ID0
SCL
VSYNC
HSYNC
GND_B
GND-R
SHIELD
GND-G
R
G
SHIELD
GND
GND
B
5V
ID2
OUT
OUT
OUT
8/19 DACC
I2CB_SCL
I2CB_SDA
DACC_VSYNC
DACC_HSYNC
DACC_RED
DACC_GREEN
DACC_BLUE
DACC_VREF
DACC_VDD
DACC_RSET
ININBIBIBIBIINBIBIBIBIBIBIBIBIBIBI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
DACC RGB-FILTER
I2CB_SDA_T
33
R9
COMMON
0402
5%
I2CB_SCL_T
33
R8
COMMON
0402
5%
SYNC_BUFFER BYPASS
33R748
NO STUFF
0402
5V
5%
27nH
LB2
COMMON
LB1
0402
0402
COMMON
27nH
R2
2.2K
5V
5%
0402
COMMON
R1
2.2K
5%
0402
COMMON
I2CB_SDA_C
C2
22PF
50V
5%
C0G
0402
COMMON
I2CB_SCL_C
C1
22PF
50V
5%
C0G
0402
COMMON
17< 15> 17< 15>
17< 15> 17< 15>
14
1
2
G1
G94-400-A1
AM11
AW8
AV7DACC_RSET
BGA1504
COMMON
AA3
AA2
AU7
AU8
AT6
AT7
I2CB_SCL
I2CB_SDA
DACC_HSYNC
DACC_VSYNC
DACC_RED
DACC_GREEN
DACC_BLUEAT8
R644
150
1%
0402
COMMON
13
12
DACC_RED
3V3
LB507
C755
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
240R@100MHz
COMMONBEAD_0402
C754
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C719
.1UF
6.3V
10%
X7R
0402
COMMON
GND
C742
1UF
6.3V
10%
X5R
0402
COMMON
C753
1UF
6.3V
10%
X5R
0402
COMMON
DACC_VDD
DACC_VREF
R637
124
1%
0402
COMMON
U505
74ACT08
DACC_VS_BUF
3
74ACT_SO
COMMON
7
R749
0402
5%
SYNC_BUFFER BYPASS
R761
0402
R762
0402
5%
5%
5V
14
U505
74ACT08
DACC_HS_BUF
11
74ACT_SO
COMMON
7
3V3
2
D509
BAV99
3
SOT23
100V
100MA
COMMON
1
33
COMMON
33
NO STUFF
33
COMMON
R754
150
0402
COMMON
1%
DACC_VS_BUF_R
DACC_HS_BUF_R
3
3
L507
C858
18PF
50V
5%
C0G
0402
COMMON
27nH
L1
5V
2
D3
BAV99
SOT23
100V
100MA
COMMON
1
5V
2
D4
BAV99
SOT23
100V
100MA
COMMON
1
DACC_RED_C
68nH
COMMON0402
C871
4.7PF
50V
+/-0.25PF
COG
0402
COMMON
COMMON0402
27nH
L2
COMMON0402
DACC_VS_C
C7
15PF
50V
5%
C0G
0603
COMMON
DACC_HS_C
C8
15PF
50V
5%
C0G
0603
COMMON
15<>
15<>
15<>
SNN_C_MON_ID2
17<
17<
17<
DDC_5V
17< 15<> 15> 15>
17< 15<> 15> 15>
16
6
1
7
2
8
3
9
4
10
5
17
15<>
15<>
J1
CON_DSUB15HD
VGA_SLIM
NO STUFF
17<
17<
11
12
15
SNN_C_MON_ID0
I2CB_SDA_C
DACC_HS_C13
DACC_VS_C14
I2CB_SCL_C
GND
DACC_GREEN
R639
150
1%
0402
NET
DACC_VDD
DACC_VREF
DACC_RSET
NET
DACC_RED
DACC_GREEN
DACC_BLUE
15> 17<
17< 15>
15>
17<
15>
17<
15> 17<
DACC_RED_C
DACC_BLUE_C
DACC_HSYNC
DACC_HS_BUF
DACC_HS_BUF_R
DACC_HS_C
DACC_VSYNC
DACC_VS_BUF
DACC_VS_BUF_R
DACC_VS_C
MIN_LINE_WIDTH
12MIL
12MIL
12MIL
NV_CRITICAL_NET
1
1
1
1
1DACC_GREEN_C
1
2
2
2
2
2
2
2
2
VOLTAGE
3.3V
IMPEDANCE
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
NV_NET_MAX_CURRENT
0.100A
MIN_LINE_WIDTH
COMMON
DACC_BLUE
R636
150
1%
0402
COMMON
www.vinafix.vn
3V3
2
D508
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
3V3
2
D507
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
DACC Interface
R753
150
0402
COMMON
R752
150
0402
COMMON
1%
1%
L506
C857
18PF
50V
5%
C0G
0402
COMMON
L505
C856
18PF
50V
5%
C0G
0402
COMMON
0402
0402
COMMON
COMMON
68nH
68nH
DACC_GREEN_C
C870
4.7PF
50V
+/-0.25PF
COG
0402
COMMON
DACC_BLUE_C
C869
4.7PF
50V
+/-0.25PF
COG
0402
COMMON
600-10547-0011-000 A
design
rachen
15 OF 32
07-AUG-2008
Page 16
Page16: IFP A/B Interface -- DVI Connector South
BIBIBI
1917
81624
C1
C5A
C2
C3
C5
C4
SHLD24
SHLD13
SHLD05
SHIELD8
SHIELD5
SHIELD6
SHIELD7
SHIELD1
SHIELD2
SHIELD3
SHIELD4
TX0ÂTX1-
TX1+
TX2-
TX0+
TX2+
TX3ÂTX3+
TX4+
TX4-
DDCC
TX5+
TX5-
GND
VDDC
SHLDC
TXC-
DDCD
HPD
R
VSYNC
TXC+
G
AGND2
AGND1
B
HSYNC
INININININININ
OUT
9/19 IFPAB
IFPA_TXC
IFPA_TXC
IFPA_TXD0
IFPA_TXD0
IFPA_TXD1
IFPA_TXD1
IFPA_TXD2
IFPA_TXD2
IFPA_TXD3
IFPA_TXD3
IFPB_TXC
IFPB_TXC
IFPB_TXD4
IFPB_TXD4
IFPB_TXD5
IFPB_TXD5
IFPB_TXD6
IFPB_TXD6
IFPB_TXD7
IFPB_TXD7
IFPAB_RSET
IFPAB_PLLVDD
IFPB_IOVDD
IFPA_IOVDD
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
NET
IFPAB_PLLVDD
IFPAB_IOVDD
IFPAB_RSET
12MIL
12MIL
12MIL
VOLTAGE NV_NET_MAX_CURRENTMIN_LINE_WIDTH
0.035A1.8V
0.145A3.3V
DDC_5V
C872
4700PF
25V
G1
G94-400-A1
AR10
AK11
AP8
AP9
BGA1504
COMMON
AT9
AR9
AY6
AY7
AY8
AW9
AY9
AV9
AU9
BA10
BB10
BA4
AY5
BB6
BA6
BB7
BA7
BA9
IFPAB_TXC*
IFPAB_TXC
IFPAB_TXD0*
IFPAB_TXD0AW7
IFPAB_TXD1*
IFPAB_TXD1
IFPAB_TXD2*
IFPAB_TXD2
SNN_IFPAB_ATXD3*
SNN_IFPAB_ATXD3
SNN_IFPAB_BTXC*
SNN_IFPAB_BTXC
IFPAB_TXD4*
IFPAB_TXD4
IFPAB_TXD5*
IFPAB_TXD5
IFPAB_TXD6*
IFPAB_TXD6
SNN_IFPAB_TXD7*
SNN_IFPAB_TXD7BB9
IFPAB_TXC
IFPAB_TXC
IFPAB_TXD0
IFPAB_TXD0
IFPAB_TXD1
IFPAB_TXD1
IFPAB_TXD2
IFPAB_TXD2
IFPAB_TXD4
IFPAB_TXD4
IFPAB_TXD5
IFPAB_TXD5
IFPAB_TXD6
IFPAB_TXD6
90DIFF
1
90DIFF
1
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
90DIFF
1
1
90DIFF
14>
14>
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
14<>
14<>
14<>
14<>
14> 14<>
14>
14>
14>
14>
R643
1K
1%
0402
COMMON
IFPAB_RSET
IFPAB_IOVDD
IFPABCD_PLLVDD
C720
.1UF
6.3V
10%
X7R
0402
COMMON
120R@100MHz
COMMONBEAD_0402
GND
C781
4.7UF 1UF
6.3V
10%
X5R
0603
COMMON
GND
C776
6.3V
10%
X5R
0402
COMMON
C746
.1UF
6.3V
10%
X7R
0402
COMMON
IFP_IOVDD
LB511
C783
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
10%
X7R
0402
COMMON
GND
I2CA_SCL_C
I2CA_SDA_C
DACA_VS_C
GPIO0_DVI_A_HPD_C
DACA_RED_C
DACA_GREEN_C
DACA_BLUE_C
DACA_HS_C
C5A
25
26
27
28
17
18
9
10
1
2
3
11
19
12
13
4
5
20
21
6
7
14
15
22
24
23
8
16
C1
C2
C3
C5
J5
DVI-I
DVI_I_(SLIM_)SHLD_M
DVI_I
CHANGED
C4
29
30
31
32
DVIAB Hotplug Detection
21<
GPIO0_DVI_A_HPD
R13
10K
0402
COMMON
3V3
5%
2
3
1
D5
BAV99
SOT23
100V
100MA
COMMON
0402
R6
GND
IFP A/B Interface -- DVI Connector South
www.vinafix.vn
5%
3V3
GND
1K
COMMON
C12
.1UF
16V
10%
X7R
0603
COMMON
GPIO0_DVI_A_HPD_R
LB6
BEAD_0603
180R@100MHz
COMMON
GND
C6
220PF
50V
5%
C0G
0402
COMMON
GND
600-10547-0011-000 A
design
rachen
16 OF 32
07-AUG-2008
Page 17
Page17: IFP C/D Interface -- DVI Connector MID
BIBIBIININ
S
D
G
1917
81624
C1
C5A
C2
C3
C5
C4
SHLD24
SHLD13
SHLD05
SHIELD8
SHIELD5
SHIELD6
SHIELD7
SHIELD1
SHIELD2
SHIELD3
SHIELD4
TX0ÂTX1-
TX1+
TX2-
TX0+
TX2+
TX3ÂTX3+
TX4+
TX4-
DDCC
TX5+
TX5-
GND
VDDC
SHLDC
TXC-
DDCD
HPD
R
VSYNC
TXC+
G
AGND2
AGND1
B
HSYNC
INININININ
OUT
IFPC
IFPD
10/19 IFPCD
AUX
AUX
DPL0_TXD2
DPL0_TXD2
DPL1_TXD1
DPL1_TXD1
DPL2_TXD0
DPL2_TXD0
DPL3_TXC
DPL3_TXC
AUX
AUX
DPL1_TXD1
DPL1_TXD1
DPL2_TXD0
DPL2_TXD0
DPL3_TXC
DPL3_TXC
DPL0_TXD2
DPL0_TXD2
IFPCD_RSET
IFPCD_PLLVDD
IFPD_IOVDD
IFPC_IOVDD
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
NET
IFPCD_PLLVDD
IFPCD_IOVDD
IFPCD_RSET
12MIL
12MIL
12MIL
VOLTAGE NV_NET_MAX_CURRENTMIN_LINE_WIDTH
1.8V 0.035A
1.1V 0.800A
DVI PULL DOWNS
IFPCD_TXC*
IFPCD_TXC
IFPCD_TXD0*
IFPCD_TXD0
IFPCD_TXD1*
IFPCD_TXD1
C788
C790
C793
C805
C807
C809
IFPCD_TXD2*
IFPCD_TXD2
IFPCD_TXD4*
IFPCD_TXD4
IFPCD_TXD5*
IFPCD_TXD5
IFPCD_TXD6*
IFPCD_TXD6
.1UFC787
COMMON
C789
.1UF
COMMON
C791
.1UF
COMMON
C792
.1UF
COMMON
C804
.1UF
COMMON
C806
.1UF
COMMON
C808
.1UF
COMMON
.1UFC786
COMMON
.1UF
COMMON
.1UF
COMMON
.1UF
COMMON
.1UF
COMMON
.1UF
COMMON
.1UF
COMMON
G1
G94-400-A1
BGA1504
COMMON
SNN_IFPC_AUX*
AV6
SNN_IFPC_AUX
AN5IFPCD_RSET
AJ11
AN8IFPCD_IOVDD
AN9
GND
C774
4.7UF
6.3V
10%
X5R
0603
COMMONR665
C679
4.7UF
10%
X5R
0603
COMMON
IFPABCD_PLLVDD
C766
1UF
6.3V
10%
X5R
0402
COMMON
GND
C670
1UF
6.3V6.3V 6.3V 6.3V
10%
X5R
0402
COMMON
C739
.1UF
6.3V
10%
X7R
0402
COMMON
C736
.1UF
10%
X7R
0402
COMMON
IFPABCD_PLLVDD
R645
1K
1%
0402
COMMON
IFP_PLLVDD
C777
4.7UF
6.3V
10%
X5R
0603
COMMON
LB509
BEAD_0402
IFPABCD_PLLVDD_RC
GND
180R@100MHZ
COMMON
1
5%
0402
COMMON
PEX_VDD
GND
C672
4.7UF
10%
X5R
0603
COMMON
LB503
BEAD_0402
120R@100MHz
COMMON
GND
AU6
AV3
AW3
AV4
AY4
AW4
AW5
AW6
AT5
AU5
AW2
AW1
AY1
AY2
AY3
BA3
BB3
BB4
IFPC_TXC*
IFPC_TXCAU4
IFPC_TXD0*
IFPC_TXD0
IFPC_TXD1*
IFPC_TXD1
IFPC_TXD2*
IFPC_TXD2
SNN_IFPD_AUX*
SNN_IFPD_AUX
SNN_IFPD_L3*
SNN_IFPD_L3
IFPD_TXD4*
IFPD_TXD4
IFPD_TXD5*
IFPD_TXD5
IFPD_TXD6*
IFPD_TXD6
IFPC_TXD0
IFPC_TXD0
IFPC_TXD1
IFPC_TXD1
IFPC_TXD2
IFPD_TXD4
IFPD_TXD4
IFPD_TXD5
IFPD_TXD5
IFPD_TXD6
IFPD_TXD6
90DIFFIFPC_TXC 1
1 90DIFFIFPC_TXC
1
90DIFF
90DIFF
1
1
90DIFF
90DIFF
1
1
90DIFF
90DIFF
1IFPC_TXD2
90DIFF1
90DIFF
1
90DIFF
1
90DIFF
1
90DIFF
1
1
90DIFF
R672
0402
R673
0402
R675
0402
R678
0402
R697
0402
R699
0402
R701
IFPCD_TXC*
IFPCD_TXC
IFPCD_TXD0*
IFPCD_TXD0
IFPCD_TXD1*
IFPCD_TXD1
IFPCD_TXD2*
IFPCD_TXD2
IFPCD_TXD4*
IFPCD_TXD4
IFPCD_TXD5*
IFPCD_TXD5
IFPCD_TXD6*
IFPCD_TXD6
499
COMMON
1%
499
COMMON
1%
499
COMMON
1%
499
COMMON
1%
499
COMMON
1%
499
COMMON
1%
499
COMMON0402
1%
499
R671
COMMON
0402
1%
499
R674
COMMON
0402
1%
499
R676
COMMON
0402
1%
499
R677
COMMON
0402
1%
499
R696
COMMON
0402
1%
499
R698
COMMON
0402
1%
499
R700
COMMON
0402
1%
IFPCD_TXC 1
IFPCD_TXC 1
IFPCD_TXD1 1
IFPCD_TXD1 1
IFPCD_TXD2 1
IFPCD_TXD4 1
IFPCD_TXD5 1
IFPCD_TXD5 1
IFPCD_TXD6 1
3V3
R718
GND
C820
.1UF
6.3V
10%
X7R
0402
COMMON
1K
5%
0402
COMMON
IFPCD_TXD4*
IFPCD_TXD4
IFPCD_TXD5*
IFPCD_TXD5
IFPCD_TXD6*
IFPCD_TXD6
I2CB_SCL_C
I2CB_SDA_C
DACC_VS_C
GPIO1_DVI_C_HPD_C
DACC_RED_C
DACC_GREEN_C
DACC_BLUE_C
DACC_HS_C
DDC_5V
C874
4700PF
25V
10%
X7R
0402
COMMON
C5A
25
26
27
28
17
18
9
10
1
2
3
11
19
12
13
4
5
20
21
6
7
14
15
22
24
23
8
16
C1
C2
C3
C5
J4
DVI-I
DVI_I_(SLIM_)SHLD_M
DVI_I
CHANGED
C4
29
30
31
32
GND
Q511
BSS138
SOT23_1G1D1S
COMMON
HDMI_PD
CONTINUOUS_CURRENT=0.22A@31C
MAX_VOLTAGE=50V
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
3
1G1D1S
HDMI_PD_EN
1
2
GND
90DIFF
90DIFF
90DIFF
1IFPCD_TXD0
90DIFF
1IFPCD_TXD0
90DIFF
90DIFF
90DIFF
1IFPCD_TXD2
90DIFF
15>
15>
15>
15<>
15>
90DIFF
90DIFF
1IFPCD_TXD4
90DIFF
90DIFF
90DIFF
1IFPCD_TXD6
90DIFF
15<>
15>
15<>
15>
15<>
15<> 15>
Hotplug Detection
21<
www.vinafix.vn
GPIO1_DVI_C_HPD
R12
10K
5%
0402
COMMON
GND
3
IFP C/D Interface -- DVI Connector MID
3V3
1K
R5
COMMON
0402
5%
3V3
2
D2
BAV99
SOT23
100V
100MA
COMMON
1
GNDGND
GPIO1_DVI_C_HPD_R
C13
.1UF
16V
10%
X7R
0603
COMMON
LB5
180R@100MHz
COMMONBEAD_0603
GND
C3
220PF
50V
5%
C0G
0402
COMMON
GND
600-10547-0011-000 A
design
rachen
17 OF 32
07-AUG-2008
Page 18
Page18: IFP E/F Interface -- Unused
IFPE
IFPF
11/19 IFPEF
AUX
AUX
DPL0_TXD2
DPL0_TXD2
DPL1_TXD1
DPL1_TXD1
DPL2_TXD0
DPL2_TXD0
DPL3_TXC
DPL3_TXC
AUX
AUX
DPL1_TXD1
DPL1_TXD1
DPL2_TXD0
DPL2_TXD0
DPL3_TXC
DPL3_TXC
DPL0_TXD2
DPL0_TXD2
IFPEF_RSET
IFPEF_PLLVDD
IFPF_IOVDD
IFPE_IOVDD
BIBIBI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
G1
G94-400-A1
BGA1504
COMMON
SNN_IFPE_AUX*
AR7
SNN_IFPE_AUX
IFPEF_RSET
AM9
R632
1K
5%
0402
COMMON
GND
R624
1K
5%
0402
COMMON
GND
AH11IFPEF_PLLVDD
AR6
AP7
AP6
AP5
AP4
AP3
AR3
AU3
AT3
SNN_IFPE_TXC*
SNN_IFPE_TXC
SNN_IFPE_L2*
SNN_IFPE_L2
SNN_IFPE_L1*
SNN_IFPE_L1
SNN_IFPE_L0*
SNN_IFPE_L0
AN6IFPEF_IOVDD
R638
1K
5%
0402
COMMON
GND
IFPEF_PLLVDD
IFPEF_IOVDD
IFPEF_RSET
12MIL
12MIL
12MIL
AN7
NV_NET_MAX_CURRENTVOLTAGENET MIN_LINE_WIDTH
AT4
AR4
AN2
AN1
AP1
AP2
AT1
AU1
AU2
SNN_IFPF_AUX*
SNN_IFPF_AUX
SNN_IFPF_L3*
SNN_IFPF_L3
SNN_IFPF_L2*
SNN_IFPF_L2
SNN_IFPF_L1*AT2
SNN_IFPF_L1
SNN_IFPF_L0*
SNN_IFPF_L0
IFP E/F Interface -- Unused
www.vinafix.vn
600-10547-0011-000 A
design
rachen
18 OF 32
07-AUG-2008
Page 19
Page19: DACB and HDTV/SDTV-Out
INININININININININ
out
7P_COMP_10P
out
out NC
Y/CVBS
GND
NC
Pb out
C/Pr
GND
7/19 DACB(TV)
DACB_CSYNC
DACB_BLUE
DACB_GREEN
DACB_RED
DACB_VREF
DACB_VDD
DACB_RSET
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
DACB_COUT
DACB_COUT_C
DACB_YOUT
DACB_YOUT_C
DACB_PBOUT
DACB_PBOUT_C
NV_CRITICAL_NETNET NET
1 75OHM
1 75OHM
1 75OHM
1 75OHM
1 75OHM
IMPEDANCE
75OHM1
3V3
2
1
GND
NV_NET_MAX_CURRENT
DACB_YOUT
3
0.100A
GND
R654
150
1%
0402
NO STUFF
NET
19<
19<
DACB_VREF
DACB_VREF
DACB_RSET
12MIL
12MIL
12MIL
VOLTAGEMIN_LINE_WIDTH
3.3V
8.2PF
C861
+/-0.5PF
50V0603
NO STUFF
NPO
C862
0603
180R@100MHz
NO STUFF
C866
82PF82PF150150
50V
C0G
0402
NO STUFF
8.2PF
+/-0.5PF
50V
NPO
180R@100MHz
NO STUFF
C867
82PF82PF150
50V
C0G
0402
NO STUFF
5%
GND
SNN_DACB_STEREO_C
DACB_PBOUT_C
DACB_COUT_C
5%
GND
GND
7
6
4
2
J3
CON_MINIDIN_7
7P_COMP_10P
NO STUFF
98
GND
SNN_DACB_TV_STEREO_C
5
DACB_YOUT_C3
1
10
8.2PF
C863
+/-0.5PF
50V0603
NO STUFF
NPO
L504
BEAD_0603
C868
82PF
50V
5%
C0G
0402
NO STUFF
GND
180R@100MHz
NO STUFF
C854
82PF
NO STUFF
0402
R757
150
50V
5%
C0G
1%
0402
NO STUFF
GND
D503
BAV99
SOT23
100V
100MA
NO STUFF
GND
L502
R661
1%
0402
AL11
AN3DACB_VREF
AL3
G1
G94-400-A1
BGA1504
COMMON
SNN_DACB_CSYNC
AK2
DACB_COUT
AK1
DACB_YOUT
AL1
DACB_PBOUTAL2
3V3
C758
.1UF
10V
10%
X5RX5R
0402
NO STUFF
DACB_VDD
DACB_RSET
R666
124
1%
0402
NO STUFF
LB510
C785
4.7UF
6.3V
10%
X5R
0603
NO STUFF
GND
240R@100MHz
NO STUFFBEAD_0402
GND
GND
C780
4.7UF
6.3V
10%
X5R
0603
NO STUFF
C730
.1UF
6.3V
10%
X7R
0402
NO STUFF
C775
0
6.3V
5%
0402
CHANGED
GND
GND
NO STUFF
R658
150
1%
0402
NO STUFF
2
D501
BAV99
3
SOT23
100V
100MA
NO STUFF
1
GND
GND
3V3
2
D502
BAV99
3
SOT23
100V
100MA
NO STUFF
1
GND
GND
3V3
R755
1%
0402
NO STUFF
R756
1%
0402
NO STUFF
GND
GND
BEAD_0603
C852
50V
5%
C0G
0402
NO STUFF
NO STUFF
L503
BEAD_0603
C853
50V
5%
C0G
0402
NO STUFF
FILTER CIRCUIT
HDTV/SDTV
from codec
82pF/330pF
www.vinafix.vn
DACB and HDTV/SDTV-Out
8.2pF/22pf
0.56uH/1.8uH
to DIN connector
82pF/270pF
600-10547-0011-000 A
design
rachen
19 OF 32
07-AUG-2008
Page 20
Page20: MIO A/B Interface
IN
SLI - EMI SHIELD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RASTER_SYNC
DR<0>
DR<1>
DR<5>
DR<2>
DR<3>
DR<4>
DR<9>
DR<8>
DR<7>
DR<6>
DR<10>
DR<11>
DR<12>
DR<13>
DR<14>
DR_CMD
DR_CLK
SWAP_RDY
EXT_REFCLK
BI
BI
12/19 MIOA
MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8
MIOAD9
MIOAD10
MIOAD11
MIOAD12
MIOAD13
MIOAD14
MIOA_CLKIN
MIOA_CLKOUT
MIOA_CLKOUT
MIOA_VSYNC
MIOA_HSYNC
MIOA_DE
MIOA_CTL3
MIOACAL_PD_VDDQ
MIOACAL_PU_GND
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOA_VREF
OUT
OUT
OUT
13/19 MIOB
MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11
MIOBD12
MIOBD13
MIOBD14
MIOBD15
MIOBD16
MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT
MIOB_CTL3
MIOBD17
MIOB_DE
MIOB_VSYNC
MIOB_HSYNC
MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VREF
INININININININ
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
MIO Feature Connector
MIOA_D<14..0>
2V5
R663
1K
1%
0402
COMMON
R660
1K
1%
0402
COMMON
MIOA_VDDQ
MIOA_CAL_PD_VDDQ
MIOA_CAL_PU_GND
MIOA_VREF
LB512
C831
4.7UF 4.7UF
6.3V
10%
X5R
0603
COMMON
GND
220R@100MHz
COMMONBEAD_0805
C822
6.3V
10%
X5R
0603
COMMON
GND
C743
1UF
6.3V
10%
X5R
0402
COMMON
.1UF .01UF.01UF
6.3V
10%
X7R
0402
COMMON
16V
10%
X7R
0402
C733C732C738
16V
10%
X7R
0402
COMMONCOMMON
49.9
R664
COMMON
0402
1%
49.9
R655
COMMON
0402
1%
GND
C735
.1UF
10V
10%
X5R
0402
COMMON
GND
AB11
AC11
AC9
AD11
AD7
AE7
AG8
G1
G94-400-A1
BGA1504
COMMON
AE1
AE2
AE3
AG3
AG2
AG1
AF4
AF6
AG4
AG5
AG6
AG7
AD8
AE9
AD9
AD6
AD5
AE4
AE6
AE5
AE8
MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8
MIOA_D9
MIOA_D10
MIOA_D11
SNN_MIOA_D12
SNN_MIOA_D13
SNN_MIOA_D14
MIOA_D12AD4
MIOA_D13
MIOA_D14
MIOA_DE
MIOA_CLKOUT
SNN_MIOA_CLKOUT*
MIOA_CLKIN
MIOA_D0
21>
21>
0
1
22
3
4
5
6
7
8
9
10
11
12
13
14
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8
MIOA_D9
MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13
MIOA_D14
GPIO11_SLI_SYNC1
GPIO22_SWAPRDY_A
0
1
3
4
5
6
7
8
9
10
11
12
13
14
20<
CN1
CON_MIO_26_EDGE_4GND
NONPHY_4GND
NO STUFF
A2
B4
A4
A5
B6
A6
A8
B9
B10
A10
B12
A12
A13
B5
A9
B13
B8
A1
B1
B2
B3
B7
B11
A3
A7
A11
1
2
3
4
GND
GND
G1
G94-400-A1
AE11
AF11
AF9
AG9
AH6
AL8
AL7
BGA1504
COMMON
SNN_MIOB_D0
AH4
SNN_MIOB_D1
AH1
SNN_MIOB_D2
AH2
SNN_MIOB_D3
AH3
SNN_MIOB_D4
AK3
SNN_MIOB_D5
AL4
SNN_MIOB_D6
AK5
SNN_MIOB_D7
AM6
SNN_MIOB_D8
AL6
SNN_MIOB_D9AL5
SNN_MIOB_D10
AM4
SNN_MIOB_D11
AN4
SNN_MIOB_D12
AK8
SNN_MIOB_D13
AJ6
SNN_MIOB_D14
AK7
MIOB_D15_STRAP0
AJ9
MIOB_D16_STRAP1
AK9
MIOB_D17_STRAP2
AL9
SNN_MIOB_CTL3
AH8
MIOB_HSYNC
AH7
SNN_MIOB_VSYNC
AH9
SNN_MIOB_DE
AH5
SNN_MIOB_CLKOUT
AJ4
SNN_MIOB_CLKOUT*
AK4
MIOB_CLKINAK6
R648
0402
MIO A/B Interface
www.vinafix.vn
TP501
5%
10K
COMMON
22<
22<
22<
3V3
C39
.1UF
10V
10%
X5R
0402
COMMON
GND
GND
R649
0402
R667
0402
1%
1%
49.9
NO STUFF
49.9
NO STUFF
R653
1K
1%
0402
NO STUFF
R650
1K
1%
0402
NO STUFF
MIOB_CAL_PD_VDDQ
MIOB_CAL_PU_GND
MIOB_VREF
GND
20<
NET NV_CRITICAL_NET
MIOA_D<14..0> 1
MIOA_DE
NET MIN_LINE_WIDTH
50OHM
2.5V
1.65V
2.5V
0.0V
50OHM
50OHM
50OHM
1MIOA_CLKIN
1MIOA_CLKOUT
1
16MILMIOA_VDDQ
12MILMIOA_VREF
12MILMIOA_CAL_PD_VDDQ
12MILMIOA_CAL_PU_GND
DIFFPAIRIMPEDANCE
NV_NET_MAX_CURRENTVOLTAGE
0.80A
GND
600-10547-0011-000 A
design
rachen
20 OF 32
07-AUG-2008
Page 21
50OHM
INININININ
VCC
VCC
GND
GND
SCL
SDA
NC
SDA
16/19 XTAL_PLL
XTALOUT
XTALOUTBUFF
VID_PLLVDD
SP_PLLVDD
PLLVDD
XTALSSIN
XTALIN
VCC
GND
HOLD
WP
CS
SI
SCK
SO
OUT
OUT
OUT
OUT
OUT
OUT
OUTINOUTININ
OUT
OUT
OUT
OUT
OUT
OUTINOUT
15/19 MISC2
ROM_SO
ROM_SI
ROM_SCLK
ROM_CS
I2CH_SDA
I2CH_SCL
SPDIF
RFU
PGOOD_OUT
RFU_GND
BUFRST
BBIASN_NC
BBIASP_NC
HDA_BCLK
HDA_RST
HDA_SDI
HDA_SDO
HDA_SYNC
STRAP_REF_MISC
STRAP_REF_MIOB
14/19 MISC1
GPIO2
GPIO5
GPIO4
GPIO3
GPIO1
GPIO0
I2CC_SCL
I2CC_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
I2CS_SCL
I2CS_SDA
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST
THERMDN
THERMDP
JTAG_TCK
ININOUTININ
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
50OHM
50OHM
50OHM
0.03A
DIFFPAIR
MIN_WIDTH
12MIL
Page21: MISC: GPIO, I2C, ROM, HDCP, and XTAL
G1
G94-400-A1
BGA1504
COMMON
R635
10K
5%
0402
CHANGED
L31
L30
Y11
W11
AP12
AR12
AR13
AP13
AP14
V7
U6
T7
V6
T1
T2
G1
G94-400-A1
BGA1504
COMMON
SNN_BBIASN
SNN_BBIASP
SNN_HDSA_BCLK
HDA_RST*
SNN_HDA_SDI
SNN_HDA_SDO
SNN_HDA_SYNC
GND
40.2K
R631
NO STUFF
0402
1%
40.2K
R630
COMMON
0402
1%
Binary Production Strap Mode:
GND
STRAP_CALPD_MIOB = 40.2K 1%
STRAP_CALPD_MISC = NO STUFF
C40
2200PF
10V
10%
X5R
0402
NO STUFF
2>
2>
2>
2<
2>
STRAP_CALPD_MISC
STRAP_CALPD_MIOB
THERMDN
THERMDP
JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
T4
V4
U4T6
T5
Y6
AA6
V5
V8
T8
L15
AP15
W2
W1
W3
W4
Y4
AA5
W6
W5
AB1
AB2
AB3
AD1
AD2
AD3
AB4
AB5
AB6
AB7
AB8
AB9
AC4
AC6
AA8
T9
U9
V9
W9
Y9
AA9
W7
W8
AA7
ROM_CS*
ROM_SI
ROM_SO
ROM_SCLK
I2CH_SCL
I2CH_SDA
SPDIF
SNN_BUFRST*
SNN_PGOOD_OUT*
GND
I2CS_SCL
I2CS_SDA
I2CC_SCL
I2CC_SDA
SNN_I2CD_SCL
SNN_I2CD_SDA
SNN_I2CE_SCL
SNN_I2CE_SDA
GPIO0_DVI_A_HPD
GPIO1_DVI_C_HPD
SNN_GPIO2
GPIO3_NVVDD_PHASE
GPIO4_FAN_TACH
GPIO5_VSEL0
GPIO6_VSEL1
GPIO7_FBVDDQ_SEL
GPIO8_GPU_SLOW*
GPIO9_FAN_PWM
SNN_GPIO10
GPIO11_SLI_SYNC1
SNN_GPIO12
SNN_GPIO13
SNN_GPIO14
SNN_GPIO15
SNN_GPIO16
SNN_GPIO17
SNN_GPIO18
SNN_GPIO19
SNN_GPIO20
SNN_GPIO21
GPIO22_SWAPRDY_A
SNN_GPIO23_STEREO
22<
22<
22<
3V3
3V3
R721
R729
47K
47K
5%
5%
0402
0402
CHANGED
CHANGED
R722
0402
3V3
R689
10K
5%
7
0402
3
COMMON
1
5
2
6
25>
25<
3V3
R706
2.2K
5%
0402
COMMON
5%
R693
0402
33
NO STUFF
5%
16>
17>
29<
31>
29<
29<
28<
25<
31<
R730
33
COMMON
0402
5%
33
NO STUFF
R692
33
COMMON0402
5%
20<>
3V3
R34
1K
1%
0402
COMMON
U503
MX25L512
SO8
SO8
COMMON
XTALSSIN
XTALIN
XTALOUT
XTALOUTBUFF
3V3
NET
GPU_PLLVDD
1
1
1
1
1.1V
NV_CRITICALNET
NV_IMPEDANCE
MAX_CURRENTVOLTAGE
8
C814
.1UF
10V
10%
X5R
4
0402
COMMON
GND
3V3
R707
2.2K
5%
0402
COMMON
PEX_SMCLK
PEX_SMDAT
I2CC_SCL_R
I2CC_SDA_R
2>
2>
GND
3V3
2K
5%
0402
COMMON
R720
10K
5%
0402
NO STUFF
R716R719
2K
5%
0402
COMMON
R709
0402
5%
0
NO STUFF
I2CH_SCL
I2CH_SDA
R708
0
5%
0402
COMMON
GND
U504
HDCP_KEYROM_PROGD_V3
SO8
COMMON
6
5
3I2CH_SDA_R
2
3V3
8
7
4
1
C829
.1UF
10V
10%
X5R
0402
COMMON
GND
GPIO TABLE
Function
I/O
20<>
GPIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DVI HOTPLUG DET A
IN
HDMI HOTPLUG DET E
IN
SWAPREADY
N/A
NVVDD PHASE CONTROL
N/A
PWM TACH SIGNAL
N/A
VOLTAGE SELECT 0
OUT
VOLTAGE SELECT 1
OUT
FBVVDQ VOLTAGE CONTROL
N/A
GPU_SLOW*
IN
PWM FAN CONTROL
OUT
UNUSED
N/A
SLI_RASTERY_SYNC
N/A
EXT_12V DETECT
IN
UNUSED
OUT
UNUSED
IN
UNUSED
IN
DP_MODE
IN
HDMI_EF
IN
UNUSED
IN
HDMI_CEC
IN
DP HOTPLUG DET F
IN
UNUSED
IN
SWAPREADY_A
IN
UNUSED
OUT
1V1_PLL
LB506
BEAD_0402
C697
1UF
6.3V
10%
X5R
0402
NO STUFF
PEX_VDD
LB505
C680
1UF 1UF1UF
6.3V
10%
X5R
0402
COMMON
BEAD_0402
120R@100MHz
COMMON
GND
MISC: GPIO, I2C, ROM, HDCP, and XTAL
www.vinafix.vn
120R@100MHz
NO STUFF
C711
6.3V
10%
X5R
0402
COMMON
C692
6.3V
10%
X5R
0402
COMMON
6.3V
10%
X7R
0402
COMMON
GND
R657
10K
0402
COMMON
C704C705
.1UF.1UF
6.3V
10%
X7R
0402
COMMON
5%
XTALSSIN
GNDGND
C41
22PF
50V
5%
C0G
0402
COMMON
AM13GPU_PLLVDD
AM15
AM14
V3
V1
G1
G94-400-A1
BGA1504
COMMON
XTAL_4PIN_HOSONIC
Y1XTALIN
+/-10 PPM
H10SSMD
COMMON
XTALOUTBUFF
T3
V2
27 MHZ
XTALOUT
C37
22PF
50V
5%
C0G
0402
COMMON
GND
GND
600-10547-0011-000 A
design
rachen
R656
330
5%
0402
COMMON
21 OF 32
07-AUG-2008
Page 22
Page22: Strap Configuration
19/19 NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
INININININ
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
3V3
R681
4.99K
1%
0402
21>
ROM_SI
COMMON
R668
4.99K
1%
0402
NO STUFF
STRAP PIN
ROM_SI
STRAP NAME
PCI_DEVID_EXT
GND
3V3
R680
4.99K
1%
0402
GND
COMMON
R670
4.99K
1%
0402
NO STUFF
21>
ROM_SO
STRAP PIN
ROM_SO
STRAP NAME
SLOT_CLK_CFG
3V3
21>
ROM_SCLK
R679
4.99K
1%
0402
NO STUFF
R669
4.99K
1%
0402
COMMON
STRAP PIN
ROM_SCLK
STRAP NAME
PCI_DEVID[3]
GND
3V3
20>
20>
20>
MIOB_D15_STRAP0
MIOB_D16_STRAP1
MIOB_D17_STRAP2
GND
3V3
GND
3V3
GND
R45
4.99K
1%
0402
NO STUFF
R48
4.99K
1%
0402
COMMON
R46
4.99K
1%
0402
COMMON
R49
4.99K
1%
0402
NO STUFF
R47
4.99K
1%
0402
NO STUFF
R50
4.99K
1%
0402
COMMON
STRAP PIN
STRAP0
STRAP PIN
STRAP1
STRAP PIN
STRAP2
STRAP NAME
RAMCFG0
STRAP NAME
RAMCFG1
STRAP NAME
RAMCFG2
*
RAMCFG[2:0]
256MB (8Mx32)
101 --- 256-bit Qimonda
110 --- 256-bit Hynix
111 --- 256-bit Samsung
512MB (16Mx32)
001 --- 256-bit Qimonda
010 --- 256-bit Hynix
011 --- 256-bit Samsung
* VBIOS will be defined on a per SKU basis.
Strap Configuration
www.vinafix.vn
1024MB (32Mx32)
101 --- 256-bit Hynix
110 --- 256-bit Hynix
111 --- 256-bit Samsung
3V3
G1
G94-400-A1
BGA1504
GND
SNN_NC<1>
15K
0
SNN_NC<2>
SNN_NC<3>
SNN_NC<4>
SNN_NC<5>
SNN_NC<6>
SNN_NC<7>
SNN_NC<8>
SNN_NC<9>
SNN_NC<10>
SNN_NC<11>
SNN_NC<12>
SNN_NC<13>
SNN_NC<14>
SNN_NC<15>
SNN_NC<16>
SNN_NC<17>
SNN_NC<18>
SNN_NC<19>
SNN_NC<20>
SNN_NC<21>
SNN_NC<22>
SNN_NC<23>
SNN_NC<24>
SNN_NC<25>
SNN_NC<26>
SNN_NC<27>
SNN_NC<28>
SNN_NC<29>
SNN_NC<30>
SNN_NC<31>
SNN_NC<32>
SNN_NC<33>
SNN_NC<34>
SNN_NC<35>
SNN_NC<36>
SNN_NC<37>
SNN_NC<38>
SNN_NC<39>
SNN_NC<40>
SNN_NC<41>
SNN_NC<42>
SNN_NC<43>
SNN_NC<44>
SNN_NC<45>
SNN_NC<46>
SNN_NC<47>
SNN_NC<48>
SNN_NC<49>
SNN_NC<50>
SNN_NC<51>
SNN_NC<52>
SNN_NC<53>
SNN_NC<54>
SNN_NC<55>
SNN_NC<56>
SNN_NC<57>
SNN_NC<58>
SNN_NC<59>
SNN_NC<60>
SNN_NC<61>
SNN_NC<62>
SNN_NC<63>
SNN_NC<64>
SNN_NC<65>
SNN_NC<66>
SNN_NC<67>
SNN_NC<68>
SNN_NC<69>
SNN_NC<70>
SNN_NC<71>
SNN_NC<72>
SNN_NC<73>
SNN_NC<74>
SNN_NC<75>
AC34
AC36
AC37
AC7
AF34
AF36
AF37
AF7
AG37
AG38
AH40
AJ7
AK32
AL32
AL40
AM29
AM30
AM31
AM32
AM7
AP34
AR36
AT11
AT13
AT35
AU14
AU17
AU20
AU23
AU26
AV10
AV12
AV28
AY31
C12
E15
E16
F16
F17
F20
F23
F31
G17
G20
G23
G26
G29
H28
J17
J20
J23
J29
L14
L16
L28
L29
M37
P11
P34
P36
R11
R35
T11
U11
U36
Y34
Y36
Y37
COMMON
G8
H7
J9
M3
R3
U7
Y7
600-10547-0011-000 A
design
rachen
22 OF 32
07-AUG-2008
Page 23
17/19 GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
18/19 NVVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
AB20
AJ17
B8
AJ15
AB19
AJ13
AG30
AG24
AG26
AG28
AG22
AG20
AB18
AG16
AG18
AG14
AG11
AF41
AF5
AF8
AF38
AF35
AF30
AK25
AK26
AK27
AK28
AK29
AK30
AM2
AM35
AM38
AC38
AC41
AC5
AC8
AB15
AE21
AK24
AK23
AK22
AK21
AE19
AE17
AE15
AE13
www.vinafix.vn
BA20
BA2
BA11
BA14
BA17
AM8
AM5
AP23
AP20
AM41
PWR and GND Signals
BA23
AP26
BA26
AR11
BA29
AR14
BA32
AR17
BA35
AR2
BA38
AR20
BA41
AR23
BA5
AR26
BA8
AR29
C3
AR32
AR35
E14
AR38
E17E2E11
AR41
AR5
E20
AR8
E23
AT14
E26
AT17
E29
AT20
E35
E32
AT26
AT23
E38
AU37
E41
AV11
E5
AV14
G94-400-A1
BGA1504G1COMMON
GND
AE23
AA11
AE25
AB21
AE27
AB22
AE29
AB23
AF13
AB24
AF14
AB25
AF15
AB26
AF16
AB27
AF17
AB28
AF18
AB29
AB16
AB30
AF19AB13
AF2
AC14
AF20
AC16
AF21
AC18
AF22
AC2
AF23
AC20
AF24
AC22
AF25
AC24
AF26
AC26
AF27
AC28
AB17
AC30
AF28
AB14
AF29
AC35
Page23: PWR and GND Signals
G1
G94-400-A1
BGA1504
COMMON
AA13
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AC13
AA14
AC15
AC17
AC19
AC21
AC23
AC25
AC27
AC29
AD13
AD14
AA15
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AA16
AD25
AD26
AD27
AD28
AD29
AD30
AE14
AE16
AE18
AE20
AA17
AE22
AE24
AE26
AE28
AE30
AG13
AA18
AA19
AA20
AA21
P20
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG29
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
Y27
Y29
N23
N24
N25
N26
N27
N28
N29
N30
P14
P16
P18
N22
AH28
N21
AH29
AH30
AJ14
AJ16
AJ18
AJ20
AJ24
AJ26
AJ28
AJ30
N20
N13
N14
N15
N16
N17
N18
N19
P22
P24
P26
P28
P30
T13
T15
T17
T19
T21
T23
T25
T27
T29
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
V14
V16
V18
V20
V22
V24
V26
V28
V30
Y13
Y15
Y17
Y19
Y21
Y23
Y25
NVVDD
AJ19
AV17
AJ2
AV2
AJ25
AJ23
AV23
AV20
AJ27
AV26
AJ29
AV29
AJ35
AV32
AJ38
AV35
AJ41
AV38
AJ5
AV41
AJ8
AV5
AK13
AV8
AK14
AY40
AK15
B11
AK16
B14
AK17
AK18
AK20E8F26
AK19
B23
B20B2B17
B26
B29
B32
B35
B38
H14
Y8Y5Y41
Y22
Y24
Y38
Y20
Y18
W30
Y14
Y16
R23
R22
R19
R20
R21
R18
R17
R16
R13
R14
R15
P5P8P41
P37
P38
P35
P29
P23
P25
P27
P21
P2
P15
P17
P19
P13
L8
L38
L41L5L35
L2
H41H5H8
H38
H35
H26
H29
H32
H23
H20
H17H2H11F6F29
U8
U5
V17
V15
V13
V11
U41
U38
U37
U35U2T30
T28
T26
T24
T22
T20
T18
T16
T14
R30
R29
R28
R27
R26
R25
R24B5B41
V19
V21
V23
V25
V27
V29
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
Y35
Y30
Y28
Y26Y2W29
600-10547-0011-000 A
design
rachen
23 OF 32
07-AUG-2008
Page 24
Page24: NVVDD and FBVDDQ Decoupling
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
NVVDD
NVVDD
Place under GPU
C712
.1UF
6.3V
10%
X7R
0402
COMMON
C699
.1UF
10V
10%
X5R
0402
COMMON
C703
.22UF
6.3V
10%
X5R
0402
COMMON
C709
.22UF
6.3V
10%
X5R
0402
COMMON
C685
1UF
6.3V
10%
0402
COMMON
C674
1UF
6.3V
10%
X5R
0402
COMMON
C663
.1UF
10V
10%
X5R
0402
COMMON
C639
.1UF
6.3V
10%
X7R
0402
COMMON COMMON
C664
.1UF
10V
10%
X5R
0402
COMMON
C676
6.3V
10%
X5R
0402
COMMON
C641
.22UF
6.3V
10%
X5R
0402
COMMON
C652
1UF
6.3V
10%
X5R X5RX5R X5R
0402
COMMON COMMON
C677
.1UF
10V
10%
X5R
0402
COMMON
C691
.1UF
10V
10%
X5R
0402
COMMON
C694
.1UF
6.3V
10%
X7R
0402
C684
.1UF
10V
10%
X5R
0402
COMMON
C715
6.3V
10%
X5R
0402
COMMON
C700
.22UF
6.3V
10%
X5R
0402
COMMON
C702
1UF
6.3V
10%
0402
C671
.1UF
10V
10%
X5R
0402
COMMON
C645
.1UF
10V
10%
X5R
0402
COMMON
C683
.1UF
10V
10%
X5R
0402
COMMON
C667
.22UF.22UF .22UF
6.3V
10%
X5R
0402
COMMON
C660
.22UF
6.3V
10%
X5R
0402
COMMON
C657
1UF
6.3V
10%
0402
COMMON
C643
.1UF
10V
10%
X5R
0402
COMMON
NVVDD
GND
GND
GND
GND
GND
GND
NVVDD
Place close to GPU
C832
10UF
10V
10%
X5R
0805
NO STUFF
C590
10UF
10V
10%
X5R
0805
NO STUFF
C678
47UF
6.3V
20%
X5R
1206
COMMON
C648
10UF
10V
10%
X5R
0805
COMMON
C592
10UF
10V
10%
X5R
0805
NO STUFF
C602
6.3V
20%
X5R
1206
NO STUFF NO STUFF
C812
10UF
10V
10%
X5R
0805
NO STUFF
C599
10UF 10UF
10V
10%
X5R
0805
NO STUFF
C762
47UF47UF
6.3V
20%
X5R
1206
C622
10UF
10V
10%
X5R
0805
NO STUFF
C799
10V
10%
X5R
0805
NO STUFF
FBVDDQ
FBVDDQ
GND
GND
GND
Place near BGA
C751
.1UF
10V
10%
X5R
0402
COMMON
C701
.1UF
10V
10%
X5R
0402
COMMON
C630
.47UF
6.3V
10%
X5R
0402
COMMON
C637
.47UF
6.3V
10%
X5R
0402
COMMON
C632
1UF
6.3V
10%
X5R
0402
COMMON
C629
4.7UF
6.3V
10%
X5R
0603
COMMON
C757
.1UF
10V
10%
X5R
0402
COMMON
C623
.1UF
10V
10%
X5R
0402
COMMON
C750
.47UF
6.3V
10%
X5R
0402
COMMON
C737
.47UF
6.3V
10%
X5R
0402
COMMON
C728
1UF
6.3V
10%
X5R
0402
COMMON
C729
.1UF
6.3V
X7R
0402
COMMON
C628
.47UF
6.3V
10%
X5R
0402
COMMON COMMON
C619
.47UF
6.3V
10%
X5R
0402
COMMON
C627
1UF
6.3V
10%
X5R
0402
COMMON
C727
4.7UF
6.3V
10%
X5R
0603
COMMON
C710
.1UF
10V
10%10%
X5R
0402
COMMON
C615
.47UF
6.3V
10%
X5R
0402
C631
.47UF
6.3V
10%
X5R
0402
COMMON
C616
1UF
6.3V
10%
X5R
0402
COMMON
C634
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
GND
GND
GND
GND
GND
C707
4.7UF
6.3V
10%
X5R
0603
COMMON
C713
4.7UF
6.3V
10%
X5R
0603
COMMON
C655
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
GND
NVVDD and FBVDDQ Decoupling
www.vinafix.vn
600-10547-0011-000 A
design
rachen
24 OF 32
07-AUG-2008
Page 25
Page25: SPDIF Input, Thermal Protection, and IFP_IOVDD Power Supply
OUTININININININ
S
DGC
E
B
POLYSWITCH
C
E
B
OUT
C
E
B
IN
C
E
B
S
D
G
S
DGD
SGS
D
G
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
SPDIF_IN_C
SPDIF_IN_R
SPDIF_IN_COMP2_D
SPDIF_IN_COMP2_Q
IMPEDANCENET
NV_CRITICAL_NET
156OHM
156OHM
156OHM
156OHM
SPDIF_IN
21< 25>
SPDIF
75OHM
56OHM
IFP_IOVDD Backdrive PreventionThermal Protection
C828
.1UF
16V
10%
X7R
0402
COMMON
THERM_N_EN3_R1
THERM_N_EN3_R2
GND
GPIO8_GPU_SLOW*
THERM_N_EN2
1B1C1E
1
C827
1000PF
16V
10%
X7R
0402
COMMON
C817
1000PF
16V
10%
X7R
0402
COMMON
Q512
MMBT2222A
SOT23_1B1C1E
COMMON
1B1C1E
GND
3
2
GND
1
C841
4.7UF
6.3V
10%
X5R
0603
COMMON
R728
2K
5%
0402
COMMON
R727
2K
5%
0402
COMMON
3
Q513
MMBT2222A
SOT23_1B1C1E
COMMON
2
GND
0.2A
16MIL
NVVDD_EN
GND
IFP_IOVDD
GND
C816
1000PF
16V
10%
X7R
0402
COMMON
C840
.1UF
16V
10%
X7R
0402
COMMON
29<
3V3
R739
2K
5%
0402
COMMON
THERM_N_EN1
1G1D1S
1
1
PEX_RST_R*1KR741PEX_RST*
3
Q518
BSS138
SOT23_1G1D1S
COMMON
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
C844
100PF
50V
5%
C0G
0402
COMMON
GND
1G1D1S
2>
0402
COMMON
5%
THERM_N_EN1_R
3
Q517
BSS138
SOT23_1G1D1S
COMMON
2 3
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
3V3
Q514
MMBT4403
SOT23_1B1C1E
COMMON
THERM_N_EN3
R724
33K
5%
0402
COMMON
GND
2
R738
2K
5%
0402
COMMON
1B1C1E
1
R726
0402
R725
0402
10K
COMMON
5%
10K
COMMON
5%
3V3
21<
1G1D1S
3V3_TMDS_IOVDD_EN
10K
R735
0402
5%
COMMON
1
3
Q515
BSS138
SOT23_1G1D1S
COMMON
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
1G1D1S
3
Q516
SI2305DS
SOT23_1G1D1S
1
COMMON
2
MAX_VOLTAGE=-8V
CONTINUOUS_CURRENT=-2.8A@70C
R_DS_ON=52mR
MAX_CURRENT=-6A
MAX_WATTAGE=0.8W@70C
V_BE_GS=+/-8V
SPDIF Input
Black, RA, 2.0mm, SPDIF connector
J8
HDR_1M2
MALE
2.0MM
90
SPDIF
COMMON
NV_CRITICAL_NET=1
NV_IMPEDANCE=75OHM
1
SPDIF_IN
2
SPDIF_GND
R747
0
5%
0402
COMMON
3V3
2
D9
BAV99
3
SOT23
100V
100MA
COMMON
1
NV_CRITICAL_NET=1
1
16MIL
0V
F501
200mA
1206
NO STUFF
C14
0402
16V
10%
X7R
COMMON
SPDIF
NV_IMPEDANCE=56OHM
.01UF
short circuit protection
if 3.3V connects to GND.
GND
2
GND
12V
3
Q2
MMBT2222A
1
SOT23_1B1C1E
COMMON
2SPDIF_IN_R
GND
R16
0402
3V3
R17
33K
5%
0402
COMMON
SPDIF_IN_C
2.2K
COMMON
5%
GND
C15
.1UF
16V
10%
X7R
0402
COMMON
R20
0402
10K
COMMON
5%
1B1C1E
R25
10K
5%
0402
COMMON
SPDIF_IN_COMP2_D
3V3
R19
180K
5%
0402
NO STUFF
R18
180K
5%
0402
COMMON
GND
NV_IMPEDANCE=56OHM
NV_CRITICAL_NET=1
GND
SPDIF_IN_COMP2_Q
1G1D1S
C19
.01UF
16V
10%
X7R
0402
COMMON
1
1
1
R22
75
5%
0805
COMMON
3
Q3
BSS138
SOT23_1G1D1S
COMMON
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
R21
75
5%
0805
NO STUFF
GND
25< 21<
GND
SPDIF Input, Backdrive Protection, and IFP_IOVDD Power Supply
www.vinafix.vn
600-10547-0011-000 A
design
rachen
25 OF 32
07-AUG-2008
Page 26
Page26: PS I: 3V3, 12V, and 12V_EXT Power Supply Filter
OUT
S
D
G
PRSNT*
GND
12V
12V
12V
GND
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
12V_EXT
12V
MIN_WIDTHMAX_CURRENTVOLTAGENET
12V_EXT
12V
GND
GND
NV_SOURCE_POWER_NET
NV_SOURCE_POWER_NET
NV_SOURCE_POWER_NET
12V 6.25A
5.5A12V
28A0V
16MIL
16MIL
16MIL
12V Power Supply Filter
INPUT POWER SELECTION for NVVDD
12V_F = 12V @ 5.5A
12V
1 UH
L11
NO STUFF
C73
10UF
16V
10%
X5R
1206
COMMON
GND
7_6X7_6
MAX_CURRENT=10.2A
DC_RESISTANCE=8.4mR
R77
0805
R70
0805
0805
R73
0805
0
COMMON
5%
0
COMMON
5%
0R75
COMMON
5%
0
COMMON
5%
12V
5.5A
16MIL
12V_EXT Power Supply Filter
12V_EXT_F = 12V @ 6.25A
12V_EXT
C503
10UF
16V
10%
X5R
1206
COMMON
GND
DC_RESISTANCE=8.4mR
1 UH
L12
NO STUFF
7_6X7_6
MAX_CURRENT=10.2A
0
R78
COMMON
0805
5%
0R71
COMMON
0805
5%
0
R74
COMMON
0805
5%
0
R76
COMMON
0805
5%
12V
6.25A
16MIL
12V_F
GND
12V_EXT_F
GND
C506
10UF
16V
10%
X5R
1206
COMMON
C70
10UF
16V
10%
X5R
1206
COMMON
29-07022H-6-T-R
MALE
4.2MM
PCIEPWR
COMMON
5%
5%
5%
0
NO STUFF
0
NO STUFF
0
NO STUFF
12V_EXT_F
12V_F
R72
0805
R69
0805
R68
0805
3V3
R501
10K
5%
J9
90
6
3
12V_EXT_PRSNT*
5
2
4
1
C502
10UF
16V
10%
X5R
1206
COMMON
GNDGND
12V_EXT
GND
C501
.1UF
16V
10%
X7R
0603
COMMON
0402
NO STUFF
R502
0402
1G1D1S
12V_EXT_PRSNT_R
1K
NO STUFF
5%
1
C504
.01UF
16V
10%
X7R
0402
NO STUFF
GND
12V_EXT_PRSNT_EN
3
Q501
2N7002
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.115A
R_DS_ON=7.5R
MAX_CURRENT=0.8A
MAX_WATTAGE=0.2W
V_BE_GS=20V
GND
29<
PS I: 3V3, 12V, and 12V_EXT Power Supply Filter
www.vinafix.vn
EMERENCY MODE
(12V_EXT present)
150W POWER MODE
(12V_EXT NOT present)
GPIO12
0
1
600-10547-0011-000 A
design
rachen
26 OF 32
07-AUG-2008
Page 27
Page27: PS II: IFP_PLLVDD, 2V5, 5V, and DDC_5V Power Supply
OUT
ADJ
GND
INENOUT
ADJ
GND
IN
EN
POLYSWITCH
VOUT
NC
ADJPGOOD
THERMGND
VDD
VIN
EN
GND
OUT
TAB
GND/ADJ
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
2V5 Power Supply
3V3
GND
PS_2V5_VDD
C24C25
6.3V
10%
X5R
0402
COMMON
12MIL
SNN_2V5_PGOOD
U3
UP7706A
SOP8
COMMON
3
4
2
1
8
6
5 SNN_2V5_NC
7
9
GND
Vout=Vref*(1+Rt/Rb)
2.52=0.8*(1+22.6/10.5)
PS_2V5_ADJ
12MIL
C32
1000PF
16V
10%
X7R
0402
COMMON
2.5V
1A
R39
22.6K
1%
0402
COMMON
R37
10.5K
GND
1%
0402
COMMON
GND
C31
10UF
10V
10%
X5R
0805
COMMON
16MIL
2V5
C29
C30
.1UF
10UF
10V
10V
10%
10%
X5R
X5R
0402
0805
COMMON
COMMON
GND
GND
3V3
GND
2V5
R42
0
5%
0402
NO STUFF
PS_1V1_EN_IN
C35
1UF
16V
10%
X5R
0603
NO STUFF
R41
0
5%
0402
NO STUFF
Vref=0.8V
Vo_Typ=0.8*(1+1/2.61)=1.106V
1
3
U4
UP7707
ADJ_VR=0.8V
SOT23-5
SOT23-5
NO STUFF
2
GND
5
4
PS_1V1_ADJ
C38
.1UF
6.3V
10%
X7R
0402
NO STUFF
Rt
Rb
1.1V
20MIL
0.2A
GND
1V1_PLL
R43
1K
1%
0402
NO STUFF
R44
2.61K
1%
0402
NO STUFF
GND
C36
10UF
10V
10%
X5R
0805
NO STUFF
10UF 1UF
12V
R30
1.2K
5%
0402
COMMON
R32
1K
5%
0402
COMMON
GND
5V
R29
0
5%
0402
NO STUFF
10V
10%
X5R
0805
COMMON
GND
C27
.1UF
10V
10%
X5R
0402
COMMON
GND
IFP_PLLVDD Power Supply
IFP_PLLVDD = 1.8V @ 200mA
3V3
R36
0
5%
0402
5V and DDC_5V Power Supply
DDC_5V = 5V @ 200mA
ADD MIN 200MM^2 COPPER AROUND THIS DPAK FOR HEAT DISSIPATIONLAYOUT NOTE:
U1
APL1117UC
C22
.1UF
16V
10%
X7R
0603
COMMON
ADJ_VR=1.25V
GOI,IGOI,TO263
SOT223_GOI
COMMON
3
2
4
1
C16
4.7UF
6.3V
10%
X5R
0603
COMMON
PS_5V_ADJ
R24
124
1%
Rt
0402
COMMON
R23
383
1%
Rb
0402
COMMON
GND
C18
.1UF
10V
10%
X5R
0402
COMMON
GND
Vref=1.256V
Vo_Typ=1.256*(1+383/124)+60uA*383=5.16V
12V
GND
C21
4.7UF
16V
10%
X7R
1206
COMMON
5V
C17
4.7UF
6.3V
10%
X5R
0603
COMMON
0.2A
F502
200mA
1206
COMMON
5V5V
0.2A
16MIL
2116MIL
DDC_5V
GND
C877
220PF
50V
5%
C0G
0603
COMMON
COMMON
PS_1V8_EN_IN
GND
2V5
R35
0
5%
0402
NO STUFF
C28
1UF
16V
10%
X5R
0603
COMMON
Vref=0.8V
Vo_Typ=0.8*(1+1/0.806)=1.793V
1
3
U2
UP7707
ADJ_VR=0.8V
SOT23-5
SOT23-5
COMMON
2
GND
5
4
PS_1V8_ADJ
FBVDDQ
C26
.1UF
6.3V
10%
X7R
0402
COMMON
R28
0
5%
0402
NO STUFF
Rt
Rb
1.8V
20MIL
0.2A
GND
IFP_PLLVDD
R31
1K
1%
0402
COMMON
R33 COMMON
806
1%
0402
COMMON
C23
10UF
10V
10%
X5R
0805
GND
www.vinafix.vn
PS II: IFP_PLLVDD, 2V5, 5V, and DDC_5V Power Supply
600-10547-0011-000 A
design
rachen
27 OF 32
07-AUG-2008
Page 28
Page28: PS III: FBVDDQ Power Supply
INININININININININININININININININ
IN
S
D
G
S
D
G
S
D
G
S
D
G
UGATE
VCC12
PVCC5
BOOT
PHASE
LGATE
SW_FB
COMP
LDO_FB
FS_DIS
LDO_DR
VCC5
GND
PGND
IN
S
D
G
S
DGC
E
B
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
MIN_LINE_WIDTHNET
FBVDDQ
PEX_VDD
FBVDDQ
PS_FB_BOOT
PS_FB_UGATE
PS_FB_UGATE_R
PS_FB_PHASE
PS_FB_LGATE
PS_FB_COMP
PS_FB_FB
PS_FB_RC
PS_FB_RBOT
PS_FB_SNUB
FBVDDQ_SENSE_R
PEX_VDD
PS_FB_PVCC5
PS_FB_VCC5
PS_1V1_DR
PS_1V1_FB
PS_1V1_CP
PS_FBVDDQ_FS
20MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
20MIL
16MIL
16MIL
12MIL
12MIL
16MIL
16MIL
1.1V
NV_NET_MAX_CURRENTVOLTAGE
16A2.1V
16A
2A
12V_F
1G2D1S
1
1G2D1S
1
C512
1000PF
16V
10%
X7R
0402
NO STUFF
R545
10K
5%
0402
NO STUFF
R546
0402
12V_F
4
2
Q12
NTD4863NT4G
COMBI_MONO_1G2D1S
COMMON
3
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=11.3A@25C
R_DS_ON=9.3m@10V
MAX_CURRENT=98A
MAX_WATTAGE=1.95W@25C
V_BE_GS=+/-20V
4
2
Q9
NTD4855NT4G
COMBI_MONO_1G2D1S
COMMON
3
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=18A@25C
R_DS_ON=0.0035R@10V
MAX_CURRENT=197A
MAX_WATTAGE=2.24W@25C
V_BE_GS=+/-20V
GND
10K
NO STUFF
5%
2.2
R526
0603
5%
COMMON
FBVDDQ
10
C58
.47UF
16V
10%
X5R
0603
COMMON
4
2
1G2D1S
Q4
APM3055L
COMBI_MONO_1G2D1S
CHANGED
MAX_VOLTAGE=30V
C50
10UF
10V
10%
X5R
0805
COMMON
CONTINUOUS_CURRENT=12A
R_DS_ON=0.100R
MAX_CURRENT=30A
MAX_WATTAGE=50W@25C
V_BE_GS=20V
C49
4.7UF
6.3V
10%
X5R
0603
COMMON
PEX_VDD
C48
22UF
6.3V
20%
X5R
1206
NO STUFF
C53
10UF
10V
10%
X5R
0805
COMMON
GND
1
3
R64
1.05K
1%
0402
COMMON
R63
2.61K
1%
0402
COMMON
PS_1V1_CP
Vout = Vref * (1+Rtop/Rbot)
10UF
16V
10%
X5R
1206
COMMON
GND
R537
200
5%
0402
COMMON
C537
1000PF
16V
10%
X7R
0402
COMMON
10UF
16V
10%
X5R
1206
COMMON
C527
1UF
16V
10%
X5R
0603
COMMON
GND
PS_1V1_DR
PS_1V1_FB
PS_FBVDDQ_FS
R538
97.6K
1%
0402
CHANGED
C60
C55
1.12V = 0.8V * (1+1.05k/2.61k)PEXVDD Power Supply
PEXVDD = 1.1V @ 3A
GND
R533
PS_FB_VCC5
U502
UP6161NSAC
VR_SW=0.8V
SO14
SO14
COMMON
9
5
6
2
12
7
80.6K ~400KHz
97.6K ~300KHz
GND
0402
COMMON
5%
PS_FB_RC_CP
PS_FB_PVCC5
8
10
1
14
13
11
4
3
GND
GND
PS_FB_BOOT
PS_FB_UGATE
PS_FB_LGATE
PS_FB_FB
PS_FB_COMP
C526
1UF
16V
10%
X5R
0603
COMMON
C528
1UF
16V
10%
X5R
0603
COMMON
C538
.22UF
6.3V
10%
X5R
0402
CHANGED
R539
4.99K
1%
0402
COMMON
PS_FB_VCC12
C536
330PF
50V
5%
C0G
0402
COMMON
R528
0402
PS_FB_UGATE_R
2.2
CHANGED
5%
C532
R505
0402
.1UF
16V0402
10%
X7R
COMMON
5%
10K
NO STUFF
GND
NVVDD
R548
10K
5%
0402
COMMON
1B1C1E
PS_FB_EN
R549
30K
5%
0402
COMMON
1
C541
.1UF
16V
10%
X7R
0402
COMMON
12V_F
3
Q509
MMBT2222A
SOT23_1B1C1E
COMMON
2
GND
R547
10K
5%
0402
COMMON
1G1D1S
1PS_FB_EN*
3
Q508
2N7002
SOT23_1G1D1S
COMMON
2
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.115A
R_DS_ON=7.5R
MAX_CURRENT=0.8A
MAX_WATTAGE=0.2W
V_BE_GS=20V
GND
21>
GPIO7_FBVDDQ_SEL
GPIO7
FBVDDQ = 1.816V
FBVDDQ = 1.997V
0
1
PS III: FBVDDQ Power Supply
www.vinafix.vn
3V3
Irms = 5.3A @ 1.8V/15A
C505
C66
10UF
10UF
16V
16V
10%
10%
X5R
X5R
12061206
COMMON
COMMON
.47UF
C68
0603
PS_FB_PHASE
PS_FB_VSEL
1G2D1S
GND
16V
10%
X5R
COMMON
1
1G1D1S
C540
1000PF
16V
10%
X7R
0402
NO STUFF
1
R544
5.62K
NO STUFF
GND
4
2
Q10
NTD4855NT4G
COMBI_MONO_1G2D1S
NO STUFF
3
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=18A@25C
R_DS_ON=0.0035R@10V
MAX_CURRENT=197A
MAX_WATTAGE=2.24W@25C
V_BE_GS=+/-20V
GND
Rbot1
1%
0402
PS_FB_RBOT
3
Q510
BSS138
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
1
2
D11
RSX201L-30
SMA
30V
2A
NO STUFF
GND
C59
2200PF
50V
10%
X5R
0603
COMMON
PS_FB_SNUB
R66
1
5%
1206
COMMON
R536
1K
1%
0402
COMMON
GND
C76
270UF
COMMON
20%
16V
FPCAP
5A@105C
0.008R
TH_D80P35
FBVDDQ Power Supply
GND
ALTERNATES
1.5 UH
L10
NO STUFF
SMD_12X5
1.2UH
L9
COMMON
TH
210
R540
COMMON
0402
1%
R542
0402
Rtop
Rbot
FBVDDQ = VREF * (1 + (Rtop / Rbot1))
2.06V = 0.8V * (1 + (1.58K/ 1K))
FBVDDQ = 1.8 - 2.0 V@ 10A
DC_RESISTANCE=3mOhm
MAX_CURRENT=18.5A
CONTINUOUS_CURRENT=14.4A
DC_RESISTANCE=0.0024R
MAX_CURRENT=40A
CONTINUOUS_CURRENT=29A
C509
10UF
10V
10%
X5R
0805
NO STUFF
GND
1.58K
CHANGED
C539
0402
PS_FB_RC
1%
C64
C508
10UF
10V
10%
X5R
0805
NO STUFF
1200UF
COMMON
20%
4V
FPCAP
6.1A@105C
0.007R
COMBI_TH_D80_D100
GND
.047UF
16V
10%
X7R
CHANGED
FBVDDQ_SENSE_R
600-10547-0011-000 A
design
rachen
R541
0402
R543
OPTIONAL
0402
5%
5%
0
COMMON
0
NO STUFF
C57
1200UF
COMMON
20%
4V
FPCAP
6.1A@105C
0.007R
COMBI_TH_D80_D100
FBVDDQ_SENSE
FBVDDQ
28 OF 32
07-AUG-2008
4>
Page 29
Page29: PS IV: NVVDD
INININININININININININININININININININININININININ
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
IN
IN
S
D
G
IN
2 PHASE PWM
VCC12
LGATE1
PHASE1
UGATE1
BOOT1
BOOT2
PHASE2
LGATE2
UGATE2
IMAX
NC
VCC9
PVCC9
FB
COMP
MODE
RT
SS
AGND
REFIN
NC
NC
PGND1
PGND2
PGND3
S
DGC
E
B
C
E
B
IN
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
12V_EXT_F
Irms = 10A @ 1.10V/50A/Two phase
.47UF
MIN_LINE_WIDTH
30MIL
NVVDD
NVVDD
MAX_CURRENTNETNAME
50A
PS_NVVDD_RC_CP
.01UF
C523
16V
0402
10%
X7R
CHANGED
C521 22PF
50V
0402
5%
C0G
CHANGED
GND
21>
3V3
R535
1K
5%
0402
NO STUFF
GPIO3_NVVDD_PHASE
R522
0402
1G1D1S
GND
5%
1
C530
.1UF
16V
10%
X7R
0402
NO STUFF
22K
CHANGED
PS1_NVVDD_SUS_R
3
R530
0402
5%
Q507
2N7002
SOT23_1G1D1S
COMMON
2
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.115A
R_DS_ON=7.5R
MAX_CURRENT=0.8A
MAX_WATTAGE=0.2W
V_BE_GS=20V
PS_NVVDD_CP
18K
NO STUFF
R531
18K
5%
0402
NO STUFF
GND
GND
300KHz Per Phase
NVVDD ENABLE
C511
.1UF
16V
10%
X7R
0402
COMMON
NVVDD_EN
R511
0402
12V_F
GND
25>
26>
12V_EXT_PRSNT_EN
3V3
R507
15K
5%
0402
COMMON
R508
10K
5%
0402
COMMON
GND
GND
GND
0
NO STUFF
5%
R504
12.7K
1%
0402
COMMON
PS_NVVDD_EN
R506
1K
1%
0402
COMMON
C524
1UF
16V
10%
X5R
0603
COMMON
R524
19.1K
1%
0402
COMMON
VOLTAGE
1.1V
PS_NVVDD_PVCC9
1B1C1E
1
1B1C1E
1
C510
.1UF
16V
10%
X7R
0402
COMMON
R519
0402
5%
C513
.047UF
16V
10%
X7R
0402
CHANGED
SS =6.58mS
3
Q504
MMBT2222A
SOT23_1B1C1E
COMMON
2
PS_NVVDD_EN_AND
3
Q502
MMBT2222A
SOT23_1B1C1E
COMMON
2
GND
2.2
COMMON
GND
PS_NVVDD_SUS
GND
PS_NVVDD_EN*
PS_NVVDD_VCC9
C522
1UF
16V
10%
X5R
0603
COMMON
PS_NVVDD_FB
PS1_NVVDD_FS
PS1_NVVDD_SS
PS1_NVVDD_VREF
C529
.1UF
16V
10%
X7R
0402
COMMON
GND
12V_EXT_F
R510
10K
5%
0402
COMMON
1G1D1S
12V_EXT_F
1
U501
UP6205
VID(0.8-1.6V)
QFN24
COMMON
21
22
10
11
7
9
14
6
5
2
17
25
3
Q503
2N7002
SOT23_1G1D1S
COMMON
2
GND
2.2
R515
COMMON
0603
5%
1
12
SNN_NVVDD_NC2
SNN_NVVDD_NC1
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.115A
R_DS_ON=7.5R
MAX_CURRENT=0.8A
MAX_WATTAGE=0.2W
V_BE_GS=20V
GND
13SNN_NVVDD_NC3
C520
1UF
16V
10%
X5R
0603
COMMON
PS_NVVDD_VCC
20
PS_NVVDD_DRVH1
3
PS_NVVDD_BOOT1
4
PS_NVVDD_PH124
PS_NVVDD_DRVL1
23
PS_NVVDD_DRVH2
16
PS_NVVDD_BOOT2
15
PS_NVVDD_PH2
18
19
8
PS_NVVDD_OC
R525
90.9K
1%
0402
CHANGED
GND
Imax total= 93A
2.2
CHANGED
5%
R532
0402
PS_NVVDD_DRVL2
21>
21>
4
PS_NVVDD_DRVH1_R
.1UFC531
16V0603
10%
X7R
COMMON
R529
10K
5%
0402
NO STUFF
1G2D1S
1G2D1S
C533
1000PF
16V
10%
X7R
0402
NO STUFF
1
1
2
Q7
NTD4863NT4G
COMBI_MONO_1G2D1S
NO STUFF
3
4
2
Q6
NTD4855NT4G
COMBI_MONO_1G2D1S
COMMON
3
GND
12V_EXT_F
PS_NVVDD_DRVH2_R
C514
0603
R509
5%
2.2
.1UF
16V
10%
X7R
COMMON
0402
CHANGED
R503
10K
5%
0402
NO STUFF
1G2D1S
1G2D1S
1
1
C507
1000PF
16V
10%
X7R
0402
NO STUFF
4
2
Q11
NTD4863NT4G
COMBI_MONO_1G2D1S
NO STUFF
3
4
2
Q14
NTD4855NT4G
COMBI_MONO_1G2D1S
COMMON
3
GND
3V3
R534
10K
5%
0402
NO STUFF
GPIO5_VSEL0
GPIO6_VSEL1
R523
10K
5%
0402
NO STUFF
R527
0402
R520
0402
5%
5%
10K
NO STUFF
10K
NO STUFF
GND
PS IV: NVVDDV
www.vinafix.vn
C62
0603
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=11.3A@25C
R_DS_ON=9.3m@10V
MAX_CURRENT=98A
MAX_WATTAGE=1.95W@25C
V_BE_GS=+/-20V
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=18A@25C
R_DS_ON=0.0035R@10V
MAX_CURRENT=197A
MAX_WATTAGE=2.24W@25C
V_BE_GS=+/-20V
C72
0603
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=11.3A@25C
R_DS_ON=9.3m@10V
MAX_CURRENT=98A
MAX_WATTAGE=1.95W@25C
V_BE_GS=+/-20V
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=18A@25C
R_DS_ON=0.0035R@10V
MAX_CURRENT=197A
MAX_WATTAGE=2.24W@25C
V_BE_GS=+/-20V
NVVDD_VSEL0
NVVDD_VSEL1
16V
10%
X5R
COMMON
.47UF
16V
10%
X5R
COMMON
GND
GND
1G2D1S
1G2D1S
1G2D1S
1G1D1S
C525
1000PF
16V
10%
X7R
0402
NO STUFF
1G1D1S
C518
1000PF
16V
10%
X7R
0402
NO STUFF
1
1G2D1S
1
1
1
1
4
2
Q8
NTD4860NT4G
COMBI_MONO_1G2D1S
CHANGED
3
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=13A@25C
R_DS_ON=0.0075R@10V
MAX_CURRENT=130A
MAX_WATTAGE=1.28W@25C
V_BE_GS=+/-20V
1
GND
4
2
Q15
NTD4860NT4G
COMBI_MONO_1G2D1S
CHANGED
3
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=13A@25C
R_DS_ON=0.0075R@10V
MAX_CURRENT=130A
MAX_WATTAGE=1.28W@25C
V_BE_GS=+/-20V
4
2
Q13
NTD4855NT4G
COMBI_MONO_1G2D1S
COMMON
3
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=18A@25C
R_DS_ON=0.0035R@10V
MAX_CURRENT=197A
MAX_WATTAGE=2.24W@25C
V_BE_GS=+/-20V
GND
NVVDD_RBOT1
3
Q506
2N7002
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.115A
R_DS_ON=7.5R
MAX_CURRENT=0.8A
MAX_WATTAGE=0.2W
V_BE_GS=20V
GND
3
Q505
2N7002
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.115A
R_DS_ON=7.5R
MAX_CURRENT=0.8A
MAX_WATTAGE=0.2W
V_BE_GS=20V
GND
GND
4
2
Q5
NTD4855NT4G
COMBI_MONO_1G2D1S
COMMON
3
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=18A@25C
R_DS_ON=0.0035R@10V
MAX_CURRENT=197A
MAX_WATTAGE=2.24W@25C
V_BE_GS=+/-20V
GND
R521
8.25K
1%
0402
NO STUFF
1
2
GND
1
2
GND
Rbot2Rbot1
C63
10UF
16V
10%
X5R
1206
COMMON
C517
10UF
10%
X5R
1206
COMMON
D10
RSX201L-30
SMA
30V
2A
NO STUFF
D12
RSX201L-30
SMA
30V
2A
NO STUFF
C74
270UF
COMMON
20%
16V
FPCAP
5A@105C
0.008R
TH_D80P35
GND
C71
10UF
16V16V
10%
X5R
1206
COMMON
R518
12.7K
1%
0402
NO STUFF
NVVDD_RBOT2
GND
GND
DC_RESISTANCE=0.0017R
MAX_CURRENT=36A
CONTINUOUS_CURRENT=31A
C54
1
2200PF
50V
10%
2
X5R
0603
COMMON
PS_NVVDD_RC1
R65
2.2
5%
1206
COMMON
C67
2200PF
50V
10%
X5R
0603
COMMON
PS_NVVDD_RC2
R67
2.2
5%
1206
COMMON
GND
PS_NVVDD_VCC9
PS_NVVDD_BOOT1
PS_NVVDD_SUS
PS_NVVDD_DRVH1
PS_NVVDD_DRVH1_R
PS_NVVDD_PH1
PS_NVVDD_DRVL1
PS_NVVDD_CP
PS_NVVDD_RC_CP
PS_NVVDD_FB
PS1_NVVDD_FS
PS1_NVVDD_SS
PS1_NVVDD_VREF
C75
270UF
COMMON
20%
16V
FPCAP
5A@105C
0.008R
TH_D80P35
R517
1.18K
1%
Rbot
0402
CHANGED
GND
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
0.47uH
L6
NO STUFFSMD_520X508
1.0UH
L5
COMMON
TH
ALTERNATES
DC_RESISTANCE=0.0017R
MAX_CURRENT=40A
CONTINUOUS_CURRENT=30A
25A
C56
820UF
COMMON
20%
2.5V
NPCAP
6.1A@105C
0.007R
TH_D80P35
C61
820UF
COMMON
20%
2.5V
NPCAP
6.1A@105C
0.007R
TH_D80P35
GND
NVVDD Power Supply
NVVDD = 1.0-1.10V @ 50A
DC_RESISTANCE=0.0017R
R516
0402
PS_NVVDD_RC
Rtop
MAX_CURRENT=36A
CONTINUOUS_CURRENT=31A
DC_RESISTANCE=0.0017R
MAX_CURRENT=40A
CONTINUOUS_CURRENT=30A
C69
820UF
COMMON
20%
2.5V
NPCAP
6.1A@105C
0.007R
TH_D80P35
GND
PS_NVVDD_VSEN
1.13K
CHANGED
1%
GPIO6
00
01
11
C65
820UF
COMMON
20%
2.5V
NPCAP
6.1A@105C
0.007R
TH_D80P35
GND
10.2
R514
COMMON
0402
1%
NVVDD
1.1745V (DEFAULT)
0.47uH
L8
NO STUFFSMD_520X508
1.0UH
L7
COMMONTH
ALTERNATES
.01UF
C519
16V
0402
10%
X7R
COMMON
NVVDD = 0.6 * (1 + Rtop/Rbot)
1.1745V = 0.6 * (1 + 1.13K/1.18K)
GPIO5
16MILPS_NVVDD_PVCC9
PS_NVVDD_VCC
PS_NVVDD_RC1
PS_NVVDD_BOOT2
PS_NVVDD_DRVH2
PS_NVVDD_DRVH2_R
PS_NVVDD_PH2
PS_NVVDD_DRVL2
PS_NVVDD_RC2
PS_NVVDD_VSEN
PS_NVVDD_RC
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
NVVDD
C535
C516
10UF
10V
10%
X5R
0805
NO STUFF
GND
10UF
10V
10%
X5R
0805
NO STUFF
GND
C515
10UF
10V
10%
X5R
0805
NO STUFF
GND
C51
10UF
10V
10%
X5R
0805
COMMON
10UF
10V
10%
X5R
0805
NO STUFF
10UF
10V
10%
X5R
0805
COMMON
C52
C534
GNDGND
100
R512
CHANGED
0402
5%
NVVDD_SENSE_GPU
0
R513
COMMON
0402
5%
OPTIONAL
600-10547-0011-000 A
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25A
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DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
BLANK
BLANK
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600-10547-0011-000 A
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07-AUG-2008
Page 31
Page31: Fan Connector
OUT
IN
S
D
G
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
GPIO9_FAN_PWM
GPIO4_FAN_TACH
3V3
D8
BAT54C
25V
200MA
SOT23
COMMON
3V3
R15
R14
10K
10K
5%
0402
COMMON
5%
0402
COMMON
1G1D1S
C11
.01UF
16V
10%
X7R
0402
NO STUFF
1
12V
C855
.47UF
16V
10%
X5R
0603
COMMON
GND
3
D1
BAT54C
25V
200MA
SOT23
21
NO STUFF
3
Q1
BSS138
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
3V3
3
21
1
2
3
4
GND
GPIO9_FAN_ON
FAN
21>
21>
J7
HDR_1M4
MALE
2.0MM
N/A
NORM
COMMON
GND
R7
0
5%
0402
NO STUFF
1
J6
HDR_1M2_FAN
2
MALE
2.5MM
0
NORM
NO STUFF
GND
Fan Connector
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600-10547-0011-000 A
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07-AUG-2008
Page 32
Page32: Thermal, Mechanical, and Bracket
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
12 connected mounting pins
COOLING SOLUTION
No connected mounting pins
SPECIAL MECHANIC
2 connected mounting pins
BOARD STIFFENER
MECH. MOUNTING TOP
Thermal
123456789
101112
GND
MEC8
TM62_DT_HFP1_BOM
12PIN
NO STUFF
Mechanical Bracket
BKT1
DVI3152_DVI1552_TEXT_1_2_TAB
ATX_1X_TOP
CHANGED
1
GND
MEC7
9000_SINGLE
2PIN
NO STUFF
1
2
MEC5
PH_4_40X.1875_SCREW
STD
COMMON
MEC1
HEX_JACK_SCREW
STD
COMMON
MEC2
HEX_JACK_SCREW
STD
COMMON
MEC3
HEX_JACK_SCREW
STD
COMMON
MEC4
HEX_JACK_SCREW
STD
COMMON
GND
MEC6
PEX_RET_BRKOFF
NOPIN
NO STUFF
Thermal, Mechanical, and Bracket
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