MSI MS-V159 Schematic 1.0

8

+12V_BUS

C1

CAP CER 10UF 20% 16V X5R

10UFC110UF

(1206)1.8MM H MAX

+12V_BUS+12V_BUS

C3

D D

C C

B B

C2

150nF_16VC3150nF_16V

150nF_16VC2150nF_16V

+3.3V_BUS

CAP CER 10UF 10% 6.3V X6S
(0805)1.4MM MAX THICK

C5
10uF_X6SC510uF_X6S

+3.3V_BUS

C7
1uF_6.3VC71uF_6.3V

C8
10nFC810nF

C6
100nF_6.3VC6100nF_6.3V

Place these caps as close to the PCIE
connector as possible

7

+3.3V

GPIO_4_SMBCLK(6)

GPIO_3_SMBDATA(6)

DNIDNI

TEST_EN_J TEST_EN_J

R10RR1

0R

PETp10_GFXRp10(2)
PETn10_GFXRn10(2)

PETp11_GFXRp11(2)
PETn11_GFXRn11(2)

PETp12_GFXRp12(2)
PETn12_GFXRn12(2)

PETp13_GFXRp13(2)
PETn13_GFXRn13(2)

PETp14_GFXRp14(2)
PETn14_GFXRn14(2)

PETp15_GFXRp15(2)
PETn15_GFXRn15(2)

PETn0_GFXRn0(2)

PETp1_GFXRp1(2)
PETn1_GFXRn1(2)

PETp2_GFXRp2(2)
PETn2_GFXRn2(2)

PETp3_GFXRp3(2)
PETn3_GFXRn3(2)

PETp4_GFXRp4(2)
PETn4_GFXRn4(2)

PETp5_GFXRp5(2)
PETn5_GFXRn5(2)

PETp6_GFXRp6(2)
PETn6_GFXRn6(2)

PETp7_GFXRp7(2)
PETn7_GFXRn7(2)

PETp8_GFXRp8(2)
PETn8_GFXRn8(2)

PETp9_GFXRp9(2)
PETn9_GFXRn9(2)

+3.3V_BUS

6

DNI , To Bypass U12

+3.3V_BUS

JTRST

PRESENCE

5

PCI-EXPRESS EDGE CONNECTOR

+12V_BUS

SMCLK
SMDAT

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

+3.3V

+12V#B1
+12V#B2
+12V#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1

3.3Vaux
WAKE#

RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82

x16 PCIe

x16 PCIe

Mechanical Key

Mechanical Key

MPCIE1

MPCIE1

PRSNT1#A1

+12V#A2
+12V#A3
GND#A4

JTAG2
JTAG3
JTAG4
JTAG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12
REFCLK+
REFCLK­GND#A15

PERp0
PERn0

GND#A18

RSVD#A19

GND#A20

PERp1

PERn1
GND#A23
GND#A24

PERp2

PERn2
GND#A27
GND#A28

PERp3

PERn3
GND#A31

RSVD#A32
RSVD#A33

GND#A34

PERp4

PERn4
GND#A37
GND#A38

PERp5

PERn5
GND#A41
GND#A42

PERp6

PERn6
GND#A45
GND#A46

PERp7

PERn7
GND#A49

RSVD#A50

GND#A51

PERp8

PERn8
GND#A54
GND#A55

PERp9

PERn9
GND#A58
GND#A59

PERp10

PERn10
GND#A62
GND#A63

PERp11

PERn11
GND#A66
GND#A67

PERp12

PERn12
GND#A70
GND#A71

PERp13

PERn13
GND#A74
GND#A75

PERp14

PERn14
GND#A78
GND#A79

PERp15

PERn15
GND#A82

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

4

PRESENCE

JTDI

+12V_BUS

+3.3V_BUS

PERp0
PERn0

PERp1
PERn1

PERp2
PERn2

PERp3
PERn3

PERp4
PERn4

PERp5
PERn5

PERp6
PERn6

PERp7
PERn7

PERp8
PERn8

PERp9
PERn9

PERp10
PERn10

PERp11
PERn11

PERp12
PERn12

PERp13
PERn13

PERp14
PERn14

PERp15
PERn15

JTCK
JTDO

JTMS

PERST#

JTRST

No JTAG

R2 0RR2 0R

3

JTAG_MODE
JTAG_TRSTB
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

PCIE_REFCLKP (2)
PCIE_REFCLKN (2)PETp0_GFXRp0(2)

PERp0 (2)
PERn0 (2)

PERp1 (2)
PERn1 (2)

PERp2 (2)
PERn2 (2)

PERp3 (2)
PERn3 (2)

PERp4 (2)
PERn4 (2)

PERp5 (2)
PERn5 (2)

PERp6 (2)
PERn6 (2)

PERp7 (2)
PERn7 (2)

PERp8 (2)
PERn8 (2)

PERp9 (2)
PERn9 (2)

PERp10 (2)
PERn10 (2)

PERp11 (2)
PERn11 (2)

PERp12 (2)
PERn12 (2)

PERp13 (2)
PERn13 (2)

PERp14 (2)
PERn14 (2)

PERp15 (2)
PERn15 (2)

TP4

TP4
35mil

35mil

TP1

TP1

TP32

TP32

TP2

TP2

TP5

TP5

TP3

TP3

35mil

35mil

35mil

35mil

35mil

35mil

35mil

35mil

35mil

35mil

PWR_GOOD(6,14,15,16)

Table 1: Connection for JTAG

Production
(No JTAG)

Internal Use Only

2

U1A

R21 1KR21 1K

JTAG_TMS (17)
JTAG_TDO (17)

JTAG_TCK (17)

JTAG_MODE (17)

JTAG_TDI (17)

MR9 1KMR9 1K

U1A

AD28

TESTEN

AM23

JTAG_TRSTB

AK23

JTAG_TCK

AN23

JTAG_TDI

AM24

JTAG_TDO

AL24

JTAG_TMS

RV730XT A12 HF MVE SLT B1

RV730XT A12 HF MVE SLT B1

Share one pad

Install R1, R2 & Don't Install TSW1

Install TSW1 & Don't Install R1 & R2

TSW1 Switch #1, 2, 3, 4, 5 and 6 closed (ON)

JTAG

#8 and 7 open

TSW1 Switch #1, 2, 3, 4, 5 and 6 open

NO JTAG

#8 & 7 closed (ON)

PART 1 OF 15

PART 1 OF 15

1
2

53

R_RST

1

J

J
T

T
A

A
G

G

+3.3V+3.3V_BUS

MR100RMR10
0R

Share one pad

NC7SZ08P5X_NL

NC7SZ08P5X_NL

4

U11

U11

DNI

Place R3 in U5

C4
100nF_6.3VC4100nF_6.3V

PERST#_buf (2,16)

TSW1, R1 & R2 are located on the bottom side of the board close to PCIE connector.

SYMBOL LEGEND

DO NOT

DNI

INSTALL

#

ACTIVE
LOW

DIGITAL
GROUND

ANALOG

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

8

7

6

5

4

3

Title

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Sheet

Sheet

Sheet

of

119

of

119

of

119

GROUND

BUO BRING UP

ONLY

Doc No.

Doc No.

Doc No.

105-B709xx-11

105-B709xx-11

105-B709xx-11

1

RevDate:

RevDate:

RevDate:

50

50

50

www.vinafix.vn

5

4

3

2

1

(2) RV730 PCIE Interface

NOTE: some of the PCIE testpoints will
be available trought via on traces.

PETp0_GFXRp0(1)
PETn0_GFXRn0(1)

PETp1_GFXRp1(1)
PETn1_GFXRn1(1)

D D

C C

+1.8V

+1.8V

+1.1V

B B

PETp2_GFXRp2(1)
PETn2_GFXRn2(1)

PETp3_GFXRp3(1)
PETn3_GFXRn3(1)

PETp4_GFXRp4(1)
PETn4_GFXRn4(1)

PETp5_GFXRp5(1)
PETn5_GFXRn5(1)

PETp6_GFXRp6(1)
PETn6_GFXRn6(1)

PETp7_GFXRp7(1)
PETn7_GFXRn7(1)

PETp8_GFXRp8(1)
PETn8_GFXRn8(1)

PETp9_GFXRp9(1)
PETn9_GFXRn9(1)

PETp10_GFXRp10(1)
PETn10_GFXRn10(1)

PETp11_GFXRp11(1)
PETn11_GFXRn11(1)

PETp12_GFXRp12(1)
PETn12_GFXRn12(1)

PETp13_GFXRp13(1)
PETn13_GFXRn13(1)

PETp14_GFXRp14(1)
PETn14_GFXRn14(1)

PETp15_GFXRp15(1)
PETn15_GFXRn15(1)

B22 BLM15BD121SN1B22 BLM15BD121SN1

B23 26R_600mAB23 26R_600mA

B21 220R_2AB21 220R_2A

+PCIE_PVDD

+PCIE_VDDR

+PCIE_VDDC

1uF_6.3V

1uF_6.3V

4.7uF_6.3V

4.7uF_6.3V

C101

C101

C94

C94

10uF_X6S

10uF_X6S

C98

C98

1uF_6.3V

1uF_6.3V

C95

C95

1uF_6.3V

1uF_6.3V

C90

C90

1uF_6.3V

1uF_6.3V

C51

C51

10uF_X6S

10uF_X6S

C86

C86

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

TP6TP6

TP13TP13

TP14TP14

TP7TP7

TP15TP15

TP8TP8

TP9TP9

TP16TP16

TP17TP17

TP10TP10

TP11TP11

TP18TP18

TP19TP19

TP12TP12

TP20TP20

TP21TP21

TP22TP22

TP23TP23

TP24TP24

TP25TP25

TP26TP26

TP27TP27

PCIE_REFCLKP(1)
PCIE_REFCLKN(1)

PERST#_buf(1,16)

C87

C87

C85

C85

C84

C100

C100

C92

C92

C89

C89

10nF

10nF

C97

C97

100nF_6.3V

100nF_6.3V

C93

C93

1uF_6.3V

1uF_6.3V

C84

100nF_6.3V

100nF_6.3V

C99

C99

100nF_6.3V

100nF_6.3V

C96

C96

C91

C91

1uF_6.3V

1uF_6.3V

C88

C88

1uF_6.3V

1uF_6.3V

U1B

U1B

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AA30

PERSTB

AB37

PCIE_PVDD

AA31

PCIE_VDDR#1

AA32

PCIE_VDDR#2

AA33

PCIE_VDDR#3

AA34

PCIE_VDDR#4

V28

PCIE_VDDR#5

W29

PCIE_VDDR#6

W30

PCIE_VDDR#7

Y31

PCIE_VDDR#8

G30

PCIE_VDDC#1

G31

PCIE_VDDC#2

H29

PCIE_VDDC#3

H30

PCIE_VDDC#4

J29

PCIE_VDDC#5

J30

PCIE_VDDC#6

L28

PCIE_VDDC#7

M28

PCIE_VDDC#8

N28

PCIE_VDDC#9

R28

PCIE_VDDC#10

T28

PCIE_VDDC#11

U28

PCIE_VDDC#12

RV730XT A12 HF MVE SLT B1

RV730XT A12 HF MVE SLT B1

PART 2 OF 15

PART 2 OF 15

P

P
C

C
I

I
E

E
X

X
P

P
R

R
E

E
S

S
S

S

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

PCIE_CALRP
PCIE_CALRN

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8

PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

Y33
Y32

W33
W32

U33
U32

U30
U29

T33
T32

T30
T29

P33
P32

P30
P29

N33
N32

N30
N29

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

Y30
Y29

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

PCIE_CALRP
PCIE_CALRN

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C11

C11

100nF_6.3V

100nF_6.3V

C13

C13

R221.27K R221.27K

R242.0K R242.0K

C12

C12

C14

C14
100nF_6.3V

100nF_6.3V

C15

C15

C16

C16
100nF_6.3V

100nF_6.3V

C17

C17

C18

C18
100nF_6.3V

100nF_6.3V

C19

C19

C20

C20
100nF_6.3V

100nF_6.3V

C21

C21

C22

C22
100nF_6.3V

100nF_6.3V

C23

C23

C24

C24
100nF_6.3V

100nF_6.3V

C25

C25

C26

C26
100nF_6.3V

100nF_6.3V

C27

C27

C28

C28
100nF_6.3V

100nF_6.3V

C29

C29

C30

C30
100nF_6.3V

100nF_6.3V

C31

C31

C32

C32
100nF_6.3V

100nF_6.3V

C33

C33

C34

C34
100nF_6.3V

100nF_6.3V

C35

C35

C36

C36
100nF_6.3V

100nF_6.3V

C37

C37

C38

C38
100nF_6.3V

100nF_6.3V

C39

C39

C40

C40
100nF_6.3V

100nF_6.3V

C41

C41

C42

C42
100nF_6.3V

100nF_6.3V

+PCIE_VDDC

PERp0 (1)
PERn0 (1)

PERp1 (1)
PERn1 (1)

PERp2 (1)
PERn2 (1)

PERp3 (1)
PERn3 (1)

PERp4 (1)
PERn4 (1)

PERp5 (1)
PERn5 (1)

PERp6 (1)
PERn6 (1)

PERp7 (1)
PERn7 (1)

PERp8 (1)
PERn8 (1)

PERp9 (1)
PERn9 (1)

PERp10 (1)
PERn10 (1)

PERp11 (1)
PERn11 (1)

PERp12 (1)
PERn12 (1)

PERp13 (1)
PERn13 (1)

PERp14 (1)
PERn14 (1)

PERp15 (1)
PERn15 (1)

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

5

4

3

2

Title

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Sheet

Sheet

Sheet

of

219

of

219

of

219

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

50

50

50

105-B709xx-11

105-B709xx-11

105-B709xx-11

www.vinafix.vn

5

(3) RV730 MEM Interface Ch A&B

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10

D D

DQMA_0(4,5)
DQMA_1(4,5)
DQMA_2(4,5)
DQMA_3(4,5)

QSA_0(4,5)
QSA_1(4,5)
QSA_2(4,5)
QSA_3(4,5)

QSA_0b(4,5)
QSA_1b(4,5)
QSA_2b(4,5)
QSA_3b(4,5)

C C

MAA_[12..0](4,5)

B B

MAA_BA_[2..0](4,5)

DRAM_RST(4,5)

DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31

CKEA0(4,5)
CLKA0(4,5)

CLKA0b(4,5)

CSA0b_0(4)
CSA0b_1(5) CSB0b_1(5)CSA1b_1 (5) CSB1b_1 (5)

CASA0b(4,5)
RASA0b(4,5)
WEA0b(4,5)

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12

MAA_BA_0
MAA_BA_1
MAA_BA_2

C346

C346

1uF_6.3V

1uF_6.3V

R102

R102
10K

10K

AH11

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18

A32
C32
D23
E22

C34
D29
D25
E20

A34
E30
E26
C20

J21

K21
H27

G27

K24
K27

K20
K23
K26

G24

J23

H24

J24

H26

J26
H21
G21
H19
H20
L13
G16

J16
H23

J19

J17
H17
H16

U1C

U1C

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31

DQMA_0
DQMA_1
DQMA_2
DQMA_3

QSA_0
QSA_1
QSA_2
QSA_3

QSA_0B
QSA_1B
QSA_2B
QSA_3B

ODTA0

CKEA0
CLKA0

CLKA0B

CSA0B_0
CSA0B_1

CASA0B
RASA0B
WEA0B

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
NC_MAA_13
NC_MAA_14

MAA_BA0
MAA_BA1
MAA_BA2

DRAM_RST

RV730XT A12 HF MVE SLT B1

RV730XT A12 HF MVE SLT B1

DDR2

DDR2

Single or

Single or

PART 3 OF 15

PART 3 OF 15

Diff Strobes

Diff Strobes

DDR3

DDR3

M

M
E

E
M

M
O

O
R

R
Y

Y

I

I
N

N
T

T
E

E
R

R
F

F
A

A
C

C
E

E

Differential Strobes

Differential Strobes

B

B
A

A
N

N
K

K

A

A

DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

DQMA_4
DQMA_5
DQMA_6
DQMA_7

GDDR3

GDDR3

Read

Strobes

Read

Strobes

QSA_4B
QSA_5B
QSA_6B
QSA_7B

Write

Strobes

Write

Strobes

CLKA1B

CSA1B_0
CSA1B_1

CASA1B
RASA1B

NC_MEM_CALRP0
NC_MEM_CALRN0

MEM_CALRP1
NC_MEM_CALRN1
NC_MEM_CALRP2
NC_MEM_CALRN2

MVREFDA

MVREFSA

C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

C14
A14
E10
D9

E16

QSA_4

E12

QSA_5

J10

QSA_6

D7

QSA_7

C16
C12
J11
F8

G19

ODTA1

J20

CKEA1

J14

CLKA1

H14

M13
K16

K17
K19
L15

WEA1B

M27
L27
M12
N12
AH12
AG12

L18

MVREFD/S =0.7*
VDDR1
(GDDR3/4/5)

L20

DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8

DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MEM_CALRP0

MEM_CALRN0

MEM_CALRP1

MEM_CALRN1

MEM_CALRP2

MEM_CALRN2

MVREFD_A

MVREFS_A

4

3

U1D

DQA1_[31..0] (4,5)DQA0_[31..0](4,5) DQB0_[31..0](4,5) DQB1_[31..0] (4,5)

CKEA1 (4,5)
CLKA1 (4,5)

CLKA1b (4,5)

CSA1b_0 (4)

CASA1b (4,5)
RASA1b (4,5)

WEA1b (4,5)

R118 243RR118 243R

DNI

1uF_6.3V

1uF_6.3V

DNI

1uF_6.3V

1uF_6.3V

DQMA_4 (4,5)
DQMA_5 (4,5)
DQMA_6 (4,5)
DQMA_7 (4,5)

QSA_4 (4,5)
QSA_5 (4,5)
QSA_6 (4,5)
QSA_7 (4,5)

QSA_4b (4,5)
QSA_5b (4,5)
QSA_6b (4,5)
QSA_7b (4,5)

R122

R122

40.2R

40.2R
1%

R125

R125

C300

C300

100R

100R

1%

R126

R126

40.2R

40.2R

R128

R128

C305

C305

100R

100R

1%

+MVDD

+MVDD

+MVDD

DQMB_0(4,5)
DQMB_1(4,5)
DQMB_2(4,5)
DQMB_3(4,5)

QSB_0(4,5)
QSB_1(4,5)
QSB_2(4,5)
QSB_3(4,5)

QSB_0b(4,5)
QSB_1b(4,5)
QSB_2b(4,5)
QSB_3b(4,5)

MAB_[12..0](4,5)

MAB_BA_[2..0](4,5)

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31

CKEB0(4,5)
CLKB0(4,5)

CLKB0b(4,5)

CSB0b_0(4)

CASB0b(4,5)
RASB0b(4,5)
WEB0b(4,5)

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12

MAB_BA_0
MAB_BA_1
MAB_BA_2

U1D

C5

DQB_0

C3

DQB_1

E3

DQB_2

E1

DQB_3

F1

DQB_4

F3

DQB_5

F5

DQB_6

G4

DQB_7

H5

DQB_8

H6

DQB_9

J4

DQB_10

K6

DQB_11

K5

DQB_12

L4

DQB_13

M6

DQB_14

M1

DQB_15

M3

DQB_16

M5

DQB_17

N4

DQB_18

P6

DQB_19

P5

DQB_20

R4

DQB_21

T6

DQB_22

T1

DQB_23

U4

DQB_24

V6

DQB_25

V1

DQB_26

V3

DQB_27

Y6

DQB_28

Y1

DQB_29

Y3

DQB_30

Y5

DQB_31

H3

DQMB_0

H1

DQMB_1

T3

DQMB_2

T5

DQMB_3

F6

QSB_0

K3

QSB_1

P3

QSB_2

V5

QSB_3

G7

QSB_0B

K1

QSB_1B

P1

QSB_2B

W4

QSB_3B

T7

ODTB0

U10

CKEB0

L9

CLKB0

L8

CLKB0B

P10

CSB0B_0

L10

CSB0B_1

W10

CASB0B

T10

RASB0B

N10

WEB0B

P8

MAB_0

T9

MAB_1

P9

MAB_2

N7

MAB_3

N8

MAB_4

N9

MAB_5

U9

MAB_6

U8

MAB_7

Y9

MAB_8

W9

MAB_9

AC8

MAB_10

AC9

MAB_11

AA7

MAB_12

T8

NC_MAB_13

W8

NC_MAB_14

Y8

MAB_BA0

AA9

MAB_BA1

AA8

MAB_BA2

RV730XT A12 HF MVE SLT B1

RV730XT A12 HF MVE SLT B1

DDR2

DDR2

Single or

Diff Strobes

Single or

Diff Strobes

PART 4 OF 15

PART 4 OF 15

M

M
E

E
M

M
O

O
R

R
Y

Y

I

I
N

N
T

T
E

E
R

R
F

F
A

A
C

C
E

E

DDR3 GDDR3

DDR3 GDDR3

Differential Strobes

Differential Strobes

B

B
A

A
N

N
K

K

B

B

2

DQB1_0

AA4

DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

DQMB_4
DQMB_5
DQMB_6
DQMB_7

QSB_4
QSB_5
QSB_6
QSB_7

Read

Strobes

Read

Strobes

QSB_4B
QSB_5B
QSB_6B
QSB_7B

Write

Strobes

Write

Strobes

ODTB1

CKEB1
CLKB1

CLKB1B

CSB1B_0
CSB1B_1

CASB1B
RASB1B

WEB1B

MVREFDB

MVREFSB

DQB1_1

AB6

DQB1_2

AB1

DQB1_3

AB3

DQB1_4

AD6

DQB1_5

AD1

DQB1_6

AD3

DQB1_7

AD5

DQB1_8

AF1

DQB1_9

AF3

DQB1_10

AF6

DQB1_11

AG4

DQB1_12

AH5

DQB1_13

AH6

DQB1_14

AJ4

DQB1_15

AK3

DQB1_16

AF8

DQB1_17

AF9

DQB1_18

AG8

DQB1_19

AG7

DQB1_20

AK9

DQB1_21

AL7

DQB1_22

AM8

DQB1_23

AM7

DQB1_24

AK1

DQB1_25

AL4

DQB1_26

AM6

DQB1_27

AM1

DQB1_28

AN4

DQB1_29

AP3

DQB1_30

AP1

DQB1_31

AP5

AE4
AF5
AK6
AK5

AB5
AH1
AJ9
AM5

AC4
AH3
AJ8
AM3

W7

AA11
AD8

AD7

AD10
AC10

AA10
Y10
AB11

MVREFD_B

Y12

MVREFD/S =0.7*
VDDR1
(GDDR3/4/5)

MVREFS_B

AA12

CKEB1 (4,5)

CLKB1 (4,5)

CLKB1b (4,5)

CSB1b_0 (4)

CASB1b (4,5)
RASB1b (4,5)

WEB1b (4,5)

DNI

C298

C298

1uF_6.3V

1uF_6.3V

DNI

C307

C307

1uF_6.3V

1uF_6.3V

DQMB_4 (4,5)
DQMB_5 (4,5)
DQMB_6 (4,5)
DQMB_7 (4,5)

QSB_4 (4,5)
QSB_5 (4,5)
QSB_6 (4,5)
QSB_7 (4,5)

QSB_4b (4,5)
QSB_5b (4,5)
QSB_6b (4,5)
QSB_7b (4,5)

R123

R123

40.2R

40.2R
1%

R124

R124
100R

100R

1%

R127

R127

40.2R

40.2R
1%1%

R129

R129
100R

100R

1%

1

+MVDD

+MVDD

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

5

4

3

2

Title

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Sheet

Sheet

Sheet

of

319

of

319

of

319

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

50

50

50

105-B709xx-11

105-B709xx-11

105-B709xx-11

www.vinafix.vn

5

4

3

2

1

(4) GDDR3 Memory Channel A&B Bank 0

DQA0_[31..0](3,5)

D D

RASA0b(3,5)
MAA_BA_0(3,5)
MAA_BA_1(3,5)

MAA_[12..0](3,5)

C C

CASA0b(3,5)
CKEA0(3,5)

MAA_BA_2(3,5)

CSA0b_0(3)
WEA0b(3,5)
CLKA0b(3,5)

CLKA0(3,5)

QSA_0

QSA_0(3,5)

QSA_1

QSA_1(3,5)

QSA_3

QSA_3(3,5)

QSA_2

QSA_2(3,5)

QSA_0b

QSA_0b(3,5)

QSA_1b

QSA_1b(3,5)

QSA_3b

QSA_3b(3,5)

QSA_2b

QSA_2b(3,5)

DQMA_0

DQMA_0(3,5)

DQMA_1

DQMA_1(3,5)

DQMA_3

DQMA_3(3,5)

DQMA_2

DQMA_2(3,5)

+MVDD

DRAM_RST(3,5)

R219

R219

C244

C244

2.37K

2.37K

10nF

10nF

B B

A A

+MVDD

+MVDD

+MVDD

C245

C245
10nF

10nF

C2201

C2201
100nF_6.3V

100nF_6.3V

C2212

C2212
1uF_6.3V

1uF_6.3V

C223

C223
100nF_6.3V

100nF_6.3V

C228

C228
1uF_6.3V

1uF_6.3V

R220

R220

5.49K

5.49K

R221

R221

2.37K

2.37K

R222

R222

5.49K

5.49K
+MVDD

C2202

C2202
100nF_6.3V

100nF_6.3V

C2213

C2213
1uF_6.3V

1uF_6.3V

C224

C224
100nF_6.3V

100nF_6.3V

C229

C229
1uF_6.3V

1uF_6.3V

C238

C238
100nF_6.3V

100nF_6.3V

+MVDD

C240

C240
100nF_6.3V

100nF_6.3V

C2203

C2203
100nF_6.3V

100nF_6.3V

C2214

C2214
1uF_6.3V

1uF_6.3V

C225

C225
100nF_6.3V

100nF_6.3V

C230

C230
1uF_6.3V

1uF_6.3V

DQA0_0
DQA0_2
DQA0_1
DQA0_4
DQA0_5
DQA0_3
DQA0_7
DQA0_6
DQA0_10
DQA0_11
DQA0_12
DQA0_14
DQA0_15
DQA0_9
DQA0_13
DQA0_8
DQA0_27
DQA0_26
DQA0_24
DQA0_25
DQA0_28
DQA0_30
DQA0_31
DQA0_29
DQA0_16
DQA0_17
DQA0_19
DQA0_18
DQA0_21
DQA0_22
DQA0_20
DQA0_23

MAA_7
MAA_8
MAA_3
MAA_10
MAA_11
MAA_2
MAA_1
MAA_0
MAA_9
MAA_6
MAA_5
MAA_4

R218

R218
243R

243R

C239

C239
10nF

10nF

C2205

C2205
100nF_6.3V

100nF_6.3V

C216

C216
1uF_6.3V

1uF_6.3V

C226

C226
100nF_6.3V

100nF_6.3V

C231

C231
1uF_6.3V

1uF_6.3V

C241

C241
10nF

10nF

T3
T2
R3
R2
M3
N2
L3

M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2

F3

E2

C3

C2

B3

B2

H10

G9

G4

L4

K2

M9
K11

L9
K10
H11

K9

M4

K3

H2

K4

F9

H9

H3

F4

H4

J10
J11

P3
P10
D10

D3

P2
P11
D11

D2

N3
N10
E10

E3

V9

A4

H1
H12

U201

U201

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

23C21287QT1A

23C21287QT1A

C2207

C2207
100nF_6.3V

100nF_6.3V

C218

C218
1uF_6.3V

1uF_6.3V

C227

C227
100nF_6.3V

100nF_6.3V

C232

C232
1uF_6.3V

1uF_6.3V

5

CLKA0(3,5)
CLKA0b(3,5)

CKEA0(3,5)
RASA0b(3,5)
CASA0b(3,5)
WEA0b(3,5)
CSA0b_0(3)

C209

C209
100nF_6.3V

100nF_6.3V

C220

C220
1uF_6.3V

1uF_6.3V

VDDQ

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

RAR/CS1/RFU2

A12/RAR/RFU1

GND | VDD

GND | VDD

C2210

C2210
100nF_6.3V

100nF_6.3V

C221

C221
1uF_6.3V

1uF_6.3V

C233

C233
10uF_X6S

10uF_X6S

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2

VDD

A11
F1
F12
M1
M12
V2
V11

B1

VSSQ

B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3

VSS

A10
G1
G12
L1
L12
V3
V10

K1

VDDA

K12

J12
J1

VSSA

J3
J2
V4

RFU0

A9

MF

R201 121RR201 121R
R202 121RR202 121R

R203 121RR203 121R
R206 121RR206 121R
R207 121RR207 121R
R205 121RR205 121R
R204 82.5RR204 82.5R

C2211

C2211
100nF_6.3V

100nF_6.3V

C222

C222
1uF_6.3V

1uF_6.3V

C236

C236

C235

C235

10uF_X6S

10uF_X6S

10uF_X6S

10uF_X6S

+MVDD

+MVDD

C242

C242
100nF_6.3V

100nF_6.3V

+MVDD

C237

C237
10uF_X6S

10uF_X6S

DQA1_[31..0](3,5)

Rank 0
Top Layer

MAA_BA_2(3,5)
MAA_BA_1(3,5)
MAA_BA_0(3,5)

MAA_[12..0](3,5)

+MVDD

B2201B2201
B2202B2202

C243

C243
10nF

10nF

MAA_[12..0] (3,5)

+MVDD

C294

C294
10nF

10nF

+MVDD

C2295

C2295
10nF

10nF

In Single Rank Design use 60.4R (PN 316060R400G)
In Dual Rank Design use 121R (PN3160121000G)
R201, R202, R251, R252,
R208, R209, R265, R266

In Single Rank Design use 120 Ohm for CS and
in Dual Rank Design use 80 Ohm for CS
R204, R254, R433, R442

+MVDD

+MVDD

+MVDD

QSA_7(3,5)
QSA_5(3,5)
QSA_6(3,5)
QSA_4(3,5)

QSA_7b(3,5)
QSA_5b(3,5)
QSA_6b(3,5)
QSA_4b(3,5)

DQMA_7(3,5)
DQMA_5(3,5)
DQMA_6(3,5)
DQMA_4(3,5)

R259

R259

2.37K

2.37K

R260

R260

5.49K

5.49K

R261

R261

2.37K

2.37K

R262

R262

5.49K

5.49K
+MVDD

C2251

C2251
100nF_6.3V

100nF_6.3V

C2262

C2262
1uF_6.3V

1uF_6.3V

C2273

C2273
100nF_6.3V

100nF_6.3V

C2278

C2278
1uF_6.3V

1uF_6.3V

CSA1b_0(3)

WEA1b(3,5)
RASA1b(3,5)
CASA1b(3,5)
CKEA1(3,5)
CLKA1b(3,5)

CLKA1(3,5)

DRAM_RST(3,5)

C2288

C2288
100nF_6.3V

100nF_6.3V

+MVDD

C2252

C2252
100nF_6.3V

100nF_6.3V

C2263

C2263
1uF_6.3V

1uF_6.3V

C2276

C2276
100nF_6.3V

100nF_6.3V

C2281

C2281
1uF_6.3V

1uF_6.3V

MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

QSA_7
QSA_5
QSA_6
QSA_4

QSA_7b
QSA_5b
QSA_6b
QSA_4b

DQMA_7
DQMA_5
DQMA_6
DQMA_4

C290

C290
100nF_6.3V

100nF_6.3V

DQA1_28
DQA1_30
DQA1_29
DQA1_31
DQA1_24
DQA1_27
DQA1_26
DQA1_25
DQA1_15
DQA1_13
DQA1_14
DQA1_12
DQA1_10
DQA1_11
DQA1_8
DQA1_9
DQA1_21
DQA1_22
DQA1_17
DQA1_23
DQA1_19
DQA1_16
DQA1_18
DQA1_20
DQA1_5
DQA1_0
DQA1_6
DQA1_7
DQA1_3
DQA1_1
DQA1_4
DQA1_2

R210

R210
243R

243R

C2289

C2289
10nF

10nF

C2253

C2253
100nF_6.3V

100nF_6.3V

C2264

C2264
1uF_6.3V

1uF_6.3V

C2277

C2277
100nF_6.3V

100nF_6.3V

C2282

C2282
1uF_6.3V

1uF_6.3V

4

T3

T2
R3
R2
M3
N2

L3
M2

T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2

F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10
H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4
J10

J11

P3

P10
D10

D3

P2

P11
D11

D2
N3

N10
E10

E3

V9

A4

H1

H12

C291

C291
10nF

10nF

C2425

C2425
100nF_6.3V

100nF_6.3V

C2265

C2265
1uF_6.3V

1uF_6.3V

U202

U202

23C21287QT1A

23C21287QT1A

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

CLKA1(3,5)
CLKA1b(3,5)

CKEA1(3,5)
RASA1b(3,5)
CASA1b(3,5)
WEA1b(3,5)
CSA1b_0(3)

C2255

C2255

C2256

C2256

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C2266

C2266

C2424

C2424

1uF_6.3V

1uF_6.3V

100nF_6.3V

100nF_6.3V

Overlap footprintsOverlap footprints

VDDQ

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ
VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1
VSSQ#T4
VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VDDA#K12

VSSA#J12

VSSA

RAR/CS1/RFU2
A12/RAR/RFU1

RFU0

GND | VDD

GND | VDD

R251 121RR251 121R

R252 121RR252 121R

R253 121RR253 121R

R256 121RR256 121R

R257 121RR257 121R

R255 121RR255 121R

R254 82.5RR254 82.5R

C2257

C2257
100nF_6.3V

100nF_6.3V

C2268

C2268
1uF_6.3V

1uF_6.3V

C2283

C2283
10uF_X6S

10uF_X6S

VDD

VSS

MF

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

C2259

C2259
100nF_6.3V

100nF_6.3V

C2270

C2270
1uF_6.3V

1uF_6.3V

C2284

C2284
10uF_X6S

10uF_X6S

+MVDD

+MVDD

C292

C292
100nF_6.3V

100nF_6.3V

MAA_12

+MVDD

C2260

C2260
100nF_6.3V

100nF_6.3V

C2271

C2271
1uF_6.3V

1uF_6.3V

C2285

C2285
10uF_X6S

10uF_X6S

C2293

C2293
10nF

10nF

C2261

C2261
100nF_6.3V

100nF_6.3V

C2272

C2272
1uF_6.3V

1uF_6.3V

C2286

C2286
10uF_X6S

10uF_X6S

+MVDD

B251B251
B252B252

MAA_[12..0] (3,5)

C2426

C2426
100nF_6.3V

100nF_6.3V

+MVDD

C344

C344
10nF

10nF

C345

C345
10nF

10nF

3

+MVDD

+MVDD

+MVDD

+MVDD

DQB0_[31..0](3,5)

MAB_[11..0](3,5)

C2301

C2301
100nF_6.3V

100nF_6.3V

C312

C312
1uF_6.3V

1uF_6.3V

C323

C323
100nF_6.3V

100nF_6.3V

C2328

C2328
1uF_6.3V

1uF_6.3V

QSB_0b(3,5)
QSB_1b(3,5)
QSB_3b(3,5)
QSB_2b(3,5)

DQMB_0(3,5)
DQMB_1(3,5)
DQMB_3(3,5)
DQMB_2(3,5)

R319

R319

2.37K

2.37K

R320

R320

5.49K

5.49K

R321

R321

2.37K

2.37K

R322

R322

5.49K

5.49K

QSB_0(3,5)
QSB_1(3,5)
QSB_3(3,5)
QSB_2(3,5)

MAB_BA_0(3,5)
MAB_BA_1(3,5)

MAB_BA_2(3,5)

+MVDD

C302

C302
100nF_6.3V

100nF_6.3V

C313

C313
1uF_6.3V

1uF_6.3V

C324

C324
100nF_6.3V

100nF_6.3V

C2329

C2329
1uF_6.3V

1uF_6.3V

CASB0b(3,5)
CKEB0(3,5)

CSB0b_0(3)
WEB0b(3,5)
CLKB0b(3,5)

CLKB0(3,5)

DRAM_RST(3,5)

C2338

C2338
100nF_6.3V

100nF_6.3V

RASB0b(3,5)

C340

C340
100nF_6.3V

100nF_6.3V

C2303

C2303
100nF_6.3V

100nF_6.3V

C314

C314
1uF_6.3V

1uF_6.3V

DQB0_0
DQB0_2
DQB0_1
DQB0_3
DQB0_5
DQB0_4
DQB0_7
DQB0_6
DQB0_11
DQB0_12
DQB0_14
DQB0_10
DQB0_13
DQB0_9
DQB0_15
DQB0_8
DQB0_24
DQB0_26
DQB0_25
DQB0_27
DQB0_29
DQB0_31
DQB0_28
DQB0_30
DQB0_16
DQB0_17
DQB0_19
DQB0_18
DQB0_23
DQB0_20
DQB0_21
DQB0_22

MAB_7
MAB_8
MAB_3
MAB_10
MAB_11
MAB_2
MAB_1
MAB_0
MAB_9
MAB_6
MAB_5
MAB_4

QSB_0
QSB_1
QSB_3
QSB_2

QSB_0b
QSB_1b
QSB_3b
QSB_2b

DQMB_0
DQMB_1
DQMB_3MAA_12
DQMB_2

R318

R318
243R

243R

C2339

C2339
10nF

10nF

C304

C304
100nF_6.3V

100nF_6.3V

C315

C315
1uF_6.3V

1uF_6.3V

C341

C341
10nF

10nF

T3
T2
R3
R2
M3
N2
L3

M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2

F3

E2

C3

C2

B3

B2

H10

G9

G4

L4

K2

M9
K11

L9
K10
H11

K9

M4

K3

H2

K4

F9

H9

H3

F4

H4
J10

J11

P3
P10
D10

D3

P2
P11
D11

D2

N3
N10
E10

E3

V9

A4

H1
H12

U301

U301

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

23C21287QT1A

23C21287QT1A

CLKB0(3,5)
CLKB0b(3,5)

CKEB0(3,5)
RASB0b(3,5)
CASB0b(3,5)
WEB0b(3,5)
CSB0b_0(3)

C306

C306

C2305

C2305

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C317

C317

C316

C316

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

Overlap footprints

VDDQ

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ
VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1
VSSQ#T4
VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VDDA#K12

VSSA#J12

VSSA

RAR/CS1/RFU2
A12/RAR/RFU1

RFU0

GND | VDD

GND | VDD

R208 121RR208 121R

R209 121RR209 121R

R432 121RR432 121R

R435 121RR435 121R

R436 121RR436 121R

R434 121RR434 121R

R433 82.5RR433 82.5R

C2307

C2307
100nF_6.3V

100nF_6.3V

C318

C318
1uF_6.3V

1uF_6.3V

C2333

C2333
10uF_X6S

10uF_X6S

VDD

VSS

MF

C308

C308
100nF_6.3V

100nF_6.3V

C319

C319
1uF_6.3V

1uF_6.3V

C2334

C2334
10uF_X6S

10uF_X6S

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

C2342

C2342
100nF_6.3V

100nF_6.3V

+MVDD+MVDD

+MVDD

C309

C309
100nF_6.3V

100nF_6.3V

C320

C320
1uF_6.3V

1uF_6.3V

C2335

C2335
10uF_X6S

10uF_X6S

+MVDD

+MVDD

MAB_12

C343

C343
10nF

10nF

C310

C310
100nF_6.3V

100nF_6.3V

C321

C321
1uF_6.3V

1uF_6.3V

+MVDD

C2336

C2336
10uF_X6S

10uF_X6S

2

DQB1_[31..0](3,5)

DQB1_28
DQB1_30
DQB1_29
DQB1_31
DQB1_25
DQB1_26
DQB1_24
DQB1_27
DQB1_15
DQB1_13
DQB1_14
DQB1_12
DQB1_10
DQB1_11
DQB1_8
DQB1_9
DQB1_23
DQB1_21
DQB1_16
DQB1_22
DQB1_19
DQB1_20
DQB1_17
DQB1_18
DQB1_6
DQB1_0
DQB1_7
DQB1_4
DQB1_2
DQB1_1
DQB1_3
DQB1_5

MAB_BA_2(3,5)
MAB_BA_1(3,5)
MAB_BA_0(3,5)

MAB_[11..0](3,5)

+MVDD

B301B301
B302B302

MAB_[12..0] (3,5)

+MVDD

C392

C392
10nF

10nF

+MVDD

C393

C393
10nF

10nF

C311

C311
100nF_6.3V

100nF_6.3V

C322

C322
1uF_6.3V

1uF_6.3V

MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

CSB1b_0(3)

WEB1b(3,5)
RASB1b(3,5)
CASB1b(3,5)
CKEB1(3,5)
CLKB1b(3,5)

CLKB1(3,5)

QSB_7

QSB_7(3,5)

QSB_5

QSB_5(3,5)

QSB_6

QSB_6(3,5)

QSB_4

QSB_4(3,5)

QSB_7b

QSB_7b(3,5)

QSB_5b

QSB_5b(3,5)

QSB_6b

QSB_6b(3,5)

QSB_4b

QSB_4b(3,5)

DQMB_7

DQMB_7(3,5)

DQMB_5

DQMB_5(3,5)

DQMB_6

DQMB_6(3,5)

DQMB_4

DQMB_4(3,5)

DRAM_RST(3,5)

R310

R359

R359

2.37K

2.37K

R360

R360

5.49K

5.49K

R361

R361

2.37K

2.37K

R362

R362

5.49K

5.49K

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

R310
243R

243R

C388

C388
100nF_6.3V

100nF_6.3V

+MVDD

C390

C390

100nF_6.3V

100nF_6.3V

+MVDD

+MVDD

C352

C352

C351

C351

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C363

C363

C362

C362

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

+MVDD

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

C389

C389
10nF

10nF

T3

T2
R3
R2
M3
N2

L3
M2

T10

T11
R10
R11
M10
N11

L10
M11
G10

F11

F10

E11
C10
C11

B10

B11

G3

F2
F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10

H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4

J10
J11

P3

P10

D10

D3

P2

P11

D11

D2
N3

N10

E10

E3

V9

A4

H1

H12

C391

C391
10nF

10nF

C353

C353
100nF_6.3V

100nF_6.3V

C364

C364
1uF_6.3V

1uF_6.3V

C373

C373
100nF_6.3V

100nF_6.3V

C378

C378
1uF_6.3V

1uF_6.3V

U302

U302

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

23C21287QT1A

23C21287QT1A

CLKB1(3,5)
CLKB1b(3,5)

CKEB1(3,5)
RASB1b(3,5)
CASB1b(3,5)
WEB1b(3,5)
CSB1b_0(3)

C354

C354
100nF_6.3V

100nF_6.3V

C2365

C2365
1uF_6.3V

1uF_6.3V

C374

C374
100nF_6.3V

100nF_6.3V

C379

C379
1uF_6.3V

1uF_6.3V

A1

VDDQ

A12

VDDQ#A12

C1

VDDQ#C1

C4

VDDQ#C4

C9

VDDQ#C9

C12

VDDQ#C12

E1

VDDQ#E1

E4

VDDQ#E4

E9

VDDQ#E9

E12

VDDQ#E12

J4

VDDQ#J4

J9

VDDQ#J9

N1

VDDQ#N1

N4

VDDQ#N4

N9

VDDQ#N9

N12

VDDQ#N12

R1

VDDQ#R1

R4

VDDQ#R4

R9

VDDQ#R9

R12

VDDQ#R12

V1

VDDQ#V1

V12

VDDQ#V12

A2

VDD

A11

VDD#A11

F1

VDD#F1

F12

VDD#F12

M1

VDD#M1

M12

VDD#M12

V2

VDD#V2

V11

VDD#V11

B1

VSSQ

B4

VSSQ#B4

B9

VSSQ#B9

B12

VSSQ#B12

D1

VSSQ#D1

D4

VSSQ#D4

D9

VSSQ#D9

D12

VSSQ#D12

G2

VSSQ#G2

G11

VSSQ#G11

L2

VSSQ#L2

L11

VSSQ#L11

P1

VSSQ#P1

P4

VSSQ#P4

P9

VSSQ#P9

P12

VSSQ#P12

T1

VSSQ#T1

T4

VSSQ#T4

T9

VSSQ#T9

T12

VSSQ#T12

A3

VSS

A10

VSS#A10

G1

VSS#G1

G12

VSS#G12

L1

VSS#L1

L12

VSS#L12

V3

VSS#V3

V10

VSS#V10

K1

VDDA

K12

VDDA#K12

J12

VSSA#J12

J1

VSSA

A12/RAR/RFU1

RFU0

GND | VDD

GND | VDD

R265 121RR265 121R
R266 121RR266 121R

R441 121RR441 121R
R444 121RR444 121R
R445 121RR445 121R
R443 121RR443 121R
R442 82.5RR442 82.5R

C356

C356
100nF_6.3V

100nF_6.3V

C2367

C2367
1uF_6.3V

1uF_6.3V

MF

J3
J2
V4

A9

C357

C357
100nF_6.3V

100nF_6.3V

C368

C368
1uF_6.3V

1uF_6.3V

C384

C384
10uF_X6S

10uF_X6S

RAR/CS1/RFU2

C355

C355
100nF_6.3V

100nF_6.3V

C2366

C2366
1uF_6.3V

1uF_6.3V

Overlap footprints

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Sheet

Sheet

Sheet

of

419

of

419

of

419

1

+MVDD

+MVDD

C394

C394
100nF_6.3V

100nF_6.3V

MAB_12

+MVDD+MVDD

C358

C358
100nF_6.3V

100nF_6.3V

C369

C369
1uF_6.3V

1uF_6.3V

C385

C385
10uF_X6S

10uF_X6S

C395

C395
10nF

10nF

Doc No.

Doc No.

Doc No.

C359

C359
100nF_6.3V

100nF_6.3V

C370

C370
1uF_6.3V

1uF_6.3V

C386

C386
10uF_X6S

10uF_X6S

+MVDD

B351B351
B352B352

MAB_[12..0] (3,5)

C360

C360

C361

C361

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C371

C371

C372

C372

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

+MVDD

C387

C387
10uF_X6S

10uF_X6S

RevDate:

RevDate:

RevDate:

50

50

50

105-B709xx-11

105-B709xx-11

105-B709xx-11

www.vinafix.vn

5

4

3

2

1

(5) GDDR3 Memory Channel A&B Bank 1

DQA0_[31..0](3,4) DQB0_[31..0](3,4)DQA1_[31..0](3,4)

D D

MAA_BA_2(3,4)
MAA_BA_1(3,4)
MAA_BA_0(3,4)

MAA_[12..0](3,4)

C C

CSA0b_1(3)

WEA0b(3,4)
RASA0b(3,4)
CASA0b(3,4)
CKEA0(3,4)
CLKA0b(3,4)

CLKA0(3,4)

QSA_1

QSA_1(3,4)

QSA_0

QSA_0(3,4)

QSA_2

QSA_2(3,4)

QSA_3

QSA_3(3,4)

QSA_1b

QSA_1b(3,4)

QSA_0b

QSA_0b(3,4)

QSA_2b

QSA_2b(3,4)

QSA_3b

QSA_3b(3,4)

DQMA_1

DQMA_1(3,4)

DQMA_0

DQMA_0(3,4)

DQMA_2

DQMA_2(3,4)

DQMA_3

DQMA_3(3,4)

+MVDD

R401

R401

C444

C444

2.37K

2.37K

10nF

10nF

B B

+MVDD

C445

C445
10nF

10nF

R402

R402

5.49K

5.49K

R415

R415

2.37K

2.37K

R418

R418

5.49K

5.49K
+MVDD

C438

C438
100nF_6.3V

100nF_6.3V

+MVDD

C440

C440
100nF_6.3V

100nF_6.3V

DQA0_10
DQA0_11
DQA0_12
DQA0_14
DQA0_15
DQA0_9
DQA0_13
DQA0_8
DQA0_0
DQA0_2
DQA0_1
DQA0_4
DQA0_5
DQA0_3
DQA0_7
DQA0_6
DQA0_16
DQA0_17
DQA0_19
DQA0_18
DQA0_21
DQA0_22
DQA0_20
DQA0_23
DQA0_27
DQA0_26
DQA0_24
DQA0_25
DQA0_28
DQA0_30
DQA0_31
DQA0_29

MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

R400

R400
243R

243R

C439

C439
10nF

10nF

U401

U401

T3

DQ31 | DQ23

T2

DQ30 | DQ22

VDDQ#A12

DQ29 | DQ21

VDDQ#C1

DQ28 | DQ20

VDDQ#C4

DQ27 | DQ19

VDDQ#C9

DQ26 | DQ18

VDDQ#C12

DQ25 | DQ17

VDDQ#E1

DQ24 | DQ16

VDDQ#E4

DQ23 | DQ31

VDDQ#E9

DQ22 | DQ30

VDDQ#E12
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

23C21287QT1A

23C21287QT1A

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4

VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1

VSSQ#P4

VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

RAR/CS1/RFU2

A12/RAR/RFU1

GND | VDD

GND | VDD

CLKA0(3,4)
CLKA0b(3,4)

CSA0b_1(3) CSA1b_1(3)

C441

C441
10nF

10nF

R3
R2
M3
N2

L3

M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2
F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10
H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4
J10

J11

P3

P10
D10

D3

P2

P11
D11

D2
N3

N10
E10

E3

V9

A4

H1

H12

+MVDD

A1

VDDQ

A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

+MVDD

A2

VDD

A11
F1
F12
M1
M12
V2
V11

B1

VSSQ

B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3

VSS

A10
G1
G12
L1
L12
V3
V10

K1

VDDA

K12

C442

C442
100nF_6.3V

100nF_6.3V

J12
J1

VSSA

J3

MAA_12

J2
V4

RFU0

A9

MF

+MVDD +MVDD

R437 121RR437 121R
R438 121RR438 121R

R428

R428

82.5R

82.5R

C443

C443
10nF

10nF

Rank 1
Bottom Layer

MAA_[12..0](3,4)

+MVDD

B401B401
B402B402

QSA_5(3,4)
QSA_7(3,4)
QSA_4(3,4)
QSA_6(3,4)

QSA_5b(3,4)
QSA_7b(3,4)
QSA_4b(3,4)
QSA_6b(3,4)

MAA_[12..0] (3,4)

DQMA_5(3,4)
DQMA_7(3,4)
DQMA_4(3,4)
DQMA_6(3,4)

+MVDD

R408

R408

C492

C492

2.37K

2.37K

10nF

10nF

R409

R409

5.49K

5.49K

+MVDD

C493

C493

R410

R410

10nF

10nF

2.37K

2.37K

R411

R411

5.49K

5.49K

MAA_BA_0(3,4)
MAA_BA_1(3,4)

MAA_BA_2(3,4)

+MVDD

CASA1b(3,4)
CKEA1(3,4)

CSA1b_1(3)
WEA1b(3,4)
CLKA1b(3,4)

CLKA1(3,4)

DRAM_RST(3,4)DRAM_RST(3,4)

C488

C488
100nF_6.3V

100nF_6.3V

+MVDD

RASA1b(3,4)

QSA_5
QSA_7
QSA_4
QSA_6

QSA_5b
QSA_7b
QSA_4b
QSA_6b

DQMA_5
DQMA_7
DQMA_4
DQMA_6

C490

C490
100nF_6.3V

100nF_6.3V

DQA1_15
DQA1_13
DQA1_14
DQA1_12
DQA1_10
DQA1_11
DQA1_8
DQA1_9
DQA1_28
DQA1_30
DQA1_29
DQA1_31
DQA1_24
DQA1_27
DQA1_26
DQA1_25
DQA1_5
DQA1_0
DQA1_6
DQA1_7
DQA1_3
DQA1_1
DQA1_4
DQA1_2
DQA1_21
DQA1_22
DQA1_17
DQA1_23
DQA1_19
DQA1_16
DQA1_18
DQA1_20

MAA_7
MAA_8
MAA_3
MAA_10
MAA_11
MAA_2
MAA_1
MAA_0
MAA_9
MAA_6
MAA_5
MAA_4

R407

R407
243R

243R

C489

C489
10nF

10nF

C491

C491
10nF

10nF

T3

T2
R3
R2
M3
N2

L3
M2

T10
T11
R10

R11
M10
N11

L10
M11
G10

F11

F10
E11
C10
C11
B10
B11

G3

F2
F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10
H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4

J10
J11

P3

P10
D10

D3

P2

P11
D11

D2
N3

N10
E10

E3

V9

A4

H1

H12

U402

U402

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

23C21287QT1A

23C21287QT1A

CLKA1(3,4)
CLKA1b(3,4)

VDDQ

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ
VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1
VSSQ#T4
VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VDDA#K12

VSSA#J12

VSSA

RAR/CS1/RFU2

A12/RAR/RFU1

GND | VDD

GND | VDD

R446 121RR446 121R

R447 121RR447 121R

+MVDD
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

+MVDD
A2

VDD

A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3

VSS

A10
G1
G12
L1
L12
V3
V10

K1
K12

C494

C494
100nF_6.3V

100nF_6.3V

J12
J1

J3

MAA_12

J2
V4

RFU0

A9

MF

+MVDD +MVDD

R429

R429

82.5R

82.5R

C495

C495
10nF

10nF

+MVDD

B451B451
B452B452

MAA_[12..0] (3,4)

C544

C544
10nF

10nF

C545

C545
10nF

10nF

+MVDD

MAB_BA_2(3,4)
MAB_BA_1(3,4)
MAB_BA_0(3,4)

MAB_[12..0](3,4)

CSB0b_1(3)

WEB0b(3,4)
RASB0b(3,4)
CASB0b(3,4)
CKEB0(3,4)
CLKB0b(3,4)

CLKB0(3,4)

QSB_1

QSB_1(3,4)

QSB_0

QSB_0(3,4)

QSB_2

QSB_2(3,4)

QSB_3

QSB_3(3,4)

QSB_1b

QSB_1b(3,4)

QSB_0b

QSB_0b(3,4)

QSB_2b

QSB_2b(3,4)

QSB_3b

QSB_3b(3,4)

DQMB_1

DQMB_1(3,4)

DQMB_0

DQMB_0(3,4)

DQMB_2

DQMB_2(3,4)

DQMB_3

DQMB_3(3,4)

R501

R501

2.37K

2.37K

C538

C538

R502

R502

100nF_6.3V

100nF_6.3V

5.49K

5.49K
+MVDD

R515

R515

2.37K

2.37K

R518

R518

C540

C540

5.49K

5.49K

100nF_6.3V

100nF_6.3V

+MVDD

DQB0_11
DQB0_12
DQB0_14
DQB0_10
DQB0_13
DQB0_9
DQB0_15
DQB0_8
DQB0_0
DQB0_2
DQB0_1
DQB0_3
DQB0_5
DQB0_4
DQB0_7
DQB0_6
DQB0_16
DQB0_17
DQB0_19
DQB0_18
DQB0_23
DQB0_20
DQB0_21
DQB0_22
DQB0_24
DQB0_26
DQB0_25
DQB0_27
DQB0_29
DQB0_31
DQB0_28
DQB0_30

MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

R500

R500
243R

243R

C539

C539
10nF

10nF

U501

U501

T3

DQ31 | DQ23

T2

DQ30 | DQ22

VDDQ#A12
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

RAR/CS1/RFU2

A12/RAR/RFU1

GND | VDD

GND | VDD

CLKB0(3,4)
CLKB0b(3,4)

CSB0b_1(3) CSB1b_1(3)

C541

C541
10nF

10nF

R3
R2
M3
N2

L3

M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2
F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10
H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4
J10

J11

P3

P10
D10

D3

P2

P11
D11

D2
N3

N10
E10

E3

V9

A4

H1

H12

23C21287QT1A

23C21287QT1A

A1

VDDQ

A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2

VDD

A11
F1
F12
M1
M12
V2
V11

B1

VSSQ

B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3

VSS

A10
G1
G12
L1
L12
V3
V10

K1

VDDA

K12

J12
J1

VSSA

J3
J2
V4

RFU0

A9

MF

R430 121RR430 121R
R431 121RR431 121R

R528

R528

82.5R

82.5R

+MVDD

+MVDD

C542

C542
100nF_6.3V

100nF_6.3V

MAB_12

+MVDD+MVDD

C543

C543
10nF

10nF

DQB1_[31..0](3,4)

+MVDD

B501B501
B502B502

MAB_[12..0] (3,4)

+MVDD

C592

C592
10nF

10nF

+MVDD+MVDD

C593

C593
10nF

10nF

U502

U502

DQB1_15

T3

DQ31 | DQ23

DQB1_13

T2

DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

CLKB1(3,4)
CLKB1b(3,4)

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

RAR/CS1/RFU2

A12/RAR/RFU1

GND | VDD

GND | VDD

DQB1_14

R3

DQB1_12

R2

DQB1_10

M3

DQB1_11

N2

DQB1_8

L3

DQB1_9

M2

DQB1_28

T10

DQB1_30

T11

DQB1_29

R10

DQB1_31

R11

DQB1_25

M10

DQB1_26

N11

DQB1_24

L10

DQB1_27

M11

DQB1_6

G10

DQB1_0

F11

DQB1_7

F10

DQB1_4

E11

DQB1_2

C10

DQB1_1

C11

DQB1_3

B10

DQB1_5

B11

DQB1_23

G3

DQB1_21

F2

DQB1_16

F3

DQB1_22

E2

DQB1_19

C3

DQB1_20

C2

DQB1_17

B3

DQB1_18

B2

H10

RASB1b(3,4)

QSB_5
QSB_7
QSB_4
QSB_6

QSB_5b
QSB_7b
QSB_4b
QSB_6b

DQMB_5
DQMB_7
DQMB_4
DQMB_6

R507

R507
243R

243R

C590

C590
100nF_6.3V

100nF_6.3V

MAB_7
MAB_8
MAB_3
MAB_10
MAB_11
MAB_2
MAB_1
MAB_0
MAB_9
MAB_6
MAB_5
MAB_4

C589

C589
10nF

10nF

C591

C591
10nF

10nF

G9
G4

L4
K2

M9

K11

L9

K10

H11

K9

M4

K3

H2

K4

F9
H9
H3

F4
H4

J10
J11

P3

P10

D10

D3

P2

P11

D11

D2
N3

N10

E10

E3

V9

A4

H1

H12

23C21287QT1A

23C21287QT1A

MAB_BA_0(3,4)
MAB_BA_1(3,4)

MAB_[12..0](3,4)

CASB1b(3,4)
CKEB1(3,4)

MAB_BA_2(3,4)

CSB1b_1(3)
WEB1b(3,4)
CLKB1b(3,4)

CLKB1(3,4)

QSB_5(3,4)
QSB_7(3,4)
QSB_4(3,4)
QSB_6(3,4)

QSB_5b(3,4)
QSB_7b(3,4)
QSB_4b(3,4)
QSB_6b(3,4)

DQMB_5(3,4)
DQMB_7(3,4)
DQMB_4(3,4)
DQMB_6(3,4)

DRAM_RST(3,4)DRAM_RST(3,4)

R508

R508

2.37K

2.37K

C588

C588

R509

R509

100nF_6.3V

100nF_6.3V

5.49K

5.49K
+MVDD

R510

R510

2.37K

2.37K

R511

R511

5.49K

5.49K

+MVDD

A1

VDDQ

A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2

VDD

A11
F1
F12
M1
M12
V2
V11

B1

VSSQ

B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3

VSS

A10
G1
G12
L1
L12
V3
V10

K1

VDDA

K12

J12
J1

VSSA

J3
J2
V4

RFU0

A9

MF

R439 121RR439 121R
R440 121RR440 121R

R529

R529

82.5R

82.5R

+MVDD

+MVDD

C594

C594
100nF_6.3V

100nF_6.3V

MAB_12

C595

C595
10nF

10nF

+MVDD

B551B551
B552B552

MAB_[12..0] (3,4)

+MVDD

C508

C501

C501
100nF_6.3V

100nF_6.3V

C512

C512
1uF_6.3V

+MVDD

C410

C409

C409
100nF_6.3V

100nF_6.3V

C420

C420
1uF_6.3V

1uF_6.3V

C436

C436
10uF_X6S

10uF_X6S

C410
100nF_6.3V

100nF_6.3V

C421

C421
1uF_6.3V

1uF_6.3V

C437

C437
10uF_X6S

10uF_X6S

+MVDD

C473

C473
100nF_6.3V

100nF_6.3V

C478

C478
1uF_6.3V

1uF_6.3V

C452

C452
100nF_6.3V

100nF_6.3V

C463

C463
1uF_6.3V

1uF_6.3V

C474

C474
100nF_6.3V

100nF_6.3V

C479

C479
1uF_6.3V

1uF_6.3V

C453

C453
100nF_6.3V

100nF_6.3V

C464

C464
1uF_6.3V

1uF_6.3V

C475

C475
100nF_6.3V

100nF_6.3V

C480

C480
1uF_6.3V

1uF_6.3V

4

C454

C454
100nF_6.3V

100nF_6.3V

C465

C465
1uF_6.3V

1uF_6.3V

C476

C476
100nF_6.3V

100nF_6.3V

C481

C481
1uF_6.3V

1uF_6.3V

C455

C455
100nF_6.3V

100nF_6.3V

C466

C466
1uF_6.3V

1uF_6.3V

C457

C457

C456

C456

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C467

C467

C468

C468

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C483

C483
10uF_X6S

10uF_X6S

Overlap footprints

C458

C458
100nF_6.3V

100nF_6.3V

C469

C469
1uF_6.3V

1uF_6.3V

C484

C484
10uF_X6S

10uF_X6S

C459

C459
100nF_6.3V

100nF_6.3V

C470

C470
1uF_6.3V

1uF_6.3V

C485

C485
10uF_X6S

10uF_X6S

C460

C460
100nF_6.3V

100nF_6.3V

C471

C471
1uF_6.3V

1uF_6.3V

C486

C486
10uF_X6S

10uF_X6S

C461

C461
100nF_6.3V

100nF_6.3V

C472

C472
1uF_6.3V

1uF_6.3V

+MVDD

3

C408

C402

C402

C403

C403

100nF_6.3V

100nF_6.3V

100nF_6.3V

A A

+MVDD +MVDD

C423

C423
100nF_6.3V

100nF_6.3V

C428

C428
1uF_6.3V

1uF_6.3V

C413

C413
1uF_6.3V

1uF_6.3V

C426

C426
100nF_6.3V

100nF_6.3V

C431

C431
1uF_6.3V

1uF_6.3V

100nF_6.3V

C414

C414
1uF_6.3V

1uF_6.3V

C427

C427
100nF_6.3V

100nF_6.3V

C432

C432
1uF_6.3V

1uF_6.3V

C404

C404
100nF_6.3V

100nF_6.3V

C415

C415
1uF_6.3V

1uF_6.3V

C405

C405
100nF_6.3V

100nF_6.3V

C416

C416
1uF_6.3V

1uF_6.3V

C406

C406
100nF_6.3V

100nF_6.3V

C417

C417
1uF_6.3V

1uF_6.3V

C407

C407
100nF_6.3V

100nF_6.3V

C418

C418
1uF_6.3V

1uF_6.3V

C434

C434
10uF_X6S

10uF_X6S

C408
100nF_6.3V

100nF_6.3V

C419

C419
1uF_6.3V

1uF_6.3V

C435

C435
10uF_X6S

10uF_X6S

Overlap footprints

5

1uF_6.3V

+MVDD

C528

C528
1uF_6.3V

1uF_6.3V

C583

C583
10uF_X6S

10uF_X6S

Overlap footprints

C584

C584
10uF_X6S

10uF_X6S

C502

C502
100nF_6.3V

100nF_6.3V

C513

C513
1uF_6.3V

1uF_6.3V

C523

C523
100nF_6.3V

100nF_6.3V

C585

C585
10uF_X6S

10uF_X6S

C503

C503
100nF_6.3V

100nF_6.3V

C514

C514
1uF_6.3V

1uF_6.3V

C586

C586
10uF_X6S

10uF_X6S

C504

C504
100nF_6.3V

100nF_6.3V

C515

C515
1uF_6.3V

1uF_6.3V

+MVDD

C506

C506

C505

C505

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C516

C516

C517

C517

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

Overlap footprints

C507

C507
100nF_6.3V

100nF_6.3V

C518

C518
1uF_6.3V

1uF_6.3V

C534

C534
10uF_X6S

10uF_X6S

C508
100nF_6.3V

100nF_6.3V

C519

C519
1uF_6.3V

1uF_6.3V

C535

C535
10uF_X6S

10uF_X6S

C509

C509
100nF_6.3V

100nF_6.3V

C520

C520
1uF_6.3V

1uF_6.3V

C536

C536
10uF_X6S

10uF_X6S

2

C510

C510
100nF_6.3V

100nF_6.3V

C521

C521
1uF_6.3V

1uF_6.3V

C537

C537
10uF_X6S

10uF_X6S

+MVDD

C511

C511
100nF_6.3V

100nF_6.3V

C522

C522
1uF_6.3V

1uF_6.3V

+MVDD

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

+MVDD

C551

C551
100nF_6.3V

100nF_6.3V

C562

C562
1uF_6.3V

1uF_6.3V

C573

C573
100nF_6.3V

100nF_6.3V

C578

C578
1uF_6.3V

1uF_6.3V

C552

C552
100nF_6.3V

100nF_6.3V

C563

C563
1uF_6.3V

1uF_6.3V

C574

C574
100nF_6.3V

100nF_6.3V

C579

C579
1uF_6.3V

1uF_6.3V

C553

C553
100nF_6.3V

100nF_6.3V

C564

C564
1uF_6.3V

1uF_6.3V

C575

C575
100nF_6.3V

100nF_6.3V

C580

C580
1uF_6.3V

1uF_6.3V

C555

C555

C554

C554

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C566

C566

C565

C565

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

C557

C557

C556

C556

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C568

C568

C567

C567

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Sheet

Sheet

Sheet

of

519

of

519

of

519

1

C558

C558
100nF_6.3V

100nF_6.3V

C569

C569
1uF_6.3V

1uF_6.3V

Doc No.

Doc No.

Doc No.

C559

C559

C560

C560

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C571

C571

C570

C570

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

105-B709xx-11

105-B709xx-11

105-B709xx-11

RevDate:

RevDate:

RevDate:

C561

C561
100nF_6.3V

100nF_6.3V

C572

C572
1uF_6.3V

1uF_6.3V

50

50

50

www.vinafix.vn

5

(06) RV730 GPIOs Strap CF XTAL

U1E

+3.3V

C332

C332
100nF_6.3V

100nF_6.3V

D D

DDC6CLK(17)

DDC6DATA(17)

+3.3V_BUS +1.8V

R899

R899

5.1K

5.1K

PWR_GOOD(1,14,15,16)

C C

DNI

C333

C333
100nF_6.3V

100nF_6.3V

SCL(17)

SDA(17)

C334

C334
100nF_6.3V

100nF_6.3V

SCL
SDA

DDC6CLK
DDC6DATA

PWR_GOOD_R

DNI

GPIO_22_ROMCSb_R
GPIO_8_R

U1E

AF23

VDDR3#1

AF24

VDDR3#2

AG23

VDDR3#3

AG24

VDDR3#4

AK26

SCL

AJ26

SDA

AJ30

DDC6CLK

AJ31

DDC6DATA

AF28

RSVD#1

AF35

RSVD#2

AG28

RSVD#3

AG36

RSVD#4

AJ27

RSVD#5

AK27

RSVD#6

AL31

RSVD#7

AN36

RSVD#8

AP37

RSVD#9

AJ21

NC#1

AK21

NC#2

AH16

NC_PWRGOOD

RV730XT A12 HF MVE SLT B1

RV730XT A12 HF MVE SLT B1

R180

R180
10K

10K

4

PART 5 OF 15

PART 5 OF 15

G

G
P

P
I

I
O

O

GPIO_17_THERMAL_INT

U2

U2

1

CE#

VCC

2

SO

HOLD#

3

WP#

SCK

GND4SI

PM25LV512A-100SCE

PM25LV512A-100SCE

GPIO_0
GPIO_1
GPIO_2

GPIO_3_SMBDATA

GPIO_4_SMBCLK

GPIO_5_AC_BATT

GPIO_6_TACH
GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_11
GPIO_12
GPIO_13

GPIO_14_HPD2

GPIO_15_PWRCNTL_0

GPIO_16_SSIN

GPIO_18_HPD3

GPIO_19_CTF

GPIO_20_PWRCNTL_1

GPIO_21_BB_EN

GPIO_22_ROMCSB

GPIO_23_CLKREQB

GENERICA

GENERICB
GENERICC
GENERICD

GENERICE_HPD4

GENERICF
GENERICG

HPD1

+3.3V

8
7

GPIO_10_R

6

GPIO_9_R

5

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13

AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

AK24

C342

C342
100nF_6.3V

100nF_6.3V

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5
GPIO_6_TACH
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
HPD2
PWRCNTL_0
GPIO_16
GPIO_17_ThermINT
HPD3
GPIO_19_CTF
PWRCNTL_1
GPIO_21
GPIO_22_ROMCSb

GENERICA
GENERICB
GENERICC
GENERICD

HPD1

BIOS1

BIOS1

BIOS

BIOS

113-B339XX-XXX

113-B339XX-XXX
VIDEO BIOS
FIRMWARE

3

GPIO_0 (17)
GPIO_1 (17)
GPIO_2 (17)

GPIO_3_SMBDATA (1)

GPIO_4_SMBCLK (1)

GPIO_6_TACH (16,17)

GPIO_8_R

RP1C33R RP1C33R

63

GPIO_9_R

RP1B33R RP1B33R

72

GPIO_10_R

RP1A33R RP1A33R

81

DNI DNI

GPIO_22_ROMCSb_R

RP1D33R RP1D33R

54

GPIO_7 (17)
GPIO_8_R (17)

GPIO_9_R (17)

GPIO_10_R (17)

HPD2 (9)
PWRCNTL_0 (15)

GPIO_17_ThermINT (17)
GPIO_19_CTF (16)

PWRCNTL_1 (15)

GPIO_22_ROMCSb_R (17)

GENERICA (7,17)

HPD1 (8)

BUO

2

R149 10KR149 10K

R152 10KR152 10K

R158 10KR158 10K

R161 10KR161 10K

R165 10KR165 10K

R176 10KR176 10K

PIN BASED STRAPS

V2SYNC (7)

V2SYNC

GPIO_9_R

GPIO_0

GPIO_0 (17)

GPIO_1

GPIO_1 (17)

GPIO_2

GPIO_2 (17)

GPIO_13
GPIO_12

GPIO_12
GPIO_11

V1SYNC (7)

V1SYNC

H1SYNC (7)

H1SYNC

GPIO_8_R

GPIO_5

GPIO_16

H2SYNC (7)

H2SYNC

GPIO_7

GPIO_7 (17)

+3.3V

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

1

VIP_DEVICE_STRAP_EN
0: No slave VIP host port devices reporting presence during reset (use
for configurations without video-in)
1:VIP host port devices present (use if Theater is populated)

VGA DISABLE : 1 for disable (set to 0 for normal operation)

GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)

GPIO(2) - BIF_GEN2_EN (5.0 GT/s Enable)
0 : Default. (Driver Controlled Gen2)
1 : Strap Controlled Gen2

GPIO(13, 12,11) - CONFIG[2..0]

100 - 512Kbit M25P05A (ST)
101 - 1Mbit M25P10A (ST)

CONFIG[2]

101 - 2Mbit M25P20 (ST)
101 - 4Mbit M25P40 (ST)

CONFIG[1]

101 - 8Mbit M25P80 (ST)
100 - 512Kbit Pm25LV512 (Chingis)

CONFIG[0]

101 - 1Mbit Pm25LV010 (Chingis)

AUD[0] : Enable HD Audio function in the PCI configuration space.
0 - Disable HD Audio
1 - Enable HD Audio
HD audio must only be enabled on systems that are legally
entitled. It is the responsibility of the system designer to
ensure that the system is entitled to support this feature.

AUD[1] : Enable on-board HDMI
Note: Board manufacturer must not set this strap to 1 unless
there is an onboard HDMI connector. It is the
manufacturers responsibility to pay royalties if this strap is
enabled.
This Board doesn't have HDMI Connector
therefore only pull down option is available

BIF_CLK_PM_EN
0 - Disable CLKREQ# power management capability
1 - Enable CLKREQ# power management capability

MEMORY CONFIG
GPIO_5:
0: Single Rank, 1: Dual Rank

RESERVED :Internal use only. Other logic must not affect this signal
during RESET.

ATI Board Feature I

1 - NTSC TVO0 - PAL TVO TV OUT STANDARD

PN 2280007900G for 1Mbit (PM25LV010A-100SCE)

GPIO_21

CrossFire Card-Edge

U1F

+1.8V

B113 BLM15BD121SN1B113 BLM15BD121SN1

B B

+1.8V

+1.8V

B110 BLM15BD121SN1B110 BLM15BD121SN1

NS6 NS_VIANS6 NS_VIA

1 2

+1.1V

B109 BLM15BD121SN1B109 BLM15BD121SN1

+1.8V

A A

NS7 NS_VIANS7 NS_VIA

+1.1V
+VDDC

B107 BLM15BD121SN1B107 BLM15BD121SN1

+1.8V +MPV18

+DPLL_PVDD

+DPLL_VDDC

1 2

5

+SPV18

+SPV10

C327

C327
1uF_6.3V

1uF_6.3V

C325

C325
10uF_X6S

10uF_X6S

VDDR4_5

C326

C326

C335

C335

100nF_6.3V

100nF_6.3V

1uF_6.3V

1uF_6.3V

C331

C331

C329

C329

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

TP84 35milTP84 35mil
TP85 35milTP85 35mil

TP86 35milTP86 35mil
TP87 35milTP87 35mil

TP88 35milTP88 35mil
TP89 35milTP89 35mil

R147 221RR147 221R
R151 110RR151 110R
C328 100nF_6.3VC328 100nF_6.3V

C147

C147

C148

C148

10uF_X6S

10uF_X6S

1uF_6.3V

1uF_6.3V

GND_DPLL_PVSS

C145

C145

1uF_6.3V

1uF_6.3V

GND_SPVSS

C150

C150

1uF_6.3V

1uF_6.3V

C330

C330
100nF_6.3V

100nF_6.3V

DVOCLK
DVPCNTL_0

DVPCNTL_1
DVPCNTL_2

DVP_MVP_CNTL_0
DVP_MVP_CNTL_1

VREFG

C149

C149

100nF_6.3V

100nF_6.3V

C146

C146

100nF_6.3V

100nF_6.3V

C151

C151

100nF_6.3V

100nF_6.3V

U1F

AD12

VDDR4#1

AF11

VDDR4#2

AF12

VDDR4#3

AG11

VDDR4#4

AF13

VDDR5#1

AF15

VDDR5#2

AG13

VDDR5#3

AG15

VDDR5#4

AR1

DVPCLK

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AH13

VREFG

RV730XT A12 HF MVE SLT B1

RV730XT A12 HF MVE SLT B1
U1G

U1G

AM32

DPLL_PVDD

AN32

DPLL_PVSS

AN31

DPLL_VDDC

AM10

NC_SPV18

AN10

SPVSS

AN9

SPV10

H7

NC_MPV18#1

H8

NC_MPV18#2

RV730XT A12 HF MVE SLT B1

RV730XT A12 HF MVE SLT B1

PART 6 OF 15

PART 6 OF 15

PART 7 OF 15

PART 7 OF 15

P

P
L

L
L

L
S

S

X

X
T

T
A

A
L

L

4

D

D
V

V
P

P

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11

DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

XTALOUT

XTALIN

CLKTESTA
CLKTESTB

AU34

AV33

AK10
AL10

DVPDATA_0

AU1

DVPDATA_1

AU3

DVPDATA_2

AW3

DVPDATA_3

AP6

DVPDATA_4

AW5

DVPDATA_5

AU5

DVPDATA_6

AR6

DVPDATA_7

AW6

DVPDATA_8

AU6

DVPDATA_9

AT7

DVPDATA_10

AV7

DVPDATA_11

AN7

DVPDATA_12

AV9

DVPDATA_13

AT9

DVPDATA_14

AR10

DVPDATA_15

AW10

DVPDATA_16

AU10

DVPDATA_17

AP10

DVPDATA_18

AV11

DVPDATA_19

AT11

DVPDATA_20

AR12

DVPDATA_21

AW12

DVPDATA_22

AU12

DVPDATA_23

AP12

XTALOUT

R86 0RR86 0R

R_RTCLK

XTALIN

R81 0RR81 0R

Place R_RTCLK close to XTAL so the
main clock line has shortest stub

CLKTESTA
CLKTESTB

TP6035mil TP6035mil
TP6135mil TP6135mil
TP6235mil TP6235mil
TP6335mil TP6335mil
TP6435mil TP6435mil
TP6535mil TP6535mil
TP6635mil TP6635mil
TP6735mil TP6735mil
TP6835mil TP6835mil
TP6935mil TP6935mil
TP7035mil TP7035mil
TP7135mil TP7135mil

TP7235mil TP7235mil
TP7335mil TP7335mil
TP7435mil TP7435mil
TP7535mil TP7535mil
TP7635mil TP7635mil
TP7735mil TP7735mil
TP7835mil TP7835mil
TP7935mil TP7935mil
TP8035mil TP8035mil
TP8135mil TP8135mil
TP8235mil TP8235mil
TP8335mil TP8335mil

XTALOUT_S

27.000MHz_10PPM

R841MR84

1M

27.000MHz_10PPM

XTALIN_S

3

C83

C83

15pF

15pF

21

Y82

Y82

C82

C82

15pF

15pF

Lower Cable Card Edge

DVPCNTL_2
DVPDATA_1
DVPDATA_3
DVPDATA_5
DVPDATA_7
DVPDATA_9
DVPDATA_11
DVPCNTL_1
GENERICD

or Bundle B or Bundle A (closer to the bracket)

PWR_GOOD

J8002J8002
1
3
5
7
9

11
13
15
17
19
21
23
25
27
29 30
31
33
35
37
39

2
4
6
8

DVPDATA_0

10
12

DVPDATA_2

14
16

DVPDATA_4

18
20

DVPDATA_6

22
24

DVPDATA_8

26
28

DVPDATA_10

32

DVPCNTL_0

34
36

GPIO_2

38
40

+1.8V

+3.3V_BUS

PWR_GOOD (1,14,15,16)

2

Upper Cable Card Edge

J8001J8001

1

DVP_MVP_CNTL_1DVOCLK
DVP_MVP_CNTL_0
DVPDATA_13
DVPDATA_15
DVPDATA_17
DVPDATA_19
DVPDATA_21
DVPDATA_23
GENERICB_R
GENERICC

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

RH RV730 GDDR3 DVII-TVO-DVII

3
5
7

9
11
13
15
17
19
21
23
25
27
29 30
31
33
35
37
39

2
4
6
8
10
12
14
16
18
20
22
24
26
28

32
34
36
38
40

DVPDATA_12
DVPDATA_14
DVPDATA_16
DVPDATA_18
DVPDATA_20
DVPDATA_22

GPIO_21_R

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Sheet

Sheet

Sheet

Do not install for BU

GENERICB: Generic I2C_SDA
DVALID: Generic I2C_SCL

Tuesday, September 02, 2008

Tuesday, September 02, 2008

Tuesday, September 02, 2008

of

619

of

619

of

619

1

Doc No.

Doc No.

Doc No.

GPIO_21
GENERICBGPIO_1

RevDate:

RevDate:

RevDate:

105-B709xx-11

105-B709xx-11

105-B709xx-11

50

50

50

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