MSI MS-v156 Schematic 0825

A B C D E F G H

P977-A01: G96, GB1-128, GDDR3, DL-DVI/VGA, DL-DVI/VGA, SD/HDTV

1

PAGE SUMMARY:

Page 1: TABLE OF CONTENTS
Page 2: PCI EXPRESS INTERFACE, PEX_VDD DECOUPLING CAPS
Page 3: FBA MEMORY INTERFACE, GPU NVVDD & FBVDDQ DECOUPLING CAPS
Page 4: FBA 16/32Mx32 GDDR3 MEMORIES, FBA COMMAND BUS PU'S, FBA CLK TERMS
Page 5: FBA MEMORY FBVDDQ DECOUPLING CAPS
Page 6: FBC MEMORY INTERFACE
Page 7: FBC 16/32MX32 GDDR3 MEMORIES, FBC CMD BUS PU'S, FBC CLK TERMS

2

Page 8: FBC MEMORY FBVDDQ DECOUPLING CAPS, GPU GND CONNECTIONS
Page 9: DACA FILTERS, DACA SYNC BUFFERS & DB15 SOUTH
Page 10: DACC FILTERS, DACC SYNC BUFFERS & DB15 MID
Page 11: TMDS LINK A/B, DVI CONNECTOR SOUTH
Page 12: TMDS LINK C/D, AC COUPLING, PD's, DVI CONNECTOR MID
Page 13: MIOA & MIOB, SLI CONNECTOR
Page 14: DACB FILTERS, MINIDIN CONNECTOR NORTH, SD/HD VIDEO OUTPUT CONNECTOR
Page 15: SPDIF-IN, XTAL, MECHANICALS, THERMALS
Page 16: EXTERNAL THERMAL SENSOR, 2/4PIN FAN CONTROL, GPIO, THERMAL PROTECTION
Page 17: BIOS ROM, HDCP ROM, STRAPPING OPTIONS

3

Page 18: POWER SUPPLY LINEARS: 5V, DDC5V, IFP PLLVDD, MIO VDD, TMDS_BACKDRIVE
Page 19: POWER SUPPLY: FBVDDQ , PEX_VDD
Page 20: POWER SUPPLY: NVVDD

REV HISTORY

Version : 0A

6/26 PAGE 16 add D701 for 4PIN FAN control protect
6/26 PAGE 12 DVI change to HDMI

add I2CD_SCL, I2CD_SDA
add GPIO17_HDMI_CMC
PAGE 14 disable DACB (TVfunction)

6/27 PAGE 20 change NVVDD power solution (UP6205)
6/30 PAGE 20 add GPIO5_VSEL0

PAGE 19 change FBVDD output choke footprint
add R1901 for RT9259A, add R1902 for UP6161
change Hi-Low side MOS from power pack to T0252

7/01 PAGE 19 change R511 from 0402 to 0603
change R515 to 100K ohm for 300Khz
change C558,C550 from 0603 to 0805, 25V
add R1903 for Hi-side GATE resistor

7/02 PAGE 16 add R1601,R1602,R1603 ,R1604 pull high resistor for I2CD (pull high 5V)
PAGE 17 add R1701 (no stuff), R1702(stuff), R1703(no stuff), R1704(no stuff), R1705(no stuff) pull down resistor for HDA
PAGE 18 change L5 footprint (12V input)

PAGE 16 add D1201,D1202 for protection diode (I2CD)
add LB1201, LB1202, C1201, C1202 for EMI filter
PAGE 20 change UGATE resister R7302,R7313 footprint to 0805

7/04 PAGE 11 add EMI bridge (R1101~R1107)
7/04 PAGE 11 add FM1 ~~ FM6 for optical point
7/09 PAGE 19 del output choke colay L17
change Q2 from T0252, PEX_VDD output CAP change to 1000 UF_DIP

7/09 PAGE 19 change L5 foot print to CHK_D2_P5

1

2

3

7/10 PAGE 15 add EM100~EM103 for EMI SPRING

Version : 10

8/22 PAGE 16 add R1216, R1217, R1218, R1219 bridge resistor for EMI

PAGE 19 del C113, add R1904 for UPI 6161 OCP resistor

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C GE

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

VARIANT ASSEMBLY

SKU

BASE

B

SKU0001

1
2

<UNDEFINED>

3

<UNDEFINED>

4

<UNDEFINED>

5

<UNDEFINED>

6

<UNDEFINED>

7

<UNDEFINED>

8

<UNDEFINED>

9

<UNDEFINED>

10

<UNDEFINED>

11

<UNDEFINED>

12

<UNDEFINED>
<UNDEFINED> <UNDEFINED>

13

<UNDEFINED>

14

<UNDEFINED>

15

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
TABLE OF CONTENTS

NVPN

600-10977-base-100
600-10977-0001-100
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>

<UNDEFINED>
<UNDEFINED>

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
G96-300, 550/800MHz 256MB 16Mx32 GDDR3 DVI+DVI+HDTV-Out
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10977-base-100 A

NAME

4

5

PAGEID
DATE

02-APR-2008

HFDBA

A B C D E F G H

16X PEX INTERFACE

CN2

CN2

CON_FINGER_PEX_164_B

CON_FINGER_PEX_164_B

CON_X16

CON_X16

COMMON

1

12V

3V3

SNN_3V3AUX

SNN_PE_PRSNT2_A

SNN_PE_RSVD2

2

SNN_PE_PRSNT2_B
SNN_PE_RSVD3
SNN_PE_RSVD4
SNN_PE_RSVD5

SNN_PE_PRSNT2_C
SNN_PE_RSVD6

3

PEX_PRSNT
SNN_PE_RSVD7
SNN_PE_RSVD8

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

COMMON

B1

+12V

B2

+12V

A2

+12V

A3

+12V

B3

+12V/RSVD

B8

+3V3

A9

+3V3

A10

+3V3

B10

+3V3AUX

A1

PRSNT1

B17

PRSNT2

B12

RSVD

B4

GND

A4

GND

B7

GND

A12

GND

B13

GND

A15

GND

B16

GND

B18

GND

A18

GND

GND

B31

PRSNT2

A19

RSVD

B30

RSVD

A32

RSVD

A20

GND

B21

GND

B22

GND

A23

GND

A24

GND

B25

GND

B26

GND

A27

GND

A28

GND

B29

GND

A31

GND

B32

GND

GND

B48

PRSNT2

A33

RSVD

A34

GND

B35

GND

B36

GND

A37

GND

A38

GND

B39

GND

B40

GND

A41

GND

A42

GND

B43

GND

B44

GND

A45

GND

A46

GND

B47

GND

B49

GND

A49

GND

GND

B81

PRSNT2

A50

RSVD

B82

RSVD

A51

GND

B52

GND

B53

GND

A54

GND

A55

GND

B56

GND

B57

GND

A58

GND

A59

GND

B60

GND

B61

GND

A62

GND

A63

GND

B64

GND

B65

GND

A66

GND

A67

GND

B68

GND

B69

GND

A70

GND

A71

GND

B72

GND

B73

GND

A74

GND

A75

GND

B76

GND

B77

GND

A78

GND

A79

GND

B80

GND

A82

GND

GND

END OF X1

END OF X1

END OF X4

END OF X4

END OF X8

END OF X8

END OF X16

END OF X16

TRST* JTAG1

TCLK JTAG2

TDI JTAG3
TDO JTAG4
TMS JTAG5

SMCLK
SMDAT

PERST

REFCLK
REFCLK

PERP0
PERN0

PETP0
PETN0

PERP1
PERN1

PETP1
PETN1

PERP2
PERN2

PETP2
PETN2

PERP3
PERN3

PETP3
PETN3

PERP4
PERN4

PETP4
PETN4

PERP5
PERN5

PETP5
PETN5

PERP6
PERN6

PETP6
PETN6

PERP7
PERN7

PETP7
PETN7

PERP8
PERN8

PETP8
PETN8

PERP9
PERN9

PETP9
PETN9

PERP10
PERN10

PETP10
PETN10

PERP11
PERN11

PETP11
PETN11

PERP12
PERN12

PETP12
PETN12

PERP13
PERN13

PETP13
PETN13

PERP14
PERN14

PETP14
PETN14

PERP15
PERN15

PETP15
PETN15

PEX_TRST*

B9

PEX_TCLK

A5

PEX_TDI

A6

PEX_TDO

A7

PEX_TMS

A8

PEX_SMCLK

B5

PEX_SMDAT

B6

SNN_PEX_WAKE*

B11

WAKE

A11

PEX_REFCLK

A13

PEX_REFCLK*

A14

PEX_TXX0

A16

PEX_TXX0*

A17

PEX_RX0

B14

PEX_RX0*

B15

PEX_TXX1

A21

PEX_TXX1*

A22

PEX_RX1

B19

PEX_RX1*

B20

PEX_TXX2

A25

PEX_TXX2*

A26

PEX_RX2

B23

PEX_RX2*

B24

PEX_TXX3

A29

PEX_TXX3*

A30

PEX_RX3

B27

PEX_RX3*

B28

PEX_TXX4

A35

PEX_TXX4*

A36

PEX_RX4

B33

PEX_RX4*

B34

PEX_TXX5

A39

PEX_TXX5*

A40

PEX_RX5

B37

PEX_RX5*

B38

PEX_TXX6

A43

PEX_TXX6*

A44

PEX_RX6

B41

PEX_RX6*

B42

PEX_TXX7

A47

PEX_TXX7*

A48

PEX_RX7

B45

PEX_RX7*

B46

PEX_TXX8

A52

PEX_TXX8*

A53

PEX_RX8

B50

PEX_RX8*

B51

PEX_TXX9

A56

PEX_TXX9*

A57

PEX_RX9

B54

PEX_RX9*

B55

PEX_TXX10

A60

PEX_TXX10*

A61

PEX_RX10

B58

PEX_RX10*

B59

PEX_TXX11

A64

PEX_TXX11*

A65

PEX_RX11

B62

PEX_RX11*

B63

PEX_TXX12

A68

PEX_TXX12*

A69

PEX_RX12

B66

PEX_RX12*

B67

PEX_TXX13

A72

PEX_TXX13*

A73

PEX_RX13

B70

PEX_RX13*

B71

PEX_TXX14

A76

PEX_TXX14*

A77

PEX_RX14

B74

PEX_RX14*

B75

PEX_TXX15

A80

PEX_TXX15*

A81

PEX_RX15

B78

PEX_RX15*

B79

R629

R629
0

0

5%

5%
0402

0402
COMMON

COMMON

R265%0

R265%0

R25

R25

0402

0402

OUT

COMMON X7R 10% 0402 16V

COMMON X7R 10% 0402 16V

COMMON X7R 040210%

COMMON X7R 040210%

COMMON X7R

COMMON X7R

X7R

X7R

COMMON

COMMON

X7R 16V

X7R 16V

COMMON 16V040210%X7R

COMMON 16V040210%X7R

COMMON 16V

COMMON 16V

COMMON 16V040210%X7R

COMMON 16V040210%X7R

R6185%0

R6185%0

JTAG_TRST*

0402 COMMON

0402 COMMON

R631 0

R631 0

R630

0402 COMMON

0402 COMMON

R627

R627

04020COMMON

04020COMMON

R625 0

R625 0

5%

5%

COMMON0402

COMMON0402

0

0

COMMON

COMMON

5%

5%

2,16,18

C729

C720 .1UF

C720 .1UF

0402COMMON X7R 10% 16V

0402COMMON X7R 10% 16V

C710

C704

C704

C693

C693

10% 0402 16V

10% 0402 16V

C684

C684

C675

C675

C654

C654

040210%X7RCOMMON

040210%X7RCOMMON

C642

C642

10%COMMON

10%COMMON

C627

C627

040210%COMMON

040210%COMMON

C609

C609

0402COMMON X7R 10%

0402COMMON X7R 10%

C597

C590

C590

040210%X7RCOMMON

040210%X7RCOMMON

C581

C581

040210%X7R

040210%X7R

C574

C574

040210%X7RCOMMON

040210%X7RCOMMON

C566 .1UF

C566 .1UF

5%

5%

5%

5%

5%

5%

COMMON0402

COMMON0402

.1UFC729

.1UF

.1UFC710

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UFC597

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

COMMON0402

COMMON0402

0R630

0

I2CS_SCL

16VCOMMON 10% 0402X7R

16VCOMMON 10% 0402X7R

16V

16V

16VCOMMON 040210%

16VCOMMON 040210%

16V040210%X7R

16V040210%X7R

16V

16V

16V0402X7R

16V0402X7R

16V

16V

16V

16V

16V

16V

I2CS_SDA

JTAG_TCLK

JTAG_TDI

JTAG_TDO

JTAG_TMS

NO STUFF
NO STUFF
NO STUFF
NO STUFF

NO STUFF

NO STUFF
NO STUFF

NO STUFF

R5645%200

R5645%200

COMMON0402

COMMON0402

C730

.1UF

C730

.1UF

0402 COMMONX7R

0402 COMMONX7R

C719

.1UF

C719

.1UF

0402

0402

C707

.1UFC707

.1UF

C701

.1UF

C701

.1UF

C689

.1UF

C689

.1UF

C681

.1UF

C681

.1UF

0402 16V 10%

0402 16V 10%

C667

.1UF

C667

.1UF

16V

16V

C652

.1UF

C652

.1UF

0402 10%

0402 10%

C636

.1UF

C636

.1UF

C622 .1UF

C622 .1UF

16V COMMON10% X7R0402

16V COMMON10% X7R0402

C608

.1UFC608

.1UF

0402 16V 10% COMMONX7R

0402 16V 10% COMMONX7R

C594

.1UFC594

.1UF

C587

.1UF

C587

.1UF

16V 10% X7R

16V 10% X7R

C578

.1UF

C578

.1UF

0402 16V

0402 16V

C573

.1UF

C573

.1UF

C565

.1UF

C565

.1UF

0402 16V

0402 16V

IN

BI

10%16V

10%16V

10% COMMON16V X7R

10% COMMON16V X7R

10%16V COMMONX7R0402

10%16V COMMONX7R0402

10%

10%

10%16V

10%16V

10% COMMON0402 16V

10% COMMON0402 16V

10%0402 16V COMMONX7R

10%0402 16V COMMONX7R

10% COMMONX7R

10% COMMONX7R

10%0402 16V

10%0402 16V

10% COMMONX7R

10% COMMONX7R

IN

IN

IN

OUT

IN

16

16

PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*

COMMONX7R16V0402

COMMONX7R16V0402

COMMONX7R0402

COMMONX7R0402

X7R COMMON

X7R COMMON

X7R0402 10% COMMON

X7R0402 10% COMMON

COMMON16V X7R

COMMON16V X7R

X7R

X7R

COMMON0402

COMMON0402

COMMONX7R

COMMONX7R

16

16

16

16

16

PEX_RST*

SNN_PEX_CLKREQ*

PEX_TX0*

PEX_TX1*

PEX_TX2*

PEX_TX3*

PEX_TX4*

PEX_TX5*

PEX_TX6*

PEX_TX7*

PEX_TX8*

PEX_TX9*

PEX_TX10*

PEX_TX11*

PEX_TX12*

PEX_TX13*

PEX_TX14*

PEX_TX15*

PEX_TX0

PEX_TX1

PEX_TX2

PEX_TX3

PEX_TX4

PEX_TX5

PEX_TX6

PEX_TX7

PEX_TX8

PEX_TX9

PEX_TX10

PEX_TX11

PEX_TX12

PEX_TX13

PEX_TX14

PEX_TX15

AM16
AR13

AJ17
AJ18

AR16
AR17

AL17
AM17

AP17
AN17

AM18
AM19

AN19
AP19

AL19
AK19

AR19
AR20

AL20
AM20

AP20
AN20

AM21
AM22

AN22
AP22

AL22
AK22

AR22
AR23

AL23
AM23

AP23
AN23

AM24
AM25

AN25
AP25

AL25
AK25

AR25
AR26

AL26
AM26

AP26
AN26

AM27
AM28

AN28
AP28

AL28
AK28

AR28
AR29

AK29
AL29

AP29
AN29

AM29
AM30

AN31
AP31

AM31
AM32

AR31
AR32

AN32
AP32

AR34
AP34

C GE

G1A

G1A

BGA_0969_P080_290X290

BGA_0969_P080_290X290
COMMON

COMMON

1/16 PCI_EXPRESS

1/16 PCI_EXPRESS

PEX_RST

PEX_CLKREQ

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT

PEX_REFCLK
PEX_REFCLK

PEX_TX0
PEX_TX0

PEX_RX0
PEX_RX0

PEX_TX1
PEX_TX1

PEX_RX1
PEX_RX1

PEX_TX2
PEX_TX2

PEX_RX2
PEX_RX2

PEX_TX3
PEX_TX3

PEX_RX3
PEX_RX3

PEX_TX4
PEX_TX4

PEX_RX4
PEX_RX4

PEX_TX5
PEX_TX5

PEX_RX5
PEX_RX5

PEX_TX6
PEX_TX6

PEX_RX6
PEX_RX6

PEX_TX7
PEX_TX7

PEX_RX7
PEX_RX7

PEX_TX8
PEX_TX8

PEX_RX8
PEX_RX8

PEX_TX9
PEX_TX9

PEX_RX9
PEX_RX9

PEX_TX10
PEX_TX10

PEX_RX10
PEX_RX10

PEX_TX11
PEX_TX11

PEX_RX11
PEX_RX11

PEX_TX12
PEX_TX12

PEX_RX12
PEX_RX12

PEX_TX13
PEX_TX13

PEX_RX13
PEX_RX13

PEX_TX14
PEX_TX14

PEX_RX14
PEX_RX14

PEX_TX15
PEX_TX15

PEX_RX15
PEX_RX15

ASSEMBLY
PAGE DETAIL

Place near balls

600mA

C626

C626

C620

C620

.1UF

.1UF

.1UF

.1UF

16V

16V

16V

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

AK16
AK17
AK21
AK24
AK27

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24

AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

2A

10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C648

C648
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

Place near balls

C616

C616
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

Place Close to PEX fingers

3V3

12V

SNN_NC<1>

A2

NC_1

SNN_NC<2>

AB7

NC_2

SNN_NC<3>

AD6

NC_3

SNN_NC<4>

AF6

NC_4

SNN_NC<5>

AG6

NC_5

SNN_NC<6>

AJ5

NC_6

SNN_NC<7>

AK15

NC_7

SNN_NC<8>

AL7

NC_8

SNN_NC<9>

D35

NC_9

SNN_NC<10>

E35

NC_10

SNN_NC<11>

E7

NC_11

SNN_NC<12>

F7

NC_12

SNN_NC<13>

H32

NC_13

SNN_NC<14>

M7

NC_14

SNN_NC<15>

P6

NC_15

SNN_NC<16>

P7

NC_16

SNN_NC<17>

R7

NC_17

SNN_NC<18>

U7

NC_18

SNN_NC<19>

V6

NC_19

Place near balls

GND

R562

1%

1%

R551

0402

0402

5%

5%

Place near balls

2,20

OUT

120mA

C660

C660

C659

C659

.1UF

.1UF

1UF

1UF

6.3V

6.3V

16V

16V
10%

10%

10%

10%

X7R

X7R

X5R

X5R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

2.49KR562

2.49K

COMMON0402

COMMON0402

10KR551

10K

COMMON

COMMON

J10

VDD33_1

J11

VDD33_2

J12

VDD33_3

J13

VDD33_4

J9

VDD33_5

NVVDD_SENSE

AD20

VDD_SENSE

AD19

GND_SENSE

GND

PEX_PLLVDD

AG14

PEX_PLLVDD

SNN_PEX_RFU1

AG19

PEX_RFU1

PEX_RFU2

PEX_TERMP

TESTMODE

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PCI EXPRESS INTERFACE, PEX_VDD DECOUPLING CAPS

SNN_PEX_RFU2

AG20

PEX_TERMP

AG21

GPU_TESTMODE

AP35

C52

C52
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C736

C736
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C655

C655
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C641

C641
1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C637

C637
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

C657

C657

4.7UF

4.7UF

6.3V

6.3V
X5R

X5R
0603

0603
COMMON

COMMON

C663

C663
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C643

C643

C634

C634

C95

1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

C95

4.7UF

4.7UF

6.3V 10%

6.3V 10%
X5R

X5R
0603

0603
COMMON

COMMON

1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

Place Close to GPU

Place Close to GPU

C610

C53

C53
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C50

C50
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C610
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

C92

C92

4.7UF

4.7UF

6.3V

10%

6.3V

10%

X5R

X5R
0603

0603
COMMON

COMMON

C55

C55
10UF

10UF

16V

16V
10%

10%
X5R

X5R
1206

1206
COMMON

COMMON

GND

C49

C49
10UF

10UF

16V

16V
10%

10%
X5R

X5R
1206

1206
COMMON

COMMON

GND

3V3

GND

Place Near BGA

LB502 10nH

LB502 10nH

COMMON0603

20%

20%

COMMON0603

GND

C699

C699
1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C90

C90
10UF

10UF

10V

10V
X5R

X5R
0805

0805
COMMON

COMMON

PEX_VDD

10%

10%

C93

C93
10UF

10UF

10V 10%

10V 10%
X5R

X5R
0805

0805
COMMON

COMMON

PEX_VDD

GND

PEX_VDD

GND

BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

2,20

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

NAME

NET NV_CRITICALNV_IMPEDANCE

PEX_REFCLK
PEX_REFCLK*

PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*

PEX_TXX0
PEX_TXX0*
PEX_TXX1
PEX_TXX1*
PEX_TXX2
PEX_TXX2*
PEX_TXX3
PEX_TXX3*
PEX_TXX4
PEX_TXX4*
PEX_TXX5
PEX_TXX5*
PEX_TXX6
PEX_TXX6*
PEX_TXX7
PEX_TXX7*
PEX_TXX8
PEX_TXX8*
PEX_TXX9
PEX_TXX9*
PEX_TXX10
PEX_TXX10*
PEX_TXX11
PEX_TXX11*
PEX_TXX12
PEX_TXX12*
PEX_TXX13
PEX_TXX13*
PEX_TXX14
PEX_TXX14*
PEX_TXX15
PEX_TXX15*

PEX_RX0
PEX_RX0*
PEX_RX1
PEX_RX1*
PEX_RX2
PEX_RX2*
PEX_RX3
PEX_RX3*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_RX14
PEX_RX14*
PEX_RX15
PEX_RX15*

NVVDD_SENSE

BI

NVVDD_GND_SENSE

BI

PEX_PLLVDD

BI

3V3

3V3

12V

12V

600-10977-base-100 A

DIFFPAIR

PEX_REFCLK 100DIFF 1
PEX_REFCLK 100DIFF 1

90DIFFPEX_TX0 1
90DIFF 1PEX_TX0

PEX_TX1 190DIFF

90DIFFPEX_TX3 1

90DIFF 1PEX_TX11

90DIFF 1PEX_TXX0
90DIFF 1PEX_TXX1
90DIFF 1PEX_TXX1
90DIFF 1PEX_TXX2
90DIFF 1PEX_TXX2

PEX_TXX3 90DIFF 1

90DIFF 1PEX_TXX3
90DIFF 1PEX_TXX4
90DIFF 1PEX_TXX4

PEX_TXX5 190DIFF
PEX_TXX6 190DIFF

PEX_TXX7 190DIFF

PEX_TXX8 190DIFF
PEX_TXX8 190DIFF

90DIFFPEX_TXX9 1

PEX_TXX10 190DIFF

90DIFFPEX_TXX10 1
PEX_TXX11 190DIFF
PEX_TXX11 90DIFF 1

90DIFFPEX_TXX12 1
PEX_TXX12 90DIFF 1

90DIFF 1PEX_TXX13
PEX_TXX13 90DIFF 1
PEX_TXX14 90DIFF 1
PEX_TXX14 190DIFF
PEX_TXX15 190DIFF
PEX_TXX15 190DIFF

90DIFF 1PEX_RX0

90DIFFPEX_RX0 1

90DIFF 1PEX_RX1

PEX_RX5 190DIFF
PEX_RX6 190DIFF
PEX_RX6 190DIFF
PEX_RX7 190DIFF
PEX_RX7 190DIFF
PEX_RX8 190DIFF
PEX_RX8 190DIFF
PEX_RX9 190DIFF
PEX_RX9 190DIFF
PEX_RX10 190DIFF

90DIFFPEX_RX10 1

90DIFFPEX_RX11 1

90DIFFPEX_RX11 1

90DIFFPEX_RX12 1

PEX_RX13 90DIFF 1

90DIFFPEX_RX13 1

MIN_LINE_WIDTH

VOLTAGE

PAGEID
DATE

02-APR-2008

HFDBA

190DIFFPEX_TX1
190DIFFPEX_TX2
190DIFFPEX_TX2

190DIFFPEX_TX3
1PEX_TX4 90DIFF
1PEX_TX4 90DIFF
190DIFFPEX_TX5
190DIFFPEX_TX5
190DIFFPEX_TX6
190DIFFPEX_TX6
190DIFFPEX_TX7
190DIFFPEX_TX7
190DIFFPEX_TX8
190DIFFPEX_TX8
190DIFFPEX_TX9
190DIFFPEX_TX9
190DIFFPEX_TX10
190DIFFPEX_TX10

190DIFFPEX_TX11
190DIFFPEX_TX12
190DIFFPEX_TX12
190DIFFPEX_TX13
190DIFFPEX_TX13
190DIFFPEX_TX14
190DIFFPEX_TX14
190DIFFPEX_TX15
190DIFFPEX_TX15

190DIFFPEX_TXX0

190DIFFPEX_TXX5

190DIFFPEX_TXX6

190DIFFPEX_TXX7

190DIFFPEX_TXX9

190DIFFPEX_RX1
190DIFFPEX_RX2
190DIFFPEX_RX2
190DIFFPEX_RX3
190DIFFPEX_RX3
190DIFFPEX_RX4
190DIFFPEX_RX4
190DIFFPEX_RX5

190DIFFPEX_RX12

190DIFFPEX_RX14
1PEX_RX14 90DIFF
1PEX_RX15 90DIFF
190DIFFPEX_RX15

1.2V
0V

1.2V10MIL

3.3V 3.5A16MIL
12V12MIL 5.5A

1

2

3

4

5

www.vinafix.vn

A B C D E F G H

G1B

G1B

BGA_0969_P080_290X290

BGA_0969_P080_290X290
COMMON

4,4

FBA_D[63..0]

BI

1

2

OUT

BI

BI

VREF = 0.70 * FBVDDQ

FBA_DQM[7..0]

FBA_DQS_WP[7..0]

FBA_DQS_RN[7..0]

SNN_FBA_WDS0
SNN_FBA_WDS0*
SNN_FBA_WDS1
SNN_FBA_WDS1*
SNN_FBA_WDS2
SNN_FBA_WDS2*
SNN_FBA_WDS3
SNN_FBA_WDS3*

FBA_VREF

COMMON

COMMON

1%

1%

0402

0402

COMMON

COMMON

1%

1%

0402

0402

4,4

4,4

4,4

C611

C611
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

VREF = FBVDDQ * Rbot/(Rtop + Rbot)

3

4

FBVDDQ

Rtop

R555 549

R555 549

1.33K

1.33K

Rbot

R559

R559

GND

COMMON

2/16 FBA

2/16 FBA

FBA_D0

0

R30

FBA_D0

FBA_D1

1

R32

FBA_D1

FBA_D2

2

P31

FBA_D2

FBA_D3

3

N30

FBA_D3

FBA_D4

4

L31

FBA_D4

FBA_D5

5

M32

FBA_D5

FBA_D6

6

M30

FBA_D6

FBA_D7

7

L30

FBA_D7

FBA_D8

8

P33

FBA_D8

FBA_D9

9

P34

FBA_D9

FBA_D10

10

N35

FBA_D10

FBA_D11

11

P35

FBA_D11

FBA_D12

12

N34

FBA_D12

FBA_D13

13

L33

FBA_D13

FBA_D14

14

L32

FBA_D14

FBA_D15

15

N33

FBA_D15

FBA_D16

16

K31

FBA_D16

FBA_D17

17

K30

FBA_D17

FBA_D18

18

G30

FBA_D18

FBA_D19

19

K32

FBA_D19

FBA_D20

20

G32

FBA_D20

FBA_D21

21

H30

FBA_D21

FBA_D22

22

F30

FBA_D22

FBA_D23

23

G31

FBA_D23

FBA_D24

24

H33

FBA_D24

FBA_D25

25

K35

FBA_D25

FBA_D26

26

K33

FBA_D26

FBA_D27

27

G34

FBA_D27

FBA_D28

28

K34

FBA_D28

FBA_D29

29

E33

FBA_D29

FBA_D30

30

E34

FBA_D30

FBA_D31

31

G33

FBA_D31

FBA_D32

32

AG30

FBA_D32

FBA_D33

33

AH31

FBA_D33

FBA_D34

34

AG32

FBA_D34

FBA_D35

35

AF31

FBA_D35

FBA_D36

36

AF30

FBA_D36

FBA_D37

37

AD30

FBA_D37

FBA_D38

38

AC32

FBA_D38

FBA_D39

39

AE30

FBA_D39

FBA_D40

40

AE32

FBA_D40

FBA_D41

41

AF33

FBA_D41

FBA_D42

42

AF34

FBA_D42

FBA_D43

43

AE35

FBA_D43

FBA_D44

44

AE33

FBA_D44

FBA_D45

45

AE34

FBA_D45

FBA_D46

46

AC35

FBA_D46

FBA_D47

47

AB32

FBA_D47

FBA_D48

48

AN33

FBA_D48

FBA_D49

49

AK32

FBA_D49

FBA_D50

50

AL33

FBA_D50

FBA_D51

51

AM33

FBA_D51

FBA_D52

52

AL31

FBA_D52

FBA_D53

53

AK30

FBA_D53

FBA_D54

54

AJ30

FBA_D54

FBA_D55

55

AH30

FBA_D55

FBA_D56

56

AM35

FBA_D56

FBA_D57

57

AH33

FBA_D57

FBA_D58

58

AH35

FBA_D58

FBA_D59

59

AH32

FBA_D59

FBA_D60

60

AH34

FBA_D60

FBA_D61

61

AM34

FBA_D61

FBA_D62

62

AL35

FBA_D62

FBA_D63

63

AJ33

FBA_D63

FBA_DQM0

0

P30

FBA_DQM0

FBA_DQM1

1

P32

FBA_DQM1

FBA_DQM2

2

J30

FBA_DQM2

FBA_DQM3

3

H34

FBA_DQM3

FBA_DQM4

4

AF32

FBA_DQM4

FBA_DQM5

5

AF35

FBA_DQM5

FBA_DQM6

6

AL32

FBA_DQM6

FBA_DQM7

7

AL34

FBA_DQM7

FBA_DQS_WP0

0

N31

FBA_DQS_WP0

FBA_DQS_WP1

1

L34

FBA_DQS_WP1

FBA_DQS_WP2

2

J32

FBA_DQS_WP2

FBA_DQS_WP3

3

H35

FBA_DQS_WP3

FBA_DQS_WP4

4

AE31

FBA_DQS_WP4

FBA_DQS_WP5

5

AC33

FBA_DQS_WP5

FBA_DQS_WP6

6

AJ32

FBA_DQS_WP6

FBA_DQS_WP7

7

AJ34

FBA_DQS_WP7

FBA_DQS_RN0

0

N32

FBA_DQS_RN0

FBA_DQS_RN1

1

L35

FBA_DQS_RN1

FBA_DQS_RN2

2

H31

FBA_DQS_RN2

FBA_DQS_RN3

3

G35

FBA_DQS_RN3

FBA_DQS_RN4

4

AD32

FBA_DQS_RN4

FBA_DQS_RN5

5

AC34

FBA_DQS_RN5

FBA_DQS_RN6

6

AJ31

FBA_DQS_RN6

FBA_DQS_RN7

7

AJ35

FBA_DQS_RN7

P29

RFU

R29

RFU

L29

RFU

M29

RFU

AD29

RFU

AE29

RFU

AG29

RFU

AH29

RFU

J27

FB_VREF

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

FBA_DEBUG

FB_DLLAVDD
FB_PLLAVDD

J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22

FBA_CMD[27..0]

FBA_CMD0

0

V32

FBA_CMD1

1

W31

FBA_CMD2

2

U31

FBA_CMD3

3

Y32

FBA_CMD4

4

AB35

FBA_CMD5

5

AB34

FBA_CMD6

6

W35

SNN_FBA_CMD7

W33

FBA_CMD8

8

W30

FBA_CMD9

9

T34

FBA_CMD10

10

T35

FBA_CMD11

11

AB31

FBA_CMD12

12

Y30

FBA_CMD13

13

Y34

FBA_CMD14

14

W32

FBA_CMD15

15

AA30

FBA_CMD16

16

AA32

FBA_CMD17

17

Y33

FBA_CMD18

18

U32

FBA_CMD19

19

Y31

FBA_CMD20

20

U34

FBA_CMD21

21

Y35

FBA_CMD22

22

W34

FBA_CMD23

23

V30

FBA_CMD24

24

U35

FBA_CMD25

25

U30

SNN_FBA_CMD26

U33

FBA_CMD27

27

AB30

SNN_FBA_CMD28

AB33

SNN_FBA_CMD29

T33

SNN_FBA_CMD30

W29

FBA_CLK0

T32

FBA_CLK0*

T31

FBA_CLK1

AC31

FBA_CLK1*

AC30

T30

AG27
AF27

FBA_DEBUG

NO STUFF

R554

R554

0402

0402

OUT

C651

C651
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C628

C628
.47UF

.47UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

1%

1%

3,6

FB_PLLAVDD

OUT
OUT
OUT
OUT

60.4

60.4

COMMON

COMMON

OUT

4,4
4,4
4,4
4,4

C600

C600
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C632

C632
.47UF

.47UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

4,4,4,4

FBVDDQ

PLACE close to GPU

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C GE

PLACE BELOW GPU

C666

C666

C647

C647
.1UF

.1UF

.1UF

.1UF

16V

16V

16V

16V
10%

10%

10%

10%
X7R

X7R

X7R

X7R
0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

C605

C605

C124

C124

C598

.47UF

.47UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C598
.47UF

.47UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

.47UF

.47UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

FBVDDQ below GPU:

4x 100nf 0402
6x 470nf 0402

FBVDDQ

C563

C563

C570

C570

10UF

10UF

10UF

10UF

10V

10V

10V

10V

10%

10%

10%

10%

X5R

X5R

X5R

X5R

0805

0805

0805

0805
COMMON

COMMON

COMMON

COMMON

PLACE MIDWAY BETWEEN GPU AND MEMORY

C606

C606

C601

C601

C602

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

ASSEMBLY
PAGE DETAIL

C602

.1UF

.1UF

1UF

1UF

16V

16V

6.3V

6.3V

10%

10%

10%

10%
X5R

X5R

X7R

X7R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

GND

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA MEMORY INTERFACE, GPU NVVDD & FBVDDQ DECOUPLING CAPS

C640

C640
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

GND

C603

C603
.47UF

.47UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C107

C107
10UF

10UF

10V

10V
10%

10%
X5R

X5R
0805

0805
COMMON

COMMON

C584

C584
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

2x 1uf 0603
2x 4.7uf 0603

GND

LB501

LB501

L0402

L0402

C604

C604

4.7UF

4.7UF

6.3V

6.3V
20%

20%
X5R

X5R
0603

0603
COMMON

COMMON

C583

C583
10UF

10UF

10V

10V
10%

10%
X5R

X5R
0805

0805
COMMON

COMMON

120R@100MHz

120R@100MHz

COMMON

COMMON

GND

PEX_VDD

C619

C619

4.7UF

4.7UF

6.3V

6.3V
20%

20%
X5R

X5R
0603

0603
COMMON

COMMON

Near GPU

FBVDDQ

C575

C575
22UF

22UF

6.3V

6.3V
20%

20%
X5R

X5R
1206

1206
COMMON

COMMON

NET

FBA_VREF

BI

BI

FB_PLLAVDD

NVVDD below GPU:

5x 22nf 0402 X7R
5x 100nf 0402 X5R
6x 1uf 0402 X5R
2x 4.7uf 0603 X5R

3,6

NVVDD

Place below GPU

C644

C644

C631

1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C653

C653
.022UF

.022UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C639

C639
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C731

C731
10UF

10UF

10V

10V
10%

10%
X5R

X5R
0805

0805
COMMON

COMMON

C631
1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C630

C630
.022UF

.022UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C617

C617
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C84

C84
10UF

10UF

10V

10V
10%

10%
X5R

X5R
0805

0805
COMMON

COMMON

C645

C645
1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C656

C656
.022UF

.022UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C623

C623
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

NVVDD

C725

C725
10UF

10UF

10V

10V
10%

10%
X5R

X5R
0805

0805
COMMON

COMMON

Place near GPU

G1C

G1C

NVVDD NVVDD

BGA_0969_P080_290X290

BGA_0969_P080_290X290
COMMON

COMMON

16/16 NVVDD

16/16 NVVDD

AB11

VDD

AB13

VDD

AB15

VDD

AB17

VDD

AB19

VDD

AB21

VDD

AB23

VDD

AB25

VDD

AC11

VDD

AC12

VDD

AC13

VDD

AC14

VDD

AC15

VDD

AC16

VDD

AC17

VDD

AC18

VDD

AC19

VDD

AC20

VDD

AC21

VDD

AC22

VDD

AC23

VDD

AC24

VDD

AC25

VDD

AD12

VDD

AD14

VDD

AD16

VDD

AD18

VDD

AD22

VDD

AD24

VDD

L11

VDD

L12

VDD

L13

VDD

L14

VDD

L15

VDD

L16

VDD

L17

VDD

L18

VDD

L19

VDD

L20

VDD

L21

VDD

L22

VDD

L23

VDD

L24

VDD

L25

VDD

M12

VDD

M14

VDD

M16

VDD

M18

VDD

M20

VDD

M22

VDD

M24

VDD

P11

VDD

P13

VDD

P15

VDD

P17

VDD

P19

VDD

C624

C624
1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C638

C638
.022UF

.022UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C613

C613
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

VOLTAGEMIN_LINE_WIDTH

C70

C70
10UF

10UF

10V

10V
10%

10%
X5R

X5R
0805

0805
COMMON

COMMON

8MIL

C614

C614
1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C646

C646
.022UF

.022UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C649

C649
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C77

C77
10UF

10UF

10V

10V
10%

10%
X5R

X5R
0805

0805
COMMON

COMMON

C615

C615
1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C621

C621
.022UF

.022UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C618

C618
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C54

C54
10UF

10UF

10V

10V
10%

10%
X5R

X5R
0805

0805
COMMON

COMMON

1.2V10MIL

C625

C625
1UF

1UF

6.3V

6.3V
10%

10%
X5R

X5R
0402

0402
COMMON

COMMON

C612

C612

4.7UF

4.7UF

6.3V

6.3V
20%

20%
X5R

X5R
0603

0603
COMMON

COMMON

C650

C650

4.7UF

4.7UF

6.3V

6.3V
20%

20%
X5R

X5R
0603

0603
COMMON

COMMON

1

2

GND

GND

3

P21

VDD

P23

VDD

P25

VDD

R11

VDD

R12

VDD

R13

VDD

R14

VDD

R15

VDD

R16

VDD

R17

VDD

R18

VDD

R19

VDD

R20

VDD

R21

VDD

R22

VDD

R23

VDD

R24

VDD

R25

VDD

T12

VDD

T14

VDD

T16

VDD

T18

VDD

T20

VDD

T22

VDD

T24

VDD

V11

VDD

V13

VDD

V15

VDD

V17

VDD

V19

VDD

V21

VDD

V23

VDD

V25

VDD

W11

VDD

W12

VDD

W13

VDD

W14

VDD

W15

VDD

W16

VDD

W17

VDD

W18

VDD

W19

VDD

W20

VDD

W21

VDD

W22

VDD

W23

VDD

W24

VDD

W25

VDD

Y12

VDD

Y14

VDD

Y16

VDD

Y18

VDD

Y20

VDD

Y22

VDD

Y24

VDD

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10977-base-100 A

NAME

PAGEID
DATE

02-APR-2008

HFDBA

4

5

www.vinafix.vn

A B C D E F G H

FrameBuffer: Partition A 16/32Mx32 BGA136 GDDR3

FB_A-CS0-LOW-32bit

M3E

M3E

BGA_0136_P080_140X120

FBA_CMD[27..0]

3,4,4,4

IN

1

Low Sub-Partition

FBA_CLK0

3,4

IN

FBA_CLK0*

3,4

IN

2

FOR QIMONDA RSEN= 1K
FOR OTHERS RSEN= 0OHM

R526

R526
1K

1K

5%

5%

FBA_CMD18

0402

0402

R67

R67

COMMON

COMMON

10K

10K

5%

5%
0402

0402
COMMON

COMMON

GND

FBVDDQ

3

FBA_CMD1

1

FBA_CMD10

10

FBA_CMD11

11

FBA_CMD8

8

CS0

FBA_CMD19

19

FBA_CMD25

25
22

FBA_CMD24

24

FBA_CMD0

0

FBA_CMD2

2

FBA_CMD21

21

FBA_CMD16

16

FBA_CMD23

23

FBA_CMD20

20

FBA_CMD17

17

FBA_CMD9

9

FBA_CMD12

12

FBA_CMD3

3

FBA_CMD27

27

FBA_CMD18

18

SNN_FBA0_NC1 SNN_FBA1_NC1

FBA_CMD14 FBA_CMD14

14

FBA_DEBUG_SEN0 FBA_DEBUG_SEN1

FBA_CMD15 FBA_CMD15

15

FBA_CMD15

R65

R65
10K

10K

5%

5%
0402

0402
COMMON

COMMON

GND GND

C506

C506
.047UF

.047UF

C532

C532
.047UF

.047UF

16V

16V
10%

10%

16V

16V

X7R

X7R

10%

10%

0402

0402

X7R

X7R

COMMON

COMMON

0402

0402
COMMON

COMMON

GND

3,4

BI

3,4

BI

3,4

BI

3,4

BI

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

H3

RAS BA2

F4

CAS CS

H9

WE CKE

F9

CS CAS

K4

A0 A4

H2

A1 A5

K3

A2 A6

M4

K9
H11
K10

L9

K11

M9

K2

L4

G4

G9
H10

H4

J11

J10

J2
J3

V4

V9

A9

FBA_ZQ0 FBA_ZQ1

A4

R68

R68
243

243

1%

1%
0402

0402
COMMON

COMMON

K1
K12

J1

J12

FBA_D[63..0]
FBA_DQM[7..0]
FBA_DQS_RN[7..0]
FBA_DQS_WP[7..0]

A4 A0

A8/AP A10
A9 A3
A10 A8/AP
A11 A7

BA0

CKE WE
CLK
CLK

NC/RFU

SEN (GND)

NONMIRROR

NONMIRROR

RESET

MIRROR

ZQ

VDDA
VDDA

VSSA
VSSA

*CS1 is required 32Mx32 Memories

*CS1 is required 32Mx32 Memories

NC/CS1NC/CS1

MIRROR

MIRROR

A9A3

A1A5
A2A6
A11A7

BA1
BA0BA1
RASBA2

4

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3

0

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3

0

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3

0

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

FBA_DQM4 FBA_DQM5 FBA_DQM6

4

FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6

4

FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6

4

FBVDDQ

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

G12

VSS

L12

VSS

FBA_VREF0

H1

VREF

FBA_VREF1

H12

VREF

VREF = 0.70 * FBVDDQ

DDR3:

VREF = FBVDDQ * R2/(R1 + R2)

M3A

M3A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

FBA_D0

0

L10

DQ0

FBA_D1

1

M10

DQ1

FBA_D2

2

M11

DQ2

FBA_D3

3

N11

DQ3

FBA_D4

4

R11

DQ4

FBA_D5

5

R10

DQ5

FBA_D6

6

T10

DQ6

FBA_D7

7

T11

DQ7

N10

DQM

P10

RDQS

P11

WDQS

M4E

M4E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

FBA_D32

32

R2

DQ0

FBA_D33

33

R3

DQ1

FBA_D34

34

T3

DQ2

FBA_D35

35

T2

DQ3

FBA_D36

36

L3

DQ4

FBA_D37

37

M3

DQ5

FBA_D38

38

N2

DQ6

FBA_D39

39

M2

DQ7

N3

DQM

P3

RDQS

P2

WDQS

GND

FBA Partition

136BGA CMD Mapping

CMD

ADDR

CMD1 RAS*

CMD10

CAS*

CMD11

WE*

CMD18

CKE

CMD15

RESET/ODT

CMD8

CS0*

CMD19

A<0>

CMD25

A<1>

CMD22

A<2>

CMD24

A<3>

CMD0

A<4>

CMD2

A<5>

A<2>

CMD4

A<3>

CMD6
CMD5

A<4>

CMD13

A<5>

CMD21

A<6>

CMD16

A<7>

CMD23

A<8>

CMD20

A<9>

CMD17

A<10

CMD9

A<11>

CMD14

A<12>

CMD12

BA0
BA1

CMD3

CMD27

BA2

FBVDDQ

R504

R504

549

549

R1

1%

1%

0402

0402

COMMON

COMMON

R505

R505

1.33K

1.33K

R2

1%

1%

0402

0402

COMMON

COMMON

GND

8
9
10
11
12
13
14
15

1

1

1

40
41
42
43
44
45
46
47

5

5

5

FBA_D8

FBA_D9

FBA_D10

FBA_D11

FBA_D12

FBA_D13

FBA_D14

FBA_D15

FBA_D40

FBA_D41

FBA_D42

FBA_D43

FBA_D44

FBA_D45

FBA_D46

FBA_D47

Low Sub-Partition

Hi Sub-Partition

C520

C520
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C10
B10
E11
B11

F10

F11
G10
C11

E10
D10
D11

R532

R532

COMMON

COMMON

R534

R534

1.33K

1.33K

COMMON

COMMON

M3B

M3B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M4A

M4A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

G3

DQ0

B3

DQ1

C3

DQ2

F3

DQ3

E2

DQ4

F2

DQ5

C2

DQ6

B2

DQ7

E3

DQM

D3

RDQS

D2

WDQS

FBVDDQ

549

549

1%

1%

0402

0402

1%

1%

0402

0402

GND

FOR QIMONDA RSEN= 1K
FOR OTHERS RSEN= 0OHM

R1

R2

C GE

C551

C551
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

3,4,4,4

Hi Sub-Partition

ASSEMBLY
PAGE DETAIL

FB_A-CS0-HI-32bit

M4C

M4C

BGA_0136_P080_140X120

FBA_CMD[27..0]

IN

3,4

IN

3,4

IN

FBVDDQ

R530

R530
1K

1K

5%

5%
0402

0402
COMMON

COMMON

GND

FBVDDQ

FBA_D16

16

R2

FBA_D17

17

T3

FBA_D18

18

N2

FBA_D19

19

T2

FBA_D20

20

M2

FBA_D21

21

R3

FBA_D22

22

FBA_D23

23

M3

2

2

2

FBA_D48

48

L10

FBA_D49

49

R11

FBA_D50

50

M11

FBA_D51

51

N11

FBA_D52

52

M10

FBA_D53

53

T10

FBA_D54

54

T11

FBA_D55

55

R10

6

N10

6

6

P10
P11

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA 16/32Mx32 GDDR3 MEMORIES, FBA COMMAND BUS PU'S, FBA CLK TERMS

C537

C537
.047UF

.047UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

GND

M3C

M3C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5

L3

DQ6
DQ7

N3

DQM

P3

RDQS

P2

WDQS

M4B

M4B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

FBA_CMD27

27

FBA_CMD8

8

CS0

FBA_CMD18

18

FBA_CMD10

10

FBA_CMD5

5

FBA_CMD13

13

FBA_CMD21FBA_CMD22

21

FBA_CMD20

20

FBA_CMD19

19

FBA_CMD25

25

FBA_CMD4

4

FBA_CMD9

9

FBA_CMD17

17

FBA_CMD6

6

FBA_CMD23

23

FBA_CMD16

16

FBA_CMD3

3

FBA_CMD12

12

FBA_CMD1

1

FBA_CMD11

11

FBA_CLK1
FBA_CLK1*

14

15

R66

R66
243

243

1%

1%
0402

0402
COMMON

COMMON

GND

C515

C515
.047UF

.047UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

H3
F4
H9
F9

K4
H2
K3
M4

K9
H11
K10

L9
K11

M9

K2

L4

G4

G9
H10

H4

J11
J10

J2

J3

V4

V9

A9

A4

K1
K12

J1

J12

3

3

7

7

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

RAS BA2

A10 A8/AP
A11 A7

BA0

CLK
CLK

NC/RFU
NC/CS1 NC/CS1
SEN (GND)

NONMIRROR

NONMIRROR

RESET

MIRROR

ZQ

VDDA
VDDA

VSSA
VSSA

*CS1 is required 32Mx32 Memories

*CS1 is required 32Mx32 Memories

3

FBA_DQM7

7

FBA_DQS_RN7

FBA_DQS_WP7

FBA_CLK0

3,4

IN

FBA_CLK0*

3,4

IN

FBA_CLK1

3,4

IN

FBA_CLK1*

3,4

IN

FBVDDQ

F1

VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VREF
VREF

M3D

M3D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M4D

M4D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M1
A2
V2
A11
V11
F12
M12

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10
G12
L12

H1
H12

DDR3:

GND

FBA_VREF2
FBA_VREF3

VREF = 0.70 * FBVDDQ
VREF = FBVDDQ * R2/(R1 + R2)

COMMON

COMMON

COMMON

COMMON

FBVDDQ

R528

R528

549

549

R1

1%

1%
0402

0402

R533

R533

1.33K

1.33K

R2

1%

1%
0402

0402

GND

CSCAS
CKEWE
CASCS

A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A10A8/AP
A3A9

BA1
BA0BA1
RASBA2

WECKE

MIRROR

MIRROR

FBA_D24

24

E2

FBA_D25

25

G3

FBA_D26

26

F3

FBA_D27

27

C2

FBA_D28

28

F2

FBA_D29

29

C3

FBA_D30

30

B3

FBA_D31

31

B2
E3

D3
D2

FBA_D56

56

B10

FBA_D57

57

G10

FBA_D58

58

F10

FBA_D59

59

E11

FBA_D60

60

F11

FBA_D61

61

C10

FBA_D62

62

B11

FBA_D63

63

C11
E10

D10
D11

FBA_D[63..0]

3,4

BI

FBA_DQM[7..0]

3,4

BI

FBA_DQS_WP7

3,4

BI

FBA_DQS_RN7

3,4

BI

FBA_CMD27

3,4,4,4

BI

FBA_VREF0

BI

FBA_VREF1

BI

FBA_VREF2

BI

FBA_VREF3

BI

3,4,4,4

IN

FBVDDQ

C553

C553
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R

R503

R503

0402

0402

549

549

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

R1

1%

1%

0402

0402

R507

R507

1.33K

1.33K

R2

1%

1%

0402

0402

GND

DIFFPAIRNET NV_IMPEDANCE

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

0.900V 12MIL

0.900V 12MIL

0.900V 12MIL

0.900V 12MIL

Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBA_CMD[27..0]

C523

C523
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

FBA_CLK0

FBA_CLK0*

FBA_CLK1

FBA_CLK1*

2

0

24

22

13

4

5

6

FBA_CMD2

FBA_CMD0

FBA_CMD24

FBA_CMD22

FBA_CMD13

FBA_CMD4

FBA_CMD5

FBA_CMD6

237 R523

237

237

237

COMMON

COMMON

2371%R508

237

2371%R509

237

COMMON 0402

COMMON 0402

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

NV_IMPEDANCE

MIN_LINE_WIDTH

121

121

COMMON

COMMON

121

121

COMMON

COMMON

121

121

COMMON

COMMON

121

121

COMMON

COMMON

R523

0402COMMON

0402COMMON

1%

1%

R521

R521

0402

0402

1%

1%

R508

0402COMMON

0402COMMON

1%

R509

1%

600-10977-base-100 A

NAME

NV_CRITICAL_NET

80DIFF
80DIFF

NV_CRITICAL_NET

40OHM 2
40OHM 2

40OHM 1

FBVDDQ

R529121

R529121

0402COMMON

0402COMMON

1%

1%

R517

R517

0402

0402

1%

1%

R5161%121

R5161%121

0402COMMON

0402COMMON

R512

R512

0402

0402

1%

1%

R5251%121

R5251%121

0402COMMON

0402COMMON

R514121

R514121

0402COMMON

0402COMMON

1%

1%

R519

R519

0402

0402

1%

1%

R520

R520

0402

0402

1%

1%

FBVDDQ

R524

R524

80.6

80.6

1%

1%
0402

0402
COMMON

COMMON

FBA_CLK0_PU

12MIL 0.900V

FBA_CLK1_PU

NO STUFF NO STUFF

0.900V12MIL

C552

C552
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

GND

PAGEID
DATE

HFDBA

180DIFF
180DIFF
1
1

140OHM

256OHM

1

2

3

4

R506

R506

80.6

80.6

1%

1%
0402

0402
COMMON

COMMON

C526

C526
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

5

02-APR-2008

www.vinafix.vn

A B C D E F G H

FRAME BUFFER: PARTITION A DECOUPLING

1

Decoupling for FBA 0..31

C540

C540
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C549

C549
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C524

C524
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

10x 100nf 0402
5x 1uf 0603

PLACE NEAR MEMORY FBVDDQ PINS

C544

C544

C535

C535

.1UF

.1UF

.1UF

.1UF

16V

16V

16V

16V

10%

10%

10%

10%

X7R

X7R

X7R

X7R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

C547

C547

C536

C536

.1UF

.1UF

.1UF

.1UF

16V

16V

16V

16V

10%

10%

10%

10%

X7R

X7R

X7R

X7R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

C522

C522

C514

C514

1UF

1UF

1UF

1UF

16V

16V

16V

16V

10%

10%

10%

10%

X5R

X5R

X5R

X5R

0603

0603

0603

0603

COMMON

COMMON

COMMON

COMMON

C528

C528
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C554

C554
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C529

C529
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

C541

C541
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C519

C519
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C507

C507
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

GND

2

3

FBVDDQ

FBVDDQ below MEMORY:

Decoupling for FBA 32..63

FBVDDQ

PLACE NEAR MEMORY FBVDD PINS

C530

C530

C516

C516

.1UF

.1UF

.1UF

.1UF

16V

16V

16V

16V

10%

10%

10%

10%

X7R

X7R

X7R

X7R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

C539

C539

C548

C548

.1UF

.1UF

.1UF

.1UF

16V

16V

16V

16V

10%

10%

10%

10%

X7R

X7R

X7R

X7R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

C533

C533

C509

C509

1UF

1UF

1UF

1UF

16V

16V

16V

16V

10%

10%

10%

10%
X5R

X5R

X5R

X5R

0603

0603

0603

0603
COMMON

COMMON

COMMON

COMMON

FBVDDQ below MEMORY:

10x 100nf 0402
5x 1uf 0603

C545

C545
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C505

C505
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C513

C513
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

C538

C538
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C518

C518
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C504

C504
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

C527

C527
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C556

C556
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C543

C543
1UF

1UF

16V

16V
10%

10%
X5R

X5R
0603

0603
COMMON

COMMON

GND

1

2

3

Return path coupling GND/FBVDDQ for FBA

C561

C561
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

PLACE NEAR CMD GTV PIONTS

C115

C115

C700

C700

.01UF

.01UF

.01UF

.01UF

16V

16V

16V

16V

10%

10%

10%

10%

X7R

X7R

X7R

X7R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

C121

C121
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C104

C104
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C96

C96
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C101

C101
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C103

C103
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

4

GND

FBVDDQ

C100

C100

C105

4

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C105
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C GE

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA MEMORY FBVDDQ DECOUPLING CAPS

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10977-base-100 A

NAME

5

PAGEID
DATE

02-APR-2008

HFDBA

A B C D E F G H

G1D

G1D

BGA_0969_P080_290X290

BGA_0969_P080_290X290
COMMON

7,7

FBC_D[63..0]

BI

1

2

FBC_DQM[7..0]

7,7

3

4

OUT

7,7

7,7

FBC_DQS_WP[7..0]

BI

FBC_DQS_RN[7..0]

BI

SNN_FBC_WDS0
SNN_FBC_WDS0*
SNN_FBC_WDS1
SNN_FBC_WDS1*
SNN_FBC_WDS2
SNN_FBC_WDS2*
SNN_FBC_WDS3
SNN_FBC_WDS3*

COMMON

3/16 FBC

3/16 FBC

FBC_D0

0

D11

FBC_D0

FBC_D1

1

E11

FBC_D1

FBC_D2

2

F10

FBC_D2

FBC_D3

3

D8

FBC_D3

FBC_D4

4

F8

FBC_D4

FBC_D5

5

F9

FBC_D5

FBC_D6

6

E8

FBC_D6

FBC_D7

7

F12

FBC_D7

FBC_D8

8

B11

FBC_D8

FBC_D9

9

C13

FBC_D9

FBC_D10

10

A11

FBC_D10

FBC_D11

11

B8

FBC_D11

FBC_D12

12

A8

FBC_D12

FBC_D13

13

C8

FBC_D13

FBC_D14

14

C11

FBC_D14

FBC_D15

15

C10

FBC_D15

FBC_D16

16

D12

FBC_D16

FBC_D17

17

E13

FBC_D17

FBC_D18

18

F17

FBC_D18

FBC_D19

19

F15

FBC_D19

FBC_D20

20

F16

FBC_D20

FBC_D21

21

E16

FBC_D21

FBC_D22

22

F14

FBC_D22

FBC_D23

23

F13

FBC_D23

FBC_D24

24

D13

FBC_D24

FBC_D25

25

A13

FBC_D25

FBC_D26

26

B13

FBC_D26

FBC_D27

27

A14

FBC_D27

FBC_D28

28

C16

FBC_D28

FBC_D29

29

A17

FBC_D29

FBC_D30

30

B16

FBC_D30

FBC_D31

31

D16

FBC_D31

FBC_D32

32

D24

FBC_D32

FBC_D33

33

D26

FBC_D33

FBC_D34

34

E25

FBC_D34

FBC_D35

35

F25

FBC_D35

FBC_D36

36

F27

FBC_D36

FBC_D37

37

E28

FBC_D37

FBC_D38

38

F28

FBC_D38

FBC_D39

39

D29

FBC_D39

FBC_D40

40

A25

FBC_D40

FBC_D41

41

B25

FBC_D41

FBC_D42

42

D25

FBC_D42

FBC_D43

43

C26

FBC_D43

FBC_D44

44

C28

FBC_D44

FBC_D45

45

B28

FBC_D45

FBC_D46

46

A28

FBC_D46

FBC_D47

47

A29

FBC_D47

FBC_D48

48

E29

FBC_D48

FBC_D49

49

F29

FBC_D49

FBC_D50

50

D30

FBC_D50

FBC_D51

51

E31

FBC_D51

FBC_D52

52

C33

FBC_D52

FBC_D53

53

D33

FBC_D53

FBC_D54

54

F32

FBC_D54

FBC_D55

55

E32

FBC_D55

FBC_D56

56

B29

FBC_D56

FBC_D57

57

C29

FBC_D57

FBC_D58

58

B31

FBC_D58

FBC_D59

59

C31

FBC_D59

FBC_D60

60

B32

FBC_D60

FBC_D61

61

C32

FBC_D61

FBC_D62

62

B34

FBC_D62

FBC_D63

63

B35

FBC_D63

FBC_DQM0

0

F11

FBC_DQM0

FBC_DQM1

1

D10

FBC_DQM1

FBC_DQM2

2

D15

FBC_DQM2

FBC_DQM3

3

A16

FBC_DQM3

FBC_DQM4

4

D27

FBC_DQM4

FBC_DQM5

5

D28

FBC_DQM5

FBC_DQM6

6

D34

FBC_DQM6

FBC_DQM7

7

A34

FBC_DQM7

FBC_DQS_WP0

0

E10

FBC_DQS_WP0

FBC_DQS_WP1

1

A10

FBC_DQS_WP1

FBC_DQS_WP2

2

D14

FBC_DQS_WP2

FBC_DQS_WP3

3

C14

FBC_DQS_WP3

FBC_DQS_WP4

4

E26

FBC_DQS_WP4

FBC_DQS_WP5

5

B26

FBC_DQS_WP5

FBC_DQS_WP6

6

D32

FBC_DQS_WP6

FBC_DQS_WP7

7

A32

FBC_DQS_WP7

FBC_DQS_RN0

0

D9

FBC_DQS_RN0

FBC_DQS_RN1

1

B10

FBC_DQS_RN1

FBC_DQS_RN2

2

E14

FBC_DQS_RN2

FBC_DQS_RN3

3

B14

FBC_DQS_RN3

FBC_DQS_RN4

4

F26

FBC_DQS_RN4

FBC_DQS_RN5

5

A26

FBC_DQS_RN5

FBC_DQS_RN6

6

D31

FBC_DQS_RN6

FBC_DQS_RN7

7

A31

FBC_DQS_RN7

G11

RFU

G12

RFU

G14

RFU

G15

RFU

G24

RFU

G25

RFU

G27

RFU

G28

RFU

G96 only

G96 only

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30

FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1

FBC_DEBUG

FBAC_DLLAVDD
FBAC_PLLAVDD

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBCAL_TERM_GND

FBVDDQ

N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27

NET MIN_LINE_WIDTH

FB_CAL_PD

BI

FB_CAL_PU

BI

FB_CAL_TERM

BI

10MIL
10MIL
10MIL

1

2

FBC_CMD[27..0]

FBC_CMD0

0

C17

FBC_CMD1

1

B19

FBC_CMD2

2

D18

FBC_CMD3

3

F21

FBC_CMD4

4

A23

FBC_CMD5

5

D21

FBC_CMD6

6

B23

SNN_FBC_CMD7

E20

FBC_CMD8

8

G21

FBC_CMD9

9

F20

FBC_CMD10

10

F19

FBC_CMD11

11

F23

FBC_CMD12

12

A22

FBC_CMD13

13

C22

FBC_CMD14

14

B17

FBC_CMD15

15

F24

FBC_CMD16

16

C25

FBC_CMD17

17

E22

FBC_CMD18

18

C20

FBC_CMD19

19

B22

FBC_CMD20

20

A19

FBC_CMD21

21

D22

FBC_CMD22

22

D20

FBC_CMD23

23

E19

FBC_CMD24

24

D19

FBC_CMD25

25

F18

SNN_FBC_CMD26

C19

FBC_CMD27

27

F22

SNN_FBC_CMD28

C23

SNN_FBC_CMD29

B20

SNN_FBC_CMD30

A20

FBC_CLK0

E17

FBC_CLK0*

D17

FBC_CLK1

D23

FBC_CLK1*

E23

FBC_DEBUG

G19

OUT
OUT
OUT
OUT

NO STUFF

R563

04021%COMMON

04021%COMMON

7,7,7

OUT

3

7,7
7,7
7,7
7,7

FBVDDQ

60.4R563

60.4

4

Place close to GPU

J19
J18

FB_CAL_PD_VDDQ

K27

FB_CAL_PU_GND

L27

FB_CAL_TERM_GND

M27

R556 44.2

R556 44.2

0402

0402

R560

R561 40.2

R561 40.2

0402

0402

FB_PLLAVDD

FBVDDQ

COMMON

COMMON

1%

1%

30.9R560

30.9

COMMON0402

COMMON0402

1%

1%

COMMON

COMMON

1%

1%

C633

C633
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C629

C629
.1UF

.1UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

GND

3,3

OUT

GND

5

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C GE

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC MEMORY INTERFACE

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10977-base-100 A

NAME

PAGEID
DATE

02-APR-2008

HFDBA

A B C D E F G H

FRAMEBUFFER: PARTITION C 16/32Mx32 BGA136 GDDR3

FB_C-CS0-LOW-32bit

M1E

M1E

BGA_0136_P080_140X120

FBC_CMD[27..0]

6,7,7

IN

1

Low Sub-Partition

6,7

IN

6,7

IN

2

FOR QIMONDA RSEN= 1K
FOR OTHERS RSEN= 0OHM

R611

R611
1K

1K

5%

5%
0402

0402
COMMON

COMMON

GND

3

FBC_CMD1

1

FBC_CMD10

10

FBC_CMD11

11

FBC_CMD8

8

CS0

FBC_CMD19

19

FBC_CMD25

25
22

FBC_CMD24

24

FBC_CMD0

0

FBC_CMD2

2

FBC_CMD21

21

FBC_CMD16

16

FBC_CMD23

23

FBC_CMD20

20

FBC_CMD17

17

FBC_CMD9

9

FBC_CMD12

12

FBC_CMD3

3

FBC_CMD27

27

FBC_CMD18

18

FBC_CLK0
FBC_CLK0*

SNN_FBC0_NC1 SNN_FBC1_NC1

FBC_CMD14 FBC_CMD14

14

FBC_DEBUG_SEN0 FBC_DEBUG_SEN1

FBC_CMD15 FBC_CMD15

15

FBC_CMD15

FBC_CMD18

R62

R62

R61

R61

10K

10K

10K

10K

5%

5%

5%

5%

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

GND GND

FBVDDQ

C697

C697
.047UF

.047UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

GND

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

H3

RAS BA2

F4

CAS CS

H9

WE CKE

F9

CS CAS

K4
H2
K3
M4

K9
H11
K10

L9

K11

M9

K2

L4

G4

G9
H10

H4
J11
J10

J2
J3

V4

V9

A9

FBC_ZQ0 FBC_ZQ1

A4

R60

R60
243

243

1%

1%
0402

0402
COMMON

COMMON

K1
K12

C723

C723
.047UF

.047UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

J1

J12

6,7

6,7
6,7
6,7

A8/AP A10

BA0

CLK
CLK

NC/RFU
NC/CS1 NC/CS1
SEN (GND)

NONMIRROR

NONMIRROR

RESET

MIRROR

ZQ

VDDA
VDDA

VSSA
VSSA

*CS1 is required 32Mx32 Memories

*CS1 is required 32Mx32 Memories

FBC_D[63..0]

BI

FBC_DQM[7..0]

BI

FBC_DQS_RN[7..0]

BI

FBC_DQS_WP[7..0]

BI

MIRROR

MIRROR

A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7

A3A9
A8/APA10
A7A11

BA1
BA0BA1

RASBA2

WECKE

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

FBVDDQ

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

GND

G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10
G12
L12

FBC_VREF0

H1

FBC_VREF1

H12

VREF = 0.70 * FBVDDQDDR3:
VREF = FBVDDQ * R2/(R1 + R2)

FBC_D0

0

FBC_D1

1

FBC_D2

2

FBC_D3

3

FBC_D4

4

FBC_D5

5

FBC_D6

6

FBC_D7

7

FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3

0

FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3

0

FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3

0

FBC_D32

32

FBC_D33

33

FBC_D34

34

FBC_D35

35

FBC_D36

36

FBC_D37

37

FBC_D38

38

FBC_D39

39

FBC_DQM4 FBC_DQM5 FBC_DQM6

4

FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6

4

FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6

4

M1A

M1A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

R2

DQ0

T2

DQ1

N2

DQ2

R3

DQ3

M2

DQ4

L3

DQ5

M3

DQ6

T3

DQ7

N3

DQM

P3

RDQS

P2

WDQS

M2E

M2E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

L3

DQ0

T3

DQ1

M2

DQ2

M3

DQ3

R2

DQ4

T2

DQ5

N2

DQ6

R3

DQ7

N3

DQM

P3

RDQS

P2

WDQS

FBC Partition

136BGA CMD Mapping

CMD

CMD1
CMD10
CMD11
CMD18
CMD15
CMD8

CMD19
CMD25

CMD22
CMD24
CMD0
CMD2

CMD4
CMD6
CMD5
CMD13

CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD14

CMD12
CMD3

FBVDDQ

R613

R613

549

549

1%

1%

R1

0402

0402

COMMON

COMMON

R612

R612

1.33K

1.33K

1%

1%

R2

0402

0402

COMMON

COMMON

GND

ADDR

RAS*
CAS*
WE*
CKE
RESET/ODT
CS0*

A<0>
A<1>

A<2>
A<3>
A<4>
A<5>

A<2>
A<3>
A<4>
A<5>

A<6>
A<7>
A<8>
A<9>
A<10
A<11>
A<12>

BA0
BA1
BA2CMD27

C722

C722
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

Low Sub-Partition

Hi Sub-Partition

1

5

COMMON

COMMON

COMMON

COMMON

FBVDDQ

R574

R574

549

549

1%

1%

0402

0402

R578

R578

1.33K

1.33K

1%

1%

0402

0402

GND

8
9
10
11
12
13
14
15

1

1

40
41
42
43
44
45
46
47

5

5

C GE

FOR QIMONDA RSEN= 1K
FOR OTHERS RSEN= 0OHM

R1

C683

C683
.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

FBC_D8

F3

FBC_D9

G3

FBC_D10

E2

FBC_D11

C3

FBC_D12

B3

FBC_D13

B2

FBC_D14

F2

FBC_D15

C2
E3

D3
D2

FBC_D40

C3

FBC_D41

B3

FBC_D42

C2

FBC_D43

E2

FBC_D44

F2

FBC_D45

F3

FBC_D46

G3

FBC_D47

B2
E3

D3
D2

Hi Sub-Partition

M1B

M1B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M2A

M2A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

ASSEMBLY
PAGE DETAIL

FB_C-CS0-HI-32bit

M2C

M2C

BGA_0136_P080_140X120

FBC_CMD[27..0]

6,7

IN

6,7

IN

FBVDDQ

R544

R544
1K

1K

5%

5%
0402

0402
COMMON

COMMON

GND

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC 16/32MX32 GDDR3 MEMORIES, FBC CMD BUS PU'S, FBC CLK TERMS

FBVDDQ

2

6

FBC_CMD27

27

FBC_CMD8

8

CS0

FBC_CMD18

18

FBC_CMD10

10

FBC_CMD5

5

FBC_CMD13

13

FBC_CMD21FBC_CMD22

21

FBC_CMD20

20

FBC_CMD19

19

FBC_CMD25

25

FBC_CMD4

4

FBC_CMD9

9

FBC_CMD17

17

FBC_CMD6

6

FBC_CMD23

23

FBC_CMD16

16

FBC_CMD3

3

FBC_CMD12

12

FBC_CMD1

1

FBC_CMD11

11

FBC_CLK1
FBC_CLK1*

14

15

R558

R558
243

243

1%

1%
0402

0402
COMMON

COMMON

GND

C572

C572

C577

C577

.047UF

.047UF

.047UF

.047UF

16V

16V

16V

16V

10%

10%

10%

10%

X7R

X7R

X7R

X7R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

GND

FBC_D16

16

R10

FBC_D17

17

T10

FBC_D18

18

L10

FBC_D19

19

N11

FBC_D20

20

M10

FBC_D21

21

M11

FBC_D22

22

R11

FBC_D23

23

T11

2

N10

2

P10
P11

FBC_D48

48

N11

FBC_D49

49

T10

FBC_D50

50

R10

FBC_D51

51

T11

FBC_D52

52

R11

FBC_D53

53

M10

FBC_D54

54

L10

FBC_D55

55

M11

6

N10

6

P10
P11

H3
F4
H9
F9

K4
H2
K3
M4

K9
H11
K10

L9
K11

M9

K2

L4

G4

G9
H10

H4

J11
J10

J2

J3

V4

V9

A9

A4

K1
K12

J1

J12

M1C

M1C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M2B

M2B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

BGA_0136_P080_140X120

BGA136

BGA136
COMMON

COMMON

RAS BA2
CAS CS
WE CKE

A1 A5
A2 A6
A3 A9
A4 A0
A5 A1

A9 A3

BA0
BA1 BA0
BA2 RAS

CLK
CLK

NC/RFU
NC/CS1 NC/CS1
SEN (GND)

NONMIRROR

NONMIRROR

RESET

MIRROR

ZQ

VDDA
VDDA

VSSA
VSSA

*CS1 is required 32Mx32 Memories

*CS1 is required 32Mx32 Memories

CASCS

A4A0

A2A6
A11A7
A10A8/AP

A8/APA10
A7A11

BA1

WECKE

MIRROR

MIRROR

3

7

NET

FBC_CLK0

6,7

IN

FBC_CLK0*

6,7

IN

FBC_CLK1

6,7

IN

FBC_CLK1*

6,7

FBVDDQ

IN

FBC_D[63..0]

6,7

BI

FBC_DQM[7..0]

6,7

BI

FBC_DQS_WP7

6,7

BI

FBC_DQS_RN7

6,7

BI

FBC_CMD[27..0]

6,7,7

IN

FBC_VREF0

BI

FBC_VREF1

BI

FBC_VREF2

BI

FBC_VREF3

BI

6,7,7

IN

R1

C595

C595
.01UF

.01UF

FBVDDQ

16V

16V
10%

10%

R2

X7R

X7R
0402

0402
COMMON

COMMON

R543

R543

549

549

1%

1%

0402

GND

COMMON

COMMON

R542

R542

1.33K

1.33K

COMMON

COMMON

FBC_CLK0

FBC_CLK0*

FBC_CLK1

FBC_CLK1*

0402

1%

1%

0402

0402

GND

FBVDDQ

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

FBC_D24

24

FBC_D25

25

FBC_D26

26

FBC_D27

27

FBC_D28

28

FBC_D29

29

FBC_D30

30

FBC_D31

31

3

3

FBC_D56

56

FBC_D57

57

FBC_D58

58

FBC_D59

59

FBC_D60

60

FBC_D61

61

FBC_D62

62

FBC_D63

63

FBC_DQM7

7

7

FBC_DQS_RN7

FBC_DQS_WP7

G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10
G12
L12

H1
H12

DDR3:

F10

F11
G10
E11
C11
C10
B11
B10

E10
D10
D11

G10

F11
E11

F10
C11
B11
C10
B10

E10
D10
D11

GND

FBC_VREF2
FBC_VREF3

VREF = 0.70 * FBVDDQ
VREF = FBVDDQ * R2/(R1 + R2)

M1D

M1D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M2D

M2D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

COMMON

COMMON

COMMON

COMMON

R553

R553

549

549

1%

1%

0402

0402

R552

R552

1.33K

1.33K

1%

1%

0402

0402

DIFFPAIR

FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1

0.900V 12MIL

0.900V 12MIL

0.900V 12MIL

Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBC_CMD[27..0]

2

0

24

22

13

4

5

6

R1

C571

C571
.01UF

.01UF

16V

16V

R2R2

10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

R595

237

R595

237

COMMON

COMMON

0402

0402

1%

1%

R599

237 R599

237

0402COMMON

0402COMMON

1%

1%

R545

237

R545

237

0402

COMMON

0402

COMMON

1%

1%

R547

237 R547

237

0402

COMMON

0402

COMMON

1%

1%

NV_IMPEDANCE

80DIFF
80DIFF
80DIFF

NV_IMPEDANCE

MIN_LINE_WIDTH

12MIL0.900V

FBC_CMD2

FBC_CMD0

FBC_CMD24

FBC_CMD22

FBC_CMD13

FBC_CMD4

FBC_CMD5

FBC_CMD6

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

R577

121

R577

121

COMMON

COMMON

0402

0402

1%

1%

R5791%121

R5791%121

0402COMMON

0402COMMON

R6061%121

R6061%121

0402COMMON

0402COMMON

R6051%121

R6051%121

0402COMMON

0402COMMON

R557121

R557121

0402COMMON

0402COMMON

1%

1%

R5501%121

R5501%121

0402COMMON

0402COMMON

R5491%121

R5491%121

0402COMMON

0402COMMON

R546121

R546121

0402COMMON

0402COMMON

1%

1%

FBC_CLK0_PU

12MIL 0.900V

FBC_CLK1_PU

12MIL 0.900V

600-10977-base-100 A

NAME

NV_CRITICAL_NET

NV_CRITICAL_NET

FBVDDQ

FBVDDQ

R610

R610

R548

R548

80.6

80.6

80.6

80.6

1%

1%

1%

1%

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

NO STUFF NO STUFF

C715

C715

C586

C586

.01UF

.01UF

.01UF

.01UF

16V

16V

16V

16V

10%

10%

10%

10%

X7R

X7R

X7R

X7R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

GND

PAGEID
DATE

HFDBA

180DIFF
1
1
1

240OHM
240OHM

256OHM

140OHM
140OHM

02-APR-2008

1

2

3

4

5

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