MSI MS-V135 Schematic 0A

A B C D E F G H

G94-P545-A01 - GDDR3, DVI/VGA + DVI/VGA + HDTV/SDTV-Out

1

2

3

4

VARIANT ASSEMBLY

SKU

B

BASE

1

SKU9100

2

SKU0000

3

SKU0010

4

SKU0020

5

<UNDEFINED>

6

<UNDEFINED>

7

<UNDEFINED>

8

<UNDEFINED>

9

<UNDEFINED>

10

<UNDEFINED>

11

<UNDEFINED>
<UNDEFINED>

12

<UNDEFINED>

13

<UNDEFINED>

14
15

<UNDEFINED>

Table of Contents:

Page 1: Overview
Page 2: PCI Express
Page 3: MEMORY: GPU Partition A/B
Page 4: MEMORY: GPU Partition C/D
Page 5: FBA Partition
Page 6: FBA Partition Decoupling
Page 7: FBB Partition
Page 8: FBB Partion Decoupling
Page 9: FBC Partition
Page 10: FBC Partition Decoupling
Page 11: FBD Partition
Page 12: FBD Partition Decoupling
Page 13: FB Net Properties
Page 14: DACA Interface
Page 15: DACC Interface
Page 16: IFP A/B Interface -- DVI Connector South
Page 17: IFP C/D Interface -- DVI Connector MID
Page 18: IFP E/F Interface -- Unused
Page 19: DACB and HDTV/SDTV-Out
Page 20: MIO A/B Interface
Page 21: MISC: GPIO, I2C, ROM, HDCP, and XTAL
Page 22: Strap Configuration
Page 23: PWR and GND Signals
Page 24: NVVDD and FBVDDQ Decoupling
Page 25: SPDIF Input, Backdrive Protection, and IFP_IOVDD Power Supply
Page 26: PS I: 3V3, 12V, and 12V_EXT Power Supply Filter
Page 27: PS II: PEX_VDD, IFP_PLLVDD, 2V5, 5V, and DDC_5V Power Supply
Page 28: PS III: FBVDDQ Power Supply
Page 29: PS IV: NVVDD VID Control
Page 30: PS V: NVVDD Power Supply
Page 31: Thermal Diode and Fan Control
Page 32: Thermal, Mechanical, and Bracket
Page 33: FBA -1Partition
Page 34: FBB-1 Partition
Page 35: FBC-1 Partition
Page 36: FBD-1 Partition

NVPN

600-10545-base-100
600-10545-9100-100
600-10545-0000-100
600-10545-0010-100
600-10545-0020-100
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
G94-400 650MHz/1000MHz 512MB 16Mx32 BGA136 GDDR3, DVI-I-DL+DVI-I-DL+HDTV-Out (Bring Up SKU)
G94-400 650MHz/1000MHz 512MB 16Mx32 BGA136 GDDR3, DVI-I-DL+DVI-I-DL+HDTV-Out
G94-300 500MHz/800MHz 512MB 16Mx32 BGA136 GDDR3, DVI-I-DL+DVI-I-DL+HDTV-Out
G94-200 500MHz/800MHz 384MB 16Mx32 BGA136 GDDR3, DVI-I-DL+DVI-I-DL+HDTV-Out
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>

V127-0A Base on P545

1.PAGE18: ADD Display port circuit

2.PAGE21: ADD GPIO circuit

3.PAGE 21: change SPDIF circuit

4.PAGE 27: remove PEX_VDD power switch circuit

5.PAGE 27: remove IFP_PLLVDD/2V5 power switch circuit cahnge APL5713 and APL5910 circuit

6.PAGE 28: remove FBVDDQ power switch circuit change APW7067N power circuit

7.PAGE 29: remove NVVDD VID circuit

8.PAGE 30: change NNVDD POWER APW7088 circuit

9.PAGE 16/17 : ADD EMI bridge R

10.PAGE 17 CO-LAYOUT HDIM CONNECT

11.PAGE 15 remove J1 D_SUB SLIM CONNECT

V135-0A Base on V127-0A and P545

1.Add Page 33,34,35,36 for extend MEM

2.Page 3,4 FBCMD7 connect to CS1

1

2

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C GE

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Overview

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date:

Date:

Date:

MS-V135

<Doc>

<Doc>

<Doc>

Tuesday, February 12, 2008

Tuesday, February 12, 2008

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

136

136

136

<RevCode>

<RevCode>

<RevCode>

5

A B C D E F G H

Page33: FBA-1 Partition

M9E

CMD-Addr Map
BGA136 ADDR

CMD1 RAS*
CMD10 CAS*

FBA_CMD273,5

CMD11 WE*

FBA_CS13

1

IN
IN

2

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6

FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11

3

FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

CMD7 CS1*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

FBA_CMD_SENA05 FBA_CMD_SENA15

DDR3:

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

FBA_CMD[6..0]

FBA_CMD[6..0] 3,5

0
1
2
3
4
5
6

FBA_CMD[25..8]

FBA_CMD[25..8] 3,5

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

FBA_D[63..0]

BI

FBA_DQM[7..0]

BI

FBA_DQS_RN[7..0]

BI

FBA_DQS_WP[7..0]

BI

FBA_CMD20

11

14

FBVDDQ

15

3

FBVDDQ

3

GND

FBA_DQM0

0

FBA_DQM1

1

FBA_DQM2

2

FBA_DQM3

3
4

FBA_DQM5

5

FBA_DQM6

6

FBA_DQM7

7

FBA_DQS_RN0

0

FBA_DQS_RN1

1

FBA_DQS_RN2

2

FBA_DQS_RN3

3

FBA_DQS_RN4

4

FBA_DQS_RN5

5

FBA_DQS_RN6

6

FBA_DQS_RN7

7

FBA_DQS_WP0

0

FBA_DQS_WP1

1

FBA_DQS_WP2

2

FBA_DQS_WP3

3

FBA_DQS_WP4

4

FBA_DQS_WP5

5

FBA_DQS_WP6

6

FBA_DQS_WP7

7

M9E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

FBB_CMD27 FBA_CMD27

H3

RAS

FBA_CS1 FBA_CS1

F4

CAS

FBA_CMD18 FBA_CMD18

H9

WE

FBA_CMD10 FBA_CMD10

F9

CS0

FBA_CMD0 FBA_CMD5

K4

A0

FBA_CMD2 FBA_CMD13

H2

FBA_CMD21

FBA_CMD19
FBA_CMD25

FBA_CMD15 FBA_CMD15 FBA_CMD15

A1

K3

A2

M4

A3

K9

A4

H11

A5

FBA_CMD22 FBA_CMD4

K10

A6

FBA_CMD9 FBA_CMD9

L9

A7

FBA_CMD17 FBA_CMD17

K11

A8/AP

FBA_CMD24 FBA_CMD6

M9

A9

FBA_CMD23 FBA_CMD23

K2

A10

FBA_CMD16 FBA_CMD16

L4

A11

FBA_CMD3 FBA_CMD3

G4

BA0

FBA_CMD12 FBA_CMD12

G9

BA1

FBA_CMD1 FBA_CMD1

H10

BA2

NONMIRRORED

GND

C95

C95
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

FBA_D1
FBA_D2
FBA_D7
FBA_D0
FBA_D6
FBA_D3
FBA_D4
FBA_D5

FBA_DQM0
FBA_DQS_RN0
FBA_DQS_WP0

FBA_D38
FBA_D37
FBA_D39
FBA_D35
FBA_D34
FBA_D33
FBA_D36
FBA_D32

FBA_DQM4
FBA_DQS_RN4
FBA_DQS_WP4

NONMIRRORED

H4

CKE

J11

CLK

J10

CLK

J2

NC/RFU

J3

A12 (32Mx32)

V4

SEN (GND)

V9

RESET

A9

MF (GND)

A4

ZQ

FBA_ZQ0_1

R117

R117
240

240

5%

5%

0603

0603

COMMON

COMMON

K1

VDDA (VDD)

K12

VDDA (VDD)

J1

VSSA (GND)

J12

VSSA (GND)

M9B

M9B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

G10

DQ0

F11

DQ1

E11

DQ2

C10

DQ3

C11

DQ4

F10

DQ5

B10

DQ6

B11

DQ7

E10

DQM

D10

RDQS

D11

WDQS

M10A

M10A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

T2

DQ0

R2

DQ1

L3

DQ2

M3

DQ3

N2

DQ4

M2

DQ5

T3

DQ6

R3

DQ7

N3

DQM

P3

RDQS

P2

WDQS

FBA_CMD11 FBA_CMD11
FBA_CLK0
FBA_CLK0*

FBA_CMD14 FBA_CMD14
FBA_CMD_SENA0 FBA_CMD_SENA1

C101

C101
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

0
1
2
3
4
5
6
7

32
33
34
35
36
37
38
39

FBVDDQ

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

GND

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

GND

G12

VSS

L12

VSS

FBA_VREF2 FBA_VREF3

H1

VREF
VREF

FBA_VREF2 5

FBA_VREF0 FBA_VREF1

H12

FBA_VREF0 5

VREF = FBVDDQ * R2/(R1 + R2)

DDR3:

VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

M9A

M9A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

FBA_D11

8

C3

DQ0

FBA_D8

9

G3

DQ1

FBA_D9

10

F2

DQ2

FBA_D13

11

F3

DQ3

FBA_D14

12

B3

DQ4

FBA_D15

13

B2

DQ5

FBA_D12

14

C2

DQ6

FBA_D10

15

E2

DQ7

FBA_DQM1

E3

DQM

FBA_DQS_RN1

D3

RDQS

FBA_DQS_WP1

D2

WDQS

M10E

M10E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

FBA_D47

40

R10

DQ0

FBA_D45

41

M11

DQ1

FBA_D44

42

N11

DQ2

FBA_D43

43

M10

DQ3

FBA_D46

44

T10

DQ4

FBA_D41

45

R11

DQ5

FBA_D40

46

T11

DQ6

FBA_D42

47

L10

DQ7

FBA_DQM5

N10

DQM

FBA_DQS_RN5

P10

RDQS

FBA_DQS_WP5

P11

WDQS

C GE

CMD-Addr Map
BGA136 ADDR

CMD1 RAS*

1

CMD10 CAS*

FBA_CMD273,5

10

CMD11 WE*

FBA_CS13

11

CMD7 CS1*

7

CMD19 A<0>
CMD25 A<1>

19

CMD4 A<2>

25

CMD6 A<3>

4

CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

IN
IN

ZQ = 6x desired output

DDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

FBA_CMD21
FBA_CMD20

6
5

FBA_CMD19

13

FBA_CMD25

21
16
23
20
17
9

12
3
27

18

FBA_CLK1
FBA_CLK1*

14

15

FBA_ZQ1_1

R120

R120
240

240

5%

5%

0603

0603

COMMON

COMMON

GND

FBVDDQ

C102

C102

C922

C922
.047UF

.047UF

.047UF

.047UF

16V

16V

16V

16V

10%

10%

10%

10%

X7R

X7R

X7R

X7R

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

GND

M9D

16

FBA_D19

17

FBA_D17

18

FBA_D22

19

FBA_D23

20

FBA_D16

21

FBA_D20

22

FBA_D18

23

FBA_DQM2
FBA_DQS_RN2
FBA_DQS_WP2

FBA_D54

48

FBA_D53

49

FBA_D50

50

FBA_D49

51

FBA_D48

52

FBA_D51

53

FBA_D52

54

FBA_D55

55

FBA_DQM6
FBA_DQS_RN6
FBA_DQS_WP6

ASSEMBLY P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PAGE DETAIL

FBA Partition

R11
N11
R10
M10
L10
M11
T10
T11

N10
P10
P11

F2
F3
G3
C3
E2
B3
B2
C2

E3
D3
D2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M10C

M10C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

M9D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

FBA_D21

FBA_D29
FBA_D26
FBA_D31
FBA_D25
FBA_D30
FBA_D24
FBA_D27
FBA_D28

FBA_DQM3FBA_DQM4
FBA_DQS_RN3
FBA_DQS_WP3

FBA_D60
FBA_D59
FBA_D58
FBA_D61
FBA_D62
FBA_D57
FBA_D56
FBA_D63

FBA_DQM7
FBA_DQS_RN7
FBA_DQS_WP7

M2
R3
T2
N2
T3
R2
M3
L3

N3
P3
P2

E11
C10
G10
B10
B11
F10
F11
C11

E10
D10
D11

M9C

M9C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M10B

M10B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

H10
H4

H11
K10
M9

H2

M4
K11

G9
G4
H3

H9
J11
J10

K12

J12

F9
F4
K9

K4
K3

L4
K2

L9

J2
J3
V4

V9
A9
A4

K1

J1

M10D

M10D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

RAS
CAS
WE
CS0

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11

BA0
BA1
BA2

CKE
CLK
CLK

NC/RFU
A12 (32Mx32)
SEN (GND)

RESET

MF (GND)

ZQ

VDDA (VDD)
VDDA (VDD)

VSSA (GND)
VSSA (GND)

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

MIRRORED

MIRRORED

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

G12

VSS

L12

VSS

H1

VREF

H12

VREF

FBVDDQ

1

2

VREF = FBVDDQ * R2/(R1 + R2)

DDR3: VREF = 0.70 * FBVDDQ

GND

1.26V = 1.8V * 1.18K/(511 + 1.18K)

GND

FBA_VREF3 5
FBA_VREF1 5

3

4

5

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc>

Custom

<Doc>

Custom

<Doc>

Custom

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

33 36

33 36

33 36

<RevCode>

<RevCode>

<RevCode>

Title

Title

Title

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

<Doc>

<Doc>

<Doc>

Date: Sheet

Date: Sheet

Date: Sheet

<RevCode>

<RevCode>

<RevCode>

of

11Tuesday, February 12, 2008

of

11Tuesday, February 12, 2008

of

11Tuesday, February 12, 2008

www.vinafix.vn

A B C D E F G H

Page34: FBB-1 Partition

M11E

CMD-Addr Map
BGA136 ADDR

CMD1 RAS*
CMD10 CAS*

FBB_CMD[6..0] 3,7

FBB_CMD[25..8] 3,7

FBB_D[63..0]

FBB_DQM[7..0]

FBB_DQS_RN[7..0]

FBB_DQS_WP[7..0]

CMD11 WE*
CMD7 CS1*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

3

3

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

1

IN
IN

2

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6

FBB_CMD8
FBB_CMD9
FBB_CMD10

3

FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25

4

FBB_CMD_SENB07 FBB_CMD_SENB17

DDR3: ZQ = 6x desired output

impedence of DQ drivers

FBB_CMD[6..0]

FBB_CMD[25..8]

BI

BI

BI

BI

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

1

FBB_CMD273,7

FBB_CMD27 FBB_CMD27

10

FBB_CS1 FBB_CS1

FBB_CS13 FBB_CS13

11

FBB_CMD18 FBB_CMD18

7

FBB_CMD10 FBB_CMD10

19

FBB_CMD0 FBB_CMD5

25

FBB_CMD2 FBB_CMD13

22

FBB_CMD21

24

FBB_CMD20

0

FBB_CMD19

2

FBB_CMD25

21

FBB_CMD22 FBB_CMD4

16

FBB_CMD9 FBB_CMD9

23

FBB_CMD17 FBB_CMD17

20

FBB_CMD24 FBB_CMD6

17

FBB_CMD23 FBB_CMD23

9

FBB_CMD16 FBB_CMD16

12

FBB_CMD3 FBB_CMD3

3

FBB_CMD12 FBB_CMD12

27

FBB_CMD1 FBB_CMD1

18

FBB_CMD11 FBB_CMD11
FBB_CLK0
FBB_CLK0*

14

FBB_CMD14 FBB_CMD14
FBB_CMD_SENB0 FBB_CMD_SENB1

FBVDDQ

15

FBB_CMD15 FBB_CMD15 FBB_CMD15

FBVDDQ

C137

C137
.047UF

.047UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

GND

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3

FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

M11E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

H3

RAS

F4

CAS

H9

WE

F9

CS0

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

H10

BA2

H4

CKE

J11

CLK

J10

CLK

J2

NC/RFU

J3

A12 (32Mx32)

V4

SEN (GND)

V9

RESET

A9

MF (GND)

A4

ZQ

FBB_ZQ0_1

R127

R127
240

240

5%

5%

0603

0603

COMMON

COMMON

GND

K1

VDDA (VDD)

K12

VDDA (VDD)

C138

C138
.047UF

.047UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

J1

VSSA (GND)

J12

VSSA (GND)

FBB_D1

0

FBB_D0

1

FBB_D6

2

FBB_D2

3

FBB_D4

4

FBB_D7

5

FBB_D3

6

FBB_D5

7

FBB_DQM0
FBB_DQS_RN0
FBB_DQS_WP0

FBB_D38

32

FBB_D35

33

FBB_D34

34

FBB_D39

35

FBB_D33

36

FBB_D32

37

FBB_D36

38

FBB_D37

39

FBB_DQM4
FBB_DQS_RN4
FBB_DQS_WP4

C3
B3
F3
B2
C2
F2
E2
G3

E3
D3
D2

T11
T10
R11
R10
N11
M11
M10
L10

N10
P10
P11

NONMIRRORED

NONMIRRORED

M11B

M11B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M12A

M12A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

FBVDDQ

F1
M1
A2
V2
A11
V11
F12
M12

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2

GND

B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10

GND

G12
L12

FBB_VREF2 FBB_VREF3

H1
H12

FBB_D9

8

FBB_D8

9

FBB_D11

10

FBB_D14

11

FBB_D12

12

FBB_D15

13

FBB_D10

14

FBB_D13

15

FBB_DQM1
FBB_DQS_RN1
FBB_DQS_WP1

FBB_D45

40

FBB_D44

41

FBB_D42

42

FBB_D41

43

FBB_D46

44

FBB_D47

45

FBB_D40

46

FBB_D43

47

FBB_DQM5
FBB_DQS_RN5
FBB_DQS_WP5

FBB_VREF2 7

FBB_VREF0 FBB_VREF1

FBB_VREF0 7

VREF = FBVDDQ * R2/(R1 + R2)

DDR3: VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

M11A

M11A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

B10

DQ0

C10

DQ1

B11

DQ2

E11

DQ3

C11

DQ4

G10

DQ5

F10

DQ6

F11

DQ7

E10

DQM

D10

RDQS

D11

WDQS

M12E

M12E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

M2

DQ0

N2

DQ1

R2

DQ2

T3

DQ3

M3

DQ4

L3

DQ5

T2

DQ6

R3

DQ7

N3

DQM

P3

RDQS

P2

WDQS

C GE

ASSEMBLY
PAGE DETAIL

CMD-Addr Map
BGA136 ADDR

CMD1 RAS*

FBB_CMD273,7

CMD10 CAS*
CMD11 WE*
CMD7 CS1*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

IN
IN

DDR3: ZQ = 6x desired outputImpedence = 240 / 6 = 40 ohm

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

M11D

M11D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

FBB_D17

16

FBB_D19

17

FBB_D16

18

FBB_D22

19

FBB_D18

20

FBB_D20

21

FBB_D23

22

FBB_D21

23

FBB_DQM2
FBB_DQS_RN2
FBB_DQS_WP2

FBB_D48

48

FBB_D49

49

FBB_D55

50

FBB_D54

51

FBB_D52

52

FBB_D51

53

FBB_D50

54

FBB_D53

55

FBB_DQM6
FBB_DQS_RN6
FBB_DQS_WP6

COMMON

R3

DQ0

L3

DQ1

M3

DQ2

N2

DQ3

M2

DQ4

R2

DQ5

T3

DQ6

T2

DQ7

N3

DQM

P3

RDQS

P2

WDQS

M12C

M12C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

G10

DQ0

F10

DQ1

F11

DQ2

E11

DQ3

B11

DQ4

B10

DQ5

C10

DQ6

C11

DQ7

E10

DQM

D10

RDQS

D11

WDQS

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBB Partition

FBB_D26

24

FBB_D24

25

FBB_D28

26

FBB_D25

27

FBB_D29

28

FBB_D31

29

FBB_D27

30

FBB_D30

31

FBB_DQM3FBB_DQM4
FBB_DQS_RN3
FBB_DQS_WP3

FBB_D56

56

FBB_D57

57

FBB_D62

58

FBB_D61

59

FBB_D60

60

FBB_D63

61

FBB_D59

62

FBB_D58

63

FBB_DQM7
FBB_DQS_RN7
FBB_DQS_WP7

1
10
11
7

19
25
4
6
5
13
21
16
23
20
17
9

12
3
27

18

14

15

FBVDDQ

GND

FBB_CMD21
FBB_CMD20
FBB_CMD19
FBB_CMD25

C141

C141
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

FBB_CLK1
FBB_CLK1*

GND

M10
R10
M11
L10
R11
T11
N11
T10

N10
P10
P11

G3

F3
C3
B3
B2
C2
E2

F2
E3

D3
D2

FBB_ZQ1_1

R132

R132
240

240

5%

5%

0603

0603

COMMON

COMMON

GND

C142

C142
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

M11C

M11C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M12B

M12B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

H10

F9
H4
F4

K9
H11
K10

M9

K4

H2

K3

L4

K2

M4
K11

L9

G9

G4

H3

H9
J11
J10

J2

J3

V4

V9

A9

A4

K1
K12

J1
J12

M12D

M12D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

RAS
CAS
WE
CS0

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11

BA0
BA1
BA2

CKE
CLK
CLK

NC/RFU
A12 (32Mx32)
SEN (GND)

RESET

MF (GND)

ZQ

VDDA (VDD)
VDDA (VDD)

VSSA (GND)
VSSA (GND)

FBVDDQ

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

MIRRORED

MIRRORED

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

G12

VSS

L12

VSS

H1

VREF

H12

VREF

VREF = FBVDDQ * R2/(R1 + R2)

GND

VREF = 0.70 * FBVDDQDDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

GND

FBB_VREF3 7
FBB_VREF1 7

1

2

3

4

5

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc>

Custom

<Doc>

Custom

<Doc>

Custom

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

34 36

34 36

34 36

<RevCode>

<RevCode>

<RevCode>

www.vinafix.vn

A B C D E F G H

Page35 : FBC-1 Partition

CMD-Addr Map
BGA136 ADDR

CMD1 RAS*
CMD10 CAS*
CMD11 WE*

1

IN
IN

CMD7 CS1*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0 CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

2

DDR3:

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6

FBC_CMD8
FBC_CMD9

3

FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25

4

FBC_CMD[6..0]

0
1
2
3
4
5
6

FBC_CMD[25..8]

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

BI

BI

BI

BI

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

FBC_D[63..0]

FBC_DQM[7..0]

FBC_DQS_RN[7..0]

FBC_DQS_WP[7..0]

FBC_CMD[6..0] 4,9

FBC_CMD[25..8] 4,9

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

1

FBC_CMD274,9 FBC_CMD274,9

FBC_CMD27 FBC_CMD27

10

FBC_CS1 FBC_CS1

11

FBC_CMD18 FBC_CMD18

7

FBC_CMD10 FBC_CMD10

19

FBC_CMD0 FBC_CMD5

25

FBC_CMD2 FBC_CMD13

22

FBC_CMD21

24

FBC_CMD20

0

FBC_CMD19

2

FBC_CMD25

21

FBC_CMD22 FBC_CMD4

16

FBC_CMD9 FBC_CMD9

23

FBC_CMD17 FBC_CMD17

20

FBC_CMD24 FBC_CMD6

17

FBC_CMD23 FBC_CMD23

9

FBC_CMD16 FBC_CMD16

12

FBC_CMD3 FBC_CMD3

3

FBC_CMD12 FBC_CMD12

27

FBC_CMD1 FBC_CMD1

18

FBC_CMD11 FBC_CMD11
FBC_CLK0
FBC_CLK0*

14

FBC_CMD14 FBC_CMD14
FBC_CMD_SENC0 FBC_CMD_SENC1

FBVDDQ

15

FBC_CMD15 FBC_CMD15 FBC_CMD15

4

FBVDDQ

4

C145

C145
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

GND

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3

FBC_DQM5
FBC_DQM6
FBC_DQM7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

M13E

M13E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

H3

RAS

F4

CAS

H9

WE

F9

CS0

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

H10

BA2

H4

CKE

J11

CLK

J10

CLK

J2

NC/RFU

J3

A12 (32Mx32)

V4

SEN (GND)

V9

RESET

A9

MF (GND)

A4

ZQ

FBC_ZQ0_1

R137

R137
240

240

5%

5%

0603

0603

COMMON

COMMON

GND

K1

VDDA (VDD)

K12

VDDA (VDD)

C146

C146
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

J1

VSSA (GND)

J12

VSSA (GND)

FBC_D5

0

FBC_D7

1

FBC_D3

2

FBC_D2

3

FBC_D0

4

FBC_D1

5

FBC_D4

6

FBC_D6

7

FBC_DQM0
FBC_DQS_RN0
FBC_DQS_WP0

FBC_D33

32
33
34
35
36
37
38
39

FBC_D36
FBC_D32
FBC_D35
FBC_D34
FBC_D38
FBC_D39
FBC_D37

FBC_DQM4
FBC_DQS_RN4
FBC_DQS_WP4

M10
R10

L10
N11
M11
R11

T10

T11
N10

P10

P11

M13B

M13B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

B3

DQ0

B2

DQ1

F3

DQ2

G3

DQ3

E2

DQ4

F2

DQ5

C2

DQ6

C3

DQ7

E3

DQM

D3

RDQS

D2

WDQS

M14A

M14A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

NONMIRRORED

NONMIRRORED

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VREF
VREF

FBVDDQ

F1
M1
A2
V2
A11
V11
F12
M12

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2

GND

B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS
VSS
VSS

GND

G12
L12

FBC_VREF2 FBC_VREF3

H1
H12

VREF = FBVDDQ * R2/(R1 + R2)

FBC_D12

8

FBC_D13

9

FBC_D11

10

FBC_D10

11

FBC_D14

12

FBC_D8

13

FBC_D15

14

FBC_D9

15

FBC_DQM1
FBC_DQS_RN1
FBC_DQS_WP1

FBC_D42

40

FBC_D40

41

FBC_D44

42

FBC_D43

43

FBC_D41

44

FBC_D47

45

FBC_D45

46

FBC_D46

47

FBC_DQM5
FBC_DQS_RN5
FBC_DQS_WP5

FBC_VREF2 9

FBC_VREF0 FBC_VREF1

FBC_VREF0 9

VREF = 0.70 * FBVDDQDDR3:

1.26V = 1.8V * 1.18K/(511K + 1.18K)

M13A

M13A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

E11

DQ0

F11

DQ1

G10

DQ2

F10

DQ3

C11

DQ4

B10

DQ5

C10

DQ6

B11

DQ7

E10

DQM

D10

RDQS

D11

WDQS

M14E

M14E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

L3

DQ0

M3

DQ1

M2

DQ2

N2

DQ3

R3

DQ4

T2

DQ5

R2

DQ6

T3

DQ7

N3

DQM

P3

RDQS

P2

WDQS

C GE

IN
IN

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

ASSEMBLY
PAGE DETAIL

CMD-Addr Map
BGA136 ADDR

CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD7 CS1*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>

CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

FBC_CMD_SENC19FBC_CMD_SENC09

ZQ = 6x desired output

DDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

1
10

FBC_CS14FBC_CS14

11
7

19
25
4

FBC_CMD21

6

FBC_CMD20

5

FBC_CMD19

13

FBC_CMD25

21
16
23
20
17
9

12
3
27

18

FBC_CLK1
FBC_CLK1*

14

15

GND

FBVDDQ

C149

C149
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

GND

M13D

M13D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136

COMMON

FBC_D19
FBC_D23
FBC_D18
FBC_D22
FBC_D17
FBC_D16
FBC_D20
FBC_D21

FBC_DQM2
FBC_DQS_RN2
FBC_DQS_WP2

FBC_D51
FBC_D55
FBC_D54
FBC_D52
FBC_D53
FBC_D50
FBC_D49
FBC_D48

FBC_DQM6
FBC_DQS_RN6
FBC_DQS_WP6

COMMON

T3

DQ0

R3

DQ1

T2

DQ2

R2

DQ3

N2

DQ4

M2

DQ5

M3

DQ6

L3

DQ7

N3

DQM

P3

RDQS

P2

WDQS

M14C

M14C

BGA_0136_P080_140X120

BGA_0136_P080_140X120

BGA136

BGA136

COMMON

COMMON

F10

DQ0

C10

DQ1

B11

DQ2

B10

DQ3

C11

DQ4

F11

DQ5

E11

DQ6

G10

DQ7

E10

DQM

D10

RDQS

D11

WDQS

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC Partition

FBC_D29

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

FBC_D28
FBC_D26
FBC_D24
FBC_D30
FBC_D31
FBC_D27
FBC_D25

FBC_DQM3FBC_DQM4
FBC_DQS_RN3
FBC_DQS_WP3

FBC_D63
FBC_D62
FBC_D61
FBC_D56
FBC_D59
FBC_D60
FBC_D58
FBC_D57

FBC_DQM7
FBC_DQS_RN7
FBC_DQS_WP7

M11
N11

T11
T10

M10

L10
R11
R10

N10

P10

P11

G3
E2

B3
C2
B2
C3

E3
D3
D2

GND

M13C

M13C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M14B

M14B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1

F2

DQ2

F3

DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M14D

M14D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

H10

RAS

F9

CAS

H4

WE

F4

CS0

K9

A0

H11

A1

K10

A2

M9

A3

K4

A4

H2

A5

K3

A6

L4

A7

K2

A8/AP

M4

A9

K11

A10

L9

A11

G9

BA0

G4

BA1

H3

BA2

H9

CKE

J11

CLK

J10

CLK

J2

NC/RFU

J3

A12 (32Mx32)

V4

SEN (GND)

V9

RESET

A9

MF (GND)

A4

ZQ

FBC_ZQ1_1

R142

R142
240

240

5%

5%

0603

0603

COMMON

COMMON

K1

VDDA (VDD)

K12

VDDA (VDD)

C150

C150
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

J1

VSSA (GND)

J12

VSSA (GND)

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

MIRRORED

MIRRORED

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VREF
VREF

FBVDDQ

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2

GND

B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS
VSS
VSS

GND

G12
L12

H1
H12

FBC_VREF3 9
FBC_VREF1 9

VREF = FBVDDQ * R2/(R1 + R2)

DDR3:

VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511K + 1.18K)

1

2

3

4

5

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc>

Custom

<Doc>

Custom

<Doc>

Custom

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

35 36

35 36

35 36

<RevCode>

<RevCode>

<RevCode>

www.vinafix.vn

A B C D E F G H

Page36: FBD-1 Partition

M15E

CMD-Addr Map

BGA136 ADDR

CMD1 RAS*
CMD10 CAS*

FBD_D[63..0]

FBD_DQM[7..0]

FBD_DQS_RN[7..0]

FBD_DQS_WP[7..0]

CMD11 WE*
CMD7 CS1*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

FBD_CMD[6..0] 4,11

FBD_CMD[25..8] 4,11

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

1

IN
IN

2

FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6

FBD_CMD8
FBD_CMD9

3

FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25

4

FBD_CMD_SEND011 FBD_CMD_SEND111

DDR3: ZQ = 6x desired output

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

FBD_CMD[6..0]

0
1
2
3
4
5
6

FBD_CMD[25..8]

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

BI

BI

BI

BI

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

1

FBD_CMD274,11 FBD_CMD274,11

FBD_CMD27 FBD_CMD27

10

FBD_CS1 FBD_CS1

FBD_CS14

11

FBD_CMD18 FBD_CMD18

7

FBD_CMD10 FBD_CMD10

19

FBD_CMD0 FBD_CMD5

25

FBD_CMD2 FBD_CMD13

22

FBD_CMD21

24

FBD_CMD20

0

FBD_CMD19

2

FBD_CMD25

21

FBD_CMD22 FBD_CMD4

16

FBD_CMD9 FBD_CMD9

23

FBD_CMD17 FBD_CMD17

20

FBD_CMD24 FBD_CMD6

17

FBD_CMD23 FBD_CMD23

9

FBD_CMD16 FBD_CMD16

12

FBD_CMD3 FBD_CMD3

3

FBD_CMD12 FBD_CMD12

27

FBD_CMD1 FBD_CMD1

18

FBD_CMD11 FBD_CMD11

FBD_CLK0
FBD_CLK0*

14

FBD_CMD14 FBD_CMD14
FBD_CMD_SEND0 FBD_CMD_SEND1

FBVDDQ

15

FBD_CMD15 FBD_CMD15 FBD_CMD15

4

FBVDDQ

4

C153

C153
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

GND

FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3

FBD_DQM5
FBD_DQM6
FBD_DQM7

FBD_DQS_RN0
FBD_DQS_RN1
FBD_DQS_RN2
FBD_DQS_RN3
FBD_DQS_RN4
FBD_DQS_RN5
FBD_DQS_RN6
FBD_DQS_RN7

FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7

M15E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

H3

RAS

F4

CAS

H9

WE

F9

CS0

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

H10

BA2

H4

CKE

J11

CLK

J10

CLK

J2

NC/RFU

J3

A12 (32Mx32)

V4

SEN (GND)

V9

RESET

A9

MF (GND)

A4

ZQ

FBD_ZQ0_1

R24

R24
240

240

5%

5%

0603

0603

COMMON

COMMON

GND

K1

VDDA (VDD)

K12

VDDA (VDD)

C154

C154
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

J1

VSSA (GND)

J12

VSSA (GND)

FBD_D2

0
1
2
3
4
5
6
7

32
33
34
35
36
37
38
39

FBD_D1
FBD_D0
FBD_D4
FBD_D6
FBD_D7
FBD_D5
FBD_D3

FBD_DQM0
FBD_DQS_RN0
FBD_DQS_WP0

FBD_D37
FBD_D36
FBD_D39
FBD_D34
FBD_D35
FBD_D33
FBD_D38
FBD_D32

FBD_DQM4
FBD_DQS_RN4
FBD_DQS_WP4

F10
F11
G10
C10
C11
E11
B11
B10

E10
D10
D11

M15B

M15B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M16A

M16A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

T2

DQ0

T3

DQ1

M2

DQ2

M3

DQ3

L3

DQ4

R2

DQ5

R3

DQ6

N2

DQ7

N3

DQM

P3

RDQS

P2

WDQS

NONMIRRORED

NONMIRRORED

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VREF
VREF

FBVDDQ

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2

GND

B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS
VSS
VSS

GND

G12
L12

FBD_VREF2 FBD_VREF3

H1

FBD_VREF0 FBD_VREF1

H12

VREF = FBVDDQ * R2/(R1 + R2)

DDR3:

VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBD_D10

8

FBD_D9

9

FBD_D8

10

FBD_D15

11

FBD_D11

12

FBD_D14

13

FBD_D12

14

FBD_D13

15

FBD_DQM1
FBD_DQS_RN1
FBD_DQS_WP1

FBD_D47

40

FBD_D45

41

FBD_D43

42

FBD_D44

43

FBD_D41

44

FBD_D40

45

FBD_D46

46

FBD_D42

47

FBD_DQM5
FBD_DQS_RN5
FBD_DQS_WP5

G3

F2
F3
B3

C3

B2

C2

E2

E3
D3
D2

N11
R11

M10

L10
T10
T11
R10

M11

N10
P10
P11

C GE

FBD_VREF2 11
FBD_VREF0 11

M15A

M15A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M16E

M16E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

ASSEMBLY
PAGE DETAIL

CMD-Addr Map
BGA136 ADDR

CMD1 RAS*
CMD10 CAS*
CMD11 WE*

FBD_CS14

CMD7 CS1*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

IN
IN

DDR3: ZQ = 6x desired output

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

M15D

M15D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

T10
R10
T11
M10
M11
L10
R11
N11

N10

P10
P11

C3
F3

G3

C2
B2
F2
E2
B3

E3
D3
D2

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M16C

M16C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

FBD_D25

24

FBD_D30

25

FBD_D24

26

FBD_D26

27

FBD_D31

28

FBD_D29

29

FBD_D28

30

FBD_D27

31

FBD_DQM3FBD_DQM4
FBD_DQS_RN3
FBD_DQS_WP3

FBD_D59

56

FBD_D57

57

FBD_D61

58

FBD_D56

59

FBD_D60

60

FBD_D58

61

FBD_D62

62

FBD_D63

63

FBD_DQM7
FBD_DQS_RN7
FBD_DQS_WP7

FBD_D18

16

FBD_D16

17

FBD_D19

18

FBD_D23

19

FBD_D22

20

FBD_D21

21

FBD_D17

22

FBD_D20

23

FBD_DQM2
FBD_DQS_RN2
FBD_DQS_WP2

FBD_D51

48

FBD_D49

49

FBD_D53

50

FBD_D48

51

FBD_D52

52

FBD_D50

53

FBD_D54

54

FBD_D55

55

FBD_DQM6
FBD_DQS_RN6
FBD_DQS_WP6

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBD Partition

1
10
11
7

19
25
4
6
5
13
21
16
23
20
17
9

12
3
27

18

14

15

FBVDDQ

GND

FBD_CMD21
FBD_CMD20
FBD_CMD19
FBD_CMD25

C157

C157
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

FBD_CLK1
FBD_CLK1*

GND

R3
R2

T3
T2

N2

L3
M2
M3

N3
P3
P2

C11
F10
F11
C10
B11
G10
E11
B10

E10
D10
D11

FBD_ZQ1_1

R149

R149
240

240

5%

5%

0603

0603

COMMON

COMMON

GND

C158

C158
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

M15C

M15C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M16B

M16B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

H10

F9
H4
F4

K9
H11
K10

M9

K4

H2

K3

L4

K2

M4
K11

L9

G9

G4

H3

H9
J11
J10

J2

J3

V4

V9

A9

A4

K1
K12

J1
J12

M16D

M16D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

RAS
CAS
WE
CS0

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11

BA0
BA1
BA2

CKE
CLK
CLK

NC/RFU
A12 (32Mx32)
SEN (GND)

RESET

MF (GND)

ZQ

VDDA (VDD)
VDDA (VDD)

VSSA (GND)
VSSA (GND)

FBVDDQ

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

MIRRORED

MIRRORED

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

GND

B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10

GND

G12
L12

H1
H12

FBD_VREF3 11
FBD_VREF1 11

VREF = FBVDDQ * R2/(R1 + R2)

DDR3: VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

1

2

3

4

5

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc>

Custom

<Doc>

Custom

<Doc>

Custom

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

36 36

36 36

36 36

<RevCode>

<RevCode>

<RevCode>

www.vinafix.vn

A B C D E F G H

J501

J501

?

Page2: PCI Express JTAG

12V

C855

C855

C856

C856

C857

C857
.1UF

COMMON

COMMON

.1UF

4.7UF

4.7UF

16V

16V

16V

16V

10%

10%

10%

10%
X7R

X7R

X5R

X5R

1206

1206

0402

0402

COMMON

COMMON

COMMON

COMMON

GND

3V3_AUX

C31

.1UF

C31

.1UF

0402

0402

16V

16V

10%

10%
X7R

X7R

4.7UF

4.7UF

16V

16V

10%

10%
X5R

X5R

3V3

1206

1206

COMMON

COMMON

C846

C846

C847

4.7UF

4.7UF

6.3V

6.3V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

C847
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

1

GND

2

GND

3

PEX_PRSNT*

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

CN2

CN2

CON_X16

CON_X16
COMMON

COMMON

B1

+12V

B2

+12V

A2

+12V

A3

+12V

B3

+12V/RSVD

B8

+3V3

A9

+3V3

A10

+3V3

B10

+3V3AUX

A1

PRSNT1

B17

PRSNT2

B12

RSVD

B4

GND

A4

GND

B7

GND

A12

GND

B13

GND

A15

GND

B16

GND

B18

GND

A18

GND

GND

B31

PRSNT2

A19

RSVD

B30

RSVD

A32

RSVD

A20

GND

B21

GND

B22

GND

A23

GND

A24

GND

B25

GND

B26

GND

A27

GND

A28

GND

B29

GND

A31

GND

B32

GND

B48

PRSNT2

A33

RSVD

A34

GND

B35

GND

B36

GND

A37

GND

A38

GND

B39

GND

B40

GND

A41

GND

A42

GND

B43

GND

B44

GND

A45

GND

A46

GND

B47

GND

B49

GND

A49

GND

GND

B81

PRSNT2

A50

RSVD

B82

RSVD

A51

GND

B52

GND

B53

GND

A54

GND

A55

GND

B56

GND

B57

GND

A58

GND

A59

GND

B60

GND

B61

GND

A62

GND

A63

GND

B64

GND

B65

GND

A66

GND

A67

GND

B68

GND

B69

GND

A70

GND

A71

GND

B72

GND

B73

GND

A74

GND

A75

GND

B76

GND

B77

GND

A78

GND

A79

GND

B80

GND

A82

GND

GND

END OF X1

END OF X1

END OF X4

END OF X4

END OF X8

END OF X8

END OF X16

END OF X16

TRST* JTAG1

TCLK JTAG2

TDI JTAG3
TDO JTAG4
TMS JTAG5

SMCLK
SMDAT

PERST

REFCLK
REFCLK

PERP0

PERN0

PETP0
PETN0

PERP1

PERN1

PETP1
PETN1

PERP2

PERN2

PETP2
PETN2

PERP3

PERN3

PETP3
PETN3

PERP4

PERN4

PETP4
PETN4

PERP5

PERN5

PETP5
PETN5

PERP6

PERN6

PETP6
PETN6

PERP7

PERN7

PETP7
PETN7

PERP8

PERN8

PETP8
PETN8

PERP9

PERN9

PETP9
PETN9

PERP10
PERN10

PETP10

PETN10

PERP11
PERN11

PETP11

PETN11

PERP12
PERN12

PETP12

PETN12

PERP13
PERN13

PETP13

PETN13

PERP14
PERN14

PETP14

PETN14

PERP15
PERN15

PETP15

PETN15

PEX_TRST*

B9

PEX_TCLK

A5

PEX_TDI

A6

PEX_TDO

A7

PEX_TMS

A8

PEX_SMCLK

B5

PEX_SMDAT

B6

PEX_WAKE*

B11

WAKE

PEX_RST*

A11

PEX_REFCLK

A13

PEX_REFCLK*

A14

PEX_TXX0

A16

PEX_TXX0*

A17

PEX_RX0

B14

PEX_RX0*

B15

PEX_TXX1

A21

PEX_TXX1*

A22

PEX_RX1

B19

PEX_RX1*

B20

PEX_TXX2

A25

PEX_TXX2*

A26

PEX_RX2

B23

PEX_RX2*

B24

PEX_TXX3

A29

PEX_TXX3*

A30

PEX_RX3

B27

PEX_RX3*

B28

PEX_TXX4

A35

PEX_TXX4*

A36

PEX_RX4

B33

PEX_RX4*

B34

PEX_TXX5

A39

PEX_TXX5*

A40

PEX_RX5

B37

PEX_RX5*

B38

PEX_TXX6

A43

PEX_TXX6*

A44

PEX_RX6

B41

PEX_RX6*

B42

PEX_TXX7

A47

PEX_TXX7*

A48

PEX_RX7

B45

PEX_RX7*

B46

PEX_TXX8

A52

PEX_TXX8*

A53

PEX_RX8

B50

PEX_RX8*

B51

PEX_TXX9

A56

PEX_TXX9*

A57

PEX_RX9

B54

PEX_RX9*

B55

PEX_TXX10

A60

PEX_TXX10*

A61

PEX_RX10

B58

PEX_RX10*

B59

PEX_TXX11

A64

PEX_TXX11*

A65

PEX_RX11

B62

PEX_RX11*

B63

PEX_TXX12

A68

PEX_TXX12*

A69

PEX_RX12

B66

PEX_RX12*

B67

PEX_TXX13

A72

PEX_TXX13*

A73

PEX_RX13

B70

PEX_RX13*

B71

PEX_TXX14

A76

PEX_TXX14*

A77

PEX_RX14

B74

PEX_RX14*

B75

PEX_TXX15

A80

PEX_TXX15*

A81

PEX_RX15

B78

PEX_RX15*

B79

PEX_WAKE* 29

C822

COMMON

COMMON

C818

COMMON

COMMON

C804

C804

COMMON

COMMON

C795

COMMON

COMMON

C782

C782

COMMON

COMMON

C771

C771

COMMON

COMMON

C761

C761

COMMON

COMMON

C734

COMMON

COMMON

C716

COMMON

COMMON

C687

C687

COMMON

COMMON

C657

C657

COMMON

COMMON

C638

C638

COMMON

COMMON

C622

C622

COMMON

COMMON

C614

C614

COMMON

COMMON

C612

C612

COMMON

COMMON

C610

C610

COMMON

COMMON

OUT
OUT

0402

0402

X5R

X5R

0402 10V

0402 10V

X5R

X5R

0402 10V

0402 10V

X5R

X5R

X5R

X5R

X5R

X5R

0402

0402

X5R

X5R

X5R

X5R

0402

0402

X5R

X5R

X5R

X5R

0402

0402

X5R

X5R

0402

0402

X5R

X5R

0402

0402

X5R

X5R

X5R

X5R

X5R

X5R

X5R

X5R

X5R

X5R

R717

R717
0

0

5%

5%
0402

0402
COMMON

COMMON

(OPT)

29

OUT

.1UFC822

.1UF

C819

C819

10V

10V
10%

10%

0402 10V

0402 10V

.1UFC818

.1UF

C816

10%

10%

.1UF

.1UF

C803

C803

10%

10%

.1UFC795

.1UF

C793

C793

10V0402

10V0402
10%

10%

0402

0402

.1UF

.1UF

C779

10V0402

10V0402
10%

10%

.1UF

.1UF

C766

C766

10V

10V
10%

10%

0402

0402

.1UF

.1UF

C753

C753

10V0402

10V0402
10%

10%

0402

0402

.1UFC734

.1UF

C727

C727

10V

10V
10%

10%

.1UFC716

.1UF

C707

C707

10V0402

10V0402
10%

10%

0402 10V

0402 10V

.1UF

.1UF

C683

10V

10V
10%

10%

0402

0402

.1UF

.1UF

C652

C652

10V

10V
10%

10%

0402

0402

.1UF

.1UF

C632

C632

10V

10V
10%

10%

.1UF

.1UF

C621

C621

10V0402

10V0402
10%

10%

0402

0402

.1UF

.1UF

C613

C613

10V0402

10V0402
10%

10%

.1UF

.1UF

C611

C611

10V0402

10V0402
10%

10%

.1UF

.1UF

C609

C609

10V0402

10V0402
10%

10%

R693

0

R693

0

JTAG_TRST*

(OPT)

COMMON

COMMON

0402

0402

5%

5%

R697

05%R697

0

JTAG_TCLK

(OPT)

0402 COMMON

0402 COMMON

5%

R716

0R716

0

(OPT)

0402 COMMON

0402 COMMON

5%

5%

R718

0

R718

0

(OPT)

COMMON

COMMON

0402

0402

5%

5%

R713

0

R713

0

JTAG_TMS

(OPT)

COMMON

COMMON

0402

0402

5%

5%

G1A

G1A

BGA_1504_P080_350X350

BGA_1504_P080_350X350
COMMON

COMMON

1/19 PCI_EXPRESS

1/19 PCI_EXPRESS

AW10

PEX_RST

AY10

PEX_CLKREQ

AW11

PEX_REFCLK

AW12

AW13
AW14

AW15

AW16

AW17
AW18

AW19

AW20
AW21

AW22

AW23
AW24

AW25
AW26

AW27

PEX_REFCLK

AU13

PEX_TX0

AV13

PEX_TX0

AY12

PEX_RX0

BA12

PEX_RX0

PEX_TX1
PEX_TX1

BB12

PEX_RX1

BB13

PEX_RX1

PEX_TX2

AV15

PEX_TX2

BA13

PEX_RX2

AY13

PEX_RX2

AV16

PEX_TX3
PEX_TX3

AY15

PEX_RX3

BA15

PEX_RX3

PEX_TX4
PEX_TX4

BB15

PEX_RX4

BB16

PEX_RX4

AV18

PEX_TX5

AU18

PEX_TX5

BA16

PEX_RX5

AY16

PEX_RX5

AV19

PEX_TX6
PEX_TX6

AY18

PEX_RX6

BA18

PEX_RX6

PEX_TX7
PEX_TX7

BB18

PEX_RX7

BB19

PEX_RX7

AV21

PEX_TX8

AU21

PEX_TX8

BA19

PEX_RX8

AY19

PEX_RX8

AV22

PEX_TX9
PEX_TX9

AY21

PEX_RX9

BA21

PEX_RX9

PEX_TX10
PEX_TX10

BB21

PEX_RX10

BB22

PEX_RX10

AV24

PEX_TX11

AU24

PEX_TX11

BA22

PEX_RX11

AY22

PEX_RX11

AU25

PEX_TX12

AV25

PEX_TX12

AY24

PEX_RX12

BA24

PEX_RX12

PEX_TX13
PEX_TX13

BB24

PEX_RX13

BB25

PEX_RX13

PEX_TX14

AV27

PEX_TX14

BA25

PEX_RX14

AY25

PEX_RX14

AU27

PEX_TX15

AT27

PEX_TX15

AY27

PEX_RX15

BA27

PEX_RX15

PEX_TX0

.1UF

.1UF

PEX_TX0*

10%

10%

COMMON

COMMON

X5R

X5R

PEX_TX1

.1UFC816

.1UF

PEX_TX1*

10%

10%

0402

10V

0402

10V

COMMON

COMMON

X5R

X5R

PEX_TX2

.1UF

.1UF

PEX_TX2*

10%

10%

10V0402

10V0402

COMMON

COMMON

X5R

X5R

PEX_TX3

.1UF

.1UF

PEX_TX3*

10%

10%

10V

10V

COMMON

COMMON

X5R

X5R

PEX_TX4

.1UFC779

.1UF

PEX_TX4*

10%

10%

10V0402

10V0402

COMMON

COMMON

X5R

X5R

PEX_TX5

.1UF

.1UF

PEX_TX5*

10%

10%

10V

10V

COMMON

COMMON

X5R

X5R

PEX_TX6

.1UF

.1UF

PEX_TX6*

10%

10%

10V

10V

COMMON

COMMON

X5R

X5R

PEX_TX7

.1UF

.1UF

PEX_TX7*

10%

10%

10V0402

10V0402

COMMON

COMMON

X5R

X5R

PEX_TX8

.1UF

.1UF

PEX_TX8*

10%

10%

COMMON

COMMON

X5R

X5R

PEX_TX9

.1UFC683

.1UF

PEX_TX9*

10%

10%

10V

10V

COMMON

COMMON

X5R

X5R

PEX_TX10

.1UF

.1UF

PEX_TX10*

10%

10%

10V

10V

COMMON

COMMON

X5R

X5R

PEX_TX11

.1UF

.1UF

PEX_TX11*

10%

10%

10V0402

10V0402

COMMON

COMMON

X5R

X5R

PEX_TX12

.1UF

.1UF

PEX_TX12*

10%

10%

10V

10V

COMMON

COMMON

X5R

X5R

PEX_TX13

.1UF

.1UF

PEX_TX13*

10%

10%

10V0402

10V0402

COMMON

COMMON

X5R

X5R

PEX_TX14

.1UF

.1UF

PEX_TX14*

10%

10%

10V0402

10V0402

COMMON

COMMON

X5R

X5R

PEX_TX15

.1UF

.1UF

PEX_TX15*

10%

10%

10V0402

10V0402

COMMON

COMMON

X5R

X5R

C GE

3V3_F

TMS2TRST*
TDI4GND
VCC
TDO8TCK

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

VDD33
VDD33
VDD33
VDD33
VDD33

VDD_SENSE
GND_SENSE

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT

PEX_PLLVDD

TESTMODE

PEX_CAL_PD_VDDQ

PEX_CAL_PU_GND

PEX_TERMP

ASSEMBLY
PAGE DETAIL

?
?

?
?

?
CON_HDR_002X004_TH

CON_HDR_002X004_TH
COMMON

COMMON

1
3

KEY

KEY

5
7

AT18
AT24
AT25
AU15
AU16
AU19
AU22

AM17
AM18
AM19
AM20
AM24
AM25
AM26
AM27
AM28
AP18
AP19
AP21
AP22
AP24
AP25
AP27
AR15
AR16
AR18
AR19
AR21
AR22
AR24
AR25
AR27
AT15
AT16
AT19
AT21
AT22

L11
L12
L13
M11
N11

AJ22
AJ21

AP16
AP17

AM16

BB27

AM21
AM22

AM23

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PCI Express

3V3_F

GND

Place near balls

C705

C705
.1UF

.1UF

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

C675

C675
.1UF

.1UF

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

Matching Rule of Thumb

4 inch from Top of Gold Fingers to GPU
*2 inch Lane to Lane Skew

*No real Skew rule, but reducing the skew will minimize latency

Place near balls

C748

C748
.47UF

.47UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

NVVDD_SENSE_GPU
NVVDD_GND_SENSE_GPU

PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*

12MIL

PEX_PLLVDD

GPU_TESTMODE

12MIL

PEX_CAL_PD_VDDQ
PEX_CAL_PU_GND

12MIL

PEX_TERMP

12MIL

C744

C744
1UF

1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

R71

R71

0402

0402

R715

R715
10K

10K

5%

5%
0402

0402
COMMON

COMMON

C701

C701
.1UF

.1UF

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

C668

C668
.1UF

.1UF

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

5%

5%

R626

R626

0402

0402

R714

R714
10K

10K

5%

5%
0402

0402
COMMON

COMMON

R694

R694
10K

10K

5%

5%
0402

0402
COMMON

COMMON

GND

C688

C688
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

C696

C696
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

C785

C785
.1UF

.1UF

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

OUT
OUT

SHOULD BE PLACED ON THE BOTTOM LAYER

SHOULD BE PLACED ON THE BOTTOM LAYER

R630

200

R630

200

COMMON

0402

COMMON

0402

5%

5%

10K

10K

COMMON

COMMON

2.49K

2.49K

COMMON

COMMON

1%

1%

R695

R695
180

180

5%

5%
0402

0402
COMMON

COMMON

R696

R696
270

270

5%

5%
0402

0402
COMMON

COMMON

R627

R627

R625

0402

0402

JTAG_TCLKJTAG_TDI

JTAG_TMS

JTAG_TDIJTAG_TDO

JTAG_TDO

JTAG_TRST*

C682

C682
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

C676

C676
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

VDD33

C751

C751
.47UF

.47UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

2.49K

2.49K

COMMON0402

COMMON0402

1%

1%

2.49KR625

2.49K

COMMON

COMMON

1%

1%

C717

C717
.1UF

.1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

C736

C736
1UF

1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

PEX_VDD

GND

C660

C660

4.7UF

4.7UF

6.3V

6.3V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

C728

C728

4.7UF

4.7UF

6.3V

6.3V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

C689

C689
1UF

1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

OUT
OUT
OUT

IN

OUT

1

PEX_VDD

C661

C661
10UF

10UF

6.3V

6.3V

20%

20%
X5R

X5R

0805

0805

COMMON

COMMON

GND

GND

C754

C754
.1UF

.1UF

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

C54

C54
10UF

10UF

6.3V

6.3V

20%

20%
X5R

X5R

0805

0805

COMMON

COMMON

3V3_F

C780

C780
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

GND

2

3

4

PEX_VDD

LB502

10nH

LB502

10nH

COMMON

IND_SMD_0402

COMMON

IND_SMD_0402

C708

C708
1UF

1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

C673

C673

4.7UF

4.7UF

6.3V

6.3V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

GND

5

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc>

Custom

<Doc>

Custom

<Doc>

Custom

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

<RevCode>

<RevCode>

<RevCode>

236

236

236

www.vinafix.vn

A B C D E F G H

Page3: MEMORY: GPU Partition A/B

1

FBA_D[63..0]

BI

2

3

FBA_DQM[7..0]

OUT

FBA_DQS_WP[7..0]

OUT

4

FBA_DQS_RN[7..0]

IN

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBVDDQ

R611

R611
511

511

1%

1%
0402

0402
COMMON

COMMON

R610

5

R610

1.3K

1.3K

1%

1%
0402

0402
COMMON

COMMON

C629

C629
.1UF

.1UF

6.3V

6.3V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

OUT

FB_VREF

AM34

AW33
AW36

AW28

AW31

AW29

AM39

AW32

AM36

AW34

AW35

AL34
AK35
AK36

AJ34
AH34
AH35

AJ36
AK37
AL39
AL41
AL42
AK42

AJ39
AH39
AH41
AH42
AN35
AP36
AP37
AR37

AL35
AL36
AL37
AP41
AP42
AN39
AN40
AN41
AN42
AR40
AT39
AR31
AP32
AR33
AT31
AT34
AU34
AU35
AU31
BB33
BA33
AY33
BA34
BB34

AY35
AU30
AP28
AP31
AR28

AP29
AR30
AT30

BA31
BB31
BB30

BB28
BA28
AY28

AJ37
AP35

AP40
AR34
AY34
AU29

AH36
AK41

AP38
AT33
AV34
AT28
AY30

AH37
AK40
AN36
AP39
AT32

AU28
BA30

AH38
AL38
AN38
AR39
AV33

AT29
AV31

L32

G1B

G1B

BGA_1504_P080_350X350

BGA_1504_P080_350X350
COMMON

COMMON

2/19 FBA

2/19 FBA

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7

FB_VREF

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

FBA_DEBUG

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

FBA_WCK0

FBA_WCK0

FBA_WCK1

FBA_WCK1

FBA_WCK2

FBA_WCK2

FBA_WCK3

FBA_WCK3

FB_DLLAVDD0
FB_PLLAVDD0

AA32
AB32
AC32
AD32
AD34
AE32
AF32
AG32
AG34
AK34
AN34
AP30
AP33
J10
J13
J16
J19
J24
J27
J30

AT40
AU38
AT38
BA39
AV37
BB39
AW38
AW42
AW39
AY41
AU39
AV36
BA40
AY39
AU40
BA37
AY36
AY37
AT37
AU36
AV39
AY38
AV40
AU42
AW40
AU41
AW41
BB37
AW37
AY42
BB40

AT36

AT41
AT42
BA36
BB36

AK38
AK39
AM37
AN37
AU32
AU33
AV30
AW30

AH32
AJ32

FBVDDQ

FBA_CMD[6..0]

FBA_CMD0
FBA_CMD1

FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6

FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21

FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25

FBA_CMD27

FBA_DEBUG

FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*

FB_PLLAVDD0

0
1
2
3
4
5
6

FBA_CMD[25..8]

FBA_CS1 33 FBB_CS1 34

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

27

FBA_CMD27 5,33

R618

60.4R618

60.4

COMMON

0402

COMMON

0402

1%

1%

(OPT) (OPT)

OUT
OUT
OUT
OUT

C651

C651
.1UF

.1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

GND

GND

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C GE

G1C

G1C

BGA_1504_P080_350X350

BGA_1504_P080_350X350
COMMON

FBB_D[63..0]

BI

FBA_CMD[6..0] 5,33

5

CMD-Addr Map

BGA136[31..0] BGA136[63..32] ADDR

CMD1 CMD1 RAS*

CMD10 CMD10 CAS*

FBA_CMD[25..8] 5,33

5 7

CMD11 CMD11 WE*

5

CMD8 CMD8 CS0*
CMD19 CMD19 A<0>
CMD25 CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 CMD21 A<6>
CMD16 CMD16 A<7>
CMD23 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD9 CMD9 A<11>
CMD12 CMD12 BA0
CMD3 CMD3 BA1
CMD27 CMD27 BA2
CMD18 CMD18 CKE
CMD15 CMD15 RST

FBB_DQM[7..0]

OUT

FBVDDQ

FBB_DQS_WP[7..0]

OUT

FBB_DQS_RN[7..0]

IN

OUT

C650

C650
1UF

1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

C647

C647
1UF

1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

LB501

120R@100MHzLB501

120R@100MHz

COMMONIND_SMD_0402

COMMONIND_SMD_0402

PEX_VDD

C643

C643

4.7UF

4.7UF

6.3V

6.3V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

GND

ASSEMBLY
PAGE DETAIL

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MEMORY: GPU Partition A/B

COMMON

3/19 FBB

3/19 FBB

C40

FBB_D0

E39

FBB_D1

F37

FBB_D2

H37

FBB_D3

G38

FBB_D4

G39

FBB_D5

G40

FBB_D6

H39

FBB_D7

C41

FBB_D8

D40

FBB_D9

D41

FBB_D10

C42

FBB_D11

D42

FBB_D12

H40

FBB_D13

G41

FBB_D14

G42

FBB_D15

J37

FBB_D16

K37

FBB_D17

J38

FBB_D18

J39

FBB_D19

L36

FBB_D20

M34

FBB_D21

M35

FBB_D22

M36

FBB_D23

J40

FBB_D24

J41

FBB_D25

J42

FBB_D26

K39

FBB_D27

L39

FBB_D28

M38

FBB_D29

M39

FBB_D30

M40

FBB_D31

W35

FBB_D32

W36

FBB_D33

W37

FBB_D34

W38

FBB_D35

AA34

FBB_D36

AA35

FBB_D37

AA36

FBB_D38

AA37

FBB_D39

W40

FBB_D40

AA40

FBB_D41

AA41

FBB_D42

AA42

FBB_D43

AB40

FBB_D44

AB41

FBB_D45

AB42

FBB_D46

AD40

FBB_D47

AB34

FBB_D48

AB35

FBB_D49

AB36

FBB_D50

AB37

FBB_D51

AE35

FBB_D52

AE36

FBB_D53

AE37

FBB_D54

AG36

FBB_D55

AD41

FBB_D56

AD42

FBB_D57

AE38

FBB_D58

AF39

FBB_D59

AE42

FBB_D60

AG40

FBB_D61

AG41

FBB_D62

AG42

FBB_D63

G37

FBB_DQM0

F41

FBB_DQM1

L37

FBB_DQM2

K42

FBB_DQM3

AA38

FBB_DQM4

AC39

FBB_DQM5

AE34

FBB_DQM6

AE41

FBB_DQM7

F39

FBB_DQS_WP0

F40

FBB_DQS_WP1

K35

FBB_DQS_WP2

K41

FBB_DQS_WP3

Y39

FBB_DQS_WP4

AB39

FBB_DQS_WP5

AD36

FBB_DQS_WP6

AE40

FBB_DQS_WP7

F38

FBB_DQS_RN0

E40

FBB_DQS_RN1

K36

FBB_DQS_RN2

K40

FBB_DQS_RN3

W39

FBB_DQS_RN4

AB38

FBB_DQS_RN5

AD35

FBB_DQS_RN6

AE39

FBB_DQS_RN7

H36

FBB_DBI0

F42

FBB_DBI1

L34

FBB_DBI2

K38

FBB_DBI3

AA39

FBB_DBI4

AD39

FBB_DBI5

AG35

FBB_DBI6

AG39

FBB_DBI7

CALIBRATION PIN

FB_CALx_PD_VDDQ

FB_CALx_PU_GND

FB_CALx_TERM_GND

VREF RATIO

0.7 FBVDDQ

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

DDR3

60

40

40

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8

FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30

FBB_DEBUG

FBB_WCK0

FBB_WCK0

FBB_WCK1

FBB_WCK1

FBB_WCK2

FBB_WCK2

FBB_WCK3

FBB_WCK3

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1

FBVDDQ

J33
K34
K9
L17
L18
L19
L20
L23
L24
L25
L26
L27

N41
R39
N42
V37
T41
T42
V38
R38
N40
U39
N39
V40
R41
V39
P39
V36
V41
T39
T38
T35
T36
T40
R37
M41
T37
M42
R36
V35
V42
R42
R40

R34

N37
N38
U34
V34

J35
J36
N35
N36
W41
W42
AD37
AD38

M32

N32

P32

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6

FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25

FBB_CMD27

FBB_DEBUG

FBB_CLK0
FBB_CLK0*

FBB_CLK1*

FBB_CLK1

FBB_CMD[6..0]

0
1
2
3
4
5
6

FBB_CMD[25..8]

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

27

FBB_CMD27 7,34

R616

60.4

R616

60.4

COMMON

0402

COMMON

0402

1%

1%

OUT
OUT
OUT
OUT

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

<Doc>

<Doc>

<Doc>

FBVDDQ

R619 54.9

R619 54.9

04021%COMMON

04021%COMMON

R622

R622

0402

0402

1%

1%

R612

R612

0402

0402

1%

1%

FBB_CMD[6..0] 7,34

FBB_CMD[25..8] 7,34

FBVDDQ

40.2

40.2

COMMON

COMMON

40.2

40.2

COMMON

COMMON

GND

Sheet of

Sheet of

Sheet of

HFDBA

7

7

336

336

336

1

2

3

4

5

<RevCode>

<RevCode>

<RevCode>

www.vinafix.vn

A B C D E F G H

Page4: MEMORY: GPU Partition C/D

1

FBC_D[63..0]

BI

2

3

FBC_DQM[7..0]

OUT

FBC_DQS_WP[7..0]

OUT

4

FBC_DQS_RN[7..0]

IN

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

5

G1D

G1D

BGA_1504_P080_350X350

BGA_1504_P080_350X350
COMMON

COMMON

J21
H21
G21
F21
F18
G18
H18
G16
B16
A16
B19
A19
D17
E18
A18
C16
H24
G24
F24
E24
J22
H22
G22
F22
C24
C22
B22
A22
C21
B21
A21
C19
F34
F33
E34
D34
G32
J31
H31
G31
C34
B34
A34
D33
D32
E31
D31
C31
D39
D38
G36
F35
E36
D36
C36
D35
B40
C39
B39
A40
A39
C35
B36
A36

J18
B18
E22
D20
F32
A33
F36
B37

G19
C18
D23
D21
H33
B33
D37
C37

H19
D18
D24
E21
G33
C33
E37
C38

H16
D16
D22
D19
J32
E33
G35
A37

4/19 FBC

4/19 FBC

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

FBC_DBI0
FBC_DBI1
FBC_DBI2
FBC_DBI3
FBC_DBI4
FBC_DBI5
FBC_DBI6
FBC_DBI7

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30

FBC_DEBUG

FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1

FBC_WCK0

FBC_WCK0

FBC_WCK1

FBC_WCK1

FBC_WCK2

FBC_WCK2

FBC_WCK3

FBC_WCK3

FB_DLLAVDD1

FB_PLLAVDD1

G1E

FBVDDQ

N34
N9
R32
T32
T34
U32
V32
W32
W34
Y32

FBC_CMD0

C25

FBC_CMD1

A27

FBC_CMD2

E25

FBC_CMD3

D30

FBC_CMD4

D28

FBC_CMD5

E28

FBC_CMD6

G27
D27

FBC_CMD8

C30

FBC_CMD9

B28

FBC_CMD10

B25

FBC_CMD11

A30

FBC_CMD12

D26

FBC_CMD13

F27

FBC_CMD14

F25

FBC_CMD15

B31

FBC_CMD16

B30

FBC_CMD17

D29

FBC_CMD18

A28

FBC_CMD19

E27

FBC_CMD20

C27

FBC_CMD21

G28

FBC_CMD22

B27

FBC_CMD23

G25

FBC_CMD24

H27

FBC_CMD25

H25
A25

FBC_CMD27

A31
F28
C28
D25

FBC_CMD[6..0]

0
1
2
3
4
5
6

FBC_CMD[25..8]

FBC_CS1 35 FBD_CS1 36

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

27

9

FBC_CMD27 9,35

FBC_CMD[6..0] 9,35

FBC_CMD[25..8] 9,35

9

CMD-Addr Map

BGA136[31..0] BGA136[63..32] ADDR

CMD1 CMD1 RAS*

CMD10 CMD10 CAS*
CMD11 CMD11 WE*

9

CMD8 CMD8 CS0*
CMD19 CMD19 A<0>
CMD25 CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 CMD21 A<6>
CMD16 CMD16 A<7>
CMD23 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD9 CMD9 A<11>
CMD12 CMD12 BA0
CMD3 CMD3 BA1
CMD27 CMD27 BA2
CMD18 CMD18 CKE
CMD15 CMD15 RST

FBVDDQ

FBC_DEBUG

J28

FBC_CLK0

J26

FBC_CLK0*

J25

FBC_CLK1

F30

FBC_CLK1*

E30

F19
E19
B24
A24
H30
G30
H34
G34

L21
L22

R624

60.41%R624

60.4

COMMON0402

COMMON0402

1%

(OPT) (OPT)

OUT
OUT
OUT
OUT

OUT

LB505

120R@100MHzLB505

120R@100MHz

IND_SMD_0402COMMON

IND_SMD_0402COMMON

C749

C750

C750
1UF

1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

C749
1UF

1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

C692

C692
.1UF

.1UF

6.3V

6.3V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

GND

PEX_VDD

GND

FBD_D[63..0]

BI

FBD_DQM[7..0]

OUT

FBD_DQS_WP[7..0]

OUT

FBD_DQS_RN[7..0]

IN

C758

C758

4.7UF

4.7UF

6.3V

6.3V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63

FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7

FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7

FBD_DQS_RN0
FBD_DQS_RN1
FBD_DQS_RN2
FBD_DQS_RN3
FBD_DQS_RN4
FBD_DQS_RN5
FBD_DQS_RN6
FBD_DQS_RN7

G1E

BGA_1504_P080_350X350

BGA_1504_P080_350X350
COMMON

COMMON

M9
N8
N7

P9
R9
R8

P7
N6
M4
M2
M1
N1

P4
R4
R2
R1

K8

J7

J6
H6

L9
M8
M7
M6

J2

J1

K4

K3

K2

K1
H3
G4

H12
J11
H10
G12

G9

F9

F8

F12
A10
B10
C10

B9

A9

D10

D7
C8

F13
J15
J12
H15
D15
J14
H13
G13
D12
B12
A12
A13
D14
A15
B15
C15

P6

L4

J8

J3
H9
C9

F14
D11

R7
N2

L7

J5

G10

E9

G15
C13

R6
N3

K7

J4

G11

D9

F15
B13

R5
M5

K5
H4

E10

D8

G14
E12

5/19 FBD

5/19 FBD

FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63

FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7

FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7

FBD_DQS_RN0
FBD_DQS_RN1
FBD_DQS_RN2
FBD_DQS_RN3
FBD_DQS_RN4
FBD_DQS_RN5
FBD_DQS_RN6
FBD_DQS_RN7

FBD_DBI0
FBD_DBI1
FBD_DBI2
FBD_DBI3
FBD_DBI4
FBD_DBI5
FBD_DBI6
FBD_DBI7

FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
FBD_CMD7
FBD_CMD8

FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25
FBD_CMD26
FBD_CMD27
FBD_CMD28
FBD_CMD29
FBD_CMD30

FBD_DEBUG

FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1

FBD_WCK0

FBD_WCK0

FBD_WCK1

FBD_WCK1

FBD_WCK2

FBD_WCK2

FBD_WCK3

FBD_WCK3

FB_VDDQ_SENSE

FBD_CMD[6..0]

FBD_CMD[25..8]

FBD_CMD[6..0] 11,36

FBD_CMD[25..8] 11,36

11

FBD_CMD0

G3

FBD_CMD1

F5

FBD_CMD2

G5

FBD_CMD3

B4

FBD_CMD4

E6

FBD_CMD5

A4

FBD_CMD6

D5
D1

FBD_CMD8

D4

FBD_CMD9

C2

FBD_CMD10

F4

FBD_CMD11

E7

FBD_CMD12

B3

FBD_CMD13

C4

FBD_CMD14

F3

FBD_CMD15

B6

FBD_CMD16

C7

FBD_CMD17

C6

FBD_CMD18

G6

FBD_CMD19

F7

FBD_CMD20

E4

FBD_CMD21

C5

FBD_CMD22

E3

FBD_CMD23

F1

FBD_CMD24

D3

FBD_CMD25

F2
D2

FBD_CMD27

A6
D6
C1
A3

0
1
2
3
4
5
6

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

27

FBD_CMD27 11,36

FBVDDQ

FBD_DEBUG

G7

FBD_CLK0

G1

FBD_CLK0*

G2

FBD_CLK1

B7

FBD_CLK1*

A7

N5
N4
L6
K6
F11
F10
E13
D13

FBVDDQ_SENSEFB_PLLAVDD1

J34

R641

60.4

R641

60.4

COMMON

COMMON

0402

0402

1%

1%

OUT
OUT
OUT
OUT

OUT

1

2

11

11

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C GE

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MEMORY: GPU Partition C/D

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc>

Custom

<Doc>

Custom

<Doc>

Custom

Date:

Date:

Date:

Tuesday, February 12, 2008

Tuesday, February 12, 2008

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

436

436

436

<RevCode>

<RevCode>

<RevCode>

A B C D E F G H

Page5: FBA Partition

M6E

R84

R84
240

240

5%

5%

0603

0603

COMMON

COMMON

C72

C72
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7

FBA_DQM0
FBA_DQS_RN0
FBA_DQS_WP0

FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39

FBA_DQM4
FBA_DQS_RN4
FBA_DQS_WP4

H3
F4
H9
F9

K4
H2
K3

M4

K9
H11
K10

L9
K11

M9

K2

L4

G4
G9

H10

H4
J11
J10

J2

J3

V4

V9

A9

A4

K1
K12

J1
J12

M6E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

RAS
CAS
WE
CS0

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11

BA0
BA1
BA2

CKE
CLK
CLK

NC/RFU
A12 (32Mx32)
SEN (GND)

RESET

MF (GND)

ZQ

VDDA (VDD)
VDDA (VDD)

VSSA (GND)
VSSA (GND)

C3
G3
F2
F3
B3
B2
C2
E2

E3
D3
D2

R10
M11
N11
M10
T10
R11
T11
L10

N10
P10
P11

NONMIRRORED

NONMIRRORED

M6A

M6A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M7E

M7E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

FBVDDQ

F1
M1
A2
V2
A11
V11
F12
M12

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10
G12
L12

FBA_VREF0 FBA_VREF1

H1

FBA_VREF2 FBA_VREF3

H12

VREF = FBVDDQ * R2/(R1 + R2)

DDR3:

FBA_D8

8

FBA_D9

9

FBA_D10

10

FBA_D11

11

FBA_D12

12

FBA_D13

13

FBA_D14

14

FBA_D15

15

FBA_DQM1
FBA_DQS_RN1
FBA_DQS_WP1

FBA_D40

40

FBA_D41

41

FBA_D42

42

FBA_D43

43

FBA_D44

44

FBA_D45

45

FBA_D46

46

FBA_D47

47

FBA_DQM5
FBA_DQS_RN5
FBA_DQS_WP5

GND

GND

VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

G10
F11
E11
C10
C11
F10
B10
B11

E10
D10
D11

MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!

Minimize the stub length!!

R80

R80
511

511

0402

0402

COMMON

COMMON

R78

R78

1.3K

1.3K

0402

0402

COMMON

COMMON

M6B

M6B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M7A

M7A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

T2

DQ0

R2

DQ1

L3

DQ2

M3

DQ3

N2

DQ4

M2

DQ5

T3

DQ6

R3

DQ7

N3

DQM

P3

RDQS

P2

WDQS

C GE

CMD-Addr Map

BGA136 ADDR

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

FBA_CMD[6..0] 3,33

FBA_CMD[25..8] 3,33

FBA_D[63..0]

FBA_DQM[7..0]

FBA_DQS_RN[7..0]

FBA_DQS_WP[7..0]

CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

3

GND

3

1

FBA_CMD1 FBA_CMD1

10

FBA_CMD10 FBA_CMD10

11

FBA_CMD11 FBA_CMD11

8

19

FBA_CMD19 FBA_CMD19

25

FBA_CMD25 FBA_CMD25

22

FBA_CMD22

24

FBA_CMD24

0

FBA_CMD0

2

FBA_CMD2

21

FBA_CMD21 FBA_CMD21

16

FBA_CMD16 FBA_CMD16

23

FBA_CMD23 FBA_CMD23

20

FBA_CMD20 FBA_CMD20

17

FBA_CMD17 FBA_CMD17

9

FBA_CMD9 FBA_CMD9

12

FBA_CMD12 FBA_CMD12

3

FBA_CMD3 FBA_CMD3

27

FBA_CMD273,33 FBA_CMD273,33

R1005

R1005
0R

0R

5%

5%
0402

0402
COMMON

COMMON

FBA_CMD27 FBA_CMD27

18

FBA_CMD18 FBA_CMD18
FBA_CLK0
FBA_CLK0*

14

FBA_CMD14 FBA_CMD14
FBA_CMD_SENA0 FBA_CMD_SENA1

15

FBA_CMD15 FBA_CMD15 FBA_CMD15

FBA_ZQ0 FBA_ZQ1

IN

FBA_CMD18

R598

R598

R571

R571

10K

10K

10K

10K

5%

5%

5%

5%

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

GND

GND GND GND

FBVDDQ

3

C81

C81
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

GND

0
1
2
3

FBA_DQM0

0

FBA_DQM1

1

FBA_DQM2

2

FBA_DQM3

3
4

FBA_DQM5

5

FBA_DQM6

6

FBA_DQM7

7

FBA_DQS_RN0

0

FBA_DQS_RN1

1

FBA_DQS_RN2

2

FBA_DQS_RN3

3

FBA_DQS_RN4

4

FBA_DQS_RN5

5

FBA_DQS_RN6

6

FBA_DQS_RN7

7

FBA_DQS_WP0

0

FBA_DQS_WP1

1

FBA_DQS_WP2

2

FBA_DQS_WP3

3

FBA_DQS_WP4

4

FBA_DQS_WP5

5

FBA_DQS_WP6

6

FBA_DQS_WP7

7

4
5
6
7

32
33
34
35
36
37
38
39

FBVDDQ

1

OUT

C574

C574
.01UF

.01UF

25V

25V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

GND

MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!

2

3

Minimize the stub length!!

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6

FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25

4

R581

R581
0

0

5%

5%
0402

0402
COMMON

COMMON

(OPT) (OPT)

FBA_CLK0_TERM

R578

R578

R577

R577

40.2

40.2

40.2

40.2

1%

1%

1%

1%

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

IN
IN

FBA_CMD_SENA033 FBA_CMD_SENA133

DDR3:

FBA_CMD[6..0]

0
1
2
3
4
5
6

FBA_CMD[25..8]

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

BI

BI

BI

BI

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

FBVDDQ

1%

1%

1%

1%

GND

GND

R1

R2

OUT

C575

C575
.01UF

.01UF

25V

25V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

ASSEMBLY
PAGE DETAIL

CMD-Addr Map
BGA136 ADDR

FBVDDQ

R582

R582
0

0

5%

5%
0402

0402
COMMON

COMMON

FBA_CLK1_TERM

R593

R593

R594

R594

40.2

40.2

40.2

40.2

1%

1%

1%

1%

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

IN
IN

OUT

C71

C71
.1UF

.1UF

10V

10V

10%

10%

FBVDDQ

X5R

X5R

0402

0402

COMMON

COMMON

R89

R89

511

511

1%

1%

0402

0402

COMMON

COMMON

R92

R92

1.3K

1.3K

1%

1%

0402

0402

COMMON

COMMON

CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

R1006

R1006
0R

0R

5%

5%
0402

0402

FBVDDQ

COMMON

COMMON

GND

DDR3:

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

R1

OUT

C80

C80
.1UF

.1UF

R2

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

IN

GND

M6C

M6C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

FBA_D16

16

FBA_D17

17

FBA_D18

18

FBA_D19

19

FBA_D20

20

FBA_D21

21

FBA_D22

22

FBA_D23

23

FBA_DQM2
FBA_DQS_RN2
FBA_DQS_WP2

FBA_D48

48

FBA_D49

49

FBA_D50

50

FBA_D51

51

FBA_D52

52

FBA_D53

53

FBA_D54

54

FBA_D55

55

FBA_DQM6
FBA_DQS_RN6
FBA_DQS_WP6

COMMON

M2

DQ0

R3

DQ1

T2

DQ2

N2

DQ3

T3

DQ4

R2

DQ5

M3

DQ6

L3

DQ7

N3

DQM

P3

RDQS

P2

WDQS

M7B

M7B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

E11

DQ0

C10

DQ1

G10

DQ2

B10

DQ3

B11

DQ4

F10

DQ5

F11

DQ6

C11

DQ7

E10

DQM

D10

RDQS

D11

WDQS

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA Partition

FBA_D24

24

FBA_D25

25

FBA_D26

26

FBA_D27

27

FBA_D28

28

FBA_D29

29

FBA_D30

30

FBA_D31

31

FBA_DQM3FBA_DQM4
FBA_DQS_RN3
FBA_DQS_WP3

FBA_D56

56

FBA_D57

57

FBA_D58

58

FBA_D59

59

FBA_D60

60

FBA_D61

61

FBA_D62

62

FBA_D63

63

FBA_DQM7
FBA_DQS_RN7
FBA_DQS_WP7

1
10
11
8

19
25
4
6
5
13
21
16
23
20
17
9

12
3
27

18

14

15

FBVDDQ

GND

FBA_CMD4
FBA_CMD6
FBA_CMD5
FBA_CMD13

FBA_CLK1
FBA_CLK1*

C74

C74
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

M6D

M6D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

R11
N11
R10
M10
L10
M11
T10
T11

N10
P10
P11

M7C

M7C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

F2
F3
G3
C3
E2
B3
B2
C2

E3
D3
D2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M7D

M7D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

H10

RAS

F9

CAS

H4

WE

F4

CS0

K9

A0

H11

A1

K10

A2

M9

A3

K4

A4

H2

A5

K3

A6

L4

A7

K2

A8/AP

M4

A9

K11

A10

L9

A11

G9

BA0

G4

BA1

H3

BA2

H9

CKE

J11

CLK

J10

CLK

J2

NC/RFU

J3

A12 (32Mx32)

V4

SEN (GND)

V9

RESET

A9

MF (GND)

A4

ZQ

R85

R85
240

240

5%

5%

0603

0603

COMMON

COMMON

GND

K1

VDDA (VDD)

K12

VDDA (VDD)

C554

C554
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

J1

VSSA (GND)

J12

VSSA (GND)

MIRRORED

MIRRORED

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

FBVDDQ

F1
M1
A2
V2
A11
V11
F12
M12

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10
G12
L12

H1
H12

FBA_CMD43,33
FBA_CMD63,33
FBA_CMD53,33
FBA_CMD133,33
FBA_CMD223,33
FBA_CMD243,33
FBA_CMD03,33
FBA_CMD23,33

GND

GND

VREF = FBVDDQ * R2/(R1 + R2)

DDR3: VREF = 0.70 * FBVDDQ

FBVDDQ

R88

R88

511

511

1%

1%

0402

0402

COMMON

COMMON

R91

R91

1.3K

1.3K

R2

1%

1%

0402

0402

COMMON

COMMON

GND

FBA_CMD4
FBA_CMD6FBA_CMD8 FBA_CMD8
FBA_CMD5
FBA_CMD13
FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2

1.26V = 1.8V * 1.18K/(511 + 1.18K)

OUT OUT

C79

C79
.1UF

.1UF

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

FBVDDQ

R589

121R589

121

COMMON0402

COMMON0402

1%

1%

R590

121

R590

121

COMMON

COMMON

0402

0402

1%

1%

R580

121R580

121

COMMON0402

COMMON0402

1%

1%

R572

121R572

121

COMMON0402

COMMON0402

1%

1%

R591

121

R591

121

COMMON

0402

COMMON

0402

1%

1%

R586

121R586

121

COMMON0402

COMMON0402

1%

1%

R579

121

R579

121

COMMON

0402

COMMON

0402

1%

1%

R567

121R567

121

COMMON0402

COMMON0402

1%

1%

1

2

FBVDDQ

R81

R81
511

511

R1R1

1%

1%

0402

0402

COMMON

COMMON

C73

C73
.1UF

.1UF

R2

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

GND

3

COMMON

COMMON

R79

R79

1.3K

1.3K

1%

1%

0402

0402

4

5

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc>

Custom

<Doc>

Custom

<Doc>

Custom

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

<RevCode>

<RevCode>

<RevCode>

536

536

536

www.vinafix.vn

A B C D E F G H

Page6: FBA Partition Decoupling

1

2

1

2

Decoupling for FBA 31..0 Decoupling for FBA 63..32

FBVDDQ

C592

C592

C584

C584

C580

C580

C561

C561

C551

.1UF

.1UF

.1UF

.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C550

C550
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C591

C591
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C557

C557
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C581

C581
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C556

C556
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C570

C570
1UF

1UF

16V

3

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C582

C582
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C562

C562
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

C551
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C583

C583
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

GND

FBVDDQ

C553

C553
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C558

C558
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C578

C578
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

PLACE NEAR MEMORY FBVDDQ PINSPLACE NEAR MEMORY FBVDDQ PINS

C565

C565

C586

C586

C585

C585

C590

.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C559

C559
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C555

C555
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C560

C560
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C573

C573
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C587

C587
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C589

C589
1UF

1UF

16V

16V

10%

10%
X5R

X5R

0603

0603

COMMON

COMMON

C590
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

C568

C568
.1UF

.1UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

3

GND

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C GE

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA Partition Decoupling

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc>

Custom

<Doc>

Custom

<Doc>

Custom

Date:

Date:

Date:

Tuesday, February 12, 2008

Tuesday, February 12, 2008

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

636

636

636

4

5

<RevCode>

<RevCode>

<RevCode>

A B C D E F G H

Page7: FBB Partition

M5E

CMD-Addr Map

FBVDDQ

1

OUT

C601

C601
.01UF

.01UF

25V

25V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

GND

MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the

2

3

MEMORY pin!!

Minimize the stub length!!

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6

FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25

4

R608

R608
0

0

5%

5%
0402

0402
COMMON

COMMON

(OPT) (OPT)

FBB_CLK0_TERM

R604

R604

R606

R606

40.2

40.2

40.2

40.2

1%

1%

1%

1%

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

IN
IN

FBB_CMD_SENB034 FBB_CMD_SENB134

DDR3: ZQ = 6x desired output

impedence of DQ drivers

FBB_CMD[6..0]

FBB_CMD[25..8]

BI

BI

BI

BI

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

BGA136 ADDR

FBB_CMD[6..0] 3,34

FBB_CMD[25..8] 3,34

FBB_D[63..0]

FBB_DQM[7..0]

FBB_DQS_RN[7..0]

FBB_DQS_WP[7..0]

CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD22 A<2>
CMD24 A<3>
CMD0 A<4>
CMD2 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

R1007

R1007
0R

0R

5%

5%
0402

0402
COMMON

COMMON

GND

3

1

FBB_CMD1 FBB_CMD1

10

FBB_CMD10 FBB_CMD10

11

FBB_CMD11 FBB_CMD11

8

FBB_CMD8 FBB_CMD8

19

FBB_CMD19 FBB_CMD19

25

FBB_CMD25 FBB_CMD25

22

FBB_CMD22

24

FBB_CMD24

0

FBB_CMD0

2

FBB_CMD2

21

FBB_CMD21 FBB_CMD21

16

FBB_CMD16 FBB_CMD16

23

FBB_CMD23 FBB_CMD23

20

FBB_CMD20 FBB_CMD20

17

FBB_CMD17 FBB_CMD17

9

FBB_CMD9 FBB_CMD9

12

FBB_CMD12 FBB_CMD12

3

FBB_CMD3 FBB_CMD3

27

FBB_CMD273,34 FBB_CMD273,34

3

IN

FBB_CMD27 FBB_CMD27

18

FBB_CMD18 FBB_CMD18
FBB_CLK0
FBB_CLK0*

14

FBB_CMD14 FBB_CMD14
FBB_CMD_SENB0 FBB_CMD_SENB1

15

FBB_CMD15 FBB_CMD15 FBB_CMD15

FBB_ZQ0 FBB_ZQ1

R601

R601

R602

R602

10K

10K

10K

10K

5%

5%

5%

5%

0402

0402

0402

0402

COMMON

COMMON

COMMON

COMMON

GND

GND GND GND

FBVDDQ

3

C70

C70
.047UF

.047UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

GND

FBB_DQM0

0

FBB_DQM1

1

FBB_DQM2

2

FBB_DQM3

3
4

FBB_DQM5

5

FBB_DQM6

6

FBB_DQM7

7

FBB_DQS_RN0

0

FBB_DQS_RN1

1

FBB_DQS_RN2

2

FBB_DQS_RN3

3

FBB_DQS_RN4

4

FBB_DQS_RN5

5

FBB_DQS_RN6

6

FBB_DQS_RN7

7

FBB_DQS_WP0

0

FBB_DQS_WP1

1

FBB_DQS_WP2

2

FBB_DQS_WP3

3

FBB_DQS_WP4

4

FBB_DQS_WP5

5

FBB_DQS_WP6

6

FBB_DQS_WP7

7

M5E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

H3

RAS

F4

CAS

H9

WE

F9

CS0

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

H10

BA2

H4

CKE

J11

CLK

J10

CLK

J2

NC/RFU

J3

A12 (32Mx32)

V4

SEN (GND)

V9

RESET

A9

MF (GND)

A4

ZQ

R73

R73
240

240

5%

5%

0603

0603

COMMON

COMMON

K1

VDDA (VDD)

K12

VDDA (VDD)

C62

C62
.047UF

.047UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

J1

VSSA (GND)

J12

VSSA (GND)

FBB_D0

0

FBB_D1

1

FBB_D2

2

FBB_D3

3

FBB_D4

4

FBB_D5

5

FBB_D6

6

FBB_D7

7

FBB_DQM0
FBB_DQS_RN0
FBB_DQS_WP0

FBB_D32

32

FBB_D33

33

FBB_D34

34

FBB_D35

35

FBB_D36

36

FBB_D37

37

FBB_D38

38

FBB_D39

39

FBB_DQM4
FBB_DQS_RN4
FBB_DQS_WP4

B10
C10
B11
E11
C11
G10

F10
F11

E10
D10
D11

M2
N2
R2

T3

M3

L3
T2

R3
N3

P3
P2

NONMIRRORED

NONMIRRORED

M5A

M5A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M8E

M8E

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

FBVDDQ

F1
M1
A2
V2
A11
V11
F12
M12

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2

GND

B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10
G12
L12

H1
H12

FBB_D8

8

FBB_D9

9

FBB_D10

10

FBB_D11

11

FBB_D12

12

FBB_D13

13

FBB_D14

14

FBB_D15

15

FBB_DQM1
FBB_DQS_RN1
FBB_DQS_WP1

FBB_D40

40

FBB_D41

41

FBB_D42

42

FBB_D43

43

FBB_D44

44

FBB_D45

45

FBB_D46

46

FBB_D47

47

FBB_DQM5
FBB_DQS_RN5
FBB_DQS_WP5

COMMON

COMMON

COMMON

COMMON

GND

FBB_VREF0 FBB_VREF1
FBB_VREF2 FBB_VREF3

VREF = FBVDDQ * R2/(R1 + R2)

DDR3: VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

M5B

M5B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

C3
B3
F3
B2
C2
F2
E2

G3

E3
D3
D2

M8A

M8A

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

T11
T10
R11
R10
N11
M11
M10
L10

N10
P10
P11

C GE

OUT

C569

C569
.01UF

.01UF

25V

25V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

GND

IN
IN

MUST BE PLACED as close as possible to
the BGA memory on the line AFTER the
MEMORY pin!!

Minimize the stub length!!

FBVDDQ

R74

R74
511

511

R1

1%

1%

0402

0402

R75

R75

1.3K

1.3K

R2

1%

1%

0402

0402

GND

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

ASSEMBLY
PAGE DETAIL

CMD-Addr Map

R588

R588

40.2

40.2

1%

1%
0402

0402
COMMON

COMMON

R1

R2

DDR3: ZQ = 6x desired outputImpedence = 240 / 6 = 40 ohm

BGA136 ADDR

CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD19 A<0>
CMD25 A<1>
CMD4 A<2>
CMD6 A<3>
CMD5 A<4>
CMD13 A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD27 BA2
CMD18 CKE
CMD15 RST

R1008

R1008
0R

0R

5%

5%
0402

0402
COMMON

COMMON

GND

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

OUT

C69

C69
.1UF

.1UF

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

FBVDDQ

1
10
11
8

19
25
4

FBB_CMD4

6

FBB_CMD6

5

FBB_CMD5

13

FBB_CMD13

21
16
23
20
17
9

12
3
27

18

14

15

IN

FBVDDQ

GND

FBB_CLK1_TERM

OUT

C61

C61
.1UF

.1UF

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

R592

R592

40.2

40.2

1%

1%
0402

0402
COMMON

COMMON

FBVDDQ

COMMON

COMMON

COMMON

COMMON

R576

R576
0

0

5%

5%
0402

0402
COMMON

COMMON

FBVDDQ

R76

R76

511

511

1%

1%

0402

0402

R77

R77

1.3K

1.3K

1%

1%

0402

0402

GND

M5C

M5C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

FBB_D16

16

FBB_D17

17

FBB_D18

18

FBB_D19

19

FBB_D20

20

FBB_D21

21

FBB_D22

22

FBB_D23

23

FBB_DQM2
FBB_DQS_RN2
FBB_DQS_WP2

FBB_D48

48

FBB_D49

49

FBB_D50

50

FBB_D51

51

FBB_D52

52

FBB_D53

53

FBB_D54

54

FBB_D55

55

FBB_DQM6
FBB_DQS_RN6
FBB_DQS_WP6

P545 BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBB Partition

M10
R10
M11

L10

R11

T11

N11

T10

N10
P10
P11

G3

F3

C3

B3
B2

C2

E2
F2

E3
D3
D2

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M8B

M8B

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

FBB_D24

24

FBB_D25

25

FBB_D26

26

FBB_D27

27

FBB_D28

28

FBB_D29

29

FBB_D30

30

FBB_D31

31

FBB_DQM3FBB_DQM4
FBB_DQS_RN3
FBB_DQS_WP3

FBB_D56

56

FBB_D57

57

FBB_D58

58

FBB_D59

59

FBB_D60

60

FBB_D61

61

FBB_D62

62

FBB_D63

63

FBB_DQM7
FBB_DQS_RN7
FBB_DQS_WP7

C75

C75
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

FBB_CLK1
FBB_CLK1*

R3
L3
M3
N2
M2
R2
T3
T2

N3

P3
P2

G10
F10
F11
E11
B11
B10
C10
C11

E10
D10
D11

R90

R90
240

240

5%

5%

0603

0603

COMMON

COMMON

GND

C77

C77
.047UF

.047UF

16V

16V

10%

10%
X7R

X7R

0402

0402

COMMON

COMMON

M5D

M5D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M8C

M8C

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

H10

F9
H4
F4

K9
H11
K10

M9

K4

H2

K3

L4

K2

M4
K11

L9

G9

G4

H3

H9
J11
J10

J2
J3

V4

V9

A9

A4

K1
K12

J1

J12

M8D

M8D

BGA_0136_P080_140X120

BGA_0136_P080_140X120
BGA136

BGA136
COMMON

COMMON

RAS
CAS
WE
CS0

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11

BA0
BA1
BA2

CKE
CLK
CLK

NC/RFU
A12 (32Mx32)
SEN (GND)

RESET

MF (GND)

ZQ

VDDA (VDD)
VDDA (VDD)

VSSA (GND)
VSSA (GND)

MIRRORED

MIRRORED

FBVDDQ

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

G12

VSS

L12

VSS

H1

VREF

H12

VREF

FBB_CMD43,34
FBB_CMD63,34
FBB_CMD53,34
FBB_CMD133,34
FBB_CMD223,34
FBB_CMD243,34
FBB_CMD03,34
FBB_CMD23,34

VREF = FBVDDQ * R2/(R1 + R2)

GND

FBVDDQ

R87

R87
511

511

1%

1%

0402

0402

COMMON

COMMON

R86

R86

1.3K

1.3K

1%

1%

0402

0402

COMMON

COMMON

GND

GND

FBB_CMD4
FBB_CMD6
FBB_CMD5
FBB_CMD13
FBB_CMD22
FBB_CMD24
FBB_CMD0
FBB_CMD2

VREF = 0.70 * FBVDDQDDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

R1

OUT OUT

C78

C78
.1UF

.1UF

R2

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

R599

R599

R597

R597

R583

R583

R575

R609

R605

R607

R607

R603

R603

COMMON

COMMON

COMMON

COMMON

FBVDDQ

121

121

COMMON

COMMON

0402

0402

1%

1%

121

121

COMMON

0402

COMMON

0402

1%

1%

121

121

COMMON

COMMON

0402

0402

1%

1%

121R575

121

COMMON0402

COMMON0402

1%

1%

121R609

121

COMMON0402

COMMON0402

1%

1%

121R605

121

COMMON0402

COMMON0402

1%

1%

121

121

COMMON

0402

COMMON

0402

1%

1%

121

121

COMMON

0402

COMMON

0402

1%

1%

FBVDDQ

R83

R83
511

511

R1

1%

1%

0402

0402

R82

R82

1.3K

1.3K

1%

1%

0402

0402

C76

C76
.1UF

.1UF

R2

10V

10V

10%

10%
X5R

X5R

0402

0402

COMMON

COMMON

GND

1

2

3

4

5

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

Micro-Star International Co., LTD.

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc>

Custom

<Doc>

Custom

<Doc>

Custom

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Date:

Tuesday, February 12, 2008

Sheet of

Sheet of

Sheet of

HFDBA

<RevCode>

<RevCode>

<RevCode>

736

736

736

www.vinafix.vn