MSI MS-V129 Schematic V129_21
A B C D E F G H
P727-A01: G96, GB1-128, GDDR3, DL-DVI, DL-DVI/VGA, SD/HDTV
REV HISTORY
1
2
3
PAGE SUMMARY:
Page 1: TABLE OF CONTENTS
Page 2: PCI EXPRESS INTERFACE, PEX_VDD DECOUPLING CAPS
Page 3: FBA MEMORY INTERFACE, GPU NVVDD & FBVDDQ DECOUPLING CAPS
Page 4: FBA 16/32Mx32 GDDR3 MEMORIES, FBA COMMAND BUS PU'S, FBA CLK TERMS
Page 5: FBA MEMORY FBVDDQ DECOUPLING CAPS
Page 6: FBC MEMORY INTERFACE
Page 7: FBC 16/32MX32 GDDR3 MEMORIES, FBC CMD BUS PU'S, FBC CLK TERMS
Page 8: FBC MEMORY FBVDDQ DECOUPLING CAPS, GPU GND CONNECTIONS
Page 9: DACA FILTERS, DACA SYNC BUFFERS & DB15 SOUTH
Page 10: DACC FILTERS, DACC SYNC BUFFERS & DB15 MID
Page 11: TMDS LINK A/B, DVI CONNECTOR SOUTH
Page 12: TMDS LINK C/D, AC COUPLING, PD's, DVI CONNECTOR MID
Page 13: MIOA & MIOB, SLI CONNECTOR
Page 14: DACB FILTERS, MINIDIN CONNECTOR NORTH, SD/HD VIDEO OUTPUT CONNECTOR
Page 15: SPDIF-IN, XTAL, MECHANICALS, THERMALS
Page 16: EXTERNAL THERMAL SENSOR, 4PIN FAN CONTROL, GPIO
Page 17: BIOS ROM, HDCP ROM, STRAPPING OPTIONS
Page 18: HYBRID POWER CIRCUIT
Page 19: POWER SUPPLY LINEARS: 5V, DDC5V, IFP PLLVDD, IFP IOVDD, MIO VDD, 3V3 FILTER, 12V FILTER
Page 20: POWER SUPPLY: FBVDDQ SINGLE PHASE SWITCHER
Page 21: POWER SUPPLY: PEX_VDD SINGLE PHASE SWITCHER
Page 22: POWER SUPPLY: NVVDD DUAL PHASE SWITCHER
Page 23: POWER SUPPLY: NVVDD VOLTAGE SELECTION
2/18 PAGE 2 add SPDIF_IN_M from PCIE's connector PIN_BA2
PAGE 15 remove DP function
PAGE 16 remove SLI function
PAGE 17 add SCART (the same as V096-3.0)
PAGE 18 add SPDIF_IN_M
PAGE 19 remove GPIO_11_SLI_SYNC0 / GPIO12_SWAPRDY / GPIO15_DP_HPD / GPIO18_DP_MODE
/ GPIO19_DP_CEC / GPIO22_SWAPRDY_A
add GPIO2_TV_SCART / GPIO13_TV_SCART_SEL / GPIO14_TV_SCART_SEL / GPIO20_TV_LOAD_TEST
/ GPIO16_SEL_HDTV_SDTV
2/20 PAGE 16 MIOB VDD from 2V5 change to 3V3_F
2/21 PAGE 20 remove J5 (HDA function), remove 2V5
PAGE 19 remove I2CD_SDA and I2CD_SCL (for DP)
remove GPIO2/GPIO13/GPIO14
PAGE 17 3V3 chnage to 3V3_F
remove SCART_TV__SEL function
remove TV_CVBS_SCART_F
PAGE 21 remove Q15, C870, R737 (for DP_ hotplug_detect_E)
PAGE 22 remove 2V5 function
2/22 PAGE 22 IFPEF_RSET PULL LOW
PAGE 18 ADD U601,U602,U603,U604 for EMI
ADD MEC10, MEC11 for external FAN holder
ADD FM7, FM8
2/22 PAGE 14 add bridge R1103,R1104,R1105,R1106 for EMI
PAGE 18 rename U514~U515,and U601~U604 to EM1 ~EM8
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
VARIANT ASSEMBLY
SKU
B
BASE
1
SKU0000
2
SKU0001
3
SKU0002
4
<UNDEFINED>
5
<UNDEFINED>
6
<UNDEFINED>
7
<UNDEFINED>
8
<UNDEFINED>
9
<UNDEFINED>
10
<UNDEFINED>
11
<UNDEFINED>
<UNDEFINED>
12
13
<UNDEFINED>
14
<UNDEFINED>
15
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
TABLE OF CONTENTS
NVPN
600-10727-base-sch
600-10727-0000-100
600-10727-0001-100
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
G96-400, 625/800MHz 256MB 16Mx32 GDDR3, DVI DVI HDTV-Out
G96-300, 550/800Mhz 256MB 16Mx32 GDDR3, DVI DVI HDTV-Out
G96-300, 550/800Mhz 256MB 16Mx32 GDDR3, DVI DVI600-10727-0002-100
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED><UNDEFINED>
<UNDEFINED>
<UNDEFINED>
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10727-base-sch A
NAME
4
5
PAGEID
DATE
31-OCT-2007
HFDBA
A B C D E F G H
16X PEX INTERFACE
CN2
CN2
CON_FINGER_PEX_164_B
CON_FINGER_PEX_164_B
CON_X16
CON_X16
COMMON
1
18
12V
3V3
3V3_AUX
PEX_PRSNT1*
IN
SNN_PE_PRSNT2_A
2
SNN_PE_PRSNT2_B
SNN_PE_RSVD3
SNN_PE_RSVD4
SNN_PE_RSVD5
SNN_PE_PRSNT2_C
SNN_PE_RSVD6
3
PEX_PRSNT2*
18
IN
SNN_PE_RSVD7
SNN_PE_RSVD8
4
5
SPDIF_IN_M
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
COMMON
B1
+12V
B2
+12V
A2
+12V
A3
+12V
B3
+12V/RSVD
B8
+3V3
A9
+3V3
A10
+3V3
B10
+3V3AUX
A1
PRSNT1
B17
PRSNT2
B12
RSVD
B4
GND
A4
GND
B7
GND
A12
GND
B13
GND
A15
GND
B16
GND
B18
GND
A18
GND
B31
PRSNT2
A19
RSVD
B30
RSVD
A32
RSVD
A20
GND
B21
GND
B22
GND
A23
GND
A24
GND
B25
GND
B26
GND
A27
GND
A28
GND
B29
GND
A31
GND
B32
GND
B48
PRSNT2
A33
RSVD
A34
GND
B35
GND
B36
GND
A37
GND
A38
GND
B39
GND
B40
GND
A41
GND
A42
GND
B43
GND
B44
GND
A45
GND
A46
GND
B47
GND
B49
GND
A49
GND
B81
PRSNT2
A50
RSVD
B82
RSVD
A51
GND
B52
GND
B53
GND
A54
GND
A55
GND
B56
GND
B57
GND
A58
GND
A59
GND
B60
GND
B61
GND
A62
GND
A63
GND
B64
GND
B65
GND
A66
GND
A67
GND
B68
GND
B69
GND
A70
GND
A71
GND
B72
GND
B73
GND
A74
GND
A75
GND
B76
GND
B77
GND
A78
GND
A79
GND
B80
GND
A82
GND
18
OUT
END OF X1
END OF X1
END OF X4
END OF X4
END OF X8
END OF X8
END OF X16
END OF X16
TRST* JTAG1
TCLK JTAG2
TDI JTAG3
TDO JTAG4
TMS JTAG5
SMCLK
SMDAT
PERST
REFCLK
REFCLK
PERP0
PERN0
PETP0
PETN0
PERP1
PERN1
PETP1
PETN1
PERP2
PERN2
PETP2
PETN2
PERP3
PERN3
PETP3
PETN3
PERP4
PERN4
PETP4
PETN4
PERP5
PERN5
PETP5
PETN5
PERP6
PERN6
PETP6
PETN6
PERP7
PERN7
PETP7
PETN7
PERP8
PERN8
PETP8
PETN8
PERP9
PERN9
PETP9
PETN9
PERP10
PERN10
PETP10
PETN10
PERP11
PERN11
PETP11
PETN11
PERP12
PERN12
PETP12
PETN12
PERP13
PERN13
PETP13
PETN13
PERP14
PERN14
PETP14
PETN14
PERP15
PERN15
PETP15
PETN15
PEX_TRST*
B9
PEX_TCLK
A5
PEX_TDI
A6
PEX_TDO
A7
PEX_TMS
A8
PEX_SMCLK
B5
PEX_SMDAT
B6
B11
WAKE
A11
A13
A14
A16
A17
B14
B15
A21
A22
B19
B20
A25
A26
B23
B24
A29
A30
B27
B28
A35
A36
B33
B34
A39
A40
B37
B38
A43
A44
B41
B42
A47
A48
B45
B46
A52
A53
B50
B51
A56
A57
B54
B55
A60
A61
B58
B59
A64
A65
B62
B63
A68
A69
B66
B67
A72
A73
B70
B71
A76
A77
B74
B75
A80
A81
B78
B79
R660
R660
0
0
5%
5%
0402
0402
COMMON
COMMON
18
IN
18
BI
SNN_PEX_WAKE*
PEX_RST*
PEX_REFCLK
PEX_REFCLK*
PEX_TXX0
PEX_TXX0*
PEX_RX0
PEX_RX0*
PEX_TXX1
PEX_TXX1*
PEX_RX1
PEX_RX1*
PEX_TXX2
PEX_TXX2*
PEX_RX2
PEX_RX2*
PEX_TXX3
PEX_TXX3*
PEX_RX3
PEX_RX3*
PEX_TXX4 PEX_TXX4
PEX_TXX4* PEX_TXX4*
PEX_RX4
PEX_RX4*
PEX_TXX5
PEX_TXX5*
PEX_RX5
PEX_RX5*
PEX_TXX6
PEX_TXX6*
PEX_RX6
PEX_RX6*
PEX_TXX7
PEX_TXX7*
PEX_RX7
PEX_RX7*
PEX_TXX8
PEX_TXX8*
PEX_RX8
PEX_RX8*
PEX_TXX9
PEX_TXX9*
PEX_RX9
PEX_RX9*
PEX_TXX10
PEX_TXX10*
PEX_RX10
PEX_RX10*
PEX_TXX11
PEX_TXX11*
PEX_RX11
PEX_RX11*
PEX_TXX12
PEX_TXX12*
PEX_RX12 PEX_RX12
PEX_RX12* PEX_RX12*
PEX_TXX13
PEX_TXX13*
PEX_RX13
PEX_RX13*
PEX_TXX14
PEX_TXX14*
PEX_RX14
PEX_RX14*
PEX_TXX15
PEX_TXX15*
PEX_RX15
PEX_RX15*
18
OUT
COMMON 040210% 16VX7R
COMMON 040210% 16VX7R
COMMON X7R 10%
COMMON X7R 10%
COMMON X7R 10%
COMMON X7R 10%
COMMON X7R 10%
COMMON X7R 10%
COMMON 16V040210%X7R
COMMON 16V040210%X7R
COMMON 16V
COMMON 16V
COMMON 16V040210%X7R
COMMON 16V040210%X7R
RP501B 0
RP501B 0
2 7
RP501A
RP501A
1 8
RPAK_PAR_4_2010
RPAK_PAR_4_2010
RP501D
RP501D
4 5
RPAK_PAR_4_2010
RPAK_PAR_4_2010
RP501C
RP501C
3 6
RPAK_PAR_4_2010
RPAK_PAR_4_2010
R655
R655
0402
0402
5%
5%
C718 .1UF
C718 .1UF
C714
C703
C703
040210%X7RCOMMON
040210%X7RCOMMON
C689
C689
0402 16V
0402 16V
C676
C676
10%
X7RCOMMON 0402 16V
10%
X7RCOMMON 0402 16V
C663
C663
C653
C646
C646
0402 16V
0402 16V
C637
C637
10%COMMON
10%COMMON
C629
C629
X7R 16V
040210%COMMON
X7R 16V
040210%COMMON
C622
C622
0402COMMON X7R 10%
0402COMMON X7R 10%
C608
C601
C601
040210%X7RCOMMON
040210%X7RCOMMON
C597
C597
040210%X7R
040210%X7R
C591
C591
040210%X7RCOMMON
040210%X7RCOMMON
C583 .1UF
C583 .1UF
0
0
COMMON
COMMON
.1UFC714
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UFC653
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UFC608
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
COMMONRPAK_PAR_4_2010
COMMONRPAK_PAR_4_2010
0
0
COMMON
COMMON
0
0
COMMON
COMMON
0
0
COMMON
COMMON
16VCOMMON X7R 10% 0402
16VCOMMON X7R 10% 0402
16V
16V
16V0402
16V0402
16V040210%X7RCOMMON
16V040210%X7RCOMMON
16V0402X7R
16V0402X7R
16V
16V
16V
16V
16V
16V
JTAG_TRST*
JTAG_TCLK
JTAG_TDI
JTAG_TDO
JTAG_TMS
IN
IN
IN
OUT
IN
18,19
R598
200R598
200
COMMON0402
COMMON0402
5%
5%
C715
.1UF
C715
.1UF
0402 10% X7R
16V COMMON
0402 10% X7R
16V COMMON
C706
.1UF
C706
.1UF
16V0402 COMMONX7R
16V0402 COMMONX7R
C699
.1UF
C699
.1UF
16V COMMON
16V COMMON
C683
.1UF
C683
.1UF
0402 16V COMMON10%
0402 16V COMMON10%
C669
.1UFC669
.1UF
C660
.1UF
C660
.1UF
0402 16V 10%
0402 16V 10%
C651
.1UFC651
.1UF
0402 16V 10% COMMONX7R
0402 16V 10% COMMONX7R
C642
.1UF
C642
.1UF
C633
.1UF
C633
.1UF
C623
.1UF
C623
.1UF
16V
16V
C611
.1UF
C611
.1UF
0402 16V
0402 16V
C604
.1UFC604
.1UF
C599
.1UF
C599
.1UF
16V 10% X7R
16V 10% X7R
C594
.1UF
C594
.1UF
0402 16V
0402 16V
C589
.1UF
C589
.1UF
C581
.1UF
C581
.1UF
0402 16V
0402 16V
16
16
16
16
16
IN
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*
10%
10%
10%0402 X7R
10%0402 X7R
X7R
X7R
10%16V0402 X7R COMMON
10%16V0402 X7R COMMON
X7R COMMON
X7R COMMON
10%
COMMON16V X7R0402
10%
COMMON16V X7R0402
10% COMMON0402 16V
X7R
10% COMMON0402 16V
X7R
COMMON10% X7R0402
COMMON10% X7R0402
10% COMMONX7R
10% COMMONX7R
10%0402 16V COMMONX7R
10%0402 16V COMMONX7R
COMMON0402
COMMON0402
10% COMMONX7R
10% COMMONX7R
10%0402 16V
COMMONX7R
10%0402 16V
COMMONX7R
10% COMMONX7R
10% COMMONX7R
GPU_RST*
SNN_PEX_CLKREQ*
PEX_TX0*
PEX_TX1*
PEX_TX2*
PEX_TX3*
PEX_TX4*
PEX_TX5*
PEX_TX6*
PEX_TX7*
PEX_TX8*
PEX_TX9*
PEX_TX10*
PEX_TX11*
PEX_TX12*
PEX_TX13*
PEX_TX14*
PEX_TX15*
PEX_TX0
PEX_TX1
PEX_TX2
PEX_TX3
PEX_TX4
PEX_TX5
PEX_TX6
PEX_TX7
PEX_TX8
PEX_TX9
PEX_TX10
PEX_TX11
PEX_TX12
PEX_TX13
PEX_TX14
PEX_TX15
AM16
AR13
AJ17
AJ18
AR16
AR17
AL17
AM17
AP17
AN17
AM18
AM19
AN19
AP19
AL19
AK19
AR19
AR20
AL20
AM20
AP20
AN20
AM21
AM22
AN22
AP22
AL22
AK22
AR22
AR23
AL23
AM23
AP23
AN23
AM24
AM25
AN25
AP25
AL25
AK25
AR25
AR26
AL26
AM26
AP26
AN26
AM27
AM28
AN28
AP28
AL28
AK28
AR28
AR29
AK29
AL29
AP29
AN29
AM29
AM30
AN31
AP31
AM31
AM32
AR31
AR32
AN32
AP32
AR34
AP34
C GE
G1A
G1A
BGA_0969_P080_290X290
BGA_0969_P080_290X290
COMMON
COMMON
1/16 PCI_EXPRESS
1/16 PCI_EXPRESS
PEX_RST
PEX_CLKREQ
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
PEX_REFCLK
PEX_REFCLK
PEX_TX0
PEX_TX0
PEX_RX0
PEX_RX0
PEX_TX1
PEX_TX1
PEX_RX1
PEX_RX1
PEX_TX2
PEX_TX2
PEX_RX2
PEX_RX2
PEX_TX3
PEX_TX3
PEX_RX3
PEX_RX3
PEX_TX4
PEX_TX4
PEX_RX4
PEX_RX4
PEX_TX5
PEX_TX5
PEX_RX5
PEX_RX5
PEX_TX6
PEX_TX6
PEX_RX6
PEX_RX6
PEX_TX7
PEX_TX7
PEX_RX7
PEX_RX7
PEX_TX8
PEX_TX8
PEX_RX8
PEX_RX8
PEX_TX9
PEX_TX9
PEX_RX9
PEX_RX9
PEX_TX10
PEX_TX10
PEX_RX10
PEX_RX10
PEX_TX11
PEX_TX11
PEX_RX11
PEX_RX11
PEX_TX12
PEX_TX12
PEX_RX12
PEX_RX12
PEX_TX13
PEX_TX13
PEX_RX13
PEX_RX13
PEX_TX14
PEX_TX14
PEX_RX14
PEX_RX14
PEX_TX15
PEX_TX15
PEX_RX15
PEX_RX15
ASSEMBLY
PAGE DETAIL
Place near balls
600mA
C628
C628
C659
C659
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
AK16
PEX_IOVDD
AK17
PEX_IOVDD
AK21
PEX_IOVDD
AK24
PEX_IOVDD
AK27
PEX_IOVDD
AG11
PEX_IOVDDQ
AG12
PEX_IOVDDQ
AG13
PEX_IOVDDQ
AG15
PEX_IOVDDQ
AG16
PEX_IOVDDQ
AG17
PEX_IOVDDQ
AG18
PEX_IOVDDQ
AG22
PEX_IOVDDQ
AG23
PEX_IOVDDQ
AG24
PEX_IOVDDQ
AG25
PEX_IOVDDQ
AG26
PEX_IOVDDQ
AJ14
PEX_IOVDDQ
AJ15
PEX_IOVDDQ
AJ19
PEX_IOVDDQ
AJ21
PEX_IOVDDQ
AJ22
PEX_IOVDDQ
AJ24
PEX_IOVDDQ
AJ25
PEX_IOVDDQ
AJ27
PEX_IOVDDQ
AK18
PEX_IOVDDQ
AK20
PEX_IOVDDQ
AK23
PEX_IOVDDQ
AK26
PEX_IOVDDQ
AL16
PEX_IOVDDQ
A2
NC_1
AB7
NC_2
AD6
NC_3
AF6
NC_4
AG6
NC_5
AJ5
NC_6
AK15
NC_7
AL7
NC_8
D35
NC_9
E35
NC_10
E7
NC_11
F7
NC_12
H32
NC_13
M7
NC_14
P6
NC_15
P7
NC_16
R7
NC_17
U7
NC_18
V6
NC_19
J10
VDD33_1
J11
VDD33_2
J12
VDD33_3
J13
VDD33_4
J9
VDD33_5
AD20
VDD_SENSE
AD19
GND_SENSE
AG14
PEX_PLLVDD
AG19
PEX_RFU1
AG20
PEX_RFU2
AG21
PEX_TERMP
AP35
TESTMODE
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PCI EXPRESS INTERFACE, PEX_VDD DECOUPLING CAPS
SNN_NC<1>
SNN_NC<2>
SNN_NC<3>
SNN_NC<4>
SNN_NC<5>
SNN_NC<6>
SNN_NC<7>
SNN_NC<8>
SNN_NC<9>
SNN_NC<10>
SNN_NC<11>
SNN_NC<12>
SNN_NC<13>
SNN_NC<14>
SNN_NC<15>
SNN_NC<16>
SNN_NC<17>
SNN_NC<18>
SNN_NC<19>
NVVDD_SENSE
SNN_NVVDD_GND_SENSE
PEX_PLLVDD
SNN_PEX_RFU1
SNN_PEX_RFU2
PEX_TERMP
GPU_TESTMODE
2A
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C648
C648
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
6MIL
6MIL
R596 2.49K
R596 2.49K
0402 COMMON
0402 COMMON
1%
1%
R583
0402 COMMON
0402 COMMON
5%
Place near balls
OUT
120mA
C666
C666
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
10K5%R583
10K
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C665
C665
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
Place Close to PEX fingers
3V3
12V
3V3_AUX
Place near balls
2,22
C762
C762
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C766
C766
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C28
C28
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C668
C668
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C621
C621
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C635
C635
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C654
C654
4.7UF
4.7UF
6.3V
6.3V
X5R
X5R
0603
0603
COMMON
COMMON
C675
C675
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
Place Close to GPU
C580
C658
C658
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C580
4.7UF
4.7UF
6.3V 10%
6.3V 10%
X5R
X5R
0603
0603
COMMON
COMMON
Place Close to GPU
C586
C760
C760
10UF
10UF
16V
16V
20%
20%
X5R
X5R
C1206_113
C1206_113
COMMON
COMMON
C29
C29
10UF
10UF
16V
16V
20%
20%
X5R
X5R
C1206_113
C1206_113
COMMON
COMMON
C586
4.7UF
4.7UF
6.3V
6.3V
X5R
X5R
0603
0603
COMMON
COMMON
10%
10%
C761
C761
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C765
C765
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0603
0603
COMMON
COMMON
C643
C643
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
Place Near BGAPlace near balls
LB502
10nHLB502
10nH
IND_SMD_0402COMMON
20%
20%
IND_SMD_0402COMMON
PEX_VDD
C574
C574
10UF
10UF
10V 10%
10V 10%
X5R
X5R
C0805_67
C0805_67
COMMON
COMMON
1
90DIFFPEX_TX0 1
90DIFF 1PEX_TX0
90DIFFPEX_TX3 1
90DIFF 1PEX_TX11
90DIFFPEX_TXX11 1
90DIFF 1PEX_TXX12
90DIFF 1PEX_TXX13
90DIFF 1PEX_TXX13
90DIFF 1PEX_TXX14
90DIFF 1PEX_RX11
90DIFF 1PEX_RX11
PAGEID
DATE
HFDBA
NV_CRITICALNV_IMPEDANCEDIFFPAIRNET
1100DIFFPEX_REFCLK
1100DIFFPEX_REFCLK
190DIFFPEX_TX1
190DIFFPEX_TX1
190DIFFPEX_TX2
190DIFFPEX_TX2
190DIFFPEX_TX3
1PEX_TX4 90DIFF
1PEX_TX4 90DIFF
190DIFFPEX_TX5
190DIFFPEX_TX5
190DIFFPEX_TX6
190DIFFPEX_TX6
190DIFFPEX_TX7
190DIFFPEX_TX7
190DIFFPEX_TX8
190DIFFPEX_TX8
190DIFFPEX_TX9
190DIFFPEX_TX9
190DIFFPEX_TX10
190DIFFPEX_TX10
190DIFFPEX_TX11
190DIFFPEX_TX12
190DIFFPEX_TX12
190DIFFPEX_TX13
190DIFFPEX_TX13
190DIFFPEX_TX14
190DIFFPEX_TX14
190DIFFPEX_TX15
190DIFFPEX_TX15
190DIFFPEX_TXX0
190DIFFPEX_TXX0
190DIFFPEX_TXX1
190DIFFPEX_TXX1
190DIFFPEX_TXX2
190DIFFPEX_TXX2
190DIFFPEX_TXX3
190DIFFPEX_TXX3
190DIFFPEX_TXX4
190DIFFPEX_TXX4
190DIFFPEX_TXX5
190DIFFPEX_TXX5
190DIFFPEX_TXX6
190DIFFPEX_TXX6
190DIFFPEX_TXX7
190DIFFPEX_TXX7
190DIFFPEX_TXX8
190DIFFPEX_TXX9
190DIFFPEX_TXX10
190DIFFPEX_TXX14
190DIFFPEX_TXX15
190DIFFPEX_TXX15
1PEX_RX0 90DIFF
190DIFFPEX_RX0
190DIFFPEX_RX1
190DIFFPEX_RX1
190DIFFPEX_RX2
190DIFFPEX_RX2
190DIFFPEX_RX3
190DIFFPEX_RX3
190DIFFPEX_RX4
190DIFFPEX_RX4
190DIFFPEX_RX5
190DIFFPEX_RX5
190DIFFPEX_RX6
190DIFFPEX_RX6
190DIFFPEX_RX7
190DIFFPEX_RX7
190DIFFPEX_RX8
190DIFFPEX_RX8
190DIFFPEX_RX9
190DIFFPEX_RX9
190DIFFPEX_RX10
190DIFFPEX_RX10
190DIFFPEX_RX12
190DIFFPEX_RX14
1PEX_RX14 90DIFF
190DIFFPEX_RX15
1.2V
0V
1.2V10MIL
12MIL 12V 5.5A
31-OCT-2007
2
3
4
5
3A3.3V12MIL
PEX_REFCLK
BI
PEX_REFCLK*
PEX_VDD
C577
C577
10UF
10UF
10V 10%
10V 10%
X5R
X5R
C0805_67
C0805_67
COMMON
COMMON
3V3_F
C690
C690
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
PEX_VDD
BI
PEX_TX0
BI
PEX_TX0*
BI
PEX_TX1
BI
PEX_TX1*
BI
PEX_TX2
BI
PEX_TX2*
BI
PEX_TX3
BI
PEX_TX3*
BI
PEX_TX4
BI
PEX_TX4*
BI
PEX_TX5
BI
PEX_TX5*
BI
PEX_TX6
BI
PEX_TX6*
BI
PEX_TX7
BI
PEX_TX7*
BI
PEX_TX8
BI
PEX_TX8*
BI
PEX_TX9
BI
PEX_TX9*
BI
PEX_TX10
BI
PEX_TX10*
BI
PEX_TX11
BI
PEX_TX11*
BI
PEX_TX12
BI
PEX_TX12*
BI
PEX_TX13
BI
PEX_TX13*
BI
PEX_TX14
BI
PEX_TX14*
BI
PEX_TX15
BI
PEX_TX15*
BI
PEX_TXX0
BI
PEX_TXX0*
BI
PEX_TXX1
BI
PEX_TXX1*
BI
PEX_TXX2
BI
PEX_TXX2*
BI
PEX_TXX3
BI
PEX_TXX3*
BI
BI
BI
PEX_TXX5
BI
PEX_TXX5*
BI
PEX_TXX6
BI
PEX_TXX6*
BI
PEX_TXX7
BI
PEX_TXX7*
BI
PEX_TXX8
BI
PEX_TXX8*
BI
PEX_TXX9
BI
PEX_TXX9*
BI
PEX_TXX10
BI
PEX_TXX10*
BI
PEX_TXX11
BI
PEX_TXX11*
BI
PEX_TXX12
BI
PEX_TXX12*
BI
PEX_TXX13
BI
PEX_TXX13*
BI
PEX_TXX14
BI
PEX_TXX14*
BI
PEX_TXX15
BI
PEX_TXX15*
BI
PEX_RX0
BI
PEX_RX0*
BI
PEX_RX1
BI
PEX_RX1*
BI
PEX_RX2
BI
PEX_RX2*
BI
PEX_RX3
BI
PEX_RX3*
BI
PEX_RX4
BI
PEX_RX4*
BI
PEX_RX5
BI
PEX_RX5*
BI
PEX_RX6
BI
PEX_RX6*
BI
PEX_RX7
BI
PEX_RX7*
BI
PEX_RX8
BI
PEX_RX8*
BI
PEX_RX9
BI
PEX_RX9*
BI
PEX_RX10
BI
PEX_RX10*
BI
PEX_RX11
BI
PEX_RX11*
BI
BI
BI
PEX_RX13
BI
PEX_RX13*
BI
PEX_RX14
BI
PEX_RX14*
BI
PEX_RX15
BI
PEX_RX15*
BI
NVVDD_SENSE
2,22
BI
NVVDD_GND_SENSE
2,22
BI
PEX_PLLVDD
BI
3V3
12V
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10727-base-sch A
PEX_TXX8 190DIFF
PEX_TXX9 190DIFF
PEX_TXX10 190DIFF
PEX_TXX11 190DIFF
PEX_TXX12 90DIFF 1
PEX_RX12 190DIFF
PEX_RX13 190DIFF
PEX_RX13 190DIFF
PEX_RX15 190DIFF
MIN_LINE_WIDTH VOLTAGE
NAME
www.vinafix.vn
A B C D E F G H
G1B
G1B
BGA_0969_P080_290X290
BGA_0969_P080_290X290
COMMON
COMMON
2/16 FBA
2/16 FBA
SNN_FBA_WDS0
SNN_FBA_WDS0*
SNN_FBA_WDS1
SNN_FBA_WDS1*
SNN_FBA_WDS2
SNN_FBA_WDS2*
SNN_FBA_WDS3
SNN_FBA_WDS3*
FBA_VREF
FBA_D0
R30
FBA_D0
FBA_D1
0
R32
FBA_D1
FBA_D2
1
P31
FBA_D2
FBA_D3
2
N30
FBA_D3
FBA_D4
3
L31
FBA_D4
FBA_D5
4
M32
FBA_D5
FBA_D6
5
M30
FBA_D6
FBA_D7
6
L30
FBA_D7
FBA_D8
7
P33
FBA_D8
FBA_D9
8
P34
FBA_D9
FBA_D10
9
N35
FBA_D10
FBA_D11
10
P35
FBA_D11
FBA_D12
11
N34
FBA_D12
FBA_D13
12
L33
FBA_D13
FBA_D14
13
L32
FBA_D14
FBA_D15
14
N33
FBA_D15
FBA_D16
15
K31
FBA_D16
FBA_D17
16
K30
FBA_D17
FBA_D18
17
G30
FBA_D18
FBA_D19
18
K32
FBA_D19
FBA_D20
19
G32
FBA_D20
FBA_D21
20
H30
FBA_D21
FBA_D22
21
F30
FBA_D22
FBA_D23
22
G31
FBA_D23
FBA_D24
23
H33
FBA_D24
FBA_D25
24
K35
FBA_D25
FBA_D26
25
K33
FBA_D26
FBA_D27
26
G34
FBA_D27
FBA_D28
27
K34
FBA_D28
FBA_D29
28
E33
FBA_D29
FBA_D30
29
E34
FBA_D30
FBA_D31
30
G33
FBA_D31
FBA_D32
31
AG30
FBA_D32
FBA_D33
32
AH31
FBA_D33
FBA_D34
33
AG32
FBA_D34
FBA_D35
34
AF31
FBA_D35
FBA_D36
35
AF30
FBA_D36
FBA_D37
36
AD30
FBA_D37
FBA_D38
37
AC32
FBA_D38
FBA_D39
38
AE30
FBA_D39
FBA_D40
39
AE32
FBA_D40
FBA_D41
40
AF33
FBA_D41
FBA_D42
41
AF34
FBA_D42
FBA_D43
42
AE35
FBA_D43
FBA_D44
43
AE33
FBA_D44
FBA_D45
44
AE34
FBA_D45
FBA_D46
45
AC35
FBA_D46
FBA_D47
46
AB32
FBA_D47
FBA_D48
47
AN33
FBA_D48
FBA_D49
48
AK32
FBA_D49
FBA_D50
49
AL33
FBA_D50
FBA_D51
50
AM33
FBA_D51
FBA_D52
51
AL31
FBA_D52
FBA_D53
52
AK30
FBA_D53
FBA_D54
53
AJ30
FBA_D54
FBA_D55
54
AH30
FBA_D55
FBA_D56
55
AM35
FBA_D56
FBA_D57
56
AH33
FBA_D57
FBA_D58
57
AH35
FBA_D58
FBA_D59
58
AH32
FBA_D59
FBA_D60
59
AH34
FBA_D60
FBA_D61
60
AM34
FBA_D61
FBA_D62
61
AL35
FBA_D62
FBA_D63
62
AJ33
FBA_D63
63
FBA_DQM0
P30
FBA_DQM0
FBA_DQM1
0
P32
FBA_DQM1
FBA_DQM2
1
J30
FBA_DQM2
FBA_DQM3
2
H34
FBA_DQM3
FBA_DQM4
3
AF32
FBA_DQM4
FBA_DQM5
4
AF35
FBA_DQM5
FBA_DQM6
5
AL32
FBA_DQM6
FBA_DQM7
6
AL34
FBA_DQM7
7
FBA_DQS_WP0
N31
FBA_DQS_WP0
FBA_DQS_WP1
0
L34
FBA_DQS_WP1
FBA_DQS_WP2
1
J32
FBA_DQS_WP2
FBA_DQS_WP3
2
H35
FBA_DQS_WP3
FBA_DQS_WP4
3
AE31
FBA_DQS_WP4
FBA_DQS_WP5
4
AC33
FBA_DQS_WP5
FBA_DQS_WP6
5
AJ32
FBA_DQS_WP6
FBA_DQS_WP7
6
AJ34
FBA_DQS_WP7
7
FBA_DQS_RN0
N32
FBA_DQS_RN0
FBA_DQS_RN1
0
L35
FBA_DQS_RN1
FBA_DQS_RN2
1
H31
FBA_DQS_RN2
FBA_DQS_RN3
2
G35
FBA_DQS_RN3
FBA_DQS_RN4
3
AD32
FBA_DQS_RN4
FBA_DQS_RN5
4
AC34
FBA_DQS_RN5
FBA_DQS_RN6
5
AJ31
FBA_DQS_RN6
FBA_DQS_RN7
6
AJ35
FBA_DQS_RN7
7
P29
RFU
R29
RFU
L29
RFU
M29
RFU
AD29
RFU
AE29
RFU
AG29
RFU
AH29
RFU
J27
FB_VREF
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBA_DEBUG
FB_DLLAVDD
FB_PLLAVDD
J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
FBA_CMD0
V32
FBA_CMD1
0
W31
FBA_CMD2
1
U31
FBA_CMD3
2
Y32
FBA_CMD4
3
AB35
FBA_CMD5
4
AB34
FBA_CMD6
5
W35
FBA_CMD7
6
W33
FBA_CMD8
W30
FBA_CMD9
8
T34
FBA_CMD10
9
T35
FBA_CMD11
10
AB31
FBA_CMD12
11
Y30
FBA_CMD13
12
Y34
FBA_CMD14
13
W32
FBA_CMD15
14
AA30
FBA_CMD16
15
AA32
FBA_CMD17
16
Y33
FBA_CMD18
17
U32
FBA_CMD19
18
Y31
FBA_CMD20
19
U34
FBA_CMD21
20
Y35
FBA_CMD22
21
W34
FBA_CMD23
22
V30
FBA_CMD24
23
U35
FBA_CMD25
24
U30
SNN_FBA_CMD26
25
U33
FBA_CMD27
AB30
27
AB33
SNN_FBA_CMD29
T33
SNN_FBA_CMD30
W29
T32
FBA_CLK0
T31
FBA_CLK0*
AC31
FBA_CLK1
AC30
FBA_CLK1*
T30
AG27
AF27
FBA_CMD[27..0]
FBA_DEBUG
C652
C652
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C617
C617
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
OUT
4,4
OUT
4,4
OUT
4,4
OUT
4,4
OUT
R589
40.2
R589
40.2
COMMON
0402
COMMON
0402
1%
1%
3,6
OUT
FB_PLLAVDD
FBA_D[63..0]
4,4
BI
1
2
FBA_DQM[7..0]
4,4
4,4
4,4
C630
C630
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
VREF = FBVDDQ * Rbot/(Rtop + Rbot)
OUT
BI
BI
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.3K/(511 + 1.3K)DDR3:
FBA_DQS_WP[7..0]
FBA_DQS_RN[7..0]
3
4
FBVDDQ
Rtop
COMMON
COMMON
511
511
1%
1%
0402
0402
R591
R591
COMMON
COMMON
1.3KR593
1.3K
Rbot
1%
1%
0402
0402
R593
5
PLACE BELOW GPU
C615
C615
C619
C619
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C702
C702
C657
C657
.47UF
.47UF
.47UF
.47UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
FBVDDQ below GPU:
4,4,4,4
PLACE MIDWAY BETWEEN GPU AND MEMORY
FBVDDQ
PLACE close to GPU
C613
C613
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
4x 100nf 0402
6x 470nf 0402
FBVDDQ
C570
C570
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
C0805_67
C0805_67
COMMON
COMMON
C620
C620
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C616
C616
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C647
C647
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C573
C573
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
C0805_67
C0805_67
COMMON
COMMON
C618
C618
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C624
C624
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C612
C612
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C605
C605
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C662
C662
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
2x 1uf 0603
2x 4.7uf 0603
C578
C578
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
C0805_67
C0805_67
COMMON
COMMON
C745
C745
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
C0805_67
C0805_67
COMMON
COMMON
120R@100MHz
120R@100MHz
LB501
LB501
IND_SMD_0402COMMON
IND_SMD_0402COMMON
C603
C603
4.7UF
4.7UF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
COMMON
FBVDDQ
PEX_VDD
C670
C670
4.7UF
4.7UF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
COMMON
NET MIN_LINE_WIDTH VOLTAGE
FBA_VREF
BI
3,6
FB_PLLAVDD
BI
NVVDD
Place below GPU
C671
C671
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C632
C632
.022UF
.022UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C631
C631
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
8MIL
10MIL 1.2V
NVVDD below GPU:
5x 22nf 0402 X7R
5x 100nf 0402 X5R
6x 1uf 0402 X5R
2x 4.7uf 0603 X5R
C677
C677
C661
C661
C645
C645
C664
1UF
1UF
1UF
1UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C638
C638
C679
C679
.022UF
.022UF
.022UF
.022UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C644
C644
C639
C639
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
G1C
G1C
NVVDD NVVDD
BGA_0969_P080_290X290
BGA_0969_P080_290X290
COMMON
COMMON
16/16 NVVDD
16/16 NVVDD
AB11
VDD
AB13
VDD
AB15
VDD
AB17
VDD
AB19
VDD
AB21
VDD
AB23
VDD
AB25
VDD
AC11
VDD
AC12
VDD
AC13
VDD
AC14
VDD
AC15
VDD
AC16
VDD
AC17
VDD
AC18
VDD
AC19
VDD
AC20
VDD
AC21
VDD
AC22
VDD
AC23
VDD
AC24
VDD
AC25
VDD
AD12
VDD
AD14
VDD
AD16
VDD
AD18
VDD
AD22
VDD
AD24
VDD
L11
VDD
L12
VDD
L13
VDD
L14
VDD
L15
VDD
L16
VDD
L17
VDD
L18
VDD
L19
VDD
L20
VDD
L21
VDD
L22
VDD
L23
VDD
L24
VDD
L25
VDD
M12
VDD
M14
VDD
M16
VDD
M18
VDD
M20
VDD
M22
VDD
M24
VDD
P11
VDD
P13
VDD
P15
VDD
P17
VDD
P19
VDD
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C641
C641
.022UF
.022UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C634
C634
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C664
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C672
C672
.022UF
.022UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C636
C636
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
P21
VDD
P23
VDD
P25
VDD
R11
VDD
R12
VDD
R13
VDD
R14
VDD
R15
VDD
R16
VDD
R17
VDD
R18
VDD
R19
VDD
R20
VDD
R21
VDD
R22
VDD
R23
VDD
R24
VDD
R25
VDD
T12
VDD
T14
VDD
T16
VDD
T18
VDD
T20
VDD
T22
VDD
T24
VDD
V11
VDD
V13
VDD
V15
VDD
V17
VDD
V19
VDD
V21
VDD
V23
VDD
V25
VDD
W11
VDD
W12
VDD
W13
VDD
W14
VDD
W15
VDD
W16
VDD
W17
VDD
W18
VDD
W19
VDD
W20
VDD
W21
VDD
W22
VDD
W23
VDD
W24
VDD
W25
VDD
Y12
VDD
Y14
VDD
Y16
VDD
Y18
VDD
Y20
VDD
Y22
VDD
Y24
VDD
C625
C625
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C626
C626
4.7UF
4.7UF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
COMMON
C667
C667
4.7UF
4.7UF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
COMMON
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA MEMORY INTERFACE, GPU NVVDD & FBVDDQ DECOUPLING CAPS
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10727-base-sch A
NAME
PAGEID
DATE
31-OCT-2007
HFDBA
A B C D E F G H
FrameBuffer: Partition A 16/32Mx32 BGA136 GDDR3
FB_A-CS0-LOW-32bit
M3E
M3E
BGA_0136_P080_140X120
FBA_CMD[27..0] FBA_CMD[27..0]
3,4,4,4
IN
1
Low Sub-Partition
FBA_CLK0
3,4
IN
FBA_CLK0*
3,4
IN
2
R680
R680
10K
10K
5%
5%
0402
0402
COMMON
COMMON
FBVDDQ
3
FBA_CMD1
1
FBA_CMD10
10
FBA_CMD11
11
FBA_CMD8
8
CS0
FBA_CMD19
19
FBA_CMD25
25
22
FBA_CMD24
24
FBA_CMD0
0
FBA_CMD2
2
FBA_CMD21
21
FBA_CMD16
16
FBA_CMD23
23
FBA_CMD20
20
FBA_CMD17
17
FBA_CMD9
9
FBA_CMD12
12
FBA_CMD3
3
FBA_CMD27
27
FBA_CMD18
18
SNN_FBA0_NC1 SNN_FBA1_NC1
FBA_CMD14 FBA_CMD14
14
FBA_DEBUG_SEN0 FBA_DEBUG_SEN1
FBA_CMD15 FBA_CMD15
15
FBA_CMD15
FBA_CMD18
R571
R571
10K
10K
R561
R561
10K
10K
5%
5%
0402
0402
5%
5%
COMMON
COMMON
0402
0402
COMMON
COMMON
C531
C531
.047UF
.047UF
C559
C559
.047UF
.047UF
16V
16V
10%
10%
16V
16V
X7R
X7R
10%
10%
0402
0402
X7R
X7R
COMMON
COMMON
0402
0402
COMMON
COMMON
3,4
BI
3,4
BI
3,4
BI
3,4
BI
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
FBA_ZQ0 FBA_ZQ1
A4
R569
R569
243
243
1%
1%
0402
0402
COMMON
COMMON
K1
K12
J1
J12
FBA_D[63..0]
FBA_DQM[7..0]
FBA_DQS_RN[7..0]
FBA_DQS_WP[7..0]
A1 A5
A8/AP A10
A9 A3
BA0
CLK
CLK
NC/RFU
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
NC/CS1NC/CS1
MIRROR
MIRROR
BA2RAS
CSCAS
CKEWE
CASCS
A4A0
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A8/APA10
A7A11
BA1
BA0BA1
RASBA2
WECKE
4
FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3
0
FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3
0
FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3
0
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBA_DQM4 FBA_DQM5 FBA_DQM6
4
FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6
4
FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6
4
FBVDDQ
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
M12
VDD
A1
VDDQ
C1
VDDQ
E1
VDDQ
N1
VDDQ
R1
VDDQ
V1
VDDQ
C4
VDDQ
E4
VDDQ
J4
VDDQ
N4
VDDQ
R4
VDDQ
C9
VDDQ
E9
VDDQ
J9
VDDQ
N9
VDDQ
R9
VDDQ
A12
VDDQ
C12
VDDQ
E12
VDDQ
N12
VDDQ
R12
VDDQ
V12
VDDQ
B1
VSSQ
D1
VSSQ
P1
VSSQ
T1
VSSQ
G2
VSSQ
L2
VSSQ
B4
VSSQ
D4
VSSQ
P4
VSSQ
T4
VSSQ
B9
VSSQ
D9
VSSQ
P9
VSSQ
T9
VSSQ
G11
VSSQ
L11
VSSQ
B12
VSSQ
D12
VSSQ
P12
VSSQ
T12
VSSQ
G1
VSS
L1
VSS
A3
VSS
V3
VSS
A10
VSS
V10
VSS
G12
VSS
L12
VSS
FBA_VREF0
H1
VREF
FBA_VREF1
H12
VREF
VREF = 0.70 * FBVDDQ
DDR3:
VREF = FBVDDQ * R2/(R1 + R2)
1.26V = 1.8V * 1.3K/(511 + 1.3K)
1.4V = 2.0V * 1.3K/(511 + 1.3K)
M3A
M3A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
FBA_D0
0
R11
DQ0
FBA_D1
1
T11
DQ1
FBA_D2
2
R10
DQ2
FBA_D3
3
T10
DQ3
FBA_D4
4
L10
DQ4
FBA_D5
5
M11
DQ5
FBA_D6
6
N11
DQ6
FBA_D7
7
M10
DQ7
N10
DQM
P10
RDQS
P11
WDQS
M4E
M4E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
FBA_D32
32
M3
DQ0
FBA_D33
33
L3
DQ1
FBA_D34
34
M2
DQ2
FBA_D35
35
N2
DQ3
FBA_D36
36
R3
DQ4
FBA_D37
37
T2
DQ5
FBA_D38
38
R2
DQ6
FBA_D39
39
T3
DQ7
N3
DQM
P3
RDQS
P2
WDQS
FBA Partition
136BGA CMD Mapping
ADDR
CMD
RAS*CMD1
CMD10
CAS*
CMD11
WE*
CMD18
CKE
CMD15
RESET/ODT
CS0*
CMD8
CMD19
A<0>
CMD25
A<1>
CMD22
A<2>
CMD24
A<3>
A<4>CMD0
CMD2
A<5>
CMD4
A<2>
CMD6
A<3>
CMD5
A<4>
CMD13
A<5>
CMD21
A<6>
CMD16
A<7>
CMD23
A<8>
CMD20
A<9>
CMD17
A<10
A<11>
CMD9
CMD14
A<12>
CMD12
BA0
BA1
CMD3
CMD27
BA2
FBVDDQ
R575
R575
511
511
R1
1%
1%
0402
0402
COMMON
COMMON
R576
R576
1.3K
1.3K
R2
1%
1%
0402
0402
COMMON
COMMON
8
9
10
11
12
13
14
15
1
1
1
40
41
42
43
44
45
46
47
5
5
5
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
Low Sub-Partition
Hi Sub-Partition
C568
C568
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R10
L10
M11
R11
T10
T11
N11
M10
N10
P10
P11
COMMON
COMMON
COMMON
COMMON
M3B
M3B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
L3
DQ0
M3
DQ1
T3
DQ2
M2
DQ3
R3
DQ4
R2
DQ5
N2
DQ6
T2
DQ7
N3
DQM
P3
RDQS
P2
WDQS
M4A
M4A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
FBVDDQ
R85
R85
511
511
R1
1%
1%
0402
0402
R86
R86
1.3K
1.3K
R2
1%
1%
0402
0402
C GE
C61
C61
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
3,4,4,4
Hi Sub-Partition
ASSEMBLY
PAGE DETAIL
FB_A-CS0-HI-32bit
M4C
M4C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
IN
3,4
IN
3,4
IN
FBVDDQ
R690
R690
10K
10K
5%
5%
0402
0402
COMMON
COMMON
FBVDDQ
FBA_D16
16
F11
FBA_D17
17
G10
FBA_D18
18
B10
FBA_D19
19
E11
FBA_D20
20
C10
FBA_D21
21
F10
FBA_D22
22
C11
FBA_D23
23
B11
2
E10
2
2
6
D10
D11
FBA_D48
48
C3
FBA_D49
49
C2
FBA_D50
50
B3
FBA_D51
51
E2
FBA_D52
52
B2
FBA_D53
53
FBA_D54
54
FBA_D55
55
G3
6
E3
6
D3
D2
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA 16/32Mx32 GDDR3 MEMORIES, FBA COMMAND BUS PU'S, FBA CLK TERMS
C571
C571
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
M3C
M3C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M4B
M4B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
F3
DQ5
F2
DQ6
DQ7
DQM
RDQS
WDQS
FBA_CMD27
27
FBA_CMD8
8
CS0
FBA_CMD18
18
FBA_CMD10
10
FBA_CMD5
5
FBA_CMD13
13
FBA_CMD21FBA_CMD22
21
FBA_CMD20
20
FBA_CMD19
19
FBA_CMD25
25
FBA_CMD4
4
FBA_CMD9
9
FBA_CMD17
17
FBA_CMD6
6
FBA_CMD23
23
FBA_CMD16
16
FBA_CMD3
3
FBA_CMD12
12
FBA_CMD1
1
FBA_CMD11
11
FBA_CLK1
FBA_CLK1*
14
15
R563
R563
243
243
1%
1%
0402
0402
COMMON
COMMON
C62
C62
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
3
3
FBA_DQS_RN7
7
FBA_DQS_WP7
7
BGA136
COMMON
COMMON
BA0
CLK
CLK
NC/RFU
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
3
FBA_DQM7
7
NET
FBA_CLK0
3,4
IN
FBA_CLK0*
3,4
IN
FBA_CLK1
3,4
IN
FBA_CLK1*
3,4
IN
FBVDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
VREF
M3D
M3D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M4D
M4D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
DDR3:
FBA_VREF2
FBA_VREF3
VREF = 0.70 * FBVDDQ
VREF = FBVDDQ * R2/(R1 + R2)
1.26V = 1.8V * 1.3K/(511 + 1.3K)
1.4V = 2.0V * 1.3K/(511 + 1.3K)
COMMON
COMMON
COMMON
COMMON
FBVDDQ
R88
R88
511
511
R1
1%
1%
0402
0402
R87
R87
1.3K
1.3K
R2
1%
1%
0402
0402
BA2RAS
CSCAS
CKEWE
CASCS
A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A10A8/AP
A3A9
A8/APA10
A7A11
BA1
BA0BA1
RASBA2
WECKE
NC/CS1NC/CS1
MIRROR
MIRROR
FBA_D24
24
C2
FBA_D25
25
G3
FBA_D26
26
E2
FBA_D27
27
B2
FBA_D28
28
F2
FBA_D29
29
B3
FBA_D30
30
F3
FBA_D31
31
C3
E3
D3
D2
FBA_D56
56
B10
FBA_D57
57
G10
FBA_D58
58
F10
FBA_D59
59
E11
FBA_D60
60
F11
FBA_D61
61
C10
FBA_D62
62
B11
FBA_D63
63
C11
E10
D10
D11
FBA_D[63..0]
3,4
BI
FBA_DQM[7..0]
3,4
BI
FBA_DQS_WP7
3,4
BI
FBA_DQS_RN7
3,4
BI
FBA_CMD27
3,4,4,4
BI
FBA_VREF0
BI
FBA_VREF1
BI
FBA_VREF2
BI
FBA_VREF3
BI
Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
FBA_CMD[26..0]
3,4,4,4
IN
FBVDDQ
C63
C63
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
R578
R578
0402
0402
511
511
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
R1
1%
1%
0402
0402
R577
R577
1.3K
1.3K
R2
1%
1%
0402
0402
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
0.900V 12MIL
0.900V 12MIL
0.900V 12MIL
0.900V 12MIL
2
0
24
22
13
4
5
6
C567
C567
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBA_CLK0
COMMON
COMMON
FBA_CLK0*
COMMON 0402
COMMON 0402
FBA_CLK1
COMMON
COMMON
FBA_CLK1*
COMMON
COMMON
NV_IMPEDANCEDIFFPAIR
NV_IMPEDANCE
MIN_LINE_WIDTH
FBA_CMD2
FBA_CMD0
FBA_CMD24
FBA_CMD22
FBA_CMD13
FBA_CMD4
FBA_CMD5
FBA_CMD6
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
R559
121 R559
121
0402
0402
1%
1%
R560
121 R560
121
1%
1%
R574
121 R574
121
0402
0402
1%
1%
R572
121 R572
121
0402
0402
1%
1%
600-10727-base-sch A
120
120
COMMON
COMMON
120
120
COMMON
COMMON
120
120
COMMON
COMMON
120
120
COMMON
COMMON
120 R562
120
COMMON5%0402
COMMON5%0402
120
120
COMMON
COMMON
120
120
COMMON
COMMON
120
120
COMMON
COMMON
NAME
NV_CRITICAL_NET
80DIFF
80DIFF 1
80DIFF 1
80DIFF 1
NV_CRITICAL_NET
40OHM 1
40OHM 1
40OHM 1
40OHM 1
40OHM 1
FBVDDQ
R557
R557
0402
0402
5%
5%
R565
R565
0402
0402
5%
5%
R570
R570
0402
0402
5%
5%
R566
R566
0402
0402
5%
5%
R562
R567
R567
0402
0402
5%
5%
R564
R564
0402
0402
5%
5%
R568
R568
0402
0402
5%
5%
FBVDDQ
R545
R545
80.6
80.6
1%
1%
0402
0402
DNI
FBA_CLK0_PU
12MIL 0.900V
FBA_CLK1_PU
12MIL 0.900V
DNI
C529
C529
.01UF
.01UF
6.3V
6.3V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
PAGEID
DATE
HFDBA
1
1
2
3
4
R573
R573
80.6
80.6
1%
1%
0402
0402
DNI
DNI
C552
C552
.01UF
.01UF
6.3V
6.3V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
5
31-OCT-2007
www.vinafix.vn
A B C D E F G H
FRAME BUFFER: PARTITION A DECOUPLING
Decoupling for FBA 0..31
Decoupling for FBA 32..63
1
C539
C539
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C543
C543
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C534
C534
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
10x 100nf 0402
5x 1uf 0603
PLACE NEAR MEMORY FBVDDQ PINS
C556
C556
C547
C547
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C538
C538
C542
C542
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C544
C544
C557
C557
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
C560
C560
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C553
C553
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C563
C563
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C549
C549
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C562
C562
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C535
C535
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
FBVDDQ FBVDDQ
2
FBVDDQ below MEMORY:
Decoupling for FBA A1 0..31 Decoupling for FBA A1 0..31
3
4
FBVDDQ
C746
C746
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C747
C747
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C749
C749
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C748
C748
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C750
C750
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C751
C751
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C840
C840
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C839
C839
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
PLACE NEAR MEMORY FBVDD PINS
C561
C561
C546
C546
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C540
C540
C541
C541
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C545
C545
C533
C533
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
FBVDDQ below MEMORY:
10x 100nf 0402
5x 1uf 0603
FBVDDQ
C841
C841
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C842
C842
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C844
C844
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C843
C843
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C548
C548
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C537
C537
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C532
C532
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C845
C845
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C846
C846
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C554
C554
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C550
C550
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C565
C565
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C850
C850
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C536
C536
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C555
C555
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C566
C566
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C847
C847
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
1
2
3
4
Return path coupling GND/FBVDDQ for FBA
C38
C38
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
PLACE NEAR CMD GTV PIONTS
C44
C44
C40
C40
.01UF
.01UF
.01UF
.01UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C39
C39
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C45
C45
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C42
C42
C655
C655
C640
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C640
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C GE
FBVDDQ
C41
C41
C43
C43
.01UF
.01UF
.01UF
.01UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
COMMON
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA MEMORY FBVDDQ DECOUPLING CAPS
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10727-base-sch A
NAME
5
PAGEID
DATE
31-OCT-2007
HFDBA
A B C D E F G H
G1D
G1D
BGA_0969_P080_290X290
BGA_0969_P080_290X290
COMMON
FBC_D[63..0]
7,7
BI
1
2
FBC_DQM[7..0]
7,7
3
4
OUT
FBC_DQS_WP[7..0]
7,7
BI
FBC_DQS_RN[7..0]
7,7
BI
SNN_FBC_WDS0
SNN_FBC_WDS0*
SNN_FBC_WDS1
SNN_FBC_WDS1*
SNN_FBC_WDS2
SNN_FBC_WDS2*
SNN_FBC_WDS3
SNN_FBC_WDS3*
COMMON
3/16 FBC
3/16 FBC
FBC_D0
0
D11
FBC_D0
FBC_D1
1
E11
FBC_D1
FBC_D2
2
F10
FBC_D2
FBC_D3
3
D8
FBC_D3
FBC_D4
4
F8
FBC_D4
FBC_D5
5
F9
FBC_D5
FBC_D6
6
E8
FBC_D6
FBC_D7
7
F12
FBC_D7
FBC_D8
8
B11
FBC_D8
FBC_D9
9
C13
FBC_D9
FBC_D10
10
A11
FBC_D10
FBC_D11
11
B8
FBC_D11
FBC_D12
12
A8
FBC_D12
FBC_D13
13
C8
FBC_D13
FBC_D14
14
C11
FBC_D14
FBC_D15
15
C10
FBC_D15
FBC_D16
16
D12
FBC_D16
FBC_D17
17
E13
FBC_D17
FBC_D18
18
F17
FBC_D18
FBC_D19
19
F15
FBC_D19
FBC_D20
20
F16
FBC_D20
FBC_D21
21
E16
FBC_D21
FBC_D22
22
F14
FBC_D22
FBC_D23
23
F13
FBC_D23
FBC_D24
24
D13
FBC_D24
FBC_D25
25
A13
FBC_D25
FBC_D26
26
B13
FBC_D26
FBC_D27
27
A14
FBC_D27
FBC_D28
28
C16
FBC_D28
FBC_D29
29
A17
FBC_D29
FBC_D30
30
B16
FBC_D30
FBC_D31
31
D16
FBC_D31
FBC_D32
32
D24
FBC_D32
FBC_D33
33
D26
FBC_D33
FBC_D34
34
E25
FBC_D34
FBC_D35
35
F25
FBC_D35
FBC_D36
36
F27
FBC_D36
FBC_D37
37
E28
FBC_D37
FBC_D38
38
F28
FBC_D38
FBC_D39
39
D29
FBC_D39
FBC_D40
40
A25
FBC_D40
FBC_D41
41
B25
FBC_D41
FBC_D42
42
D25
FBC_D42
FBC_D43
43
C26
FBC_D43
FBC_D44
44
C28
FBC_D44
FBC_D45
45
B28
FBC_D45
FBC_D46
46
A28
FBC_D46
FBC_D47
47
A29
FBC_D47
FBC_D48
48
E29
FBC_D48
FBC_D49
49
F29
FBC_D49
FBC_D50
50
D30
FBC_D50
FBC_D51
51
E31
FBC_D51
FBC_D52
52
C33
FBC_D52
FBC_D53
53
D33
FBC_D53
FBC_D54
54
F32
FBC_D54
FBC_D55
55
E32
FBC_D55
FBC_D56
56
B29
FBC_D56
FBC_D57
57
C29
FBC_D57
FBC_D58
58
B31
FBC_D58
FBC_D59
59
C31
FBC_D59
FBC_D60
60
B32
FBC_D60
FBC_D61
61
C32
FBC_D61
FBC_D62
62
B34
FBC_D62
FBC_D63
63
B35
FBC_D63
FBC_DQM0
0
F11
FBC_DQM0
FBC_DQM1
1
D10
FBC_DQM1
FBC_DQM2
2
D15
FBC_DQM2
FBC_DQM3
3
A16
FBC_DQM3
FBC_DQM4
4
D27
FBC_DQM4
FBC_DQM5
5
D28
FBC_DQM5
FBC_DQM6
6
D34
FBC_DQM6
FBC_DQM7
7
A34
FBC_DQM7
FBC_DQS_WP0
0
E10
FBC_DQS_WP0
FBC_DQS_WP1
1
A10
FBC_DQS_WP1
FBC_DQS_WP2
2
D14
FBC_DQS_WP2
FBC_DQS_WP3
3
C14
FBC_DQS_WP3
FBC_DQS_WP4
4
E26
FBC_DQS_WP4
FBC_DQS_WP5
5
B26
FBC_DQS_WP5
FBC_DQS_WP6
6
D32
FBC_DQS_WP6
FBC_DQS_WP7
7
A32
FBC_DQS_WP7
FBC_DQS_RN0
0
D9
FBC_DQS_RN0
FBC_DQS_RN1
1
B10
FBC_DQS_RN1
FBC_DQS_RN2
2
E14
FBC_DQS_RN2
FBC_DQS_RN3
3
B14
FBC_DQS_RN3
FBC_DQS_RN4
4
F26
FBC_DQS_RN4
FBC_DQS_RN5
5
A26
FBC_DQS_RN5
FBC_DQS_RN6
6
D31
FBC_DQS_RN6
FBC_DQS_RN7
7
A31
FBC_DQS_RN7
G11
RFU
G12
RFU
G14
RFU
G15
RFU
G24
RFU
G25
RFU
G27
RFU
G28
RFU
G96 only
G96 only
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
FBC_DEBUG
FBAC_DLLAVDD
FBAC_PLLAVDD
FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND
FBVDDQ
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27
NET MIN_LINE_WIDTH
FB_CAL_PD
BI
FB_CAL_PU
BI
FB_CAL_TERM
BI
10MIL
10MIL
10MIL
1
2
FBC_CMD[27..0]
FBC_CMD0
0
C17
FBC_CMD1
1
B19
FBC_CMD2
2
D18
FBC_CMD3
3
F21
FBC_CMD4
4
A23
FBC_CMD5
5
D21
FBC_CMD6
6
B23
FBC_CMD7
E20
FBC_CMD8
8
G21
FBC_CMD9
9
F20
FBC_CMD10
10
F19
FBC_CMD11
11
F23
FBC_CMD12
12
A22
FBC_CMD13
13
C22
FBC_CMD14
14
B17
FBC_CMD15
15
F24
FBC_CMD16
16
C25
FBC_CMD17
17
E22
FBC_CMD18
18
C20
FBC_CMD19
19
B22
FBC_CMD20
20
A19
FBC_CMD21
21
D22
FBC_CMD22
22
D20
FBC_CMD23
23
E19
FBC_CMD24
24
D19
FBC_CMD25
25
F18
SNN_FBC_CMD26
C19
FBC_CMD27
27
F22
SNN_FBC_CMD28
C23
SNN_FBC_CMD29
B20
SNN_FBC_CMD30
A20
FBC_CLK0
E17
FBC_CLK0*
D17
FBC_CLK1
D23
FBC_CLK1*
E23
FBC_DEBUG
G19
7,7
OUT
3
7,7
OUT
7,7
OUT
7,7
OUT
7,7
OUT
R603
FBVDDQ
40.2
R603
40.2
COMMON
COMMON
0402
0402
1%
1%
4
Place close to GPU
J19
J18
FB_CAL_PD_VDDQ
K27
FB_CAL_PU_GND
L27
FB_CAL_TERM_GND
M27
R592
R592
0402
0402
R594
R595 40.2
R595 40.2
0402
0402
FB_PLLAVDD
FBVDDQ
40.2
40.2
COMMON
COMMON
1%
1%
40.2R594
40.2
COMMON0402
COMMON0402
1%
1%
COMMON
COMMON
1%
1%
C602
C602
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C596
C596
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
3,3
OUT
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC MEMORY INTERFACE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10727-base-sch A
NAME
5
PAGEID
DATE
31-OCT-2007
HFDBA
A B C D E F G H
FRAMEBUFFER: PARTITION C 16/32Mx32 BGA136 GDDR3
FB_C-CS0-LOW-32bit FB_C-CS0-HI-32bit
M1E
M1E
BGA_0136_P080_140X120
FBC_CMD[27..0] FBC_CMD[27..0]
6,7
IN
1
Low Sub-Partition
6,7
IN
6,7
IN
2
R744
R744
10K
10K
5%
5%
0402
0402
COMMON
COMMON
3
FBC_CMD1
1
FBC_CMD10
10
FBC_CMD11
11
FBC_CMD8
8
CS0
FBC_CMD19
19
FBC_CMD25
25
22
FBC_CMD24
24
FBC_CMD0
0
FBC_CMD2
2
FBC_CMD21
21
FBC_CMD16
16
FBC_CMD23
23
FBC_CMD20
20
FBC_CMD17
17
FBC_CMD9
9
FBC_CMD12
12
FBC_CMD3
3
FBC_CMD27
27
FBC_CMD18
18
FBC_CLK0
FBC_CLK0*
SNN_FBC0_NC1 SNN_FBC1_NC1
FBC_CMD14 FBC_CMD14
14
FBC_DEBUG_SEN0 FBC_DEBUG_SEN1
FBC_CMD15 FBC_CMD15
15
FBC_CMD15
FBC_CMD18
R600
R600
R597
R597
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
FBVDDQ
C716
C716
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
H3
RAS BA2
F4
CAS CS
H9
WE CKE
F9
CS CAS
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
FBC_ZQ0 FBC_ZQ1
A4
R625
R625
243
243
1%
1%
0402
0402
COMMON
COMMON
K1
K12
C728
C728
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
J1
J12
6,7
6,7
6,7
6,7
A2 A6
A4 A0
A5 A1
A6 A2
A7 A11
A8/AP A10
A11 A7
BA0
CKE WE
CLK
CLK
NC/RFU
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
FBC_D[63..0]
BI
FBC_DQM[7..0]
BI
FBC_DQS_RN[7..0]
BI
FBC_DQS_WP[7..0]
BI
NC/CS1NC/CS1
MIRROR
MIRROR
A4A0
A5A1
A9A3
A3A9
A8/APA10
BA1
BA0BA1
RASBA2
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBVDDQ
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
M12
VDD
A1
VDDQ
C1
VDDQ
E1
VDDQ
N1
VDDQ
R1
VDDQ
V1
VDDQ
C4
VDDQ
E4
VDDQ
J4
VDDQ
N4
VDDQ
R4
VDDQ
C9
VDDQ
E9
VDDQ
J9
VDDQ
N9
VDDQ
R9
VDDQ
A12
VDDQ
C12
VDDQ
E12
VDDQ
N12
VDDQ
R12
VDDQ
V12
VDDQ
B1
VSSQ
D1
VSSQ
P1
VSSQ
T1
VSSQ
G2
VSSQ
L2
VSSQ
B4
VSSQ
D4
VSSQ
P4
VSSQ
T4
VSSQ
B9
VSSQ
D9
VSSQ
P9
VSSQ
T9
VSSQ
G11
VSSQ
L11
VSSQ
B12
VSSQ
D12
VSSQ
P12
VSSQ
T12
VSSQ
G1
VSS
L1
VSS
A3
VSS
V3
VSS
A10
VSS
V10
VSS
G12
VSS
L12
VSS
FBC_VREF0
H1
VREF
FBC_VREF1
H12
VREF
VREF = 0.70 * FBVDDQ
DDR3:
VREF = FBVDDQ * R2/(R1 + R2)
1.26V = 1.8V * 1.3K/(511 + 1.3K)
1.4V = 2.0V * 1.3K/(511 + 1.3K)
FBC_D0
0
FBC_D1
1
FBC_D2
2
FBC_D3
3
FBC_D4
4
FBC_D5
5
FBC_D6
6
FBC_D7
7
FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3
0
FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3
0
FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3
0
FBC_D32
32
FBC_D33
33
FBC_D34
34
FBC_D35
35
FBC_D36
36
FBC_D37
37
FBC_D38
38
FBC_D39
39
FBC_DQM4 FBC_DQM5 FBC_DQM6
4
FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6
4
FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6
4
M1A
M1A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
G10
DQ0
F10
DQ1
C10
DQ2
B10
DQ3
E11
DQ4
C11
DQ5
B11
DQ6
F11
DQ7
E10
DQM
D10
RDQS
D11
WDQS
M2E
M2E
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
R2
DQ0
R3
DQ1
T2
DQ2
T3
DQ3
L3
DQ4
M3
DQ5
N2
DQ6
M2
DQ7
N3
DQM
P3
RDQS
P2
WDQS
FBC Partition
136BGA CMD Mapping
CMD
CMD1
CMD11
CMD18
CMD15
CMD8
CMD19
CMD25
CMD22
CMD24
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD14
CMD12
CMD3
CMD27
FBVDDQ
R622
R622
511
511
1%
1%
R1
0402
0402
COMMON
COMMON
R619
R619
1.3K
1.3K
1%
1%
R2
0402
0402
COMMON
COMMON
ADDR
RAS*
CAS*CMD10
WE*
CKE
RESET/ODT
CS0*
A<0>
A<1>
A<2>
A<3>
A<4>CMD0
A<5>
A<2>
A<3>
A<4>
A<5>
A<6>
A<7>
A<8>
A<9>
A<10
A<11>
A<12>
BA0
BA1
BA2
C725
C725
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
Low Sub-Partition
Hi Sub-Partition
1
5
COMMON
COMMON
COMMON
COMMON
FBVDDQ
R80
R80
511
511
1%
1%
0402
0402
R81
R81
1.3K
1.3K
1%
1%
0402
0402
8
9
10
11
12
13
14
15
1
1
40
41
42
43
44
45
46
47
5
5
C GE
NET
FBC_CLK0
6,7
IN
FBC_CLK0*
6,7
IN
FBC_CLK1
6,7
IN
FBC_CLK1*
6,7
FBVDDQ
IN
FBC_D[63..0]
6,7
BI
FBC_DQM[7..0]
6,7
BI
FBC_DQS_WP7
6,7
BI
FBC_DQS_RN7
6,7
BI
FBC_CMD[27..0]
6,7
IN
FBC_VREF0
BI
FBC_VREF1
BI
FBC_VREF2
BI
FBC_VREF3
BI
R1
C47
C47
.1UF
.1UF
FBVDDQ
16V
16V
10%
10%
R2
X7R
X7R
0402
0402
COMMON
COMMON
R581
R581
511
511
1%
1%
0402
0402
COMMON
COMMON
R580
R580
1.3K
1.3K
1%
1%
0402
0402
COMMON
COMMON
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
M2C
M2C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
M1C
M1C
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M2B
M2B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
F2
DQ0
E2
DQ1
G3
DQ2
B2
DQ3
F3
DQ4
C3
DQ5
C2
DQ6
B3
DQ7
E3
DQM
D3
RDQS
D2
WDQS
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
BA2RAS
CAS CS
WE CKE
CS CAS
A4A0
A1 A5
A2 A6
A3 A9
A4 A0
A5 A1
A6 A2
A11A7
A10A8/AP
A9 A3
A8/APA10
A7A11
BA0
BA1
BA1 BA0
BA2 RAS
WECKE
CLK
CLK
NC/RFU
NC/CS1 NC/CS1
SEN (GND)
NONMIRROR
MIRROR
NONMIRROR
MIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
3
3
FBC_DQS_RN7
7
FBC_DQS_WP7
7
FBC_CMD27
27
FBC_CMD8
8
CS0
FBC_CMD18
18
FBC_CMD10
10
FBC_CMD5
5
FBC_CMD13
13
FBC_CMD21FBC_CMD22
21
FBC_CMD20
20
FBC_CMD19
19
FBC_CMD25
Hi Sub-Partition
6,7
6,7
R745
R745
10K
10K
5%
5%
0402
0402
COMMON
COMMON
R1
C37
C37
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
M1B
M1B
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
FBC_D8
F3
DQ0
FBC_D9
G3
DQ1
FBC_D10
E2
DQ2
FBC_D11
B3
DQ3
FBC_D12
C3
DQ4
FBC_D13
B2
DQ5
FBC_D14
F2
DQ6
FBC_D15
C2
DQ7
E3
DQM
D3
RDQS
D2
WDQS
M2A
M2A
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
FBC_D40
M10
DQ0
FBC_D41
L10
DQ1
FBC_D42
N11
DQ2
FBC_D43
T10
DQ3
FBC_D44
T11
DQ4
FBC_D45
R11
DQ5
FBC_D46
R10
DQ6
FBC_D47
M11
DQ7
N10
DQM
P10
RDQS
P11
WDQS
ASSEMBLY
PAGE DETAIL
25
FBC_CMD4
4
FBC_CMD9
9
FBC_CMD17
17
FBC_CMD6
6
FBC_CMD23
23
FBC_CMD16
16
FBC_CMD3
3
FBC_CMD12
12
FBC_CMD1
1
FBC_CMD11
11
FBVDDQ
2
6
FBC_CLK1
FBC_CLK1*
14
15
R579
R579
243
243
1%
1%
0402
0402
COMMON
COMMON
C46
C46
C576
C576
.047UF
.047UF
.047UF
.047UF
16V
16V
16V
16V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
FBC_D16
16
M10
FBC_D17
17
L10
FBC_D18
18
R11
FBC_D19
19
T10
FBC_D20
20
T11
FBC_D21
21
R10
FBC_D22
22
N11
FBC_D23
23
M11
2
N10
2
P10
P11
FBC_D48
48
FBC_D49
49
FBC_D50
50
FBC_D51
51
FBC_D52
52
FBC_D53
53
FBC_D54
54
FBC_D55
55
6
6
IN
IN
FBVDDQ
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC 16/32MX32 GDDR3 MEMORIES, FBC CMD BUS PU'S, FBC CLK TERMS
FBVDDQ
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
M12
VDD
A1
VDDQ
C1
VDDQ
E1
VDDQ
N1
VDDQ
R1
VDDQ
V1
VDDQ
C4
VDDQ
E4
VDDQ
J4
VDDQ
N4
VDDQ
R4
VDDQ
C9
VDDQ
E9
VDDQ
J9
VDDQ
N9
VDDQ
R9
VDDQ
A12
VDDQ
C12
VDDQ
E12
VDDQ
N12
VDDQ
R12
VDDQ
V12
VDDQ
B1
VSSQ
D1
VSSQ
P1
VSSQ
T1
VSSQ
G2
VSSQ
L2
VSSQ
B4
VSSQ
D4
VSSQ
P4
VSSQ
T4
VSSQ
B9
VSSQ
D9
VSSQ
P9
VSSQ
T9
VSSQ
G11
VSSQ
L11
VSSQ
B12
VSSQ
D12
VSSQ
P12
VSSQ
T12
VSSQ
G1
VSS
L1
VSS
A3
VSS
V3
VSS
A10
VSS
V10
VSS
G12
VSS
L12
VSS
FBC_VREF2
H1
VREF
FBC_VREF3
H12
VREF
VREF = 0.70 * FBVDDQ
DDR3:
VREF = FBVDDQ * R2/(R1 + R2)
1.26V = 1.8V * 1.3K/(511 + 1.3K)
1.4V = 2.0V * 1.3K/(511 + 1.3K)
M1D
M1D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
FBC_D24
24
M2
DQ0
FBC_D25
25
M3
DQ1
FBC_D26
26
L3
DQ2
FBC_D27
27
N2
DQ3
FBC_D28
28
R2
DQ4
FBC_D29
29
R3
DQ5
FBC_D30
30
T2
DQ6
FBC_D31
31
T3
DQ7
3
N3
DQM
P3
RDQS
P2
WDQS
M2D
M2D
BGA_0136_P080_140X120
BGA_0136_P080_140X120
BGA136
BGA136
COMMON
COMMON
FBC_D56
56
G10
DQ0
FBC_D57
57
F11
DQ1
FBC_D58
58
E11
DQ2
FBC_D59
59
F10
DQ3
FBC_D60
60
B11
DQ4
FBC_D61
61
C11
DQ5
FBC_D62
62
B10
DQ6
FBC_D63
63
C10
DQ7
FBC_DQM7
7
E10
DQM
D10
RDQS
D11
WDQS
COMMON
COMMON
COMMON
COMMON
R83
R83
511
511
1%
1%
0402
0402
R82
R82
1.3K
1.3K
1%
1%
0402
0402
DIFFPAIR
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
0.900V 12MIL
0.900V 12MIL
0.900V 12MIL
Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
FBC_CMD[26..0]
R1
R2R2
2
0
24
22
13
4
5
6
C593
C593
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R613
121 R613
121
0402
COMMON
0402
COMMON
1%
1%
R618
121 R618
121
COMMON1%0402
COMMON1%0402
R587
121 R587
121
COMMON 0402
COMMON 0402
1%
1%
R588
121 R588
121
COMMON 0402
COMMON 0402
1%
1%
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
FBC_CMD2
FBC_CMD0
FBC_CMD24
FBC_CMD22
FBC_CMD13
FBC_CMD4
FBC_CMD5
FBC_CMD6
NAME
NV_IMPEDANCE NV_CRITICAL_NET
80DIFF 1
NV_IMPEDANCE NV_CRITICAL_NET
40OHM 1
40OHM 1
MIN_LINE_WIDTH
12MIL0.900V
R617
120 R617
120
COMMON 0402
COMMON 0402
5%
5%
R614
120
R614
120
COMMON
0402
COMMON
0402
5%
5%
R609
120 R609
120
COMMON5%0402
COMMON5%0402
R611
120 R611
120
COMMON5%0402
COMMON5%0402
R582
120
R582
120
COMMON
0402
COMMON
0402
5%
5%
R584
120 R584
120
COMMON5%0402
COMMON5%0402
R585
120 R585
120
COMMON5%0402
COMMON5%0402
R586
120
R586
120
COMMON
COMMON
0402
0402
5%
5%
R616
R616
80.6
80.6
1%
1%
0402
0402
COMMON
FBC_CLK0_PU
12MIL 0.900V
FBC_CLK1_PU
12MIL 0.900V
COMMON
C727
C727
.01UF
.01UF
6.3V
6.3V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
600-10727-base-sch A
FBVDDQ
FBVDDQ
R590
R590
80.6
80.6
1%
1%
0402
0402
COMMON
COMMON
HFDBA
C609
C609
.01UF
.01UF
6.3V
6.3V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
180DIFF
180DIFF
180DIFF
140OHM
140OHM
140OHM
1
2
3
4
5
PAGEID
DATE
31-OCT-2007
www.vinafix.vn
A B C D E F G H
FRAMEBUFFER: PARTITION C DECOUPLING
Decoupling for FBC 0..31
1
2
FBVDDQ FBVDDQ
PLACE NEAR MEMORY FBVDDQ PINS
C738
C738
C711
C711
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C724
C724
C722
C722
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C708
C708
C712
C712
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
FBVDDQ below MEMORY:
10x 100nf 0402
5x 1uf 0603
C691
C691
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C740
C740
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C737
C737
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C694
C694
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C733
C733
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C704
C704
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C732
C732
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C741
C741
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C736
C736
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
Decoupling for FBC C1 0..31 Decoupling for FBC C1 32..63
3
4
FBVDDQ
C851
C851
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C852
C852
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C854
C854
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C853
C853
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C855
C855
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C856
C856
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C858
C858
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C857
C857
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
Decoupling for FBC 32..63
PLACE NEAR MEMORY FBVDDQ PINS
C606
C606
C582
C582
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C587
C587
C614
C614
.1UF
.1UF
.1UF
.1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C575
C575
C610
C610
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
FBVDDQ below MEMORY:
10x 100nf 0402
5x 1uf 0603
FBVDDQ
C859
C859
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C860
C860
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C862
C862
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C861
C861
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C598
C598
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C584
C584
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C585
C585
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C863
C863
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C864
C864
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C595
C595
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C600
C600
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C627
C627
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C866
C866
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C592
C592
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C607
C607
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C579
C579
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C865
C865
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA2
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AA5
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD11
AD13
AD15
AD17
AD2
AD21
AD23
AD25
AD31
AD34
AD5
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG31
AG34
AG5
AK2
AK31
AK34
AK5
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AL6
AL9
AN2
AN34
AP12
AP15
AP18
AP21
AP24
AP27
AP3
AP30
AP33
AP6
AP9
B12
B15
B21
B24
B27
B3
B30
B33
B6
B9
C2
C34
E12
G1E
G1E
BGA_0969_P080_290X290
BGA_0969_P080_290X290
COMMON
COMMON
15/16 GND
15/16 GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E15
GND
E18
GND
E24
GND
E27
GND
E30
GND
E6
GND
E9
GND
F2
GND
F31
GND
F34
GND
F5
GND
J2
GND
J31
GND
J34
GND
J5
GND
L9
GND
M11
GND
M13
GND
M15
GND
M17
GND
M19
GND
M2
GND
M21
GND
M23
GND
M25
GND
M31
GND
M34
GND
M5
GND
N11
GND
N12
GND
N13
GND
N14
GND
N15
GND
N16
GND
N17
GND
N18
GND
N19
GND
N20
GND
N21
GND
N22
GND
N23
GND
N24
GND
N25
GND
P12
GND
P14
GND
P16
GND
P18
GND
P20
GND
P22
GND
P24
GND
R2
GND
R31
GND
R34
GND
R5
GND
T11
GND
T13
GND
T15
GND
T17
GND
T19
GND
T21
GND
T23
GND
T25
GND
U11
GND
U12
GND
U13
GND
U14
GND
U15
GND
U16
GND
U17
GND
U18
GND
U19
GND
U20
GND
U21
GND
U22
GND
U23
GND
U24
GND
U25
GND
V12
GND
V14
GND
V16
GND
V18
GND
V2
GND
V20
GND
V22
GND
V24
GND
V31
GND
V5
GND
V9
GND
Y11
GND
Y13
GND
Y15
GND
Y17
GND
Y19
GND
Y21
GND
Y23
GND
Y25
GND
1
2
3
4
Return path coupling GND/FBVDDQ for FBC
C54
C54
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
PLACE NEAR CMD GTV PIONTS
C53
C53
C56
C56
.01UF
.01UF
.01UF
.01UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C60
C60
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C52
C52
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C590
C590
C57
C57
C588
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C588
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
.01UF
.01UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C GE
FBVDDQ
C51
C51
C58
C58
.01UF
.01UF
.01UF
.01UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
COMMON
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC MEMORY FBVDDQ DECOUPLING CAPS, GPU GND CONNECTIONS
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NV_PN
600-10727-base-sch A
NAME
5
PAGEID
DATE
31-OCT-2007
HFDBA
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