MSI MS-v118 Schematic 3.0

8

7

6

5

4

3

2

1

D D

SMBCLK(2)
SMBDATA(2)

TP6TP6

PETn0_GFXRn0(2)

PETp1_GFXRp1(2)
PETn1_GFXRn1(2)

PETp2_GFXRp2(2)

C C

+12V_BUS

C1

CAP CER 10UF 20% 16V X5R

10UFC110UF

(1206)1.8MM H MAX

+12V_BUS

+12V_BUS

C2

C3

150nF_16VC2150nF_16V

150nF_16VC3150nF_16V

+3.3V_BUS

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

C4

+3.3V_BUS

10uFC410uF

C5
1uF_6.3VC51uF_6.3V

Place these caps last,
ideally as close to the bus
connector as possible

C6
1uF_6.3VC61uF_6.3V

C0
10nFC010nF

B B

PETn2_GFXRn2(2)

PETp3_GFXRp3(2)
PETn3_GFXRn3(2)

PETp4_GFXRp4(2)
PETn4_GFXRn4(2)

PETp5_GFXRp5(2)
PETn5_GFXRn5(2)

PETp6_GFXRp6(2)
PETn6_GFXRn6(2)

PETp7_GFXRp7(2)
PETn7_GFXRn7(2)

PETp8_GFXRp8(2)
PETn8_GFXRn8(2)

PETp9_GFXRp9(2)
PETn9_GFXRn9(2)

PETp10_GFXRp10(2)
PETn10_GFXRn10(2)

PETp11_GFXRp11(2)
PETn11_GFXRn11(2)

PETp12_GFXRp12(2)
PETn12_GFXRn12(2)

PETp13_GFXRp13(2)
PETn13_GFXRn13(2)

PETp14_GFXRp14(2)
PETn14_GFXRn14(2)

PETp15_GFXRp15(2)
PETn15_GFXRn15(2)

PRESENCE

PCI-EXPRESS EDGE CONNECTOR

+12V_BUS+3.3V_BUS +3.3V_BUS+12V_BUS

x16 PCIe

x16 PCIe

PRSNT1#A1

+12V#A2
+12V#A3

GND#A4

JTAG2
JTAG3
JTAG4
JTAG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12
REFCLK+
REFCLK­GND#A15

PERp0
PERn0

GND#A18

RSVD#A19

GND#A20

PERp1

PERn1
GND#A23
GND#A24

PERp2

PERn2
GND#A27
GND#A28

PERp3

PERn3
GND#A31

RSVD#A32
RSVD#A33

GND#A34

PERp4

PERn4
GND#A37
GND#A38

PERp5

PERn5
GND#A41
GND#A42

PERp6

PERn6
GND#A45
GND#A46

PERp7

PERn7
GND#A49

RSVD#A50

GND#A51

PERp8

PERn8
GND#A54
GND#A55

PERp9

PERn9
GND#A58
GND#A59

PERp10

PERn10
GND#A62
GND#A63

PERp11

PERn11
GND#A66
GND#A67

PERp12

PERn12
GND#A70
GND#A71

PERp13

PERn13
GND#A74
GND#A75

PERp14

PERn14
GND#A78
GND#A79

PERp15

PERn15
GND#A82

MPCIE1

MPCIE1

R158 0RR158 0R
R159 0RR159 0R

B1

+12V#B1

B2

+12V#B2

B3

+12V#B3

B4

SMCLK
SMDAT JTDI

JTRST#

B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1

3.3Vaux
WAKE#

RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82

Mechanical Key

Mechanical Key

TP4TP4

TP3TP3

TP1TP1

PERp0
PERn0

PERp1
PERn1

PERp2
PERn2

PERp3
PERn3

PERp4
PERn4

PERp5
PERn5

PERp6
PERn6

PERp7
PERn7

PERp8
PERn8

PERp9
PERn9

PERp10
PERn10

PERp11
PERn11

PERp12
PERn12

PERp13
PERn13

PERp14
PERn14

PERp15
PERn15

PRESENCE

JTCK
JTDO

JTMS

C7
100nFC7100nF

C9
100nFC9100nF

C11

C11
100nF

100nF

C13

C13
100nF

100nF

C15

C15
100nF

100nF

C17

C17
100nF

100nF

C19

C19
100nF

100nF C20

C21

C21
100nF

100nF

C23

C23
100nF

100nF

C25

C25
100nF

100nF

C27

C27
100nF

100nF

C29

C29
100nF

100nF

C31

C31
100nF

100nF

C33

C33
100nF

100nF

C35

C35
100nF

100nF

C37

C37
100nF

100nF C38

C8
100nFC8100nF

C10

C10
100nF

100nF

C12

C12
100nF

100nF

C14

C14
100nF

100nF

C16

C16
100nF

100nF

C18

C18
100nF

100nF

C20
100nF

100nF

C22

C22
100nF

100nF

C24

C24
100nF

100nF

C26

C26
100nF

100nF

C28

C28
100nF

100nF

C30

C30
100nF

100nF

C32

C32
100nF

100nF

C34

C34
100nF

100nF

C36

C36
100nF

100nF

C38
100nF

100nF

PCIE_REFCLKP (2)
PCIE_REFCLKN (2)PETp0_GFXRp0(2)

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)

GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)

GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)

GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)

GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)

GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)

GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)

GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)

GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)

GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)

GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)

GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)

GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)

GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)

GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)

GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)

TP2TP2

PERST#

+3.3V

C39

C39
100nF

100nF

53

1

4

2

U5

U5
NC7SZ08P5X_NL

NC7SZ08P5X_NL

PERST#_buf (2)

SYMBOL LEGEND

DO NOT

DNI

INSTALL
ACTIVE

#

LOW

Doc No.

Doc No.

Doc No.

1

DIGITAL
GROUND

ANALOG
GROUND

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

8

7

6

5

4

3

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

1 20

of

1 20

of

1 20

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

D D

4

3

2

1

NOTE: some of the PCIE testpoints will
be available through via on traces.

PETp0_GFXRp0(1)
PETn0_GFXRn0(1)

PETp1_GFXRp1(1)
PETn1_GFXRn1(1)

PETp2_GFXRp2(1)
PETn2_GFXRn2(1)

PETp3_GFXRp3(1)
PETn3_GFXRn3(1)

PETp4_GFXRp4(1)
PETn4_GFXRn4(1)

PETp5_GFXRp5(1)
PETn5_GFXRn5(1)

PETp6_GFXRp6(1)

C C

B B

PETn6_GFXRn6(1)

PETp7_GFXRp7(1)
PETn7_GFXRn7(1)

PETp8_GFXRp8(1)
PETn8_GFXRn8(1)

PETp9_GFXRp9(1)
PETn9_GFXRn9(1)

PETp10_GFXRp10(1)
PETn10_GFXRn10(1)

PETp11_GFXRp11(1)
PETn11_GFXRn11(1)

PETp12_GFXRp12(1)
PETn12_GFXRn12(1)

PETp13_GFXRp13(1)
PETn13_GFXRn13(1)

PETp14_GFXRp14(1)
PETn14_GFXRn14(1)

PETp15_GFXRp15(1)
PETn15_GFXRn15(1)

PCIE_REFCLKP(1)
PCIE_REFCLKN(1)

DNI DNI

R13

R13
51R

51R

402 402

R14

R14
51R

51R

TP11TP11

TP12TP12

TP13TP13

TP14TP14

TP19TP19

TP20TP20

TP21TP21

TP22TP22 TP23TP23

TP27TP27

TP28TP28

SMBCLK(1)
SMBDATA(1)

PERST#_buf(1)

TP7TP7

TP8TP8

TP9TP9

TP10TP10

TP15TP15

TP16TP16

TP17TP17

TP18TP18

TP24TP24

TP25TP25

TP26TP26

AC30
AC31

AC29
AB29

AB31
AB30

AA31
AA30

AD29
AD30

AC28
AC27

AG25

W30
W31

W29

V29

V31
V30

U31
U30

P30
P31

P29
N29

N31
N30

M31
M30

K30
K31

K29

J29

J31
J30

H31
H30

U1A

U1A

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

PCIE_RX10P
PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX12P
PCIE_RX12N

PCIE_RX13P
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N

PCIE_RX15P
PCIE_RX15N

Clock

Clock

PCIE_REFCLKP
PCIE_REFCLKN

NC_SMBCLK
NC_SMBDATA

PERSTB

RV620 GL A11 RH

RV620 GL A11 RH

PART 1 OF 6

PART 1 OF 6

P

P
C

C
I

I

-

­E

E
X

X
P

P
R

R
E

E
S

S
S

S

I

I
N

N
T

T
E

E
R

R
F

F
A

A
C

C
E

E

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

Calibration

Calibration

PCIE_CALRN
PCIE_CALRP

AA28
AA27

AA25
AA24

Y28
Y27

Y25
Y24

V28
V27

V25
V24

T28
T27

T25
T24

P28
P27

P25
P24

M28
M27

M25
M24

L28
L27

L25
L24

J28
J27

G28
G27

PCIE_CALRN

AF25

PCIE_CALRP

AE25

PCIE_CALI

AE23

NC

+1.1V

402

R82.0K R82.0K

402

R91.27K R91.27K

402

R1010K R1010K

GFXTp0_PERp0 (1)
GFXTn0_PERn0 (1)

GFXTp1_PERp1 (1)
GFXTn1_PERn1 (1)

GFXTp2_PERp2 (1)
GFXTn2_PERn2 (1)

GFXTp3_PERp3 (1)
GFXTn3_PERn3 (1)

GFXTp4_PERp4 (1)
GFXTn4_PERn4 (1)

GFXTp5_PERp5 (1)
GFXTn5_PERn5 (1)

GFXTp6_PERp6 (1)
GFXTn6_PERn6 (1)

GFXTp7_PERp7 (1)
GFXTn7_PERn7 (1)

GFXTp8_PERp8 (1)
GFXTn8_PERn8 (1)

GFXTp9_PERp9 (1)
GFXTn9_PERn9 (1)

GFXTp10_PERp10 (1)
GFXTn10_PERn10 (1)

GFXTp11_PERp11 (1)
GFXTn11_PERn11 (1)

GFXTp12_PERp12 (1)
GFXTn12_PERn12 (1)

GFXTp13_PERp13 (1)
GFXTn13_PERn13 (1)

GFXTp14_PERp14 (1)
GFXTn14_PERn14 (1)

GFXTp15_PERp15 (1)
GFXTn15_PERn15 (1)

For Tektronix LA only

Place close
to ASIC

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

5

4

3

2

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

2 20

of

2 20

of

2 20

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

PSYNC(4,13)

VID_6(13)
VID_7(13)

D D

C C

GPIO_16 IS OUT ONLY

B B

+3.3V_BUS

B80

B80
BLM15BD121SN1

BLM15BD121SN1

C81

C81

1uF_6.3V

1uF_6.3V

A A

C80

C80
100nF

100nF

GPIO21_BB_EN(13)

XTALOUT

GPIO_[13..0](13)

PWRCNTL_0(11,13)

ThermINT(17)

PWRCNTL_1(11)

GPIO_22(13)

XTALOUT_S
is done for
ease of layout

C82

C82
12pF_50V

12pF_50V

C83

C83
22pF

22pF

PLACE TOGETHER

CTFb(17)

Y81

Y81

4

VCC

2

GND

27.000MHz

27.000MHz

5

Y82

Y82

27.000MHz_10PPM

27.000MHz_10PPM

2 1

OUT

E/D

+3.3V

TP47TP47

TP48TP48

R33 33RR33 33R

XTALIN

3
1

+3.3V

R47

R47

R48

R48

4.7K

4.7K

4.7K

4.7K

FLOW_CONTROL_1 - Lower Cable
FLOW_CONTROL_2 - Upper Cable
SWAP_LOCK_1 - Lower Cable
SWAP_LOCK_2 - Upper Cable

GPIO_8
GPIO_9
GPIO_10

MR51KMR5
1K

R81 182RR81 182R

OSC_EN (11,12)

TP57TP57
TP54TP54

TP50TP50
TP62TP62

TP61TP61
TP64TP64
TP63TP63

+1.8V_D2

R30 33RR30 33R
R31 33RR31 33R
R32 33RR32 33R

R43 221RR43 221R

R44 110RR44 110R
C46 100nFC46 100nF

OSC_OUT

R82

R82

51.1R

51.1R

R841MR84
1M

DVALID(13)

GPIO_18(13)

GENERICB(13)
GENERICC(13)

R83 0RR83 0R

MR83 0RMR83 0R

XTALIN

XTALOUT

PSYNC

VID_6
VID_7

DVALID

SCL
SDA

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO8_SO
GPIO9_SI
GPIO10_SCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14

PWRCNTL_0

GPIO_16

GPIO_18
CTFb
PWRCNTL_1
GPIO21_BB_EN

GPIO22_CS
PCIE_CLK_REQb
JTAG_MODE

JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

GENERICB
GENERICC

VREFG

XTALIN

XTALOUT

4

AE7

AH6
AG6

AD9
AA4

AA5
AK4

AL3

AA2
AA3
AB1
AB2
AB3
AC1
AC3
AD1
AD2
AD3
AF3
AG3
AH3
AG1
AH2
AH1

AK2
AK3

AC11

AJ31

AJ30

4

U1B

U1B

V2
V1

W3
W1

Y1
Y2
Y3

AJ3
AJ1
AJ2

Y4
V3
V4
V5
U3
U2
T4
T5
T7
T8
R1
R2
R3
P1
P3
N1
N2
P4
P7
P8
P5
V7
N3
Y5
M4
M5
M7
M8
L8

Y8
Y7
V8

RV620 GL A11 RH

RV620 GL A11 RH

PSYNC_NEW

GEN_D_HPD4
GEN_E

MISC/I2C

MISC/I2C

DVALID
SDA

SCL
DVPCNTL_MVP_0

DVPCNTL_MVP_1
DVPCNTL_0

DVPCNTL_1
DVPCNTL_2

DVPCLK
DVPDATA_0

DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5

External

External

DVPDATA_6

TMDS

TMDS

DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

GPIO_0
GPIO_1
GPIO_2

General

General

GPIO_3

Purpose

Purpose

GPIO_4

I/O

I/O

GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTFB
GPIO_20_PWRCNTL1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
GPIO_24_JMODE
GPIO_25_TDI
GPIO_26_TCK
GPIO_27_TMS
GPIO_28_TDO

GENERICA
GENERICB
GENERICC

VREFG

XTALIN

XTAL

XTAL

XTALOUT

PART 2 OF 6

PART 2 OF 6

PLL Power

PLL Power

DAC / CRT

DAC / CRT

DAC2 (TV/CRT2)

DAC2 (TV/CRT2)

Monitor

Monitor
Interface

Interface

DDC3DATA_DP3_AUXN

DDC3CLK_DP3_AUXP

Thermal

Thermal

Test

Test

DPLL_PVDD

DPLL_PVSS

PCIE_PVDD

MPVDD

MPVSS

DPLL_VDDC

HSYNC
VSYNC

RSET
AVDD

AVSSQ

VDD1DI

VSS1DI

COMP

V2SYNC
H2SYNC

A2VDD

A2VDDQ
A2VSSQ

VDD2DI

VSS2DI
R2SET

HPD1

DDC1DATA

DDC1CLK

DDC2DATA

DDC2CLK

TS_FDO

DPLUS

DMINUS

TESTEN

PLLTEST

3

+DPLL_PVDD

AH12

C71

C71

C72

C72

100nF

100nF

10uF_X6S

10uF_X6S

GND_PVSS

AG12

GND_PVSS

+PCIE_PVDD

AH31

C933

C933

C932

C932

1uF_6.3V

1uF_6.3V

10uF_X6S

10uF_X6S

+MPVDD

A9

GND_MPVSS

B9

+DPLL_VDDC

AE12

AL28
AK28

AL27
AK27

AL26
AK26

AK29
AK30

AJ28
AL29

AH28
AJ27
AJ26

AL17
AK17

AL15
AK15

AL14
AK14

AJ17
AJ15
AJ14
AE16

AF16
AH14

AH16
AG16
AF18
AE18
AG14
AA8
AJ29

AH29
AC5

AC4
AF4

AH4
AE14
AE5

AE4
AH26
AD12

A_R_DAC1 (14)

A_RB_DAC1 (14)

A_G_DAC1 (14)

A_GB_DAC1 (14)

A_B_DAC1 (14)

A_BB_DAC1 (14)

A_HSYNC_DAC1 (13,14)
A_VSYNC_DAC1 (13,14)

RSET

R1030 499RR1030 499R

+AVDD

+VDD1DI

A_VSYNC_DAC2 (13,15)
A_HSYNC_DAC2 (13,15)

+A2VDDQ

TEST_EN

C1020

C1020
10nF

10nF

10VX7R
40210%

C1023

C1023
10nF

10nF

A_R_DAC2 (15)

A_RB_DAC2 (15)

A_G_DAC2 (15)

A_GB_DAC2 (15)

A_B_DAC2 (15)

A_BB_DAC2 (15)

C2021

C2021
100nF

100nF

C2024

C2024
10nF

10nF

R2SET

HPD1 (14)

CRT1DDCDATA (14)
CRT1DDCCLK (14)

CRT2DDCDATA (15)
CRT2DDCCLK (15)

TS_FDO (17)

GPU_DPLUS (17)

GPU_DMINUS (17)

TP42TP42

C2022

C2022
1uF_6.3V

1uF_6.3V

3

R

RB

G

GB

B

BB

R2

R2B

G2

G2B

B2

B2B

C
Y

+DPLL_PVDD

C70

C70

10nF

10nF

C931

C931

100nF

100nF

C60

C60

C61

C61

10nF

10nF

100nF

100nF

GND_PVSS

C1022

C1022

C1021

C1021
100nF

100nF

1uF_6.3V

1uF_6.3V

6.3VX5R

10VX5R

402 10%

40210%

C1025

C1025

C1024

C1024
100nF

100nF

1uF_6.3V

1uF_6.3V

+A2VDD +3.3V

B2030 120R_300mAB2030 120R_300mA

C2032

C2032
1uF_6.3V

1uF_6.3V

+VDD2DI

C2025

C2025

C2026

C2026

100nF

100nF

1uF_6.3V

1uF_6.3V

R2030 715RR2030 715R

+3.3V

R40

R40

4.7K

4.7K

402 402

R7 1KR7 1K

MR71KMR7
1K

NS70NS_VIA NS70NS_VIA

12

C84

C84

C85

C85

C86

C86

100nF

100nF

10nF

10nF

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C62

C62
1uF_6.3V

1uF_6.3V

GND_AVSSQ

NS1020NS_VIANS1020NS_VIA

12

GND_AVSSQ

NS1021NS_VIANS1021NS_VIA

12

GND_VSS1DI

Possible alternate 5150005600G

C2031

C2031
100nF

100nF

NS2020NS_VIANS2020NS_VIA

12

GND_A2VSSQ

NS2021NS_VIANS2021NS_VIA

12

GND_VSS2DI

GND_A2VSSQ

I2C DEVICE ADDRESS' ON DDC3

DEVICE
LM63

+3.3V

ADDRESS
x100 1100

DDC3DATA (11,17)
DDC3CLK (11,17)

R41

R41

4.7K

4.7K

C76

C76

C63

C63
10uF_X6S

10uF_X6S

B6760R B6760R

GND_MPVSS

2

+1.8V_D2

B931

B931

BLM15BD121SN1

BLM15BD121SN1

+VDDC

NS64NS_VIA NS64NS_VIA

12

+1.1V

B60

B60
BLM15BD121SN1

BLM15BD121SN1

+3.3V

GPIO_22
GPIO_8

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

2

Title

+3.3V

R46

R46

NEW CHINGIS SERIAL FLASH

10K

10K

U2

U2

1

CE#

VCC

2

SO

ROM_WP

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

HOLD#

3

WP#

SCK

GND4SI

PM25LV512A-100SCE

PM25LV512A-100SCE

1

8
7

GPIO_10

6

GPIO_9

5

BIOS1

BIOS1

BIOS

BIOS

113-XXXXXX-XXX

113-XXXXXX-XXX
VIDEO BIOS
FIRMWARE

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

3 20

of

3 20

of

3 20

1

Doc No.

Doc No.

Doc No.

+3.3V

C47

C47
100nF

100nF

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

D D

+1.8V_D2

LTVDD18_IN

32

Q100

Q100

SI2304DS

SI2304DS

1

LVT_EN(11)

+3.3V_BUS

C C

B B

SI2304DS

SI2304DS

1

Q101

Q101

32

PLEASE SEE p.13 FOR STRAP DETAILS

LTVDD33_IN

BLM15BD121SN1

BLM15BD121SN1

NS110NS_VIA NS110NS_VIA

1 2

GND_TPVSS

BLM15BD121SN1

BLM15BD121SN1

+LTVDD18

B100

B100

B101

B101

4.7uF_6.3V

4.7uF_6.3V

+1.8V_D2

+1.1V

DPAVSS-VID5(13)
DPAVSS-VID4(13)
DPVSS-VID0(13)
DPAVSS-VID3(13)

R1100RR110
0R

C119

C119

10uF_X6S

10uF_X6S

OVERLAP C119 & C118

+1.8V_D2

+TPVDD

C110

C110
10nF

10nF

BLM15BD121SN1

BLM15BD121SN1
BLM15BD121SN1

BLM15BD121SN1

INSTALL B888 FOR RV610
INSTALL B881 FOR RV620OVERLAP

4

RV620: INSTALL R110, DNI B101, Q101.
RV610: DNI R110

RV620 DECOUPLING RECOMMENDATIONS FOR T2XVDDR/C WILL
BE AVAILABLE AFTER BU. C118 AND C103 WILL NOT BOTH BE
INSTALLED.

LVDDR

C106

C106

C105

1uF_6.3V

1uF_6.3V

+LTVDD18

1 2

10uF_X6S

10uF_X6S

NS100NS_VIA NS100NS_VIA

1uF_6.3V

1uF_6.3V

C102

C102

C108

C108

C105

100nF

100nF

C101

C101
100nF

100nF

GND_T2PVSS

C109

C109

100nF

100nF

C100

C100
1uF_6.3V

1uF_6.3V

+TPVDD

GND_TPVSS

DPAB_VDDR

DPAVSS-VID5
DPAVSS-VID4
DPVSS-VID0
DPAVSS-VID3

C118

C118

C103

C103

10uF_X6S

10uF_X6S

B888

B888
B881

B881

3

U1F

U1F

PART 6 OF 6

PART 6 OF 6

AF20

T2XVDDR_1

AG20

T2XVDDR_2

Control

Control

LVTM channel

T2XVDDC_1
T2XVDDC_2

T2XVSSR_1
T2XVSSR_2
T2XVSSR_3
T2XVSSR_4
T2XVSSR_5
T2XVSSR_6
T2XVSSR_7
T2XVSSR_8
T2XVSSR_9
T2XVSSR_10
T2XVSSR_11

T2PVDD
T2PVSS

Integrated TMDP

Integrated TMDP

DPA_PVDD
DPB_PVDD

DPA_PVSS
DPB_PVSS

DPA_VDDR_1
DPA_VDDR_2
DPB_VDDR_2
DPB_VDDR_1

DPA_VSSR_1
DPA_VSSR_2
DPA_VSSR_3
DPA_VSSR_4
DPA_VSSR_5
DPB_VSSR_1
DPB_VSSR_2
DPB_VSSR_3
DPB_VSSR_4
DPB_VSSR_5

LVTM channel

DDC4CLK_DP4_AUXP

DDC4DATA_DP4_AUXN

AJ18

AH20

AF23
AF21
AL18

AJ22

AJ25
AK18
AK23
AK25

AJ21
AL23
AL25

AG18
AH18

AL7

AE11

AK7

AF11

AJ12

AJ13
AK13

C11410nF C11410nF

AL13

AF7

AG7

AH7
AJ7

AJ8
AH11
AL12

AH9

AJ11

AK12

RV620 GL A11 RH

RV620 GL A11 RH

RSVD_7

RSVD

RSVD_1
RSVD_2

T2X4P

T2X4M

T2X5P

T2X5M
RSVD_4
RSVD_3
RSVD_6
RSVD_5

T2XCP

T2XCM

T2X0P

T2X0M

T2X1P

T2X1M

T2X2P

T2X2M

T2X3P

T2X3M

TXCM_DPA0P
TXCP_DPA0N

TX0M_DPA1P
TX0P_DPA1N

TX1M_DPA2P
TX1P_DPA2N

TX2M_DPA3P
TX2P_DPA3N

TXCM_DPB0P
TXCP_DPB0N

TX0M_DPB1P
TX0P_DPB1N

TX1M_DPB2P
TX1P_DPB2N

TX2M_DPB3P
TX2P_DPB3N

DP_CALR

AA7
AC6

AD21
AE21
AJ24
AJ23
AK24
AL24
AG21
AH21
AG23
AH23

AL19
AK19
AJ20
AJ19
AK20
AL20
AK21
AL21
AK22
AL22

AJ4
AJ5

AL5
AK5

AL6
AK6

AK8
AL8

AK9
AL9

AJ9
AJ10

AL10
AK10

AL11
AK11

AG9
AF9

AG11

RV620: DO NOT INSTALL R100-R106 (INTERNAL SHUNT IN ASIC)

Place close to ASIC
<7mm

R104 100RR104 100R
TjX4P
TjX4M

R105 100RR105 100R
TjX5P
TjX5M

R106 100RR106 100R
TjXCM

R100 100RR100 100R
TjX0P
TjX0M

R101 100RR101 100R
TjX1P
TjX1M

R102 100RR102 100R
TjX2P
TjX2M

R103 100RR103 100R
TjX3P
TjX3M

R150 0RR150 0R

RV610 - INSTALL R150-R152
RV620 - DO NOT INSTALL R150-R152

R151 0RR151 0R
R152 0RR152 0R

R153

R153
150R

150R

DP_CALR

TjXCP

RV610_PSYNC

DPX-VID1
DPX-VID2

2

TjX4P (14)
TjX4M (14)

TjX5P (14)
TjX5M (14)

TjXCP (14)
TjXCM (14)

TjX0P (14)
TjX0M (14)

TjX1P (14)
TjX1M (14)

TjX2P (14)
TjX2M (14)

TjX3P (14)
TjX3M (14)

PSYNC (3,13)

VID_1 (13)
VID_2 (13)

1

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

5

4

3

2

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

4 20

of

4 20

of

4 20

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

D D

C C

B B

A A

5

4

U1E

U1E

AA26

PCIE_VSS_1

AA29

PCIE_VSS_2

AC26

PCIE_VSS_3

AD31

PCIE_VSS_4

AE29

PCIE_VSS_5

AE30

PCIE_VSS_6

AE31

PCIE_VSS_7

F28

PCIE_VSS_8

G26

PCIE_VSS_9

G29

PCIE_VSS_10

G30

PCIE_VSS_11

G31

PCIE_VSS_12

H29

PCIE_VSS_13

J25

PCIE_VSS_14

J26

PCIE_VSS_15

L26

PCIE_VSS_16

L29

PCIE_VSS_17

L30

PCIE_VSS_18

L31

PCIE_VSS_19

M26

PCIE_VSS_20

M29

PCIE_VSS_21

P26

PCIE_VSS_22

R29

PCIE_VSS_23

R30

PCIE_VSS_24

R31

PCIE_VSS_25

T26

PCIE_VSS_26

U29

PCIE_VSS_27

V26

PCIE_VSS_28

Y26

PCIE_VSS_29

Y29

PCIE_VSS_30

Y30

PCIE_VSS_31

Y31

PCIE_VSS_32

A13

VSS_1

A2

VSS_2

C18

VSS_3

A24

VSS_4

A30

VSS_5

AA1

VSS_6

AA11

VSS_7

AA14

VSS_8

AA17

VSS_9

AA20

VSS_10

AA6

VSS_11

AC2

VSS_12

AC7

VSS_13

AE3

VSS_15

AL4

VSS_16

AD14

VSS_17

AF12

VSS_18

AF14

VSS_19

AD16

VSS_20

AD18

VSS_21

AE6

VSS_22

AG2

VSS_23

AE9

VSS_24

AH25

VSS_25

AK1

VSS_26

AK31

VSS_27

AJ6

VSS_28

AL2

VSS_29

AL30

VSS_30

B1

VSS_31

C13

VSS_32

CORE GND

CORE GND

RV620 GL A11 RH

RV620 GL A11 RH

4

Part 5 of 6

Part 5 of 6

PCI-Express GND

PCI-Express GND

VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102

B25
J8
B5
D11
C17
C22
C27
D29
C3
C6
D3
D28
F29
D4
F11
F12
F14
F16
F18
F20
F21
F23
F25
F7
F9
G3
G6
H23
J3
J4
J6
K1
L12
L15
L18
L21
L6
M11
M14
M17
M20
M6
P12
P15
P18
P21
P6
AC21
R14
R17
R20
T6
U1
U12
U15
U18
U21
AE20
V14
V17
V20
P2
V6
W2
Y12
Y15
Y18
Y21
Y6
M9

3

Title

Title

3

Title

2

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Thursday, November 29, 2007

Thursday, November 29, 2007

Thursday, November 29, 2007

Sheet

Sheet

Sheet

of

5 20

of

5 20

of

5 20

1

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

4

3

2

1

D D

C C

PLACE MVREF DIVIDERS
AND CAPS CLOSE TO ASIC

+MVDD

R291

R291
100R

100R
1%

C296

R292

+MVDD

R292
100R

100R
1%

R293

R293
100R

100R
1%

R294

R294
100R

100R
1%

B B

C295

C295
100nF

100nF

C297

C297
100nF

100nF

C296
10nF

10nF

C298

C298
10nF

10nF

M_MDA[63..0](8)

U1C

MVREFD_0
MVREFS_0

R296

R296

4.7K

4.7K

U1C

Part 3 of 6

M_MDA0

E29

M_MDA1

E30

M_MDA2

E31

M_MDA3

D31

M_MDA4

C29

M_MDA5

B29

M_MDA6

B30

M_MDA7

A29

M_MDA8

E26

M_MDA9

D26

M_MDA10

E25

M_MDA11

D25

M_MDA12

G23

M_MDA13

G21

M_MDA14

E21

M_MDA15

D21

M_MDA16

C28

M_MDA17

B28

M_MDA18

B27

M_MDA19

A27

M_MDA20

C25

M_MDA21

A25

M_MDA22

C24

M_MDA23

B24

M_MDA24

C23

M_MDA25

B23

M_MDA26

A23

M_MDA27

B22

M_MDA28

C20

M_MDA29

B20

M_MDA30

A20

M_MDA31

C19

M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA63

F30
F31

TEST_MCLK
TEST_YCLK
MEMTEST DRAM_RST

R297

R297

R298

R298

4.7K

4.7K

243R

243R

DQ_0
DQ_1
DQ_2
DQ_3
DQ_4
DQ_5
DQ_6
DQ_7
DQ_8
DQ_9
DQ_10
DQ_11
DQ_12
DQ_13
DQ_14
DQ_15
DQ_16
DQ_17
DQ_18
DQ_19
DQ_20
DQ_21
DQ_22
DQ_23
DQ_24
DQ_25
DQ_26
DQ_27
DQ_28
DQ_29
DQ_30
DQ_31

C8

DQ_32

C7

DQ_33

B7

DQ_34

A7

DQ_35

A5

DQ_36

C4

DQ_37

B4

DQ_38

A3

DQ_39

G9

DQ_40

E9

DQ_41

D9

DQ_42

G7

DQ_43

G5

DQ_44

F5

DQ_45

G4

DQ_46

F4

DQ_47

B3

DQ_48

B2

DQ_49

C2

DQ_50

C1

DQ_51

E3

DQ_52

F3

DQ_53

F2

DQ_54

F1

DQ_55

G2

DQ_56

G1

DQ_57

H3

DQ_58

H2

DQ_59

K2

DQ_60

L3

DQ_61

L2

DQ_62

L1

DQ_63
MVREFD

MVREFS

L5

TEST_MCLK

L7

TEST_YCLK

J7

MEMTEST

RV620 GL A11 RH

RV620 GL A11 RH

Part 3 of 6

MEMORY

MEMORY
INTERFACE

INTERFACE

wri te stro be r ead st robe

wri te stro be r ead st robe

MA_0
MA_1
MA_2
MA_3
MA_4
MA_5
MA_6
MA_7
MA_8

MA_9
MA_10
MA_11

MA_BA0
MA_BA1

MA_A12

MA_BA2
DQMb_0

DQMb_1
DQMb_2
DQMb_3
DQMb_4
DQMb_5
DQMb_6
DQMb_7

QS_0

QS_1

QS_2

QS_3

QS_4

QS_5

QS_6

QS_7

QS_0B
QS_1B
QS_2B
QS_3B
QS_4B
QS_5B
QS_6B
QS_7B

ODT0

ODT1

CLK0b
CLK1b

RAS0b
RAS1b

CAS0b
CAS1b

CS0b_0
CS0b_1

CS1b_0
CS1b_1

CKE0

CKE1

WE0b

WE1b

DRAM_RST

CLK0
CLK1

M_MAA0

B14

M_MAA1

A14

M_MAA2

B13

M_MAA3

E14

M_MAA4

B17

M_MAA5

A17

M_MAA6

C15

M_MAA7

G16

M_MAA8

E16

M_MAA9

C14

M_MAA10

A12

M_MAA11

B12

M_MAA14

C12

M_MAA15

D14

M_MAA12

B15

M_MAA13

G14

M_DQMA#0

D30

M_DQMA#1

G25

M_DQMA#2

C26

M_DQMA#3

C21

M_DQMA#4

C5

M_DQMA#5

D6

M_DQMA#6

D2

M_DQMA#7

K3

M_QSA0

C30

M_QSA1

D23

M_QSA2

B26

M_QSA3

B21

M_QSA4

B6

M_QSA5

E7

M_QSA6

E2

M_QSA7

J2
C31

E23
A26
A21
A6
D7
E1
J1

E20
C11

A18

CLKA0 (8)

A11

CLKA1 (8)

B18

CLKA#0 (8)

B11

CLKA#1 (8)

G20

RASA#0 (8)

D12

RASA#1 (8)

D20

CASA#0 (8)

E12

CASA#1 (8)

E18

CSA#0_0 (8)

G18
G11

CSA#1_0 (8)

E11
D18

CKEA0 (8)

G12

CKEA1 (8)

D16

WEA#0 (8)

C10

WEA#1 (8)

J5

ODT (8)

+MVDD

R295

R295

2.0K

2.0K

DNI
MR295

MR295

4.7K

4.7K

M_MAA[15..0] (8)

M_DQMA#[7..0] (8)

M_QSA[7..0] (8)

Overlap

A A

5

DIVIDER RESISTORS DDR2 GDDR3

MVREF TO 1.8V

MVREF TO GND

40.2R100R

100R100R

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

4

3

2

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

6 20

of

6 20

of

6 20

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

D D

C134

C134
10uF_X6S

10uF_X6S

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 10%, 0805, 6.3V, 1.4MM MAX THICK
1uF, X6S, 10%, 0402, 6.3V
100nF, X7R, 10%, 0402
10nF , X7R, 10%, 0402

C C

B B

C135

C135
10uF_X6S

10uF_X6S

+MVDD

C136

C136
10uF_X6S

10uF_X6S

C124

C124
10nF

10nF

C137

C137
10uF_X6S

10uF_X6S

+MVDD

B120 BLM15BD121SN1B120 BLM15BD121SN1
B121 BLM15BD121SN1B121 BLM15BD121SN1

NS121 NS_VIANS121 NS_VIA

C125

C125
10nF

10nF

C138

C138
1uF_6.3V

1uF_6.3V

C126

C126
10nF

10nF

C139

C139
1uF_6.3V

1uF_6.3V

C120

C120

1uF_6.3V

1uF_6.3V

12

GND_VSSRH0

+1.8V_D2

C127

C127
10nF

10nF

C140

C140
1uF_6.3V

1uF_6.3V

B70

B70

BLM15BD121SN1

BLM15BD121SN1

C121

C121

1uF_6.3V

1uF_6.3V

C128

C128

C129

C129

10nF

10nF

100nF

100nF C904

C142

C142

C141

C141

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C68

C68
10uF_X6S

C123

C123

1uF_6.3V

1uF_6.3V

12

GND_VSSRH1

10uF_X6S

C91

C91
1uF_6.3V

1uF_6.3V

+3.3V

+3.3V

NS122 NS_VIANS122 NS_VIA

C130

C130
100nF

100nF

C143

C143
1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C122

C122

C69

C69
100nF

100nF

C131

C131
100nF

100nF

C144

C144
1uF_6.3V

1uF_6.3V

C92

C92
1uF_6.3V

1uF_6.3V

C95

C95
1uF_6.3V

1uF_6.3V

+VDDC

4

U1D

C78

C78
100nF

100nF

C132

C132
100nF

100nF

C145

C145
100nF

100nF

C93

C93
100nF

100nF

C97

C97
100nF

100nF

C133

C133
100nF

100nF

C146

C146
100nF

100nF

C79

C79
100nF

100nF

C99

C99
100nF

100nF

C96

C96
1uF_6.3V

1uF_6.3V

+VDDRH1
+VDDRH2

GND_VSSRH1
GND_VSSRH0

+VDD_CT

C59

C59
100nF

100nF

C98
100nF

100nF

AC18
AC16
AC14
AC12

AD11
AH30

A15
A22
A28

A4
A8
B8
C9
D1

H1
H11
H12
H14
H16
H18
H20
H21
B31

M1
AA9

Y9

V9

T9
J11

J20
J21

L9

AF1
AF2

AE1
AE2

M2

M3

L4

A10
A19

B10
B19

V11
U11

R11

P11

U1D

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18

VDD_CT_1
VDD_CT_2
VDD_CT_3
VDD_CT_4

VDD_CT_5
VDD_CT_6
VDD_CT_7
VDD_CT_8

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4

VDDR4_1
VDDR4_2

VDDR5_1
VDDR5_2

NC_1
NC_2
NC_3
NC_4
NC_5

VDDRH_1
VDDRH_2

VSSRH_1
VSSRH_2

BBN_1
BBN_2

BBP_1
BBP_2

RV620 GL A11 RH

RV620 GL A11 RH

I/O

Clock

I/O

Clock

PART 4 OF 6

PART 4 OF 6

I/O Internal

I/O Internal

Memory

Memory

3

AF30

PCIE_VDDR_1

AF31

PCIE_VDDR_2

AF29

PCIE_VDDR_3

AF27

PCIE_VDDR_4

AF28

PCIE_VDDR_5

AG29

PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8

PCIE_VDDC_1
PCIE_VDDC_2
PCIE_VDDC_3
PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8
PCIE_VDDC_9

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33

VDDCI_1

VDDCI_2

VDDCI_3

VDDCI_4

AG30
AG31

AA23
AC24
AC25
AE26
AE27
AE28
L23
M23
P23
T23
V23
Y23

L11
L14
L17
L20
M12
M15
M18
M21
AC20
P14
P17
P20
R12
R15
R18
R21
AD20
U14
U17
U20
V12
V15
V18
V21
Y11
Y14
Y17
Y20
AA12
AA15
AA18
AA21
P9

J12
J14
J16
J18

Memory I/O

Memory I/O

PCIE_VDDC_10
PCIE_VDDC_11

PCI-Express

PCI-Express

PCIE_VDDC_12

P

P
O

O
W

W

Core

Core

E

E
R

R

Back Bias

Back Bias

C900

C900
1uF_6.3V

1uF_6.3V

+VDDCI

C901

C901
1uF_6.3V

1uF_6.3V

C920

C920
1uF_6.3V

1uF_6.3V

C161

C161
1uF_6.3V

1uF_6.3V

C171

C171
1uF_6.3V

1uF_6.3V

C74

C74
100nF

100nF

C902

C902
1uF_6.3V

1uF_6.3V

C921

C921
1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C162

C162
1uF_6.3V

1uF_6.3V

C173

C173
1uF_6.3V

1uF_6.3VC98

C75

C75

C903

C903
1uF_6.3V

1uF_6.3V

C922

C922
1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C163

C163
1uF_6.3V

1uF_6.3V

C73

C73

C904
10uF_X6S

10uF_X6S

C174

C174
1uF_6.3V

1uF_6.3V

C923

C923
1uF_6.3V

1uF_6.3V

C167

C167
1uF_6.3V

1uF_6.3V

C77

C77
10uF_X6S

10uF_X6S

2

C905

C905
10nF

10nF

C175

C175
1uF_6.3V

1uF_6.3V

C924

C924
1uF_6.3V

1uF_6.3V

C906

C906
100nF

100nF

C925

C925
1uF_6.3V

1uF_6.3V

C168

C168
1uF_6.3V

1uF_6.3V

C176

C176
1uF_6.3V

1uF_6.3V

Overlap

B78 220R_2AB78 220R_2A
MR78 0RMR78 0R

C169

C169
1uF_6.3V

1uF_6.3V

C177

C177
1uF_6.3V

1uF_6.3V

C927

C927
1uF_6.3V

1uF_6.3V

+1.8V_D2

C178

C178
1uF_6.3V

1uF_6.3V

C928

C928
1uF_6.3V

1uF_6.3V

C181

C181
10uF_X6S

10uF_X6S

+VDDC

C926

C926
10uF_X6S

10uF_X6S

C182

C182
10uF_X6S

10uF_X6S

C179

C179
1uF_6.3V

1uF_6.3V

C183

C183
10uF_X6S

10uF_X6S

C180

C180
1uF_6.3V

1uF_6.3V

+1.1V

+VDDC

1

C184

C184
10uF_X6S

10uF_X6S

C192

C192

C193

C193

1uF_6.3V

1uF_6.3V

100nF

100nF

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

5

4

3

2

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

7 20

of

7 20

of

7 20

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

8

7

6

5

4

3

2

1

CHANNEL A: RANK 0 128MB DDR2

M_DQMA#[7..0](6)

D D

M_MDA[63..0](6)

M_MAA[15..0](6)

M_MAA[15..0](6)

C C

VREF_A0

+MVDD +MVDD +MVDD

R201

R201

4.99K

4.99K

R202

B B

R202

4.99K

4.99K

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

M_MAA14

L2

M_MAA15

L3

M_MAA12

R2

M_MAA11

P7

M_MAA10

M2

M_MAA9

P3

M_MAA8

P8

M_MAA7

P2

M_MAA6

N7

M_MAA5

N3

M_MAA4

N8

M_MAA3

N2

M_MAA2

M7

M_MAA1

M3

M_MAA0

M8

M_MAA13

TP200TP200

K8

CLKA#0(6)

J8

CLKA0(6)

K2

CKEA0(6)

L8

CSA#0_0(6)

WEA#0(6)

K7

RASA#0(6)

L7

CASA#0(6)

M_DQMA#2

F3

M_DQMA#3 M_DQMA#7

B3

M_QSA2

M_QSA3

K9

F7
E8

B7
A8

J2

A2
E2

L1
R3
R7
R8

ODT(6) ODT(6) ODT(6) ODT(6)

R211 10RR211 10R

R212 10RR212 10R

VREF_U20

C413

C413
100nF

100nF

U201

U201

BA0
BA1

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CK
CK

CKE

CS
WEK3VDDQ10
RAS
CAS
LDM

UDM

ODT

LDQS
LDQS

UDQS
UDQS

VREF

VSSQ10
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

HY5PS561621F-25

HY5PS561621F-25

M_QSA[7..0](6)

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSS1
VSS2
VSS3
VSS4
VSS5

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

M_MDA27

B9

M_MDA30

B1

M_MDA24

D9

M_MDA29

D1

M_MDA31

D3

M_MDA26

D7

M_MDA28

C2

M_MDA25

C8

M_MDA18

F9

M_MDA21

F1

M_MDA17

H9

M_MDA22

H1

M_MDA23

H3

M_MDA16

H7

M_MDA20

G2

M_MDA19

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

Possible alternate 5150005600G

A1
E1
J9
M9
R1

VDDL_U20

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

C411

C411
100nF

100nF

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7

C412

C412
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

VREF_A0

R213 10RR213 10R

R214 10RR214 10R

R203

R203

4.99K

4.99K
VREF_U21

R204

R204

4.99K

4.99K

M_MAA14
M_MAA15

M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

CLKA#0(6)
CLKA0(6)

CKEA0(6)

CSA#0_0(6)

WEA#0(6)
RASA#0(6)
CASA#0(6)

M_DQMA#0
M_DQMA#1

M_QSA0

M_QSA1

C438

C438
100nF

100nF

U202

U202

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS
WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

U204

U203

U203

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS
WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

R217 10RR217 10R

R218 10RR218 10R

R207

R207

4.99K

4.99K

R208

R208

4.99K

4.99K

VREF_U23

M_MAA14
M_MAA15

M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

CLKA#1(6)
CLKA1(6)

CKEA1(6)

CSA#1_0(6)

WEA#1(6)
RASA#1(6)
CASA#1(6)

M_DQMA#4
M_DQMA#5

M_QSA4

M_QSA5

C448

C448
100nF

100nF

M_MDA58

B9

M_MDA60

B1

M_MDA57

D9

M_MDA62

D1

M_MDA63

D3

M_MDA56

D7

M_MDA61

C2

DQ9

M_MDA59M_MDA15

C8

DQ8

M_MDA51

F9

DQ7

M_MDA53

F1

DQ6

M_MDA48

H9

DQ5

M_MDA52

H1

DQ4

M_MDA55

H3

DQ3

M_MDA49

H7

DQ2

M_MDA54

G2

DQ1

M_MDA50

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

VDDL_U22

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

C461

C461
100nF

100nF

C462

C462
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

VREF_A1

+MVDD

R215 10RR215 10R

R216 10RR216 10R

R205

R205

4.99K

4.99K

R206

R206

4.99K

4.99K

VREF_U22

M_MAA14
M_MAA15

M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

CLKA#1(6)
CLKA1(6)

CKEA1(6)

CSA#1_0(6)

WEA#1(6)
RASA#1(6)
CASA#1(6)

M_DQMA#6

M_QSA6

M_QSA7

C463

C463
100nF

100nF

M_MDA14

B9

M_MDA9

B1

M_MDA13

D9

M_MDA8

D1

M_MDA10

D3

M_MDA12

D7

M_MDA11

C2

DQ9

C8

DQ8

M_MDA6

F9

DQ7

M_MDA3

F1

DQ6

M_MDA4

H9

DQ5

M_MDA1

H1

DQ4

M_MDA2

H3

DQ3

M_MDA7

H7

DQ2

M_MDA0

G2

DQ1

M_MDA5

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

Possible alternate 5150005600G

A1
E1
J9
M9
R1

VDDL_U21

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

C436

C436
100nF

100nF

C437

C437
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

VREF_A1

U204

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS
WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

M_MDA46

B9

M_MDA40

B1

M_MDA45

D9

M_MDA43

D1

M_MDA41

D3

M_MDA47

D7

M_MDA42

C2

DQ9

M_MDA44

C8

DQ8

M_MDA36

F9

DQ7

M_MDA34

F1

DQ6

M_MDA39

H9

DQ5

M_MDA32

H1

DQ4

M_MDA33

H3

DQ3

M_MDA38

H7

DQ2

M_MDA35

G2

DQ1

M_MDA37

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

VDDL_U23

C446

C446
100nF

100nF

C447

C447
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

+MVDD

C402

C402

C401

C401
1uF_6.3V

1uF_6.3V

+MVDD

C406

C406
1uF_6.3V

1uF_6.3V

402

A A

8

C403

C403

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

402402402

C407

C407

C408

C408

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

402 402 402

7

C409

C409
1uF_6.3V

1uF_6.3V

C410

C410
1uF_6.3V

1uF_6.3V

402

CLKA0(6)

CLKA#0(6)

CLKA1(6)

CLKA#1(6)

R221

R221
56R

56R

402

R222

R222
56R

56R

402 402

R223

R223
56R

56R

402

R224

R224
56R

56R

402 402

6

+MVDD

C428

C426

C426
1uF_6.3V

1uF_6.3V

402 402402

+MVDD

C431

C431
1uF_6.3V

1uF_6.3V

402 402

C499

C499
10nF

10nF

C500

C500
10nF

10nF

C428

C427

C427

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C432

C432
1uF_6.3V

1uF_6.3V

402 402 402 402

C434

C434

C433

C433

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

+MVDD +MVDD

R209

R209

4.99K

4.99K

VREF_A0 VREF_A1

R210

R210

4.99K

4.99K

5

C435

C435
1uF_6.3V

1uF_6.3V

R219

R219

4.99K

4.99K

R220

R220

4.99K

4.99K

+MVDD

C453

C451

C451
1uF_6.3V

1uF_6.3V

402 402402

+MVDD

C456

C456
1uF_6.3V

1uF_6.3V

4

C453

C452

C452

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C458

C458

C457

C457

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

402 402 402

C459

C459
1uF_6.3V

1uF_6.3V

C460

C460
1uF_6.3V

1uF_6.3V

402

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

3

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

+MVDD

C477

C477

C476

C476
1uF_6.3V

1uF_6.3V

402 402402

+MVDD

C481

C481
1uF_6.3V

1uF_6.3V

402

2

C478

C478

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C482

C482
1uF_6.3V

1uF_6.3V

402 402 402 402

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Sheet

Sheet

Sheet

C484

C484

C483

C483

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

of

8 20

of

8 20

of

8 20

Doc No.

Doc No.

Doc No.

C485

C485
1uF_6.3V

1uF_6.3V

105-B350xx-00

105-B350xx-00

105-B350xx-00

1

RevDate:

RevDate:

RevDate:

00

00

00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

8

7

6

5

4

3

2

1

Thermal

Thermal

Pad

Pad

9

6
7
8

Place Rs and Cs across QL

RC snubber values shown
are for reference only,
tuning is required

MVDDC_FB

+MVDDC_S

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

NL701

NL701

1 2

PCMC063T-2R2MN

PCMC063T-2R2MN

ML701ML701

1 2

L701 2.2uH_13AL701 2.2uH_13A

1 2

R719

R719
33MOHM

33MOHM

1210
1%

C708

C708
10nF_25V

10nF_25V

402
X7R
25V

C716

C716

C715

C715

10UF

10UF

10UF

10UF

12061206

on PCB

Rs

Cs

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

+PW_MVDDC_LGDR

4 5
3
2
1

MULTI FOOTPRINT

R1

RFB1
R711

R711

4.99K

4.99K

402
1%

R4

Place R1 and
R4 close to

RFB2

PWM and

R710

R710

routed with

3.24K

3.24K

402

separate

1%

20mil trace to
the ASIC

MQ702

MQ702

Thermal

Thermal

Pad

Pad

FDS7096N3

FDS7096N3

C717

C717

4.7uF_10V

4.7uF_10V

805 805

Use16V 0805 MLCCMirrored
Mirrored on PCB

C713

C713

3.9nF

3.9nF

402

16V

10%

X7R

R713

R713

3.65K

3.65K

402
5%

9

6
7
8

C719

C719

4.7uF_10V

4.7uF_10V

C718

C718

150nF_16V

150nF_16V

603

***

C725

C725
470uF_10V

470uF_10V

***

Over Lap

MULTI FOOTPRINT
For SO-8

Q701

Q701

QH

+PW_MVDDC_HGD +PW_MVDDC_HGDR

D D

C703

C703

0.22uF

0.22uF

MVDD_EN (11)

R708 20KR708 20K

+PW_MVDDC_LGD

402

+PW_MVDDC_M

R722 0RR722 0R

+MVDDC_B

U703

U703

1

BOOT

2

UGATE

3

+PW_MVDDC_LGD

R715

R715

42.2K

42.2K

List of supported foodprint
The following ICs are not necessarily evaluated by

ATI, please refer to BOM for evaluation status

ANPEC APW7120/APW7065 (12V)

C C

B B

CAT CAT7583 (12V)
INTERSIL ISL6545
NEXSEM NX2114/2307
RICHTEK RT9214/RT8101
OnSemi ON1582
uPI UP6101 (No Ext_Vref in)
uPI UP6103 (with Ext_Vref in, can use voltage console UP6261 to change Vout)

GND
LGATE4VCC

APW7065

APW7065

PHASE

COMP

+PW_MVDDC_M

8

MVDDC_COMP+PW_MVDDC_HGD

7

MVDDC_FB

6

FB

5

+MVDD_VCC

+PW_MVDDC_LGDR

603

R721 0RR721 0R

QL

402

Q702

Q702

Thermal

Thermal

Pad

Pad

4 5
3
2
1

BSC119N03SG

BSC119N03SG

MVDDC_FB(11)

+PW_MVDDC_HGDR

MQ701

MQ701

Thermal

Thermal

4 5
3
2
1

FDS7096N3

FDS7096N3

+PW_MVDDC_M

Pad

Pad

9

6
7
8

4 5
3
2
1

BSC119N03SG

BSC119N03SG

+MVDDC_S

9

6
7
8

B701 60RB701 60R
R701 0RR701 0R

Over Lap

***

MC725

MC725
470uF_6.3V

470uF_6.3V

***

ALTPOLY

+VDDC_S

KC725

KC725
330uF_2.5V

330uF_2.5V
TAN LP

25mOHM

+MVDDC_S

C720

C720

MC720

MC720

10UF

10UF

4.7uF_10V

4.7uF_10V

1206

805 1206

Overlap

Mirrored on PCB

+MVDD

NC725

NC725
330uF_2.5V

330uF_2.5V

TAN LP
25mOHM

Over Lap

*** ***

C723

C723
100uF_6.3V

100uF_6.3V

1210 1210

*** ***

C724

C724
100uF_6.3V

100uF_6.3V

SMPS02- Regulator for MVDD

Vout = 1.8V ~ 2.85V

Part RFB2RFB1

Vout

0.8V Ref

2.03V
(1.98V~2.08V)

1.8V
(1.78V~1.86V)

4.99K
p/n 3160499100G

4.99K
p/n 3160499100G

C721

C721
10UF

10UF

MC721

MC721

4.7uF_10V

4.7uF_10V

805

Overlap

3.24K
p/n 3160324100G

3.92K
p/n 3160392100G

COMPENSATION CIRCUIT

MVDDC_COMP

402

C712

C712

C711

C711
15nF

15nF

10V

402

10%

X7R

R712

A A

R712

2.94K

2.94K

402
1%

8

390pF

390pF

603
NPO

R714 0RR714 0R

R7090RR709
0R

C714

C714
100nF

100nF

402

10V

50V

X5R

10%

5%

MVDDC_FB

FILTERED SMPS VCC BOOT CIRCUIT

+12V_BUS

R707

+MVDD_VCC

7

R707

2.2R

2.2R

C707

C707
100nF

100nF

603
X7R
5%

3

1

2

C705

C705
100nF

100nF

603X7R

16V

5%

6

D701

D701
BAT54A

BAT54A

+12V_BUS

+MVDDC_B

C706

C706
150nF_16V

150nF_16V

+PW_MVDDC_M

5

Layout guideline for Nexsem NX2114/2307

1-Position the controller (U703) such that LGate(pin4) is the closet to gate
of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate
of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as
short and as wide as possible to reduce the trace inductance.
2-Place the bypass capacitors for Vcc as well as Boost caps as close to the
controller as possible. They are as follows;
Vcc bypass cap is C703, and Boost cap is C705.
3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place
the rest of the compensation network close to the pins 7 and 6. These are R710,
R711, R713, C713 and R712, C711 and C712.

4

3

SMPS02 Specifications

Vin 12V(power stage) +/-8% PCIe ATX12V ver. 2.2 +/-5%

Vout 2V

Vout ripple (DC) 50mVpp

Iout 6Aavg, 8Adc_max

Step load 3Amax

Protections

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

Nominal Value Adjustable range / Notes

+/-10% or 200mVpp @ 3A step loadVout ripple (AC)

2

Tolerance

;

;

+2%/-2%

;

~300kHzSwitching Freq. TBD

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

9 20

of

9 20

of

9 20

1.8V ~ 2.85V

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

8

D D

7

+PW_VDDC_HGD +PW_VDDC_HGDR

6

R621 0RR621 0R

5

Thermal

Thermal

+VDDC_S

Pad

Pad

9

6
7
8

C615

C615

C616

C616

10UF

10UF

10UF

10UF

12061206

on PCB

USE CAP CER 10UF 20% 16V
X7R (1206)

L601

L601
R68UH

R68UH

Q601

Q601

QH

402

4 5
3
2
1

BSC119N03SG

BSC119N03SG

C617

C617

4.7uF_10V

4.7uF_10V

805

4

4.7uF_10V

4.7uF_10V

Use16V 0805 MLCCMirrored
Mirrored on PCB

3

ML602

Find 100nH
SM Alt. IND

C627

C627
68uF_16V

68uF_16V

Overlap

ML602

0.47uH

0.47uH

Overlap

L602

L602

IND_0.47uH_7A

IND_0.47uH_7A

6 3

8 1

7 2

5 4

RP60 1A 0 RRP 601A 0R

RP6 01B 0RRP6 01B 0R

RP6 01C 0RRP6 01C 0R

RP60 1D 0RRP601 D 0 R

C618

C619

C619

805

C618
150nF_16V

150nF_16V

603

+12V_BUS

B601

B601
60R

60R

MC627

MC627
180uF_16V

180uF_16V
SM 8mm DiaSM 6.3mm Dia

2

C630

C630

100uF_16V

100uF_16V

C620

C620
10UF

10UF

1206

+VDDC_S

MC620

MC620

4.7uF_10V

4.7uF_10V

805 1206

Overlap

Mirrored on PCB

+VDDC_S

1

C621

C621

MC621

MC621

10UF

10UF

4.7uF_10V

4.7uF_10V

805

Overlap

MULTI FOOTPRINT

+PW_VDDC_M

Q602

Q602

QL

Thermal

Thermal

Pad

Pad

+PW_VDDC_LGD

C C

B B

+VDDC_B

U603

U603

1

+PW_VDDC_HGD

+PW_VDDC_LGD

R615

R615

42.2K

42.2K

List of supported foodprint
The following ICs are not necessarily evaluated by

ATI, please refer to BOM for evaluation status

ANPEC APW7120/APW7065 (12V)
CAT CAT7583 (12V)
INTERSIL ISL6545
NEXSEM NX2114/2307
RICHTEK RT9214/RT8101
OnSemi ON1582
uPI UP6101 (No Ext_Vref in)

Layout guideline for Nexsem NX2114/2307

1-Position the controller (U703) such that LGate(pin4) is the closet to gate
of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate
of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as
short and as wide as possible to reduce the trace inductance.
2-Place the bypass capacitors for Vcc as well as Boost caps as close to the
controller as possible. They are as follows;
Vcc bypass cap is C703, and Boost cap is C705.
3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place
the rest of the compensation network close to the pins 7 and 6. These are R710,
R711, R713, C713 and R712, C711 and C712.

BOOT

2

UGATE

3

GND
LGATE4VCC

APW7065

APW7065

PHASE

COMP

+PW_VDDC_M

8

VDDC_COMP

7

VDDC_FB

6

FB

5

+VDD_VCC

C603

C603

0.22uF

0.22uF

R608 20KR608 20K

VDD_EN (11,17)

402

COMPENSATION CIRCUIT FILTERED SMPS VCC

VDDC_COMP

402

C611

C611

C612

15nF

15nF

402

R612

R612

2.94K

2.94K

402
1%

C612
390pF

390pF

C614

C614

402

10V

50V

10V

603

100nF

100nF

X5R

5%

R614 0RR614 0R

10%

VDDC_FB

10%

NPOX7R

R6090RR609
0R

8

+VDD_VCC

+12V_BUS

R607

R607

2.2R

2.2R

603
X7R

C607

C607

5%

100nF

100nF

7

A A

R622 0RR622 0R

+PW_VDDC_LGDR

603

+PW_VDDC_HGDR

+PW_VDDC_M

MQ601

MQ601

Thermal

Thermal

Pad

Pad

4 5
3
2
1

FDS7096N3

FDS7096N3

BOOT CIRCUIT

3

1

C605

C605
100nF

100nF

603X7R

16V

5%

6

2

+VDDC_S

9

6
7
8

4 5
3
2
1

BSC119N03SG

BSC119N03SG

VDDC_FB(11)

+12V_BUS

C606

C606
150nF_16V

150nF_16V

D601

D601
BAT54A

BAT54A

+VDDC_B

9

6
7
8

+PW_VDDC_M

NL601 2.2uH_13ANL601 2.2uH_13A

1 2

R619

R619
33MOHM

33MOHM

1210
1%

C608

C608
10nF_25V

10nF_25V

402
X7R
25V

Place Rs and Cs across QL

RC snubber values shown
are for reference only,
tuning is required

VDDC_FB

+PW_VDDC_LGDR

MQ602

MQ602

4 5
3
2
1

FDS7096N3

FDS7096N3

5

Thermal

Thermal

Pad

Pad

Rs

Cs

R1

RFB1
R611

R611

4.99K

4.99K

402
1%

R4

RFB2
R610

R610

3.24K

3.24K

402
1%

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

9

6
7
8

C613

C613

3.9nF

3.9nF

402

16V

10%

X7R

R613

R613

3.65K

3.65K

402
5%

Place R1 and
R4 close to
PWM and
routed with
separate
20mil trace to
the ASIC

MULTI FOOTPRINT

4

**

MC623

MC623
22uF_16V

22uF_16V

**

ALT

Over Lap

***

C625

C625
820uF_2.5V

820uF_2.5V

*** ***

8 x 8 mm, TH

C623

C623
10uF

10uF

Over Lap

3

+VDDC

C624

C624
10uF

10uF

CAP CER 10UF 10%

6.3V X5R (0805)1.4MM
MAX THICK

+VDDC

***

KC625

KC625
470uF_10V

470uF_10V

10 x 12.5 mm, TH

SMPS02 Specifications

Vin 12V(power stage) +/-8% PCIe ATX12V ver. 2.2 +/-5%

Vout 2V

Vout ripple (DC) 50mVpp

Iout 6Aavg, 8Adc_max

Step load 3Amax

Protections

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

SMPS02- Regulator for VDDC

Vout = 0.9V ~ 1.1V

Vout

Part RFB2RFB1

1.1V

0.8V Ref
(1.98V~2.08V)

1.1V
(1.10V~1.14V)

Nominal Value Adjustable range / Notes

+/-10% or 200mVpp @ 3A step loadVout ripple (AC)

~300kHzSwitching Freq. TBD

Sheet

Sheet

Sheet

2

MC622

MC622

C622

C622

4.7uF_10V

4.7uF_10V

10UF

10UF

1206

805 1206

Overlap

Mirrored on PCB

200R
p/n 3160200000G

10K

;

;

;

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

p/n 3160100200G

Tolerance

+2%/-2%

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

of

10 20

of

10 20

of

10 20

C628

C628
10UF

10UF

511R
p/n 3160511000G

24.9K
p/n 3160249200G

1.8V ~ 2.85V

Doc No.

Doc No.

Doc No.

105-B350xx-00

105-B350xx-00

105-B350xx-00

1

MC628

MC628

4.7uF_10V

4.7uF_10V

805

Overlap

RevDate:

RevDate:

RevDate:

00

00

00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

8

7

6

5

4

3

2

1

Stitching Capacitors

THESE ARE STITCHING CAPACITORS. THEIR PLACEMENT IS LAYOUT DEPENDANT. Place C490-492 near layer transitions (top/bottom).

+3.3V+3.3V_BUS +VDDC+3.3V_BUS

C300

C300

C301

C301

C302

C302

C303

D D

100nF

100nF

100nF

100nF

100nF

100nF

C303
100nF

100nF

+MVDD

THIS IS LAYOUT DEPENDENT.

C490

C490
100nF

100nF

C491

C491
100nF

100nF

C492

C492
100nF

100nF

DDC3DATA

DDC3DATA(3,17)

DDC3CLK

DDC3CLK(3,17)

+3.3V_BUS

Power up/down Sequencing

Power Sequence Circuit to ensure SMPS_EN is released after

+12V_BUS+3.3V_BUS +12V_BUS

R857

R857

Node 1

4.7K

Node 3

Node 2

4.7K
PSEQ_N1

5%

Q850

Q850
MMBT3904

MMBT3904

2 3

PSEQ_MID

Q851

Q851
MMBT3904

MMBT3904

2 3

2 3

R843

R843

5.1K

5.1K

5%

Q840

Q840
MMBT3904

MMBT3904

R8590RR859
0R

PSEQ_VDDCUP2

+3.3V

+1.8V_D2

R899

R899

5.1K

5.1K

1

1

+12V_BUS

1

LDO2_POK(3,12)

7

C846

C846
100nF

100nF

1

R846 5.1KR846 5.1K

R847 10KR847 10K

5%

C844

C844

100nF_6.3V

100nF_6.3V

Q852

Q852
MMBT3904

MMBT3904

2 3

R844 5.1KR844 5.1K

PSEQ_EN23

5%

PSEQ_ENM

5%

OSC_EN (3,12)

Q843

Q843

1

MMBT3904

MMBT3904

2 3

C C

B B

A A

R852

R852

R850

R850

1.62K

1.62K

475R

475R

1%

R851

R851
200R

200R

1%

+VDDC

8

1%

R853

R853
200R

200R

1%

R8411KR841
1K

PSEQ_VDDCUP

C841

C841
1uF_6.3V

1uF_6.3V

PSEQ_N3

PSEQ_N2

+12V_BUS and +3.3V_BUS are both in regulation.

VDD_EN (10,17)

Node 1

When +3.3V_BUS gets close to regulation, one of the two

Node 2

conditions of releasing SMPS_EN is active
Target ~ 900mV when +3.3 at min regulation (worse case)

Typical trigger when +3.3V ramps above 2.2V (650mV)

Node 3When +12V gets close to regulation, one of the two

conditions of releasing SMPS_EN is active
Target ~ 1.25V when +12 at min regulation (worse case)

Typical trigger when +12V ramps above 10V (1.1V)
When +12V_BUS ramps above min Vbe, SMPS_EN will be held low

+3.3V_BUS

5.1K

5.1K
R845

R845

Q841

Q841

1

MMBT3904

MMBT3904

2 3

Q842

Q842

1

MMBT3904

MMBT3904

2 3

+12V_BUS

R848

R848
100K

100K

1

2 3

6

R849

R849
10K

10K

Q844

Q844

MMBT3904

MMBT3904

LDO2-3_EN (12)

MVDD_EN (9)

C843

C843

100NF

100NF

402
X5R
16V

+3.3V_BUS

C842

C842
10uF_X6S

10uF_X6S

3 2

Q845

Q845
SI2304DS

SI2304DS

PWRCNTL_1PWRCNTL_0

0

1

PWRCNTL_0(3,13)

PWRCNTL_1(3)

+3.3V

1

5

R840

R840
100K

100K

LVT_EN (4)

4

Rf1=

GPIO_15GPIO_20

Rf2=

0

10

01

1

+3.3V

R1240

R1240
10K

10K

+3.3V

R1241

R1241
10K

10K

VDDC Voltage Settings Using GPIOs

I2C control of VDDC/MVDD

R1200 200RR1200 200R
R1201 200RR1201 200R

R1207 0RR1207 0R
R1208 0RR1208 0R

R1202

R1202

1.8R

1.8R
C1201

C1201
10uF

10uF

C1200

C1200
100nF

100nF

Power Play

Output Voltage (V)

Rf1=
Rf2=

0 11

PWRCNTL_0_S

PWRCNTL_1_SPWRCNTL_1_S

3

Should be
placed near
SPMS, NOT

DAC_FS1
DAC_FS0

near U1200.

R1205 0RR1205 0R
R1206 0RR1206 0R

R1203 10KR1203 10K
R1204 10KR1204 10K

U1200

U1200

1

SDA

2

SCL
A111NC#12

9

A0

13

VCC

15

EPAD

3

GND

DS4402

DS4402

CUR_ADJ_0

8

OUT0

CUR_ADJ_1

10

OUT1

12
14

NC#14

4

NC#4

5

NC#5

6

FS1

7

FS0

Rf1=
Rf2=

Power-up Default

PWR_CNTL_OUT

Rf1 Rf2

R1226

R1226

1.5K

1.5K
1% 1%

32

2N7002E

2N7002E
Q1200

Q1200

1

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

R1221 0RR1221 0R

R1225

R1225

1.5K

1.5K

32

2N7002E

2N7002E
Q1201

Q1201

1

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

2

VDDC_FB (10)

MVDDC_FB (9)

VDDC_FB (10)

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

11 20

of

11 20

of

11 20

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

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6

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2

1

LDO #2: Vout = +1.8V +/- 2%Vin = 2.1V to 3.6V MAX Iout = 0.8A (TBV) RMS MAX
PCB: 50 to 70mm sq. copper area for cooling

+12V_BUS+3.3V_BUS

R861

R861

MR8610RMR861

D861

D861

5.1V

5.1V

U861

U861

1

POK

2

EN

3

VIN
CNTL4REFIN

uP7706U8

uP7706U8

placeholder values

SS432GN

SS432GN

2 1

GND#8

FB

VOUT

GND#9

REG861

REG861

8
7
6
5
9

3 2

R866 0RR866 0R

DNI

D D

+3.3V_BUS

Use 0.5R

R868

1206

0.50R

0.50R
TP861TP861

LDO2_POK(3,11)

C C

LDO2-3_EN(11)

LDO2_VCNTL

C866

C866

10uF_X6S

10uF_X6S

LDO2_POK
LDO2-3_EN

C868

C868
1uF_6.3V

1uF_6.3V

1

R869

R869

6.8K

6.8K

R867

R867

6.8K

6.8K

+1.8V_LDO2

DNI

LDO2_FB

C867

C867
10uF

10uF

0R

OVERLAP

R865

R865

12.7K_0.1%

12.7K_0.1%

R864

R864
10K_0.1%

10K_0.1%

0.1%

R5
R4

10K

10K

R862

R862

6.8K

6.8K

C865

C865
33pF_50V

33pF_50V

C3

VOUT = Vref x (1 + R5/R4)

LDO2_VCNTL

Overlap

+MVDD

B880 220R_2AB880 220R_2A

0805

MR880 0RMR880 0R

0805

DNI

C862

C862
10uF_X6S

10uF_X6S

C861

C861
10uF_X6S

10uF_X6S

C864

C864
100nF

100nF

R880 0RR880 0R

+1.8V_D2

+12V_BUS

Regulators for +5V, +5V_VESA

MR8120RMR812

R812

1206

1/4W

5%

C810

C810
100nF

100nF

0603
16V

R812
47R

47R

R811

R811

MR811

1206

1/4W

+VESA_IN

MR811
27R

27R

47R

47R

0805

1/8W

0R

0805

1/8W

5%

Vout(V) = Vref (1+R2/R1)

MU810

MU810
MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

1

U810

U810

1

VIN

VOUT#2

5

NC

VOUT#3

8

NC#8

VOUT#6

ADJ4VOUT

LM317LCDR

LM317LCDR

VESA_FB

+5V_VESA

3

GND

2
3

R813

R813

6

499R

499RR868

7

0402

R1

C811

C811

1uF_6.3V

1uF_6.3V

R814

R814

1.5K

1.5K

0402

R2

R868 (0.5R 1/2W or 0R 1206), R864, R865 & C865: To Be Verified

LDO #3: Vout = +1.1V +/- 2.5%
PCB: 50 to 70mm sq. copper area for cooling

1210

B B

+MVDD

1/2W

R858

R858

0.1R

0.1R

Vin = +1.4V to 2.087VMAX Iout = 1.4A (TBV) RMS MAX

TP850TP850

LDO3_VIN

C856

C856

10uF_X6S

10uF_X6S

TP851TP851

LDO2-3_EN

LDO2_VCNTL

C858

C858
1uF_6.3V

1uF_6.3V

U851

U851

1

POK

2

EN

3

VIN
CNTL4REFIN

uP7706U8

uP7706U8

GND#8

VOUT

GND#9

R855

R855

3.92K

8
7

FB

6

R856 0RR856 0R

5

DNI

9

LDO3_FB

3.92K

R854

R854
10K

10K

VOUT = Vref x (1 + R5/R4)

R5

R4

+1.1V

C855

C855
33pF_50V

33pF_50V

C3

C852

C852
10uF_X6S

10uF_X6S

DNI

C851

C851
10uF_X6S

10uF_X6S

C854

C854
100nF

100nF

Overlap

MR890 0RMR890 0R
B890 220R_2AB890 220R_2A

+VDDC+1.1V

Shared Power Rails

+VDD1DI +VDD2DI +DPLL_PVDD +TPVDD

B885

B883

B883
BLM15BD121SN1

BLM15BD121SN1

7

B884

B884
BLM15BD121SN1

BLM15BD121SN1

B885
BLM15BD121SN1

BLM15BD121SN1

B886

B886
BLM15BD121SN1

BLM15BD121SN1

6

B887

B887
BLM15BD121SN1

BLM15BD121SN1

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

5

4

3

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

12 20

of

12 20

of

12 20

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

B882

B882
BLM15BD121SN1

BLM15BD121SN1

+A2VDDQ

A A

+1.8V_D2

8

+AVDD

PDF created with pdfFactory Pro trial version www.pdffactory.com

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5

D D

C C

B B

A A

5

4

PSYNC
DVALID

RV610: (DEFAULT) MR70, R73, MR74, MR75 INSTALLED

PSYNC (3,4)
DVALID (3)

RV620: MR70, MR73, MR74, MR75 MUST BE INSTALLED

GPIO_[13..0](3)

4

3

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13

3

2

PIN BASED STRAPS

GPIO_0

GPIO_1

GPIO_1

GPIO_2

GPIO_2
GPIO_3

GPIO_3

GPIO_4

GPIO_5

GPIO_5
GPIO_6

GPIO_6

GPIO_7GPIO_7

GPIO_7GPIO_7

GPIO_8

GPIO_9

GPIO_13

GPIO_13
GPIO_12

GPIO_12
GPIO_11GPIO_11

GPIO_11GPIO_11

GENERICC
GENERICB

A_VSYNC_DAC1

A_HSYNC_DAC1

PSYNC

PSYNC

GPIO21_BB_EN

A_VSYNC_DAC2
A_HSYNC_DAC2

DVALID

GPIO_22

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

MR50 10KMR50 10K

MR51 10KMR51 10K

MR52 10KMR52 10K
MR53 10KMR53 10K

MR54 10KMR54 10K

MR55 10KMR55 10K
MR56 10KMR56 10K

MR57 10KMR57 10K

MR58 10KMR58 10K

MR59 10KMR59 10K
MR63 10KMR63 10K
MR62 10KMR62 10K
MR61 10KMR61 10K

MR65 10KMR65 10K
MR64 10KMR64 10K

MR66 10KMR66 10K

MR67 10KMR67 10K

MR68 10KMR68 10K

MR69 10KMR69 10K

MR70 10KMR70 10K

MR71 10KMR71 10K

MR72 10KMR72 10K

MR73 10KMR73 10K

MR74 10KMR74 10K

MR75 10KMR75 10K

MR76 10KMR76 10K

MR77 10KMR77 10K

MR80 10KMR80 10K
MR79 10KMR79 10K

MR60 10KMR60 10K

MR87 10KMR87 10K

MR46 10KMR46 10K

MR88 10KMR88 10K

+3.3V

DNI

DNI

DNI

DNI

DNI

NTSC

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

R50 10KR50 10K

R51 10KR51 10K

R52 10KR52 10K
R53 10KR53 10K

R54 10KR54 10K

R55 10KR55 10K
R56 10KR56 10K

R57 10KR57 10K

R58 10KR58 10K

R59 10KR59 10K
R63 10KR63 10K
R62 10KR62 10K
R61 10KR61 10K

R65 10KR65 10K
R64 10KR64 10K

R66 10KR66 10K

R67 10KR67 10K

R68 10KR68 10K

R69 10KR69 10K

R70 10KR70 10K

R71 10KR71 10K

R72 10KR72 10K

R73 10KR73 10K

R74 10KR74 10K

R75 10KR75 10K

R76 10KR76 10K

R77 10KR77 10K

R80 10KR80 10K
R79 10KR79 10K

R60 10KR60 10K

R87 10KR87 10K

R88 10KR88 10K

Pull-Down Resistors are for BU until built-in pull-downs are verified.

Overlap pads to save space
and to prevent assembly of
both resistors.

Layout

High logic voltageGround

Signal

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

2

1

GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)

0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)

0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)

GPIO(3:2) - ATI Internal Use Only - Reserved (Default: 00)

GPIO(4) - DEBUG_ACCESS
ATI Internal Use Only - Reserved (Default: 0)

GPIO(5) - ATI Internal Use Only - Reserved (Default: 0)

GPIO(6) - ATI Internal Use Only - Reserved (Default: 0)

GPIO(7) - TV OUT STANDARD (Jumper position overwrite resistor settings)

0 - PAL TVO (Jumper is closed)
1 - NTSC TVO (Jumper is open)

RV610: INSTALL MR58
RV620: INSTALL R58

GENERICC (3)
GENERICB (3)

A_VSYNC_DAC1 (3,14)

A_HSYNC_DAC1 (3,14)

GPIO21_BB_EN (3)

DPVSS-VID0 (4)

VID_1 (4)

VID_2 (4)

DPAVSS-VID3 (4)

DPAVSS-VID4 (4)

DPAVSS-VID5 (4)

VID_6 (3)

VID_7 (3)

A_VSYNC_DAC2 (3,15)
A_HSYNC_DAC2 (3,15)

PWRCNTL_0 (3,11)

GPIO_22 (3)

GPIO_18 (3)

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

GPIO(8) - ATI Internal Use Only - Reserved (Default: 0)

GPIO(9,13:11) - CONFIG[3..0] IF
BIOS_ROM_EN=1 [default] (GPIO_22)

M25P10A (1 Mbit) 0101
M25P20 (2 Mbit) 0101
Chingis (formerly PMC) ­ Pm25LV512 (512 kbit) 0100
Pm25LV010 (1 Mbit) 0101

GENERICC, GENERICB - ATI Internal Use Only - Reserved (Default: 0)

VSYNC - VIP_DEVICE_STRAP_EN

0: Slave VIP host port devices present (use if Theater is populated)
1: No slave VIP host port devices reporting presence during reset (use for
configurations without video-in)

HSYNC - ATI Internal Use Only - Reserved (Default 0)

PSYNC - VGA DISABLE : 1 for disable (set to 0 for normal operation)

GPIO_21 - ATI Internal Use Only - Reserved (Default: 0)

VID_0 - ATI Internal Use Only - Reserved (Default: 0)

VID_1 - MSI_DIS (Default: 0)

VID_2 - ATI Internal Use Only - Reserved (Default: 0)

VID_3 - ATI Internal Use Only - Reserved (Default: 0)

VID_4 - ATI Internal Use Only - Reserved (Default: 0)

VID_5 - 64BAR_EN_A (Default: 0)
Enable 64-bit BARS

VID_6:7 - ATI Internal Use Only - Reserved (Default: 00)

VSYNC - DDR2 VENDOR SELECT
(see GPIO_18)

HSYNC2 - ATI Internal Use Only - Reserved

BIF_CLK_PM_EN
0 - Disable CLKREQ# power management capability
1 - Enable CLKREQ# power management capability

GPIO_15 - FOR FUTURE EXPANSION

GPIO_22_ROMCSb - Enable external BIOS ROM device (Default 1)

GPIO_18 - DDR2 MEM VENDOR [V2SYNC:GPIO_18]
QUIMONDA [0:0]
HYNIX [0:1]
SAMSUNG [1:0]

tmel - AT25F512A (512 kbit)0010

AT25F1024A (1 Mbit)0011

ST Microelectronics- M25P05A (512 kbit) 0100

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

13 20

of

13 20

of

13 20

ATI Board Feature I

1

ATI PCIE FEATURE I

ATI PCIE FEATURE II

If BIOS_ROM_EN = 0, then Config[2:0]
defines the primary memory aperture size.
(Config 3 = don care).

x000 128MB
x001 256MB
x010 64MB
x011 32MB
x100 512MB
x101 1GB
x110 2GB
x111 4GB

(Default: 0)

ATI Board Feature I

RevDate:

RevDate:

RevDate:

00

00

00

Doc No.

Doc No.

Doc No.

105-B350xx-00

105-B350xx-00

105-B350xx-00

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1

Optional ESD Protection Diodes

Place close to Connector
Pseudo differential RGB signals should be routed from the ASIC to the display connector without switching reference plane or running over split plane
Resistors are footprint options for the inductors. Footprints should be overlapped. (R1024-26)

DNI

R1024 0RR1024 0R

DNI

R1025 0RR1025 0R

DNI

L1004 47nHL1004 47nH
L1005 47nHL1005 47nH
L1006 47nHL1006 47nH

C1003

C1003

C1002

C1002

8.0pF

8.0pF

8.0pF

8.0pF

R1026 0RR1026 0R

A_R_DAC1(3)

A_RB_DAC1(3)

D D

A_G_DAC1(3)

A_GB_DAC1(3)

A_B_DAC1(3)

A_BB_DAC1(3)

R1003

R1003

R1002

R1002

R1001

R1001

75R

75R

75R

75R

75R

R1029

R1029

37.4R

37.4R

R1028

R1028

37.4R

37.4R

R1027

R1027

37.4R

37.4R

75R

A_R_DAC1_M
A_G_DAC1_M
A_B_DAC1_M

C1001

C1001

8.0pF

8.0pF

402 402 402

+3.3V +5V_VESA

D1001

D1001

4
5
6

CM1213-04

CM1213-04

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F

DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R

A_VSYNC_DAC1_R

3

CH2

CH3

2

Vn

Vp

1

CH1

CH4

Place close to Connector
SHOULD BE A LOW INDUCTANCE PATH TO PIN 5

4
5
6

D1002

D1002

CH3
Vp
CH4

CM1213-04

CM1213-04

3

CH2

2

Vn

1

CH1

C1010

C1010
68pF

68pF

603

603

+5V_VESA

MJ1001

MJ1001

1
2

3
11
12

4
15

9
13
14

5

6

7

8
10
16
17

G3179C219-005

G3179C219-005

R
G
B
MS0
MS1
MS2
MS3
NC
HS
VS
VSS
VSS#6
VSS#7
VSS#8
VSS#10
CASE
CASE#17

SLIM VGA

+3.3V

R1004

R1004
10K

10K

C C

A_HSYNC_DAC1(3,13)

A_VSYNC_DAC1(3,13)

B B

CRT1DDCDATA(3)

CRT1DDCCLK(3)

C1999 100nFC1999 100nF

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

402

+3.3V +5V_VESA

R1007

R1007
10K

10K

402

+5V_VESA

U1999A

U1999A

14

2 3

7

5 6

A_HSYNC_DAC1_B

74AHCT125

74AHCT125

1

U1999B

U1999B

4

A_VSYNC_DAC1_B

74AHCT125

74AHCT125

+5V_VESA

1

R1005

R1005

2.2K

2.2K
DDCDATA_DAC1_5V

402

32

BSH111

BSH111
Q1001

Q1001

1

R1008

R1008

2.2K

2.2K
DDCCLK_DAC1_5V

402

32

BSH111

BSH111
Q1002

Q1002

R1006 33RR1006 33R

R1009 33RR1009 33R

R1010

R1010

R1011

R1011

33R

33R

33R

33R

402

402

DDCDATA_DAC1_R

DDCCLK_DAC1_R

A_HSYNC_DAC1_R

A_VSYNC_DAC1_R

TjX2M(4)
TjX2P(4)

TjX4M(4)
TjX4P(4)

DDCCLK_DAC1_R
DDCDATA_DAC1_R
A_VSYNC_DAC1_R

TjX1M(4)

+3.3V

Q1021

Q1021

MMBT3904

HPD1(3)

MMBT3904

2 3

R1023

R1023
10K

10K

1

R1022 10KR1022 10K

TjX1P(4)
TjX3M(4)

TjX3P(4)

HPD_DVI1

TjX0M(4)
TjX0P(4)

TjX5M(4)
TjX5P(4)

TjXCP(4)
TjXCM(4)

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F
A_HSYNC_DAC1_R

DB15 pin

Standard VGA

DDC1 Host

Monitor ID bit 0
Monitor ID bit 1
Monitor ID bit 2
Monitor ID bit 3

N/C
Mechanical Key

Monitor ID bit 0
Data from display
Monitor ID bit 2
Open
+5V
50mA min
1A max

J1001

J1001

25

CASE

1

TMDS Data2-

2

TMDS Data2+

3

TMDS Data2/4 Shield

4

TMDS Data4-

5

TMDS Data4+

6

DDC Clock

7

DDC Data

8

Analog VSYNC

9

TMDS Data1-

10

TMDS Data1+

11

TMDS Data1/3 Shield

12

TMDS Data3-

13

TMDS Data3+

14

+5V Power

15

GND (for +5V)

16

Hot Plug Detect

17

TMDS Data0-

18

TMDS Data0+

19

TMDS Data0/5 Shield

20

TMDS Data5-

21

TMDS Data5+

22

TMDS Clock Shield

23

TMDS Clock+

24

TMDS Clock-

C1

Analog Red

C2

Analog Green

C3

Analog Blue

C4

Analog HYNC

C5

Analog GND

C6

Analog GND#C6

26

CASE#26

27

CASE#27

28

CASE#28

29

CASE#29

30

CASE#30

DVI_CONNECTOR

DVI_CONNECTOR

11
12
4
15

9

Hardware
Support No Yes Yes No Yes

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA

DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max

DDC2AB Host
Monitor ID bit 0

SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max

DDC1/2 Display
Optional

SDA
Optional
SCL

Optional

A A

8

7

TMDS_2(Daul_Link) + DAC_1-CRT

6

5

4

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

3

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

14 20

of

14 20

of

14 20

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

8

7

6

5

4

3

2

1

Optional ESD Protection Diods

Place close to Connector
Pseudo differential RGB signals should be routed from the ASIC to the display connector without switching reference plane or running over split plane

DNI

R2024 0RR2024 0R

DNI

R2025 0RR2025 0R

DNI

A_R_DAC2_M
A_G_DAC2_M

C2003

C2003

8.0pF

8.0pF

402

R2006 33RR2006 33R

R2009 33RR2009 33R

R2010

R2010

R2011

R2011

R2026 0RR2026 0R

L2004 47nHL2004 47nH
L2005 47nHL2005 47nH
L2006 47nHL2006 47nH

OVERLAP

402

DDCCLK_DAC2_R

A_HSYNC_DAC2_R

402

33R

33R

A_VSYNC_DAC2_RA_VSYNC_DAC2_B

402

33R

33R

A_R_DAC2(3)

A_RB_DAC2(3)

D D

A_G_DAC2(3)

A_GB_DAC2(3)

A_B_DAC2(3)

A_BB_DAC2(3)

R2028

R2029

R2029

37.4R

37.4R

C C

A_HSYNC_DAC2(3,13)

A_VSYNC_DAC2(3,13)

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

R2028

37.4R

37.4R

+3.3V

CRT2DDCDATA(3)

CRT2DDCCLK(3)

+3.3V +5V_VESA

9 8

10
13

12 11

R2003

R2003

R2001

R2001

R2002

R2002

75R

75R

75R

75R

75R

R2027

R2027

37.4R

37.4R

R2004

R2004
10K

10K

402

R2007

R2007
10K

10K

402 402

U1999C

U1999C

74AHCT125

74AHCT125

U1999D

U1999D

74AHCT125

74AHCT125

75R

1

32

BSH111

BSH111
Q2001

Q2001

1

32

BSH111

BSH111
Q2002

Q2002

A_HSYNC_DAC2_B

402

+5V_VESA

R2005

R2005

2.2K

2.2K
DDCDATA_DAC2_5V DDCDATA_DAC2_R

402

R2008

R2008

2.2K

2.2K
DDCCLK_DAC2_5V

402

C2001

C2001

8.0pF

8.0pF

402 402

C2002

C2002

8.0pF

8.0pF

A_B_DAC2_M

+3.3V +5V_VESA

D2001

A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F

DDCDATA_DAC2_R
DDCCLK_DAC2_R
A_HSYNC_DAC2_R

A_VSYNC_DAC2_R

A_R_DAC2_F
A_B_DAC2_F

DDCCLK_DAC2_R

4
5
6

D2001

CM1213-04

CM1213-04

CH3
Vp
CH4

+5V_VESA

3

CH2

2

Vn

1

CH1

J2

J2

1
3
5
7

9
11
13
15

Header_16_Pin_2X8

Header_16_Pin_2X8

2
4
6
8
10
12
14
16

A_G_DAC2_F

DDCDATA_DAC2_R
A_VSYNC_DAC2_RA_HSYNC_DAC2_R

2X8 HEADER FOR VGA RIBBON CONNECTOR

D2002

D2002

4

CH3

5

Vp

6

CH4

CM1213-04

CM1213-04

Place close to Connector

3

CH2

2

Vn

1

CH1

B B

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

8

7

6

5

4

3

TMDS_1(Single_Link) + DAC_2-CRT

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

15 20

of

15 20

of

15 20

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

8

D D

DDC3CLK(3,11)

DDC3DATA(3,11)

C C

Warning: TS_FDO is not 5V
tolerant. MAX sink current

1.65mA

R4032

R4032

2.61K

2.61K

R4033

R4033
20K

20K

DNI

PWM

R4016 1KR4016 1K

OVERLAP

+3.3V

B B

A A

TS_FDO(3)

TP4002TP4002 R1260

+3.3V

DNI

R40050RR4005
0R

R4003

R4003
10K

10K

DNI DNI

R4017

R4017
10K

10K

7

R4001 100RR4001 100R
R4002 100RR4002 100R
R4015 0RR4015 0R

R4028

R4028
10K

10K

DNI

R40190RR4019
0R

1

+12V_BUS

2 3

R4034

R4034

2.61K

2.61K

Q4001

Q4001

MMBT3904

MMBT3904

402

402

1

R4031 0RR4031 0R
DNI-TEST ONLY

INTERFACE INFO: SMBUS SLAVE
Clock: Min 10kHz - Max 100kHz
7 bit address: 100 1100

SCL_R
SDA_R
TACH

R4006

R4006

2.61K

2.61K

402 1%

Q4004

Q4004

MMBT3904

MMBT3904

2 3

C4005

C4005
56pF_50V

56pF_50V

402
NPO

6

C4006

C4006
56pF_50V

56pF_50V

402
NPO

R4008 100KR4008 100K

R40071KR4007
1K

402
1%

FAN_REF

+3.3V

MMBT3906

MMBT3906

Q4002

Q4002

Qx

C4001

C4001

10uF

10uF

U4001

U4001

8

SMCLK

7

SMDATA

6

ALERT
GND5FAN

EMC2101-ACZT-TR

EMC2101-ACZT-TR

1

R40350RR4035
0R

C4007

C4007
1uF

1uF

805
16V
Y5V

5

C4002

C4002

C4003

C4003

1uF_6.3V

1uF_6.3V

100pF_50V

100pF_50V

1

VDD

2

D+

3

D-

PWM

4

R4009

R4009
100K

100K

402 402

1

23

R4010 0RR4010 0R

DNI

C4004

C4004

2.2nF_50V

2.2nF_50V

402
50V
X7R

2 3

+3.3V_BUS

R1258

R1258
100K

100K

R4011

R4011
100K

100K

Q4003

Q4003
MMBT3904

MMBT3904

R4013

R4013

1.47K

1.47K

402

R4004

R4004
10K

10K

12V_FAN_SUPPLY

FAN_BJT_CNTL

R4012 10KR4012 10K

CTF_SET_EN1

R1256

R1256
200R

200R

CTFb(3)

4

Remote diode temp sensor is for
RV620 BU, until internal thermal
sensor is calibrated.

GPU_DPLUS

GPU_DMINUS

C1252

C1252
100nF

100nF

GPU_DPLUS (3)

GPU_DMINUS (3)ThermINT(3)

32

MQ4004

MQ4004
2SB1188

2SB1188

1

+3.3V_BUS

R1260
10K

10K

CTF_SET_EN2

Q1253

Q1253

1

MMBT3904

MMBT3904

2 3

R1254 0RR1254 0R

CTF_IN

CTFb

R1255

R1255
10K

10K

DNI

IF CTF IS ACTIVE HIGH, DNI R1254, R1251
IF CTF IS ACTIVE LOW, DNI R1255, Q1252

+3.3V_BUS

1

R40140RR4014
0R

3

H3A

H3A

RV610_FANSINK

RV610_FANSINK

H3C

H3C

+12V_BUS

B4001

B4001
26R_600mA

26R_600mA

C4008

C4008
1uF

1uF

805
16V

C4010

C4010

10uF

10uF

16V

Y5V

FAN_OUT

DNI

17181920212223

JU4001JU4001

1
2

23567

1

RV610_FANSINK

RV610_FANSINK

2

H2

H2
RV610_LP_HEATSINK

RV610_LP_HEATSINK

8

H3B

H3B

9

10111213141516

H3D

H3D

25262728293031

RV610_FANSINK

RV610_FANSINK

RV610_FANSINK

RV610_FANSINK

32

1

Critial Temperature Fault

1

Q1250

Q1250
BSH111

BSH111

C1251

C1251
100nF

100nF

+3.3V_BUS

32

R1253 0RR1253 0R

+3.3V_BUS

R1252

R1252
10K

10K

CTF_SET

C1250

C1250
100nF

100nF

2

1

CTF_GATED

DNI

U1250

U1250

8PR7

NC7SZ74K8X

NC7SZ74K8X

5

D

Q

Vcc

CTF_OUT

R1259 10KR1259 10K

3

G4CL

C

Q

6

R1257

R1257
100K

100K

CTF_VCNTL

VDD_EN

VDD_EN (10,11)

Q1251

Q1251

1

MMBT3904

MMBT3904

2 3

R1250

R1250
10K

10K

Q1254

Q1254
MMBT3904

MMBT3904

2 3

+3.3V

R1251

R1251
10K

10K

32

Q1252

Q1252
BSH111

BSH111

1

DNI

8

7

6

5

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

4

3

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Sheet

Sheet

Sheet

of

17 20

of

17 20

of

17 20

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

5

D D

4

3

2

1

DVI/VGA SCREWS

ASSY-SCREW1

ASSY-SCREW1

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
ASSY

ASSY

ASSY-SCREW3

ASSY-SCREW3

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
ASSY

ASSY

C C

ASSY1

ASSY1

BRACKET

BRACKET

8020040100G

8020040100G

ASSY-SCREW2

ASSY-SCREW2

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
ASSY

ASSY

ASSY-SCREW4

ASSY-SCREW4

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
ASSY

ASSY

ASSY2

ASSY2

BRACKET

BRACKET
LP

LP

8020040400G

8020040400G

ASSY-SCREW5

ASSY-SCREW5

SCREW

SCREW
SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L

SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L

SK1

SK1

BGA_Socket_RV620

BGA_Socket_RV620

MT1

MT1
MT_Hole_0.136_in.

MT_Hole_0.136_in.

DNI DNI

MT2

MT2
MT_Hole_0.136_in_6VIA

MT_Hole_0.136_in_6VIA

1

FM2

FM1

FM1

SW_FB

SW_FB

NS

NS

FM3

FM3

SW_FB

SW_FB

1

NS

NS

FM2

SW_FB

SW_FB

1

NS

NS

FM4

FM4

SW_FB

SW_FB

1

NS

NS

FM5

FM5

SW_FB

SW_FB

1

NS

NS

FM6

FM6

SW_FB

SW_FB

1

NS

NS

FM11FM11

B B

FM12FM12

A A

5

4

3

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, December 12, 2007

Wednesday, December 12, 2007

Wednesday, December 12, 2007

Sheet

Sheet

Sheet

of

18 20

of

18 20

of

18 20

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

REVISION HISTORY

REVISION HISTORY

D D

Sch

PCB

Sch

PCB

Sch
Rev

Rev

Rev

PCB
Rev

Rev

Rev

Date

Date

Date

2007.05.07

00A01

REVISION HISTORY

START NEW SCHEMATIC. DERIVED FROM B170 (RV610) SCHEMATIC.

4

NOTE:

NOTE:

NOTE:

3

105-B350xx-00

105-B350xx-00

105-B350xx-00

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU.
For Stuffing options (component values, DNI, ? please consult the product specific BOM.

For Stuffing options (component values, DNI, ? please consult the product specific BOM.

For Stuffing options (component values, DNI, ? please consult the product specific BOM.
Please contact AMD representative to obtain latest BOM closest to the application desired.

Please contact AMD representative to obtain latest BOM closest to the application desired.

Please contact AMD representative to obtain latest BOM closest to the application desired.

REVISION DESCRIPTION

REVISION DESCRIPTION

REVISION DESCRIPTION

2

1

Date:Schematic No.

Date:Schematic No.

Date:Schematic No.

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Tuesday, December 11, 2007

Rev

Rev

Rev

00

00

00

00A03

00A

00A

00A

00A09

00A

00A

00A013

00A

00A

2007.05.17

2007.05.17

2007.05.22

2007.05.24

2007.05.25

2007.05.28

2007.05.28

2007.05.29

2007.05.30

2007.05.30

2007.05.31

2007.05.31

2007.05.32

2007.06.1

02 00A

04 00A

05

C C

06

07

08 00A

010 00A

011

012

B B

014

015

p. 4 MR155/R155 FIX SHORT

RM R7, NR7, R5, MB60, MR45, R45, R890, R1248, R1247, R1242, R1243, C853, C863; ADD R2, B890, MR890, C846; CHANGE R1022, R1023;

REMOVE GND_TXVSSR, GND_PVSS; AG23 NOW NC - WAS SCHEM MISTAKE; ADD R858 FOR BUO; R858 CHANGE TO 1210;

CTF: ADD Q1252, R1254, R1255, R1256, R1258, Q1253, Q1254, CHANGE U1250 TO SINGLE FF; UPDATE BLOCK DIAGRAM.

LVTM: ADD R110, RM R109, MR109, R108, R107;

LVTM: ADD C118, RM C104; REMOVE MR85, MR86 FOR SIMPLIFICATION;

XTALIN/OUT: LAYOUT EASEMENT; REMOVE MR108 (R849 ALREADY THERE); LVTM: ADD C119 (LOWER COST OPTION); POWER SUPPLY: REMOVE R706, MR707, R606 & MR607;

REMOVAL OF +5V: ADD R861, MR861, R862, REG861, R869, R863, R867; REMOVE MU830, U830, C830. R833, R834, C831, R832, MR832, R831, MR831; CONNECT DDC TO 5V_VESA;

CHNG C858 TO 3.3VBUS; CONNECTION TO R845 CHNG; ADD R870, MR870, C867;

REMOVE R4033; REMOVE B201-204; ADD R30-33 [PLACE NEAR ASIC]; REMOVE R3004, R3005;

REMOVE C164-C166, C170, C172 PER SIMULATION RESULTS - THESE CAPS DO NOT IMPROVE DECOUPLING. RM TP860 (LAYOUT CONSTRAINTS. ALREADY ICT TP ON THAT NET);

RM R154-R157, MR154-157 -> FUNCTIONALITY TAKEN BY EXISTING STRAPS. LAYOUT USE PLACE OF M/R154-7; ADD R7; RM MR706, MR606, B889, R863; ADD D861;

ADD SOCKET SK1

SK? CORRECTED TO SK1.

2007.06.25

00B

016

017

A A

018 00

2007.10.01

00

2007.12.11

5

NO NETLIST CHANGES; - MOUNTING HOLES CHANGED TO 3.175mm;

p. 1 - CONNECT B7 TO GND (SEE PA RV6XX H1)

- REMOVE R2. IT IS ALWAYS POPULATED, NO NEED TO ZERO OHM. THIS BOARD DOES NOT SUPPORT JTAG DEBUG;
p. 11 - REMOVE R839. THIS CIRCUIT IS VERIFIED, THERE IS NO NEED TO BE ABLE TO DISCONNECT IT;
p. 12 - REMOVE R870 - THIS OPTION NOT USED, VCNTRL MUST BE HIGHER THAN +3.3V;

- MR870 REMOVED - ALWAYS POPULATED, DO NOT NEED ZERO OHM RESISTOR OPTION;

- REMOVE R860 - WAS BRING UP ONLY OPTION;
p. 17 - REPLACED FAN CIRCUIT WITH ONE THAT HAS FEEDBACK:

- ADD R4033, R4031, R4019, R4034, R4006, R4035, Q4004, R4035, Q40002. R4009, R4011, Q4003, R4012, R4013;

P.16-Base on105-B350XX-00.DSN remove TV-OUT function:

-Remove R3001-3003,C3001-3006,L3001-3003

-Remove R3006-3011,C3007-3010,J3001

4

3

2

1

PDF created with pdfFactory Pro trial version www.pdffactory.com

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5

4

3

2

1

MEMORY CHANNEL A

D D

64bit DDR2 32M/16Mx16

MEMORY CHANNEL B

64bit DDR2 32M/16Mx16

MEM A MEM B

POWER REGULATION

From +12V SMPS

ASIC Core:
ASIC Core I/O:
Memory:

From +12V LIN.REG.

+5V, +5V_VESA

C C

B B

From +12V_BUS DIRECT

From +3.3V LIN.REG.

Memory PLL:
PCIe:
I/O Level Shift:
PLL_Analog:
DVP:
DAC1:
TMDS1:
DAC2:

From +3.3V DIRECT

3.3V I/O:

VDDC
VDDCI
MVDD, VDDR1, VDDRH

FAN

MPVDD

PCIE_VDDC, PCIE_VDDR, PCIE_PVDD

VDD_CT
DPLL_PVDD
VDDR4, VDDR5
AVDD, VDD1DI
TPVDD, TXVDDR
A2VDD, VDD2DI, A2VDDQ

VDDR3

+PCIE_SOURCE

+12V_BUS+3.3V_BUS

FAN

Straps

BIOS

Built-in PWM

External
Fan
Controller

Critical Temp.
Fault Circuit

Flash ROM

Settings

Interrupt

Temperature
Sensor Output

CFTb

GPIO0..7
GPIO9, 11..13

GPIO8..10
GPIO22

TS_FDO

DDC3CLK
DDC3DATA

GPIO17

D+/D-

GPIO19

Dual-Link TMDS

DAC1

DAC2

RV620 ASIC

XTALIN/OUT

HPD1

CRT

H/VSync

DDC1

TVO

CRT2

H/V2Sync

DDC2

TMDS matching

XTAL / Oscillator

RGB Filters

TVO Filters

RGB Filters

DVI-I or Slim VGA

Connector

TVO

Connector

(optional)

VGA Ribbon

Connector

PCI-Express

Power Up/Down
Sequencing Circuit

+3.3V_BUS
+12V_BUS

PCI-Express Bus

RV620 B350 DDR2-BGA84 LP 4-Layer

REV 01

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices

?2007 Advanced Micro Devices

?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

5

4

3

2

RH RV620 256/128MB DDR2-BGA84 32/16Mx16 VO dDVI

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Thursday, November 29, 2007

Thursday, November 29, 2007

Thursday, November 29, 2007

Sheet

Sheet

Sheet

of

20 20

of

20 20

of

20 20

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

00

00

00

105-B350xx-00

105-B350xx-00

105-B350xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn