Page 1
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
ASSEMBLYNVPNVARIANT
B
1
2
SKU
3
4
5
6
12
13
14
7
8
9
10
11
15
P393-A01 DT SKU 4
G92-270, 16Mx32 GDDR3 900 MHz,
DVI-I-DL, DVI-I-DL, HDTVout
Table of Contents:
Page 1: Overview
Page 2: PCI Express 1.0
Page 3: MEMORY: GPU Partition A/B
Page 4: MEMORY: GPU Partition C/D
Page 5: FBA Partition
Page 6: FBB Partition
Page 7: FBC Partition
Page 8: FBD Partition
Page 9: FrameBuffer Net Rules
Page 10: DACA Interface
Page 11: DACC Interface
Page 12: IFP A/B and C/D Interface
Page 13: DACB and Stereo Interface
Page 14: Multi-use IO(MIO) Interface
Page 15: DisplayPort Transmitter
Page 16: MISC: GPIO, I2C, BIOS, PLL, and XTAL
Page 17: Thermal Control/Protection and SPDIF Input
Page 18: Power/GND and Decoupling
Page 19: Configuration Straps and Mechanical
Page 20: Power Supply: 5V, STEREO_5V, 2V5, DP_PWR
Page 21: Power Supply: 1V2, 1V8
Page 22: Power Supply: FBVDD/Q, 8V5
Page 23: Power Supply: NVVDD Regulator
Page 24: Power Supply: NVVDD Phase 1 & 2
Page 25: Power Supply: NVVDD Phase 3
Page 26: Power Supply: Filter/Detection 3V3, 12V, 12V_PEX6
Page 27: Power Supply: Hybrid Power
BASE
SKU_DT_0000
SKU_DT_0002
SKU_WS_0500
SKU_WS_0501
SKU_DT_0004
SKU_DT_0006
SKU_WS_0503
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Overview
www.vinafix.vn
600-10393-base-100
600-10393-0000-100
600-10393-0002-100
600-50393-0500-100
600-50393-0501-100
600-10393-0004-100
600-10393-0006-100
600-50393-0503-100
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
P393 G92-300 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-200 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-875 512MB GDDR3 16Mx32 DVI-I+DP+STEREO
P393 G92-850 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I, Apple
P393 G92-875 512Mb GDDR4 16Mx32 DVI-I+DVI-I+STEREO
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
600-10393-0004-100 A
p393_a01
whill
1 OF 27
28-SEP-2007
Page 2
J501
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTININ
23/24 JTAG
JTAG_TDI
JTAG_TCLK
JTAG_TMS
JTAG_TDO
JTAG_TRST
KEY
TRST*
TCK
GND
TMS
TDO
VCC
TDI
IN
IN
1/24 PCI EXPRESS
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
RFU
RFU
PEX_PLLAVDD
PEX_PLLDGND
PEX_PLLAGND
PEX_PLLDVDD
PEX_TEST_PLL_CLK_OUT
PEX_TEST_PLL_CLK_OUT
PEX_TX0
PEX_REFCLK
PEX_REFCLK
PEX_RST
PEX_TX0
PEX_RX1
PEX_TX1
PEX_RX0
PEX_TX2
PEX_TX2
PEX_RX2
PEX_TX3
PEX_RX1
PEX_TX3
PEX_RX3
PEX_RX3
PEX_TX1
PEX_RX0
PEX_RX2
PEX_RX5
PEX_TX6
PEX_RX6
PEX_RX6
PEX_TX7
PEX_TX4
PEX_TX4
PEX_RX4
PEX_TX6
PEX_RX5
PEX_RX4
PEX_TX5
PEX_TX5
PEX_TX7
PEX_TX9
PEX_RX8
PEX_TX8
PEX_RX9
PEX_RX7
PEX_TX9
PEX_TX10
PEX_RX7
PEX_TX8
PEX_TX10
PEX_RX9
PEX_RX8
PEX_RX10
PEX_RX11
PEX_RX10
PEX_TX12
PEX_TX12
PEX_RX11
PEX_RX12
PEX_RX12
PEX_TX13
PEX_TX13
PEX_RX13
PEX_RX13
PEX_TX11
PEX_TX11
PEX_TX14
PEX_RX15
PEX_RX15
PEX_TX15
PEX_TX15
PEX_RX14
PEX_RX14
PEX_TX14
INININ
OUT
S
D
G
IN
END OF X8
END OF X16
END OF X1
END OF X4
TCLK JTAG2
TMS JTAG5
TDO JTAG4
TDI JTAG3
WAKE
SMDAT
SMCLK
PERN0
PERP0
REFCLK
PERST
REFCLK
PETN1
PERP2
PETN0
PERP1
PERN1
PETP0
PETP1
PERN3
PETP3
PETN3
PETP2
PERP3
PETN2
PERN2
PERP4
PERN4
PETN4
PERP5
PETP4
PERN5
PETP5
PETP6
PERN6
PERP6
PETN5
PERP7
PETN6
PERN7
PETN8
PETP8
PERP8
PETN7
PETP7
PERN8
PERN9
PERP9
PERP10
PERN10
PETP10
PETP9
PETN9
PETN10
PETN11
PERP12
PERN12
PERP11
PERN11
PETP11
PETN12
PETP12
PETN13
PERP13
PERN13
PETP13
PERP14
PERN15
PETP15
PETN15
PERN14
PETN14
PETP14
PERP15
TRST* JTAG1+12V
+12V/RSVD
+3V3AUX
+12V
+12V
+12V
+3V3
+3V3
+3V3
PRSNT2
PRSNT1
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
GND
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
HDR_2F4
FEMALE
3V3_F
1
3
5
7
1.274MM
0
KEY6_JTAG_SMALL
NO STUFF
2
4
8
AH21
AJ21
AH22
AJ22
AH23
AJ23
AH16
AF17
AH17
AF18
AH18
AF19
AH19
AE20
AF20
AH20
AJ20
PEX_PLL_CLK_OUT
AM9
PEX_PLL_CLK_OUT*
AN9
SNN_PEXCAL_PD_VDDQ
AK19
SNN_PEXCAL_PD_GND
AK20
PEX_PLLAVDD
AE15
AE17
Fix for G92 NC pin issue
AF15
AE16
GND
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
PCI Express 1.0
www.vinafix.vn
2<
27<>
2> 27>
.1UF
10V
10%
.1UF
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UFC800
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
16<
27<
0402
0402
C894
0402
C885
0402
C869
0402
C853
0402
C837
C811
0402
C791
0402
C763
0402
C729
0402
C704
0402
C692
0402
0402
C673
0402
C670
R692
0402
0402
R697
0402
R695
0402
R693
0402
5%
5%
5%
5%
5%
0
NO STUFF
0R700
NO STUFF
0
NO STUFF
0
NO STUFF
0
NO STUFF
JTAG_TRST*
JTAG_TCLK
JTAG_TDI
JTAG_TDO
JTAG_TMS
27> 16>
G1
G92-300-A1
BGA1148
COMMON
AR9
AK10
AL10
AM11
AM10
AP9
AP10
AN10
AR10
AR11
AN12
AM12
AT11
AT12
AL12
AK12
AP12
AP13
AM14
AM13
AR13
AR14
AN13
AN14
AT14
AT15
AN15
AM15
AP15
AP16
AL15
AK15
AR16
AR17
AN16
AT17
AT18
AN17
AN18
AP18
AP19
AM18
AM17
AR19
AR20
AL18
AK18
AT20
AT21
AM19
AN19
AP21
AP22
AN20
AN21
AR22
AR23
AM21
AM20
AT23
AT24
AL21
AK21
AR24
AR25
.1UFC915
10V
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V0402
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UFC677
10V
.1UF
10V
.1UF
10V0402
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
10%
X5R
10%
X5R
10%
X5R
10%
X5R
GPU_RST*
PEX_TX0
PEX_TX0*
COMMON
PEX_TX1
PEX_TX1* AN11
COMMON
PEX_TX2
PEX_TX2*
COMMON
PEX_TX3
PEX_TX3*
COMMON
PEX_TX4
PEX_TX4*
COMMON
PEX_TX5
PEX_TX5*
COMMON
PEX_TX6
PEX_TX6*
COMMON
PEX_TX7
PEX_TX7*
COMMON
PEX_TX8 AM16
PEX_TX8*
COMMON
PEX_TX9
PEX_TX9*
COMMON
PEX_TX10
PEX_TX10*
COMMON
PEX_TX11
PEX_TX11*
COMMON
PEX_TX12
PEX_TX12*
COMMON
PEX_TX13
PEX_TX13*
COMMON
PEX_TX14
PEX_TX14*
COMMON
PEX_TX15
PEX_TX15*
COMMON
Page2: PCI Express 1.0
12V
3V3
See filtering on page 26
1
PEX_REFCLK_EN
C50
C51
4.7UF
4.7UF
16V
16V
20%
20%
X7R
X7R
1206
1206
COMMON
COMMON
GND
PEX_PRSNT1*
SNN_PEX_PRSNT2_A
SNN_PEX_RSVD1
SNN_PEX_PRSNT2_B
SNN_PEX_RSVD2
SNN_PEX_RSVD3
SNN_PEX_RSVD4
SNN_PEX_PRSNT2_C
SNN_PEX_RSVD5
V_BE_GS=+/-20V
MAX_WATTAGE=0.36W@25C
MAX_CURRENT=0.88A
R_DS_ON=3.5R
CONTINUOUS_CURRENT=0.22A@31C
MAX_VOLTAGE=50V
1G1D1S
2
NO STUFF
SOT23_1G1D1S
BSS138
Q1209
3
PEX_PRSNT2*
SNN_PE_RSVD6
SNN_PE_RSVD7
27>
C54
.1UF
16V
10%
X7R
0402
COMMON
3V3_AUX
GND
GND
GND
GND
PEX_PRSNT1*
CN1
NONPHY-X16-B
CON_X16
CON_PCIEXP_X16_EDGE
NO STUFF
B1
B2
A2
A3
B3
B8
A9
A10
B10
A1
B17
B12
B4
A4
B7
A12
B13
A15
B16
B18
A18
B31
A19
B30
A32
A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32
B48
A33
A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49
B81
A50
B82
A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82
R1219
0402
PEX_TRST*
B9
PEX_TCLK
A5
PEX_TDI
A6
PEX_TDO
A7
PEX_TMS
A8
I2CS_SCL_R
B5
I2CS_SDA_R
B6
SNN_PEX_WAKE*
B11
PEX_RST*
A11
PEX_REFCLK
A13
PEX_REFCLK*
A14
PEX_TX0_C
A16
PEX_TX0_C*
A17
PEX_RX0
B14
PEX_RX0*
B15
PEX_TX1_C
A21
PEX_TX1_C*
A22
PEX_RX1
B19
PEX_RX1*
B20
PEX_TX2_C
A25
PEX_TX2_C*
A26
PEX_RX2
B23
PEX_RX2*
B24
PEX_TX3_C
A29
PEX_TX3_C*
A30
PEX_RX3
B27
PEX_RX3*
B28
PEX_TX4_C
A35
PEX_TX4_C*
A36
PEX_RX4
B33
PEX_RX4*
B34
PEX_TX5_C
A39
PEX_TX5_C*
A40
PEX_RX5
B37
PEX_RX5*
B38
PEX_TX6_C
A43
PEX_TX6_C*
A44
PEX_RX6
B41
PEX_RX6*
B42
PEX_TX7_C
A47
PEX_TX7_C*
A48
PEX_RX7
B45
PEX_RX7*
B46
PEX_TX8_C
A52
PEX_TX8_C*
A53
PEX_RX8
B50
PEX_RX8*
B51
PEX_TX9_C
A56
PEX_TX9_C*
A57
PEX_RX9
B54
PEX_RX9*
B55
PEX_TX10_C
A60
PEX_TX10_C*
A61
PEX_RX10
B58
PEX_RX10*
B59
PEX_TX11_C
A64
PEX_TX11_C*
A65
PEX_RX11
B62
PEX_RX11*
B63
PEX_TX12_C
A68
PEX_TX12_C*
A69
PEX_RX12
B66
PEX_RX12*
B67
PEX_TX13_C
A72
PEX_TX13_C*
A73
PEX_RX13
B70
PEX_RX13*
B71
PEX_TX14_C
A76
PEX_TX14_C*
A77
PEX_RX14
B74
PEX_RX14*
B75
PEX_TX15_C
A80
PEX_TX15_C*
A81
PEX_RX15
B78
PEX_RX15*
B79
PEX_PRSNT2*
0
COMMON
5%
* PRSNT# isolation bypass option
R696
0
5%
0402
NO STUFF
C917
0402
COMMON
X5R
C907
0402 10V .1UFC906
COMMON
X5R
C904
0402
COMMON
X5R
C890
0402
COMMON
X5R
C872
0402
COMMON
X5R
C857
0402
COMMON
X5R
C843
0402
COMMON
X5R
C818
0402
COMMON
X5R
0402
COMMON
X5R
C768
0402
COMMON
X5R
C736
0402
COMMON
X5R
C707
0402
COMMON
X5R X5R
C697
0402
COMMON
X5R
C681
0402
COMMON
X5R
C674
0402
COMMON
X5R
C671
0402
COMMON
X5R
3V3_F
GND
C752
.1UF
10V
10%
X5R
0402
COMMON
C753
10V
10%
X5R
0402
COMMON
C745
.1UF
10V
10%
X5R
0402
COMMON
PEX_TEST_PLL_CLK_OUT
Termination = 200ohm
Place on bottom side
for test access
R683
10K
5%
0402
COMMON
3V3_AUX
GND
C773
.1UF
10V
10%
X5R
0402
COMMON
C767
.1UF.1UF
10V
10%
X5R
0402
COMMON
C765
.1UF
10V
10%
X5R
0402
COMMON
C63
.1UF
16V
10%
X7R
0402
COMMON
R688
R677
180
10K
5%
5%
0402
0402
COMMON
3.3V
.01A
10MIL
COMMON
R649
200
5%
0402
COMMON
JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
R689
R681
270
10K
5%
5%
0402
0402
COMMON
COMMON
GND
.1UF
10V
10%
X5R
0402
R55
47K
5%
0402
NO STUFF
C771
1UF
6.3V
10%
X5R
0402
C770
1UF 4.7UF
6.3V
10%
X5R
0402
COMMON
C785
1UF
6.3V
10%
X5R
0402
COMMON
C790
1UF
6.3V
10%
X5R
0402
COMMON
C746
1UF
6.3V
10%
X5R
0402
COMMON
C772
1UF
6.3V
10%
X5R
0402
COMMON
R58
47K
5%
0402
NO STUFF
Place components within 750mils from pad
Replaced bead with 10nH inductor per SI recommendation
C792C802
1UF
6.3V
10%
X5R
0402
JTAG
AK6
AL8
AL7
AK7
AL9
C731
4.7UF
6.3V
10%
X5R
0603
COMMONCOMMON
C727
6.3V
10%
X5R
0603
COMMON
I2CS_SCL_R
I2CS_SDA_R
G1
G92-300-A1
BGA1148
COMMON
GND
GND
L6
C93
4.7UF
6.3V
10%
X5R
0603
COMMONCOMMONCOMMON
C699
10UF
6.3V
20%
X5R
0805
COMMON
C92
10UF
6.3V
20%
X5R
0805
COMMON
1V2
1V2
2< 16<
2< 16<
10nH
COMMON0402
16<>
1V2
GND
27> 16>
27<>
C95
4.7UF
6.3V
10%
X5R
0603
COMMON
PEX NET RULES
PEX_PLLAVDD
PEX_PLLDVDD
NV_CRITICALNET
PEX_REFCLK
PEX_REFCLK*
PEX_TX0_C
PEX_TX0_C*
PEX_TX1_C
PEX_TX1_C*
PEX_TX2_C
PEX_TX2_C*
PEX_TX3_C
PEX_TX3_C*
PEX_TX4_C
PEX_TX4_C*
PEX_TX5_C
PEX_TX5_C*
PEX_TX6_C
PEX_TX6_C*
PEX_TX7_C
PEX_TX7_C*
PEX_TX8_C
PEX_TX8_C*
PEX_TX9_C
PEX_TX9_C*
PEX_TX10_C
PEX_TX10_C*
PEX_TX11_C
PEX_TX11_C*
PEX_TX12_C
PEX_TX12_C*
PEX_TX13_C
PEX_TX13_C*
PEX_TX14_C
PEX_TX14_C*
PEX_TX15_C
PEX_TX15_C*
PEX_RX0
PEX_RX0* 1
PEX_RX1
PEX_RX1*
PEX_RX2
PEX_RX2*
PEX_RX3
PEX_RX3*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_RX14
PEX_RX14*
PEX_RX15
PEX_RX15*
PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*
PEX_RST*
PEX_TRST*
PEX_TCLK
PEX_TDI
PEX_TDO
PEX_TMS
JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1PEX_TX4*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
3
1.2V
1.2V
100DIFF
100DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
0.25A
0.10A
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT
600-10393-0004-100 A
p393_a01
whill
DIFFPAIRNV_IMPEDANCE
PEX_REFCLK
PEX_REFCLK
PEX_TX0_C
PEX_TX0_C
PEX_TX1_C
PEX_TX1_C
PEX_TX2_C
PEX_TX2_C
PEX_TX3_C
PEX_TX3_C
PEX_TX4_C
PEX_TX4_C
PEX_TX5_C
PEX_TX5_C
PEX_TX6_C
PEX_TX6_C
PEX_TX7_C
PEX_TX7_C
PEX_TX8_C
PEX_TX8_C
PEX_TX9_C
PEX_TX9_C
PEX_TX10_C
PEX_TX10_C
PEX_TX11_C
PEX_TX11_C
PEX_TX12_C
PEX_TX12_C
PEX_TX13_C
PEX_TX13_C
PEX_TX14_C
PEX_TX14_C
PEX_TX15_C
PEX_TX15_C
PEX_RX0
PEX_RX0
PEX_RX1
PEX_RX1
PEX_RX2
PEX_RX2
PEX_RX3
PEX_RX3
PEX_RX4
PEX_RX4
PEX_RX5
PEX_RX5
PEX_RX6
PEX_RX6
PEX_RX7
PEX_RX7
PEX_RX8
PEX_RX8
PEX_RX9
PEX_RX9
PEX_RX10
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_RX12
PEX_RX13
PEX_RX13
PEX_RX14
PEX_RX14
PEX_RX15
PEX_RX15
PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15
MIN_WIDTHMAX_CURRENTVOLTAGENET
12MIL
12MIL
2 OF 27
28-SEP-2007
27< 2>
Page 3
Page3: MEMORY: GPU Partition A/B
OUT
OUT
OUT
OUT
OUT
BI
3/24 MEM_B
FBB_CMD6
FBB_CMD4
FBB_CMD5
FBB_CMD3
FBB_CMD1
FBB_CMD2
FBB_CMD0
FBB_CMD7
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD19
FBB_CMD18
FBB_CMD17
FBB_CMD16
FBB_CMD14
FBB_CMD15
FBB_CMD13
FBB_CMD12
FBB_CMD11
FBB_CMD9
FBB_CMD10
FBB_CMD8
FBB_CLK1
FBB_CLK0
FBB_CLK0
FBB_CMD28
FBB_CLK1
RFU
RFU
FBB_DEBUG
FBCAL1_PD_VDDQ
FBCAL1_PU_GND
FBB_PLLVDD_NC
FBCAL1_TERM_GND
FBB_PLLGND
FBBD6
FBBD4
FBBD5
FBBD3
FBBD2
FBBD1
FBBD0
FBBD7
FBBD27
FBBD26
FBBD25
FBBD24
FBBD23
FBBD22
FBBD21
FBBD19
FBBD20
FBBD17
FBBD16
FBBD15
FBBD13
FBBD12
FBBD11
FBBD9
FBBD10
FBBD8
FBBD14
FBBD18
FBBD47
FBBD46
FBBD45
FBBD44
FBBD42
FBBD43
FBBD41
FBBD40
FBBD39
FBBD37
FBBD38
FBBD36
FBBD35
FBBD34
FBBD32
FBBD33
FBBD31
FBBD30
FBBD29
FBBD28
FBBD48
FBBDQM2
FBBDQM1
FBBDQM0
FBBD62
FBBD63
FBBD60
FBBD61
FBBD59
FBBD57
FBBD58
FBBD55
FBBD56
FBBD54
FBBD53
FBBD52
FBBD50
FBBD51
FBBD49
FBBDQS_RN6
FBBDQS_WP2
FBBDQS_WP1
FBBDQS_WP0
FBBDQS_RN7
FBBDQS_RN4
FBBDQS_RN5
FBBDQS_RN3
FBBDQS_RN2
FBBDQS_RN1
FBBDQS_RN0
FBBDQM7
FBBDQM6
FBBDQM4
FBBDQM5
FBBDQM3
FBBDQS_WP3
FB_VREF2
FBBDQS_WP7
FBBDQS_WP6
FBBDQS_WP5
FBBDQS_WP4
BI
OUT
OUT
OUT
OUT
OUT
OUTINOUTBIBIBIBI
2/24 MEM_A
FBA_CMD6
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD7
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD19
FBA_CMD18
FBA_CMD17
FBA_CMD16
FBA_CMD14
FBA_CMD15
FBA_CMD13
FBA_CMD12
FBA_CMD11
FBA_CMD9
FBA_CMD10
FBA_CMD8
FBA_CMD22
FBA_CMD21
FBA_CMD20
FBA_CMD28
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
RFU
RFU
FBA_DEBUG
FBCAL0_PU_GND
FBCAL0_TERM_GND
FBCAL0_PD_VDDQ
FBA_PLLAVDD
FBA_DLLAVDD
FBA_PLLGND
FBAD6
FBAD4
FBAD5
FBAD3
FBAD2
FBAD1
FBAD0
FBAD7
FBAD20
FBAD21
FBAD26
FBAD25
FBAD24
FBAD23
FBAD22
FBAD19
FBAD17
FBAD15
FBAD12
FBAD13
FBAD11
FBAD9
FBAD10
FBAD8
FBAD27
FBAD14
FBAD16
FBAD18
FBAD45
FBAD44
FBAD42
FBAD41
FBAD37
FBAD38
FBAD36
FBAD35
FBAD32
FBAD33
FBAD31
FBAD30
FBAD29
FBAD28
FBAD46
FBAD40
FBAD39
FBAD43
FBAD34
FBAD47
FBAD48
FBAD60
FBADQM2
FBADQM1
FBAD61
FBAD58
FBAD57
FBAD55
FBAD56
FBAD54
FBAD53
FBAD52
FBAD51
FBAD50
FBAD49
FBAD59
FBADQM0
FBAD63
FBAD62
FBADQS_WP2
FBADQS_RN7
FBADQS_RN5
FBADQS_RN3
FBADQS_RN2
FBADQM4
FBADQM3
FBADQS_RN6
FBADQS_RN4
FBADQM7
FBADQM6
FBADQM5
FBADQS_RN1
FBADQS_RN0
FBADQS_WP0
FBADQS_WP1
FBADQS_WP3
FBADQS_WP5
FBADQS_WP4
FBADQS_WP7
FBADQS_WP6
FB_VREF1
OUTINOUT
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
G1
G92-300-A1
BGA1148
AH35
AH36
AH34
AJ34
AK36
AJ36
AK34
AL34
AH32
AK33
AJ33
AH33
AL33
AN32
AN33
AN31
AE32
AF30
AF32
AE30
AE31
AC30
AC32
AD30
AG36
AG34
AF36
AD36
AD34
AD35
AE34
AP36
AN35
AM34
AP35
AP34
AP33
AT34
AR34
AM22
AM25
AN26
AN24
AK24
AL22
AK23
AM23
AT32
AT33
AR33
AP31
AR30
AT30
AP30
AT29
AP26
AP27
AT25
AP25
AR28
AP28
AT28
AP29
AK35
AF33
AF34
AN34
AM24
AP32
AR27
AL35
AK32
AG33
AE36
AM36
AN22
AR31
AT27
AL36
AL32
AG32
AE35
AN36
AN23
AT31
AT26
J29
COMMON
CALIBRATION PIN
FB_CALx_PD_VDDQ
FB_CALx_PU_GND
FB_CALx_TERM_GND
VREF RATIO
DDR3
60
40
40
0.7 FBVDDQ
FBA_CMD<0>
AK28
FBA_CMD<1>
AK29
FBA_CMD<2>
AN30
FBA_CMD<3>
AM27
FBA_CMD<4>
AN28
FBA_CMD<5>
AL29
AM30
FBA_CMD<6>
FBA_CMD<7>
AJ31
FBA_CMD<8>
AK31
FBA_CMD<9>
AH31
FBA_CMD<10>
AK25
FBA_CMD<11>
AM26
FBA_CMD<12>
AL31
FBA_CMD<13>
AN29
FBA_CMD<14>
AK27
FBA_CMD<15>
AK26
FBA_CMD<16>
AN27
FBA_CMD<17>
AL25
FBA_CMD<18>
AJ30
FBA_CMD<19>
AM31
FBA_CMD<20>
AH30
FBA_CMD<21>
AL30
FBA_CMD<22>
AH29
FBA_CMD<23>
AL28
FBA_CMD<24>
AH28
FBA_CMD<25>
AM28
SNN_FBA_CMD_26AG30
SNN_FBA_CMD_27
AG28
SNN_FBA_CMD_28
AF28
FBA_CLK0
AH26
FBA_CLK0*
AH27
FBA_CLK1
AJ29
FBA_CLK1*
AJ28
SNN_FBA_RFU0
AJ24
SNN_FBA_RFU1AH24
FBA_DEBUG
AH25
FB_CAL_PD_VDDQ0
J28
FB_CAL_PU_GND0
H28
FB_CAL_TERM_GND0
H29
FBAB_PLLAVDD
AC29
AD29
AE29
GND
Place components as close
as possible to the pad
C702
.1UF
10V
10%
X5R
0402
COMMON
GND
C676
.1UF
10V
10%
X5R
0402
COMMON
GND
FBA_D<63..0>
FBA_DQM<7..0>
FBA_DQS_RN<7..0>
FBA_DQS_WP<7..0>
FBVDD
R616
549
1%
0402
COMMON
R615
1.33K
1%
0402
COMMON
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBA_D<0>
FBA_D<1>
FBA_D<2>
FBA_D<3>
FBA_D<4>
FBA_D<5>
FBA_D<6>
FBA_D<7>
FBA_D<8>
FBA_D<9>
FBA_D<10>
FBA_D<11>
FBA_D<12>
FBA_D<13>
FBA_D<14>
FBA_D<15>
FBA_D<16>
FBA_D<17>
FBA_D<18>
FBA_D<19>
FBA_D<20>
FBA_D<21>
FBA_D<22>
FBA_D<23>
FBA_D<24>
FBA_D<25>
FBA_D<26> AG35
FBA_D<27>
FBA_D<28>
FBA_D<29>
FBA_D<30>
FBA_D<31>
FBA_D<32>
FBA_D<33>
FBA_D<34>
FBA_D<35>
FBA_D<36>
FBA_D<37>
FBA_D<38>
FBA_D<39>
FBA_D<40>
FBA_D<41>
FBA_D<42>
FBA_D<43>
FBA_D<44>
FBA_D<45>
FBA_D<46>
FBA_D<47>
FBA_D<48>
FBA_D<49>
FBA_D<50>
FBA_D<51>
FBA_D<52>
FBA_D<53>
FBA_D<54>
FBA_D<55>
FBA_D<56>
FBA_D<57>
FBA_D<58>
FBA_D<59>
FBA_D<60>
FBA_D<61>
FBA_D<62>
FBA_D<63>
FBA_DQM<0>
FBA_DQM<1> AM33
FBA_DQM<2>
FBA_DQM<3>
FBA_DQM<4>
FBA_DQM<5>
FBA_DQM<6>
FBA_DQM<7>
FBA_DQS_RN<0>
FBA_DQS_RN<1>
FBA_DQS_RN<2>
FBA_DQS_RN<3>
FBA_DQS_RN<4>
FBA_DQS_RN<5>
FBA_DQS_RN<6>
FBA_DQS_RN<7>
FBA_DQS_WP<0>
FBA_DQS_WP<1>
FBA_DQS_WP<2>
FBA_DQS_WP<3>
FBA_DQS_WP<4>
FBA_DQS_WP<5>
FBA_DQS_WP<6>
FBA_DQS_WP<7>
FB_VREF1
9<> 5<>
9> 5<>
9< 5<>
9> 5<>
9<>
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
C708
.1UF
10V
10%
X5R
0402
COMMON
0
1
2
3
4
5
6
7
8
9
FBA_CMD<28..0>
FBVDD
R626
60.4
1%
0402
NO STUFF
5<
5<
5<
5<
9>
9>
9>
9>
9> 5<
136BGA CMD Mapping
ADDR
CMD
A<4>
CMD0
RAS*CMD1
A<5>
CMD2
BA1
CMD3
A<2>
CMD4
A<4>
CMD5
A<3>
CMD6
BA2
CMD7
CS0*
CMD8
A<11>
CMD9
CAS*
CMD10
CMD11 WE*
BA0
CMD12
A<5>
CMD13
A<12>
CMD14
RST
CMD15
A<7>
CMD16
A<10>
CMD17
CKE
CMD18
A<0>
CMD19
A<9>
CMD20
A<6>
CMD21
A<2>
CMD22
A<8>
CMD23
A<3>
CMD24
A<1>
CMD25
A<13>
CMD26
BA2
CMD27
N/A
CMD28
6<> 9<>
9> 6<>
9<>
FBVDD
60.4
9<>
R624
0402
R620
0402
R619
0402
COMMON
1%
40.2
COMMON
1%
40.2
COMMON
1%
GND
1V2
9<
9>
6<>
6<>
9<>
240R@100MHz
LB501
COMMONBEAD_0402
C688
C687
4.7UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0402
COMMON
COMMON
Place these components within
750 mils of the pad
C675
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
MEMORY: GPU Partition A/B
www.vinafix.vn
FBB_D<63..0>
FBB_DQM<7..0>
FBB_DQS_RN<7..0>
FBB_DQS_WP<7..0>
C710
.1UF
10V
10%
X5R
0402
COMMON
GND
FBVDD
GND
R629
549
1%
0402
COMMON
R628
1.33K
1%
0402
COMMON
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBB_D<0>
0
FBB_D<1>
1
FBB_D<2>
2
FBB_D<3>
3
FBB_D<4>
4
FBB_D<5>
5
FBB_D<6>
6
FBB_D<7>
7
FBB_D<8>
8
FBB_D<9>
9
FBB_D<10>
10
FBB_D<11>
11
FBB_D<12>
12
FBB_D<13>
13
FBB_D<14>
14
FBB_D<15>
15
FBB_D<16>
16
FBB_D<17>
17
FBB_D<18>
18
FBB_D<19>
19
FBB_D<20>
20
FBB_D<21>
21
FBB_D<22>
22
FBB_D<23>
23
FBB_D<24>
24
FBB_D<25>
25
FBB_D<26>
26
FBB_D<27>
27
FBB_D<28>
28
FBB_D<29>
29
FBB_D<30>
30
FBB_D<31>
31
FBB_D<32>
32
FBB_D<33>
33
FBB_D<34>
34
FBB_D<35>
35
FBB_D<36>
36
FBB_D<37>
37
FBB_D<38>
38
FBB_D<39>
39
FBB_D<40>
40
FBB_D<41>
41
FBB_D<42>
42
FBB_D<43>
43
FBB_D<44>
44
FBB_D<45>
45
FBB_D<46>
46
FBB_D<47>
47
FBB_D<48>
48
FBB_D<49>
49
FBB_D<50>
50
FBB_D<51>
51
FBB_D<52>
52
FBB_D<53>
53
FBB_D<54>
54
FBB_D<55>
55
FBB_D<56>
56
FBB_D<57>
57
FBB_D<58>
58
FBB_D<59>
59
FBB_D<60>
60
FBB_D<61>
61
FBB_D<62>
62
FBB_D<63>
63
FBB_DQM<0>
FBB_DQM<1>
FBB_DQM<2>
FBB_DQM<3>
FBB_DQM<4>
FBB_DQM<5>
FBB_DQM<6>
FBB_DQM<7>
FBB_DQS_RN<0>
FBB_DQS_RN<1>
FBB_DQS_RN<2>
FBB_DQS_RN<3>
FBB_DQS_RN<4>
FBB_DQS_RN<5>
FBB_DQS_RN<6>
FBB_DQS_RN<7>
FBB_DQS_WP<0>
FBB_DQS_WP<1>
FBB_DQS_WP<2>
FBB_DQS_WP<3>
FBB_DQS_WP<4>
FBB_DQS_WP<5>
FBB_DQS_WP<6>
FBB_DQS_WP<7>
FB_VREF2
G1
G92-300-A1
BGA1148
COMMON
G36
G35
H36
H34
J35
J34
K34 T30
K35
J31
K32
J30
H30
L32
K30
M31
L30
G31
J32
J33
F33
H31
E33
F31
F32
F35
G34
F36
F34
C35
D34
C36
D35
N35
M34
L34
N36
P36
P34
R36
R34
AC33
Y33
Y30
AB30
AA32
AD32
AD33
AA33
T36
R35
T34
U36
W35
U34
V34
W36
AC36
AA36
AC34
AB34
AA35
Y34
Y36
W34
J36
M32
H33
E34
N34
Y32
T35
AA34
L36
K33
G32
E36
M36
AB32
V35
AB35
K36
L33
G33
D36
M35
AB31
V36
AB36
J27
FBB_CMD<0>
P33
FBB_CMD<1>
N33
FBB_CMD<2>
R31
FBB_CMD<3>
U33
FBB_CMD<4>
V30
FBB_CMD<5>
T33
FBB_CMD<6>
FBB_CMD<7>
N32
FBB_CMD<8>
R32
FBB_CMD<9>
P32
FBB_CMD<10>
U32
FBB_CMD<11>
U30
FBB_CMD<12>
P30
FBB_CMD<13>
V31
FBB_CMD<14>
T28
FBB_CMD<15>
W30
FBB_CMD<16>
V32
FBB_CMD<17>
T32
FBB_CMD<18>
N30
FBB_CMD<19>
P28
FBB_CMD<20>
P29
FBB_CMD<21>
U29
FBB_CMD<22>
N28
FBB_CMD<23>
R30
FBB_CMD<24>
M30
FBB_CMD<25>
T29
SNN_FBB_CMD_26
N29
SNN_FBB_CMD_27
AA30
SNN_FBB_CMD_28
Y29
FBB_CLK0
M28
FBB_CLK0*
L28
FBB_CLK1
W31
FBB_CLK1*
W32
SNN_FBB_RFU0
R28
SNN_FBB_RFU1
K29
FBB_DEBUG
C34
FB_CAL_PD_VDDQ1
H27
FB_CAL_PU_GND1
H26
FB_CAL_TERM_GND1
J26
SNN_FBB_PLLVDD_NC
AB28
AC28
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBB_CMD<28..0>
6<
6<
6<
6<
FBVDD
R617
60.4
1%
0402
NO STUFF
9>
9>
9>
9>
6< 9>
9<>
60.4
R630
COMMON
0402
1%
40.2
R633
COMMON
0402
1%
40.2
R634
COMMON
0402
1%
600-10393-0004-100 A
p393_a01
whill
FBVDD
GND
3 OF 27
28-SEP-2007
Page 4
Page4: MEMORY: GPU Partition C/D
OUT
OUT
OUT
OUT
OUT
BI
5/24 MEM_D
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD5
FBD_CMD4
FBD_CMD6
FBD_CMD7
FBD_CMD21
FBD_CMD20
FBD_CMD19
FBD_CMD8
FBD_CMD10
FBD_CMD9
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD23
FBD_CMD22
FBD_CMD27
FBD_CMD26
FBD_CMD25
FBD_CMD24
FBD_CLK1
FBD_CLK1
FBD_CLK0
FBD_CLK0
FBD_CMD28
RFU
RFU
FBD_DEBUG
FBD_PLLVDD_NC
FBD_PLLGND
FBDD0
FBDD1
FBDD2
FBDD3
FBDD4
FBDD5
FBDD6
FBDD7
FBDD9
FBDD21
FBDD25
FBDD8
FBDD10
FBDD11
FBDD12
FBDD13
FBDD15
FBDD14
FBDD16
FBDD17
FBDD18
FBDD20
FBDD19
FBDD22
FBDD23
FBDD24
FBDD26
FBDD27
FBDD28
FBDD29
FBDD30
FBDD31
FBDD33
FBDD32
FBDD36
FBDD35
FBDD38
FBDD37
FBDD40
FBDD41
FBDD39
FBDD42
FBDD43
FBDD44
FBDD45
FBDD46
FBDD47
FBDD34
FBDD48
FBDD57
FBDD58
FBDD59
FBDD60
FBDD49
FBDD50
FBDD51
FBDD52
FBDD53
FBDD54
FBDD56
FBDD55
FBDD61
FBDD62
FBDD63
FBDDQM0
FBDDQM2
FBDDQM1
FBDDQM3
FBDDQM5
FBDDQM4
FBDDQM6
FBDDQM7
FBDDQS_RN0
FBDDQS_RN1
FBDDQS_RN2
FBDDQS_RN3
FBDDQS_RN6
FBDDQS_RN4
FBDDQS_RN7
FBDDQS_WP0
FBDDQS_WP1
FBDDQS_WP2
FBDDQS_RN5
FBDDQS_WP3
FBDDQS_WP4
FBDDQS_WP5
FBDDQS_WP6
FBDDQS_WP7
BI
OUT
OUT
OUT
OUT
OUT
OUTINOUTBIBI
BI
4/24 MEM_C
FBC_CMD6
FBC_CMD5
FBC_CMD4
FBC_CMD3
FBC_CMD2
FBC_CMD1
FBC_CMD0
FBC_CMD7
FBC_CMD24
FBC_CMD25
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD20
FBC_CMD19
FBC_CMD18
FBC_CMD17
FBC_CMD16
FBC_CMD15
FBC_CMD14
FBC_CMD13
FBC_CMD12
FBC_CMD11
FBC_CMD10
FBC_CMD9
FBC_CMD8
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CLK1
FBC_CLK1
FBC_CLK0
FBC_CLK0
RFU
RFU
FBC_DEBUG
FBC_DLLAVDD
FBC_PLLAVDD
FBC_PLLVDD_NC
FBC_PLLGND
FBCD5
FBCD3
FBCD1
FBCD6
FBCD4
FBCD2
FBCD0
FBCD7
FBCD16
FBCD19
FBCD27
FBCD26
FBCD25
FBCD22
FBCD23
FBCD20
FBCD13
FBCD9
FBCD8
FBCD14
FBCD15
FBCD17
FBCD12
FBCD24
FBCD21
FBCD18
FBCD11
FBCD10
FBCD29
FBCD28
FBCD33
FBCD35
FBCD47
FBCD45
FBCD46
FBCD44
FBCD43
FBCD42
FBCD39
FBCD41
FBCD40
FBCD37
FBCD32
FBCD30
FBCD36
FBCD34
FBCD31
FBCD38
FBCD48
FBCD60
FBCD63
FBCDQM0
FBCDQM2
FBCDQM1
FBCD62
FBCD61
FBCD57
FBCD58
FBCD59
FBCD55
FBCD56
FBCD53
FBCD54
FBCD51
FBCD50
FBCD49
FBCD52
FBCDQM5
FBCDQM4
FBCDQM6
FBCDQM7
FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7
FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_RN3
FBCDQM3
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7
OUTINOUT
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
G1
G92-300-A1
BGA1148
C18
C17
A17
B16
C14
A16FBC_D<5>
C15
A14
A18
A19
B19
B18
B21
C19
B22
C21
E15
D16
D17
G16
E16
E14
G13
D13
A22
C22
A23
A24
C24
C25
B24
C28
B27
C27
B28
C29
A29
B30
A30
E31
E28
D28
F29
F30
D33
D32
D31
G27
F25
G26
D26
G29
G28
E27
F28
A34
C32
B34
C33
C31
B31
A31
C30
C16
G14
C26
A28
D29
D27
B33
B15
A21
D14
B25
A27
E30
E25
A33
A15
A20
E13
A25
A26
D30
E26
A32
COMMON
H20
E18
E20
D23
G24
D24
G23
D20
E22
J21
E21
G20
F22
H21
E17
E19
D21
E23
F19
E24
G21
G19
G25
G18
G22
F15
G15
H17
J16
J24
H23
H24
H16
H13
J11
J12
J13
GND
FBC_CMD<0>F18
FBC_CMD<1>
FBC_CMD<2>
FBC_CMD<3>
FBC_CMD<4>
FBC_CMD<5>
FBC_CMD<6>
FBC_CMD<7>
FBC_CMD<8>
FBC_CMD<9>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<12>
FBC_CMD<13>
FBC_CMD<14>
FBC_CMD<15>
FBC_CMD<16>
FBC_CMD<17>
FBC_CMD<18>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<21>
FBC_CMD<22>
FBC_CMD<23>
FBC_CMD<24>
FBC_CMD<25>
SNN_FBC_CMD_26G17
SNN_FBC_CMD_27
SNN_FBC_CMD_28
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
SNN_FBC_RFU0
SNN_FBC_RFU1J25
FBC_DEBUG
SNN_FBC_PLLVDD_NC
FBCD_PLLAVDD
C832
.1UF
10V
10%
X5R
0402
COMMON
as possible to the pad
FBC_D<63..0>
FBC_DQM<7..0>
FBC_DQS_RN<7..0>
FBC_DQS_WP<7..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBC_D<0>
FBC_D<1>
FBC_D<2>
FBC_D<3>
FBC_D<4>
FBC_D<6>
FBC_D<7>
FBC_D<8>
FBC_D<9>
FBC_D<10>
FBC_D<11>
FBC_D<12>
FBC_D<13>
FBC_D<14>
FBC_D<15>
FBC_D<16>
FBC_D<17>
FBC_D<18>
FBC_D<19>
FBC_D<20>
FBC_D<21>
FBC_D<22>
FBC_D<23>
FBC_D<24>
FBC_D<25>
FBC_D<26> C23
FBC_D<27>
FBC_D<28>
FBC_D<29>
FBC_D<30>
FBC_D<31>
FBC_D<32>
FBC_D<33>
FBC_D<34>
FBC_D<35>
FBC_D<36>
FBC_D<37>
FBC_D<38>
FBC_D<39>
FBC_D<40>
FBC_D<41>
FBC_D<42>
FBC_D<43>
FBC_D<44>
FBC_D<45>
FBC_D<46>
FBC_D<47>
FBC_D<48>
FBC_D<49>
FBC_D<50>
FBC_D<51>
FBC_D<52>
FBC_D<53>
FBC_D<54>
FBC_D<55>
FBC_D<56>
FBC_D<57>
FBC_D<58>
FBC_D<59>
FBC_D<60>
FBC_D<61>
FBC_D<62>
FBC_D<63>
FBC_DQM<0>
FBC_DQM<1> C20
FBC_DQM<2>
FBC_DQM<3>
FBC_DQM<4>
FBC_DQM<5>
FBC_DQM<6>
FBC_DQM<7>
FBC_DQS_RN<0>
FBC_DQS_RN<1>
FBC_DQS_RN<2>
FBC_DQS_RN<3>
FBC_DQS_RN<4>
FBC_DQS_RN<5>
FBC_DQS_RN<6>
FBC_DQS_RN<7>
FBC_DQS_WP<0>
FBC_DQS_WP<1>
FBC_DQS_WP<2>
FBC_DQS_WP<3>
FBC_DQS_WP<4>
FBC_DQS_WP<5>
FBC_DQS_WP<6>
FBC_DQS_WP<7>
9<> 7<>
9> 7<>
9< 7<>
9> 7<>
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBVDD
C822
.1UF
10V
10%
X5R
0402
COMMON
FBC_CMD<28..0>
7<
7<
7<
7<
R638
60.4
1%
0402
NO STUFF
9>
9>
9>
9>
9> 7<
136BGA CMD Mapping
ADDR
CMD
A<4>CMD0
RAS*CMD1
A<5>
CMD2
BA1
CMD3
A<2>
CMD4
A<4>
CMD5
A<3>
CMD6
BA2CMD7
CS0*
CMD8
A<11>
CMD9
CAS*
CMD10
CMD11 WE*
BA0
CMD12
A<5>
CMD13
A<12>
CMD14
RST
CMD15
A<7>
CMD16
A<10>
CMD17
CKE
CMD18
A<0>
CMD19
A<9>
CMD20
A<6>
CMD21
A<2>
CMD22
A<8>
CMD23
A<3>
CMD24
A<1>
CMD25
A<13>
CMD26
BA2
CMD27
N/A
CMD28
8<> 9<>
9> 8<>
9<>
8<>
9<
8<>
9<>
C841
1UF
6.3V
10%
X5R
0402
COMMON
Place these components withinPlace components as close
750 mils of the pad
240R@100MHz
LB503
BEAD_0402
C855
4.7UF
6.3V
10%
X5R
0603
COMMON
COMMON
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
MEMORY: GPU Partition C/D
9>
1V2
C852
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
www.vinafix.vn
FBD_D<63..0>
FBD_DQM<7..0>
FBD_DQS_RN<7..0>
FBD_DQS_WP<7..0>
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBD_D<0>
0
FBD_D<1>
1
FBD_D<2>
2
FBD_D<3>
3
FBD_D<4>
4
FBD_D<5>
5
FBD_D<6>
6
FBD_D<7>
7
FBD_D<8>
8
FBD_D<9>
9
FBD_D<10>
10
FBD_D<11>
11
FBD_D<12>
12
FBD_D<13>
13
FBD_D<14>
14
FBD_D<15>
15
FBD_D<16>
16
FBD_D<17>
17
FBD_D<18>
18
FBD_D<19>
19
FBD_D<20>
20
FBD_D<21>
21
FBD_D<22>
22
FBD_D<23>
23
FBD_D<24>
24
FBD_D<25>
25
FBD_D<26>
26
FBD_D<27>
27
FBD_D<28>
28
FBD_D<29>
29
FBD_D<30>
30
FBD_D<31>
31
FBD_D<32>
32
FBD_D<33>
33
FBD_D<34>
34
FBD_D<35>
35
FBD_D<36>
36
FBD_D<37>
37
FBD_D<38>
38
FBD_D<39>
39
FBD_D<40>
40
FBD_D<41>
41
FBD_D<42>
42
FBD_D<43>
43
FBD_D<44>
44
FBD_D<45>
45
FBD_D<46>
46
FBD_D<47>
47
FBD_D<48>
48
FBD_D<49>
49
FBD_D<50>
50
FBD_D<51>
51
FBD_D<52>
52
FBD_D<53>
53
FBD_D<54>
54
FBD_D<55>
55
FBD_D<56>
56
FBD_D<57>
57
FBD_D<58>
58
FBD_D<59>
59
FBD_D<60>
60
FBD_D<61>
61
FBD_D<62>
62
FBD_D<63>
63
FBD_DQM<0>
FBD_DQM<1>
FBD_DQM<2>
FBD_DQM<3>
FBD_DQM<4>
FBD_DQM<5>
FBD_DQM<6>
FBD_DQM<7>
FBD_DQS_RN<0>
FBD_DQS_RN<1>
FBD_DQS_RN<2>
FBD_DQS_RN<3>
FBD_DQS_RN<4>
FBD_DQS_RN<5>
FBD_DQS_RN<6>
FBD_DQS_RN<7>
FBD_DQS_WP<0>
FBD_DQS_WP<1>
FBD_DQS_WP<2>
FBD_DQS_WP<3>
FBD_DQS_WP<4>
FBD_DQS_WP<5>
FBD_DQS_WP<6>
FBD_DQS_WP<7>
G1
G92-300-A1
BGA1148
COMMON
H3
J3
J1
J2
M3
K3
L3 F8
M1
H1
G3
G1
G2
F3
E1
D1
D2
P4
N7
M7
N5
P5
R7
T7
P7
C1
C5
C2
B4
A3
B3
C4
C3
A8
C6
C7
A7
C8
C9
A9
B9
E12
E9
F9
G10
D10
G12
F12
D11
F4
E4
D4
D5
D8
E7
D7
D9
B13
C11
A13
C13
A11
A10
B10
C10
K2
E3
N4
D3
B7
G11
F5
C12
K1
F2
R6
A4
B6
E10
E6
A12
L1
F1
R5
A5
A6
E11
D6
B12
FBD_CMD<0>
M6
FBD_CMD<1>
G5
FBD_CMD<2>
L7
FBD_CMD<3>
K5
FBD_CMD<4>
J10
FBD_CMD<5>
G8
FBD_CMD<6>
FBD_CMD<7>
G6
FBD_CMD<8>
H6
FBD_CMD<9>
F6
FBD_CMD<10>
K8
FBD_CMD<11>
L5
FBD_CMD<12>
H4
FBD_CMD<13>
G4
FBD_CMD<14>
K9
FBD_CMD<15>
L4
FBD_CMD<16>
K4
FBD_CMD<17>
K7
FBD_CMD<18>
G7
FBD_CMD<19>
J4
FBD_CMD<20>
F7
FBD_CMD<21>
J5
FBD_CMD<22>
J6
FBD_CMD<23>
H7
FBD_CMD<24>
L8
FBD_CMD<25>
J7
SNN_FBD_CMD_26
M5
SNN_FBD_CMD_27
H9
SNN_FBD_CMD_28
G9
FBD_CLK0
L9
FBD_CLK0*
M9
FBD_CLK1
J9
FBD_CLK1*
J8
SNN_FBD_RFU0
H10
SNN_FBD_RFU1
L11
FBD_DEBUG
N8
SNN_FBD_PLLVDD_NC
H11
H12
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBVDD
FBD_CMD<28..0>
9>
8<
9>
8<
9>
8<
9>
8<
R645
60.4
1%
0402
NO STUFF
8< 9>
9<>
600-10393-0004-100 A
p393_a01
whill
4 OF 27
28-SEP-2007
Page 5
Page5: FBA Partition
OUT
OUT
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
ININININOUT
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<8>
A<9>
A<10>
A<11>
CKE
RST
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16A<7>
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
3>
9>
3>
9>
FBVDD
R592
121
1%
0402
NO STUFF
FBA_CLK0_MIDPT
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
3> 5< 9>
R588 R589
243
1%
0402
COMMON
GND
FBA_CMD<28..0>
243
1%
0402
COMMON
C615
.01UF
25V
10%
X7R
0402
COMMON
9<>
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
14
15
FBVDD
R604
10K
5%
0402
COMMON
GND
C146
.047UF
16V
10%
X7R
0402
COMMON
FBA_CMD<1>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<8>
FBA_CMD<19>
FBA_CMD<25>
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
FBA_CMD<21>
FBA_CMD<16>
FBA_CMD<23>
FBA_CMD<20>
FBA_CMD<17>
FBA_CMD<9>
FBA_CMD<12>
FBA_CMD<3>
FBA_CMD<7>
FBA_CMD<18>
FBA_CLK0
FBA_CLK0*
SNN_FBA_NC0
FBA_CMD<14>
GND
FBA_CMD<15>
GND
FBA_ZQ0
R585
10K
5%
0402
COMMON
GND
C132
.047UF
16V
10%
X7R
0402
COMMON
R115
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
K12
J12
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
K1
J1
1%
1%
1%
1%
1%
1%
1%
1%
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
R112
549
0402
COMMON
R110
1.33K
04020402
COMMON
FBVDD
1%
1%
GND
FBVDD
R1
R2
C133
.1UF
10V
X5R
0402
COMMON
9<>
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBA_VREF0
FBA_VREF2
FBVDD
GND
GND
FBVDD
R111
549
1%
0402
COMMON
R109
1.33K
1%
0402 0402
COMMON
GND
136BGA CMD Mapping
ADDR 136MAP
CMD1
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD0
0A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
CMD23A<8>
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15
RST
FBVDD
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
FBVDD
R120
549
R1
9<>
C131
.1UF
R2
10V
X5R
0402
COMMON
0402
COMMON
R123
1.33K
COMMON
R1
1%
R2
1%
GND
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
R593
121
1%
0402
NO STUFF
C149
.1UF
10V
10%10%
X5R
0402
COMMON
3>
9>
3>
9>
FBA_CLK1_MIDPT
9<>
R602
243
0402
COMMON
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
R116
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
K12
J12
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
K1
J1
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBVDD
R601
243
0402
COMMON
C616
.01UF
25V
10%
X7R
0402
COMMON
1%
FBA_CMD<28..0>
FBVDD
9<>
FBA_CMD<7>
7
FBA_CMD<8>
8
FBA_CMD<18>
18
FBA_CMD<10>
10
FBA_CMD<5>
5
FBA_CMD<13>
13
FBA_CMD<21>
21
FBA_CMD<20>
20
FBA_CMD<19>
19
FBA_CMD<25>
25
FBA_CMD<4>
4
FBA_CMD<9>
9
FBA_CMD<17>
17
FBA_CMD<6>
6
FBA_CMD<23>
23
FBA_CMD<16>
16
FBA_CMD<3>
3
FBA_CMD<12>
12
FBA_CMD<1>
1
FBA_CMD<11>
11
FBA_CLK1
FBA_CLK1*
SNN_FBA_NC1
FBA_CMD<14>
14
GND
FBA_CMD<15>
15
FBA_ZQ1
3> 5< 9>
1%
GND
GND
FBVDD
C134
.047UF
16V
10%
X7R
0402
COMMON
C147
.047UF
16V
10%
X7R
0402
COMMON
GND
FBA_VREF1
FBA_VREF3
FBVDD
FBVDD
GND
GND
R119
549
0402
COMMON
R122
1.33K
COMMON
FBA_CMD<4>
FBA_CMD<6>
FBA_CMD<5>
FBA_CMD<13>
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
R1
1%
C148
.1UF
R2
1%
10V
10% 10%
X5R
0402
COMMON
GND
9<>
R597
0402
R598
0402
R591
0402
R587
0402
R599
0402
R595
0402
R590
0402
R579
0402
9>
9<
9>
3<>
3>
3<
3>
FBA_D<63..0>
FBA_DQM<7..0>
FBA_DQS_RN<7..0>
FBA_DQS_WP<7..0>
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
E11
B11
F11
G10
C10
C11
B10
F10
E10
D10
D11
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M11
N11
M10
T10
R11
T11
R10
N10
P10
P11FBA_DQS_WP<7>
F2
G3
F3
C2
E2
C3
B3
B2
E3
D3
D2
B3
C3
F3
C2
F2
E2
B2
G3
E3
D3
D2
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBA_D<24>
24
FBA_D<25>
25
FBA_D<26>
26
FBA_D<27>
27
FBA_D<28>
28
FBA_D<29>
29
FBA_D<30>
30
FBA_D<31>
31
FBA_DQM<3>
FBA_DQS_RN<3>
FBA_DQS_WP<3>
FBA_D<56>
56
FBA_D<57>
57
FBA_D<58>
58
FBA_D<59> L10
59
FBA_D<60>
60
FBA_D<61>
61
FBA_D<62>
62
FBA_D<63>
63
FBA_DQM<7>
FBA_DQS_RN<7>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FBA Partition
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBA_D<0>
0
FBA_D<1>
1
FBA_D<2>
2
FBA_D<3>
3
FBA_D<4>
4
FBA_DQM<0>
0
FBA_DQM<1>
1
FBA_DQM<2>
2
FBA_DQM<3>
3
FBA_DQM<4>
4
FBA_DQM<5>
5
FBA_DQM<6>
6
FBA_DQM<7>
7
FBA_DQS_RN<0>
0
FBA_DQS_RN<1>
1
FBA_DQS_RN<2>
2
FBA_DQS_RN<3>
3
FBA_DQS_RN<4>
4
FBA_DQS_RN<5>
5
FBA_DQS_RN<6>
6
FBA_DQS_RN<7>
7
FBA_DQS_WP<0>
0
FBA_DQS_WP<1>
1
FBA_DQS_WP<2>
2
FBA_DQS_WP<3>
3
FBA_DQS_WP<4>
4
FBA_DQS_WP<5>
5
FBA_DQS_WP<6>
6
FBA_DQS_WP<7>
7
5
6
7
32
33
34
35
36
37
38
39
FBA_D<5>
FBA_D<6>
FBA_D<7>
FBA_DQM<0>
FBA_DQS_RN<0>
FBA_DQS_WP<0>
FBA_D<32>
FBA_D<33>
FBA_D<34>
FBA_D<35>
FBA_D<36>
FBA_D<37>
FBA_D<38>
FBA_D<39>
FBA_DQM<4>
FBA_DQS_RN<4>
FBA_DQS_WP<4>
L10
T10
M10
R11
T11
R10
N11
M11
N10
P10
P11
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L3
R3
T3
M3
M2
N2
T2
R2
N3
P3
P2
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBA_D<8>
FBA_D<9>
FBA_D<10>
FBA_D<11>
FBA_D<12>
FBA_D<13>
FBA_D<14>
FBA_D<15>
FBA_DQM<1>
FBA_DQS_RN<1>
FBA_DQS_WP<1>
FBA_D<40>
FBA_D<41>
FBA_D<42>
FBA_D<43>
FBA_D<44>
FBA_D<45>
FBA_D<46>
FBA_D<47>
FBA_DQM<5>
FBA_DQS_RN<5>
FBA_DQS_WP<5>
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
R3
T2
R2
N2
T3
M3
M2
L3
N3
P3
P2
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
B10
E11
F11
C10
C11
G10
F10
B11
E10
D10
D11
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBA_D<16>
FBA_D<17>
FBA_D<18>
FBA_D<19>
FBA_D<20>
FBA_D<21>
FBA_D<22>
FBA_D<23>
FBA_DQM<2>
FBA_DQS_RN<2>
FBA_DQS_WP<2>
FBA_D<48>
FBA_D<49>
FBA_D<50>
FBA_D<51>
FBA_D<52>
FBA_D<53>
FBA_D<54>
FBA_D<55>
FBA_DQM<6>
FBA_DQS_RN<6>
FBA_DQS_WP<6>
www.vinafix.vn
9<>
Decoupling
for FBA Lo
Decoupling
for FBA Hi
FBVDD
C624
.1UF
10V
10%
X5R
0402
COMMON
C647
1UF
16V
10%
X5R
0603
COMMON
C576
4.7UF
6.3V
10%
X5R
0805
COMMON
C595
.1UF
10V
10%
X5R
0402
COMMON
C646
1UF
16V
10%
X5R
0603
COMMON
C623
4.7UF
6.3V
10%
X5R
0805
COMMON
C608
.1UF
10V
10%
X5R
0402
COMMON
C587
1UF
16V
10%
X5R
0603
COMMON
C632
4.7UF
6.3V
10%
X5R
0805
COMMON
C629
.1UF
10V
10%
X5R
0402
COMMON
C617
1UF
16V
10%
X5R
0603
COMMON
C577
4.7UF
6.3V
10%
X5R
0805
COMMON
C597
C598
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C641
C614
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603 0603
COMMON
COMMON
C574
4.7UF
6.3V
10%
X5R
0805
COMMON
C600
C637
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
04020402
COMMON
COMMON
C581C642
1UF
1UF
16V
16V
10%
10%
X5R
X5R
06030603
COMMON
COMMON
C579
4.7UF
6.3V
10%
X5R
0805
COMMON
C636
.1UF
10V
10%
X5R
0402
Place 1uF caps at
center of memory
C585
.1UF
10V
10%
X5R
0402
NO STUFF
C601
.1UF
10V
10%
X5R
0402
COMMON
Place 1uF caps at
center of memory
C633
.1UF
10V
10%
X5R
0402
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMONCOMMON
C580
C584
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
C627
C609
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C638
C589
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFFNO STUFF
600-10393-0004-100 A
p393_a01
whill
C599
C625
C630
.1UF
10V
10%
X5R
0402
COMMON
C586
.1UF
10V
10%
X5R
0402
NO STUFF
C628
.1UF
10V
10%
X5R
0402
COMMON
C582
.1UF
10V
10%
X5R
0402
NO STUFF
C631
.1UF
10V
10%
X5R
0402
COMMON
C635
.1UF
10V
10%
X5R
0402
NO STUFF
C596
.1UF
10V
10%
X5R
0402
COMMON
C588
.1UF
10V
10%
X5R
0402
NO STUFF
C602
.1UF
10V
10%
X5R
0402
COMMON
C640
.1UF
10V
10%
X5R
0402
NO STUFF
C626
.1UF
10V
10%
X5R
0402
COMMON
C583
.1UF
10V
10%
X5R
0402
NO STUFF
5 OF 27
28-SEP-2007
GND
GND
GND
GND
GND
GND
Page 6
R605
OUT
OUT
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
ININININOUT
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
0402
R603
0402
R594
0402
R584
0402
R614
0402
R610
0402
R612
0402
R607
0402
COMMON
1.33K
COMMON
R114
549
0402
R113
04020402
1%
1%
1%
1%
1%
1%
1%
1%
FBVDD
1%
1%
GND
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
R1
R2
FBVDD
C136
.1UF
10V
X5R
0402
COMMON
9<>
Page6: FBB Partition
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6> CMD21
A<7>
A<8>
A<9>
A<10>
A<11>
CKE
RST
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD16
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
FBVDD
R613
121
1%
0402
NO STUFF
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
3> 9>
3> 9>
R609
COMMON
FBB_CLK0_MIDPT
243
0402
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
R104
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
VERSION=BGA136
CHANGED
R611
243
0402
COMMON
C659
.01UF
25V
10%
X7R
0402
COMMON
FBB_CMD<28..0>
1%
9<>
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
14
15
R608
10K
5%
0402
COMMON
FBB_CMD<1>
FBB_CMD<10>
FBB_CMD<11>
FBB_CMD<8>
FBB_CMD<19>
FBB_CMD<25>
FBB_CMD<22>
FBB_CMD<24>
FBB_CMD<0>
FBB_CMD<2>
FBB_CMD<21>
FBB_CMD<16>
FBB_CMD<23>
FBB_CMD<20>
FBB_CMD<17>
FBB_CMD<9>
FBB_CMD<12>
FBB_CMD<3>
FBB_CMD<7>
FBB_CMD<18>
FBB_CLK0
FBB_CLK0*
SNN_FBB_NC0
FBB_CMD<14>
GND
FBB_CMD<15>
GND
FBB_ZQ0
R606
10K
5%
0402
COMMON
6< 3> 9>
1%
GND
GND
FBVDD
C109
.047UF
16V
10%
X7R
0402
COMMON
C129
.047UF
16V
10%
X7R
0402
COMMON
K12
J12
K1
J1
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBB_VREF0
FBB_VREF2
FBVDD
GND
GND
FBVDD
R105
549
1%
0402
COMMON
R106
1.33K
1%
0402 0402
COMMON
GND
GND
136BGA CMD Mapping
136MAPADDR
CMD1
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD0
0A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
A<8> CMD23
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15RST
FBVDD
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
FBVDD
R107
549
R1
9<>
C108
.1UF
R2
10V
X5R
0402
COMMON
0402
COMMON
R108
1.33K
COMMON
R1
1%
R2
1%
GND
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
9>
R586
121
1%
0402
NO STUFF
FBB_CLK1_MIDPT
C128
.1UF
10V
10%10%
X5R
0402
COMMON
3> 9>
3>
R596
243
0402
COMMON
3> 6< 9>
1%
9<>
GND
R600
243
0402
COMMON
C610
.01UF
25V
10%
X7R
0402
COMMON
1%
FBB_CMD<28..0>
FBVDD
9<>
7
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
12
1
11
14
15
FBVDD
GND
C130
.047UF
16V
10%
X7R
0402
COMMON
FBB_CMD<7>
FBB_CMD<8>
FBB_CMD<18>
FBB_CMD<10>
FBB_CMD<5>
FBB_CMD<13>
FBB_CMD<21>
FBB_CMD<20>
FBB_CMD<19>
FBB_CMD<25>
FBB_CMD<4>
FBB_CMD<9>
FBB_CMD<17>
FBB_CMD<6>
FBB_CMD<23>
FBB_CMD<16>
FBB_CMD<3>
FBB_CMD<12>
FBB_CMD<1>
FBB_CMD<11>
FBB_CLK1
FBB_CLK1*
SNN_FBB_NC1
FBB_CMD<14>
GND
FBB_CMD<15>
FBB_ZQ1
GND
R121
243
1%
0402
COMMON
C141
.047UF
16V
10%
X7R
0402
COMMON
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBB_VREF1
FBB_VREF3
FBVDD
FBVDD
GND
GND
R118
549
0402
COMMON
R117
1.33K
COMMON
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
R1
1%
C144
.1UF
R2
1%
10V
10% 10%
X5R
0402
COMMON
GND
FBB_CMD<4>
FBB_CMD<6>
FBB_CMD<5>
FBB_CMD<13>
FBB_CMD<22>
FBB_CMD<24>
FBB_CMD<0>
FBB_CMD<2>
9<>
9<>
3<>
3> 9>
3< 9<
3> 9>
FBB_D<63..0>
FBB_DQM<7..0>
FBB_DQS_RN<7..0>
FBB_DQS_WP<7..0>
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBB_D<0>
0
FBB_D<1>
1
FBB_D<2>
2
FBB_D<3>
3
FBB_D<4>
4
FBB_DQM<0>
0
FBB_DQM<1>
1
FBB_DQM<2>
2
FBB_DQM<3>
3
FBB_DQM<4>
4
FBB_DQM<5>
5
FBB_DQM<6>
6
FBB_DQM<7>
7
FBB_DQS_RN<0>
0
FBB_DQS_RN<1>
1
FBB_DQS_RN<2>
2
FBB_DQS_RN<3>
3
FBB_DQS_RN<4>
4
FBB_DQS_RN<5>
5
FBB_DQS_RN<6>
6
FBB_DQS_RN<7>
7
FBB_DQS_WP<0>
0
FBB_DQS_WP<1>
1
FBB_DQS_WP<2>
2
FBB_DQS_WP<3>
3
FBB_DQS_WP<4>
4
FBB_DQS_WP<5>
5
FBB_DQS_WP<6>
6
FBB_DQS_WP<7>
7
5
6
7
32
33
34
35
36
37
38
39
FBB_D<5>
FBB_D<6>
FBB_D<7>
FBB_DQS_RN<0>
FBB_DQS_WP<0>
FBB_D<32>
FBB_D<33>
FBB_D<34>
FBB_D<35>
FBB_D<36>
FBB_D<37>
FBB_D<38>
FBB_D<39>
FBB_DQM<4>
FBB_DQS_RN<4>
FBB_DQS_WP<4>
L10
R10
M10
R11
T11
T10
M11
N11
N10FBB_DQM<0>
P10
P11
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L3
R3
T3
M2
M3
T2
R2
N2
N3
P3
P2
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBB_D<8>
FBB_D<9>
FBB_D<10>
FBB_D<11>
FBB_D<12>
FBB_D<13>
FBB_D<14>
FBB_D<15>
FBB_DQM<1>
FBB_DQS_RN<1>
FBB_DQS_WP<1>
FBB_D<40>
FBB_D<41>
FBB_D<42>
FBB_D<43>
FBB_D<44>
FBB_D<45>
FBB_D<46>
FBB_D<47>
FBB_DQM<5>
FBB_DQS_RN<5>
FBB_DQS_WP<5>
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M2
T3
R2
N2
R3
T2
M3
L3
N3
P3
P2
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
F10
E11
F11
B10
B11
C10
G10
C11
E10
D10
D11
FBB_D<16>
16
FBB_D<17>
17
FBB_D<18>
18
FBB_D<19>
19
FBB_D<20>
20
FBB_D<21>
21
FBB_D<22>
22
FBB_D<23>
23
FBB_DQM<2>
FBB_DQS_RN<2>
FBB_DQS_WP<2>
FBB_D<48>
48
FBB_D<49>
49
FBB_D<50> T10
50
FBB_D<51>
51
FBB_D<52>
52
FBB_D<53>
53
FBB_D<54>
54
FBB_D<55>
55
FBB_DQM<6>
FBB_DQS_RN<6>
FBB_DQS_WP<6>
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
G3
C3
B3
E2
F3
C2
B2
F2
E3
D3
D2
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
R11
R10
N11
M10
T11
M11
L10
N10
P10
P11
FBB_D<24>
24
FBB_D<25>
25
FBB_D<26>
26
FBB_D<27>
27
FBB_D<28>
28
FBB_D<29>
29
FBB_D<30>
30
FBB_D<31>
31
FBB_DQM<3>
FBB_DQS_RN<3>
FBB_DQS_WP<3>
FBB_D<56>
56
FBB_D<57>
57
FBB_D<58>
58
FBB_D<59>
59
FBB_D<60>
60
FBB_D<61>
61
FBB_D<62>
62
FBB_D<63>
63
FBB_DQM<7>
FBB_DQS_RN<7>
FBB_DQS_WP<7>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FBB Partition
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
E11
B11
F11
C11
B10
C10
G10
F10
E10
D10
D11
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
E2
C2
G3
F2
B3
F3
B2
C3
E3
D3
D2
www.vinafix.vn
Decoupling
for FBB Lo
Decoupling
for FBB Hi
FBVDD
C666
.1UF
10V
10%
X5R
0402
COMMON
C645
1UF
16V
10%
X5R
0603
COMMON
C672
4.7UF
6.3V
10%
X5R
0805
COMMON
C590
.1UF
10V
10%
X5R
0402
COMMON
C591
1UF
16V
10%
X5R
0603
COMMON
C572
4.7UF
6.3V
10%
X5R
COMMON
C656
.1UF
10V
10%
X5R
0402
COMMON
C665
1UF
16V
10%
X5R
0603
COMMON
C644
4.7UF
6.3V
10%
X5R
0805
COMMON
C618
.1UF
10V
10%
X5R
0402
COMMON
C649
1UF
16V
10%
X5R
0603
COMMON
C605
4.7UF
6.3V
10%
X5R
08050805
COMMON
C652
C661
.1UF
.1UF
10V10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C669
C663
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603 0603
COMMON
COMMON
C664
4.7UF
6.3V
10%
X5R
0805
COMMON
C634
C613
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
04020402
COMMON
COMMON
C620 C621
1UF
1UF
16V
16V
10%
10%
X5R
X5R
06030603
COMMON
COMMON
C603
4.7UF
6.3V
10%
X5R
0805
COMMON
C660
.1UF
10V
10%
X5R
0402
Place 1uF caps at
center of memory
C654
.1UF
10V
10%
X5R
0402
NO STUFF
C607
.1UF
10V
10%
X5R
0402
COMMON
Place 1uF caps at
center of memory
C612
.1UF
10V
10%
X5R
0402
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMONCOMMON
C668
C651
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
C606
C639
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C619
C611
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFFNO STUFF
600-10393-0004-100 A
p393_a01
whill
C655
C667
C657
.1UF
10V
10%
X5R
0402
COMMON
C658
.1UF
10V
10%
X5R
0402
NO STUFF
C643
.1UF
10V
10%
X5R
0402
COMMON
C604
.1UF
10V
10%
X5R
0402
NO STUFF
C653
.1UF
10V
10%
X5R
0402
COMMON
C648
.1UF
10V
10%
X5R
0402
NO STUFF
C622
.1UF
10V
10%
X5R
0402
COMMON
C573
.1UF
10V
10%
X5R
0402
NO STUFF
C650
.1UF
10V
10%
X5R
0402
COMMON
C662
.1UF
10V
10%
X5R
0402
NO STUFF
C575
.1UF
10V
10%
X5R
0402
COMMON
C578
.1UF
10V
10%
X5R
0402
NO STUFF
6 OF 27
28-SEP-2007
GND
GND
GND
GND
GND
GND
Page 7
Page7: FBC Partition
OUT
OUT
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
ININININOUT
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<7> CMD16
A<8>
A<9>
A<10>
A<11>
CKE
RST
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
FBVDD
R659
121
1%
0402
NO STUFF
FBC_CLK0_MIDPT
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
9> 4>
9> 4>
4> 7< 9>
R658
243
0402
COMMON
1%
FBC_CMD<28..0>
R655
243
1%
0402
COMMON
C864
.01UF
25V
10%
X7R
0402
COMMON
9<>
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
FBC_CMD<1>
1
FBC_CMD<10>
10
FBC_CMD<11>
11
FBC_CMD<8>
8
FBC_CMD<19>
19
FBC_CMD<25>
25
FBC_CMD<22>
22
FBC_CMD<24>
24
FBC_CMD<0>
0
FBC_CMD<2>
2
FBC_CMD<21>
21
FBC_CMD<16>
16
FBC_CMD<23>
23
FBC_CMD<20>
20
FBC_CMD<17>
17
FBC_CMD<9>
9
FBC_CMD<12>
12
FBC_CMD<3>
3
FBC_CMD<7>
7
FBC_CMD<18>
18
FBC_CLK0
FBC_CLK0*
SNN_FBC0_NC1
FBC_CMD<14>
14
GND
15
FBC_CMD<15>
V9
A9
A4
GND
FBC_ZQ0
GND
R635
10K
5%
0402
COMMON
10K
5%
0402
COMMON
243
1%
0402
COMMON
R93
R640
GND
FBVDD
C86
.047UF
16V
10%
X7R
0402
COMMON
C87
.047UF
16V
10%
X7R
0402
COMMON
K12
J12
K1
J1
GND
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBVDD
FBC_VREF0
FBC_VREF2
GND
GND
FBVDD
R95
549
R1
1%
0402
COMMON
R97
1.33K
R2
1%
COMMON
GND
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
136BGA CMD Mapping
136MAPADDR
CMD1
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD00A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
CMD23A<8>
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15
RST
FBVDD
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
R623
121
1%
0402
NO STUFF
4>
9>
4>
9>
FBC_CLK1_MIDPT
Minimize STUB length!
FBVDD
R94
549
R1
1%
0402
9<>
C84
.1UF
10V
10% 10%
X5R
0402
COMMON
COMMON
R96
1.33K
04020402
COMMON
R2
1%
C83
.1UF
10V
X5R
0402
COMMON
9<>
GND
R621
243
0402
COMMON
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
R102
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
K12
J12
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
K1
J1
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBVDD
4> 7< 9>
FBC_CMD<28..0>
R625
243
1%
1%
0402
COMMON
FBVDD
C703
.01UF
25V
10%
X7R
0402
COMMON
9<>
FBC_CMD<7>
7
FBC_CMD<8>
8
FBC_CMD<18>
18
FBC_CMD<10>
10
FBC_CMD<5>
5
FBC_CMD<13>
13
FBC_CMD<21>
21
FBC_CMD<20>
20
FBC_CMD<19>
19
FBC_CMD<25>
25
FBC_CMD<4>
4
FBC_CMD<9>
9
FBC_CMD<17>
17
FBC_CMD<6>
6
FBC_CMD<23>
23
FBC_CMD<16>
16
FBC_CMD<3>
3
FBC_CMD<12>
12
FBC_CMD<1>
1
FBC_CMD<11>
11
FBC_CLK1
FBC_CLK1*
SNN_FBC1_NC1
FBC_CMD<14>
14
GND
FBC_CMD<15>
15
FBC_ZQ1
GND
GND
FBVDD
C100
.047UF
16V
10%
X7R
0402
COMMON
C98
.047UF
16V
10%
X7R
0402
COMMON
GND
FBVDD
FBVDD
FBC_VREF1
FBC_VREF3
GND
GND
R101
549
0402
COMMON
R99
1.33K
COMMON
FBC_CMD<4>
FBC_CMD<6>
FBC_CMD<5>
FBC_CMD<13>
FBC_CMD<22>
FBC_CMD<24>
FBC_CMD<0>
FBC_CMD<2>
VREF = 0.70 * FBVDDQ
GDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
R1
1%
C103
.1UF
R2
1%
10V
10% 10%
X5R
0402
COMMON
GND
9<>
R632
0402
R631
0402
R622
0402
R627
0402
R654
0402
R648
0402
R653
0402
R657
0402
FBVDD
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
FBVDD
R100
549
R1
1%
0402
COMMON
R98
1.33K
04020402
COMMON
C102
.1UF
R2
1%
10V
X5R
0402
COMMON
9<>
GND
9<>
4<>
4> 9>
4< 9<
4> 9>
FBC_D<63..0>
FBC_DQM<7..0>
FBC_DQS_RN<7..0>
FBC_DQS_WP<7..0>
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBC_D<0>
0
FBC_D<1>
1
FBC_D<2>
2
FBC_D<3>
3
FBC_D<4>
4
FBC_DQM<0>
0
FBC_DQM<1>
1
FBC_DQM<2>
2
FBC_DQM<3>
3
FBC_DQM<4>
4
FBC_DQM<5>
5
FBC_DQM<6>
6
FBC_DQM<7>
7
FBC_DQS_RN<0>
0
FBC_DQS_RN<1>
1
FBC_DQS_RN<2>
2
FBC_DQS_RN<3>
3
FBC_DQS_RN<4>
4
FBC_DQS_RN<5>
5
FBC_DQS_RN<6>
6
FBC_DQS_RN<7>
7
FBC_DQS_WP<0>
0
FBC_DQS_WP<1>
1
FBC_DQS_WP<2>
2
FBC_DQS_WP<3>
3
FBC_DQS_WP<4>
4
FBC_DQS_WP<5>
5
FBC_DQS_WP<6>
6
FBC_DQS_WP<7>
7
5
6
7
32
33
34
35
36
37
38
39
FBC_D<5>
FBC_D<6>
FBC_D<7>
FBC_DQM<0>
FBC_DQS_RN<0>
FBC_DQS_WP<0>
FBC_D<32>
FBC_D<33>
FBC_D<34>
FBC_D<35>
FBC_D<36>
FBC_D<37>
FBC_D<38>
FBC_D<39>
FBC_DQM<4>
FBC_DQS_RN<4>
FBC_DQS_WP<4>
B11
C11
F11
G10
C10
E11
F10
B10
E10
D10
D11
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M2
R3
T3
M3
L3
N2
R2
T2
N3
P3
P2
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBC_D<8>
FBC_D<9>
FBC_D<10>
FBC_D<11>
FBC_D<12>
FBC_D<13>
FBC_D<14>
FBC_D<15>
FBC_DQM<1>
FBC_DQS_RN<1>
FBC_DQS_WP<1>
FBC_D<40>
FBC_D<41>
FBC_D<42>
FBC_D<43>
FBC_D<44>
FBC_D<45>
FBC_D<46>
FBC_D<47>
FBC_DQM<5>
FBC_DQS_RN<5>
FBC_DQS_WP<5>
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M2
T2
R2
N2
R3
T3
L3
M3
N3
P3
P2
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
B10
E11
F11
C11
B11
G10
F10
C10
E10
D10
D11
16
FBC_D<17>
17
FBC_D<18>
18
FBC_D<19>
19
FBC_D<20>
20
FBC_D<21>
21
FBC_D<22>
22
FBC_D<23>
23
FBC_DQM<2>
FBC_DQS_RN<2>
FBC_DQS_WP<2>
FBC_D<48>
48
FBC_D<49>
49
FBC_D<50> R11
50
FBC_D<51>
51
FBC_D<52>
52
FBC_D<53>
53
FBC_D<54>
54
FBC_D<55>
55
FBC_DQM<6>
FBC_DQS_RN<6>
FBC_DQS_WP<6>
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
C2FBC_D<16>
G3
F3
E2
F2
B2
B3
C3
E3
D3
D2
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L10
M11
T11
R10
M10
N11
T10
N10
P10
P11
24
FBC_D<25>
25
FBC_D<26>
26
FBC_D<27>
27
FBC_D<28>
28
FBC_D<29>
29
FBC_D<30>
30
FBC_D<31>
31
FBC_DQM<3>
FBC_DQS_RN<3>
FBC_DQS_WP<3>
FBC_D<56>
56
FBC_D<57>
57
FBC_D<58> G3
58
FBC_D<59>
59
FBC_D<60>
60
FBC_D<61>
61
FBC_D<62>
62
FBC_D<63>
63
FBC_DQM<7>
FBC_DQS_RN<7>
FBC_DQS_WP<7>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FBC Partition
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L10FBC_D<24>
M10
N11
R10
T11
R11
M11
T10
N10
P10
P11
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
E2
B2
C2
C3
F2
B3
F3
E3
D3
D2
www.vinafix.vn
Decoupling
for FBC Lo
Decoupling
for FBC Hi
FBVDD
C835
.1UF
10V
10%
X5R
0402
COMMON
C882
1UF
16V
10%
X5R
0603
COMMON
C893
4.7UF
6.3V
10%
X5R
0805
COMMON
C685
.1UF
10V
10%
X5R
0402
COMMON
C690
1UF
16V
10%
X5R
0603
COMMON
C691
4.7UF
6.3V
10%
X5R
0805
COMMON
C850
.1UF
10V
10%
X5R
0402
COMMON
C838
1UF
16V
10%
X5R
0603
COMMON
C883
4.7UF
6.3V
10%
X5R
0805
COMMON
C742
.1UF
10V
10%
X5R
0402
COMMON
C689
1UF
16V
10%
X5R
0603
COMMON
C738
4.7UF
6.3V
10%
X5R
0805
COMMON
C836
.1UF
10V
10%
X5R
0402
COMMON
C880
1UF
16V
10%
X5R
COMMON
C840
4.7UF
6.3V
10%
X5R
0805
COMMON
C726
.1UF
10V
10%
X5R
COMMON
1UF
16V
10%
X5R
COMMON
C678
4.7UF
6.3V
10%
X5R
0805
COMMON
C847
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
C813
1UF
Place 1uF caps at
16V
center of memory
10%
X5R
06030603
COMMON
C888
.1UF
10V
10%
X5R
0402
NO STUFF
C695
C749
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
04020402
COMMON
COMMON
C741C766
1UF
Place 1uF caps at
16V
center of memory
10%
X5R
06030603
COMMON
C696
.1UF
10V
10%
X5R
0402
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMONCOMMON
C851
C875
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
C740
C684
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C725
C683
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFFNO STUFF
600-10393-0004-100 A
p393_a01
whill
C878
C887
C834
C876
.1UF
10V
10%
X5R
0402
COMMON
C846
.1UF
10V
10%
X5R
0402
NO STUFF
C739
.1UF
10V
10%
X5R
0402
COMMON
C748
.1UF
10V
10%
X5R
0402
NO STUFF
C830
.1UF
10V
10%
X5R
0402
COMMON
C886
.1UF
10V
10%
X5R
0402
NO STUFF
C686
.1UF
10V
10%
X5R
0402
COMMON
C693
.1UF
10V
10%
X5R
0402
NO STUFF
C889
.1UF
10V
10%
X5R
0402
COMMON
C829
.1UF
10V
10%
X5R
0402
NO STUFF
C694
.1UF
10V
10%
X5R
0402
COMMON
C717
.1UF
10V
10%
X5R
0402
NO STUFF
7 OF 27
28-SEP-2007
GND
GND
GND
GND
GND
GND
Page 8
Page8: FBD Partition
OUT
OUT
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
ININININOUT
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<7> CMD16
A<8>
A<10>
A<11>
CKE
RST
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD23
CMD20A<9>
CMD17
CMD9
CMD18
CMD15
FBVDD
R706
121
1%
0402
NO STUFF
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
4>
9>
4>
9>
FBD_CLK0_MIDPT
R709
243
0402
COMMON
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
R28
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
GND
R707
243
0402
COMMON
C958
.01UF
25V
10%
X7R
0402
COMMON
FBD_CMD<28..0>
1%
9<>
FBD_CMD<1>
1
FBD_CMD<10>
10
FBD_CMD<11>
11
FBD_CMD<8>
8
FBD_CMD<19>
19
FBD_CMD<25>
25
FBD_CMD<22>
22
FBD_CMD<24>
24
FBD_CMD<0>
0
FBD_CMD<2>
2
FBD_CMD<21>
21
FBD_CMD<16>
16
FBD_CMD<23>
23
FBD_CMD<20>
20
FBD_CMD<17>
17
FBD_CMD<9>
9
FBD_CMD<12>
12
FBD_CMD<3>
3
FBD_CMD<7>
7
FBD_CMD<18>
18
FBD_CLK0
FBD_CLK0*
SNN_FBD0_NC1
FBD_CMD<14>
14
FBD_CMD<15>
15
FBD_ZQ0
R694
R690
10K
10K
5%
5%
0402
0402
COMMON COMMON
GND
GND
4> 8< 9>
1%
GND
FBVDD
C43
.047UF
16V
10%
X7R
0402
COMMON
C57
.047UF
16V
10%
X7R
0402
COMMON
K12
J12
K1
J1
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBD_VREF0
FBD_VREF2
FBVDD
GND
GND
R42
549
0402
COMMON
R47
1.33K
COMMON
1%
1%
GND
136BGA CMD Mapping
136MAPADDR
CMD1
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD0
0A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
CMD23A<8>
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15
RST
FBVDD
R682
121
1%
0402
NO STUFF
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
R26
549
0402
COMMON
R27
1.33K
04020402
COMMON
FBVDD
1%
1%
GND
FBVDD
R1
C55
.1UF
R2
10V
10% 10%
X5R
0402
COMMON
GND
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
9<>
4> 9>
4> 9>
FBD_CLK1_MIDPT
R1
R2
C42
.1UF
10V
X5R
0402
COMMON
R678
243
0402
COMMON
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
H11
K10
K11
H10
J11
J10
K12
J12
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
K1
J1
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBVDD
R676
243
0402
COMMON
C929
.01UF
25V
10%
X7R
0402
COMMON
1%
FBD_CMD<28..0>
FBVDD
9<>
FBD_CMD<7>
7
FBD_CMD<8>
8
FBD_CMD<18>
18
FBD_CMD<10>
10
FBD_CMD<5>
5
FBD_CMD<13>
13
FBD_CMD<21>
21
FBD_CMD<20>
20
FBD_CMD<19>
19
FBD_CMD<25>
25
FBD_CMD<4>
4
FBD_CMD<9>
9
FBD_CMD<17>
17
FBD_CMD<6>
6
FBD_CMD<23>
23
FBD_CMD<16>
16
FBD_CMD<3>
3
FBD_CMD<12>
12
FBD_CMD<1>
1
FBD_CMD<11>
11
FBD_CLK1
FBD_CLK1*
SNN_FBD1_NC1
FBD_CMD<14>
14
GND
FBD_CMD<15>
15
FBD_ZQ1
R69
243
1%
0402
COMMON
4> 8< 9>
1%
GND
GND
9<>
FBVDD
C68
.047UF
16V
10%
X7R
0402
COMMON
C59
.047UF
16V
10%
X7R
0402
COMMON
GND
FBD_VREF1
FBD_VREF3
FBVDD
FBVDD
GND
GND
FBD_CMD<4>
FBD_CMD<6>
FBD_CMD<5>
FBD_CMD<13>
FBD_CMD<22>
FBD_CMD<24>
FBD_CMD<0>
FBD_CMD<2>
VREF = 0.70 * FBVDDQ
GDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
R59
549
R1
1%
0402
COMMON
R51
1.33K
R2
1%
0402 0402
COMMON
C64
.1UF
10V
X5R
0402
COMMON
GND
R79
549
0402
COMMON
R76
1.33K
COMMON
R679
0402
R684
0402
R685
0402
R687
0402
R705
0402
R701
0402
R703
0402
R710
0402
FBVDD
1%
1%
GND
9<>
FBVDD
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
R1
9<>
C70
R2
.1UF
10V
10%10%
X5R
0402
COMMON
9<
4<>
4> 9>
4<
4> 9>
FBD_D<63..0>
FBD_DQM<7..0>
FBD_DQS_RN<7..0>
FBD_DQS_WP<7..0>
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M10
T10
L10
M11
T11
R11
N11
R10
N10
P10
P11
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
B2
C3
C2
E2
G3
F2
F3
E3
D3
D2FBD_DQS_WP<7>
E2
F3
C3
F2
G3
B2
B3
C2
E3
D3
D2
R3
T3
R2
T2
N2
L3
M3
M2
N3
P3
P2
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBD_D<24>
24
FBD_D<25>
25
FBD_D<26>
26
FBD_D<27>
27
FBD_D<28>
28
FBD_D<29>
29
FBD_D<30>
30
FBD_D<31>
31
FBD_DQM<3>
FBD_DQS_RN<3>
FBD_DQS_WP<3>
FBD_D<56>
56
FBD_D<57>
57
FBD_D<58>
58
FBD_D<59> B3
59
FBD_D<60>
60
FBD_D<61>
61
FBD_D<62>
62
FBD_D<63>
63
FBD_DQM<7>
FBD_DQS_RN<7>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FBD Partition
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBD_D<0>
0
FBD_D<1>
1
FBD_D<2>
2
FBD_D<3>
3
FBD_D<4>
4
FBD_DQM<0>
0
FBD_DQM<1>
1
FBD_DQM<2>
2
FBD_DQM<3>
3
FBD_DQM<4>
4
FBD_DQM<5>
5
FBD_DQM<6>
6
FBD_DQM<7>
7
FBD_DQS_RN<0>
0
FBD_DQS_RN<1>
1
FBD_DQS_RN<2>
2
FBD_DQS_RN<3>
3
FBD_DQS_RN<4>
4
FBD_DQS_RN<5>
5
FBD_DQS_RN<6>
6
FBD_DQS_RN<7>
7
FBD_DQS_WP<0>
0
FBD_DQS_WP<1>
1
FBD_DQS_WP<2>
2
FBD_DQS_WP<3>
3
FBD_DQS_WP<4>
4
FBD_DQS_WP<5>
5
FBD_DQS_WP<6>
6
FBD_DQS_WP<7>
7
5
6
7
32
33
34
35
36
37
38
39
FBD_D<5>
FBD_D<6>
FBD_D<7>
FBD_DQM<0>
FBD_DQS_RN<0>
FBD_DQS_WP<0>
FBD_D<32>
FBD_D<33>
FBD_D<34>
FBD_D<35>
FBD_D<36>
FBD_D<37>
FBD_D<38>
FBD_D<39>
FBD_DQM<4>
FBD_DQS_RN<4>
FBD_DQS_WP<4>
C11
E11
F11
G10
B11
F10
C10
B10
E10
D10
D11
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L10
R10
T10
N11
T11
M10
M11
R11
N10
P10
P11
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBD_D<8>
FBD_D<9>
FBD_D<10>
FBD_D<11>
FBD_D<12>
FBD_D<13>
FBD_D<14>
FBD_D<15>
FBD_DQM<1>
FBD_DQS_RN<1>
FBD_DQS_WP<1>
FBD_D<40>
FBD_D<41>
FBD_D<42>
FBD_D<43>
FBD_D<44>
FBD_D<45>
FBD_D<46>
FBD_D<47>
FBD_DQM<5>
FBD_DQS_RN<5>
FBD_DQS_WP<5>
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
N2
T2
R2
R3
T3
M2
L3
M3
N3
P3
P2
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
C10
F11
E11
B11
C11
G10
F10
B10
E10
D10
D11
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBD_D<16>
FBD_D<17>
FBD_D<18>
FBD_D<19>
FBD_D<20>
FBD_D<21>
FBD_D<22>
FBD_D<23>
FBD_DQM<2>
FBD_DQS_RN<2>
FBD_DQS_WP<2>
FBD_D<48>
FBD_D<49>
FBD_D<50>
FBD_D<51>
FBD_D<52>
FBD_D<53>
FBD_D<54>
FBD_D<55>
FBD_DQM<6>
FBD_DQS_RN<6>
FBD_DQS_WP<6>
www.vinafix.vn
9<>
Decoupling
for FBD Lo
Decoupling
for FBD Hi
FBVDD
C950
.1UF
10V
10%
X5R
0402
COMMON
C967
1UF
16V
10%
X5R
0603
COMMON
C977
4.7UF
6.3V
10%
X5R
0805
COMMON
C934
.1UF
10V
10%
X5R
0402
COMMON
C908
1UF
16V
10%
X5R
0603
COMMON
C933
4.7UF
6.3V
10%
X5R
0805
COMMON
C969
.1UF
10V
10%
X5R
0402
COMMON
C938
1UF
16V
10%
X5R
0603
COMMON
C962
4.7UF
6.3V
10%
X5R
0805
COMMON
C930
.1UF
10V
10%
X5R
0402
COMMON
C941
1UF
16V
10%
X5R
0603
COMMON
C910
4.7UF
6.3V
10%
X5R
0805
COMMON
C943
C961
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C952
C949
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603 0603
COMMON
COMMON
C965
4.7UF
6.3V
10%
X5R
0805
COMMON
C937
C935
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C920
C925
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C942
4.7UF
6.3V
10%
X5R
0805
COMMON
C972
.1UF
10V
10%
X5R
0402
COMMON
Place 1uF caps at
center of memory
C974
.1UF
10V
10%
X5R
0402
NO STUFF
C927
.1UF
10V
10%
X5R
0402
COMMON
Place 1uF caps at
center of memory
C936
.1UF
10V
10%
X5R
0402
NO STUFF
p393_a01
whill
.1UF
.1UF
10V10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C963
C944
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
C924
C931
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C932
C926
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
600-10393-0004-100 A
C957
C948
C953
.1UF
10%
X5R
0402
COMMON
C971
.1UF
10V
10%
X5R
0402
NO STUFF
C928
.1UF
10V
10%
X5R
0402
COMMON
C914
.1UF
10V
10%
X5R
0402
NO STUFF
C947
.1UF
10V10V
10%
X5R
0402
COMMON
C956
.1UF
10V
10%
X5R
0402
NO STUFF
C919
.1UF
10V
10%
X5R
0402
COMMON
C939
.1UF
10V
10%
X5R
0402
NO STUFF
C940
.1UF
10V
10%
X5R
0402
COMMON
C955
.1UF
10V
10%
X5R
0402
NO STUFF
C916
.1UF
10V
10%
X5R
0402
COMMON
C923
.1UF
10V
10%
X5R
0402
NO STUFF
8 OF 27
28-SEP-2007
GND
GND
GND
GND
GND
GND
Page 9
Page9: FrameBuffer Net Rules
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUTINOUT
OUT
OUT
OUT
OUTBIOUTINOUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI
OUTINOUT
OUT
OUT
OUT
OUT
OUTBIOUTINOUT
OUT
OUT
OUT
OUT
OUT
NET RULES for FrameBuffer A/B
5<>
5<>
5<>
5<>
5<
5<
5<
5<
5<
3<>
3>
3>
3>
3>
3>
3>
3<
3>
NET
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1* 1
FBA_CMD<28..0>
FBA_DQS_WP<7..0>
FBA_DQS_RN<7..0>
FBA_DQM<7..0>
FBA_D<63..0>
NET
6<
3>
6<
3>
6<
3>
6<
3>
6<
3>
3> 6<>
6<>
6<>
6<>
3<>
3<>
3<>
3<
3>
FBB_CLK0
FBB_CLK0*
FBB_CLK1
FBB_CLK1*
FBB_CMD<28..0>
FBB_DQS_WP<7..0> 1
FBB_DQS_RN<7..0>
FBB_DQM<7..0>
FBB_D<63..0>
FBA_DEBUG
FBB_DEBUG
NET VOLTAGE
3<>
FBAB_PLLAVDD
NV_CRITICAL
1
1
1
1
1
1
1
1
NV_CRITICAL
1
1
1
1
1
1
1
1
1
1
1.2V
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
MAX_CURRENT MIN_WIDTH NET VOLTAGE
0.02A
12MIL
NET RULES for FrameBuffer C/D
7<>
8<>
7<
7<
7<
7<
7<
7<>
7<>
7<>
8<
8<
8<
8<
8<
8<>
8<>
4<>
4<>
4<>
4<>
4<>
4>
4>
4>
4>
4>
4>
4<
4>
4>
4>
4>
4>
4>
4> 8<>
4<
4>
NET
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
FBC_CMD<28..0>
FBC_DQS_WP<7..0>
FBC_DQS_RN<7..0>
FBC_DQM<7..0>
FBC_D<63..0>
NET
FBD_CLK0
FBD_CLK0*
FBD_CLK1
FBD_CLK1*
FBD_CMD<28..0>
FBD_DQS_WP<7..0> 1
FBD_DQS_RN<7..0>
FBD_DQM<7..0>
FBD_D<63..0>
FBC_DEBUG
FBD_DEBUG
FBCD_PLLAVDD
NV_CRITICAL
1
1
1
1
1
1
1
1
1
NV_CRITICAL
1
1
1
1
1
1
1
1
1
1
1.2V
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
MAX_CURRENT MIN_WIDTH
0.02A
12MIL
5>
5>
5>
5>
5<
5<
6>
6>
6>
6>
6<
6<
FBA_VREF0
FBA_VREF1
FBA_VREF2
FBA_VREF3
FBA_ZQ0
FBA_ZQ1
FBB_VREF0
FBB_VREF1
FBB_VREF2
FBB_VREF3
FBB_ZQ0
FBB_ZQ1
3<>
3<>
FB_VREF1
FB_VREF2
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
1.40V
1.40V
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A 12MIL
0.02A
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
7>
7>
7>
7>
7<
7<
8>
8>
8>
8>
8<
8<
FBC_VREF0
FBC_VREF1
FBC_VREF2
FBC_VREF3
FBC_ZQ0
FBC_ZQ1
FBD_VREF0
FBD_VREF1
FBD_VREF2
FBD_VREF3
FBD_ZQ0
FBD_ZQ1
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FrameBuffer Net Rules
www.vinafix.vn
600-10393-0004-100 A
p393_a01
whill
9 OF 27
28-SEP-2007
Page 10
11<
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTININ
BA
BEBABE
IN
8/24 DACA
DACA_VSYNC
DACA_HSYNC
I2CA_SCL
I2CA_SDA
DACA_RED
DACA_IDUMP
DACA_GREEN
DACA_BLUE
DACA_VDD
DACA_VREF
DACA_RSET
ININININININININININININININININININININININININININBI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
21<
Page10: DACA Interface
23<
27>
26>
R728
0402
R729
0402
26<
5%
5%
DDC isolation from GPU to Micro-Controller
when in Hybrid Power mode
3V3_F
LB504
BEAD_0402
C873
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
240R@100MHz
COMMON
C810
.1UF
10V
10%
X5R
0402
COMMON
GND
C868
4.7UF
6.3V
10%
X5R
0603
COMMON
DACA_VREF
DACA_RSET
R641
124
1%
0402
COMMON
C819
1UF
6.3V
10%
X5R
0402
COMMON
DACA_VDD
C866
.1UF
10V
10%
X5R
0402
COMMON
AK13
AK14
AH11
G1
G92-300-A1
BGA1148
COMMON
T9
U8
AJ11
AF14
AJ14
AH12
I2CA_SCL
I2CA_SDA
DACA_HS
DACA_VS
DACA_REDAH13
DACA_GREEN
DACA_BLUE
AJ13
GND
PS3_OUTEN
I2CA_SCL_QS
33
COMMON
I2CA_SDA_QS
33
COMMON
5V
10
9
4
5
U507
74ACT08
74ACT_SO
COMMON
GND
5V
U507
74ACT08
74ACT_SO
COMMON
GND
R637
150
1%
0402
COMMON
GND
8
6
0402
0402
R4
U1201
IDTQS3VH126
XSOP16_SECT
COMMON
XSOP16_SECT
2
U1201
IDTQS3VH126
XSOP16_SECT
COMMON
XSOP16_SECT
6
5
0
NO STUFF
5%
DACA_HS_BUF
0R14
NO STUFF
5%
DACA_VS_BUF
I2CA_SCL_R
3
3
GND
GND
DACA_RED_F
GND
5V
2
D512
BAV99
SOT23
100V
100MA
NO STUFF
1
GND
5V
2
D513
BAV99
SOT23
100V
100MA
NO STUFF
1
GND
C11
3.3PF
50V
+/-0.25PF
C0G
0402
COMMON
C10
3.3PF
50V
+/-0.25PF
C0G
0402
COMMON
C996
10PF
50V
5%
C0G
0402
COMMON
43
7
I2CA_SDA_R
5V
GND
33
R7
COMMON
0402
5%
33
R12
COMMON
0402
5%
3V3_F
2
D1001
BAV99
SOT23
100V
100MA
COMMON
1
C4
.1UF
10V
10%
X5R
0402
COMMON
DACA_HS_BUF_R
DACA_VS_BUF_R
3
GND
27<> 10<
R723
150
1%
0402
COMMON
R730
2.2K
5%
5V
0402
COMMON
R731
2.2K
5%
0402
COMMON
0
L4
COMMON
0603
5%
5V
2
D8
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
5V
2
D7
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
C987
15PF
50V
5%
C0G
0402
COMMON
GND
L3
0603
L504
5%
0603
0
COMMON
21
COMMON
68nH
LB518
LB519
CMFLTR4_2012
R1014
L510
R1020
27nH
COMMON0402
27nH
COMMON0402
DACA_HS_DVI
DACA_VS_DVI
0402
5%
1
2
0402
5%
0
COMMON
4
360R@100mhz
NO STUFF
3
N/A
0
COMMON
I2CA_SCL_DVI
C1007
22PF
50V
5%
C0G
0402
COMMON
GND
I2CA_SDA_DVI
C1008
22PF
50V
5%
C0G
0402
COMMON
GND
10< 12<
12< 10<
12< 10<
12< 10<
* stuff CMC for WS cards
* stuff resistor and
revise filter for DT cards
DACA_RED_DVI
12< 10<
27> 10<
GND
DACA NET RULES
NV_CRITICAL
1
1
1
1
1
1
1
1
1
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
12<
12<
12<
10>
10>
10>
NET
DACA_RED
DACA_GREEN
DACA_BLUE
DACA_RED_F
DACA_GREEN_F
DACA_BLUE_F
DACA_RED_DVI
DACA_GREEN_DVI
DACA_BLUE_DVI
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
0.100A
12<
12<
27>
27<>
12<
12<
10>
10>
10<
10<
10>
10>
10> 12<
DACA_HS
DACA_VS
DACA_HS_BUF
DACA_VS_BUF
DACA_VS_BUF_R
DACA_HS_DVI
DACA_VS_DVI
I2CA_SCL
I2CA_SDA
I2CA_SCL_R
I2CA_SDA_R
I2CA_SDA_DVI
NET
DACA_VREF
DACA_RSET
DACA_VDD
DACA_GND
2
2
2
2
2DACA_HS_BUF_R
2
2
2
3
3
3
3
3I2CA_SCL_DVI
3
3.3V
0.0V
DIFFPAIRNV_IMPEDANCE
MIN_WIDTHMAX_CURRENTVOLTAGE
12MIL
12MIL
16MIL
16MIL
D1002
BAV99
SOT23
100V
100MA
COMMON
D1003
BAV99
SOT23
100V
100MA
COMMON
3V3_F
2
1
GND
3V3_F
2
1
GND
R636
150
1%
0402
COMMON
GND
R639
150
1%
0402
COMMON
GND
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
DACA Interface
www.vinafix.vn
3
3
R725
150
1%
0402
COMMON
GND
R724
150
1%
0402
COMMON
GND GND
0
R1015
COMMON
0402
5%
68nH
DACA_GREEN_F
C998
10PF
50V
5%
C0G
0402
COMMON
GND
L512
CMFLTR4_2012
R1021
0402
1
2
4
3
0
COMMON
5%
360R@100mhz
NO STUFF
N/A
21
L506
COMMON
0603
C989
15PF
50V
5%
C0G
0402
COMMON
GND
* stuff CMC for WS cards
* stuff resistor and
revise filter for DT cards
DACA_GREEN_DVI
12< 10<
* stuff CMC for WS cards
* stuff resistor and
revise filter for DT cards
DACA_BLUE_DVI
DACA_GND
12< 10<
12< 10<
C988
15PF
50V
5%
C0G
0402
COMMON
L505
0603 COMMON
21
68nH
DACA_BLUE_F
C997
10PF
50V
5%
C0G
0402
COMMON
GND
R1016
L511
CMFLTR4_2012
R1022
0402
0402
1
2
0
COMMON
5%
4
3
0
COMMON
5%
360R@100mhz
NO STUFF
N/A
600-10393-0004-100 A
p393_a01
whill
10 OF 27
28-SEP-2007
Page 11
27>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTININ
BA
BEBABE
IN
10/24 DACC
DACC_VSYNC
DACC_HSYNC
I2CB_SCL
I2CB_SDA
DACC_IDUMP
DACC_BLUE
DACC_GREEN
DACC_RED
DACC_VDD
DACC_VREF
DACC_RSET
ININININININININININININININININININININININININBIBIIN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
I2CB_SCL_R
I2CB_SDA_R
11<
11<
27<>
0402
COMMON
COMMON0402
27nH
27nH
R718
2.2K
5%
5V
0402
COMMON
R719
2.2K
5%
0402
COMMON
5V
2
D510
BAV99
3
SOT23
100V
100MA
NO STUFF
1
GND
5V
2
3
1
D511
BAV99
SOT23
100V
100MA
NO STUFF
LB516
LB515
I2CB_SCL_DVI
C999
22PF
50V
5%
C0G
0402
COMMON
GND
I2CB_SDA_DVI
C1000
22PF
50V
5%
C0G
0402
COMMON
GND
11< 12<
12< 11<
33
COMMON
33
COMMON
PS3_OUTEN
I2CB_SCL_QS
I2CB_SDA_QS
12
14
15
U1201
IDTQS3VH126
XSOP16_SECT
COMMON
XSOP16_SECT
U1201
IDTQS3VH126
XSOP16_SECT
COMMON
XSOP16_SECT
1011
13
Page11: DACC Interface
10<
21<
23<
27>
26<
26>
R716
0402
5%
R717
0402
5%
DDC isolation from GPU to Micro-Controller
when in Hybrid Power mode
0
R3
NO STUFF
0402
U507
74ACT08
11
74ACT_SO
COMMON
R13
0402
U507
74ACT08
3
74ACT_SO
COMMON
5%
DACC_HS_BUF
0
NO STUFF
5%
DACC_VS_BUF
0402
R11
0402
R6
D1004
BAV99
SOT23
100V
100MA
COMMON
5%
5%
33
COMMON
33
COMMON
3V3_F
GND
2
1
DACC_HS_BUF_R
DACC_VS_BUF_R
R720
150
1%
0402
COMMON
3
GND
5V
13
12
3V3_F
GND
240R@100MHz
LB508
BEAD_0402
C912
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C845
.1UF
10V
10%
X5R
0402
COMMON
COMMON
C899
4.7UF
6.3V
10%
X5R
0603
COMMON
DACC_VREF
DACC_RSET
R652
124
1%
0402
COMMON
C865
1UF
6.3V
10%
X5R
0402
COMMON
DACC_VDD
C870
.1UF
10V
10%
X5R
0402
COMMON
AH7
AK8
AH8
G1
G92-300-A1
BGA1148
COMMON
R9
AJ10
AJ7
AJ9
AH9
AK9
GND
I2CB_SCL
I2CB_SDAT8
DACC_HS
DACC_VS
DACC_RED
DACC_GREEN
DACC_BLUEAH10
GND
5V
1
2
GND
R647
150
1%
0402
COMMON
GND
DACC NET RULES
NV_CRITICALNET
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
12<
12<
12<
11>
11>
11>
DACC_RED
DACC_GREEN
DACC_BLUE
DACC_RED_F
DACC_GREEN_F
DACC_BLUE_F
DACC_RED_DVI
DACC_GREEN_DVI
DACC_BLUE_DVI
1
1
1
1
1
1
1
1
1
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
0.100A
12<
12<
27>
27<>
12<
12<
12< 11>
11>
11>
11<
11<
11>
11>
DACC_HS
DACC_VS
DACC_HS_BUF
DACC_VS_BUF
DACC_HS_BUF_R
DACC_VS_BUF_R
DACC_HS_DVI
DACC_VS_DVI
I2CB_SCL
I2CB_SDA
I2CB_SCL_R
I2CB_SDA_R
I2CB_SCL_DVI
I2CB_SDA_DVI
NET
DACC_VREF
DACC_RSET
DACC_VDD
DACC_GND
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3.3V
0.0V
DIFFPAIRNV_IMPEDANCE
R650
150
1%
0402
COMMON
GND
R643
150
1%
0402
COMMON
GND
MIN_WIDTHMAX_CURRENTVOLTAGE
12MIL
12MIL
16MIL
16MIL
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
DACC Interface
D1005
BAV99
SOT23
100V
100MA
COMMON
D1006
BAV99
SOT23
100V
100MA
COMMON
3V3_F
GND
3V3_F
GND
R722
150
1%
0402
2
1
2
1
COMMON
3
GND
R721
150
1%
0402
COMMON
3
www.vinafix.vn
0
L2
COMMON
0603
L501
L503
0603
L1
0603
0603
5%
5%
0
COMMON
21
COMMON
21
COMMON
68nH
68nH
5V
2
D6
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
5V
2
D5
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
C984
15PF
50V
5%
C0G
0402
COMMON
GND
C986
15PF
50V
5%
C0G
0402
COMMON
GND
GND
C9
3.3PF
50V
+/-0.25PF
C0G
0402
COMMON
GND
C8
3.3PF
50V
+/-0.25PF
C0G
0402
COMMON
GND
DACC_RED_F
C993
10PF
50V
5%
C0G
0402
COMMON
GND
DACC_GREEN_F
C995
10PF
50V
5%
C0G
0402
COMMON
GND
R1017
L507
CMFLTR4_2012
R1023
R1018
L509
CMFLTR4_2012
R1024
DACC_HS_DVI
DACC_VS_DVI
0402
5%
1
2
0402
5%
0402
5%
1
2
0402
5%
0
COMMON
4
360R@100mhz
NO STUFF
3
N/A
0
COMMON
0
COMMON
4
360R@100mhz
NO STUFF
3
N/A
0
COMMON
* stuff CMC for WS cards
* stuff resistor and
revise filter for DT cards
DACC_RED_DVI
* stuff CMC for WS cards
* stuff resistor and
revise filter for DT cards
DACC_GREEN_DVI
12< 11<
12< 11<
12<
11<
12<
11<
0
R1019
COMMON
0402
5%
68nH
DACC_BLUE_F
C994
10PF
50V
5%
C0G
0402
COMMON
GND
L508
CMFLTR4_2012
R1025
0402
1
2
4
3
0
COMMON
5%
360R@100mhz
NO STUFF
N/A
21
L502
0603 COMMON
C985
15PF
50V
5%
C0G
0402
COMMON
GNDGND
* stuff CMC for WS cards
* stuff resistor and
revise filter for DT cards
DACC_BLUE_DVI
DACC_GND
11<
11<>
12<
12<
600-10393-0004-100 A
p393_a01
whill
11 OF 27
28-SEP-2007
Page 12
INININININININININ
IN
1917
81624
C1
C5A
C2
C3
C5
C4
SHLD24
SHLD13
SHLD05
SHIELD8
SHIELD5
SHIELD6
SHIELD7
SHIELD1
SHIELD2
SHIELD3
SHIELD4
TX0ÂTX1-
TX1+
TX2-
TX0+
TX2+
TX3ÂTX3+
TX4+
TX4-
DDCC
TX5+
TX5-
GND
VDDC
SHLDC
TXC-
DDCD
HPD
R
VSYNC
TXC+
G
AGND2
AGND1
B
HSYNC
1917
81624
C1
C5A
C2
C3
C5
C4
SHLD24
SHLD13
SHLD05
SHIELD8
SHIELD5
SHIELD6
SHIELD7
SHIELD1
SHIELD2
SHIELD3
SHIELD4
TX0ÂTX1-
TX1+
TX2-
TX0+
TX2+
TX3ÂTX3+
TX4+
TX4-
DDCC
TX5+
TX5-
GND
VDDC
SHLDC
TXC-
DDCD
HPD
R
VSYNC
TXC+
G
AGND2
AGND1
B
HSYNC
ININININININININININININININININOUT
OUT
12/24 IFPAB TMDS
IFPA_TXD0
IFPA_TXC
IFPA_TXC
IFPA_TXD0
IFPA_TXD1
IFPA_TXD1
IFPA_TXD3
IFPA_TXD3
IFPA_TXD2
IFPA_TXD2
IFPB_TXD7
IFPB_TXD7
IFPB_TXD4
IFPB_TXD6
IFPB_TXD6
IFPB_TXD5
IFPB_TXD5
IFPB_TXD4
IFPB_TXC
IFPB_TXC
IFPAB_RSET
IFPAB_PLLVDD
IFPAB_PLLGND
IFPA_IOVDD
IFPAB_VPROBE
IFPB_IOVDD
13/24 IFPCD TMDS
IFPC_TXD2
IFPC_TXC
IFPC_TXC
IFPC_TXD0
IFPC_TXD0
IFPC_TXD1
IFPC_TXD1
IFPC_TXD2
IFPD_TXD6
IFPD_TXD6
IFPD_TXD5
IFPD_TXC
IFPD_TXC
IFPD_TXD4
IFPD_TXD4
IFPD_TXD5
IFPCD_RSET
IFPCD_VPROBE
IFPCD_PLLGND
IFPC_IOVDD
IFPCD_PLLVDD
IFPD_IOVDD
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
16<
27< 16<
15>
NET RULES
IFPAB_TXC*
AT9
IFPAB_TXC
AT8
IFPAB_TXD0*
AN4
IFPAB_TXD0
AN5
AT3
IFPAB_TXD1*
IFPAB_TXD1
AT4
IFPAB_TXD2*
AP4
IFPAB_TXD2
AP5
SNN_IFPAB_TXD3*
AR3
SNN_IFPAB_TXD3
AR4
SNN_IFPB_TXC*
AP1
SNN_IFPB_TXC
AR2
IFPAB_TXD4*
AP6
IFPAB_TXD4
AP7
IFPAB_TXD5*AR7
IFPAB_TXD5
AR8
IFPAB_TXD6*
AT5
IFPAB_TXD6
AT6
SNN_IFPAB_TXD7*
AN2
SNN_IFPAB_TXD7
AP2
GPIO0_DVIAB_HPD
R8
10K
5%
0402
COMMON
GND
NET RULES
IFPCD_TXC*
AJ6
IFPCD_TXC
AH6
IFPCD_TXD0*AL2
IFPCD_TXD0
AL1
IFPCD_TXD1*
AJ1
IFPCD_TXD1
AK1
IFPCD_TXD2*
AL3
IFPCD_TXD2
AM3
SNN_IFPD_TXC*
AH5
SNN_IFPD_TXC
AH4
IFPCD_TXD4*
AK2
IFPCD_TXD4
AK3
IFPCD_TXD5*
AK4
IFPCD_TXD5
AK5
IFPCD_TXD6*
AM1
IFPCD_TXD6
AN1
GPIO1_DVICD_DP_HPD
R737
10K
5%
0402
COMMON
GND
DIFFPAIRNET
IFPAB_TXC
IFPAB_TXC
IFPAB_TXD0
IFPAB_TXD0
IFPAB_TXD1
IFPAB_TXD1
IFPAB_TXD2
IFPAB_TXD2
IFPAB_TXD4
IFPAB_TXD4
IFPAB_TXD5
IFPAB_TXD5
IFPAB_TXD6
IFPAB_TXD6
3V3_F
2
3
1
GND
DIFFPAIRNET
IFPC_TXC
IFPC_TXC
IFPCD_TXD0
IFPCD_TXD0
IFPCD_TXD1
IFPCD_TXD1
IFPCD_TXD2
IFPCD_TXD2
IFPCD_TXD4
IFPCD_TXD4
IFPCD_TXD5
IFPCD_TXD5
IFPCD_TXD6
IFPCD_TXD6
D4
BAV99
SOT23
100V
100MA
COMMON
1V8
LB511
240R@100MHz
G1
G92-300-A1
BGA1148
1KR651
COMMON
0402
5%
GND
COMMONBEAD_0402
C902
4.7UF
6.3V
10%
X5R
0603
COMMON
SNN_IFPAB_VPROBE
IFPAB_RSET
IFPAB_PLLVDD
1UF .1UF
6.3V
10%
X5R
0402
C862C867
10V
10%
X5R
0402
COMMONCOMMON
COMMON
AR6
AM7
AN6
AN7
Page12: IFP A/B and C/D Interface
IFP_IOVDD
LB512
COMMON
BEAD_0402
240R@100MHz
IFP_IOVDD
3.3V
0.35A
16MIL
C75
4.7UF
6.3V
20%
X5R
0603
COMMON
GND
GND
C903
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C863
1UF
6.3V
10%
X5R
0402
COMMON
GND
C858
1UF
6.3V
10%
X5R
0402
COMMON
GND
1K
R662
COMMON
0402
1V8
LB510
BEAD_0402
240R@100MHz
COMMON
5%
GND
C901
4.7UF
6.3V
10%
X5R
0603
COMMON
SNN_IFPCD_VPROBE
IFPCD_RSET
IFPCD_PLLVDD
C881
1UF
6.3V
10%
X5R
0402
COMMON
C859
.1UF
10V
10%
X5R
0402
COMMON
C856
.1UF
10V
10%
X5R
0402
COMMON
C877
.1UF
10V
10%
X5R
0402
COMMON
AN8IFPAB_IOVDD
AM6
AL6
AN3
AM4
AL4
G1
G92-300-A1
BGA1148
COMMON
IFP_IOVDD
LB509
240R@100MHz
COMMONBEAD_0402
GND
C900
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
GND
GND
IFPCD_IOVDD
C871
1UF
6.3V
10%
X5R
0402
COMMON
C884
1UF
6.3V
10%
X5R
0402
COMMON
C861
.1UF
10V
10%
X5R
0402
COMMON
C874
.1UF
10V
10%
X5R
0402
COMMON
AL5
AJ4
NV_IMPEDANCENV_CRITICAL
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
LB1
240R@100MHz
COMMONBEAD_0402
0402
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPIO0_DVIAB_HPD_R
1K
R5
COMMON
5%
NV_IMPEDANCENV_CRITICAL
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
GPIO1_DVICD_HPD_R
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
IFP A/B and C/D Interface
LB517
BEAD_0402 COMMON
240R@100MHz
3
3V3_F
2
1
GND
04025%COMMON
D508
BAV99
SOT23
100V
100MA
COMMON
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1KR739
www.vinafix.vn
10<
10<
10<
10<
10>
10>
10>
10<
C2
220PF
50V
5%
C0G
0402
COMMON
GND
11<
11<
11<
11<
11>
11>
11>
11<
C1005
220PF
50V
5%
C0G
0402
COMMON
GND
10>
10>
10>
10>
10<
10<
10<
10>
11>
11>
11>
11>
11<
11<
11<>
11>
C3
4700PF
25V
10%
X7R
0402
COMMON
GND
IFPAB_TXD0*
IFPAB_TXD0
IFPAB_TXD1*
IFPAB_TXD1
IFPAB_TXD2*
IFPAB_TXD2
IFPAB_TXD4*
IFPAB_TXD4
IFPAB_TXD5*
IFPAB_TXD5
IFPAB_TXD6*
IFPAB_TXD6
I2CA_SCL_DVI
I2CA_SDA_DVI
IFPAB_TXC*
IFPAB_TXC
DACA_VS_DVI
GPIO0_DVIAB_HPD_F
DACA_RED_DVI
DACA_GREEN_DVI
DACA_BLUE_DVI
DACA_GND
DACA_HS_DVI
C1009
4700PF
25V
10%
X7R
0402
COMMON
GND
IFPCD_TXD0*
IFPCD_TXD0
IFPCD_TXD1*
IFPCD_TXD1
IFPCD_TXD2*
IFPCD_TXD2
IFPCD_TXD4*
IFPCD_TXD4
IFPCD_TXD5*
IFPCD_TXD5
IFPCD_TXD6*
IFPCD_TXD6
I2CB_SCL_DVI
I2CB_SDA_DVI
IFPCD_TXC*
IFPCD_TXC
DACC_VS_DVI
GPIO1_DVICD_HPD_F
DACC_RED_DVI
DACC_GREEN_DVI
DACC_BLUE_DVI
DACC_GND
DACC_HS_DVI
DDC_5V
DDC_5V
IFPABCD NET RULES
NET
IFPAB_RSET
IFPCD_RSET
GPIO0_DVIAB_HPD_F
GPIO0_DVIAB_HPD_R
GPIO1_DVICD_HPD_F
GPIO1_DVICD_HPD_R
NET
IFPAB_PLLVDD
IFPAB_IOVDD
IFPCD_PLLVDD
25
26
27
28
17
18
9
10
1
2
3
11
19
12
13
4
5
20
21
6
7
14
15
22
24
23
8
16
C1
C2
C3
C5
C5A
C4
29
30
31
32
GND
J5
DVI-I
DVI_I_(SLIM_)SHLD_M
DVI_I_RA_VERT
CHANGED
IFPCD_IOVDD
3
3
3
3
VOLTAGE
1.8V
3.3V
1.8V
3.3V
NV_IMPEDANCENV_CRITICAL
50OHM
50OHM
50OHM
50OHM
0.03A
0.09A
0.03A
0.09A
DIFFPAIR
12MIL
12MIL
MIN_WIDTHMAX_CURRENT
16MIL
16MIL
16MIL
16MIL
25
26
27
28
17
18
9
10
1
2
3
11
19
12
13
4
5
20
21
6
7
14
15
22
24
23
8
16
C1
C2
C3
C5
C5A
C4
29
30
31
32
GND
J4
DVI-I
DVI_I_(SLIM_)SHLD_M
DVI_I_RA_VERT
CHANGED
600-10393-0004-100 A
p393_a01
whill
12 OF 27
28-SEP-2007
Page 13
Page13: DACB and Stereo Interface
INININININININININININININININININ
out
7P_COMP_10P
out
out NC
Y/CVBS
GND
NC
Pb out
C/Pr
GND
IN
9/24 DACB (TVout)
DACB_RED
DACB_BLUE
DACB_GREEN
DACB_IDUMP
DACB_CSYNC
DACB_VDD
DACB_VREF
DACB_RSET
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
DACB,STEREO, FL NET RULES
NET
DACB_PR
DACB_Y
DACB_PB
DACB_PR_F
DACB_Y_F
DACB_PB_F
1
1
1
1
1
1
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
DIFFPAIRNV_IMPEDANCENV_CRITICAL
GPU_STEREO_BUF1
GPU_STEREO_R1
GPIO14_FL_SYNC_R
GPU_STEREO_BUF2
GPU_STEREO_R2
GPU_STEREO_F
3
3
3
3
3
3
NET
D1009
BAV99
SOT23
100V
100MA
COMMON
0.0V
5V
3.3V
TV_GND1
Stereo
STEREO_BUF2
G1
G92-300-A1
BGA1148
COMMON
Y9
Y8
Y11
5V
C5
.1UF
10V
10%
X5R
0402
NO STUFF
GND
DACB_PB_F
C1011
82PF
50V
5%
C0G
0402
COMMON
DACB_PR_F
STEREO_F
C1010
220PF
50V
5%
C0G
0603
NO STUFF
TV_GND1
Rgnd
R744
0
5%
0603
COMMON
7
6
4
2
J2
CON_MINIDIN_7
7P_COMP_10P
COMMON
SNN_TV_STEREO_NC
5
3
1
Rgnd_video
LB521
220R@100MHz
BEAD_0603
NO STUFF
TV_GND2_5V_STEREO_F
DACB_Y_F
R742
0
5%
0603
COMMON
C1003
COMMON
L515
C1013
82PF
50V
5%
C0G
0402
COMMON
STEREO_5V
0603
0603
8.2PF
50V
NPO
0.56uH
COMMON
+/-0.5PF
C992
82PF
50V
5%
C0G
0402
COMMON
0402
R9
5%
AA8
AB9
AA9
AG9
W9
33
NO STUFF
DACB_PR
SVID_CHROM
DACB_Y
SVID_LUM
DACB_PB
COMPOSITE
SNN_DACB_CSYNC
GND
R656
150
1%
0402
COMMON
R644
150
1%
0402
COMMON12
D1008
BAV99
SOT23
100V
100MA
COMMON
D1007
BAV99
SOT23
100V
100MA
COMMON
3V3_F
GND
3V3_F
GND
2
1
STEREO_R2
2
3
1
3
R733
150
1%
0402
COMMON
R732
150
1%
0402
COMMON12
LB520
BEAD_0402
240R@100MHz
C1001
COMMON
L513
C990
1
82PF
50V
5%
2
C0G
0402
COMMON
C1002
0603
COMMON
L514
0603
C991
82PF
50V
5%
C0G
0402
COMMON
1
0603
1
0603
8.2PF
50V
NPO
COMMON
NO STUFF
8.2PF
2
50V
NPO
2
0.56uH
COMMON
+/-0.5PF
0.56uH
+/-0.5PF
1
2
C1012
82PF
50V
5%
C0G
0402
COMMON
5V
LB505
BEAD_0402
240R@100MHz
STEREO
COMMON
16>
3V3_F
GND
C891
4.7UF
6.3V
10%
X5R
0603
COMMON
R10
3.3K
5%
0402
NO STUFF
C879
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C831
.1UF
10V
10%
X5R
0402
COMMON
1
2
C849
1UF
6.3V
10%
X5R
0402
COMMON
5V
5
3
GND
DACB_VREF
DACB_RSET
R642
124
1%
0402
COMMON
GND
U2
SN74LVC1G08
4
SC70-5
NO STUFF
DACB_VDD
C854
.1UF
10V
10%
X5R
0402
COMMON
TV_GND2_5V_STEREO_F
DACB_VDD
DACB_VREF
DACB_RSET
R734
150
1%
0402
COMMON
3V3_F
2
3
1
GND
DACB_Y
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
0.5A
0.2A
R646
150
1%
0402
COMMON
MIN_WIDTHMAX_CURRENTVOLTAGE
12MIL
20MIL
12MIL
12MIL
12MIL
GND FOR STEREO
Rgnd can be used for EMI purposes.
NOTE:
www.vinafix.vn
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
DACB and Stereo Interface
STUFF 1UF CAP
WHEN STEREO
ELSE 0 OHM R
600-10393-0004-100 A
p393_a01
whill
13 OF 27
28-SEP-2007
Page 14
Page14: Multi-use IO(MIO) Interface
IN
SLI - G80/NVIO
GND
GND
GND
GND
GND
GND
RASTER_SYNC
DR<0>
DR<9>
DR<8>
DR<2>
DR<1>
DR<3>
DR<5>
DR<4>
DR<6>
DR<7>
DR<10>
DR_CLK
DR_CMD
DR<14>
DR<13>
DR<12>
DR<11>
SWAP_RDY
EXT_REFCLK
BIBIOUT
MIO
DRA_D10
DR
DRA_D0
DRA_D11
DRA_D9
DRA_D8
DRA_D7
DRA_D6
DRA_D5
DRA_D1
DRA_D2
DRA_D3
DRA_D4
DRA_D12
NC
DRA_CLK
DRA_CMD
DRA_D13
DRA_D14
14/24 MIOA
MIOAD4
MIOAD5
MIOAD3
MIOAD0
MIOAD1
MIOAD2
MIOAD6
MIOAD8
MIOAD9
MIOAD10
MIOAD11
MIOAD7
MIOA_CTL3
MIOA_DE
MIOA_CLKOUT
MIOA_CLKOUT
MIOA_VSYNC
MIOA_HSYNC
MIOACAL_PD_VDDQ
MIOA_VREF
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOACAL_PU_GND
OUT
OUT
OUT
OUT
OUT
MIO
DRB_D6
DRB_D7
DRB_D8
DRB_D2
DRB_D3
DRB_D4
DRB_D5
DR
DRB_D9
DRB_D1
DRB_D0
DRB_D11
DRB_D10
DRB_D12
DRB_CLK
NC
DR_REFCLK
DRB_D14
DRB_D13
DRB_CMD
15/24 MIOB
MIOBD2
MIOBD1
MIOBD0
MIOBD5
MIOBD4
MIOBD3
MIOBD6
MIOBD10
MIOBD9
MIOBD11
MIOBD8
MIOBD7
MIOB_CTL3
MIOB_DE
MIOB_CLKIN
MIOB_HSYNC
MIOB_CLKOUT
MIOB_CLKOUT
MIOB_VSYNC
MIOBCAL_PD_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VREF
MIOB_VDDQ
MIOB_VDDQ
MIOBCAL_PU_GND
INININININININININININININININ
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
MIO Feature Connector
MIOA_D<14..0>
G1
U11
V11
W11
T12
U12
AE11
AE12
AF12
AE13
AF13
AG2
W3
V3
V2
G92-300-A1
BGA1148
COMMON
G1
G92-300-A1
BGA1148
COMMON
Y7
V6
V5
U7
Y3
W1
W2
Y4
W5
W6
AA7
AA5
Y5
W7
AA2
Y1
AE6
AG7
AF9
AF8
AE9
AE7
AD8
AD9
AC8
AD7
AD5
AC5
MIOA_D<0>AA4
MIOA_D<1>
MIOA_D<2>V7
MIOA_D<3>
MIOA_D<4>
MIOA_D<5>
MIOA_D<6>
MIOA_D<7>
MIOA_D<8>
MIOA_D<9>
MIOA_D<10>
MIOA_D<11>
MIOA_D<12>
MIOA_D<13>
MIOA_D<14>
MIOA_DE
MIOA_CLKOUT
SNN_MIOA_CLKOUT*
MIOB_D<0>
MIOB_D<1>
MIOB_D<2>
MIOB_D<3>
MIOB_D<4>
MIOB_D<5>
MIOB_D<6>
MIOB_D<7>
MIOB_D<8>
MIOB_D<9>
MIOB_D<10>
MIOB_D<11>
J3
CON_MIO_26_EDGE
NONPHY
COMMON
B10
A10
B12
A12
A13
B13
A2
B4
A4
A5
B6
A6
A8
B9
B5
A9
B8
A1
B1
MIOA_D<0>
0
MIOA_D<1>
16<
16<
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MIOA_D<2>
MIOA_D<3>
MIOA_D<4>
MIOA_D<5>
MIOA_D<6>
MIOA_D<7>
MIOA_D<8>
MIOA_D<9>
MIOA_D<10>
MIOA_D<11>
MIOA_D<12>
MIOA_D<13>
MIOA_D<14>
GPIO11_RASTER_SYNC
GPU_SWAPRDY
0
STRAPS
1
2
3
4
5
6
7
8
9
10
11
12
13
STRAPS
14
16>
16<>
B2GPU_EXT_REFCLK
0
1
2
3
4
5
6
7
8
9
10
11
MIOB_D<12..0>
STRAPS
STRAPS
STRAPS
STRAPS
STRAPS
19>
14<
15<
2V5
C913
4.7UF
6.3V
0603
COMMON
LB513
220R@100MHz
10%
X5R
GND
COMMON
MIOA_VDDQ
BEAD_0603
2V5
C911
4.7UF
6.3V
10%
X5R
0603
COMMON
LB514
220R@100MHz
COMMON
GND
MIOB_VDDQ
BEAD_0603
2.5V
1A
30MIL
4.7UF .01UF1UF .01UF .1UF
6.3V
10%
0603
COMMON
GND
2.5V
1A
30MIL
C898
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
6.3V
10%
X5RX5R
0402
COMMON
C828
1UF
6.3V
10%
X5R
0402
COMMON
16V
10%
X7R
0402
COMMON
C814
.01UF
16V
10%
X7R
0402
COMMON
16V
10%
X7R
0402
COMMON
C842
.01UF
16V
10%
X7R
0402
COMMON
C812C860C820C827C895
10V
10%
X5R
0402
COMMON
C71
.1UF
10V
10%
X5R
0402
COMMON
R665
1K
1%
0402
COMMON
MIOA_VREF
R667
C905
1K
.1UF
1%
10V
0402
10%
COMMON
X5R
0402
COMMON
GND
MIOA_CAL_PD_VDDQ
49.9
R660
COMMON
0402
1%
MIOA_CAL_PU_GND
49.9
R661
COMMON
0402
1%
GND
R72
1K
1%
0402
COMMON
MIOB_VREF
C72 R77
1K
.1UF
1%
10V
0402
10%
COMMON
X5R
0402
COMMON
B3
B7
B11
A3
A7
A11
19> 14<
GND
GND
MIOB_CAL_PD_VDDQ
49.9
R663
COMMON
0402
1%
MIOB_CAL_PU_GND
49.9
R664
COMMON
0402
1%
GND
AG1
AF1
AE5
AF5
AG5
AF7
AG3
AG4
AD3
MIOB_D<12>
MIOB_HSYNC
MIOB_VSYNC
MIOB_DE
MIOB_CLKOUT
MIOB_CLKOUT*
GPU_EXT_REFCLK
MIO NET RULES
NV_CRITICALNET
1
1
1
1
1
1
1
1
1
1
VOLTAGENET
1.25V
1.25V
MIOA_D<14..0>
MIOA_CLKOUT
MIOA_DE
MIOB_D<12..0>
MIOB_HSYNC
MIOB_VSYNC
MIOB_DE
MIOB_CLKOUT
MIOB_CLKOUT*
GPU_EXT_REFCLK
MIOA_VREF
MIOACAL_PD_VDDQ
MIOACAL_PU_GND
MIOB_VREF
MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND
14<
19>
19>
14>
15<
14>
15<
14>
15<
14>
15<
14>
15<
14>
15<
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
100DIFF
100DIFF
50OHM
MAX_CURRENT
DIFFPAIRNV_IMPEDANCE
MIOB_CLK
MIOB_CLK
MIN_WIDTH
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Multi-use IO(MIO) Interface
www.vinafix.vn
12
14<
14<
14<
14<
14<
STRAPS
15<
15<
15<
15<
15<
600-10393-0004-100 A
p393_a01
whill
14 OF 27
28-SEP-2007
Page 15
DP_MODE*
17
19
15
13
11
9
7
5
1
3
20
18
16
12
14
10
6
8
2
4
SHIELD6
SHIELD4
SHIELD5
PWR
GND
GND
MODE
GND
PWR_RET
GND
GND
GND
SHIELD1
SHIELD3
SHIELD2
LANE_3N
AUXN
LANE_3P
HPD
AUXP
LANE_2N
LANE_0P
LANE_0N
LANE_1P
LANE_1N
LANE_2P
2\2
BIBIBIBIBIBIBIBIBIBIBIBIBI
BI
1\2
1\2
2\2
2\2
S
D
G
S
D
G
S
D
G
S
D
G
OUT
1\2
ANX9802
1/2
HPD
DSCL
DSDA
AUXN*
AUXP
TX3P
TX3N*
TX2N*
TX2P
TX1N*
TX1P
TX0N*
TX0P
R_BIAS
RSVL
DEV_ADR_SEL_GPIO
XTAL_OUT
XTAL_IN
D0
D1
D5
D3
D2
D4
D6
D14
D10
D15
D13
D12
D11
D9
D7
D8
D16
D19
D22
D23
D21
D18
D17
D20
HSYNC
VSYNC
CSCL
CSDA
CLKP
CLKN*
DE
NC
INTP
RESETN*
OUTINININININININININOUTBIIN
ANX9802
2/2
VREF
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
PWRPAD
AVDD33
AVDD33
AVDD33
VPP
AVDD33
AVDD33
AVDD33
DVDD18
DVDD33
DVDD33
DVDD33
DVDD18
DVDD18
DVDD18
DVDD18
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
SOT23_1G1D1S
MAX_VOLTAGE=50V
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
R33
100K
0402
NO STUFF
100K
NO STUFF
NO STUFF
NO STUFF
NO STUFF
NO STUFF
NO STUFF
NO STUFF
NO STUFF
NO STUFF
3V3_F
GND
12V_PEX6_F
Q513
BSS138
NO STUFF
R_DS_ON=3.5R
V_BE_GS=+/-20V
1G1D1S
5%
R32
5%
0402
3
2
GND
3V3_F
GND
High=6.0V
R714
10K
1%
0402
GPIO3_DP_PIN13
R712
0402
5%
0
NO STUFF
DP_MODE_R*
High=3.0V
NO STUFF
R713
10K
1%
0402
NO STUFF
GND
NO STUFF
6.3V
X7R
10%
29
38
39
CONTINUOUS_CURRENT=0.22A@31C
DP_AUX*
58
DP_AUX
59
DP_L3*
42
DP_L343
DP_L2*
46
DP_L2
47
DP_L1*
50
DP_L1
51
DP_L0*
54
DP_L0
55
DP_GPIO
34
DP_RBIAS
64
12MIL
BSS138
SOT23_1G1D1S
NO STUFF
MAX_VOLTAGE=50V
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
1G1D1S
Q3
.1UFC48
0402
DP_AUX_C*
3
2
R22
0402
C40
C36
C35
C33
C30
1%
.1UFC41
.1UF
.1UFC39
.1UF
.1UF
.1UF
.1UFC31
.1UF
4.99K
NO STUFF
11
6.3V
6.3V
6.3V
6.3V
10%
6.3V
.1UF
0402
C46
DP_AUX_C
3
Q2
BSS138
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
1G1D1S
X7R
10%
X7R
10%
X7R10%6.3V
X7R10%6.3V
X7R10%6.3V
X7R10%6.3V
X7R
10%
X7R
10%
R36
0402
R38
0402
GND
40
C32
.1UF
16V
10%
X5R
0402
NO STUFF
DP_RSVL
2V5
R23
1K
1%
0402
NO STUFF
R24
1K
1%
0402
NO STUFF
R29
0402
1%
4.99K
NO STUFF
GND
I2CC Address:
H=0x78,0x79,0x7C,0x7D
L=0x70,0x71,0x74,0x75
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Display Port
www.vinafix.vn
CONTINUOUS_CURRENT=0.22A@31C
X7R
NO STUFF
0402
0402
0402
0402
0402
0402
0402
0402
1K
NO STUFF
5%
1K
NO STUFF
5%
GPIO1_DVICD_DP_HPD
R21
100
0402
5%
DP_XTAL_IN
MIOB_D<12..0>
DP_D_PD
DP_GPIO3
DP_GPIO2
DP_CEC
DP_SPDIF_0
MIOB_HSYNC
MIOB_VSYNC
MIOB_DE
MIOB_CLKOUT
MIOB_CLKOUT*
I2CC_SDA_R
I2CC_SCL_R
GPIO10_DP_INT*
GPU_BUFRST*
U3
ANX9802
TQFP_80
NO STUFF
41
45
49
53
57
61
31
12
30
75
1
16
26
35
72
16<
R702
0
5%
0402
NO STUFF
R704
604K
1%
0402
NO STUFF
U3
GND
ANX9802
TQFP_80
DP_XTAL_OUT
NO STUFF
62
50OHM1
0
1
2
3
4
5
6
7
8
9
10
11
63
22
21
20
19
17
15
14
13
9
8
7
6
5
3
2
80
78
77
76
74
73
71
70
68
25
24
23
10
11
32
33
28
37
SNN_DP_NC
65
DP_VREF67
44
48
52
56
60
66
GND
4
18
27
36
69
79
GND
TP
GND
Page15: Display Port (Analogix ANX9802/ANX9805)
* I2C keeper circuit removed
* ANX9805 support
NO STUFF
NO STUFF
GND
pin 76 - GPIO3 to DP mode, from pin 13, grounded on ANX9802
- place GND resistor away from ANX device if needed
pin 74 - GPIO2, grounded on ANX9802
- place GND resistor away from ANX device if needed
pin 73 - CEC support via FET and pull-up, grounded on ANX9802
- place GND resistor away from ANX device if needed
pin 71 - SPDIF1 - tie to GND, input select 0/1 through internal register
pin 70 - SPDIF0 - support for Audio input, grounded on ANX9802
- place GND resistor away from ANX device if needed
pin 68 - NC - tie to GND
R1000
100
0402
5%
100
NO STUFF
R1002
100
0402
5%
100
STUFF if ANX9802 is used
DNI ONLY IF using ANX9805
NO STUFF
DP_GPIO3
R1001
0402
5%
R1003
0402
5%
DP_GPIO2
DP_CEC
DP_SPDIF_0
0
NO STUFF
5%
STUFF ONLY IF using ANX9805
R1004
0402
GPIO3_DP_PIN13
19>
27< 16<
14< 14>
100
NO STUFF
16>
12>
NO STUFF
GND
R711
0402
5%
GND
17> 17<
14>
14<
14>
14<
14>
17<>
17<
14<
14<
14<
16<
16<
14>
14>
16<>
16>
27<> 23<
27> 23<>
16<
16< 16>
3V3_F
NO STUFF
3V3_F
1V8
NO STUFF
4.7UF
6.3V
10%
X5R
0603
C56
4.7UF
6.3V
10%
X5R
0603
GND
GND
GND
LB5
220R@100MHz
NO STUFF
C951
4.7UF
6.3V
10%
X5R
0603
NO STUFF
LB6
220R@100MHz
NO STUFF
BEAD_0603
BEAD_0603
GND
C28C21
4.7UF
6.3V
10%
X5R
0603
NO STUFF
C38
4.7UF
6.3V
10%
X5R
0603
NO STUFF
C44
4.7UF
10%
X5R
0603
NO STUFF
DP_AVDD33
C980 C979 C978 C981C975
C973
.1UF
16V
10%
X5R
0402
NO STUFF
C959
.1UF
16V
10%
X5R
0402
NO STUFF
DP_DVDD18
C37
1UF
6.3V6.3V
10%
X5R
0402
NO STUFF
.01UF
16V
10%
X5R
0402
NO STUFF
C976
.1UF
16V
10%
X5R
0402
NO STUFF
C954
.1UF
16V
10%
X5R
0402
NO STUFF
.01UF
16V
10%
X5R
0402
NO STUFF
C960
.01UF
16V
10%
X5R
0402
NO STUFF
C49
.1UF
16V
10%
X5R
0402
NO STUFF
.01UF
16V
10%
X5R
0402
NO STUFF
C964
.01UF
16V
10%
X5R
0402
NO STUFF
C53
.01UF
16V
10%
X5R
0402
NO STUFF
12MIL
1000PF
16V
10%
X7R
0402
NO STUFF
C45
.01UF
16V
10%
X5R
0402
NO STUFF
12MIL
1000PF
16V
10%
X7R
0402
NO STUFF
R715
20K
1%
0402
NO STUFF
R31
100K
5%
0402
NO STUFF
R30
100K
5%
0402
NO STUFF
DP_MODE_RC
1
DP_HPD_F
10
3
GND
D3
RCLAMP0524
15KV/8KV
DUAL
NO STUFF
R18
10K
5%
0402
NO STUFF
R19
47K
5%
0402
NO STUFF
DP_AUX_Q*
DP_AUX_Q
DP_L3_C*
DP_L3_C
DP_L2_C*
DP_L2_C
DP_L1_C*
DP_L1_C
DP_L0_C*
DP_L0_C
21
7
9
GND
D3
RCLAMP0524
15KV/8KV
DUAL
NO STUFF
DP_CEC
STUFF ONLY IF using ANX9805
RC=100ns
C982
100PF
50V
5%
C0G
0402
NO STUFF
R16
1%
DP_MODE_R
1K
NO STUFF0402
GND
RC=100ns
C26
100PF
50V
5%
C0G
0402
NO STUFF
R17
0402
1%
1K
NO STUFF
DP_HPD_R
GND
1
1
1
1
1
1
1
1
1
1
21
9
7
GND
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
54
10
6
3
3
GND
D2
RCLAMP0524
15KV/8KV
DUAL
NO STUFF
DP_AUX_Q
DP_AUX_Q
DP_L3_C
DP_L3_C
DP_L2_C
DP_L2_C
DP_L1_C
DP_L1_C
DP_L0_C
DP_L0_C
54
6
3
D2
RCLAMP0524
15KV/8KV
DUAL
NO STUFF
Place near DP Connector's Pins.
12V_PEX6_F
3V3_F
R1005
27K
5%
0402
NO STUFF
1
DP_CABLE_CEC_L
3
Q1000
BSS138
SOT23_1G1D1S
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
1G1D1S
NO STUFF
3
3V3_F
2
1
GND
D1010
BAV99
SOT23
100V
100MA
NO STUFF
LB3
240R@100MHz
LB4
BEAD_0402
240R@100MHz
10
3
GND
D1
RCLAMP0524
15KV/8KV
DUAL
NO STUFF
LB1000
240R@100MHz
EMC
NO STUFFBEAD_0402
DP_MODE
C16
220PF
50V
5%
C0G
0402
NO STUFF
GND
EMC
NO STUFF
C17
220PF
50V
5%
C0G
0402
NO STUFF
GND
J1
DISPLAYPORT
RECEPTACLE
NORM
NO STUFF
DP_HPD
18
17
15
12
10
9
7
6
4
3
1
DP_MODE
DP_HPD
5
21
9
BEAD_0402
4
6
7
3
GND
D1
RCLAMP0524
15KV/8KV
DUAL
NO STUFF
DP_CABLE_CEC
NO STUFF
ESD
NETNAME
DP_AUX*
DP_AUX
DP_AUX_C*
DP_AUX_C
DP_AUX_Q*
DP_AUX_Q
DP_L3*
DP_L3
DP_L2*
DP_L2
DP_L1*
DP_L1
DP_L0*
DP_L0
600-10393-0004-100 A
p393_a01
whill
DIFF_PAIR
DP_AUX
DP_AUX
DP_AUX_C
DP_AUX_C
DP_AUX_Q
DP_AUX_Q
DP_L3
DP_L3
DP_L2
DP_L2
DP_L1
DP_L1
DP_L0
DP_L0
DP_PWR
21
23
25
20
19
16
14
13
11
8
5
2
22
24
26
GND
NV_IMPEDANCE
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
GND
DP_MODE
NO STUFF
C12
.1UF
50V
10%
X7R
0603
NO STUFF
0
15 OF 27
GND
R1006
0402
5%
NV_CRIT_NET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
28-SEP-2007
R15
100K
1%
0402
NO STUFF
GND
Page 16
Page16: MISC: GPIO, I2C, BIOS, PLL, and XTAL
INININININININININININININININININININININININININININININININININININININININ
OUT
16/24 XTAL
XTALOUTBUFF
XTALOUT
XTALSSIN
XTALIN
IN
OUT
OUTBIOUT
VCC
VCC
GND
GND
SCL
SDA
NC
SDA
IN
17/24 I2C
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CS_SCL
I2CS_SDA
I2CH_SDA
BI
S
D
G
INININ
OUT
OUT
OUTINININOUT
S
D
G
18/24 GPIO
GPIO<0>
GPIO<1>
GPIO<2>
GPIO<8>
GPIO<11>
GPIO<12>
GPIO<7>
GPIO<6>
GPIO<14>
GPIO<13>
GPIO<10>
GPIO<9>
GPIO<5>
GPIO<4>
GPIO<3>
VCC
GND
HOLD
WP
CS
SI
SCK
SO
OUT
BI
11/24 PLLVDD
VID_PLLVDD_NC
VID_PLLGND
H_PLLAVDD
VID_PLLAVDD
PLLVDD
PLLAVDD
PLLGND
OUTINOUT
OUT
24/24 MISC
ROM_SCLK
BUFRST
ROMCS
ROM_SI
ROM_SO
STEREO
TESTMODE
CLAMP
SWAPRDY_A
SPDIF
RFU
RFU
RFU
RFU
RFU
RFU
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
PLLVDD/VID_PLLVDD
G1
G92-300-A1
BGA1148
COMMON
1V2
GND
1V2
GND
1V2
GND
C918
4.7UF
6.3V
10%
X5R
0603
COMMON
C909
4.7UF
6.3V
10%
X5R
0603
COMMON
C680
4.7UF
6.3V
10%
X5R
0603
COMMON
LB506
240R@100MHz
LB507
BEAD_0402
240R@100MHz
LB502
BEAD_0402
240R@100MHz
COMMONBEAD_0402
COMMON
COMMON
C896
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C897
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C679
1UF
6.3V
10%
X5R
0402
COMMON
GND
C817
1UF
6.3V
10%
X5R
0402
COMMON
C844
1UF
6.3V
10%
X5R
0402
COMMON
C701
1UF
6.3V
10%
X5R
0402
COMMON
SNN_GPU_VID_PLLVDD
GPU_VID_PLLAVDD
C825
.1UF
10V
10%
X5R
0402
COMMON
Fix for G92 NC pins issue
GPU_PLLAVDD
C839
.1UF
10V
10%
X5R
0402
COMMON
GPU_H_PLLAVDD
C682
.1UF
10V
10%
X5R
0402
COMMON
AB11
AC12
AA12
AC11
AB12
AF29
AD12
I2CC / I2CH(+ HDCP ROM) / I2CS
G1
G92-300-A1
BGA1148
COMMON
P9
U9
V9
AE1
AE2
* Weak pull-ups needed if the GPU
is isolated from the SMBus
I2CS isolation for Hybrid Power
I2CS_SCL_Q
I2CC_SCL_R
I2CC_SDA_R
R65
47K
5%
0402
COMMON
3V3_F
3V3_F
R74
47K
5%
0402
COMMON
I2CC_SCLP8
I2CC_SDA
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA
0402
R85
0402
5%
5%
3V3_F
33R88
COMMON
33
COMMON
1
1G1D1S
Q1212
SOT23_1G1D1S
BSS138
NO STUFF
3
2
MAX_VOLTAGE=50V
MAX_CURRENT=0.88A
R_DS_ON=3.5R
V_BE_GS=+/-20V
CONTINUOUS_CURRENT=0.22A@31C
MAX_WATTAGE=0.36W@25C
I2CS_SCL_R
3V3_F
3V3_F
R78
R81
2.2K
2.2K
5%
5%
0402
0402
COMMON
COMMON
R691 U503
10K
5%
0402
COMMON
R668
10K
5%
0402
COMMON
GND
R66
0402
5%
R75
0402
5%
16< 2<
27>
I2CH_SCL
I2CH_SDA
SNN_CRYPT
33
NO STUFF
33
NO STUFF
I2CS_ENABLE
15<>
6
5
3
2
I2CS_SCL_Q
I2CS_SDA_Q
1
0
R1217
COMMON
0402
5%
ROM / MISC
G1
G92-300-A1
AB1
AC3
AC9
AB7
AB6
AC7
AB5
BGA1148
COMMON
17<
17>
SPDIFIN_F
SNN_GPU_RFU1
SNN_GPU_RFU2
SNN_GPU_RFU3
SNN_GPU_RFU4
SNN_GPU_RFU5
SNN_GPU_RFU6
(BUFRST/STEREO/SWAPRDY/CLAMP/TESTMODE)
19>
16<
16<
19>
16<
3V3_F
R686
10K
5%
0402
AC4
AB2
AA3
AA1
U5
Y12
N9
R12
ROM_CS*
ROM_SI
ROM_SO
ROM_SCLK
GPU_BUFRST*
STEREO
GPU_SWAPRDY
SNN_GPU_5V_CLAMP
GPU_TESTMODEV1
COMMON
13<
R89
10K
5%
0402
COMMON
GND
GND
R666
10K
5%
0402
COMMON
3V3_F
R53
1K
1%
0402
COMMON
7
3
1
5
2
6
U4
MX25L1005
SO8
SO8
COMMON
15<
14<>
16<
8
4
16<
3V3_F
GND
C922
.1UF
10V
10%
X5R
0402
COMMON
GPIO
G1
G92-300-A1
BGA1148
COMMON
www.vinafix.vn
I2CS_SDA_Q
GPIO0_DVIAB_HPD
N3
GPIO1_DVICD_DP_HPD
U3
SNN_GPIO2
T4
GPIO3_DP_PIN13
R2
GPIO4_FAN_PWM
N1
GPIO5_VSEL0
T3
GPIO6_VSEL1
T5
GPIO7_FAN_TACH
P1
GPIO8_THERM_OVERT*
M2
GPIO9_THERM_ALERT*
N2
GPIO10_DP_INT*
R1
GPIO11_RASTER_SYNC
R3
GPIO12_POWER_ALERT*
P3
SNN_GPIO13
T2
SNN_GPIO14
U4
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
MISC: GPIO, I2C, BIOS, PLL, and XTAL
1G1D1S
NO STUFF
SOT23_1G1D1S
2
R_DS_ON=3.5R
CONTINUOUS_CURRENT=0.22A@31C
MAX_WATTAGE=0.36W@25C
MAX_VOLTAGE=50V
MAX_CURRENT=0.88A
V_BE_GS=+/-20V
R1218
0402
5%
Q1214
BSS138
0
COMMON
3
I2CS_SDA_R
12>
12> 15> 27<
15>
17< 16<
23<
16<
23<
16<
17>
16<
16<
15>
26>
23>
17<
16<
17<>
16< 15<
HDCP_KEYROM_PROGD_V3
SO8
COMMON
27>
GND
16< 2<
R54
10K
5%
0402
COMMON
MISC NET RULES
NET
I2CC_SCL
I2CC_SDA
15<>
23>
16>
16<>
27<>
16<>
17<>
16>
27>
19>
19>
16>
17<
23<
23<
17>
17<
16<
15<
16> 2<
16>
16<
16>
15<
14<>
16>
16>
16>
16<
16>
16<
15>
14<>
2< 16<>
27> 23<> 17<
27<> 23< 17<>
27> 23<>
27<> 23<
3V3_F
8
7
4
1
C921
.1UF
10V
10%
X5R
0402
COMMON
GND
I2CC_SCL_R
I2CC_SDA_R
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA
I2CS_SCL_R
I2CS_SDA_R
ROM_CS*
ROM_SI
ROM_SO
ROM_SCLK
GPU_BUFRST*
GPU_STEREO
GPU_SWAPRDY
GPU_TESTMODE
GPIO0_DVI_A_HPD
GPIO1_DVI_C_HPD
GPIO4_FAN_PWM
GPIO5_VSEL0
GPIO6_VSEL1
GPIO7_FAN_TACH
GPIO8_THERM_OVERT*
GPIO9_THERM_ALERT*
GPIO10_DP_INT*
GPIO11_RASTER_SYNC
GPIO12_POWER_ALERT
GPIO13_DP_KEEP
XTAL_SSIN
XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
NET
GPU_VID_PLLVDD
GPU_VID_PLLAVDD
GPU_PLLVDD
GPU_PLLAVDD
GPU_H_PLLAVDD
1.2V
1.2V
1.2V
1.2V
1.2V
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
0.05A
0.05A
0.05A
0.05A
0.05A
DIFFPAIRNV_IMPEDANCENV_CRITICAL
MIN_WIDTHMAX_CURRENTVOLTAGE
12MIL
12MIL
12MIL
12MIL
12MIL
XTAL
G1
G92-300-A1
BGA1148
27<>
3V3_F
R90
10K
5%
0402
COMMON
GND
XTAL_SSIN
R92
10K
5%
0402
COMMON
16<
16<
14<>
17<>
16<
COMMON
XTAL_OUT
AC1
XTAL_OUTBUFFAB3
C77
22PF
50V
5%
C0G
0402
COMMON
GND
AD2
AD1
XTAL_4PIN
27 MHZ
XTAL_IN
C78
22PF
50V
5%
C0G
0402
COMMON
GND
Y1
H10SSMD
10 PPM 85C
COMMON
GPIO Assignment Table
Function
I/O
GPIO
0
1
2
3
4
5
6
23> 17<
7
8
9
10
11
12
13
14
DVI Hotplug Detect South
IN
DVI or DP Hotplug Detect Mid
IN
Framelock Interrupt
IN
Framelock GPIO/DP Dongle Detect
BI
Fan PWM Output
OUT
Voltage Select 0
OUT
Voltage Select 1
OUT
Fan Tach Input
IN
THERM_OVERT*
OUT
THERM_ALERT*
IN
DisplayPort Interrupt
IN
RASTER (SLI) SYNC
OUT
POWER_ALERT*
IN
DP I2C Keeper
OUT
Framelock Sync
IN
600-10393-0004-100 A
p393_a01
whill
* only stuff R91 for DP support
DP_XTAL_IN
33
R91
NO STUFF
0402
5%
15<
16 OF 27
28-SEP-2007
Page 17
Page17: Thermal Control/Protection and SPDIF Input
OUT
OUT
S
D
G
INININININININININININ
OUT
OUTBIIN
IN
V+
V-
OUT
S
D
G
S
D
G
V+
V-
PWM1/XTO
TACH1
VCC
PWM3
TACH3
TACH2
PWM2/ALERT*
GPIO/THERM*
D1+
SDA
VCCP
SCL
D1-
D2+
GND
D2-
IN
BI
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
IN
IN
19/24 THERMAL
THERMDN (CATHODE)
THERMDP (ANODE)
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
THERMAL PROTECTION
SOT23_1G1D1S
NO STUFF
MAX_VOLTAGE=50V
R_DS_ON=3.5R
MAX_CURRENT=0.88A
V_BE_GS=+/-20V
THERM_OVERT
BSS138
GND
Q7
3
2
UC_3V3
R60
0402
1G1D1S
5%
R1211
10K
5%
0402
COMMON
1G1D1S
1
1K
NO STUFF
1
THERM_LATCH
CONTINUOUS_CURRENT=0.22A@31C
THERM_OVERT_R
GND
3
Q1208
BSS138
SOT23_1G1D1S
COMMON
2
GND
THERM_LATCH*
Thermal protection
23>
16<
16>
handled by the ADT7473-1
3V3_F
GPIO8_THERM_OVERT*
R62
10K
5%
0402
COMMON
10K
R57
0402 NO STUFF
5%
1G1D1S
CONTINUOUS_CURRENT=0.22A@31C
MAX_WATTAGE=0.36W@25C
3V3_F
R56
10K
5%
0402
NO STUFF
3
Q4
BSS138
SOT23_1G1D1S
1
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
IFP_IOVDD_EN*
1
3
Q10
BSS138
SOT23_1G1D1S
COMMON
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
1G1D1S
27> 2<
GPU_RST*
R71
0402
5%
1K
COMMON
GPU_RST_R*
GND
C69
100PF
50V
5%
C0G
0402
COMMON
TMDS BACKDRIVE PREVENTION
Stuffing posibilities for thermal control and protection:
2) ADT7473 is COMMON
GPIO4 is not used.
GPIO7 is the tach input from the fan
GPIO9 is the thermal alert for GPU slowdown.
With a newer version of the ADT chip, PWM2 can optionally be used for shutdown
3V3_F
BSS138
SOT23_1G1D1S
NO STUFF
MAX_VOLTAGE=50V
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
1G1D1S
1
C65
100PF
50V
5%
C0G
0402
NO STUFF
IFP_IOVDD_EN
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
3
Q8
2
12V
R68
10K
5%
0402
NO STUFF
Q5
BSS138
SOT23_1G1D1S
NO STUFF
R84
10K
5%
0402
COMMON
3
2
1G1D1S
1
PU placed at power
detection circuit
THERM_SHUTDOWN*
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
1
1G1D1S
1G1D1S
1
3V3_F
2
Q9
RTR040N03
SOT23_1G1D1S
COMMON
3
IFP_IOVDD_Q
3.3V
0.35
16MIL
3
Q1207
RTR040N03
SOT23_1G1D1S
COMMON
2
GND
IFP_IOVDD
C67
1000PF
16V
10%
X7R
0402
COMMON
GND
SPDIF INPUT / DETECTION
17>
26<
SPDIFIN_COMP_R
V_BE_GS=12V
MAX_WATTAGE=1W@25C
MAX_CURRENT=16A
R_DS_ON=0.066R@2.5V
CONTINUOUS_CURRENT=4A@25C
MAX_VOLTAGE=30V
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=4A@25C
R_DS_ON=0.066R@2.5V
MAX_CURRENT=16A
MAX_WATTAGE=1W@25C
V_BE_GS=12V
C76
.1UF
16V
10%
X5R
0402
COMMON
GND
R741
0402
1%
5V
R2
1.5K
1%
0402
COMMON
R1
1K
1%
0402
COMMON
GND
1K
COMMON
1N4148
COMMON
R738
0402
C1004
1UF
6.3V
10%
X5R
0402
COMMON
SPDIFIN_COMP_R1
SPDIFIN_C3
3 1
D509
SOT23
SPDIFIN_COMP
330
COMMON
5%
R743
0402
1%
COMMON
OPA2830
COMMON
7.15K
NO STUFF
U1
SO8
1
5V
U1
OPA2830
8
SO8
6
COMMON
7
5
4
GND
THERMAL CONTROL
0
R63
COMMON
0402
5%
0
R64
COMMON
0402
5%
0
R83
COMMON
0402
5%
0
R82
NO STUFF
0402
3V3_F
C74
.1UF
16V
10%
X5R
0402
COMMON
3
GND
15
6
THERM_ALERT*
5
GPIO9_THERM_ALERT_R*
9
SNN_THERM_TACH2_NC
7
THERM_PWM3_ADDR_EN*
8
SNN_THERM_TACH3_NC
4
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Thermal Control/Protection and SPDIF Input
3V3_F
C66
.1UF
16V
10%
X5R
0402
COMMON
I2CC_SCL_R
I2CC_SDA_R
THERM_DP_R
THERM_DN_R
3V3_F
U5
ADT7473ARQZ
XSOP16
COMMON
14
GND
1
16
13
12
11
10
2
GND
www.vinafix.vn
G92-300-A1
BGA1148
COMMON
G1
10MIL
THERM_DN
T1
10MIL
THERM_DP
U1
R86
0402
R87
0402
0
COMMON
5%
0
COMMON
5%
C73
100PF
50V
5%
C0G
0402
COMMON
27> 23<>
27<> 23<
16<
16<
16> 15<>
16<> 15<
10MIL
10MIL
3V3_F
1
R61
10K
5%
0402
COMMON
5%
3
D507
BAT54C
25V
200MA
SOT23
2
COMMON
The ADT7473-1 requires a pull-up
to disable address select
R735
0
0402
5%
5V
8
2
SPDIFIN_C2
3 SPDIFIN_C
4
GND
placed near op-amp
SPDIFIN_COMP2
C1006
.01UF
16V
10%
X7R
0402
COMMON
GND
THERM_SHUTDOWN*
GPIO7_FAN_TACH
GPIO9_THERM_ALERT*
GPIO4_FAN_PWM
3V3_F
R680
10K
5%
0402
COMMON
3V3_F
5V
R669
10K
5%
0402
COMMON
NO STUFF
R740
10K
5%
0402
NO STUFF
R736
1K
1%
0402
GND
5V
C1
.1UF
16V
10%
X5R
0402
COMMON
GND
GPIO4_FAN_PWM_R
GPIO7_FAN_TACHIN_R
17>
16<
16<
16<
GND
26<
16>
5V
R727
6.2K
5%
0402
COMMON
GND
R726
10K
1%
0402
COMMON
C135
.47UF
16V
10%
X5R
0603
COMMON
17>
17>
C983
0402
27>
12V_PEX6_F
GND
16<
15<
1
2
3
4
.01UF
16V
10%
X7R
COMMON
FAN
J7
HDR_1M4
MALE
2.0MM
N/A
NORM
COMMON
SPDIFIN
SPDIFIN_C
SPDIFIN_C2
SPDIFIN_COMP
SPDIFIN_COMP_R
SPDIFIN_COMP_R1
SPDIFIN_C3
SPDIFIN_COMP2
SPDIFIN_COMP2_Q
SPDIFIN_F
DP_SPDIF_0
Updated with smaller footprint,
black, SPDIF connector
HDR_1M2
MALE
2.0MM
NORM
CHANGED
IMPEDANCENET
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM 1
50OHM
56OHM 1
1
J6
90
SPDIFIN
2
GND
SPDIFIN_COMP2_Q
1G1D1S
1
NV_CRITICAL_NET
C34
0402
C1100
0402
3
Q1
RHK003N06
SOT23_1G1D1S
COMMON
2
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.3A@25C
R_DS_ON=1.5R
MAX_CURRENT=1.2A
MAX_WATTAGE=0.2W@25C
V_BE_GS=+/-20V
R20
75
5%
0805
COMMON
156OHM
1
150OHM
1
1
1
1
1
156OHM
.01UF
16V
10%
X7R
COMMON
.01UF
16V
10%
X7R
NO STUFF
GND
The FAN connector needs to move
as follows for mechanical / ID support:
* move -43mils in Y
* move +33mils in X
600-10393-0004-100 A
p393_a01
whill
MIN_LINE_WIDTH
3V3_F
2
D9
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
SPDIFIN_F
DP_SPDIF_0
* STUFF ONLY IF using ANX9805
R25
75
5%
0805
NO STUFF
GND
17< 16<
17< 15<
17 OF 27
28-SEP-2007
Page 18
Page18: Power/GND and Decoupling
22/24 GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
OUT
OUT
20/24 VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD_SENSE
GND_SENSE
6/24 FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
VDD33
21/24
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
7/24 VTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
IN
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
VDD33
G1
G92-300-A1
BGA1148
COMMON
N11
P11
G1
G92-300-A1
BGA1148
COMMON
23< 18>
23< 18>
FBVTT
R11
N12
AH15
AJ16
AK16
AJ17
AK17
AH1
AH2
AE3
AF3
AH3
AJ3
AD4
AF4
AG8
AE21
AF23
AP23
AJ26
SNN_FBVTT_NC1M12
SNN_FBVTT_NC2
M13
SNN_FBVTT_NC3
M15
SNN_FBVTT_NC4
M16
SNN_FBVTT_NC5
M17
SNN_FBVTT_NC6
M20
SNN_FBVTT_NC7
M21
SNN_FBVTT_NC8
M22
SNN_FBVTT_NC9
AE22
SNN_FBVTT_NC10
AE23
SNN_FBVTT_NC11
M24
SNN_FBVTT_NC12
AE24
SNN_FBVTT_NC13
M25
SNN_FBVTT_NC14
N25
SNN_FBVTT_NC15
R25
SNN_FBVTT_NC16
T25
SNN_FBVTT_NC17
U25
SNN_FBVTT_NC18
Y25
SNN_FBVTT_NC19AA25
SNN_FBVTT_NC20
AB25
SNN_FBVTT_NC21
AD25
SNN_FBVTT_NC22
AE25
PS3_NVVDD_VSENP_R
PS3_NVVDD_VSENN_R
SNN_GPU_NC0
SNN_GPU_NC1
SNN_GPU_NC2
SNN_GPU_NC3
SNN_GPU_NC4
SNN_GPU_NC5
SNN_GPU_NC6
SNN_GPU_NC7
SNN_GPU_NC8
SNN_GPU_NC9
SNN_GPU_NC10
SNN_GPU_NC11
SNN_GPU_NC12
C826
.47UF
6.3V
10%
X5R
0402
COMMON
1UF
6.3V
10%
X7R
0603
COMMON
C126
10UF
20%
X5R
0805
COMMON
C124
10UF
6.3V
20%
X5R
0805
COMMON
C801
1UF
6.3V
10%
X5R
COMMON
C789 C816C848
1UF
6.3V
10%
X5R
COMMON
C125
20%
X5R
0805
COMMON
C116
10UF
6.3V
20%
X5R
0805
COMMON
80DIFF1
80DIFF1
3V3_F
C833
.1UF
10V
10%
X5R
04020402
COMMON
.1UF
10V
10%
X5R
04020402
COMMON
10UF10UF
6.3V6.3V 6.3V 6.3V
20%
X5R
0805
C89
10UF
6.3V
20%
X5R
0805
COMMON
DIFFPAIRNV_IMPEDANCENV_CRITICALNET
NVVDD_SENSE
NVVDD_SENSE
C803
.47UF
6.3V
10%
X5R
0402
COMMON
C119C127
10UF
20%
X5R
0805
COMMONCOMMON
C117
10UF
6.3V
20%
X5R
0805
COMMON
GND
GND
GND
GND
FBVDDQ
FBVDD
Place near BGA
GND
C91
10UF
6.3V
20%
X5R
0805
COMMON
C85
10UF
20%
X5R
0805
COMMON
C94
10UF
6.3V
20%
X5R
0805
COMMON
C113
10UF
6.3V
20%
0805
COMMON
C732
.47UF
6.3V
10%
X5R
0402
COMMON
C706
.47UF
6.3V
X5R
0402
COMMON
C796
.47UF
6.3V
10%
X5R
0402
COMMON
C723
.47UF
6.3V
10%
X5R
0402
COMMON
C750
.47UF
6.3V
10%
X5R
0402
COMMON
C698
4.7UF
6.3V
10%
X5R
0603
COMMON
C776
.1UF
10V
10%
0402
COMMON
C892
47UF
6.3V
20%
X5R
1206
COMMON
GND
C97
10UF
6.3V
20%
0805
COMMON
C80
10UF
20%
X5R
0805
COMMON
C115
10UF
6.3V
20%
0805
COMMON
C110
10UF
6.3V
20%
X5RX5R
0805
COMMON
C700
1UF
6.3V
10%
X5R
0402
COMMON
C714
1UF
6.3V
X5R
0402
COMMON
C774
.47UF
6.3V
10%
X5R
0402
COMMON
C787
.47UF
6.3V
10%
X5R
0402
COMMON
C713
.47UF
6.3V
10%
X5R
0402
COMMON
C728
4.7UF
6.3V
10%
X5R
0603
COMMON
C709
.1UF
10V
10%
0402
COMMON
C775
1UF
6.3V
10%
X5R
0402
COMMON
C81
10UF
6.3V
20%
X5RX5R
0805
COMMON
C96
10UF
6.3V 6.3V6.3V 6.3V
20%
X5R
0805
COMMON
C114
10UF
6.3V
20%
X5RX5R
0805
COMMON
C111
10UF
6.3V
20%
X5R
0805
COMMON
NVVDD
NVVDD
Place near BGA
C823
.1UF
10V
10%
X5R
0402
COMMON
C804
.1UF
10V
10%10%10%
X5R
0402
COMMON
C786
1UF
6.3V
10%
X5R
0402
COMMON
C824
.47UF
6.3V
10%
X5R
0402
COMMON
C751
.47UF
6.3V
10%
X5R
0402
COMMON
C730
4.7UF
6.3V
X5R
0603
COMMON
C711
.1UF
10V
10%
0402
COMMON
C716
.1UF
6.3V
10%
X7R
0402
COMMON
GND
GND
C82
10UF
6.3V
20%
X5R
0805
COMMON
C90
10UF
20%
X5R
0805
COMMON
C112
10UF
6.3V
20%
X5R
0805
COMMON
C121
10UF
6.3V
20%
X5R
0805
COMMON
C718
1UF
6.3V
10%
X5R
0402
COMMON
C759
.47UF
6.3V
10%
X5R
0402
COMMON
C705
.47UF
6.3V
10%
X5R
0402
COMMON
C720
1UF
6.3V
10%10%
X5R
0402
COMMON
C712
.01UF
6.3V
10%
X7R
0402
COMMON
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Power/GND and Decoupling
C724
1UF
6.3V
10%
X5R
0402
COMMON
C806
1UF
6.3V
10% 10% 10%10%
X5R
0402
COMMON
C769
1UF
6.3V
10%
X5R
0402
COMMON
C783
1UF
6.3V
10%
X5R
0402
COMMON
C744
1UF
6.3V
10%
X5R
0402
COMMON
C807
1UF
6.3V
10%
X5R
0402
COMMON
C815
1UF
6.3V
10%
X5RX5R X5RX5R X5RX5RX5R
0402
COMMON
C755
1UF
6.3V
10%
X5R
0402
COMMON
C734
1UF
6.3V
10%
X5R
0402
COMMON
1UF
6.3V
10%
X5R
0402
COMMON
C719
1UF
6.3V
10%
X5R
0402
COMMON
C118
10UF
6.3V
X5R
0805
COMMON
C79
10UF
6.3V
20%
X5R
0805
COMMON
C106
10UF
6.3V
20%
X5R
0805
COMMON
www.vinafix.vn
C737
1UF
6.3V
10%
X5R
0402
COMMON
C799
1UF
6.3V
X5R
0402
COMMON
C757
1UF
6.3V
10%
X5R
0402
COMMON
C781
1UF
6.3V
10%
X5R
0402
COMMON
C762
1UF
6.3V
10%
X5R
0402
COMMON
C743
1UF
6.3V
10%
X5R
0402
COMMON
C754
1UF
6.3V
10%
0402
COMMON
C761
1UF
6.3V
10%
X5R
0402
COMMON
C721
1UF
6.3V
10%
X5R
0402
COMMON
C715C795
1UF
6.3V
10%
X5R
0402
COMMON
C756
1UF
6.3V
10%
X5R
0402
COMMON
C122
10UF
6.3V
X5R
0805
COMMON
C104
10UF
6.3V
20%
X5R
0805
COMMON
C120
10UF
6.3V
20%
X5R
0805
COMMON
C808
.22UF
6.3V
10%
X5R
0402
COMMON
C779
.22UF
6.3V
X5R
0402
COMMON
C821
.22UF
6.3V
10%
X5R
0402
COMMON
C805
.22UF
6.3V
10%
X5R
0402
COMMON
C784
.22UF
6.3V
10%
X5R
0402
COMMON
C780
.47UF
6.3V
10%
X5R
0402
COMMON
C760
.47UF
6.3V
10%
0402
COMMON
C777
.47UF
6.3V
10%
X5R
0402
COMMON
C794
.47UF
6.3V
10%
X5R
0402
COMMON
C733
.47UF
6.3V
10%
X5R
0402
COMMON
C722
1UF
6.3V
10%
X5R
0402
COMMON
C123
10UF
6.3V
20%20%20% 20%
X5R
0805
COMMON
C105
10UF
6.3V
20%
X5R
0805
COMMON
C99
10UF
6.3V
20%
X5R
0805
COMMON
C809
.22UF
6.3V
10%
X5R
0402
COMMON
C798
.22UF
6.3V
X5R
0402
COMMON
C797
.22UF
6.3V
10%
X5R
0402
COMMON
C764
.22UF
6.3V
10%
X5R
0402
COMMON
C793
.22UF
6.3V
10%
X5R
0402
COMMON
C782
.47UF
6.3V
10%
X5R
0402
COMMON
C735
.47UF
6.3V
10%
0402
COMMON
C747
.47UF
6.3V
10%
X5R
0402
COMMON
C778
.47UF
6.3V
10%
X5R
0402
COMMON
C788
.47UF
6.3V
10%
X5R
0402
COMMON
C758
4.7UF
6.3V
10%
X5R
0603
COMMON
C88
10UF
6.3V
X5R
0805
COMMON
C107
10UF
6.3V
20%
X5R
0805
COMMON
C101
10UF
6.3V
20%
X5R
0805
COMMON
G1
G1
G92-300-A1
BGA1148
COMMON
R14
V14
W14
AB14
P15
R15
T15
V15
W15
AA15
AB15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AC15
R16
T16
V16
W16
AA16
AB16
P18
R18
T18
V18
W18
AA18
AB18
AC18
P19
R19
T19
V19
W19
AA19
AB19
AC19
R21
T21
V21
W21
AA21
AB21
R22
T22
V22
W22
AA22
AB22
AC22
R23
V23
W23
AB23
P23
NVVDD
PS3_NVVDD_VSENP_RP22
PS3_NVVDD_VSENN_R
FBVDD
AF24
AB26
AC26
AD26
AE26
AF26
AA28
AD28
AE28
AA29
L12
L13
J14
L14
J15
L15
J17
L17
J18
L18
J19
L19
J20
L20
J22
L22
J23
L23
L24
L25
M26
N26
P26
R26
U26
V26
W26
Y26
K28
U28
V28
W28
Y28
L29
G1
G92-300-A1
BGA1148
COMMON
23< 18<
23< 18<
GND
G92-300-A1
BGA1148
COMMON
M19
U19
Y19
AE19
AJ19
AL19
AT19
B20
P20
R20
T20
U20
V20
W20
AA20
AB20
AC20
AP20
F21
L21
P21
U21
Y21
AC21
AF21
AR21
D22
H22
U22
Y22
AF22
AK22
AT22
B23
M23
T23
U23
Y23
AA23
AC23
F24
AL24
AP24
D25
H25
P25
V25
W25
AC25
AF25
AJ25
AN25
B26
L26
T26
AA26
AR26
F27
AJ27
AL27
B29
E29
M29
R29
V29
W29
AB29
AG29
AM29
AR29
G30
AK30
K31
N31
T31
AA31
AD31
AG31
B32
E32
H32
AJ32
AM32
AR32
M33
R33
V33
W33
AB33
AE33
B35
E35
H35
L35
P35
U35
Y35
AC35
AF35
AJ35
AM35
AR35
AH14
600-10393-0004-100 A
p393_a01
whill
B2
E2
H2
L2
P2
U2
Y2
AC2
AF2
AJ2
AM2
AP3
M4
R4
V4Y20
W4
AB4
AE4
B5
E5
H5
AJ5
AM5
AR5
K6
N6
T6
AA6
AD6
AG6
AT7
B8
E8
H8
M8
R8
V8
W8
AB8
AE8
AJ8
AM8
AP8
F10
AT10
B11
M11
T11
AA11
AD11
AF11
AK11
AP11
D12
P12
V12
W12
AJ12
AR12
F13
AL13
AT13
B14
H14
M14
P14
T14
U14
Y14
AA14
AC14
AE14
AP14
D15
H15
U15
Y15
AJ15
AR15
F16
L16
P16
U16
Y16
AC16
AF16
AL16
AT16
B17
P17
R17
T17
U17
V17
W17
Y17
AA17
AB17
AC17
AP17
D18
H18
M18
U18
Y18
AE18
AJ18
AR18
D19
H19
18 OF 27
28-SEP-2007
GND
Page 19
Page19: Configuration Straps and Mechanical
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
OUT
OUT
OUT
OUT
12 connected mounting pins
COOLING SOLUTION
4 connected mounting pins
BOARD STIFFENER
No connected mounting pins
SPECIAL MECHANIC
MECH. MOUNTING TOP
2 connected mounting pins
BOARD STIFFENER
STRAPS
3V3_F
5%
5%
5%
5%
5%
5%
5%
5%
5%5%
2.2K
COMMON
2.2K
NO STUFF
2.2K
NO STUFF
2.2K
NO STUFF
2.2K
NO STUFF
2.2K
COMMON
2.2K
COMMON
2.2K
NO STUFF
2.2K
NO STUFF
2V5
STRAP 0
*
02: RAM_CFG[0]
*
03: RAM_CFG[1]
*
04: RAM_CFG[2]
*
05: RAM_CFG[3]
*
13: PCI_DEVID[3]
*
28: PCI_DEVID[4]
*
17: PEX_PLL_EN_TERM100
STRAP 1
*
12: MIO_EN_33V_0
*
13: MIO_EN_33V_1
14<
15< 14<
14>
MIOA_D<14..0>
MIOB_D<12..0>
0
MIOB_D<0>
MIOB_D<1>
MIOB_D<8>
MIOB_D<9>
MIOB_D<11>
MIOB_D<12>
MIOA_D<0>
R44
0402
R45
0402
R41
0402
R37
0402
R35
0402
R674
0402
R48
0402
0
1
8
9
11
12
5%
5%
5%
5%
5%
5%
5%
2.2K
NO STUFF
2.2K
COMMON
2.2K
COMMON
2.2K
COMMON
2.2K
COMMON
2.2K
NO STUFF
2.2K
NO STUFF
MIOB_D<0>
MIOB_D<1>
MIOB_D<8>
MIOB_D<9>
MIOB_D<11>
MIOB_D<12>
MIOA_D<0>
R43
0402
R46
0402
R40
0402
R39
0402
R34
0402
R675
0402
R49
0402
16>
16>
16<
16<
ROM_SI
ROM_SCLK
R673
0402
R670
0402
5%
2.2K
COMMON
2.2K
COMMON
ROM_SI
ROM_SCLK
R672
0402
R671
0402
Samsung
256b
8Mx32
256MB
1
1
1
0
Samsung
256b
16Mx32
512MB
DEVID =
Per G92 Guide (PEX term)..
* Strap definition inverted
- set to 0x1 to enable
- set to 0x0 to disable
DEFAULT = 1 (3.3V)
MIOA = 0 (2.5V)
DEFAULT = 1 (3.3V)
MIOB = 0 (2.5V)
Hynix
256b
8Mx32
256MB
1
1
0
0
0
1
1
0
0x0602 DT0 G92-300 0000 0010
0x0607 DT2 G92-240 0000 0111
0x0611 DT4 G92-270 0001 0001
0x061A WS500 G92-875 0001 1010
0x061B WS501 G92-850 0001 1011
Hynix
256b
16Mx32
512MB
0
1
0
0
Qimonda
256b
16Mx32
512MB
1
0
0
0
4 3
MECHANICAL
BKT1
SS_TAB_DVI3152_DVI1552_MINIDIN489_BLKCOB
ATX_1X_TOP
CHANGED
1
GND
2
1
GND
MEC2
EDGE_STIFFENER_P356_NONHYBRID
2PIN
NO STUFF
Top edge stiffener
MEC1
PEX_RET_BRKOFF
NOPIN
NO STUFF
Hockey stick
MEC5
HEX_JACK_SCREW
STD
COMMON
MEC6
HEX_JACK_SCREW
STD
COMMON
MEC7
HEX_JACK_SCREW
STD
COMMON
MEC8
HEX_JACK_SCREW
STD
COMMON
MEC9
PH_4_40X.1875_SCREW
STD
COMMON
13
MIOA_D<13>
R52
0402 NO STUFF
GND
MIOA_D<13>
2.2K
5%
R50
0402
2.2K
COMMON
5%
*
15: SLOT_CLK_CFG
DISABLE = 0; ENABLE = 1
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Configuration Straps and Mechanical
www.vinafix.vn
123
4
GND
123547689
GND
111012
MEC3
G92 GPU STIFFENER
4PIN
NO STUFF
Need G92 GPU stiffener symbol
(currently local in the .brd)
MEC4
TM68
12PIN
NO STUFF
Need board extender symbol
(currently local in the .brd)
600-10393-0004-100 A
p393_a01
whill
19 OF 27
28-SEP-2007
Page 20
Page20: Power Supply: 5V, STEREO_5V, 2V5, DP_PWR
S
D
G
POLYSWITCH
POLYSWITCH
POLYSWITCH
OUT
TAB
GND/ADJ
IN
OUT
TAB
GND/ADJ
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
5V and DDC5V Supply
12V_PEX6_F
C25
4.7UF
25V
10%
X5R
1206
5V STEREO Supply
COMMON
GND GND
C29
.1UF
16V
10%
X7R
0603
COMMON
1
U506
MC7805ECDTX
VR=5V
IGO,IGOI
COMBINED_IGO
COMMON
4
2
GND GND
3
C27
.1UF
10V
10%
X5R
0402
COMMON
5V
5V
0.2A
16MIL
C24
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
1
F3
200mA
1206
COMMON
DDC_5V
5V
0.15A
2
16MIL
C19
220PF
50V
5%
C0G
0603
COMMON
GND
2V5 Supply
2V5
GND
DP_PWR
2.5V
1.5A
16MIL
C47
100UF
COMMON
+/-20%
4.0V
POSCAP
1.4A
0.035R
SMD_3528
C966
4.7UF
6.3V
10%
X5R
0805
COMMON
GND
C52
100UF
NO STUFF
+/-20%
4.0V
POSCAP
1.4A
0.035R
SMD_3528
GND GND
2V5 = Vref * (1 + Rt/Rb)
2.495V = 2.495V * (1 + 0/oo)
2.500V = 2.495V * (1 + 2.2/1000)
C946
10UF
6.3V
20%
X5R
0805
COMMON
C945
.1UF
16V
10%
X5R
0402
COMMON
GND
3V3_F
C968
.1UF
16V
10%
X5R
0402
COMMON
GND
AOD408L
COMBI_MONO_1G2D1S
Rt
Rb
Q512
COMMON
1G2D1S
4
2
3
R699
0
5%
0402
COMMON
R698
1K
5%
0402
NO STUFF
12MIL
2V5_G
1
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=18A@25C,18A@70C
R_DS_ON=0.018R
MAX_CURRENT=40A
MAX_WATTAGE=60@25C,33W@100C
V_BE_GS=+/-20V
12MIL
2V5_ADJ
12V_PEX6_F
2
1
3
GND
R708
5.1K
5%
0402
COMMON
U504
SC431
ADJ_VR2.495
SOT23
SOT23
COMMON
12V_PEX6_F
GND
C18
4.7UF
25V
10%
X5R
1206
NO STUFF
U505
MC7805ECDTX
VR=5V
IGO,IGOI
COMBINED_IGO
NO STUFF
1
C22
.1UF
16V
10%
X7R
0603
NO STUFF
GND
2
GND
STEREO_5V_OUT3
C23
.1UF
10V
10%
4
X5R
0402
NO STUFF
GND
5V
0.3A
20MIL
C20
4.7UF
6.3V
10%
X5R
0603
NO STUFF
GND
F2
500mA
1206
NO STUFF
1
STEREO_5V
5V
0.3A
2
20MIL
C13
220PF
50V
5%
C0G
0603
NO STUFF
GND
3V3_F
LB2
220R@100MHz
NO STUFF
BEAD_0603
DP_PWR_F
C15
.1UF
16V
10%
X7R
0402
NO STUFF
3.3V
0.5A
C14
.01UF
16V
10%
X7R
0402
NO STUFF
F1
1A
1812
NO STUFF
120MIL
DP_PWR
3.3V
0.5A
2
20MIL
C6
.1UF
16V
10%
X7R
0402
NO STUFF
C7
.01UF
16V
10%
X7R
0402
NO STUFF
Power for DP dongle support.
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Power Supply: 5V, STEREO_5V, 2V5, DP_PWR
www.vinafix.vn
600-10393-0004-100 A
p393_a01
whill
20 OF 27
28-SEP-2007
Page 21
Page21: Power Supply: 1V2, 1V8
S
D
G
S
D
G
VCC5
UGATE
BOOT
PVCC5
PHASE
LGATE
SW_FB
COMP
LDO_FB
LDO_DR
FS_DIS
VCC12
PGND
GND
S
D
G
S
D
G
S
D
G
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
1V2
C174
100UF
COMMON
+/-20%
4.0V
POSCAP
1.4A
0.035R
SMD_3528
1G2D1S
4
1G2D1S
2
1000PF
16V
10%
X5R
COMMON
12V_PEX6_F
6
5
Q13
FDS6982
SO8_DUAL_1G2D1S
COMMON
3
8
7
Q13
FDS6982
SO8_DUAL_1G2D1S
COMMON
1
GND
PLACE CLOSE TO FET
Input ripple Irms = ~1A
1
2
GND
C161
1UF
25V
10%
X7R
0805
COMMON
GND
D10
IR10MQ040N
SMA
40V
2.1A
COMMON
C160
.47UF
16V
10%
X5R
0603
COMMON
C568
10UF
16V
20%
X5R
1206
COMMON
C564
680PF
50V
5%
C0G
0603
COMMON
PS1_1V2_PH_RC
16MIL
R574
2.2
5%
0805
COMMON
GND
C563
C162
10UF
10UF
16V
16V
20%
20%
X5R
X5R
1206
1206
COMMON
COMMON
PEX 1V15 @ 2.5A
1.15V
2.5A
1 UH
L7
COMMON7_6X7_6
Rtop
Rbot
RIPPLE CURRENT ~1.8A
1V2
R572
1.74K
1%
0402
NO STUFF
R573
4.02K
1%
0402
COMMON
R571
22.1
1%
0402
COMMON
PS1_1V2_FB_RC
R618
1.74K
1%
0402
COMMON
10MIL
C550
4700PF
16V
10%
X7R
0402
COMMON
Remote VSense Options:
Place one Rtop at output
Place one Rtop at GPU, nearest PEX_IOVDDQ
C173
47UF
6.3V
20%
X5R
1206
COMMON
16MIL
C549
100UF
NO STUFF
+/-20%
4.0V
POSCAP
1.4A
0.035R
SMD_3528
GND
U7
RT9259PS
C151
1UF
25V
10%
X7R
0805
COMMON
GND
8PS1_VCC12
5
6
2
12
7
VR_SW=0.8V, VR_LD=0.8V
SO14
SO14
COMMON
10
14
1
13
11
4
3
16MIL
PS1_VCC59
16MIL
PS1_PVCC5
PS1_1V2_UG
PS1_1V2_BOOT
15V
16MIL
PS1_1V2_PH
1.2V
6A
16MIL
PS1_1V2_LG
PS1_1V2_FB
16MIL
16MIL
10MIL
10MILPS1_1V2_CP
R575
10
5%
0603
COMMON
C142
0603
C593
0402
C571
0603
.1UF
25V
10%
X7R
COMMON
1UF
10V
10%
X5R
COMMON
.022UF
16V
10%
X7R
COMMON
R576
0402
5%
PS1_1V2_CP_RC
10MIL
C594
0402
C570
1UF
10V
10%
X5R
0603
COMMON
2.2
COMMON
1000PF
50V
10%
X7R
COMMON
GND
PS1_1V2_UG_R
16MIL
R577
0402
1.74K
COMMON
1%
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=6.3A/8.6A @25C
R_DS_ON=0.035/0.020 @25C
MAX_CURRENT=20A/30A
MAX_WATTAGE=2W @25C
V_BE_GS=+/-20V
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=6.3A/8.6A @25C
R_DS_ON=0.035/0.020 @25C
MAX_CURRENT=20A/30A
MAX_WATTAGE=2W @25C
V_BE_GS=+/-20V
C569
0402
12V_PEX6_F
16MIL
2.2
R124
COMMON
0402
5%
3V3_F
MAX_VOLTAGE=30V
C143
C145
.01UF
10UF
16V
6.3V
10%
20%
X7R
X5R
0402
1V8
1.8V
0.5A
16MIL
C138
10UF
6.3V
20%
X5R
0805
COMMON
GND
C137
10UF
6.3V
20%
X5R
0805
COMMON
GND
0805
COMMON
GND
GND
C140
.1UF
16V
10%
X7R
0402 0603
COMMON
C139
4.7UF
6.3V
10%
X5R
COMMON
GNDGND
COMMON
RTQ045N03
TSOP6_1G4D1S
CONTINUOUS_CURRENT=4.5A
R_DS_ON=0.043@4.5V
MAX_CURRENT=18A
MAX_WATTAGE=1.25W
V_BE_GS=12V
6
5
2
1
1G4D1S
Q12
COMMON
4
R583
1.62K
Rt
1%
0402
COMMON
R582
1.3K
Rb
1%
0402
COMMON
GND
1V8 power = 0.8V * (1 + Rt / Rb)
1.8 = 0.8V * ( 1+ 1.62k / 1.3k)
PS1_1V8_DR_R
3
10MIL
R581
0402
COMMON
PS1_1V8_DR
R578
2.7K
0
5%
5%
0402
COMMON
PS1_1V8_FB_RC
C592
1000PF
50V
10%
X7R
0402
COMMON
Short to disable LDO
DNI all else
10MIL
PS1_1V8_FB
10MIL
PS1_FS
10MIL
FREQ_SET = 47.5K FOR 600KHz
FREQ_SET = 110K FOR 300KHz
GND
R580
47K
5%
0402
COMMON
GND
12V_PEX6_F
1G1D1S
10< 11< 23< 26< 26> 27>
PS3_OUTEN
1
R1206
10K
5%
0402
NO STUFF
PS1_EN*
3
Q1205
BSS138
SOT23_1G1D1S
NO STUFF
2
GND
HYBRID->1V2 Sequencing
1G1D1S
1
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
3
Q1206
BSS138
SOT23_1G1D1S
NO STUFF
2
GND
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
www.vinafix.vn
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Power Supply: 1V2, 1V8
GND
PEX_VDD = 0.8 * (Rt+Rb)/Rb
1.20 = 0.8 * (2000+4020)/4020
1.15 = 0.8 * (1740+4020)/4020
1.10 = 0.8 * (1500+4020)/4020
600-10393-0004-100 A
p393_a01
whill
21 OF 27
28-SEP-2007
Page 22
Page22: Combined FBVDD/VDDQ, 8V5
S
D
G
S
D
G
S
D
G
VCC5
UGATE
BOOT
PVCC5
PHASE
LGATE
SW_FB
COMP
LDO_FB
LDO_DR
FS_DIS
VCC12
PGND
GND
S
D
G
S
D
G
S
D
G
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
12V_F
Input Ripple Irms = ~7A
3
SOT23
BAV99
5%
1UF
16V
10%
X5R
COMMON
SNN_FB_AC
100V
100MA
NO STUFF
0
COMMON
R537
2
C199
10UF
16V
X5R
NO STUFF
0402
GND
C512
4.7UF
6.3V
10%
X5R
0603
COMMON
2.2
COMMON
5%
R515
470
5%
0402
NO STUFF
C202
180UF
COMMON20%
+/-20%
16V1206
OSCON
3.64A@105C
0.020R
COMBI_7343_D80
GND
GND
Place close to PVCC5 pin
PS2_UGATE_R
16MIL
PS2_LGATE_AC
LFPAK
4
5
Q26
RJK0303DPB
LFPAK
COMMON
1
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=40A
2
R_DS_ON=0.0056R MAX
MAX_CURRENT=160A
3
MAX_WATTAGE=55W
V_BE_GS=16V
GND
C208
180UF
COMMON
+/-20%
16V
OSCON
3.64A@105C
0.020R
COMBI_7343_D80
GND
LFPAK
LFPAK
416MIL
4
Place near drain of top FET
Near FET
C197
.47UF
16V
10%
X5R X5R
0603
COMMON
5
Q24
RJK0305DPB
LFPAK
COMMON
1
2
3
5
Q25
RJK0303DPB
LFPAK
COMMON
1
2
3
GND
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=30A
R_DS_ON=0.013R MAX
MAX_CURRENT=120A
MAX_WATTAGE=45W
V_BE_GS=16V
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=40A
R_DS_ON=0.0056R MAX
MAX_CURRENT=160A
MAX_WATTAGE=55W
V_BE_GS=16V
GND
GND
D14
1
RSX201L-30
SMA
30V
2A
2
COMMON
Near FET
C196
.47UF
16V
10%
0603
COMMON
C526
820PF
50V
5%
C0G
0603
COMMON
PS2_RC
16MIL
R562
2.21
1%
1206
COMMON
GND
CONTINUOUS_CURRENT=20A
DC_RESISTANCE=3.0mOhm MAX
21
1uHL11
COMMONSMD_MULTI_590X530
FBVDD = 1.8-2.0V @ 14-18A
C548
10UF
6.3V
X5R
0805
COMMON
C547
47UF
6.3V
20%
X5R
1206
COMMON
C558
10UF
6.3V
20%
X5R
0805
COMMON
C557
10UF
6.3V
20% 20% 20%
X5R
0805
COMMON
C546
47UF
6.3V
X5R
1206
COMMON
C559
47UF
6.3V
20%
X5R
1206
COMMON
2.0V
18A
16MIL
C167
220UF
COMMON
+/-20%
6.3V
POSCAP
2.4A
0.025R
SMD_7343
C168
220UF
COMMON
+/-20%
6.3V
POSCAP
2.4A
0.025R
SMD_7343
FBVDD
GND
C166
220UF
COMMON
+/-20%
6.3V
POSCAP
2.4A
0.025R
SMD_7343
C200
10UF
16V
20%
X5R
1206
NO STUFF
C198
10UF
16V
20%
X5R
1206
NO STUFF
GND
GND
U502
ISL6549CB_600KHZ
VR_SW=0.8V, VR_LD=0.8V
SO14
SO14
COMMON
5
6
2
12
14
1
13
11
4
37
PS2_PVCC510
PS2_UGATE
PS2_BOOT
PS2_PHASE
PS2_LGATE
PS2_FB
12MILPS2_VCC598
12MIL
16MIL
16MIL
16MIL
16MIL
12MIL
12MILPS2_CP
5V
1
2
5V
C522
0603
20A
AC coupling
option...
Place close to VCC5 pin
C516
0603
R523
10
5%
0805
COMMON
.1UF
25V
10%
X7R
COMMON
1
D501
R521
0603
12V_F
8V5 can be sourced from 12V or 12V PEX6
depending upon actual power numbers/limitations
R568
0
5%
0603
COMMON
C158
10UF
16V
20%
X5R
1206
COMMON
8.5V
0.4A
20MIL
12V_F
R570
0
5%
0603
NO STUFF
PS2_12V_VIN
GND
C157
10UF
16V
20%
X5R
1206
COMMON
C175
10UF
16V
20%
X5R
1206
COMMON
12V
0.4A
20MIL
C172
.1UF
25V
10%
X7R
0603
COMMON
GND
COMBI_MONO_1G2D1S
C159
.1UF
16V
10%
X7R
0402
COMMON
Rrun divider to enable 8V5 startup
when regulator is not running.
12V_F
1G2D1S
4
2
Q14
AOD408L
COMMON
3
R130
6.34K
Rt
1%
0402
COMMON
R126
665
Rb
1%
0402
COMMON
GND
8V5 = 0.8V * (1 + Rt/Rb)
8.5V = 0.8V * (1 + 6.34K/655)
R129
4.75K
1%
Rrun
0402
1
PS2_8V5_DR_R
10MIL
CONTINUOUS_CURRENT=18A@25C,18A@70C
MAX_WATTAGE=60@25C,33W@100C
MAX_VOLTAGE=30V
R_DS_ON=0.018R
MAX_CURRENT=40A
V_BE_GS=+/-20V
R128
10K
1%
0402
COMMONCOMMON
R125
2.7K
5%
0402
COMMON
PS2_8V5_FB_RC
C152
1000PF
50V
10%
X7R
0402
COMMON
12V_PEX6_F
8V5
GND
C521
1UF
25V
10%
X7R
0805
COMMON
GND
PS2_8V5_DR
10MIL
PS2_8V5_FB
10MIL
PS2_FS_DIS
10MIL
R541
68K
5%
0402
COMMON
GND
FREQ_SET = 47.5K for 600kHz
68.0K for 440kHz
23>
PS3_PGOOD
1
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
1G1D1S
12V_F
NVVDD->FBVDDQ Sequencing
R533
10K
5%
0402
COMMON
3
Q504
BSS138
SOT23_1G1D1S
COMMON
2
GND
PS3_PGOOD* 1
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
1G1D1S
3
Q508
BSS138
SOT23_1G1D1S
COMMON
2
GND
Compensation for FBVDD
C534
C2
C1
.047UF
16V0402
10%
X7R
COMMON
1000PFC533
16V0402
10%
X7R
COMMON
PS2_CP_RC
12MIL
R559
0402
R2
1.1K
COMMON
1%
FBVDD = VREF * (1 + Rtop/Rbot)
FBVDD = 0.8V * (1 + 1.27K/1K) = 1.8V
FBVDD = 0.8V * (1 + 1.37K/1K) = 1.9V
FBVDD = 0.8V * (1 + 1.50K/1K) = 2.0V
C535
0402
C3
16V
10%
X7R
COMMON
www.vinafix.vn
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Power Supply: FBVDD/Q, 8V5
PS2_FB_RC.022UF
12MIL
R552
0402
470
R550
COMMON
0402
R3
22
COMMON
5%
R551
1.5K
1%
0402
COMMON
R560
1K
1%
0402
COMMON
Rtop
Rbot
5%
PS2_VSEN
10MIL
R103
0402
0
COMMON
5%
GND
FBVDD
Remote sense
GND
600-10393-0004-100 A
p393_a01
whill
22 OF 27
28-SEP-2007
Page 23
Page23: Power Supply: NVVDD Regulator
S
D
G
OUTININ
OUTINININININOUT
IN
PX3544
V12_AUX2
V12_AUX1
V12_SEN
ISEN1+
PWM1
ISEN1-
PWM2
ISEN2-
PWM3
ISEN3ÂISEN3+
PWM4
ISEN2+
ISEN4-
NC
NC
(GND)NC
ATRL
ISEN4+
(GND)NC
NC
VSENP
VSENN
TEMPSEN
NC
NC
VDD
VDD
VDD
VID0
OUTEN
VIDEN
VID1
VR_READY
FAULT1
FAULT2
SDA
SADDR1
SCL
SADDR0
I2C_WEN
RESET
NC
NC
GND
VD25
VMAX
GND
VSTART
INININ
OUT
OUT
OUTBIIN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
27<> 17<>
27> 17<
21< 11<
26> 16<
17< 16> 16<
16<
16>
15<> 16<
16< 16>
16< 16>
10< 26< 27> 26>
22<
15< 16<>
GPIO6_VSEL1
GPIO5_VSEL0
PS3_OUTEN
PS3_PGOOD
GPIO12_POWER_ALERT*
GPIO8_THERM_OVERT*
I2CC_SDA_R
I2CC_SCL_R
SADDR[1:0] = LL, 0xE0/0xE1
3V3_F
R505
10K
5%
0402
COMMON
R506
5%
0402
COMMON
GND
R512
4.42K
1%
0603
COMMON
C515
1UF
6.3V
10%
X5R
0402 04020402
COMMON
GND
R508
10K10K
5%
0402
COMMON
R513
5.23K
1%
0603
COMMON
3V3_F
C502
.1UF
16V
10%
X5R
R507
10K
5%
0402
COMMON
3V3_F
R503
0
5%
0603
COMMON
12MIL
GND
U501
PX3544_NV2412_A
0.5%
DYNAMIC VID(0.5V..1.6V)
MLFP_48
COMMON
12
24
36
3
4
5
11
15
13
14
46
47
43
45
6
44
42
41
48
16
49
PS3_V12_SEN
17
PS3_V12_AUX1
1
SNN_V12_AUX2
2
12MIL
40
12MIL
38
12MIL
39
12MIL
37
12MIL
34
12MIL
35
12MIL
33
12MIL
31
12MIL
32
SNN_PWM4
30
28
SNN_ISEN4
29
SNN_PWM5
23
21
SNN_ISEN5
22
10MIL
PS3_ATRL_PWM6
27
25
SNN_ISEN626
PS3_VSENP
19
8MIL
PS3_VSENN
18
8MIL
SNN_PS3_TEMP_SEN
20
7
PS3_VDD
3.3V12MIL
C503
1UF
6.3V
10%
X5R
COMMONCOMMON
PS3_VIDEN
R504
10K
5%
0402
COMMON
C513
1UF
6.3V
10%
X5R
0402
COMMON
GND
PS3_I2C_WEN
3V3_F
R509
10K
5%
0402
COMMON
PS3_RST*
PS3_VSTART
PS3_VMAX
PS3_VD25
C507
C505
.1UF
1UF
16V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
soft-start gated by V12_SEN
C508
.1UF
25V
10%
X7R
0603
COMMON
PS3_PWM1
PS3_ISEN1*
PS3_ISEN1
PS3_PWM2
PS3_ISEN2*
PS3_ISEN2
PS3_PWM3
PS3_ISEN3*
PS3_ISEN3
GND
GND
GND
C510
220PF
50V
5%
C0G
0402
COMMON
12V_PEX6_F
1
R511
43.2K
1%
0402
COMMON
2
R510
6.04K
1%
0402
COMMON
NVVDD
R519
470
5%
0402
COMMON
R514
470
5%
0402
COMMON
GND
25<
25>
25>
24<
24>
24>
24<
24>
24>
12V_F
R518
0402
R516
0402
1
R1012
43.2K
1%
0402
NO STUFF
2
enable at 8V..10.3V max.enable at 9.4V..10.2V max.
12V_PEX6_F
12V_F
R501
11.3K
1%
0402
COMMON
1
R1013
11.3K
1%
0402
NO STUFF
2
1
2
R502
C501
6.04K
.1UF
1%
25V
0402
10%
COMMON
X7R
0603
COMMON
GND
NVVDD
1G1D1S
GND
10MIL
PS3_ATRL_C
R527
5.1K
5%
0402
COMMON
10MIL
PS3_ATRL_R
47
R526
COMMON
0402
5%
10
COMMON
5%
10
COMMON
5%
PS3_NVVDD_VSENP_R
PS3_NVVDD_VSENN_R
Remote power and ground
Sense placed at GPU
C517
0402
18>
18>
18<
18<
.1UF
16V
10%
X5R
COMMON
3
Q503
IRLML2502
SOT23_1G1D1S
1
COMMON
2
MAX_VOLTAGE=20V
CONTINUOUS_CURRENT=3.4A
R_DS_ON=0.08R
MAX_CURRENT=20A
MAX_WATTAGE=0.8W@70C
V_BE_GS=+/-12V
Wire to control the resistance 20mR..40mR:
OUTHER COPPER LAYER: 1.7mil thick, 6mil wide, 400mil long
INTERNAL COPPER LAYER: 1.2mil thick, 8mil wide, 350mil long
Impulse current up to 20A !!
GND
GNDGND
VSTART and VMAX
Vout = 250uA * Rset
0.9V = 250uA * 3600
3.57k,1% = 0.88V .. 0.9V
1.1V = 250uA * 3600
4.42k,1% = 1.09V .. 1.12V
1.2V = 250uA * 4800
4.87k,1% = 1.2V .. 1.23V
1.3V = 250uA * 3600
5.23k,1% = 1.29V .. 1.32V
SNN_3540_4 10
SNN_3540_3 9
SNN_3540_1
SNN_3540_2 8
www.vinafix.vn
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Power Supply: NVVDD Regulator
600-10393-0004-100 A
p393_a01
whill
23 OF 27
28-SEP-2007
Page 24
Page24: Power Supply: NVVDD Phase 2, 3
OUT
OUT
S
D
G
S
D
G
S
D
G
OUT
OUT
S
D
G
S
D
G
PVCC
BOOT
PHASE
UGATE
LGATE
THERMAL_GND
VCC
GND
NC
PWM
NC
IN
S
D
G
PVCC
BOOT
PHASE
UGATE
LGATE
THERMAL_GND
VCC
GND
NC
PWM
NC
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
U8
PX35311ADDG
C188
1UF
16V
10%
X5R
0603
COMMON
MOSFET DRIVER
DFN10
DFN10
COMMON
7
5
12V_F
PHASE 2
11
GND
23>
PS3_PWM2
SNN_6594_02
4
3SNN_6594_01
8
8V5
9
16MIL
PS4_UG1
1
PS4_PHASE1
10
12V2
PS4_BOOT1
16MIL
R542
0402
6
16MIL
AC coupling
option...
GND
R545
0603PS4_LG1
R561
0402
R556
0603
C187
1UF
16V
10%
X5R
0603
COMMON
5%
5%
16MIL
5%
16MIL
PS4_LG_D
0
NO STUFF
5%
16MIL
PS4_UG1_R
0
COMMON
1
COMMON
PS4_BOOT1_RC
16MIL
3
0
COMMON
12V
12V C530
1
D502
BAV99
SOT23
100V
100MA
NO STUFF
2
PS4_LG1_AC
GND
LFPAK
30A
0603
16MIL
R553
470
5%
0402
NO STUFF
12V_PEX6_F
Place near FET
C551
22UF
6.3V
20%
X5R
COMMON
C194C206
180UF
COMMON
+/-20%
16V
OSCON
3.64A@105C
0.020R
COMBI_7343_D80
GND
GND
C539
22UF
6.3V
20%
X5R
COMMON
C543
22UF
6.3V
20%
X5R
0805 1210
COMMON
GND
For Bring UP
without GPU
1V
NVVDD
75A
16MIL
C169
100UF
6.3V
20%
X5R
COMMON
GND
C163
330UF
COMMON
20%
2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM
SMD_7343
GND
Q15
RJK0303DPB
LFPAK
COMMON
23<
23<
Near FETNear FETMAX_VOLTAGE=30V
C178
.47UF
16V
10%
X5R
0603
COMMON
GND
L8
1
2
GND
R530
1.4K
1%
0603
COMMON
CDR73
D13
IR10MQ040N
SMA
40V
COMMON
120A@5US
C536
470PF
50V
5%
PS3_ISEN2*
PS3_ISEN2
C0G
0603
COMMON
PS4_RC1
16MIL
R567
2.2
5%
1206
COMMON
GND
5
1
2
3
GND
0.125uH
COMMON
C518
0.22UF
25V
10%
X7R
0603
COMMON
C523
10UF
16V
20%
X5R
1206
COMMON
GND
GND
GND
R529
63.4
1%
0603
COMMON
C527
10UF
16V
20%
X5R
1206
COMMON
GND
C560
10UF
6.3V
20%
X5R
0805 0805
COMMON
GND
C184
10UF
16V
20%
X5R
1206
NO STUFF
C554
10UF
6.3V
20%
X5R
COMMON
180UF
COMMON
+/-20%
16V
OSCON
3.64A@105C
0.020R
COMBI_7343_D80
GND
C565
10UF
6.3V
20%
X5R
0805 0805 0805
COMMON
GND
GND
CONTINUOUS_CURRENT=30A
R_DS_ON=0.013R MAX
MAX_CURRENT=120A
MAX_WATTAGE=45W
V_BE_GS=16V
5
Q18
RJK0305DPB
LFPAK
4
COMMON
1
2
3
0.22UF
25V
10%
X7R
COMMON
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=40A
R_DS_ON=0.0056R MAX
MAX_CURRENT=160A
MAX_WATTAGE=55W
V_BE_GS=16V
LFPAK
5
Q21
RJK0303DPB
LFPAK
4
COMMON
1
2
3
GND
C181
.47UF
16V
10%
X5R
0603
COMMON
GND
LFPAK
4
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=40A
R_DS_ON=0.0056R MAX
MAX_CURRENT=160A
MAX_WATTAGE=55W
V_BE_GS=16V
NVVDD
NVVDD
GND
R127
100
5%
0603
NO STUFF
Place near the switcher
10UF 10UF
6.3V
20%
X5R
0805
COMMON
GND
6.3V
20%
X5R
0805
COMMON
GND
GND
C156C154C153C155
22UF 22UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
NO STUFF
NO STUFF
GND
8V5
12V_PEX6_F
C150
330UF
NO STUFF
20%
2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM
SMD_7343
GND
Place near FET
C189
1UF
U9
PX35311ADDG
C190
1UF
16V
10%
X5R
0603
NO STUFF
MOSFET DRIVER
DFN10
DFN10
NO STUFF
7
5
9
16MIL
PS5_UG2
1
10
2
PS5_BOOT2
16MIL
12V_F
PHASE 3
11
GND
23>
PS3_PWM3
SNN_6594_03
SNN_6594_04
4
3
8
6
PS5_LG2
16MIL
16V
10%
X5R
0603
NO STUFF
GND
R563
0402
PS5_PHASE2
12V
R557
0603
PS5_LG_D
R543
0402
5%
R546
0603
5%
AC coupling
option...
5%
16MIL
5%
PS5_BOOT2_RC
16MIL
0
NO STUFF
0
NO STUFF
16MIL
0
NO STUFF
12V 30A
1
NO STUFF
3
16MIL
12V
1
D503
BAV99
SOT23
100V
100MA
NO STUFF
2
PS5_LG2_AC
GND
LFPAK
4PS5_UG2_R
C531
0603
16MIL
R554
470
5%
0402
NO STUFF
0.22UF
25V
10%
X7R
NO STUFF
LFPAK
4
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=30A
R_DS_ON=0.013R MAX
MAX_CURRENT=120A
MAX_WATTAGE=45W
V_BE_GS=16V
5
Q19
RJK0305DPB
LFPAK
NO STUFF
1
2
3
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=40A
R_DS_ON=0.0056R MAX
MAX_CURRENT=160A
MAX_WATTAGE=55W
V_BE_GS=16V
5
Q22
RJK0303DPB
LFPAK
NO STUFF
1
2
3
GND
GND
LFPAK
4
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=40A
R_DS_ON=0.0056R MAX
MAX_CURRENT=160A
MAX_WATTAGE=55W
V_BE_GS=16V
Near FET
C182
.47UF
16V
10%
X5R
0603
NO STUFF
Q16
RJK0303DPB
LFPAK
NO STUFF
23<
23<
GND
5
1
2
3
GND
Near FET
C179
.47UF
16V
10%
X5R
0603
NO STUFF
PS3_ISEN3*
PS3_ISEN3
C537
470PF
50V
5%
C0G
0603
NO STUFF
PS5_RC2
16MIL
R565
2.2
5%
1206
NO STUFF
GND
1
GND
R532
1.4K
1%
0603
COMMON
L9
CDR73
D11
IR10MQ040N
SMA
40V
NO STUFF
120A@5US2
10UF 10UF 10UF
16V
20%
X5R
1206
NO STUFF
GND
GND
0.125uH
NO STUFF
GND
R531
C519
63.4
0.22UF
1%
25V
0603
10%
NO STUFF
X7R
0603
NO STUFF
16V
20%
X5R
1206
NO STUFF
C555
10UF
6.3V
X5R
0805
NO STUFF
C528C524C185
16V
20%
X5R
1206
NO STUFF
GND
C561
10UF
6.3V
X5R
0805
NO STUFF
GND
GND
C195
180UF
NO STUFF
+/-20%
16V
OSCON
3.64A@105C
0.020R
COMBI_7343_D80
GND
C566
10UF
6.3V
X5R
0805
NO STUFF
GND
C540
22UF
6.3V
20% 20%20% 20% 20%
X5R
0805
NO STUFF
C207
180UF
NO STUFF
+/-20%
16V
OSCON
3.64A@105C
0.020R
COMBI_7343_D80
GND
GND
C544
22UF
6.3V
X5R
0805
NO STUFF
GND
C552
22UF
6.3V
20%
X5R
0805
NO STUFF
GND
C170
100UF
6.3V
20%
X5R
1210
NO STUFF
NVVDD
C164
330UF
NO STUFF
20%
2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM
SMD_7343
GND
Place near the switcher
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Power Supply: NVVDD Phase 1 & 2
www.vinafix.vn
600-10393-0004-100 A
p393_a01
whill
24 OF 27
28-SEP-2007
Page 25
Page25: Power Supply: NVVDD Phase 1
OUT
S
D
G
S
D
G
S
D
G
OUT
OUT
PVCC
BOOT
PHASE
UGATE
LGATE
THERMAL_GND
VCC
GND
NC
PWM
NC
IN
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
Boost from 12V pex to create 17V
12V_F
INPUT_BOOST
10MIL
C177
1
.1UF
25V
10%
2
X7R
0603
NO STUFF
3
1
1
3
2
D506
MMBZ5232BLT1-5.6V
SOT23
5.6VR
350MW@25C
NO STUFF
INPUT_17V_D
10MIL
D505
BAV99
SOT23
100V
100MA
NO STUFF
INPUT17V_R
10MIL
R569
22
5%
0603
NO STUFF
C542
4.7UF
25V
10%
X5R
1206
NO STUFF
INPUT_17V
10MIL
17V
26<
GND
12V_F
8V5
CONTINUOUS_CURRENT=30A
C191
1UF
U10
C192
1UF
16V
10%
X5R
0603
COMMON
PX35311ADDG
MOSFET DRIVER
DFN10
DFN10
COMMON
7
5
9
16MIL
PS6_UG3
1
2
PS6_BOOT3
16MIL
12V_F
PHASE 1
11
23>
PS3_PWM1
GND
SNN_6594_05
SNN_6594_06
4
3
8
6
PS6_LG3
16MIL
16V
10%
X5R
0603
COMMON
GND
R564
0402
PS6_PHASE310
12V
R558
0603
R544
0402
5%
R547
0603
AC coupling
option...
LFPAK
16MIL
PS6_UG3_R 4
0
COMMON
5%
16MIL 30A12V 3
5%
PS6_BOOT3_RC
16MIL
16MIL
PS6_LG_D
0
NO STUFF
0
COMMON
5%
3
1
COMMON
12V
1
D504
BAV99
SOT23
100V
100MA
NO STUFF
2
PS6_LG3_AC
C532
0603
16MIL
R555
470
5%
0402
NO STUFF
0.22UF
25V
10%
X7R
COMMON
LFPAK
MAX_VOLTAGE=30V
R_DS_ON=0.013R MAX
MAX_CURRENT=120A
MAX_WATTAGE=45W
V_BE_GS=16V
5
Q20
RJK0305DPB
LFPAK
COMMON
1
2
4
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=40A
R_DS_ON=0.0056R MAX
MAX_CURRENT=160A
MAX_WATTAGE=55W
V_BE_GS=16V
5
Q17
RJK0303DPB
LFPAK
COMMON
1
2
3
LFPAK
4
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=40A
R_DS_ON=0.0056R MAX
MAX_CURRENT=160A
MAX_WATTAGE=55W
V_BE_GS=16V
GND
GND
Place near FET
5
Q23
RJK0303DPB
LFPAK
COMMON
1
2
3
GND
23<
23<
GND
PS3_ISEN1*
PS3_ISEN1
Near FET
C180
.47UF
16V
10%
X5R
0603
COMMON
GND
GND
C538
470PF
50V
5%
C0G
0603
COMMON
PS6_RC3
16MIL
R566
2.2
5%
1206
COMMON
Near FET
C183
.47UF
16V
10%
X5R
0603
COMMON
1
2
GND
1.4K
1%
0603
COMMON
L10
D12
IR10MQ040N
SMA
40V
COMMON
120A@5US
0.125uH
COMMONCDR73
C511 R517R522
0.22UF
25V
10%
X7R
0603
COMMON
63.4
1%
0603
COMMON
GND
C556
6.3V
X5R
0805
COMMON
GND
C562
10UF10UF
6.3V
20%20%
X5R
0805
COMMON
GND
C186
10UF
16V
20%
X5R
1206
NO STUFF
C567
10UF
6.3V
20%
X5R
0805
COMMON
GNDGND
C525
10UF
16V
20%
X5R
1206
COMMON
GND
C529
10UF
16V
20%
X5R
1206
COMMON
GND
22UF
6.3V
20% 20%
X5R
0805
COMMON
GND
C545C553
22UF
6.3V
X5R
0805
COMMON
C193
180UF
COMMON
+/-20%
16V
OSCON
3.64A@105C
0.020R
COMBI_7343_D80
GND
GND
C541
22UF
6.3V
20%
X5R
0805
COMMON
GND
GND
C205
180UF
COMMON
+/-20%
16V
OSCON
3.64A@105C
0.020R
COMBI_7343_D80
C171
100UF
6.3V
20%
X5R
1210
COMMON
NVVDD
C165
330UF
COMMON
20%
2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM
SMD_7343
GND
Place near the switcher
www.vinafix.vn
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Power Supply: NVVDD Phase 3
600-10393-0004-100 A
p393_a01
whill
25 OF 27
28-SEP-2007
Page 26
Page26: Power Supply: Filter/Detection of 3V3,12V,12V_PEX
OUT
S
D
G
S
D
G
C
E
B
OUT
JMPR
S
D
G
S
D
G
S
D
G
IN
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
IN
S
D
G
IN
PRSNT*
GND
12V
12V
12V
GND
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
12V_F
POWER FILTER 3.3V
3.3V
3V3
3A
NV_SOURCE_POWER_NET=TRUE
16MIL
V_BE_GS=12V
MAX_CURRENT=18A
MAX_WATTAGE=1.25W
R_DS_ON=0.043@4.5V
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=4.5A
4
125
6
TSOP6_1G4D1S
RTQ045N03
Q1213
1G4D1S
12V_PEX6_F
R1010
10K
1%
0402
NO STUFF
GND
COMMON
3
C1101
100PF
50V
5%
C0G
0402
COMMON
12V_NV_OUTEN_G
12V
R1224
10K
5%
0402
COMMON
21<
27>
11<
10<
23< 26>
PS3_OUTEN
UC_3V3
R1226
10K
5%
0402
NO STUFF
1
3V3_Q_EN*
3
Q1215
BSS138
SOT23_1G1D1S
NO STUFF
2
1G1D1S
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
UC_3V3
R1225
10K
5%
0402
NO STUFF
1
3V3_Q_EN
3
Q1216
BSS138
SOT23_1G1D1S
NO STUFF
2
1G1D1S
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
GND
12V_F
12V_F
THERM_SHUTDOWN*
R1008
10K
1%
0402
COMMON
R1009
2.2K
5%
0402
COMMON
17>
POWER FILTER 12V
12V
12V
5.5A
NV_SOURCE_POWER_NET=TRUE
16MIL
0V
28A
NV_SOURCE_POWER_NET=TRUE
16MIL
GND
C509
10UF
16V 16V
20%
X5R
1206
COMMON
L13
7_6X7_6
COMMON
1 UH
C504
.1UF
10%
X5R
0402
COMMON
GND
12V
5.5A
16MIL
GND
INPUT FROM EXTERNAL
75W PEX EXTENSION POWER
1G1D1S
3V3_Q
C62
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C60
.1UF
16V
10%
X7R
0402
COMMON
3.3V
3A
16MIL
C61
.1UF
16V
10%
X5R
0402
COMMON
1 UHL5
COMMON7_6X7_6
GND
C970
22UF
6.3V
20%
X5R
0805
COMMON
C58
220UF
COMMON
+/-20%
6.3V
POSCAP
2.4A
0.025R
SMD_7343
GND
3V3_F
R548
10K
5%
0402
NO STUFF
THERM_SHUTDOWN
3
Q505
BSS138
SOT23_1G1D1S
1
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
R535
0402
1G1D1S
1
5%
0
COMMON
3
Q510
BSS138
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
3V3_F
R1011
1K
5%
0402
12V_NV_OUTEN_G*
3
Q1002
1G1D1S
BSS138
SOT23_1G1D1S
1
COMMON
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
COMMON
3
1G1D1S
BSS138
SOT23_1G1D1S
1
COMMON
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
GND
3.3V
3A
16MIL
Q1001
3V3_F
D1000
BAV99
SOT23
100V
100MA
COMMON
12V_EXT_6PIN_ON_R*
R549
1K
5%
0402
NO STUFF
GND
R539
0
5%
0402
COMMON
GND
R538
300
5%
2512
COMMON
1
2
1
3
1G1D1S
1
2
3
Q511
BSS138
SOT23_1G1D1S
COMMON
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
3
Q509
1G1D1S
BSS138
SOT23_1G1D1S
1
COMMON
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
R common ONLY IF the
low-power,SW warning
is implemented
R DNI ONLY IF the
low-power,SW warning
is implemented
12V_F
R528
10K
5%
0402
COMMON
HDR_2M3
MALE
4.2MM
PCIEPWR
COMMON
J9
90
12V_PEX6
6
3
5
2
4
1
12V_PEX6
12V
6.25A
NV_SOURCE_POWER_NET=TRUE
12V_EXT_6PIN_ON*
C520
.001UF
50V
10%
X7R
0402
COMMON
GNDGND
16MIL
10MIL
12V_EXT_6PIN_ON*
4.7K .01UF
5%
0603
COMMON
C204R131
16V
10%
X7R
0402
COMMON
25V
10%
X7R
0603
COMMON
C203C201
10UF.1UF
16V
20%
X5R
1206
COMMON
L12
7_6X7_6
COMMON
1 UH
12V_PEX6_F
12V
6.25A
16MIL
C176
10UF
16V
20%
X5R
1206
COMMON
GND
1
1
BUZZ IF 12V_PEX6 = FAIL
when 12V_F is powered
R540
300
5%
2512
COMMON
10MIL
INPUT_BUZZ
BZ1
80dB
30mA
RB9650NL
TH_D09_6_P5_0
COMMON
10MIL
INPUT_BUZZ*
12V_EXT_6PIN_ON
3
Q507
1G1D1S
BSS138
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
GPIO12_POWER_ALERT*
3
Q506
1G1D1S
BSS138
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
25>
1
2
3V3_F
R536
10K
5%
0402
COMMON
Install Jumper to
disable buzzer
J8
HDR_1M2
MALE
2.54MM
0
NORM
COMMON
START POWER SUPPLY if
2X3 HEADER IS CONNECTED
PS3_OUTEN
INPUT_17V
C514
1UF
25V
10%
X7R
0805
NO STUFF
GND
10K
R534
NO STUFF
0603
5%
3V3_F
R524
10K
5%
0402
COMMON
POWER ALERT if running
in LOW POWER mode
R525
47K
5%
0402
NO STUFF
INPUT_17V_R
1B1C1E
23> 16<
27> 26< 23< 21< 11< 10<
Power from Edge connector
pass through power to all
12V rails. (low-power only).
12V_F
C506
4.7UF
16V
20%
X7R
1206
COMMON
GND
2
2
Q502
MMBT4403
1
SOT23_1B1C1E
NO STUFF
3
INPUT_GATE
R520
27K
5%
0402
NO STUFF
GND
1G2D1S
1G2D1S
4
V_BE_GS=+/-20V
MAX_WATTAGE=2W@25C, 1.44W@70C
MAX_CURRENT=30A
R_DS_ON=0.028R
CONTINUOUS_CURRENT=6.9A@25C, 5.8A@70C
MAX_VOLTAGE=30V
1
NO STUFF
SO8_DUAL_1G2D1S
A04812
Q501
7
8
12V
5.5A
24MIL
12V_PEX6_Q
6
5
Q501
A04812
SO8_DUAL_1G2D1S
NO STUFF
MAX_VOLTAGE=30V
3
CONTINUOUS_CURRENT=6.9A@25C, 5.8A@70C
R_DS_ON=0.028R
MAX_CURRENT=30A
MAX_WATTAGE=2W@25C, 1.44W@70C
V_BE_GS=+/-20V
12V_PEX6_F
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Power Supply: Filter/Detection of 3V3, 12V, 12V_PEX6
www.vinafix.vn
600-10393-0004-100 A
p393_a01 26 OF 27
whill
28-SEP-2007
Page 27
Page27: Power Supply: Hybrid Power
OUTBIOUT
BI
S
D
G
S
D
G
IN
S
D
G
VCC
GND
NC
NC
S
D
G
S
D
G
OUT
OUT
OUT
OUT
S
D
G
PIC16F690
I2CA_SCL
HOTPLUG_DETECT_C
I2CB_SDA
I2CB_SCL
I2CA_SDA
HOTPLUG_DETECT_D
POWER_ENABLE
HOTPLUG_DETECT_F
FAN_ENABLE
HOTPLUG_DETECT_E
GPU_RESET*
PEX_REF_CLK_ENABLE
VDD
IICC_SDA
SMB_SDA
SMB_SCL
IICC_SCL
PCI_E_RESET*
VPP
GND
S
D
G
OUT
OUTBIIN
OUT
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
I2CA_SCL_R
I2CA_SDA_R
23< 21< 11< 10<
UC_3V3
1
26<
1G1D1S
UC_3V3
26>
3
Q1200
BSS138
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
3
Q1203
BSS138
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
1G1D1S
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
UC_3V3
16<>
17<>
3V3_F
D1200
1
2
BAT54C
25V
200MA
SOT23
NO STUFF
3
C1200
1UF
6.3V
10%
X5R
0402
COMMON
15<> 16>
15<
2>
R1221
0
5%
0402
COMMON
3.0V
0.01A
10MIL
C1201
.1UF
16V
10%
X7R
0402
COMMON
GND
I2CC_SCL_R
I2CC_SDA_R
I2CS_SCL_R
I2CS_SDA_R
PEX_RST*
HYBRID_PRG_TP
UC_3V3
U1200
HYBRID_PIC16F690
XSOP20
NO STUFF
1
2
3
17
11
13
16
4
15
14
8
12
10
19
18
6
7
I2CA_SCL_UC
I2CA_SDA_UC
I2CB_SCL_UC
I2CB_SDA_UC9
HYBRID_DP_HPD
HPLG_DET_D
HPLG_DET_E
HPLG_DET_F
GPU_RST*
PS3_OUTEN
R1207
68K
5%
0402
NO STUFF
R1212
0402
R1200
0402
5%
R1222
0402
R1223
0402
R1202
0402
5%
UC_3V3
R1208
68K
5%
0402
NO STUFF
10K
NO STUFF
5%
5%
5%
10K
NO STUFF
68K
NO STUFF
68K
NO STUFF
68K
NO STUFF
R1209
68K
5%
0402
NO STUFF
GND
GND
UC_3V3
3V3_AUX
Per Datasheet:
Vf = 400mV at 10mA
Vf = 500mV at 30mA
* expected current < 2mA
UC_3V3
R1201
68K
5%
0402
23<>
R1214R1213
68K
5%
0402
NO STUFF
UC_3V3
NO STUFF
17<
R1220
68K
5%
0402
NO STUFF
16<
16<
23<
Weak pull-ups needed for I2CS:
* if SMBus is isolated from the GPU
2<
PEX_REFCLK_EN
UC_3V3
* if MB does not support SMBus
* if MB does not support 3V3AUX
16>
16<>
16<
16<
2<
2<
68K
5%
0402
NO STUFF
3
Q1201
BSS138
SOT23_1G1D1S
1
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
1G1D1S
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
R1210
68K
5%
0402
NO STUFF
Stuff 10K pull-down for DP skus
17< 2<
10<
10<
UC_3V3
11
UC_3V3
SOT23_1G1D1S
NO STUFF
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
Q1204
BSS138
GND
1G1D1S
R1203
68K
5%
0402
NO STUFF
3
2
3
Q1202
BSS138
SOT23_1G1D1S
NO STUFF
2
1G1D1S
I2CB_SCL_R
I2CB_SDA_R
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
Inverts DP HPD signal polarity
1
11<
11<
GPIO1_DVICD_DP_HPD
16< 15> 12>
GPIO4_FAN_PWM_R
5
20
GND
PEX_RST*
R1205
0402
GPU_RST*
0
COMMON
5%
Stuff only to bypass the micro-controller
UC_3V3
R1215
68K
5%
0402
NO STUFF
3
Q1211
BSS138
SOT23_1G1D1S
1
NO STUFF
2
1G1D1S
GND
PS3_OUTEN
I2CS_ENABLE*
3
Q1210
BSS138
SOT23_1G1D1S
1
NO STUFF
2
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
1G1D1S
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
GND
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Power Supply: Hybrid Power
www.vinafix.vn
12V
R1216
10K
5%
0402
NO STUFF
I2CS_ENABLE
MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V
17<
SNN_QS_NC1
SNN_QS_NC2
1
9
16<
isolates SMBus to the GPU when in Hybrid mode
U1201
XSOP16_SECT
IDTQS3VH126
COMMON
XSOP16_SECT
UC_3V3
16
8
C1202
.1UF
16V
10%
X7R
0402
COMMON
GND
Vcc section of I2C bus switch
See sheets 10-11 for switch sections
600-10393-0004-100 A
p393_a01
whill
27 OF 27
28-SEP-2007
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