MSI MS-V113 Schematic 2.0

A B C D E F G H

P409:MXM-III,G3-128,256/512MB,128-bit,8/16Mx32 DDR-3

1

LVDS,DVI_A, DVI_B,TV_OUT,VGA

1

Table of Contents

Page 1: Overview
Page 2: PCI EXPRESS Interface
Page 3: Frame Buffer A GPU
Page 4: Frame Buffer A Memories Rank0
Page 5: Frame Buffer A Memories Rank1
Page 6: Frame Buffer C GPU
Page 7: Frame Buffer C Memories Rank0
Page 8: Frame Buffer C Memories Rank1
Page 9: Frame Buffer Physical Constrains

2

3

4

Page 10: DACs, Clock-Generation
Page 11: LVDS / TMDS Interface GPU
Page 12: MXM Connector IO-Section
Page 13: GPIO Thermal Sensor Chip
Page 14: Spread Spectrum, BIOS/ HDCP ROM
Page 15: MIOA, MIOB
Page 16: NVVDD Supply
Page 17: FBVDDQ, PEX1V2, PLLVDD Supply
Page 18: Straps

HISTORY:

A03:

INITIAL VERSION

2

3

4

SKU

VARIANT ASSEMBLY

B

BASE

1

0501 NB8E-SE/G84-750 with HDCP Kit,512MB, 8pcs 16Mx32 GDDR3

2

0002

3

0003

4

0004 NB8E-SE/G84-750 with HDCP Kit, 512MB, 8pcs 16Mx32 GDDR3

5

<UNDEFINED>
6
7

<UNDEFINED>
8

<UNDEFINED>
9

<UNDEFINED>

10

<UNDEFINED>

5

11

<UNDEFINED>

12

<UNDEFINED>

13

<UNDEFINED>

14

<UNDEFINED> <UNDEFINED>

15

<UNDEFINED>

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

NVPN

600-10409-xxxx-300
600-50409-0501-300
600-10409-0002-300
600-10409-0003-300
600-10409-0004-300
<UNDEFINED>

<UNDEFINED> <UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL

NB8P-NVS2/G84-710 with HDCP Kit, 256MB,4pcs 16Mx32 GDDR3 (1Mb VBIOS ROM)
NB8E-SE/G84-750 with HDCP Kit, 512MB, 8pcs 16Mx32 GDDR3 (1Mb VBIOS ROM)

<UNDEFINED>
<UNDEFINED><UNDEFINED><UNDEFINED>

<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED><UNDEFINED>

ASSEMBLY
PAGE DETAIL

C GE

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Overview

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

5

PAGEID
DATE

16-MAR-2007

HFDBA

A B C D E F G H

MXM Connector

PEX_TX0_C
PEX_TX0_C*

PEX_TX1_C
PEX_TX1_C*

PEX_TX2_C
PEX_TX2_C*

PEX_TX3_C
PEX_TX3_C*

PEX_TX4_C
PEX_TX4_C*

PEX_TX5_C
PEX_TX5_C*

PEX_TX6_C
PEX_TX6_C*

PEX_TX7_C
PEX_TX7_C*

PEX_TX8_C
PEX_TX8_C*

PEX_TX9_C
PEX_TX9_C*

PEX_TX10_C
PEX_TX10_C*

PEX_TX11_C
PEX_TX11_C*

PEX_TX12_C
PEX_TX12_C*

PEX_TX13_C
PEX_TX13_C*

PEX_TX14_C
PEX_TX14_C*

PEX_TX15_C
PEX_TX15_C*

PEX Interface

PEX_TX0_C 100DIFF 1
PEX_TX0_C 100DIFF 1

100DIFF 1PEX_TX1_C

PEX_TX2_C 100DIFF 1
PEX_TX2_C 100DIFF 1

PEX_TX3_C 100DIFF 1
PEX_TX3_C 100DIFF 1

100DIFFPEX_TX4_C 1

PEX_TX4_C 1100DIFF

PEX_TX5_C 1100DIFF
PEX_TX5_C 1100DIFF

PEX_TX6_C 100DIFF 1
PEX_TX6_C 1100DIFF

PEX_TX7_C 1100DIFF

PEX_TX8_C 1100DIFF

PEX_TX9_C 100DIFF 1

100DIFFPEX_TX9_C 1

100DIFF 1PEX_TX10_C

PEX_TX10_C 100DIFF 1

PEX_TX11_C 100DIFF 1
PEX_TX11_C 100DIFF 1

PEX_TX12_C 100DIFF 1
PEX_TX12_C 1100DIFF

PEX_TX13_C 1100DIFF
PEX_TX13_C 100DIFF 1

100DIFF 1PEX_TX14_C
100DIFF 1PEX_TX14_C

PEX_RST

SNN_RFU1
SNN_RFU2

R572

200
COMMON

0402

5%

NV_CRITICALNV_IMPEDANCEDIFF_PAIRNET_NAME

C711 .1UF

C697 .1UF

1100DIFFPEX_TX1_C

C682

.1UF

0402

C677

.1UF

16V COMMON10%

C667 .1UF

C659

.1UF

10%

C648

.1UF

0402

C636

1100DIFFPEX_TX7_C

1100DIFFPEX_TX8_C

1100DIFFPEX_TX15_C
1100DIFFPEX_TX15_C

.1UF

0402 COMMONX7R

10%16V

C623

.1UF

10%

C617

.1UF

10%

C608

.1UF

16V COMMONX7R0402

10%

C605

.1UF

10% COMMONX7R16V0402

C601

.1UF

10%0402 COMMONX7R16V

C590

.1UF

10%

C587

.1UF

10%

C584

.1UF

10%

C703

X7R0402 16V COMMON10%

X7R16V0402 COMMON10%

X7R0402

.1UF
16V0402 10%

C686

.1UF

C680
0402

C669
0402 COMMONX7R16V

C662

C652

C639

C630

C619

C609

C606

C603

C597

C588

C585

C582

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF
16V COMMONX7R0402

.1UF

.1UF

.1UF

.1UF

.1UF

COMMONX7R16V 10%

COMMONX7R16V0402 10%

COMMONX7R16V0402

COMMONX7R16V 10%

COMMONX7R16V0402

COMMONX7R16V0402

COMMONX7R16V0402

COMMONX7R16V0402

COMMONX7R16V0402

C GE

CN1A

(NPHY,NONPHY)-HE(_SLI)
CON_FINGER_MXMHE_212

2V5RUN_R

C565
.1UF
16V
10%
X7R
0402
COMMON

C566
.1UF
50V
10%
X7R
0603
COMMON

C64
.1UF
16V
10%
X7R
0402
COMMON

238

2

1

E1

234

18

17
20
41
44
47
50
53
56
59
62
65
68
71
74
77
80
83
86
89
92
95

98
101
104
107
110
113
116
119
122
125
128
131
138
142
146
150
154
158
164
176
182
188
194
199
200
205
206
211
212
218
223
229
235
236
241

E2

COMMON

1/2 PCI-Express, Power

3V3RUN
(1.5A)

1V8RUN
(3.5A)

PWR_SRC
PWR_SRC

(14A)

2V5RUN
(0.5A)

5VRUN
(0.5A)

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

CLK_REQ

PEX_RST

PEX_REFCLK
PEX_REFCLK

PEX_RX0
PEX_RX0

PEX_TX0
PEX_TX0

PEX_RX1
PEX_RX1

PEX_TX1
PEX_TX1

PEX_RX2
PEX_RX2

PEX_TX2
PEX_TX2

PEX_RX3
PEX_RX3

PEX_TX3
PEX_TX3

PEX_RX4
PEX_RX4

PEX_TX4
PEX_TX4

PEX_RX5
PEX_RX5

PEX_TX5
PEX_TX5

PEX_RX6
PEX_RX6

PEX_TX6
PEX_TX6

PEX_RX7
PEX_RX7

PEX_TX7
PEX_TX7

PEX_RX8
PEX_RX8

PEX_TX8
PEX_TX8

PEX_RX9
PEX_RX9

PEX_TX9
PEX_TX9

PEX_RX10
PEX_RX10

PEX_TX10
PEX_TX10

PEX_RX11
PEX_RX11

PEX_TX11
PEX_TX11

PEX_RX12
PEX_RX12

PEX_TX12
PEX_TX12

PEX_RX13
PEX_RX13

PEX_TX13
PEX_TX13

PEX_RX14
PEX_RX14

PEX_TX14
PEX_TX14

PEX_RX15
PEX_RX15

PEX_TX15
PEX_TX15

PRSNT1
PRSNT2

137

139

135
133

129
127

132
130

123
121

126
124

117
115

120
118

111
109

114
112

105
103

108
106

99
97

102
100

93
91

96
94

87
85

90
88

81
79

84
82

75
73

78
76

69
67

72
70

63
61

66
64

57
55

60
58

51
49

54
52

45
43

48
46

39
37

42
40

134
38

1

C1

C794

.1UF

.1UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C562
.1UF
50V
10%

2

Stuffed? Ra Rb

3

Non_SLI:

X7R
0603
COMMON

Ra
R2
0

5%
0402
COMMON

R6

0

04025%COMMON

Rb

C5
.1UF
16V
10%
X7R
0402
COMMON

No Yes

SLI:

Yes No

4

R112

1K

1%

0402

COMMON

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

NV_IMPEDANCE

NV_CRITICAL DIFF_PAIR NET_NAME

100DIFF 1 PEX_TCLK

1 PEX_TCLK100DIFF

1 PEX_RCLK100DIFF

100DIFF 1 PEX_TX0
100DIFF 1 PEX_TX0

COMMONX7R

1 PEX_RX0100DIFF
1100DIFF PEX_RX0

1 PEX_TX1100DIFF
1 PEX_TX1100DIFF

COMMON16V0402 10% X7R

100DIFF 1 PEX_TX2

COMMONX7R16V 10%

1 PEX_RX2100DIFF

10%

10%

10%

10%0402 X7R

10%

10%16V

10%

10%

10%

10%

10%

10%

10%

1100DIFF PEX_TX3

100DIFF PEX_RX31

100DIFF 1 PEX_TX4

COMMONX7R16V0402
100DIFF PEX_RX41
100DIFF PEX_RX41

100DIFF PEX_TX51

1100DIFF PEX_TX5

COMMONX7R16V0402

1100DIFF PEX_RX5

1100DIFF PEX_TX6

COMMON16V

1 PEX_RX6100DIFF
1100DIFF PEX_RX6

1100DIFF PEX_TX7
1100DIFF PEX_TX7

COMMON16V0402 X7R
100DIFF 1 PEX_RX7
100DIFF PEX_RX71

1 PEX_TX8100DIFF
1100DIFF PEX_TX8

COMMONX7R0402
100DIFF PEX_RX81

1 PEX_RX8100DIFF

1 PEX_TX9100DIFF
1 PEX_TX9100DIFF

COMMONX7R16V0402
100DIFF 1 PEX_RX9

1 PEX_RX9100DIFF

1100DIFF PEX_TX10

100DIFF PEX_TX101

100DIFF 1 PEX_TX11

1100DIFF PEX_TX11

COMMONX7R16V0402
100DIFF PEX_RX111

1100DIFF PEX_TX12
1 PEX_TX12100DIFF

COMMONX7R16V0402

1100DIFF PEX_RX12

1100DIFF PEX_TX13
1100DIFF PEX_TX13

COMMONX7R16V0402

1100DIFF PEX_TX14
1100DIFF PEX_TX14

COMMONX7R16V0402

100DIFF 1 PEX_TX15

1100DIFF PEX_TX15

COMMONX7R16V0402

ASSEMBLY
PAGE DETAIL

PEX_RCLK100DIFF 1

PEX_RX1100DIFF 1
PEX_RX1100DIFF 1

PEX_TX2100DIFF 1

PEX_RX2100DIFF 1

PEX_TX31100DIFF

PEX_RX3100DIFF 1

PEX_TX41100DIFF

PEX_RX51100DIFF

PEX_TX61100DIFF

PEX_RX10100DIFF 1
PEX_RX10100DIFF 1

PEX_RX111100DIFF

PEX_RX121100DIFF

PEX_RX13100DIFF 1
PEX_RX13100DIFF 1

PEX_RX14100DIFF 1
PEX_RX141100DIFF

PEX_RX15100DIFF 1
PEX_RX151100DIFF

PCI EXPRESS Interface

PEX_TSTCLK
PEX_TSTCLK*

REFCLK
REFCLK*

PEX_TX0
PEX_TX0*

PEX_RX0
PEX_RX0*

PEX_TX1
PEX_TX1*

PEX_RX1
PEX_RX1*

PEX_TX2
PEX_TX2*

PEX_RX2
PEX_RX2*

PEX_TX3
PEX_TX3*

PEX_RX3
PEX_RX3*

PEX_TX4
PEX_TX4*

PEX_RX4
PEX_RX4*

PEX_TX5
PEX_TX5*

PEX_RX5
PEX_RX5*

PEX_TX6
PEX_TX6*

PEX_RX6
PEX_RX6*

PEX_TX7
PEX_TX7*

PEX_RX7
PEX_RX7*

PEX_TX8
PEX_TX8*

PEX_RX8
PEX_RX8*

PEX_TX9
PEX_TX9*

PEX_RX9
PEX_RX9*

PEX_TX10
PEX_TX10*

PEX_RX10
PEX_RX10*

PEX_TX11
PEX_TX11*

PEX_RX11
PEX_RX11*

PEX_TX12
PEX_TX12*

PEX_RX12
PEX_RX12*

PEX_TX13
PEX_TX13*

PEX_RX13
PEX_RX13*

PEX_TX14
PEX_TX14*

PEX_RX14
PEX_RX14*

PEX_TX15
PEX_TX15*

PEX_RX15
PEX_RX15*

AH15

AG12
AH13

AM12
AM11

AH14
AJ14

AJ15
AK15

AK13
AK14

AH16
AG16

AM14
AM15

AG17
AH17

AL15
AL16

AG18
AH18

AK16
AK17

AK18
AJ18

AL17
AL18

AJ19
AH19

AM18
AM19

AG20
AH20

AK19
AK20

AG21
AH21

AL20
AL21

AK21
AJ21

AM21
AM22

AJ22
AH22

AK22
AK23

AG23
AH23

AL23
AL24

AK24
AJ24

AM24
AM25

AJ25
AH25

AK25
AK26

AH26
AG26

AL26
AL27

AK27
AJ27

AM27
AM28

AJ28
AH27

AL28
AL29

G1A

BGA_0820_P100_330X330_G3_128B
COMMON

1/14 PCI_EXPRESS

PEX_RST

RFU
RFU

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT

PEX_REFCLK
PEX_REFCLK

PEX_TX0
PEX_TX0

PEX_RX0
PEX_RX0

PEX_TX1
PEX_TX1

PEX_RX1
PEX_RX1

PEX_TX2
PEX_TX2

PEX_RX2
PEX_RX2

PEX_TX3
PEX_TX3

PEX_RX3
PEX_RX3

PEX_TX4
PEX_TX4

PEX_RX4
PEX_RX4

PEX_TX5
PEX_TX5

PEX_RX5
PEX_RX5

PEX_TX6
PEX_TX6

PEX_RX6
PEX_RX6

PEX_TX7
PEX_TX7

PEX_RX7
PEX_RX7

PEX_TX8
PEX_TX8

PEX_RX8
PEX_RX8

PEX_TX9
PEX_TX9

PEX_RX9
PEX_RX9

PEX_TX10
PEX_TX10

PEX_RX10
PEX_RX10

PEX_TX11
PEX_TX11

PEX_RX11
PEX_RX11

PEX_TX12
PEX_TX12

PEX_RX12
PEX_RX12

PEX_TX13
PEX_TX13

PEX_RX13
PEX_RX13

PEX_TX14
PEX_TX14

PEX_RX14
PEX_RX14

PEX_TX15
PEX_TX15

PEX_RX15
PEX_RX15

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

VDD_LP
VDD_LP
VDD_LP
VDD_LP
VDD_LP
VDD_LP

VDD_SENSE

GND_SENSE

PEX_PLLAVDD
PEX_PLLDVDD

PEX_PLLGND

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

SPDIF

AD23

C635
.022UF
16V
10%
X7R
0402
COMMON

C647
.022UF
16V
10%
X7R
0402
COMMON

PEX_PLLDVDD

12mil
C693
470PF
50V
10%
X7R
0402
COMMON

C738 .01UF

0402

25V
10%
X7R
COMMON

OUT
OUT

C678
470PF
50V
10%
X7R
0402
COMMON

C624
.022UF
16V
10%
X7R
0402
COMMON

C679
.022UF
16V
10%
X7R
0402
COMMON

C675
.1UF

6.3V
10%
X7R
0402
COMMON

C660
.1UF

6.3V
10%
X7R
0402
COMMON

C691
.1UF

6.3V
10%
X7R
0402
COMMON

C705
.1UF

6.3V
10%
X7R
0402
COMMON

C632
.1UF

6.3V
10%
X7R
0402
COMMON

C721
4700PF
25V
X7R
0402
COMMON

C715
4700PF
25V
X7R
0402
COMMON

16
16

10%

10%

AF23
AF24
AF25
AG24
AG25

AC16
AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18
AF21
AF22

K16

VDD

K17

VDD

N13

VDD

N14

VDD

N16

VDD

N17

VDD

N19

VDD

P13

VDD

P14

VDD

P16

VDD

P17

VDD

P19

VDD

R16

VDD

R17

VDD

T13

VDD

T14

VDD

T15

VDD

T18

VDD

T19

VDD

U13

VDD

U14

VDD

U15

VDD

U18

VDD

U19

VDD

V16

VDD

V17

VDD

W13

VDD

W14

VDD

W16

VDD

W17

VDD

W19

VDD

Y13

VDD

Y14

VDD

Y16

VDD

Y17

VDD

Y19

VDD

Y20

VDD

P20
T20
T23
U20
U23
W20

NVVDD_SENSE

N20

GND_SENSE

M21

AC11
AC12
AC24
AD24
AE11
AE12
H7
J7
K7
L10
L7
L8
M10

AF15
AE15
AE16

SPDIF

J6

C671
4700PF
25V
10%
X7R
0402
COMMON

C611
.1UF
16V
10%
X7R
0402
COMMON

C656
.022UF
16V
10%
X7R
0402
COMMON

C661
.1UF
16V
10%
X7R
0402
COMMON

C681
.1UF
16V
10%
X7R
0402
COMMON

C644
.1UF
16V
10%
X7R
0402
COMMON

C710
.1UF
16V
10%
X7R
0402
COMMON

C654
.1UF
16V
10%
X7R
0402
COMMON

C569
1UF

6.3V
10%
X7R
0603
COMMON

C634
.1UF
16V
10%
X7R
0402
COMMON

C685
.1UF
16V
10%
X7R
0402
COMMON

C676
.1UF
16V
10%
X7R
0402
COMMON

C643
.1UF
16V
10%
X7R
0402
COMMON

C709
.1UF
16V
10%
X7R
0402
COMMON

C665
.1UF
16V
10%
X7R
0402
COMMON

C649
1UF

6.3V
10%
X7R
0603
COMMON

C674
1UF

6.3V
10%
X7R
0603
COMMON

C672
1UF

6.3V
10%
X7R
0603
COMMON

C670
1UF

6.3V
10%
X7R
0603
COMMON

C712
1UF

6.3V
10%
X7R
0603
COMMON

C651
1UF

6.3V
10%
X7R
0603
COMMON

C664
.022UF
16V
10%
X7R
0402
COMMON

<<place on bottom
north of GPU

<<place on bottom
east of GPU

<<place on bottom
south of GPU

<<place on bottom
west of GPU

C694
.022UF
16V
10%
X7R
0402
COMMON

C640
.1UF
16V
10%
X7R
0402
COMMON

1

2

C615
.022UF
16V
10%
X7R
0402
COMMON

C653
.022UF
16V
10%
X7R
0402
COMMON

C688
.1UF

6.3V
10%
X7R
0402
COMMON

C690
.1UF

6.3V
10%
X7R
0402
COMMON

C666
.1UF

6.3V
10%
X7R
0402
COMMON

C696
.1UF

6.3V
10%
X7R
0402
COMMON

C642
.1UF

6.3V
10%
X7R
0402
COMMON

3

C739
.1UF
16V
10%
X7R
0402
COMMON

C706
4700PF
25V
X7R
0402
COMMON

C687

4.7UF

6.3V
10%
X5R
0603
COMMON

C789
1UF

10%

6.3V
X7R
0603
COMMON

C622
.1UF

10%

16V
10%
X7R
0402
COMMON

C668

4.7UF

6.3V
10%
X5R
0603
COMMON

LB502
IND_SMD_0603

180R@100MHz

COMMON

NV_CRITICALNV_IMPEDANCE

150OHM

12

IN

4

C720
.1UF
16V
10%
X7R
0402
COMMON

C733
.1UF
16V
10%
X7R
0402
COMMON

C684
4700PF
25V
10%
X7R
0402
COMMON

SPDIF_C

5

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

PAGEID
DATE

16-MAR-2007

HFDBA

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

G1B

BGA_0820_P100_330X330_G3_128B

4,5,9

1

Frame Buffer A GPU

2

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

4,7,13 GPIO10_FBVREFCTL

IN

4,5,9

4,5,9

1G1D1S

D

Q9

SOT23

G

1

COMMON

S

FBAD[63..0]

BI

FBADQM[7..0]

BI

FBADQS_WP[7..0]

BI

FBADQS_RN[7..0]

4,5,9

IN

6

OUT

R88

511

1%

0402

COMMON

R86

R87

845

1.3K

1%

1%

0402

0402

COMMON

FB_VREF1CTL

3

2

60V

0.115A

7.5R

0.8A

0.2W
20V

COMMON

0

FBAD0

1

FBAD1

2

FBAD2

3

FBAD3

4

FBAD4

5

FBAD5

6

FBAD6

7

FBAD7

8

FBAD8

9

FBAD9

10

FBAD10

11

FBAD11

12

FBAD12

13

FBAD13

14

FBAD14

15

FBAD15

16

FBAD16

17

FBAD17

18

FBAD18

19

FBAD19

20

FBAD20

21

FBAD21

22

FBAD22

23

FBAD23

24

FBAD24

25

FBAD25

26

FBAD26

27

FBAD27

28

FBAD28

29

FBAD29

30

FBAD30

31

FBAD31

32

FBAD32

33

FBAD33

34

FBAD34

35

FBAD35

36

FBAD36

37

FBAD37

38

FBAD38

39

FBAD39

40

FBAD40

41

FBAD41

42

FBAD42

43

FBAD43

44

FBAD44

45

FBAD45

46

FBAD46

47

FBAD47

48

FBAD48

49

FBAD49

50

FBAD50

51

FBAD51

52

FBAD52

53

FBAD53

54

FBAD54

55

FBAD55

56

FBAD56

57

FBAD57

58

FBAD58

59

FBAD59

60

FBAD60

61

FBAD61

62

FBAD62

63

FB_VREF

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

C602
.1UF

16V
10%
X7R
0402
COMMON

FBAD63

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

R1

R2

COMMON

2/14 FBA

N27

FBAD0

M27

FBAD1

N28

FBAD2

L29

FBAD3

K27

FBAD4

K28

FBAD5

J29

FBAD6

J28

FBAD7

P30

FBAD8

N31

FBAD9

N30

FBAD10

N32

FBAD11

L31

FBAD12

L30

FBAD13

J30

FBAD14

L32

FBAD15

H30

FBAD16

K30

FBAD17

H31

FBAD18

F30

FBAD19

H32

FBAD20

E31

FBAD21

D30

FBAD22

E30

FBAD23

H28

FBAD24

H29

FBAD25

E29

FBAD26

J27

FBAD27

F27

FBAD28

E27

FBAD29

E28

FBAD30

F28

FBAD31

AD29

FBAD32

AE29

FBAD33

AD28

FBAD34

AC28

FBAD35

AB29

FBAD36

AA30

FBAD37

Y28

FBAD38

AB30

FBAD39

AM30

FBAD40

AF30

FBAD41

AJ31

FBAD42

AJ30

FBAD43

AJ32

FBAD44

AK29

FBAD45

AM31

FBAD46

AL30

FBAD47

AE32

FBAD48

AE30

FBAD49

AE31

FBAD50

AD30

FBAD51

AC31

FBAD52

AC32

FBAD53

AB32

FBAD54

AB31

FBAD55

AG27

FBAD56

AF28

FBAD57

AH28

FBAD58

AG28

FBAD59

AG29

FBAD60

AD27

FBAD61

AF27

FBAD62

AE28

FBAD63

M29

FBADQM0

M30

FBADQM1

G30

FBADQM2

F29

FBADQM3

AA29

FBADQM4

AK30

FBADQM5

AC30

FBADQM6

AG30

FBADQM7

L28

FBADQS_WP0

K31

FBADQS_WP1

G32

FBADQS_WP2

G28

FBADQS_WP3

AB28

FBADQS_WP4

AL32

FBADQS_WP5

AF32

FBADQS_WP6

AH30

FBADQS_WP7

M28

FBADQS_RN0

K32

FBADQS_RN1

G31

FBADQS_RN2

G27

FBADQS_RN3

AA28

FBADQS_RN4

AL31

FBADQS_RN5

AF31

FBADQS_RN6

AH29

FBADQS_RN7

E32

12mil

FB_VREF1

C GE

ASSEMBLY
PAGE DETAIL

FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

FBA_DEBUG

H_PLLAVDD

FBA_PLLAVDD

FBA_PLLGND

Frame Buffer A GPU

A12
A18
A21
A24
A27
A3
A30
A6
A9
AA32
AD32
AG32
AK32
C32
F32
J32
M32
R32

AA25
AA26
AB25
AB26
G11
G12
G15
G18
G21
G22
H11
H12
H15
H18
H21
H22
L25
L26
M25
M26
R25
R26
V25
V26

P32
U27
P31
U30
Y31
W32
W31
T32
V27
T28
T31
U32
W29
W30
T27
V28
V30
U31
R27
V29
T30
W28
R29
R30
P29
U28
Y32
Y30
V32

P28
R28
Y27
AA27

AC27

G23
G25
G24

SNN_FBA_NC1_D31

D31

NC1

SNN_FBA_NC2_D32

D32

NC2

NET_NAME

FBA_CLK0*
FBA_CLK1
FBA_CLK1*

FBA_DEBUG

FBA_PLLAVDD

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
SNN_FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
SNN_FBA_CMD26
FBA_CMD27
SNN_FBA_CMD28

OUT
OUT
OUT
OUT

C719
.1UF

6.3V
10%
X7R
0402
COMMON

C626
.1UF

6.3V
10%
X7R
0402
COMMON

C596
.1UF

6.3V
10%
X7R
0402
COMMON

C593
.1UF

6.3V
10%
X7R
0402
COMMON

C598
1UF

6.3V
10%
X7R
0603
COMMON

0
1
2
3
4
5
6
7
8

9
10
11
12
13

15
16
17
18
19
20
21
22
23
24
25

27

4,5,9FBA_CLK0
4,5,9
4,5,9
4,5,9

TP501

12mil

C701
.1UF

6.3V
10%
X7R
0402
COMMON

C625
.1UF

6.3V
10%
X7R
0402
COMMON

C645
.1UF

6.3V
10%
X7R
0402
COMMON

C591
.1UF

6.3V
10%
X7R
0402
COMMON

C48
1UF

6.3V
10%
X7R
0603
COMMON

FBA_CMD[27..0]

C570
470PF
50V
10%
X7R
0402
COMMON

C689
.1UF

6.3V
10%
X7R
0402
COMMON

C613
.1UF

6.3V
10%
X7R
0402
COMMON

C595
.1UF

6.3V
10%
X7R
0402
COMMON

C718
.1UF

6.3V
10%
X7R
0402
COMMON

C599
1UF

6.3V
10%
X7R
0603
COMMON

C621
.022UF
16V
10%
X7R
0402
COMMON

C657
.1UF

6.3V
10%
X7R
0402
COMMON

C629
.1UF

6.3V
10%
X7R
0402
COMMON

C736
.1UF

6.3V
10%
X7R
0402
COMMON

C618
.1UF

6.3V
10%
X7R
0402
COMMON

C35
1UF

6.3V
10%
X7R
0603
COMMON

C567
1UF

6.3V
10%
X7R
0603
COMMON

OUT

180R@100MHz

IND_SMD_0603

C699

C650

C658

.1UF

.1UF

6.3V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C683

C614

.1UF

.1UF

6.3V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C663

C655

.1UF

.1UF

6.3V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C633

C751

.1UF

.1UF

6.3V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C616

C673

1UF

1UF

6.3V

6.3V

10%

10%

X7R

X7R

0603

0603

COMMON

COMMON

4,5,9

.1UF

16V
10%
X7R
0402
COMMON

C628
.1UF

16V
10%
X7R
0402
COMMON

C627
.1UF

16V
10%
X7R
0402
COMMON

C641
.1UF

16V
10%
X7R
0402
COMMON

C612
.1UF

16V
10%
X7R
0402
COMMON

C713
.1UF

16V
10%
X7R
0402
COMMON

1

2

3

4

LB501

COMMON

5

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

PAGEID
DATE

16-MAR-2007

HFDBA

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

FB Partition A

1

2

3,5,9

R522
121

1%
0402
COMMON

FBA_CLK0_TERM FBA_CLK1_TERM

C529

R101

.01UF

121

25V

1%
0402

10%

COMMON

X7R
0402
COMMON

3,5,9

IN

3,5,9

IN

MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

Stuff CKE Pull-down resistor only

FBA_CMD[27..0]

IN

CMD-Addr

136 ADDR

CMD1 RAS*
CMD10 CAS*

1

FBA_CMD1

10

FBA_CMD10

11

FBA_CMD11

8

FBA_CMD8

19

FBA_CMD19

25

FBA_CMD25
22
24

FBA_CMD24

0

FBA_CMD0

2

FBA_CMD2

21

FBA_CMD21
16

FBA_CMD16
23

FBA_CMD23
20

FBA_CMD20
17

FBA_CMD17
9

FBA_CMD9

12

FBA_CMD12
3

FBA_CMD3
27

FBA_CMD27

18

FBA_CMD18

FBA_CLK0

FBA_CLK0*

SNN_FBA0_NC1 SNN_FBA1_NC1

7

FBA_CMD7 FBA_CMD7

15

FBA_CMD15 FBA_CMD15

R509

R527

10K

10K

5%

5%

0402

0402

COMMON

COMMON

R103
121

1%
0402
COMMON

GDDR3:

CMD11 WE*
CMD8 CS0*
CMD7 BA2
CMD19 A<0>
CMD25 A<1>
CMD22 0A<2>
CMD24 0A<3>
CMD0 0A<4>
CMD2 0A<5>
CMD4 1A<2>
CMD6 1A<3>
CMD5 1A<4>
CMD13 1A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD18 CKE
CMD15 RST

R507 10K

0402 COMMON

5%

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

9

OUT

FBA_ZQ0

R104
240

5%
0402
COMMON

H3

F4

H9

F9

K4
H2
K3
M4

K9
H11
K10

L9

K11

M9

K2

L4

G4

G9
H10

H4

J11
J10

J2
J3
V4

V9
A9
A4

K1
K12

M3E

BGA_0136_P080_140X110
BGA136
COMMON

RAS BA2
CAS CS
WE CKE
CS CAS

A0 A4
A1 A5
A2 A6
A3 A9
A4 A0
A5 A1
A6 A2
A7 A11

A9 A3
A10 A8/AP
A11 A7

BA0
BA1 BA0
BA2 RAS

CKE WE
CLK
CLK

NC/RFU
NC/CS1 NC/CS1
SEN (GND)

NONMIRROR

RESET
MIRROR
ZQ

VDDA
VDDA

A10A8/AP

BA1

MIRROR

3

J1

VSSA

J12

VSSA

*CS1 is required 32Mx32 Memories

FBAD[63..0]

3,5,9

BI

M3A

BGA_0136_P080_140X110
BGA136

0

FBAD0

1

FBAD1

2

FBAD2

3

FBAD3

4

3,5,9 FBADQM[7..0]

4

BI

3,5,9 FBADQS_RN[7..0]

BI

3,5,9 FBADQS_WP[7..0]

BI

0

FBADQM0

1

FBADQM1

2

FBADQM2

3

FBADQM3
4
5

FBADQM5
6

FBADQM6
7

FBADQM7

0

FBADQS_RN0
1

FBADQS_RN1
2

FBADQS_RN2
3

FBADQS_RN3
4

FBADQS_RN4
5

FBADQS_RN5
6

FBADQS_RN6
7

FBADQS_RN7

0

FBADQS_WP0
1

FBADQS_WP1
2

FBADQS_WP2
3

FBADQS_WP3
4

FBADQS_WP4
5

FBADQS_WP5
6

FBADQS_WP6
7

FBADQS_WP7

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

FBAD4

5

FBAD5

6

FBAD6

7

FBAD7

FBADQM0
FBADQS_RN0
FBADQS_WP0

32

FBAD32

33

FBAD33

34

FBAD34

35

FBAD35

36

FBAD36

37

FBAD37

38

FBAD38

39

FBAD39

FBADQM4
FBADQS_RN4
FBADQS_WP4

C10
B10
B11
C11

F10

F11
E11
G10

E10
D10
D11

E2

F3

G3

F2
B2
C3
B3
C2

E3
D3
D2

COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M4E

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

Topside memory

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

G12

VSS

L12

VSS

FBA_VREF0

H1

VREF

FBA_VREF2

H12

VREF

8

FBAD8

9

FBAD9

10

FBAD10

11

FBAD11

12

FBAD12

13

FBAD13

14

FBAD14

15

FBAD15

FBADQM1
FBADQS_RN1
FBADQS_WP1

40

FBAD40

41

FBAD41

42

FBAD42

43

FBAD43

44

FBAD44

45

FBAD45

46

FBAD46

47

FBAD47

FBADQM5
FBADQS_RN5
FBADQS_WP5

COMMON

COMMON

E2
B3
B2
C2
G3
F3
F2
C3

E3
D3
D2

T11
M11
L10
N11
M10
R10
R11
T10

N10
P10
P11

R111

511

R1

1%

0402

R110

1.3K

R2

1%

0402

M3B

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M4A

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

C GE

3,5,9

3,5,9

IN
IN

MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

5,9

OUT

C120
.1UF

16V
10%
X7R
0402
COMMON

16

FBAD16

17

FBAD17

18

FBAD18

19

FBAD19

20

FBAD20

21

FBAD21

22

FBAD22

23

FBAD23

FBADQM2
FBADQS_RN2
FBADQS_WP2

48

FBAD48

49

FBAD49

50

FBAD50

51

FBAD51

52

FBAD52

53

FBAD53

54

FBAD54

55

FBAD55

FBADQM6
FBADQS_RN6
FBADQS_WP6

ASSEMBLY
PAGE DETAIL

R519
121

1%
0402
COMMON

R102
121

1%
0402
COMMON

COMMON

COMMON

R90
511

0402

R89

1.3K

0402

R1

1%

R2

1%

C534

R100

.01UF

121

25V

1%
0402

10%

COMMON

X7R
0402
COMMON

GDDR3:

OUT

C75
.1UF

16V
10%
X7R
0402
COMMON

M3C

BGA_0136_P080_140X110
BGA136
COMMON

N2

DQ0

M3

DQ1

L3

DQ2

R3

DQ3

M2

DQ4

T3

DQ5

R2

DQ6

T2

DQ7

N3

DQM

P3

RDQS

P2

WDQS

M4B

BGA_0136_P080_140X110
BGA136
COMMON

E11

DQ0

G10

DQ1

F11

DQ2

F10

DQ3

B10

DQ4

C10

DQ5

C11

DQ6

B11

DQ7

E10

DQM

D10

RDQS

D11

WDQS

Frame Buffer A Memories Rank0

CMD-Addr

136 ADDR

CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD7 BA2
CMD19 A<0>
CMD25 A<1>
CMD22 0A<2>
CMD24 0A<3>
CMD0 0A<4>
CMD2 0A<5>
CMD4 1A<2>
CMD6 1A<3>
CMD5 1A<4>
CMD13 1A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD18 CKE
CMD15 RST

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

5,9

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

9

FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31

FBADQM3FBADQM4
FBADQS_RN3
FBADQS_WP3

FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

FBADQM7
FBADQS_RN7
FBADQS_WP7

M4D

BGA_0136_P080_140X110

BGA136

FBA_ZQ1

R99
240

5%
0402
COMMON

M3D

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M4C

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

H3
F4
H9
F9

K4
H2
K3
M4

K9
H11
K10

L9
K11

M9

K2

L4

G4

G9
H10

H4

J11
J10

J2
J3
V4

V9
A9
A4

K1

K12

J1

J12

COMMON

RAS BA2
CAS CS
WE CKE
CS CAS

A0 A4
A1 A5
A2 A6
A3 A9
A4 A0
A5 A1
A6 A2

A11 A7

BA0

CKE WE
CLK
CLK

NC/RFU
NC/CS1 NC/CS1
SEN (GND)

NONMIRROR

RESET
MIRROR
ZQ

VDDA
VDDA

VSSA
VSSA

*CS1 is required 32Mx32 Memories

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

A11A7

VDDQ

R1

A10A8/AP

VDDQ

V1

A3A9

VDDQ

C4

A8/APA10

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

BA1

VDDQ

C9

BA0BA1

VDDQ

E9

RASBA2

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

MIRROR

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

G12

VSS

L12

VSS

FBA_VREF1

H1

VREF

FBA_VREF3

H12

VREF

27

FBA_CMD27

8

FBA_CMD8

18

FBA_CMD18

10

FBA_CMD10

5

FBA_CMD5

13

FBA_CMD13

21

FBA_CMD21FBA_CMD22

20

FBA_CMD20

19

FBA_CMD19

25

FBA_CMD25

4

FBA_CMD4

9

FBA_CMD9

17

FBA_CMD17

6

FBA_CMD6

23

FBA_CMD23

16

FBA_CMD16

3

FBA_CMD3

12

FBA_CMD12

1

FBA_CMD1

11

FBA_CMD11
FBA_CLK1
FBA_CLK1*

7

15

OUT

M10
L10
R11
M11
N11
R10
T10
T11

N10
P10
P11

R3
R2

T2

T3
N2
M2
M3

L3
N3

P3

P2

Low Power VREF Switch

R92 845

VREF = FBVDDQ * R2/(R1 + R2)

Low Power:

High Perf:

R94

511

1%

0402

COMMON

R93

1.3K

1%

0402

COMMON

FBA_VREF1

FBA_VREF2

FBA_VREF0

FBA_VREF3

0.72V = 1.8V * (1.3K|464)/(511 + (1.3K|464))

1.29V = 1.8V * 1.3K/(511 + 1.3K)

R1

R2

VREF = 0.40 * FBVDDQ

VREF = 0.70 * FBVDDQ

C76
.1UF

16V
10%
X7R
0402
COMMON

1%

R91

0402

1%

60V

0.115A

7.5R

0.8A

0.2W
20V

R106

0402 COMMON

1%

R109

0402 COMMON

1%

60V

0.115A

7.5R

0.8A

0.2W
20V

5,9

OUT

COMMON0402

845

COMMON

845
845

SOT23

FBA_VREFCTL2

SOT23

Decoupling for FBA 0..31

C507

C557

C502
1UF

6.3V
10%
X7R
0603
COMMON

C533
1UF

6.3V
10%
X7R
0603
COMMON

C532
1UF

6.3V
10%
X7R
0603
COMMON

C559
1UF

6.3V
10%
X7R
0603
COMMON

C558
1UF

6.3V
10%
X7R
0603
COMMON

C503
1UF

6.3V
10%
X7R
0603
COMMON

.1UF

6.3V
10%
X7R
0402
COMMON

C509
.1UF

6.3V
10%
X7R
0402
COMMON

C520
.1UF

6.3V
10%
X7R
0402
COMMON

C505
.1UF

6.3V
10%
X7R
0402
COMMON

C551
.1UF

6.3V
10%
X7R
0402
COMMON

C544
.1UF

6.3V
10%
X7R
0402
COMMON

.1UF

6.3V
10%
X7R
0402
COMMON

C543
.1UF

6.3V
10%
X7R
0402
COMMON

C554
.1UF

6.3V
10%
X7R
0402
COMMON

C517
.1UF

6.3V
10%
X7R
0402
COMMON

C504
.1UF

6.3V
10%
X7R
0402
COMMON

C506
.1UF

6.3V
10%
X7R
0402
COMMON

C555
.1UF

6.3V
10%
X7R
0402
COMMON

C527
.1UF

6.3V
10%
X7R
0402
COMMON

C549
.1UF

6.3V
10%
X7R
0402
COMMON

C512
.1UF

6.3V
10%
X7R
0402
COMMON

C521
.1UF

6.3V
10%
X7R
0402
COMMON

C511
.1UF

6.3V
10%
X7R
0402
COMMON

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

FBA_VREFCTL1

3

D

Q502

COMMON

S

2

3

D

Q501

COMMON

S

2

R107

511

1%

0402

COMMON

R108

1.3K

1%

0402

COMMON

C552
.1UF

6.3V
10%
X7R
0402
COMMON

C548
.1UF

6.3V
10%
X7R
0402
COMMON

C524
.1UF

6.3V
10%
X7R
0402
COMMON

C510
.1UF

6.3V
10%
X7R
0402
COMMON

C553
.1UF

6.3V
10%
X7R
0402
COMMON

C539
.1UF

6.3V
10%
X7R
0402
COMMON

600-10409-xxxx-300 A

R548
10K

5%
0402

GPIO10_FBVREFCTL

COMMON

R545
10K

5%
0402
COMMON

3,7,13

IN

1G1D1S

G

1

1G1D1S

G

1

1

2

R1

R2

C119
.1UF

16V
10%
X7R
0402
COMMON

5,9

OUT

3

C516
.1UF

6.3V
10%
X7R
0402
COMMON

C513
.1UF

6.3V
10%
X7R
0402
COMMON

C550
.1UF

6.3V
10%
X7R
0402
COMMON

C111
.1UF

6.3V
10%
X7R
0402
COMMON

C526
.1UF

6.3V
10%
X7R
0402
COMMON

C508
.1UF

6.3V
10%
X7R
0402
COMMON

PAGEID
DATE

16-MAR-2007

HFDBA

4

5

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

FB Partition A

1

2

3,4,9

3,4,9

IN

3,4,9

IN

ZQ = 6x desired output GDDR3:

GDDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

FBA_CMD[27..0]

IN

CMD-Addr

136 ADDR

CMD1 RAS*
CMD10 CAS*

27
CMD11 WE*
CMD8 CS0*

CMD19 A<0>
CMD25 A<1>
CMD22 0A<2>
CMD24 0A<3>
CMD0 0A<4>
CMD2 0A<5>
CMD4 1A<2>
CMD6 1A<3>
CMD5 1A<4>
CMD13 1A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11> CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD18 CKE
CMD15 RST
CMD7 CS1*

9

OUT

FBA_CMD27

7

FBA_CMD7

18

FBA_CMD18

10

FBA_CMD10

0

FBA_CMD0

2

FBA_CMD2

21

FBA_CMD21

20

FBA_CMD20

19

FBA_CMD19

25

FBA_CMD25
22
9

FBA_CMD9
17

FBA_CMD17
24

FBA_CMD24

23

FBA_CMD23
16

FBA_CMD16

3

FBA_CMD3
12

FBA_CMD12
1

FBA_CMD1

11

FBA_CMD11

FBA_CLK0

FBA_CLK0*

SNN_FBA0_NC3 SNN_FBA1_NC2
SNN_FBA0_NC2

15

FBA_CMD15 FBA_CMD15

FBA_ZQ2

3

FBAD[63..0]

3,4,9

BI

0

FBAD0

1

FBAD1

2

FBAD2

3

FBAD3

4

3,4,9 FBADQM[7..0]

4

BI

3,4,9 FBADQS_RN[7..0]

BI

3,4,9 FBADQS_WP[7..0]

BI

0

FBADQM0

1

FBADQM1

2

FBADQM2

3

FBADQM3
4
5

FBADQM5
6

FBADQM6
7

FBADQM7

0

FBADQS_RN0
1

FBADQS_RN1
2

FBADQS_RN2
3

FBADQS_RN3
4

FBADQS_RN4
5

FBADQS_RN5
6

FBADQS_RN6
7

FBADQS_RN7

0

FBADQS_WP0
1

FBADQS_WP1
2

FBADQS_WP2
3

FBADQS_WP3
4

FBADQS_WP4
5

FBADQS_WP5
6

FBADQS_WP6
7

FBADQS_WP7

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

FBAD4

5

FBAD5

6

FBAD6

7

FBAD7

FBADQM0
FBADQS_RN0
FBADQS_WP0

32

FBAD32

33

FBAD33

34

FBAD34

35

FBAD35

36

FBAD36

37

FBAD37

38

FBAD38

39

FBAD39

FBADQM4
FBADQS_RN4
FBADQS_WP4

R535
240

5%
0402
COMMON

H3

F4

H9

F9

K4
H2
K3
M4

K9
H11
K10

L9

K11

M9

K2

L4

G4

G9
H10

H4

J11
J10

J2
J3
V4

V9
A9
A4

K1
K12

J1

J12

M502E

BGA_0136_P080_140X110
BGA136
COMMON

RAS BA2
CAS CS
WE CKE
CS CAS

A0 A4
A2 A6

A3 A9
A4 A0

A7 A11
A8/AP A10

A10 A8/AP
A11 A7

BA0
BA1 BA0

CLK
CLK

NC/RFU
NC/CS1 NC/CS1
SEN (GND)

NONMIRROR

RESET
MIRROR
ZQ

VDDA
VDDA

VSSA
VSSA

*CS1 is required 32Mx32 Memories

BOTTOM SIDE MEMORY

VDD
VDD
VDD
VDD
VDD
VDD

A5A1

VDD
VDD

VDDQ

A1A5

VDDQ

A2A6

VDDQ
VDDQ
VDDQ

A3A9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

BA1

VDDQ
VDDQ

RASBA2

VDDQ
VDDQ

WECKE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

MIRROR

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

M502A

BGA_0136_P080_140X110
BGA136

C3
B3
B2
C2

F3

F2
E2
G3

E3
D3
D2

E11

F10

G10

F11
B11
C10
B10
C11

E10
D10
D11

COMMON

M501E

BGA_0136_P080_140X110
BGA136
COMMON

8

DQ0

9

DQ1

10

DQ2

11

DQ3

12

DQ4

13

DQ5

14

DQ6

15

DQ7
DQM

RDQS
WDQS

40

DQ0

41

DQ1

42

DQ2

43

DQ3

44

DQ4

45

DQ5

46

DQ6

47

DQ7
DQM

RDQS
WDQS

F1
M1
A2
V2
A11
V11
F12
M12

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10
G12
L12

H1

FBA_VREF0

H12

FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15

FBADQM1
FBADQS_RN1
FBADQS_WP1

FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47

FBADQM5
FBADQS_RN5
FBADQS_WP5

OUT
OUT

E11
B10
B11
C11
G10
F10
F11
C10

E10
D10
D11

T2
M2
L3
N2
M3
R3
R2
T3

N3
P3
P2

4,9FBA_VREF2
4,9

M502B

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M501A

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

C GE

FBA_ZQ3

R105
240

5%
0402
COMMON

M502D

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M501C

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

H3
F4
H9
F9

K4
H2
K3
M4

K9
H11
K10

L9
K11

M9

K2

L4

G4

G9
H10

H4

J11
J10

J2
J3

V4

V9

A9

A4

K1
K12

J1

J12

M501D

BGA_0136_P080_140X110
BGA136
COMMON

RAS BA2
CAS CS
WE CKE
CS CAS

A0 A4
A1 A5

A3 A9
A4 A0
A5 A1

BA0

CLK
CLK

NC/RFU
NC/CS1 NC/CS1
SEN (GND)

NONMIRROR

RESET
MIRROR
ZQ

VDDA
VDDA

VSSA
VSSA

*CS1 is required 32Mx32 Memories

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

A6A2

VDD

A1

VDDQ

C1

VDDQ

E1

A2A6

VDDQ

N1

A11A7

VDDQ

R1

A10A8/AP

VDDQ

V1

A3A9

VDDQ

C4

A8/APA10

VDDQ

E4

A7A11

VDDQ

J4

VDDQ

N4

VDDQ

R4

BA1

VDDQ

C9

BA0BA1

VDDQ

E9

RASBA2

VDDQ

J9

VDDQ

N9

WECKE

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

MIRROR

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

G12

VSS

L12

VSS

H1

VREF

FBA_VREF1

H12

VREF

4,9FBA_VREF3

OUT

4,9

OUT

Decoupling for FBA 0..31

C44
1UF

6.3V
10%
X7R
0603
COMMON

C21
1UF

6.3V
10%
X7R
0603
COMMON

C51
1UF

6.3V
10%
X7R
0603
COMMON

C53
1UF

6.3V
10%
X7R
0603
COMMON

C70
1UF

6.3V
10%
X7R
0603
COMMON

C43
1UF

6.3V
10%
X7R
0603
COMMON

C89
.1UF

6.3V
10%
X7R
0402
COMMON

C85
.1UF

6.3V
10%
X7R
0402
COMMON

C114
.1UF

6.3V
10%
X7R
0402
COMMON

C547
.1UF

6.3V
10%
X7R
0402
COMMON

C50
.1UF

6.3V
10%
X7R
0402
COMMON

C25
.1UF

6.3V
10%
X7R
0402
COMMON

C72
.1UF

6.3V
10%
X7R
0402
COMMON

C28
.1UF

6.3V
10%
X7R
0402
COMMON

C60
.1UF

6.3V
10%
X7R
0402
COMMON

C30
.1UF

6.3V
10%
X7R
0402
COMMON

C98
.1UF

6.3V
10%
X7R
0402
COMMON

C94
.1UF

6.3V
10%
X7R
0402
COMMON

C66
.1UF

6.3V
10%
X7R
0402
COMMON

C726
.1UF

6.3V
10%
X7R
0402
COMMON

C62
.1UF

6.3V
10%
X7R
0402
COMMON

C87
.1UF

6.3V
10%
X7R
0402
COMMON

C59
.1UF

6.3V
10%
X7R
0402
COMMON

C108
.1UF

6.3V
10%
X7R
0402
COMMON

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C57

C24

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C68

C86

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C83

C71

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C116

C115

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C67

C29

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C37

C102

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

600-10409-xxxx-300 A

PAGEID
DATE

16-MAR-2007

HFDBA

1

2

3

4

5

CMD-Addr

136 ADDR

CMD1 RAS*
CMD10 CAS*

1
CMD11 WE*
CMD8 CS0*
CMD27 BA2CMD27 BA2
CMD19 A<0>
CMD25 A<1>
CMD22 0A<2>
CMD24 0A<3>
CMD0 0A<4>
CMD2 0A<5>
CMD4 1A<2>
CMD6 1A<3>
CMD5 1A<4>
CMD13 1A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>

CMD12 BA0
CMD3 BA1
CMD18 CKE
CMD15 RST

M502C

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M501B

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

CMD7 CS1*

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

9

FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31

FBADQM3FBADQM4
FBADQS_RN3
FBADQS_WP3

FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

FBADQM7
FBADQS_RN7
FBADQS_WP7

3,4,9

IN

3,4,9

IN

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23

FBADQM2
FBADQS_RN2
FBADQS_WP2

FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55

FBADQM6
FBADQS_RN6
FBADQS_WP6

ASSEMBLY
PAGE DETAIL

N11
M10
L10
R10
M11
T10
R11
T11

N10
P10
P11

E2
G3
F2
F3
B3
C3
C2
B2

E3
D3
D2

Frame Buffer A Memories Rank1

FBA_CMD1

10

FBA_CMD10

11

FBA_CMD11

7

FBA_CMD7

19

FBA_CMD19

25

FBA_CMD25

4

FBA_CMD4

6

FBA_CMD6

5

FBA_CMD5

13

FBA_CMD13

21

FBA_CMD21FBA_CMD22

16

FBA_CMD16

23

FBA_CMD23

20

FBA_CMD20

17

FBA_CMD17

9

FBA_CMD9

12

FBA_CMD12

3

FBA_CMD3

27

FBA_CMD27

18

FBA_CMD18
FBA_CLK1
FBA_CLK1*

SNN_FBA1_NC3

15

OUT

M3

L3
R2
M2
N2
R3

T3

T2
N3

P3

P2

R10
R11
T11
T10
N11
M11
M10
L10

N10
P10
P11

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

7,8,9 FBCD[63..0]

BI

0

FBCD0

1

FBCD1

2

FBCD2

3

FBCD3

4

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7

FBCD4

5

FBCD5

6

FBCD6

7

FBCD7

8

FBCD8

9

FBCD9

10

FBCD10

11

FBCD11

12

FBCD12

13

FBCD13

14

FBCD14

15

FBCD15

16

FBCD16

17

FBCD17

18

FBCD18

19

FBCD19

20

FBCD20

21

FBCD21

22

FBCD22

23

FBCD23

24

FBCD24

25

FBCD25

26

FBCD26

27

FBCD27

28

FBCD28

29

FBCD29

30

FBCD30

31

FBCD31

32

FBCD32

33

FBCD33

34

FBCD34

35

FBCD35

36

FBCD36

37

FBCD37

38

FBCD38

39

FBCD39

40

FBCD40

41

FBCD41

42

FBCD42

43

FBCD43

44

FBCD44

45

FBCD45

46

FBCD46

47

FBCD47

48

FBCD48

49

FBCD49

50

FBCD50

51

FBCD51

52

FBCD52

53

FBCD53

54

FBCD54

55

FBCD55

56

FBCD56

57

FBCD57

58

FBCD58

59

FBCD59

60

FBCD60

61

FBCD61

62

FBCD62

63

FBCD63

1

Frame Buffer C GPU

2

FBCDQM[7..0]

7,8,9

3

BI

7,8,9

BI

7,8,9

BI

FBCDQS_WP[7..0]

FBCDQS_RN[7..0]

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

G1C

BGA_0820_P100_330X330_G3_128B
COMMON

3/14 FBC

B7

FBCD0

A7

FBCD1

C7

FBCD2

A2

FBCD3

B2

FBCD4

C4

FBCD5

A5

FBCD6

B5

FBCD7

F9

FBCD8

F10

FBCD9

D12

FBCD10

D9

FBCD11

E12

FBCD12

D11

FBCD13

E8

FBCD14

D8

FBCD15

E7

FBCD16

F7

FBCD17

D6

FBCD18

D5

FBCD19

D3

FBCD20

E4

FBCD21

C3

FBCD22

B4

FBCD23

C10

FBCD24

B10

FBCD25

C8

FBCD26

A10

FBCD27

C11

FBCD28

C12

FBCD29

A11

FBCD30

B11

FBCD31

B28

FBCD32

C27

FBCD33

C26

FBCD34

B26

FBCD35

C30

FBCD36

B31

FBCD37

C29

FBCD38

A31

FBCD39

D28

FBCD40

D27

FBCD41

F26

FBCD42

D24

FBCD43

E23

FBCD44

E26

FBCD45

E24

FBCD46

F23

FBCD47

B23

FBCD48

A23

FBCD49

C25

FBCD50

C23

FBCD51

A22

FBCD52

C22

FBCD53

C21

FBCD54

B22

FBCD55

E22

FBCD56

D22

FBCD57

D21

FBCD58

E21

FBCD59

E18

FBCD60

D19

FBCD61

D18

FBCD62

E19

FBCD63

A4

FBCDQM0

E11

FBCDQM1

F5

FBCDQM2

C9

FBCDQM3

C28

FBCDQM4

F24

FBCDQM5

C24

FBCDQM6

E20

FBCDQM7

C5

FBCDQS_WP0

E10

FBCDQS_WP1

E5

FBCDQS_WP2

B8

FBCDQS_WP3

A29

FBCDQS_WP4

D25

FBCDQS_WP5

B25

FBCDQS_WP6

F20

FBCDQS_WP7

C6

FBCDQS_RN0

E9

FBCDQS_RN1

E6

FBCDQS_RN2

A8

FBCDQS_RN3

B29

FBCDQS_RN4

E25

FBCDQS_RN5

A25

FBCDQS_RN6

F21

FBCDQS_RN7

4

3 FB_VREF

IN

C594
.1UF

16V
10%
X7R
0402
COMMON

A28

FB_VREF2

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

C GE

ASSEMBLY
PAGE DETAIL

FBCAL_TERM_GND

Frame Buffer C GPU

FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28

FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1

FBC_DEBUG

FBC_PLLVDD

FBC_PLLAVDD

FBC_PLLGND

FBCAL_PD_VDDQ

FBCAL_PU_GND

AA23
AB23
H16
H17
J10
J23
J24
J9
K11
K12
K21
K22
K24
K9
L23
M23
T25
U25

C13
A16
A13
B17
B20
A19
B19
B14
E16
A14
C15
B16
F17
C19
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20
C20
A15

E13
F13
F18
E17

F12

G8
G10
G9

K26
H26
J26

SNN_FBVTT_AA23
SNN_FBVTT_AB23
SNN_FBVTT_H16
SNN_FBVTT_H17
SNN_FBVTT_J10
SNN_FBVTT_J23
SNN_FBVTT_J24
SNN_FBVTT_J9
SNN_FBVTT_K11
SNN_FBVTT_K12
SNN_FBVTT_K21
SNN_FBVTT_K22
SNN_FBVTT_K24
SNN_FBVTT_K9
SNN_FBVTT_L23
SNN_FBVTT_M23
SNN_FBVTT_T25
SNN_FBVTT_U25

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
SNN_FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
SNN_FBC_CMD26
FBC_CMD27
SNN_FBC_CMD28

NET_NAME
FBC_CLK0

FBC_CLK1*

FBC_DEBUG

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBCAL_TERM_GND

12mil

SNN_FBC_PLLVDD

FBC_PLLAVDD
12mil

TP503

0
1
2
3
4
5
6
7
8

9
10
11
12
13

15
16
17
18
19
20
21
22
23
24
25

27

7,8,9

OUT

7,8,9FBC_CLK0*

OUT

7,8,9FBC_CLK1

OUT

7,8,9

OUT

12mil

12mil

R547

04021%COMMON

C702
470PF

50V
10%
X7R
0402
COMMON

R562 30.1

40.2

R561 40.2

04021%COMMON

COMMON0402

1%

C727
.022UF

16V
10%
X7R
0402
COMMON

C695
1UF

6.3V
10%
X7R
0603
COMMON

1

2

7,8,9FBC_CMD[27..0]

OUT

3

LB503180R@100MHz

IND_SMD_0603COMMON

4

5

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

PAGEID
DATE

16-MAR-2007

HFDBA

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

FB Partition C

1

2

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

6,8,9

IN

6,8,9

IN

Stuff CKE Pull-down resistor only

6,8,9

6,8,9 FBCDQM[7..0]

6,8,9 FBCDQS_RN[7..0]

6,8,9 FBCDQS_WP[7..0]

R568
121

1%
0402
COMMON

FBC_CLK0_TERM FBC_CLK1_TERM

R78
121

1%
0402
COMMON

MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBCD[63..0]

BI

BI

BI

BI

C692
.01UF

25V
10%
X7R
0402
COMMON

6,8,9

IN

R77
121

1%
0402
COMMON

R566 10K

0402 COMMON

5%

GDDR3:

FBC_CMD[27..0]

CMD-Addr

136 ADDR

CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD7 BA2
CMD19 A<0>
CMD25 A<1>
CMD22 0A<2>
CMD24 0A<3>
CMD0 0A<4>
CMD2 0A<5>
CMD4 1A<2>
CMD6 1A<3>
CMD5 1A<4>
CMD13 1A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD18 CKE
CMD15 RST

9 FBC_ZQ0

OUT

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

0

FBCDQM0

1

FBCDQM1

2

FBCDQM2

3

FBCDQM3
4
5

FBCDQM5
6

FBCDQM6
7

FBCDQM7

0

FBCDQS_RN0
1

FBCDQS_RN1
2

FBCDQS_RN2
3

FBCDQS_RN3
4

FBCDQS_RN4
5

FBCDQS_RN5
6

FBCDQS_RN6
7

FBCDQS_RN7

0

FBCDQS_WP0
1

FBCDQS_WP1
2

FBCDQS_WP2
3

FBCDQS_WP3
4

FBCDQS_WP4
5

FBCDQS_WP5
6

FBCDQS_WP6
7

FBCDQS_WP7

M1E

BGA_0136_P080_140X110
BGA136

1

FBC_CMD1

10

FBC_CMD10

11

FBC_CMD11

8

FBC_CMD8

19

FBC_CMD19

25

FBC_CMD25
22
24

FBC_CMD24

0

FBC_CMD0

2

FBC_CMD2

21

FBC_CMD21
16

FBC_CMD16
23

FBC_CMD23
20

FBC_CMD20
17

FBC_CMD17
9

FBC_CMD9

12

FBC_CMD12
3

FBC_CMD3
27

FBC_CMD27

18

FBC_CMD18

FBC_CLK0

FBC_CLK0*

SNN_FBC0_NC1 SNN_FBC1_NC1

7

FBC_CMD7 FBC_CMD7

15

FBC_CMD15 FBC_CMD15

R565

R567

10K

10K

5%

5%

0402

0402

COMMON

COMMON

COMMON

H3

RAS BA2

F4

H9

F9

K4
H2
K3
M4

K9
H11
K10

L9

K11

M9

K2

L4

G4

G9
H10

H4

J11
J10

J2
J3
V4

V9
A9
A4

R75
240

5%
0402
COMMON

K1

K12

J1

J12

0

FBCD0

1

FBCD1

2

FBCD2

3

FBCD3

4

FBCD4

5

FBCD5

6

FBCD6

7

FBCD7

FBCDQM0
FBCDQS_RN0
FBCDQS_WP0

32

FBCD32

33

FBCD33

34

FBCD34

35

FBCD35

36

FBCD36

37

FBCD37

38

FBCD38

39

FBCD39

FBCDQM4
FBCDQS_RN4
FBCDQS_WP4

CS CAS

A1 A5

A7 A11
A8/AP A10
A9 A3

BA0

BA2 RAS

CLK
CLK

NC/RFU
SEN (GND)

NONMIRROR

RESET
MIRROR
ZQ

VDDA
VDDA

VSSA
VSSA

*CS1 is required 32Mx32 Memories

M1A

BGA_0136_P080_140X110
BGA136
COMMON

M2
M3

L3

R2

T2
R3
N2

T3
N3

P3

P2

M2E

BGA_0136_P080_140X110
BGA136
COMMON

N2
M2

L3
M3

T2
R3
R2

T3
N3

P3

P2

CSCAS
CKEWE

A4A0
A6A2

A9A3
A0A4
A1A5
A2A6

A8/APA10
A7A11

BA1
BA0BA1

WECKE

NC/CS1NC/CS1

MIRROR

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

F1

VDD

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

G12

VSS

L12

VSS

FBC_VREF0

H1

VREF

FBC_VREF2

H12

VREF

8

FBCD8

9

FBCD9

10

FBCD10

11

FBCD11

12

FBCD12

13

FBCD13

14

FBCD14

15

FBCD15

FBCDQM1
FBCDQS_RN1
FBCDQS_WP1

40

FBCD40

41

FBCD41

42

FBCD42

43

FBCD43

44

FBCD44

45

FBCD45

46

FBCD46

47

FBCD47

FBCDQM5
FBCDQS_RN5
FBCDQS_WP5

COMMON

COMMON

F11
C11
C10
E11
B10
B11
G10
F10

E10
D10
D11

T10
R10
R11
M10
M11
N11
T11
L10

N10
P10
P11

Topside memory

R74
511

R1

1%

0402

R70

1.3K

R2

1%

0402

M1B

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M2A

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

6,8,9
6,8,9

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

C GE

IN
IN

MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

8,9

OUT

C36
.1UF

16V
10%
X7R
0402
COMMON

FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23

FBCDQM2
FBCDQS_RN2
FBCDQS_WP2

FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55

FBCDQM6
FBCDQS_RN6
FBCDQS_WP6

ASSEMBLY
PAGE DETAIL

R564
121

1%
0402
COMMON

R79
121

1%
0402
COMMON

COMMON

COMMON

R584

R585

511

0402

1.3K

0402

1%

1%

R1

R2

C646
.01UF

25V
10%
X7R
0402
COMMON

L10
M10
M11
N11
R10

T11

T10
R11

N10
P10
P11

G10
E11

F11

F10
B11
C10
C11
B10

E10
D10
D11

M1C

BGA_0136_P080_140X110
BGA136
COMMON

M2B

BGA_0136_P080_140X110
BGA136
COMMON

136 ADDR

CMD1 RAS*
CMD10 CAS*
CMD11 WE*
CMD8 CS0*
CMD7 BA2
CMD19 A<0>
CMD25 A<1>
CMD22 0A<2>
CMD24 0A<3>
CMD0 0A<4>
CMD2 0A<5>
CMD4 1A<2>
CMD6 1A<3>
CMD5 1A<4>
CMD13 1A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>

R80
121

CMD20 A<9>

1%

CMD17 A<10>

0402

CMD9 A<11>

COMMON

CMD12 BA0
CMD3 BA1
CMD18 CKE
CMD15 RST

GDDR3:

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

8,9

OUT

C743
.1UF

16V
10%
X7R
0402
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

Frame Buffer C Memories Rank0

CMD-Addr

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31

FBCDQM3FBCDQM4
FBCDQS_RN3
FBCDQS_WP3

FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

FBCDQM7
FBCDQS_RN7
FBCDQS_WP7

27

FBC_CMD27

8

FBC_CMD8

18

FBC_CMD18

10

FBC_CMD10

5

FBC_CMD5

13

FBC_CMD13

21

FBC_CMD21FBC_CMD22

20

FBC_CMD20

19

FBC_CMD19

25

FBC_CMD25

4

FBC_CMD4

9

FBC_CMD9

17

FBC_CMD17

6

FBC_CMD6

23

FBC_CMD23

16

FBC_CMD16

3

FBC_CMD3

12

FBC_CMD12

1

FBC_CMD1

11

FBC_CMD11
FBC_CLK1
FBC_CLK1*

7

15

9 FBC_ZQ1

OUT

M1D

BGA_0136_P080_140X110
BGA136
COMMON

G3

DQ0

F3

DQ1

F2

DQ2

C3

DQ3

B3

DQ4

E2

DQ5

B2

DQ6

C2

DQ7

E3

DQM

D3

RDQS

D2

WDQS

M2C

BGA_0136_P080_140X110
BGA136
COMMON

F3

DQ0

F2

DQ1

E2

DQ2

G3

DQ3

C2

DQ4

B2

DQ5

B3

DQ6

C3

DQ7

E3

DQM

D3

RDQS

D2

WDQS

R81
240

5%
0402
COMMON

M2D

H3

F4

H9

F9

K4
H2
K3
M4

K9
H11
K10

L9

K11

M9

K2

L4

G4

G9
H10

H4
J11
J10

J2
J3
V4

V9
A9
A4

K1
K12

J1

J12

*CS1 is required 32Mx32 Memories

BGA_0136_P080_140X110
BGA136
COMMON

RAS BA2

CS CAS
A0 A4

A1 A5

BA0

CLK
CLK

NC/RFU
SEN (GND)

NONMIRROR

RESET
MIRROR
ZQ

VDDA
VDDA

VSSA
VSSA

F1

VDD
CSCAS
CKEWE

A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A10A8/AP
A3A9
A8/APA10
A7A11

BA1
BA0BA1

RASBA2
WECKE

NC/CS1NC/CS1

MIRROR

M1

VDD

A2

VDD

V2

VDD

A11

VDD

V11

VDD

F12

VDD

M12

VDD

A1

VDDQ

C1

VDDQ

E1

VDDQ

N1

VDDQ

R1

VDDQ

V1

VDDQ

C4

VDDQ

E4

VDDQ

J4

VDDQ

N4

VDDQ

R4

VDDQ

C9

VDDQ

E9

VDDQ

J9

VDDQ

N9

VDDQ

R9

VDDQ

A12

VDDQ

C12

VDDQ

E12

VDDQ

N12

VDDQ

R12

VDDQ

V12

VDDQ

B1

VSSQ

D1

VSSQ

P1

VSSQ

T1

VSSQ

G2

VSSQ

L2

VSSQ

B4

VSSQ

D4

VSSQ

P4

VSSQ

T4

VSSQ

B9

VSSQ

D9

VSSQ

P9

VSSQ

T9

VSSQ

G11

VSSQ

L11

VSSQ

B12

VSSQ

D12

VSSQ

P12

VSSQ

T12

VSSQ

G1

VSS

L1

VSS

A3

VSS

V3

VSS

A10

VSS

V10

VSS

G12

VSS

L12

VSS

FBC_VREF1

H1

VREF

FBC_VREF3

H12

VREF

Decoupling for FBC 0..31

C620

C698
.1UF

6.3V
10%
X7R
0402
COMMON

C755
.1UF

6.3V
10%
X7R
0402
COMMON

C757
.1UF

6.3V
10%
X7R
0402
COMMON

C764
.1UF

6.3V
10%
X7R
0402
COMMON

C700
.1UF

6.3V
10%
X7R
0402
COMMON

C581
.1UF

6.3V
10%
X7R
0402
COMMON

C571
.1UF

6.3V
10%
X7R
0402
COMMON

C604
.1UF

6.3V
10%
X7R
0402
COMMON

C758
.1UF

6.3V
10%
X7R
0402
COMMON

C600
.1UF

6.3V
10%
X7R
0402
COMMON

C583
.1UF

6.3V
10%
X7R
0402
COMMON

C574
.1UF

6.3V
10%
X7R
0402
COMMON

1UF

6.3V
10%
X7R
0603
COMMON

C631
1UF

6.3V
10%
X7R
0603
COMMON

C765
1UF

6.3V
10%
X7R
0603
COMMON

C704
1UF

6.3V
10%
X7R
0603
COMMON

C708
1UF

6.3V
10%
X7R
0603
COMMON

C572
1UF

6.3V
10%
X7R
0603
COMMON

Low Power VREF Switch

FBC_VREF2

FBC_VREF1

FBC_VREF0

FBC_VREF3

VREF = FBVDDQ * R2/(R1 + R2)

VREF = 0.40 * FBVDDQ

Low Power:

0.72V = 1.8V * (1.3K|464)/(511 + (1.3K|464))

VREF = 0.70 * FBVDDQ

High Perf:

1.29V = 1.8V * 1.3K/(511 + 1.3K)

R554

511

R1

1%

0402

COMMON

R555

1.3K

R2

1%

0402

COMMON

C578

C763

.1UF

.1UF

6.3V

6.3V
10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C607

C754

.1UF

.1UF

6.3V

6.3V
10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C732

C610

.1UF

.1UF

6.3V

6.3V
10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C749

C735

.1UF

.1UF

6.3V

6.3V
10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C637

C762

.1UF

.1UF

6.3V

6.3V
10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C573

C750

.1UF

.1UF

6.3V

6.3V
10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C589
.1UF

16V
10%
X7R
0402
COMMON

OUT

C586
.1UF

6.3V
10%
X7R
0402
COMMON

C575
.1UF

6.3V
10%
X7R
0402
COMMON

C638
.1UF

6.3V
10%
X7R
0402
COMMON

C576
.1UF

6.3V
10%
X7R
0402
COMMON

C761
.1UF

6.3V
10%
X7R
0402
COMMON

C740
.1UF

6.3V
10%
X7R
0402
COMMON

R586 845

1%

R556 845

1%

60V

0.115A

7.5R

0.8A

0.2W
20V

R67 845

1%

R5571%845

60V

0.115A

7.5R

0.8A

0.2W
20V

8,9

COMMON0402

COMMON0402

COMMON0402

COMMON0402

FBC_VREFCTL1

3

1G1D1S

D

Q8

SOT23

G

1

COMMON

S

2

FBC_VREFCTL2

3

1G1D1S

D

Q503

SOT23

G

GPIO10_FBVREFCTL

1

COMMON

S

2

R559

511

R1

1%

0402

COMMON

R558

1.3K

R2

1%

0402

COMMON

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

C592
.1UF

16V
10%
X7R
0402
COMMON

1

3,4,13

IN

2

8,9

OUT

3

4

5

PAGEID
DATE

16-MAR-2007

HFDBA

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

FB Partition C

1

2

6,7,9

IN

6,7,9

IN

GDDR3:

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

FBC_CMD[27..0]

6,7,9

IN

CMD-Addr

136 ADDR

CMD1 RAS*
CMD10 CAS*

27

CMD11 WE*
CMD8 CS0*
CMD27 BA2
CMD19 A<0>
CMD25 A<1>
CMD22 0A<2>
CMD24 0A<3>
CMD0 0A<4>
CMD2 0A<5>
CMD4 1A<2>
CMD6 1A<3>
CMD5 1A<4>
CMD13 1A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD18 CKE
CMD15 RST
CMD7 CS1*

9 FBC_ZQ2

FBC_CMD27

7

FBC_CMD7

18

FBC_CMD18

10

FBC_CMD10

0

FBC_CMD0

2

FBC_CMD2

21

FBC_CMD21

20

FBC_CMD20

19

FBC_CMD19

25

FBC_CMD25
22
9

FBC_CMD9
17

FBC_CMD17
24

FBC_CMD24

23

FBC_CMD23
16

FBC_CMD16

3

FBC_CMD3
12

FBC_CMD12
1

FBC_CMD1

11

FBC_CMD11

FBC_CLK0

FBC_CLK0*

SNN_FBC0_NC3
SNN_FBC0_NC2

15

FBC_CMD15 FBC_CMD15

OUT

R76
240

5%
0402
COMMON

3

FBCD[63..0]

6,7,9

BI

0

FBCD0

1

FBCD1

2

FBCD2

3

FBCD3

4

6,7,9 FBCDQM[7..0]

4

BI

6,7,9 FBCDQS_RN[7..0]

BI

6,7,9 FBCDQS_WP[7..0]

BI

0

FBCDQM0

1

FBCDQM1

2

FBCDQM2

3

FBCDQM3
4
5

FBCDQM5
6

FBCDQM6
7

FBCDQM7

0

FBCDQS_RN0
1

FBCDQS_RN1
2

FBCDQS_RN2
3

FBCDQS_RN3
4

FBCDQS_RN4
5

FBCDQS_RN5
6

FBCDQS_RN6
7

FBCDQS_RN7

0

FBCDQS_WP0
1

FBCDQS_WP1
2

FBCDQS_WP2
3

FBCDQS_WP3
4

FBCDQS_WP4
5

FBCDQS_WP5
6

FBCDQS_WP6
7

FBCDQS_WP7

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

FBCD4

5

FBCD5

6

FBCD6

7

FBCD7

FBCDQM0
FBCDQS_RN0
FBCDQS_WP0

32

FBCD32

33

FBCD33

34

FBCD34

35

FBCD35

36

FBCD36

37

FBCD37

38

FBCD38

39

FBCD39

FBCDQM4
FBCDQS_RN4
FBCDQS_WP4

M504E

H3

F4

H9

F9

K4
H2
K3
M4

K9
H11
K10

L9

K11

M9

K2

L4

G4

G9
H10

H4

J11
J10

J2
J3
V4

V9
A9
A4

K1
K12

J1

J12

*CS1 is required 32Mx32 Memories

BGA_0136_P080_140X110
BGA136
COMMON

CAS CS
WE CKE
CS CAS

A0 A4
A1 A5
A2 A6
A3 A9

A6 A2
A7 A11
A8/AP A10
A9 A3
A10 A8/AP
A11 A7

BA0
BA1 BA0

BA2 RAS

CKE WE
CLK
CLK

NC/RFU
SEN (GND)

NONMIRROR

RESET
MIRROR
ZQ

VDDA
VDDA

VSSA
VSSA

BOTTOM SIDE MEMORY

BA2RAS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A0A4

VDDQ

A1A5

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

BA1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

NC/CS1NC/CS1

VDDQ
VDDQ
VDDQ

MIRROR

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

M504A

BGA_0136_P080_140X110
BGA136
COMMON

M11

DQ0

M10

DQ1

L10

DQ2

R11

DQ3

T11

DQ4

R10

DQ5

N11

DQ6

T10

DQ7

N10

DQM

P10

RDQS

P11

WDQS

M503E

BGA_0136_P080_140X110
BGA136
COMMON

N11

DQ0

M11

DQ1

L10

DQ2

M10

DQ3

T11

DQ4

R10

DQ5

R11

DQ6

T10

DQ7

N10

DQM

P10

RDQS

P11

WDQS

F1
M1
A2
V2
A11
V11
F12
M12

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10
G12
L12

H1
H12

8

FBCD8

9

FBCD9

10

FBCD10

11

FBCD11

12

FBCD12

13

FBCD13

14

FBCD14

15

FBCD15

FBCDQM1
FBCDQS_RN1
FBCDQS_WP1

40

FBCD40

41

FBCD41

42

FBCD42

43

FBCD43

44

FBCD44

45

FBCD45

46

FBCD46

47

FBCD47

FBCDQM5
FBCDQS_RN5
FBCDQS_WP5

OUT
OUT

F2
C2
C3
E2
B3
B2
G3
F3

E3
D3
D2

T3
R3
R2
M3
M2
N2
T2
L3

N3
P3
P2

7,9FBC_VREF2
7,9FBC_VREF0

M504B

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M503A

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

6,7,9
6,7,9

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

C GE

IN
IN

FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23

FBCDQM2
FBCDQS_RN2
FBCDQS_WP2

FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55

FBCDQM6
FBCDQS_RN6
FBCDQS_WP6

ASSEMBLY
PAGE DETAIL

CMD-Addr

136 ADDR

CMD1 RAS*
CMD10 CAS*

1

FBC_CMD1

CMD11 WE*

10

CMD8 CS0*

11

CMD27 BA2

7
CMD19 A<0>
CMD25 A<1>

19
CMD22 0A<2>

25
CMD24 0A<3>

4
CMD0 0A<4>
CMD2 0A<5>
CMD4 1A<2>
CMD6 1A<3>

CMD5 1A<4>
CMD13 1A<5>
CMD21 A<6>
CMD16 A<7>
CMD23 A<8>
CMD20 A<9>
CMD17 A<10>
CMD9 A<11>
CMD12 BA0
CMD3 BA1
CMD18 CKE
CMD15 RST
CMD7 CS1*

ZQ = 6x desired output
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

M504C

BGA_0136_P080_140X110
BGA136
COMMON

L3
M3
M2
N2
R3
T2
T3
R2

N3
P3
P2

M503B

BGA_0136_P080_140X110
BGA136
COMMON

G3
E2
F2
F3
B2
C3
C2
B3

E3
D3
D2

24

DQ0

25

DQ1

26

DQ2

27

DQ3

28

DQ4

29

DQ5

30

DQ6

31

DQ7
DQM

RDQS
WDQS

56

DQ0

57

DQ1

58

DQ2

59

DQ3

60

DQ4

61

DQ5

62

DQ6

63

DQ7
DQM

RDQS
WDQS

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Frame Buffer C Memories Rank1

FBC_CMD4

6

FBC_CMD6

5

FBC_CMD5

13

FBC_CMD13
21
16
23
20
17
9

12
3
27

18

15

9 FBC_ZQ3

OUT

FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31

FBCDQM3FBCDQM4
FBCDQS_RN3
FBCDQS_WP3

FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

FBCDQM7
FBCDQS_RN7
FBCDQS_WP7

FBC_CMD10
FBC_CMD11
FBC_CMD7

FBC_CMD19
FBC_CMD25

FBC_CMD21FBC_CMD22
FBC_CMD16
FBC_CMD23
FBC_CMD20
FBC_CMD17
FBC_CMD9

FBC_CMD12
FBC_CMD3
FBC_CMD27

FBC_CMD18
FBC_CLK1
FBC_CLK1*

SNN_FBC1_NC3
SNN_FBC1_NC2

G10

F10

F11
C10
B10
E11
B11
C11

E10
D10
D11

F10

F11
E11
G10
C11
B11
B10
C10

E10
D10
D11

R563
240

5%
0402
COMMON

M504D

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

M503C

BGA_0136_P080_140X110
BGA136
COMMON

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM
RDQS
WDQS

H3

F4

H9

F9

K4
H2
K3
M4

K9
H11
K10

L9

K11

M9

K2

L4

G4

G9
H10

H4
J11
J10

J2
J3
V4

V9
A9
A4

K1
K12

J1

J12

M503D

BGA_0136_P080_140X110
BGA136
COMMON

BA2RAS
CAS CS
WE CKE

A2 A6
A3 A9
A4 A0
A5 A1
A6 A2
A7 A11

A10 A8/AP
A11 A7

BA0
BA1 BA0

BA2 RAS
CKE WE

CLK
CLK

NC/RFU
NC/CS1 NC/CS1
SEN (GND)

NONMIRROR

RESET
MIRROR
ZQ

VDDA
VDDA

VSSA
VSSA

*CS1 is required 32Mx32 Memories

VDD
VDD
VDD

CASCS

VDD
VDD

A4A0

VDD

A5A1

VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ

A10A8/AP

VDDQ

A3A9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

BA1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

MIRROR

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREF
VREF

Decoupling for FBC 0..31

C77
1UF

6.3V
10%
X7R
0603
COMMON

C95
1UF

6.3V
10%
X7R
0603
COMMON

C78
1UF

6.3V
10%
X7R
0603
COMMON

C96
1UF

6.3V
10%
X7R
0603
COMMON

C117
1UF

6.3V
10%
X7R
0603
COMMON

C118
1UF

6.3V
10%
X7R
0603
COMMON

F1
M1
A2
V2
A11
V11
F12
M12

A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12

B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12

G1
L1
A3
V3
A10
V10
G12
L12

H1
H12

C69
.1UF

6.3V
10%
X7R
0402
COMMON

C33
.1UF

6.3V
10%
X7R
0402
COMMON

C20
.1UF

6.3V
10%
X7R
0402
COMMON

C80
.1UF

6.3V
10%
X7R
0402
COMMON

C90
.1UF

6.3V
10%
X7R
0402
COMMON

C54
.1UF

6.3V
10%
X7R
0402
COMMON

C112
.1UF

6.3V
10%
X7R
0402
COMMON

C109
.1UF

6.3V
10%
X7R
0402
COMMON

C23
.1UF

6.3V
10%
X7R
0402
COMMON

C97
.1UF

6.3V
10%
X7R
0402
COMMON

C58
.1UF

6.3V
10%
X7R
0402
COMMON

C93
.1UF

6.3V
10%
X7R
0402
COMMON

C38
.1UF

6.3V
10%
X7R
0402
COMMON

C22
.1UF

6.3V
10%
X7R
0402
COMMON

C82
.1UF

6.3V
10%
X7R
0402
COMMON

C91
.1UF

6.3V
10%
X7R
0402
COMMON

C61
.1UF

6.3V
10%
X7R
0402
COMMON

C27
.1UF

6.3V
10%
X7R
0402
COMMON

1

2

7,9FBC_VREF3

OUT

7,9FBC_VREF1

OUT

C538

C101

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C113

C63

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C45

C556

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C84

C92

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C110

C39

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C81

C79

.1UF

.1UF

6.3V

6.3V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

PAGEID
DATE

16-MAR-2007

HFDBA

3

4

5

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

FrameBuffer Net Rules

1

NET RULES for FrameBuffer A

NV_CRITICAL

3,4,5 FBA_CLK0
3,4,5 FBA_CLK0*
3,4,5
3,4,5

3,4,5,9
3,4,5
3,4,5 FBADQS_RN[7..0]
3,4,5 FBADQM[7..0]

3,4,5

NET NV_IMPEDANCE

IN
IN

FBA_CLK1

IN

FBA_CLK1*

IN

FBA_CMD[27..0]

IN

FBADQS_WP[7..0]

OUT
IN
OUT

FBAD[63..0]

BI

1

1 56OHM

1 40OHM
1 40OHM
1

80DIFF1 FBA_CLK0

80DIFF

40OHM1

40OHM

FBA_CLK080DIFF1
FBA_CLK1
FBA_CLK11 80DIFF

NET RULES for FrameBuffer C

NV_CRITICAL NV_IMPEDANCE DIFFPAIR

6,7,8 FBC_CLK0
6,7,8 FBC_CLK0*
6,7,8
6,7,8

6,7,8,9
6,7,8
6,7,8 FBCDQS_RN[7..0]
6,7,8 FBCDQM[7..0]

6,7,8

NETDIFFPAIR

IN
IN

FBC_CLK1

IN

FBC_CLK1*

IN

FBC_CMD[27..0]

IN

FBCDQS_WP[7..0]

OUT
IN
OUT

FBCD[63..0]

BI

1 FBC_CLK080DIFF
1 80DIFF FBC_CLK0
1

1 56OHM

1 40OHM
1 40OHM
1

80DIFF
80DIFF1 FBC_CLK1

40OHM1

40OHM

FBC_CLK1

2

R65

R69

R72

R82

R84

R85

R502

R501

R95

R96

R503

R504

R97

120

120

120

120

120

5%

5%

5%

0402

0402

COMMON

3,4,5,9

FBA_CMD[27..0]

IN

22

FBA_CMD22

24

FBA_CMD24

0

FBA_CMD0

2

FBA_CMD2

4

FBA_CMD4

6

FBA_CMD6

5

FBA_CMD5

13

FBA_CMD13

COMMON

0402
COMMON

5%
0402
COMMON

5%
0402
COMMON

120

5%
0402
COMMON

120

5%
0402
COMMON

R98
120

5%
0402
COMMON

6,7,8,9

FBC_CMD[27..0]

IN

22

FBC_CMD22

24

FBC_CMD24

0

FBC_CMD0

2

FBC_CMD2

4

FBC_CMD4

6

FBC_CMD6

5

FBC_CMD5

13

FBC_CMD13

R66
120

5%
0402
COMMON

120

5%
0402
COMMON

120

5%
0402
COMMON

120

5%
0402
COMMON

120

5%
0402
COMMON

120

5%
0402
COMMON

120

5%
0402
COMMON

R83
120

5%
0402
COMMON

3

FBA_VREF0

4,5

BI

4,5 FBA_VREF1

BI

FBA_VREF2

4,5

BI

FBA_VREF3

4,5

BI

4 FBA_ZQ0

BI

4 FBA_ZQ1

BI

FBA_ZQ2

5

BI

FBA_ZQ3

5

BI

0.02A 12MIL1.47V

1.47V

1.47V 0.02A 12MIL

1.47V 0.02A 12MIL

1.47V

0.02A 12MIL1.47V

0.02A 12MIL1.47V

MIN_WIDTH

NETMAX_CURRENTVOLTAGENET

FBC_VREF0

7,8

BI

7,8 FBC_VREF1

BI

FBC_VREF2

12MIL0.02A

12MIL0.02A
12MIL0.02A1.47V

7,8

BI

FBC_VREF3

7,8

BI

7 FBC_ZQ0

BI

7 FBC_ZQ1

BI

FBC_ZQ2

8

BI

FBC_ZQ3

8

BI

1.47V

1.47V

1.47V 0.02A 12MIL

0.02A

0.02A 12MIL

MIN_WIDTHMAX_CURRENTVOLTAGE

12MIL0.02A1.47V
12MIL0.02A1.47V

12MIL
12MIL0.02A1.47V

12MIL0.02A1.47V
12MIL0.02A1.47V

4

1

2

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

C GE

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

Frame Buffer Physical Constrains

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

5

PAGEID
DATE

16-MAR-2007

HFDBA

A B C D E F G H

DACs, Clockgeneration

R608

R578
150
1%
0402
COMMON

R631 33

5%

R571
150
1%
0402
COMMON

4.7K
5%
0402
COMMON

COMMON0402

R609

4.7K
5%
0402
COMMON

Place close to GPU

Place close to GPU

NV_CRITICAL NV_IMPEDANCE

1 50OHM

1 50OHM

NV_CRITICAL

1 50OHM

1 50OHM

1 50OHM

R634

4.7K
5%
0402
COMMON

R632

4.7K
5%
0402
COMMON

50OHM1

NV_IMPEDANCE

I2CB_SCL_R
I2CB_SDA_R

1

12I2CA_SCL_R

OUT

12I2CA_SDA_R

BI

12

OUT

12DACA_VSYNC

OUT

12

OUT

12DACA_GREEN

OUT

12

OUT

2

12

OUT

12DACB_GREEN

OUT

12

OUT

3

12

OUT

12

BI

1

C717
.01UF
25V
X7R
0402
COMMON

DACA_VDD

DACA_VREF

DACA_RSET

10%

LB506
IND_SMD_0603

COMMON

180R@100MHz

C770

4.7UF

6.3V
X5R
0603
COMMON

16mil

C725

C714

4700PF

470PF

10%

10%

25V

10%50V

X7R

X7R

0402

0402

COMMON

COMMON

2

LB507 180R@100MHz
IND_SMD_0603COMMON

C771

4.7UF

6.3V
X5R
0603
COMMON

DACB_VREF

C734

C728
470PF
50V
X7R
0402
COMMON

C746
.01UF

10%

25V

10%
X7R
0402
COMMON

4700PF

10%

25V

10%

X7R
0402
COMMON

DACB_VDD
18mil

DACB_RSET

3

R580 1K

DACC_VDD

COMMON0402

5%

SNN_DACC_VREF

SNN_DACC_RSET

R576
124
1%
0402
COMMON

R582
124
1%
0402
COMMON

G1D

BGA_0820_P100_330X330_G3_128B
COMMON

4/14 DACA

AD10

DACA_VDD

AH10

DACA_VREF

AH9

DACA_RSET

G1G

BGA_0820_P100_330X330_G3_128B
COMMON

V8
R5
R7

G1F

BGA_0820_P100_330X330_G3_128B
COMMON

AD7
AH4
AF5

5/14 DACB(TV)

DACB_VDD
DACB_VREF
DACB_RSET

6/14 DACC

DACC_VDD
DACC_VREF
DACC_RSET

I2CA_SCL
I2CA_SDA

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_IDUMP

DACB_CSYNC

DACB_RED

DACB_GREEN

DACB_BLUE

DACB_IDUMP

I2CB_SCL
I2CB_SDA

DACC_HSYNC
DACC_VSYNC

DACC_RED

DACC_GREEN

DACC_BLUE

DACC_IDUMP

I2CA_SCL

K2

I2CA_SDA

J3

DACA_HSYNC

AF10
AK10

DACA_RED

AH11
AJ12

DACA_BLUE

AH12

R604 33
0402

R605 33
0402 COMMON

5%

COMMON

5%

AG9

R573

R569

150

150

1%

1%

0402

0402

COMMON

COMMON

SNN_DACB_CSYNC

U5

DACB_RED

R6
T5

DACB_BLUE

T6

V7

I2CB_SCL

H4

I2CB_SDA

J4

DACC_HSYNC

AG7

DACC_VSYNC

AG5

SNN_DACC_RED

AF6

SNN_DACC_GREEN

AG6

SNN_DACC_BLUE

AE5

TP512
TP509

R581
150
1%
0402
COMMON

R6225%33

R583
150
1%
0402
COMMON

COMMON0402

AG4

4

LB504

C777

4.7UF

6.3V
10%
X5R
0603
COMMON

IND_SMD_0603

COMMON

180R@100MHz

C768
1UF

6.3V
X7R
0603
COMMON

16mil

C716
4700PF

10%

25V
10%
X7R
0402
COMMON

14

IN

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

PLL_VDD

C707
470PF
50V

10%
X7R
0402
COMMON

SSFOUT

50OHM 1

XTALIN

C7
22PF
50V
5%
C0G
0402
COMMON

G1E

BGA_0820_P100_330X330_G3_128B
COMMON

13/14 XTAL_PLL

T9

PLLAVDD

T10

VID_PLLVDD

U10

PLLGND

T1

XTALSSIN

U1

XTALIN

Y1

27 MHZ

50OHM1 1 50OHM

10 PPMXTAL_SMD_4_060X035
COMMON

13

C GE

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

XTALOUTBUFF

ASSEMBLY
PAGE DETAIL

XTALOUT

T2

U2

NV_IMPEDANCENV_CRITICNV_IMPEDANCENV_CRITIC

BXTALOUT

XTALOUT

DACs, Clock-Generation

50OHM 1

C4
18PF
50V
5%
C0G
0402
COMMON

R39
10K
5%
0402
COMMON

R10 22

4

XTALOUTBUFF

COMMON0402

5%

1 50OHM

14

OUT

5

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

PAGEID
DATE

16-MAR-2007

HFDBA

A B C D E F G H

LVDS / TMDS Interface

Loading options for IFPAB outputs

Option #1) IFPAB outputs to LVDS only.
Option #2) IFPAB outputs to DVI-C only.
Option #3) Controlled with GPIO9, IFPAB dynamically outputs to LVDS or DVI-C.

1

2

3

4

5

FB_VCC

17

IN

1G1D1S

D

G

1

S

current on
IFPA_IOVDD.

LVDS
Sequencing
Circuit

LB509 180R@100MHz
IND_SMD_0603COMMON

LB508 180R@100MHz
IND_SMD_0603COMMON

C769

4.7UF

6.3V
10%
X5R
0603
COMMON

C788

4.7UF

6.3V
10%
X5R
0603
COMMON

Load for option #2.

LB1

TMDSIOVDD_D_EN

R625
10K
5%
0402
COMMON

C6
.1UF
16V
10%
X7R
0402
COMMON

Delay to
control
inrush

LB505 180R@100MHz

COMMONIND_SMD_0603

LB512 180R@100MHz
IND_SMD_0603COMMON

LB2

180R@100MHz

COMMONIND_SMD_0603

180R@100MHz

COMMONIND_SMD_0603

C26

.1UF
16V
10%
X7R
0402
COMMON

R43
10K

5%
0402
COMMON

C787

4.7UF

6.3V
10%
X5R
0603
COMMON

LB510

C773

4.7UF

6.3V
10%
X5R
0603
COMMON

FB_PWRGOOD

17

IN

R640
0

5%
0402
COMMON

D

S

Load forLoad forLoad for
options
#1 and #3.

12mil

3

Q506

SOT23

COMMON

2

30V

4A@25C

0.066R@2.5V
16A

1W@25C

12V

12mil

C785

4.7UF

6.3V
10%
X5R
0603
COMMON

Load for option #2.

3

Q509

SOT23
COMMON

-8V

2

-2.8A@70C
52mR

-6A

0.8W@70C
+/-8V

TMDSIOVDD_C

12mil

TMDSIOVDD_D

D

G

1

S

Delay to control
inrush current
on IFPD_IOVDD.

1G1D1S

12mil

R32 1K

0402 COMMON

5%

3

Q4

SOT23

COMMON

-8V

2

-2.8A@70C
52mR

-6A

0.8W@70C
+/-8V

Q2B

SOT23_6
COMMON

4

1G1D1S

D

G

3

S

COMMON

SOT23_6
COMMON

2

R4

10K

5%

0402

1G1D1S

G

3

TMDSIOVDD_AB__EN*

3

Q507

SOT23

COMMON

-8V

2

-2.8A@70C
52mR

-6A

0.8W@70C
+/-8V

6

D

Q2A

G

1

S

5

4

D

Q508B

SOT23_6
COMMON

S

2

20V

2.4A

0.2R
8A

1.15W
+/-12V

20V

2.4A

0.2R
8A

1.15W
+/-12V

13 GPIO9_LVDS_SYS*

IN

20V

2.4A

0.2R
8A

1.15W
+/-12V

1G1D1S

RUNPWROK

12,14,16,17

IN

GPIO1_DVI_B_HPD

13

IN

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

option #3.

LVDSIOVDD_ISOL

3

1G1D1S

D

Q1

SOT23

G

1

COMMON

S

2

30V
4A@25C

0.066R@2.5V
16A
1W@25C
12V

1G1D1S

1G1D1S

D

G

1

C795

Load for
options
#1 and #3.

.1UF
16V
10%
X7R
0402
COMMON

TMDSIOVDD_C_EN*

SOT23_6

COMMON

R62

10K
5%
0402
COMMON

6

D

Q508A

5

20V

2.4A

0.2R
8A

1.15W
+/-12V

S

option
#1.

TMDS_LVDS_IOVDD

3

D

Q6

SOT23

G

1

COMMON

S

-8V

2

-2.8A@70C
52mR

-6A

0.8W@70C
+/-8V

1G1D1S

G

1

R638
10K
5%
0402
COMMON

1G1D1S

G

1

S

TMDSIOVDD_D_EN*

C GE

C775

4.7UF

6.3V
10%
X5R
0603
COMMON

C32

4.7UF

6.3V
10%
X5R
0603
COMMON

COMMONIND_SMD_0603

180R@100MHz

C752
.1UF
16V
10%
X7R
0402
COMMON

ASSEMBLY
PAGE DETAIL

G1I

BGA_0820_P100_330X330_G3_128B
COMMON

C724
470PF
50V
10%
X7R
0402
COMMON

C767
470PF
50V
10%
X7R
0402
COMMON

7/14 IFPAB

AM4

IFPAB_VPROBE

AL5

IFPAB_RSET

AC9

IFPAB_PLLVDD

AD9

IFPAB_PLLGND

AF9

IFPA_IOVDD

AF8

IFPB_IOVDD

G1H

BGA_0820_P100_330X330_G3_128B
COMMON

8/14 IFPCD

AK3

IFPCD_VPROBE

AH3

IFPCD_RSET

AA10

IFPCD_PLLVDD

AB10

IFPCD_PLLGND

AD6

IFPC_IOVDD

AE7

IFPD_IOVDD

IFPABVPROBE

TP511

IFPABRSET

R588

1K

0402

COMMON

1%

IFPABPLLVDD

12mil

C778

C723

4.7UF

4700PF

6.3V

25V

10%

10%

X5R

X7R

0603

0402

COMMON

COMMON

IFPAIOVDD

16mil

C772

C737

.022UF

4700PF

16V

25V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

IFPCVPROBE

TP510

R587
0402

C780

4.7UF

6.3V
10%
X5R
0603
COMMON

C745
.1UF
16V
10%
X7R
0402
COMMON

C731

.1UF
16V
10%
X7R
0402
COMMON

IFPCBRSET

1K
COMMON

1%

IFPCPLLVDD

12mil

C741

C722

4700PF

470PF

25V

50V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

12mil

C747

C742

4700PF

470PF

25V

50V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

IFPD_IOVDD

12mil

C31

C34

4700PF

470PF

25V

50V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
LVDS / TMDS Interface GPU

C19
.01UF

16V
10%
X7R
0402
COMMON

C17
.01UF

16V
10%
X7R
0402
COMMON

C13
.01UF

16V
10%
X7R
0402
COMMON

IFPA_TXC
IFPA_TXC

IFPA_TXD0
IFPA_TXD0

IFPA_TXD1
IFPA_TXD1

IFPA_TXD2
IFPA_TXD2

IFPA_TXD3
IFPA_TXD3

IFPB_TXC
IFPB_TXC

IFPB_TXD4
IFPB_TXD4

IFPB_TXD5
IFPB_TXD5

IFPB_TXD6
IFPB_TXD6

IFPB_TXD7
IFPB_TXD7

C12
.01UF

16V
10%
X7R
0402
COMMON

IFPC_TXC
IFPC_TXC

IFPC_TXD0
IFPC_TXD0

IFPC_TXD1
IFPC_TXD1

IFPC_TXD2
IFPC_TXD2

IFPD_TXC
IFPD_TXC

IFPD_TXD4
IFPD_TXD4

IFPD_TXD5
IFPD_TXD5

IFPD_TXD6
IFPD_TXD6

C748
.01UF

16V
10%
X7R
0402
COMMON

NET NAME

IFPATXC*

AJ9

IFPATXC

AK9

AJ6

IFPATXD0

AH6

AH7
AH8

IFPATXD2*

AK8
AJ8

IFPATXD3*

AH5

IFPATXD3

AJ5

IFPBTXC*

AL4

IFPBTXC

AK4

AM5

IFPBTXD4

AM6

AL7
AM7

IFPBTXD6*

AK5
AK6

IFPBTXD7*

AL8

IFPBTXD7

AK7

IFPC_IOVDD

C18

C14

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

NET NAME DIFFPAIR

IFPCTXC*

AM3
AM2

IFPCTXD0*

AE1

IFPCTXD0

AE2

IFPCTXD1*

AF2

IFPCTXD1

AF1

AH1

IFPCTXD2

AG1

IFPDTXC*

AH2
AG3

IFPDTXD3*

AJ1

IFPDTXD3

AK1

IFPDTXD4*

AL1

IFPDTXD4

AL2

AJ3

IFPDTXD5

AJ2

C753
.01UF

16V
10%
X7R
0402
COMMON

Place Pullups and Caps near GPU
1 CAP per DIFF_PAIR

DIFFPAIR

IFPATXC
IFPATXC 1 100DIFF

IFPATXD0 1 100DIFF
IFPATXD0

IFPATXD1 1 100DIFF
IFPATXD1 1 100DIFF

IFPATXD2 1 100DIFF

IFPATXD3 1 100DIFF
IFPATXD3 1 100DIFF

IFPBTXC
IFPBTXC 1 100DIFF

IFPBTXD4 1 100DIFF
IFPBTXD4

IFPBTXD5 1 100DIFF
IFPBTXD5 1 100DIFF

IFPBTXD6 1 100DIFF
IFPBTXD6 1 100DIFF

IFPBTXD7 1 100DIFF
IFPBTXD7 1 100DIFF

R49

49.9

COMMON

0402

1%

R47

49.9

COMMON

0402

1%

R45

49.9

04021%COMMON

R55

49.9

04021%COMMON

IFPCTXC 1 100DIFF
IFPCTXC 1 100DIFF

IFPCTXD0 1 100DIFF
IFPCTXD0 1 100DIFF

IFPCTXD1

IFPCTXD2 1 100DIFF
IFPCTXD2

IFPDTXC 1 100DIFF

IFPDTXD3 1 100DIFF

IFPDTXD4

IFPDTXD5 1 100DIFF
IFPDTXD5

R596

49.9

04021%COMMON

R595

49.9

0402

COMMON

1%

R54

49.9

0402

COMMON

1%

R52

49.9

0402

COMMON

1%

1 100DIFF

1 100DIFF

1 100DIFF

1 100DIFF

R50

49.9

COMMON

0402

1%

R48

49.9

COMMON

0402

1%

R46 49.9

COMMON

0402

1%

R56

49.9

COMMON0402

1%

NV_CRITICAL

1
1IFPCTXD1 100DIFF

1

1IFPDTXC 100DIFF

1IFPDTXD3 100DIFF

1
1IFPDTXD4 100DIFF

1

R593

49.9

0402

COMMON

1%

R594

49.9

0402

COMMON

1%

R53

49.9

0402

COMMON

1%

R51

49.9

0402

COMMON

1%

NV_IMPEDANCENV_CRITICAL

100DIFFIFPATXD2 1

Place Pullups and Caps near GPU
1 CAP per DIFF_PAIR

NV_IMPEDANCE

100DIFF

100DIFF

100DIFF

100DIFF

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

1

12

OUT

12

OUT

12IFPATXD0*

OUT

12

OUT

12IFPATXD1*

OUT

12IFPATXD1

OUT

12

OUT

12IFPATXD2

OUT

12

OUT

12

OUT

12

OUT

12

OUT

12IFPBTXD4*

OUT

12

OUT

12IFPBTXD5*

OUT

12IFPBTXD5

OUT

12

OUT

12IFPBTXD6

OUT

12

OUT

12

OUT

2

3

12

OUT

12IFPCTXC

OUT

12

OUT

12

OUT

12

OUT

12

OUT

12IFPCTXD2*

OUT

12

OUT

12

BI

12IFPDTXC

BI

12

OUT

12

OUT

12

OUT

12

OUT

12IFPDTXD5*

OUT

12

OUT

4

5

PAGEID
DATE

16-MAR-2007

HFDBA

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

MXM Connector IO-Section

1

CN1B

(N,NON)PHY(-X16,-HE)_SLI
CON_FINGER_MXMHE_212
COMMON

13 DVI_A_HPD

OUT

10

IN

10

BI

I2CB_SCL_R
I2CB_SDA_R

217
232

230

2/2 IO - LVDS,DVI,VGA,TV

DVI_A_HPD
DDCB_SCLK

DDCB_SDATA

DVI-A

2

13

IN

13

IN

13

IN

13,13,14 I2CC_SCL_R

IN

13,14

BI

DVI_B_HPD

DACB_GREEN

DACB_RED

DACA_HSYNC

DACA_RED

DACA_BLUE

GPIO3_PPEN
GPIO4_BLEN
GPIO2_BL_PWM

I2CC_SDA_R

193

DVI_B_HPD

SDTV HDTV

140
136
144

153
151

148
152
156
155

157 159

224
228
226

222
220

HDTV_YTV_Y
HDTV_PrTV_C
HDTV_PbTV_CVBS

VSYNC
HSYNC

VGA_RED
VGA_GRN
VGA_BLU
DDCA_SCLK

DDCA_SDATA DR_D11

LVDS_PPEN
LVDS_BLEN
LVDS_BL_BRGHT

DDCC_SCLK
DDCC_SDATA

SLI

DVI-B

DVI_B_TX2DVI_B_TX2
DVI_B_TX2DVI_B_TX2

DVI_B_TX1DVI_B_TX1
DVI_B_TX1DVI_B_TX1

DVI_B_TX0DVI_B_TX0

DVI_B_TX0 DVI_B_TX0
DVI_B_CLK DR_RASTER_SYNC

DVI_B_CLK DR_SWAP_RDY

DR_D0
DR_D1
DR_D2
DR_D3
DR_D4
DR_D5
DR_D6
DR_D7
DR_D8
DR_D9
DR_D10

DR_D12GND
DR_D13
DR_D14
DR_CMD
DR_REFCLK
DR_CLK

13

OUT

10

IN

10

IN

10 DACB_BLUE

IN

10 DACA_VSYNC

IN

10

IN

10

IN

10 DACA_GREEN

3

IN

10

IN

10 I2CA_SCL_R

IN

10 I2CA_SDA_R

BI

ESD Protection for exposed Gates

SMB_DAT

13

IN

13 SMB_CLK

BI

4

11,14,16,17 RUNPWROK

OUT

R549 1K

0402 COMMON

5%

12mil 12mil

C579
220PF

50V
5%
C0G
0402
COMMON

THERM_ALERT*

13

IN

RUNPWROK_C

13 AC_BATT*

OUT

2 SPDIF_C

OUT

145

SMB_DAT

147

SMB_CLK

149

THERM

16

RUNPWROK

169

AC/BATT*

170

SPDIF

DVI_A_CLK
DVI_A_CLK

DVI_A_TX0
DVI_A_TX0

DVI_A_TX1
DVI_A_TX1

DVI_A_TX2
DVI_A_TX2

LVDS_UTX0
LVDS_UTX0

LVDS_UTX1
LVDS_UTX1

LVDS_UTX2
LVDS_UTX2

LVDS_UTX3
LVDS_UTX3

LVDS_UCLK
LVDS_UCLK

LVDS_LTX0
LVDS_LTX0

LVDS_LTX1
LVDS_LTX1

LVDS_LTX2
LVDS_LTX2

LVDS_LTX3
LVDS_LTX3

LVDS_LCLK
LVDS_LCLK

219
221

237
239

231
233

225
227

201
203

207
209

213
215

189
191

SLI_D0

185

SLI_D1

183

SLI_D2

181

SLI_D3

179

SLI_D4

177

SLI_D5

175

SLI_D6

173

SLI_D7

167

SLI_D8

165

SLI_D9

163

SLI_D10

161

SLI_D11
SLI_D12

187

SLI_D13

195

SLI_D14

197
143
141

SLI_CLKOUT

171

186
184

180
178

174
172

168
166

162
160

216
214

210
208

204
202

198
196

192
190

IFPCTXC*

IFPCTXD0*
IFPCTXD0

IFPCTXD2*
IFPCTXD2

IFPDTXD5*
IFPDTXD5

IFPDTXD3*
IFPDTXD3

IFPDTXC

SLI_D[14..0]
0
1
2
3
4
5
6
7
8
9

10
11
12
13
14

IFPBTXD4*

IFPBTXD5

IFPBTXD6

IFPBTXD6*

IFPBTXC*

IFPATXD0

IFPATXD0*

IFPATXD1*

IFPATXD2

IFPATXD3

IFPATXD3*

15,18

BI

15SLI_DE

BI

15SLI_REFCLK

BI

15

BI

IFPBTXC

11

IN

11IFPCTXC

IN

11

IN

11

IN

11IFPCTXD1*

IN

11IFPCTXD1

IN

11

IN

11

IN

11

IN

11

IN

11IFPDTXD4*

IN

11IFPDTXD4

IN

11

IN

11

IN

11IFPDTXC*

BI

11

BI

Re

R63

1K

SLI_SYNC

COMMON0402

5%

R61 1K

Rf

SLI_SWAP_OUT

0402 COMMON

5%

Place these components so
that the signal loading on
the DVI CLKs is equal
between the diff pair.

R577
10K
5%
0402
COMMON

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

Stuffed? Re Rf

Yes Yes

R579
10K
5%
0402
COMMON

11IFPBTXD4
11

11
11IFPBTXD5*

11
11

11IFPBTXD7
11IFPBTXD7*

11
11

11
11

11IFPATXD1
11

11
11IFPATXD2*

11
11

11IFPATXC
11IFPATXC*

SLI:

No No

Non_SLI:

13

BI

14

BI

1

2

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

C GE

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

MXM Connector IO-Section

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

5

PAGEID
DATE

16-MAR-2007

HFDBA

A B C D E F G H

GPIO Thermal Alert

R19 0
0402 COMMON

1

R25
200
5%
0402

CLAMP

I2CS_SCL
I2CS_SDA

I2CC_SCL
I2CC_SDA

GPIO10

DRA_SYNC/GPIO11

GPIO12
GPIO13

DRB_SYNC/GPIO14

COMMON

THERM_VDD

12mil

R629 0

0402

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9

C10
.1UF
16V
10%
X7R
0402
COMMON

R37

COMMON

5%

0402

5%

SNN_CLAMP

F6

I2CS_SCL

C1

I2CS_SDA

B1

I2CC_SCL

G2

I2CC_SDA

G1

GPIO0_DVI_A_HPD

K3

GPIO1_DVI_B_HPD

H1
K5

GPIO3_PPEN_GPU

G5

GPIO4_BLEN_GPU

E2

GPIO5_NVVDDCTL0

J5
G6
K6

GPIO8_THERM_ALERT*

E1

GPIO9_LVDS_SYS*

D2

GPIO10_FBVREFCTL

H5
F4

GPIO12_AC_DET

E3

GPIO13_FBVDDQCTL

U3

SNN_GPIO14

U4

0

COMMON

R58

R621

10k

2.2K

5%

5%

0402

0402

COMMON

COMMON

1G1 D1S

G

1

S

D

5R

0.5A

25V

Q3A

5

6

0.22A

SOT 23_6

CO MMO N

0.7W@125C

R59

33

COMMON

R38

0402

33

5%

COMMON0402

5%

R22

0

0402

COMMON

5%

R17
10K
5%
0402
COMMON

I2C ADDRESS: 0x98H

NOSTUFF for internal sensor

U4
XSOP08_P065_030X030

COMMON

10MIL

3

10MIL

D-

X7R
COMMON

2200PF

0402 50V

THERM_SCL

8

SCL

THERM_SDA

7

V6

J1

K1

AJ11
AK11
AK12
AL12
AL13

SDA

G1J

BGA_0820_P100_330X330_G3_128B
COMMON

9/14 MISC1

THERMALSENSOR_OBS

THERMDN
THERMDP

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST

C16

10%

SNN_THERMAL

THERM*

THERM

JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST

12,13,14 I2CC_SCL_R

IN

12,13,14 I2CC_SDA_R

2

BI

3

R18

0

0402

COMMON

5%

R16

0

COMMON

0402

5%

R589

R590

R575
10K
5%
0402
COMMON

10K
5%
0402
COMMON

R570
10K
5%
0402
COMMON

R574
10K
5%
0402
COMMON

10K
5%
0402
COMMON

TP507
TP504
TP505
TP502
TP506

THERM

12

VDDD+

M_THERM_ALERT*

4

M_GPIO8_SLOWDOWN*

6

ALERT

5

GND

5%
R15 0
0402 COMMON

5%

NOSTUFF,
except to
connect
SMBus to
external
sensor.

SMB_CLK

12

IN

SMB_DAT

12

BI

NV_PWRGOOD

1G1D1S

G

3

1G1D1S

S

D

8V

5R

8V

0.5A

25V

Q3B

2

4

0.22A

SOT23_ 6

COMM ON

0.7W@125C

16,17

IN

3

D

Q510

SOT323

G

1

COMMON

S

2

60V
200mA
4R
800mA
200mW
+/-20V

R26

R619

10K

10K

5%

5%

0402

0402

COMMON

COMMON

R620
10K
5%
0402
COMMON

R57
47K
5%
0402
COMMON

GPIO3_PPEN
GPIO4_BLEN

R28
47K
5%
0402
COMMON

NOSTUFF for external
sensor in production

R31

0

0402

COMMON

5%

R36

0

04025%COMMON

install for
dev testing

THERM_ALERT*

R616

10K

0402

COMMON

3

R615
100K
5%
0402
COMMON

5%

D502

SOT23
70V
215MA
COMMON

1 2

12GPIO2_BL_PWM

OUT

12

OUT

12

OUT

16

OUT

16GPIO6_NVVDDCTL1

OUT

16GPIO7_NVVDDCTL2

OUT

11

OUT

3,4,7

OUT

12SLI_SYNC

BI

12AC_BATT*

IN

17

OUT

3

R599
100K
5%
0402
COMMON

OUT

R633

2.2K
5%
0402
COMMON

R597 10K

0402

1 2

D501

SOT23
70V
215MA
COMMON

12

R627

2.2K
5%
0402
COMMON

DVI_A_HPD

COMMON

5%

R35

47K
5%
0402
COMMON

R34

47K
5%
0402
COMMON

1

2

12,13,14I2CC_SCL_R

OUT

12,13,14I2CC_SDA_R

BI

12

IN

12DVI_B_HPD

IN

11

OUT

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

C GE

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

GPIO Thermal Sensor Chip

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

4

5

PAGEID
DATE

16-MAR-2007

HFDBA

A B C D E F G H

SPREAD SPECTRUM CLOCK

1

C796
.1UF
16V
10%
X7R
0402
COMMON

10SSFOUT

OUT

R6185%4.7

COMMON0402

C793
470PF
50V
10%
X7R
0402
COMMON

R27

22
COMMON

0402
R21
10K
5%

CLKOUT/

0402
COMMON

2

VDD

SS_OUT

4

FS_IN0

SS_REF

5

FS_IN1

3

GND

CLK_VDD

R20
10K
5%
0402
COMMON

U3

SO08_I190X150

RUNPWROK

11,12,16,17

IN

10 XTALOUTBUFF

IN

I2CC_SCL_R

12,13,13

IN

12,13 I2CC_SDA_R

BI

2

I2C ADDRESS: 0xD4H

COMMON

8

PD

1

CLKIN

7
6

REFOUT/

SCLK
SDATA

Place close to ICS91730

ALWAYS POPULATE

C786

4.7UF

6.3V
10%
X5R
0603
COMMON

5%

12mil 3.3V

C790

4.7UF

6.3V
10%
X5R
0603
COMMON

ROM Interface

14,18

ROMCS*

ROM_SI

ROM_SCLK

IN

U2
SO08_I190X150

SO8
COMMON

7 8

HOLD VCC

3

WP

1

CS

5

SI

2

SO

6

SCK

C9
.1UF
16V
10%
X7R
0402

4

GND

COMMON

3

C792
.1UF
16V
10%
X7R
0402
COMMON

R12
10K
5%
0402
COMMON

G1K

BGA_0820_P100_330X330_G3_128B
COMMON

AE26
AD26
AH31
AH32

AC26

AM8
AM9

B32

F1

V3
V4

U6
D1

10/14 MISC2

STRAP
MEMSTRAPSEL0

MEMSTRAPSEL1
MEMSTRAPSEL2
MEMSTRAPSEL3

RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU

SNN_STRAP

SNN_MSTRAPSEL0
SNN_MSTRAPSEL1
SNN_MSTRAPSEL2
SNN_MSTRAPSEL3

SNN_G3_RFU9
SNN_G3_RFU10
SNN_G3_RFU11
SNN_G3_RFU12
SNN_G3_RFU13
SNN_G3_RFU14
SNN_G3_RFU15

4

SNN_G3_RFU16

ROMCS
ROM_SI

ROM_SO

ROM_SCLK

I2CH_SCL

I2CH_SDA

BUFRST
STEREO

SWAPRDY_A

TESTMEMCLK

TESTMODE

AA4
W2

ROM_SO

AA6
AA7

I2CH_SCL

G3

I2CH_SDA

H3

SNN_BUFRST*

F3

SNN_STEREO

T3
M6

TESTMCLK

A26

TESTMODE

H2

R630
10K
5%
0402
COMMON

12SLI_SWAP_OUT

BI

R560
10K
5%
0402
COMMON

COMMON

R636

2.2K
5%

0402

SNN_HDCP_ROM

R626
10K
5%
0402
COMMON

6
5

3

U1
SO08_I190X150

COMMON

SCL
SDA

SDA

NC

8

VCC

7

VCC

4

GND

12

GND

G1L

BGA_0820_P100_330X330_G3_128B
COMMON

AA12

GND

AA2

GND

AA21

GND

AA31

GND

AB27

GND

AB6

GND

AC10

GND

AC23

GND

AC29

GND

AC4

GND

AD16

GND

AD17

GND

AD2

GND

AD31

GND

AE17

GND

AE27

GND

AE6

GND

AF11

GND

AF26

GND

AF29

GND

AF4

GND

AF7

GND

AG10

GND

AG11

GND

AG14

GND

AG15

GND

AG19

GND

AG2

GND

AG22

GND

AG31

GND

AG8

GND

AH24

GND

AJ10

GND

AJ13

GND

AJ16

GND

AJ17

GND

AJ20

GND

AJ23

GND

AJ26

GND

AJ29

GND

AJ4

GND

AJ7

GND

AK2

GND

AK28

GND

AK31

GND

AL11

GND

AL14

GND

AL19

GND

AL22

GND

AL25

GND

AL3

GND

AL6

GND

AL9

GND

AM13

GND

AM16

GND

AM17

GND

AM20

GND

AM23

GND

AM26

GND

AM29

GND

B12

GND

B15

GND

B18

GND

B21

GND

B24

GND

B27

GND

B3

GND

B30

GND

B6

GND

B9

GND

C2

GND

C31

GND

D10

GND

D13

GND

D16

GND

D17

GND

D20

GND

D23

GND

D26

GND

D29

GND

D4

GND

D7

GND

F11

GND

F14

GND

F19

GND

F2

GND

F22

GND

F25

GND

F31

GND

F8

GND

G26

GND

G29

GND

G4

GND

G7

GND

H27

GND

H6

GND

J16

GND

J17

GND

J2

GND

J31

GND

14/14 _GND_

K10

GND

K23

GND

K29

GND

K4

GND

L27

GND

L6

GND

M12

GND

M2

GND

M31

GND

N15

GND

N18

GND

N29

GND

N4

GND

P15

GND

P18

GND

P27

GND

P6

GND

R13

GND

R14

GND

R15

GND

R18

GND

R19

GND

R2

GND

R20

GND

R31

GND

T16

GND

T17

GND

T24

GND

T29

GND

T4

GND

U16

GND

U17

GND

U24

GND

U29

GND

U8

GND

V13

GND

V14

GND

V15

GND

V18

GND

V19

GND

V2

GND

V20

GND

V31

GND

W15

GND

W18

GND

W27

GND

W6

GND

Y15

GND

Y18

GND

Y29

GND

Y4

GND

AL10

GND

AM10

GND

AG13

GND

1

2

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

C GE

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

Spread Spectrum, BIOS/ HDCP ROM

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

5

PAGEID
DATE

16-MAR-2007

HFDBA

A B C D E F G H

MIOA

1

LB511

180R@100MHz

IND_SMD_0603COMMON

2

C791

4.7UF

6.3V
10%
X5R
0603
COMMON

R30
1K

1%
0402
COMMON

R614
1K

1%
0402
COMMON

C730
.1UF
16V
10%
X7R
0402
COMMON

R23

0402 COMMON

1%

R607

0402 COMMON

1%

MIOA_VDDQ

49.9

49.9

C15
.1UF
16V
10%
X7R
0402
COMMON

C729
.01UF

25V
10%
X7R
0402
COMMON

MIOACAL_PD_VDDQ

MIOACAL_PU_GND

MIOA_VREF

C779
.01UF

25V
10%
X7R
0402
COMMON

G1M

BGA_0820_P100_330X330_G3_128B
COMMON

11/14 DRA/MIOA

M7

MIOA_VDDQ

M8

MIOA_VDDQ

R8

MIOA_VDDQ

T8

MIOA_VDDQ

U9

MIOA_VDDQ

L1

MIOACAL_PD_VDDQ

L3

MIOACAL_PU_GND

L2

MIOA_VREF

DR MIO

DRA_D0 MIOAD0
DRA_D1 MIOAD1
DRA_D2 MIOAD2
DRA_D3 MIOAD3
DRA_D4 MIOAD4
DRA_D5 MIOAD5
DRA_D6 MIOAD6
DRA_D7 MIOAD7
DRA_D8 MIOAD8

DRA_D9 MIOAD9
DRA_D10 MIOAD10
DRA_D11 MIOAD11

DRA_D12 MIOA_CTL3
DRA_D13 MIOA_HSYNC
DRA_D14 MIOA_VSYNC

DRA_CMD MIOA_DE

DRA_CLK MIOA_CLKOUT

NC MIOA_CLKOUT

NV_CRITICAL

P2
N2
N1
N3
M1
M3
P5
N6
N5
M4
L4
L5

P3
R3
R1
P1

SLI_CLKOUT

R4

MIOACLKOUTR*

P4

SNN_RFU

M5

RFU

SLI_D0
SLI_D1
SLI_D2
SLI_D3
SLI_D4
SLI_D5
SLI_D6
SLI_D7
SLI_D8
SLI_D9
SLI_D10
SLI_D11

SLI_D12
SLI_D13
SLI_D14

TP508

0
1
2
3
4
5
6
7
8

9
10
11

12
13
14

NV_IMPEDANCE

50OHM1

NV_IMPEDANCENV_CRITICAL

50OHM1

50OHM1

12,18SLI_D[14..0]

BI

12SLI_DE

BI

12

BI

1

2

MIOB

3

G1N

BGA_0820_P100_330X330_G3_128B
COMMON

12/14 DRB/MIOB

AA8

MIOB_VDDQ

AB7
AB8
AC6
AC7

Y1
Y3

Y2

MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ

MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND

MIOB_VREF

C744
.1UF
16V
10%
X7R
0402
COMMON

SNN_MIOBCAL_PD_VDDQ

SNN_MIOBCAL_PU_GND

SNN_MIOB_VREF

4

DR

DRB_CMD

DR_REFCLK MIOB_CLKIN

MIO

DRB_D0 MIOBD0
DRB_D1 MIOBD1
DRB_D2 MIOBD2
DRB_D3 MIOBD3
DRB_D4 MIOBD4
DRB_D5 MIOBD5
DRB_D6 MIOBD6
DRB_D7 MIOBD7
DRB_D8 MIOBD8

DRB_D9 MIOBD9
DRB_D10 MIOBD10
DRB_D11 MIOBD11

DRB_D12 MIOB_CTL3
DRB_D13 MIOB_HSYNC
DRB_D14 MIOB_VSYNC

DRB_CLK MIOB_CLKOUT

MIOB_DE

NC MIOB_CLKOUT

MIOBD0

AC3

MIOBD1

AC1

SNN_MIOBD<2>

AC2

MIOBD3

AB2

MIOBD4

AB1

MIOBD5

AA1

SNN_MIOBD<6>

AB3

SNN_MIOBD<7>

AA3

MIOBD8

AC5

MIOBD9

AB5

SNN_MIOBD<10>

AB4

MIOBD11

AA5

SNN_G3_RFU1

W3

RFU

SNN_G3_RFU2

V1

RFU

SNN_G3_RFU3

Y5

RFU

SNN_G3_RFU4

W1

RFU

SNN_G3_RFU5

W4

RFU

SNN_G3_RFU6

W5

RFU

SNN_G3_RFU7

V5

RFU

SNN_G3_RFU8

Y6

RFU

MIOB_CTL3

AD3
AF3

SNN_MIOB_VSYNC

AE3

SNN_MIOB_DE

AD1

SNN_MIOB_CLKOUT

AD4

SNN_MIOB_CLKOUT*

AD5

SLI_REFCLK

AE4

0
1

3
4
5

8
9

11

18

IN

18MIOB_HSYNC

IN

NV_CRITICAL NV_IMPEDANCE

1 50OHM

18MIOBD[11..0]

IN

12

BI

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

C GE

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

MIOA, MIOB

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

5

PAGEID
DATE

16-MAR-2007

HFDBA

A B C D E F G H

Power Supply I - NVVDD

R540
10

5%

1

2

3

4

5

Single-Phase

Rvdiff

Cvdiff

Rfb

Cfb

Rcomp

Ccomp

Stuff for Dual-Phase

Stuff for Single-Phase

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

1.8K

150pF

365ohm

82pF

732K

100pF

Cvdiff

C515

0402

C514

Cfb

0402

13 GPIO5_NVVDDCTL0

IN

13 GPIO6_NVVDDCTL1

IN

13

IN

Dual-Phase

1.8K

300pF

365ohm

120pF

412K

330pF

220PF

COMMON50V
C0G

5%

120PF

COMMON

50V

C0G

5%

C522 120PF

0402 50V5%COMMON

R514
10K

5%
0402
COMMON

R517
0

5%
0402
COMMON

GPIO7_NVVDDCTL2

Rvdiff

R506

04025%COMMON

COMP_R

Ccomp

C0G

R529
10K

5%
0402
COMMON

R526
0

5%
0402
COMMON

1.8K

COMMON

COMMON

COMMON

R510

R505

R591

10K

5%

0402

R624

10K

5%

0402

R623

10K

5%

0402

13,17

OUT

Rfb

365

0402

COMMON

1%

Rcomp

453K

0402 COMMON

1%

Rfsw

R513

0402 COMMON

Cvw

C525

R534
10K

5%
0402
COMMON

R536
0

5%
0402
COMMON

R598

10K

5%

0402

DNI

1%

47PF

50V04025%COMMON

R541

COMMON

NV_PWRGOOD

4.42K

0

5%

0402

R525
680

5%
0402
COMMON

C530
.01UF

16V
10%
X7R
0402
COMMON

11,12,14,17

IN

C0G

R508 147K

COMMON

0402

1%

C523

15NF

0402

16V
10%
X7R
COMMON

R539
0

5%
0402
COMMON

R601
10K

5%
0402

1G1D1S

G

1

COMMON

3

D

Q504

SOT23
COMMON

S

2

50V

0.22A@31C

3.5R

0.88A

0.36W@25C
+/-20V

R538
0

5%
0402
COMMON

COMMON

C560

1UF

6.3V

0603

RUNPWROK

VDIFFVDIFF_R

FB

COMP

VW

RBIAS

SNN_NTC

SNN_VRHOT*

SOFT

ISL9502_SET1

ISL9502_SET2

ISL9502_SET3

VID0

VID4

VID5

10%
X7R

NVVDD_VDD

Termination resistors
are to be loaded if
necessary during the
GPU initialization.

R516
10

5%
0603
COMMON

U501

DYNAMIC VID(0.5V..1.50V)
QFN048Q_P050_0078_TI210X210_B
QFN48
COMMON

3

VDD

22

VDD

1

PGOOD

44

VR_ON

13

VDIFF

11

FB

10

COMP

9

VW

4

RBIAS

6

NTC

5

VRHOT*

7

SOFT

45

SET1

46

SET2

2

SET3

38

VID0

39

VID1

40

VID2

41

VID3

42

VID4

43

VID5

21

GND

37

GND

48

GND

49

2 Phase PWM

THERM_GND

31

PVCC

20

VIN

35MIL
UG1

35

UGATE1

25MIL
BT1

36

BOOT1

25MIL
PH1

34

PHASE1

35MIL
LG1

32

LGATE1

12MIL
ISEN1

24

ISEN1

33

PGND1

***PGND1 should be connected with a

35MIL
UG2

27

UGATE2

25MIL
BT2

26

BOOT2

25MIL
PH2

28

PHASE2

35MIL
LG2

30

LGATE2

12MIL
ISEN2

23

ISEN2

29

PGND2

***PGND2 should be connected with a

SNN_FB2

12

FB2

VSUM

19

VSUM

OCSET

8

OCSET

VO

18

VO

DROOP

16

DROOP

DFB

17

DFB

VSEN

14

VSEN

15

RTN

NC

NC

25

47

VOLTAGE IDENTIFICATION CODES
(normal voltages w/ zero offset)

VID<5..0> NVVDD

0 0 0 0 0 0 1.550 <­0 0 0 0 0 1 1.475 <­0 0 0 0 1 0 1.450 <­0 0 0 0 1 1 1.425 <-

SNN _IS L950 2_NC 1

0 0 0 1 0 0 1.400 <-

SNN _IS L950 2_NC 2

0 0 0 1 0 1 1.375 <­0 0 0 1 1 0 1.350 <­0 0 0 1 1 1 1.325 <­0 0 1 0 0 0 1.300 <­0 0 1 0 0 1 1.275 <­0 0 1 0 1 0 1.250 <­0 0 1 0 1 1 1.225 <­0 0 1 1 0 0 1.200 <­0 0 1 1 0 1 1.175 <­0 0 1 1 1 0 1.150 <­0 0 1 1 1 1 1.125 <­0 1 0 0 0 0 1.100 <­0 1 0 0 0 1 1.075 <­0 1 0 0 1 0 1.050 <­0 1 0 0 1 1 1.025 <­0 1 0 1 0 0 1.000 <­0 1 0 1 0 1 0.975 <­0 1 0 1 1 0 0.950 <­0 1 0 1 1 1 0.925 <­0 1 1 0 0 0 0.900 <­0 1 1 0 0 1 0.875 <­0 1 1 0 1 0 0.850 <­0 1 1 0 1 1 0.825 <­0 1 1 1 0 0 0.800 <­0 1 1 1 0 1 0.775 <­0 1 1 1 1 0 0.750 <­0 1 1 1 1 1 0.725 <-

C GE

NVVDD_VIN

C568

1UF

0603

6.3V
10%
X7R

COMMON

R518

20mil trace to GND of Q5 and Q7

R524

20mil trace to GND of Q4 and Q6

R532

0402

R530

0402

0603
COMMON

C561
.1UF

25V
10%
X7R
0603
COMMON

0

04025%COMMON

0

0402 COMMON

5%

27K

COMMON

5%

200

COMMON

5%

X7R

C545
.1UF

16V
10%
X5R
0402
COMMON

C537 1000PF

0402

16V
10%
X7R
COMMON

R531

04021KCOMMON

5%

ASSEMBLY
PAGE DETAIL

C47
470UF

COMMON
20%

2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM

COMMON

0.68UH

C541

0.22UF

25V
10%
X7R
0603
COMMON

C580

0.22UF

25V
10%
X7R
0603
COMMON

CAP_SMD_7343

C46
470UF

COMMON
20%

2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM
CAP_SMD_7343

C52
.1UF

50V
10%
X7R
0805
COMMON

R552
0

5%
0402
COMMON

R543
1

5%
0402
COMMON

C100

C107

C106

C105

4.7UF

4.7UF

25V
10%
X5R
1206
COMMON

1000PF

COMMON

1000PF

COMMON

4.7UF

25V
10%
X5R
1206
COMMON

LFPAK

C536

16V
10%
X7R
0402

35MIL
UG2_R

LFPAK

C535

16V
10%
X7R
0402

25V
10%
X5R
1206
COMMON

C88

0.22UF

25V

0603

COMMON

10%

***Stuff for Single-Phase

R544

0

COMMON

0402

5%

C564

0.22UF

0603

25V

COMMON

X7R

10%

R641

1.69K

1%

0402

COMMON

C542
.01UF

16V
10%
X7R
0402
COMMON

4.7UF

25V
10%
X5R
1206
COMMON

C518
2200PF

50V
10%
X7R
0603
COMMON

G

4

G

4

UG1_R

5

D

Q13

MULTI_SMD_SOT669_LFPAK_B
COMMON

S

30V

1

50A

3.2mR

2

200A

2.8W

3

+/-20V

5

D

Q12

MULTI_SMD_SOT669_LFPAK_B
COMMON

30V

S

1

50A

3.2mR

2

200A

2.8W

3

+/-20V

C104

4.7UF

25V
10%
X5R
1206
COMMON

C99
.1UF

25V
10%
X7R
0603
COMMON

5

LFPAK

D

35MIL

Q14

MULTI_SMD_SOT669_LFPAK_B

G

4

COMMON

S

30V

1

50A

5.5mR

2

200A

2.8W

3

+/-20V

5

LFPAK

D

Q11

MULTI_SMD_SOT669_LFPAK_B

G

4

COMMON

S

30V

1

50A

3.2mR

2

200A

2.8W

3

+/-20V

5

LFPAK

D

Q15

MULTI_SMD_SOT669_LFPAK_B

G

4

COMMON

30V

S

1

50A

5.5mR

2

200A

2.8W

3

+/-20V

5

LFPAK

D

Q10

MULTI_SMD_SOT669_LFPAK_B

G

4

COMMON

30V

S

1

50A

3.2mR

2

200A

2.8W

3

+/-20V

C519
2200PF

50V
10%
X7R
0603
COMMON

Place these components
close together

D2

12

DIODE_SMD_SMA

40V

2.1A
COMMON

C501
.1UF

50V
10%
X7R
0603
COMMON

Place these components
close together

D3

12

DIODE_SMD_SMA

40V

2.1A
COMMON

Cap should
be 2200pF

C74
1000PF

50V
10%
X7R
0402
COMMON

SNUB 1SNUB 2

25M IL25M IL

R546

2.21

1%
1206
COMMON

COMMON

C121

C103

4.7UF

4.7UF

25V

25V

10%

10%

X5R

X5R

1206

1206

COMMON

COMMON

C528
1000PF

50V
10%
X7R
0402
COMMON

R512

2.21

1%
1206

COMMON

COMMON

L4 0.68UH

COMMONIND_NONRKO_SMD_076X076

L3 0.68uH

35A

COMMONIND_NONRKO_SMD_115X100

R551
10K

5%
0402
COMMON

C577

0.22UF

0603

25V
10%

COMMON

R528
10K

5%
0402
COMMON

COMMON

X7R

L5

IND_NONRKO_SMD_076X076

C540

0.22UF

0603

25V
10%
X7R

R550

3.65K

1%

0402

17A

R523

3.65K

1%

0402

COMMON

C55
470UF

COMMON
20%

2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM

COMMON

35A

R553

10K

0402

CAP_SMD_7343

C49
470UF

COMMON
20%

2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM
CAP_SMD_7343

C56
.1UF

50V
10%
X7R
0805
COMMON

5%

1

2

3

R542

10K

5%

0402

4

R515

COMMON

68

10MIL

C531

1UF

10V
10%
X5R
0603

R520
2K

5%
0402
COMMON

04025%COMMON

10MIL

NVVDD_SENSE

2

IN

2 GND_SENSE

IN

Note: Route to Rnv_vsen with single trace from Output Cap Via

R511

100

0402

COMMON

5%

100 ohm resistors
are loaded in case
GPU is not installed

R521

100

Note: Route to RGND pin with single trace from Output Cap Via

04025%COMMON

Via at RGND pin must be isolated from GND

5

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY

NVVDD Supply

SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

PAGEID
DATE

16-MAR-2007

HFDBA

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

Power Supply II - FBVDDQ, PEX_VDD, and LVDS_IOVDD

5VRUN
3V3RUN
1V8RUN
PEX1V2

FBVDDQ

1

NVVDD
PWR_SRC
2V5RUN
GND

MIN_LINE_WIDTHNETatt

16MIL 0.5A 5V
16MIL 3.3V1.5A

16MIL 2.0V
16MIL 4A 22V

VOLTAGE

3.5A 1.8V16MIL
1A 1.2V16MIL

10A

1.25V25MIL

2.5V0.5A16MIL

25A 0V16MIL

PEX_VDD

C563

4.7UF

11,12,14,16 RUNPWROK

COMMON

IN

6.3V

0603

SNN_POK

10%
X5R

U5

SO08_I190X150_TI118X102
COMMON

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

VOUT
VOUT

GND

1

PEXVDD = 1.2V @ 1.8A

3
4

PEX_VDD_FB

2

FB

R533
2K

R2

1%
0402
COMMON

R537

R1

1K

COMMON0402

1%

C546 1000PF

50V0402
10%
X7R
COMMON

C65
1UF

16V
10%
X7R
0805
COMMON

C73
1UF

16V
10%
X7R
0805
COMMON

1

PEX1V2 min = 1.184V
PEX1V2 max = 1.216V

Vout = Vref * (1+R1/R2)

1.2V = 0.8V * (1+1K/2K)

FBVDDQ

2

Stuff for ISL6269A

R628

0

COMMON

0402

5%

C759

4.7UF

6.3V
10%
X5R
0603
COMMON

11 FB_VCC

OUT

11

OUT

13,16 NV_PWRGOOD

3

IN

FB_PWRGOOD

R603
28K
1%
0402
COMMON

Switching Fre =

600KHz

C781
1UF

6.3V

R613

10%

0402

5%

X7R
0603
COMMON

R612

04020COMMON

5%
FCCM = 0 -- ENABLE DIODE EMULATION
FCCM = 1 -- DISABLE DIODE EMULATION

C766
.01UF
16V
10%
X7R
0402
COMMON

0

COMMON

FBVDDQ_FSET

FBVDDQ_COMP

4

FBVDDQ_FCCM

R635

0402 COMMON

5%

75K

U502

VR_SW=0.6V
QFN016Q_P065_I0185_TI088X088
MLFP16
COMMON

12

PVCC

2

VCC

FCCM

PGOOD

EN

FSET

GND(PAD)
COMP FB

FBVDDQ_COMP_RC

C784

47PF

50V

0603

5%
C0G
COMMON

BOOT

PHASE

PGND

3

16

4

7

TP

5 6

1

VIN

16MIL 16MIL
FBVDDQ_UG FBVDDQ_UG_R

14

UG

16MIL
FBVDDQ_BOOT

13

16MIL 10A
FBVDDQ_PHASE

15

10MIL
FBVDDQ_ISEN

9

ISEN

16MIL
FBVDDQ_LG

11

LG

R600 0
04025%COMMON

C760

.1UF

0603 25V

10%
X7R
COMMON

R602

2.4K

0402

COMMON

5%

10

FBVDDQ

8

VO

10MIL
FBVDDQ_FB

C783

.01UF

0402 6.3V

10%
X7R
COMMON

5

D

Q7

LFPAK

MULTI_SMD_SOT669_LFPAK_B

G

4

COMMON

S

30V

1

50A

5.5mR

2

200A

2.8W

3

+/-20V

5

D

Q5

LFPAK

MULTI_SMD_SOT669_LFPAK_B

G

4

COMMON

30V

S

1

50A

C756

3.2mR

2

200A

1000PF

2.8W

3

+/-20V

16V
10%
X7R
0402
COMMON

GPIO13_FBVDDQCTL

13

IN

R610
10K
5%
0402
COMMON

C782
2200PF
50V
10%
X7R
0603
COMMON

C774
.1UF

25V
10%
X7R
0603
COMMON

12

R606 10K

5%

D1

DIODE_SMD_SMA
40V

2.1A
COMMON

COMMON0402

C42

4.7UF
25V
10%
X5R
1206
COMMON

FBVDDCTL

COMMON

5.62K

FBVDDQ

R639

1%

0402

FBVDDQ = 0.6*[1+(Rtop/Rbot)]

RTop

1.8

3.01K

1.5V

9.09k|3.01K

1.9

2.49K

1.5V

2.49k|5.62K

Rtop

R611

2.49K

1%
0402
COMMON

Rbot

R617

1.15K

1%
0402
COMMON

C3
330UF

COMMON
20%

2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM
CAP_SMD_7343

RBot

1.5K

1.5K

1.15K Low

1.15K

C8
330UF

COMMON
20%

2.5V
POSCAP
3900MA@100KHZ,45C
9MOHM
CAP_SMD_7343

GPIO13

Low
High

High

C2
.1UF
50V
10%
X7R
0805
COMMON

C41

C40

4.7UF

4.7UF

25V

25V

10%

10%

X5R

X5R

1206

1206

COMMON

COMMON

L1

2.2uH

IND_NONRKO_SMD_076X076COMMON

6.5A

L2

2.2uH

COMMON

IND_NONRKO_SMD_076X076

C776
.01UF
16V
10%
X7R
0402
COMMON

6.5A

Rtop1

FBCTL_R

3

1G1D1S

D

Q505
SOT23

G

1

COMMON

S

2

60V

0.115A

7.5R

0.8A

0.2W
20V

C11
470PF

50V
10%
X7R
0402
COMMON

FBV DD Q_SN UB

R13

3.3

5%
1206
COMMON

2

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

C GE

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

FBVDDQ, PEX1V2, PLLVDD Supply

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

5

PAGEID
DATE

16-MAR-2007

HFDBA

A B C D E F G H

SLI_D1

MIOBD0

MIOBD1

MIOBD8

MIOBD9

MIOBD4

MIOBD5

MIOBD3

MIOBD11

MIOB_CTL3

SLI_D0

ROM_SI

SLI_D13

SLI_D6

SLI_D8

SLI_D9

MIOB_HSYNC

LOGIC 1

0402 COMMON

R11

0402

5%

04025%COMMON

R3

0402

5%

R29

04025%COMMON

R42

5%

R24

0402 COMMON

5%

R637
04025%COMMON

R41

5%

LOGIC 1

5%

R71

5%

R73

0402

5%

R68

0402 COMMON

5%

R33

0402 COMMON

5%

10K5%R1

10K
COMMON

10KR14

10K
COMMON

2.2K

2.2K
COMMON0402

2.2K

2.2K

2.2K
COMMON0402

2.2KR44
COMMON0402

2.2K
COMMON0402

2.2K
COMMON

2.2K

2.2K

1

15

15 MIOB_CTL3

12,15

14 ROM_SI

15

2

MIOBD[11..0]

OUT

OUT

SLI_D[14..0]

OUT

OUT

MIOB_HSYNC

OUT

STRAP BIT

2

3 RAM_CFG_1

4

5

10

11

LOGIC 0

R64

0402

R5

R8

0402 COMMON

04025%COMMON

R7

0402

2.2K
COMMON

5%

10K
COMMON0402

5%

10K

5%

10KR9

10K
COMMON

5%

12

13

FM13

FM12

SW_FB

SW_FB

1

1

NS

NS

FM16

SW_FB

SW_FB

1

1

NS

NS

FM20

SW_FB

3

4

SW_FB

1

1

NS

NS

FM14

SW_FB

1

NS

FM18

FM17

SW_FB

1

NS

FM21

SW_FB

1

NS

FM15

SW_FB

1

NS

FM19

SW_FB

1

NS

SW_FB

FM22

FM23

1

NS

28

17

R592
0402 COMMON

STRAP BIT LOGIC 0

12

15

Stuffed? Rd

Non_SLI:

0402 COMMON

SLI:

Yes

No

2.2K

5%

Rd

2.2KR40

5%

REG: NV_STRAP_0

SUB_VENDOR

RAM_CFG_0

RAM_CFG_2

RAM_CFG_3

PCI_DEVID_0

PCI_DEVID_1

PCI_DEVID_2

PCI_DEVID_3

PCI_DEVID_EXT (4)

PEX_PLL_EN_TERM100

REG: NV_STRAP_1

MIOA_EN_3.3V

Slot Clock Configuration

3GIO_PADCFG_LUT_ADR[0]

3GIO_PADCFG_LUT_ADR[1]

3GIO_PADCFG_LUT_ADR[2]

3GIO_PADCFG_LUT_ADR[3]

1 = Read from BIOS

RAM_CFG[3:0]
MS_1001: 16Mx32 GDDR3 SDRAM 128 Bit, Qimoda Dual Rank
MS_1010: 16Mx32 GDDR3 SDRAM 128 Bit, Hynix Dual Rank
MS_1011: 16Mx32 GDDR3 SDRAM 128 Bit, Samsung Dual Rank
MS_0011: 16Mx32 GDDR3 SDRAM 128 Bit, Samsung Single Rank
MS_0010: 16Mx32 GDDR3 SDRAM 128 Bit, Hynix Single Rank

MS_00111: (G84M-600)
MS_01000: (G84M-700)
MS_01001: (G84M-750)
MS_01010: (G84M-610)
MS_01100: (G84GLM-950)
MS_01101: (G84GLM-975)

MEC1-1

MECH_MXM3_HOLES
COMMON

1

MEC1-2

MECH_MXM3_HOLES
COMMON

2

MEC501-1

HSB_MXM3_HP_G_B
COMMON

1

MEC501-2

HSB_MXM3_HP_G_B
COMMON

2

MEC501-3

HSB_MXM3_HP_G_B
COMMON

3

MEC501-4

HSB_MXM3_HP_G_B
COMMON

4

1

2

3

4

5

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

C GE

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

ASSEMBLY
PAGE DETAIL

5

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY

Straps

SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

PAGEID
DATE

16-MAR-2007

HFDBA

A B C D E F G H

Title: Basenet Report
Design: p409
Date: Feb 9 16:02:25 2007

Base nets and synonyms for
p409_lib.P409(@p409_lib.p409(sch_1))
Base Signal Location([Zone][dir])

1

1V8RUN 17.1A
2V5RUN 17.1A
2V5RUN_R 2.2A
3V3RUN 17.1A
5VRUN 17.1A
AC_BATT* 12.4C> 13.3G<
BT1 16.2C
BT2 16.2C
BXTALOUT 10.4D
CLK_VDD 14.2C
COMP 16.2B
COMP_R 16.2A
DACA_BLUE 10.2H> 12.3B<
DACA_GREEN 10.2H> 12.3B<
DACA_HSYNC 10.1H> 12.3B<
DACA_RED 10.2H> 12.3B<
DACA_RSET 10.1C
DACA_VDD 10.1C
DACA_VREF 10.1C
DACA_VSYNC 10.1H> 12.3B<
DACB_BLUE 10.3H> 12.3B<

2

DACB_GREEN 10.3H> 12.2B<
DACB_RED 10.3H> 12.3B<
DACB_RSET 10.2C
DACB_VDD 10.2C
DACB_VREF 10.2B
DACC_HSYNC 10.3D
DACC_VDD 10.3C
DACC_VSYNC 10.3D
DFB 16.4C
DROOP 16.3C
DVI_A_HPD 12.2B> 13.3H<
DVI_B_HPD 12.2B> 13.3H<
FB 16.2B
FBAD<0> 3.1C 4.4B 5.4B
FBAD<63..0> 3.1B<> 4.4A<> 5.4A<>

9.2B<>
FBAD<1> 3.1C 4.4B 5.4B
FBAD<2> 3.1C 4.4B 5.4B
FBAD<3> 3.1C 4.4B 5.4B
FBAD<4> 3.1C 4.4B 5.4B
FBAD<5> 3.1C 4.4B 5.4B
FBAD<6> 3.1C 4.4B 5.4B

3

FBAD<7> 3.1C 4.4B 5.4B
FBAD<8> 3.1C 4.4C 5.4C
FBAD<9> 3.1C 4.4C 5.4C
FBAD<10> 3.1C 4.4C 5.4C
FBAD<11> 3.1C 4.4C 5.4C
FBAD<12> 3.1C 4.4C 5.4C
FBAD<13> 3.1C 4.4C 5.4C
FBAD<14> 3.1C 4.4C 5.4C
FBAD<15> 3.1C 4.4C 5.4C
FBAD<16> 3.1C 4.4D 5.4D
FBAD<17> 3.1C 4.4D 5.4D
FBAD<18> 3.1C 4.4D 5.4D
FBAD<19> 3.1C 4.4D 5.4D
FBAD<20> 3.2C 4.4D 5.4D
FBAD<21> 3.2C 4.4D 5.4D
FBAD<22> 3.2C 4.4D 5.4D
FBAD<23> 3.2C 4.4D 5.4D
FBAD<24> 3.2C 4.4E 5.4E
FBAD<25> 3.2C 4.4E 5.4E
FBAD<26> 3.2C 4.4E 5.4E
FBAD<27> 3.2C 4.4E 5.4E
FBAD<28> 3.2C 4.4E 5.4E

4

FBAD<29> 3.2C 4.4E 5.4E
FBAD<30> 3.2C 4.4E 5.4E
FBAD<31> 3.2C 4.4E 5.4E
FBAD<32> 3.2C 4.5B 5.5B
FBAD<33> 3.2C 4.5B 5.5B
FBAD<34> 3.2C 4.5B 5.5B
FBAD<35> 3.2C 4.5B 5.5B
FBAD<36> 3.2C 4.5B 5.5B
FBAD<37> 3.2C 4.5B 5.5B
FBAD<38> 3.2C 4.5B 5.5B
FBAD<39> 3.2C 4.5B 5.5B
FBAD<40> 3.2C 4.5C 5.5C
FBAD<41> 3.2C 4.5C 5.5C
FBAD<42> 3.2C 4.5C 5.5C
FBAD<43> 3.2C 4.5C 5.5C
FBAD<44> 3.2C 4.5C 5.5C
FBAD<45> 3.2C 4.5C 5.5C
FBAD<46> 3.2C 4.5C 5.5C
FBAD<47> 3.2C 4.5C 5.5C
FBAD<48> 3.2C 4.5D 5.5D
FBAD<49> 3.2C 4.5D 5.5D
FBAD<50> 3.3C 4.5D 5.5D

5

FBAD<51> 3.3C 4.5D 5.5D

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

FBAD<52> 3.3C 4.5D 5.5D
FBAD<53> 3.3C 4.5D 5.5D
FBAD<54> 3.3C 4.5D 5.5D
FBAD<55> 3.3C 4.5D 5.5D
FBAD<56> 3.3C 4.5E 5.5E
FBAD<57> 3.3C 4.5E 5.5E
FBAD<58> 3.3C 4.5E 5.5E
FBAD<59> 3.3C 4.5E 5.5E
FBAD<60> 3.3C 4.5E 5.5E
FBAD<61> 3.3C 4.5E 5.5E
FBAD<62> 3.3C 4.5E 5.5E
FBAD<63> 3.3C 4.5E 5.5E
FBADQM<0> 3.3C 4.4B 4.4B 5.4B

5.4B
FBADQM<7..0> 3.3B<> 4.4A<> 5.4A<>

9.2B>
FBADQM<1> 3.3C 4.4B 4.4C 5.4B

5.4C
FBADQM<2> 3.3C 4.4B 4.4D 5.4B

5.4D
FBADQM<3> 3.3C 4.4B 4.4E 5.4B

5.4E
FBADQM<4> 3.3C 4.4B 4.5B 5.4B

5.5B
FBADQM<5> 3.3C 4.4B 4.5C 5.4B

5.5C
FBADQM<6> 3.3C 4.4B 4.5D 5.4B

5.5D
FBADQM<7> 3.3C 4.4B 4.5E 5.4B

5.5E
FBADQS_RN<0> 3.4C 4.4B 4.4B 5.4B

5.4B
FBADQS_RN<7..0> 3.4B< 4.4A<> 5.4A<>

9.2B<
FBADQS_RN<1> 3.4C 4.4B 4.4C 5.4B

5.4C
FBADQS_RN<2> 3.4C 4.4B 4.4D 5.4B

5.4D
FBADQS_RN<3> 3.4C 4.4B 4.4E 5.4B

5.4E
FBADQS_RN<4> 3.4C 4.4B 4.5B 5.4B

5.5B
FBADQS_RN<5> 3.4C 4.4B 4.5C 5.4B

5.5C
FBADQS_RN<6> 3.4C 4.4B 4.5D 5.4B

5.5D
FBADQS_RN<7> 3.4C 4.5B 4.5E 5.5B

5.5E
FBADQS_WP<0> 3.3C 4.4B 4.5B 5.4B

5.5B
FBADQS_WP<7..0> 3.3B<> 4.5A<> 5.5A<>

9.2B>
FBADQS_WP<1> 3.3C 4.4C 4.5B 5.4C

5.5B
FBADQS_WP<2> 3.3C 4.4D 4.5B 5.4D

5.5B
FBADQS_WP<3> 3.3C 4.4E 4.5B 5.4E

5.5B
FBADQS_WP<4> 3.4C 4.5B 4.5B 5.5B

5.5B
FBADQS_WP<5> 3.4C 4.5B 4.5C 5.5B

5.5C
FBADQS_WP<6> 3.4C 4.5B 4.5D 5.5B

5.5D
FBADQS_WP<7> 3.4C 4.5B 4.5E 5.5B

5.5E
FBA_CLK0 3.4E> 4.2A< 5.2A<

9.1B<
FBA_CLK0* 3.4E> 4.2A< 5.2A<

9.1B<
FBA_CLK0_TERM 4.1A
FBA_CLK1 3.4E> 4.2D< 5.2D<

9.1B<
FBA_CLK1* 3.4E> 4.2D< 5.2D<

9.2B<
FBA_CLK1_TERM 4.1D
FBA_CMD<0> 3.3E 4.1B 5.1B 9.2B
FBA_CMD<27..0> 3.3F> 4.1A< 5.1A<

9.2A< 9.2B<
FBA_CMD<1> 3.3E 4.1B 4.2E 5.1E

5.2B
FBA_CMD<2> 3.3E 4.1B 5.1B 9.3B
FBA_CMD<3> 3.3E 4.1E 4.2B 5.1B

5.2E
FBA_CMD<4> 3.3E 4.1E 5.1E 9.3B
FBA_CMD<5> 3.3E 4.1E 5.1E 9.3B
FBA_CMD<6> 3.3E 4.1E 5.1E 9.3B
FBA_CMD<7> 3.3E 4.2B 4.2E 5.1B

5.1E
FBA_CMD<8> 3.3E 4.1B 4.1E
FBA_CMD<9> 3.3E 4.1B 4.1E 5.1B

5.1E
FBA_CMD<10> 3.3E 4.1B 4.1E 5.1B

5.1E
FBA_CMD<11> 3.3E 4.1B 4.2E 5.1E

5.2B

FBA_CMD<12> 3.3E 4.1B 4.2E 5.1E

5.2B
FBA_CMD<13> 3.3E 4.1E 5.1E 9.3B
FBA_CMD<15> 3.3E 4.2B 4.2E 5.2B

5.2E
FBA_CMD<16> 3.3E 4.1B 4.1E 5.1B

5.1E
FBA_CMD<17> 3.3E 4.1B 4.1E 5.1B

5.1E
FBA_CMD<18> 3.3E 4.1E 4.2B 5.1B

5.2E
FBA_CMD<19> 3.3E 4.1B 4.1E 5.1B

5.1E
FBA_CMD<20> 3.3E 4.1B 4.1E 5.1B

5.1E
FBA_CMD<21> 3.3E 4.1B 4.1E 5.1B

5.1E
FBA_CMD<22> 3.3E 4.1B 5.1B 9.2B
FBA_CMD<23> 3.3E 4.1B 4.1E 5.1B

5.1E
FBA_CMD<24> 3.3E 4.1B 5.1B 9.2B
FBA_CMD<25> 3.3E 4.1B 4.1E 5.1B

5.1E
FBA_CMD<27> 3.3E 4.1E 4.2B 5.1B

5.2E
FBA_DEBUG 3.4E
FBA_PLLAVDD 3.4E
FBA_VREF0 4.1G 4.3D> 5.3D>

9.4B<>
FBA_VREF1 4.1G 4.3G> 5.3G>

9.4B<>
FBA_VREF2 4.1G 4.3E> 5.3D>

9.4B<>
FBA_VREF3 4.1G 4.3H> 5.3G>

9.4B<>
FBA_VREFCTL1 4.1G
FBA_VREFCTL2 4.1G
FBA_ZQ0 4.2B> 9.4B<>
FBA_ZQ1 4.2E> 9.4B<>
FBA_ZQ2 5.2B> 9.4B<>
FBA_ZQ3 5.2E> 9.4B<>
FBCAL_PD_VDDQ 6.4E
FBCAL_PU_GND 6.4E
FBCAL_TERM_GND 6.4E
FBCD<0> 6.1C 7.4B 8.4B
FBCD<63..0> 6.1C<> 7.3A<> 8.3A<>

9.2E<>
FBCD<1> 6.1C 7.4B 8.4B
FBCD<2> 6.1C 7.4B 8.4B
FBCD<3> 6.1C 7.4B 8.4B
FBCD<4> 6.1C 7.4B 8.4B
FBCD<5> 6.1C 7.4B 8.4B
FBCD<6> 6.1C 7.4B 8.4B
FBCD<7> 6.1C 7.4B 8.4B
FBCD<8> 6.1C 7.4C 8.4C
FBCD<9> 6.1C 7.4C 8.4C
FBCD<10> 6.1C 7.4C 8.4C
FBCD<11> 6.1C 7.4C 8.4C
FBCD<12> 6.1C 7.4C 8.4C
FBCD<13> 6.1C 7.4C 8.4C
FBCD<14> 6.1C 7.4C 8.4C
FBCD<15> 6.1C 7.4C 8.4C
FBCD<16> 6.1C 7.4D 8.4D
FBCD<17> 6.1C 7.4D 8.4D
FBCD<18> 6.1C 7.4D 8.4D
FBCD<19> 6.1C 7.4D 8.4D
FBCD<20> 6.1C 7.4D 8.4D
FBCD<21> 6.1C 7.4D 8.4D
FBCD<22> 6.2C 7.4D 8.4D
FBCD<23> 6.2C 7.4D 8.4D
FBCD<24> 6.2C 7.4E 8.4E
FBCD<25> 6.2C 7.4E 8.4E
FBCD<26> 6.2C 7.4E 8.4E
FBCD<27> 6.2C 7.4E 8.4E
FBCD<28> 6.2C 7.4E 8.4E
FBCD<29> 6.2C 7.4E 8.4E
FBCD<30> 6.2C 7.4E 8.4E
FBCD<31> 6.2C 7.4E 8.4E
FBCD<32> 6.2C 7.5B 8.5B
FBCD<33> 6.2C 7.5B 8.5B
FBCD<34> 6.2C 7.5B 8.5B
FBCD<35> 6.2C 7.5B 8.5B
FBCD<36> 6.2C 7.5B 8.5B
FBCD<37> 6.2C 7.5B 8.5B
FBCD<38> 6.2C 7.5B 8.5B
FBCD<39> 6.2C 7.5B 8.5B
FBCD<40> 6.2C 7.5C 8.5C
FBCD<41> 6.2C 7.5C 8.5C
FBCD<42> 6.2C 7.5C 8.5C
FBCD<43> 6.2C 7.5C 8.5C
FBCD<44> 6.2C 7.5C 8.5C
FBCD<45> 6.2C 7.5C 8.5C
FBCD<46> 6.2C 7.5C 8.5C
FBCD<47> 6.2C 7.5C 8.5C
FBCD<48> 6.2C 7.5D 8.5D
FBCD<49> 6.2C 7.5D 8.5D

C GE

FBCD<50> 6.2C 7.5D 8.5D
FBCD<51> 6.2C 7.5D 8.5D
FBCD<52> 6.3C 7.5D 8.5D
FBCD<53> 6.3C 7.5D 8.5D
FBCD<54> 6.3C 7.5D 8.5D
FBCD<55> 6.3C 7.5D 8.5D
FBCD<56> 6.3C 7.5E 8.5E
FBCD<57> 6.3C 7.5E 8.5E
FBCD<58> 6.3C 7.5E 8.5E
FBCD<59> 6.3C 7.5E 8.5E
FBCD<60> 6.3C 7.5E 8.5E
FBCD<61> 6.3C 7.5E 8.5E
FBCD<62> 6.3C 7.5E 8.5E
FBCD<63> 6.3C 7.5E 8.5E
FBCDQM<0> 6.3C 7.4B 7.4B 8.4B

8.4B
FBCDQM<7..0> 6.3C<> 7.4A<> 8.4A<>

9.2E>
FBCDQM<1> 6.3C 7.4B 7.4C 8.4B

8.4C
FBCDQM<2> 6.3C 7.4B 7.4D 8.4B

8.4D
FBCDQM<3> 6.3C 7.4B 7.4E 8.4B

8.4E
FBCDQM<4> 6.3C 7.4B 7.5B 8.4B

8.5B
FBCDQM<5> 6.3C 7.4B 7.5C 8.4B

8.5C
FBCDQM<6> 6.3C 7.4B 7.5D 8.4B

8.5D
FBCDQM<7> 6.3C 7.4B 7.5E 8.4B

8.5E
FBCDQS_RN<0> 6.4C 7.4B 7.4B 8.4B

8.4B
FBCDQS_RN<7..0> 6.4C<> 7.4A<> 8.4A<>

9.2E<
FBCDQS_RN<1> 6.4C 7.4B 7.4C 8.4B

8.4C
FBCDQS_RN<2> 6.4C 7.4B 7.4D 8.4B

8.4D
FBCDQS_RN<3> 6.4C 7.4B 7.4E 8.4B

8.4E
FBCDQS_RN<4> 6.4C 7.4B 7.5B 8.4B

8.5B
FBCDQS_RN<5> 6.4C 7.4B 7.5C 8.4B

8.5C
FBCDQS_RN<6> 6.4C 7.4B 7.5D 8.4B

8.5D
FBCDQS_RN<7> 6.4C 7.4B 7.5E 8.4B

8.5E
FBCDQS_WP<0> 6.3C 7.4B 7.5B 8.4B

8.5B
FBCDQS_WP<7..0> 6.3C<> 7.5A<> 8.5A<>

9.2E>
FBCDQS_WP<1> 6.3C 7.4C 7.5B 8.4C

8.5B
FBCDQS_WP<2> 6.3C 7.4D 7.5B 8.4D

8.5B
FBCDQS_WP<3> 6.3C 7.4E 7.5B 8.4E

8.5B
FBCDQS_WP<4> 6.3C 7.5B 7.5B 8.5B

8.5B
FBCDQS_WP<5> 6.3C 7.5B 7.5C 8.5B

8.5C
FBCDQS_WP<6> 6.4C 7.5B 7.5D 8.5B

8.5D
FBCDQS_WP<7> 6.4C 7.5B 7.5E 8.5B

8.5E
FBCTL_R 17.4G
FBC_CLK0 6.4E> 7.2A< 8.2A<

9.1E<
FBC_CLK0* 6.4E> 7.2A< 8.2A<

9.1E<
FBC_CLK0_TERM 7.1A
FBC_CLK1 6.4E> 7.2D< 8.2D<

9.1E<
FBC_CLK1* 6.4E> 7.2D< 8.2D<

9.2E<
FBC_CLK1_TERM 7.1D
FBC_CMD<0> 6.3E 7.1B 8.1B 9.2E
FBC_CMD<27..0> 6.2F> 7.1A< 8.1A<

9.2E< 9.2E<
FBC_CMD<1> 6.3E 7.1B 7.2E 8.1E

8.2B
FBC_CMD<2> 6.3E 7.1B 8.1B 9.3E
FBC_CMD<3> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<4> 6.3E 7.1E 8.1E 9.3E
FBC_CMD<5> 6.3E 7.1E 8.1E 9.3E
FBC_CMD<6> 6.3E 7.1E 8.1E 9.3E
FBC_CMD<7> 6.3E 7.2B 7.2E 8.1B

8.1E
FBC_CMD<8> 6.3E 7.1B 7.1E
FBC_CMD<9> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<10> 6.3E 7.1B 7.1E 8.1B

ASSEMBLY
PAGE DETAIL

8.1E
FBC_CMD<11> 6.3E 7.1B 7.2E 8.1E

8.2B
FBC_CMD<12> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<13> 6.3E 7.1E 8.1E 9.3E
FBC_CMD<15> 6.3E 7.2B 7.2E 8.2B

8.2E
FBC_CMD<16> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<17> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<18> 6.3E 7.1E 7.2B 8.1B

8.2E
FBC_CMD<19> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<20> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<21> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<22> 6.3E 7.1B 8.1B 9.2E
FBC_CMD<23> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<24> 6.3E 7.1B 8.1B 9.2E
FBC_CMD<25> 6.3E 7.1B 7.1E 8.1B

8.1E
FBC_CMD<27> 6.3E 7.1E 7.2B 8.1B

8.2E
FBC_DEBUG 6.4E
FBC_PLLAVDD 6.4E
FBC_VREF0 7.1G 7.3D> 8.3D>

9.4E<>
FBC_VREF1 7.1G 7.3G> 8.3G>

9.4E<>
FBC_VREF2 7.1G 7.3E> 8.3D>

9.4E<>
FBC_VREF3 7.1G 7.3H> 8.3G>

9.4E<>
FBC_VREFCTL1 7.1G
FBC_VREFCTL2 7.1G
FBC_ZQ0 7.2B> 9.4E<>
FBC_ZQ1 7.2E> 9.4E<>
FBC_ZQ2 8.2B> 9.4E<>
FBC_ZQ3 8.2E> 9.4E<>
FBVDDCTL 17.4E
FBVDDQ 17.1A 17.3C
FBVDDQ_BOOT 17.2C
FBVDDQ_COMP 17.3B
FBVDDQ_COMP_RC 17.3C
FBVDDQ_FB 17.3C
FBVDDQ_FCCM 17.3B
FBVDDQ_FSET 17.3B
FBVDDQ_ISEN 17.3C
FBVDDQ_LG 17.3C
FBVDDQ_PHASE 17.3C
FBVDDQ_SNUB 17.3F
FBVDDQ_UG 17.2C
FBVDDQ_UG_R 17.2D
FB_PWRGOOD 11.1A< 17.3A>
FB_VCC 11.1A< 17.3A>
FB_VREF 3.4C> 6.5C<
FB_VREF1CTL 3.5B
GND_SENSE 2.3G> 16.5F<
GPIO0_DVI_A_HPD 13.3D
GPIO1_DVI_B_HPD 11.5A< 13.3H>
GPIO2_BL_PWM 12.4C< 13.3G>
GPIO3_PPEN 12.3C< 13.3G>
GPIO3_PPEN_GPU 13.3D
GPIO4_BLEN 12.4C< 13.3G>
GPIO4_BLEN_GPU 13.3D
GPIO5_NVVDDCTL0 13.3G> 16.4A<
GPIO6_NVVDDCTL1 13.3G> 16.4A<
GPIO7_NVVDDCTL2 13.3G> 16.5A<
GPIO8_THERM_ALERT* 13.3D
GPIO9_LVDS_SYS* 11.2A< 13.3G>
GPIO10_FBVREFCTL 3.5B< 4.2H< 7.2H<

13.3G>
GPIO12_AC_DET 13.3D
GPIO13_FBVDDQCTL 13.3G> 17.4D<
I2CA_SCL 10.1D
I2CA_SCL_R 10.1H> 12.3B<
I2CA_SDA 10.1D
I2CA_SDA_R 10.1H<> 12.3B<>
I2CB_SCL 10.3D
I2CB_SCL_R 10.3H> 12.2B<
I2CB_SDA 10.3D
I2CB_SDA_R 10.3H<> 12.2B<>
I2CC_SCL 13.3D
I2CC_SCL_R 12.4C< 13.2A< 13.3H>

14.2A<
I2CC_SDA 13.3D
I2CC_SDA_R 12.4C<> 13.2A<>

13.3H<> 14.2A<>
I2CH_SCL 14.4C
I2CH_SDA 14.4C
I2CS_SCL 13.3D

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
<edit here to insert page detail>

I2CS_SDA 13.3D
IFPABPLLVDD 11.2D
IFPABRSET 11.2D
IFPABVPROBE 11.1D
IFPAIOVDD 11.2D
IFPATXC 11.2H> 12.4G<
IFPATXC* 11.1H> 12.4G<
IFPATXD0 11.2H> 12.4G<
IFPATXD0* 11.2H> 12.4G<
IFPATXD1 11.2H> 12.4G<
IFPATXD1* 11.2H> 12.4G<
IFPATXD2 11.2H> 12.4G<
IFPATXD2* 11.2H> 12.4G<
IFPATXD3 11.2H> 12.4G<
IFPATXD3* 11.2H> 12.4G<
IFPBTXC 11.2H> 12.4G<
IFPBTXC* 11.2H> 12.4G<
IFPBTXD4 11.2H> 12.3G<
IFPBTXD4* 11.2H> 12.3G<
IFPBTXD5 11.2H> 12.4G<
IFPBTXD5* 11.2H> 12.4G<
IFPBTXD6 11.3H> 12.4G<
IFPBTXD6* 11.3H> 12.4G<
IFPBTXD7 11.3H> 12.4G<
IFPBTXD7* 11.3H> 12.4G<
IFPCBRSET 11.3D
IFPCPLLVDD 11.3D
IFPCTXC 11.3H> 12.2F<
IFPCTXC* 11.3H> 12.2F<
IFPCTXD0 11.3H> 12.2F<
IFPCTXD0* 11.3H> 12.2F<
IFPCTXD1 11.4H> 12.2F<
IFPCTXD1* 11.3H> 12.2F<
IFPCTXD2 11.4H> 12.2F<
IFPCTXD2* 11.4H> 12.2F<
IFPCVPROBE 11.3D
IFPC_IOVDD 11.3F 11.4D
IFPDTXC 11.4H<> 12.3G<>
IFPDTXC* 11.4H<> 12.3G<>
IFPDTXD3 11.4H> 12.3F<
IFPDTXD3* 11.4H> 12.3F<
IFPDTXD4 11.4H> 12.2F<
IFPDTXD4* 11.4H> 12.2F<
IFPDTXD5 11.4H> 12.2F<
IFPDTXD5* 11.4H> 12.2F<
IFPD_IOVDD 11.5D 11.5F
ISEN1 16.2C
ISEN2 16.3C
ISL9502_SET1 16.3B
ISL9502_SET2 16.3B
ISL9502_SET3 16.3B
JTAG_TCLK 13.3C
JTAG_TDI 13.3C
JTAG_TDO 13.3C
JTAG_TMS 13.3C
JTAG_TRST 13.3C
LG1 16.2C
LG2 16.3C
LVDSIOVDD_ISOL 11.2B
MIOACAL_PD_VDDQ 15.2B
MIOACAL_PU_GND 15.2B
MIOACLKOUTR* 15.2D
MIOA_VDDQ 15.1B
MIOA_VREF 15.2B
MIOBD<0> 15.3F 18.1C
MIOBD<11..0> 15.3G< 18.1A>
MIOBD<1> 15.3F 18.1C
MIOBD<3> 15.3F 18.2C
MIOBD<4> 15.4F 18.2C
MIOBD<5> 15.4F 18.2C
MIOBD<8> 15.4F 18.2C
MIOBD<9> 15.4F 18.2C
MIOBD<11> 15.4F 18.2C
MIOB_CTL3 15.4F< 18.1A> 18.2C
MIOB_HSYNC 15.4F< 18.2A> 18.4C
M_GPIO8_SLOWDOWN* 13.2C
M_THERM_ALERT* 13.2C
NVVDD 17.1A
NVVDD_SENSE 2.3G> 16.4F<
NVVDD_VDD 16.1C
NVVDD_VIN 16.1D
NV_PWRGOOD 13.2F< 16.1B> 17.3A<
OCSET 16.3C
PEX1V2 17.1A
PEX_PLLDVDD 2.4F
PEX_RST 2.1D
PEX_RX0 2.2E
PEX_RX0* 2.2E
PEX_RX1 2.2E
PEX_RX1* 2.2E
PEX_RX2 2.2E
PEX_RX2* 2.2E
PEX_RX3 2.3E
PEX_RX3* 2.3E
PEX_RX4 2.3E
PEX_RX4* 2.3E

PEX_RX5 2.3E
PEX_RX5* 2.3E
PEX_RX6 2.3E
PEX_RX6* 2.3E
PEX_RX7 2.3E
PEX_RX7* 2.3E
PEX_RX8 2.4E
PEX_RX8* 2.4E
PEX_RX9 2.4E
PEX_RX9* 2.4E
PEX_RX10 2.4E
PEX_RX10* 2.4E
PEX_RX11 2.4E
PEX_RX11* 2.4E
PEX_RX12 2.4E
PEX_RX12* 2.4E
PEX_RX13 2.5E
PEX_RX13* 2.5E
PEX_RX14 2.5E
PEX_RX14* 2.5E
PEX_RX15 2.5E
PEX_RX15* 2.5E
PEX_TSTCLK 2.2E
PEX_TSTCLK* 2.2E
PEX_TX0 2.2E
PEX_TX0* 2.2E
PEX_TX0_C 2.2B
PEX_TX0_C* 2.2B
PEX_TX1 2.2E
PEX_TX1* 2.2E
PEX_TX1_C 2.2B
PEX_TX1_C* 2.2B
PEX_TX2 2.2E
PEX_TX2* 2.2E
PEX_TX2_C 2.2B
PEX_TX2_C* 2.2B
PEX_TX3 2.2E
PEX_TX3* 2.2E
PEX_TX3_C 2.2B
PEX_TX3_C* 2.2B
PEX_TX4 2.3E
PEX_TX4* 2.3E
PEX_TX4_C 2.3B
PEX_TX4_C* 2.3B
PEX_TX5 2.3E
PEX_TX5* 2.3E
PEX_TX5_C 2.3B
PEX_TX5_C* 2.3B
PEX_TX6 2.3E
PEX_TX6* 2.3E
PEX_TX6_C 2.3B
PEX_TX6_C* 2.3B
PEX_TX7 2.3E
PEX_TX7* 2.3E
PEX_TX7_C 2.3B
PEX_TX7_C* 2.3B
PEX_TX8 2.3E
PEX_TX8* 2.3E
PEX_TX8_C 2.3B
PEX_TX8_C* 2.3B
PEX_TX9 2.4E
PEX_TX9* 2.4E
PEX_TX9_C 2.4B
PEX_TX9_C* 2.4B
PEX_TX10 2.4E
PEX_TX10* 2.4E
PEX_TX10_C 2.4B
PEX_TX10_C* 2.4B
PEX_TX11 2.4E
PEX_TX11* 2.4E
PEX_TX11_C 2.4B
PEX_TX11_C* 2.4B
PEX_TX12 2.4E
PEX_TX12* 2.4E
PEX_TX12_C 2.4B
PEX_TX12_C* 2.4B
PEX_TX13 2.4E
PEX_TX13* 2.4E
PEX_TX13_C 2.4B
PEX_TX13_C* 2.4B
PEX_TX14 2.5E
PEX_TX14* 2.5E
PEX_TX14_C 2.5B
PEX_TX14_C* 2.5B
PEX_TX15 2.5E
PEX_TX15* 2.5E
PEX_TX15_C 2.5B
PEX_TX15_C* 2.5B
PEX_VDD_FB 17.1G
PH1 16.2C
PH2 16.3C
PLL_VDD 10.4C
PWR_SRC 17.1A
RBIAS 16.2B
REFCLK 2.2E
REFCLK* 2.2E

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

<ENGINEER>

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

1

2

3

4

5

PAGEID
DATE

16-MAR-2007

HFDBA

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

ROMCS* 14.3C 14.3E
ROM_SCLK 14.3C 14.3E
ROM_SI 14.3E< 14.3E< 18.2A>

18.3C
ROM_SO 14.3C 14.3E
RUNPWROK 11.4A< 12.4A> 14.2A<

16.2B< 17.1F<
RUNPWROK_C 12.4C

1

SLI_CLKOUT 12.3F<> 15.2F<>
SLI_D<0> 12.3E 15.1D 18.3C
SLI_D<14..0> 12.3F<> 15.1F<>

18.2A>
SLI_D<1> 12.3E 15.1D 18.1C
SLI_D<2> 12.3E 15.1D
SLI_D<3> 12.3E 15.1D
SLI_D<4> 12.3E 15.1D
SLI_D<5> 12.3E 15.2D
SLI_D<6> 12.3E 15.2D 18.3C
SLI_D<7> 12.3E 15.2D
SLI_D<8> 12.3E 15.2D 18.4C
SLI_D<9> 12.3E 15.2D 18.4C
SLI_D<10> 12.3E 15.2D
SLI_D<11> 12.3E 15.2D
SLI_D<12> 12.3E 15.2D
SLI_D<13> 12.3E 15.2D 18.3C
SLI_D<14> 12.3E 15.2D
SLI_DE 12.3F<> 15.2F<>
SLI_REFCLK 12.3F<> 15.4G<>
SLI_SWAP_OUT 12.3H<> 14.4C<>

2

SLI_SYNC 12.3H<> 13.3G<>
SMB_CLK 12.4C<> 13.2F<
SMB_DAT 12.4C< 13.2F<>
SNN_BUFRST* 14.4C
SNN_CLAMP 13.3D
SNN_DACB_CSYNC 10.2D
SNN_DACC_BLUE 10.4D
SNN_DACC_GREEN 10.3D
SNN_DACC_RED 10.3D
SNN_DACC_RSET 10.3C
SNN_DACC_VREF 10.3C
SNN_FB2 16.3C
SNN_FBA0_NC1 4.2B
SNN_FBA0_NC2 5.2B
SNN_FBA0_NC3 5.2B
SNN_FBA1_NC1 4.2E
SNN_FBA1_NC2 5.2E
SNN_FBA1_NC3 5.2E
SNN_FBA_CMD14 3.3E
SNN_FBA_CMD26 3.3E
SNN_FBA_CMD28 3.4E
SNN_FBA_NC1_D31 3.4E

3

SNN_FBA_NC2_D32 3.4E
SNN_FBC0_NC1 7.2B
SNN_FBC0_NC2 8.2B
SNN_FBC0_NC3 8.2B
SNN_FBC1_NC1 7.2E
SNN_FBC1_NC2 8.2E
SNN_FBC1_NC3 8.2E
SNN_FBC_CMD14 6.3E
SNN_FBC_CMD26 6.3E
SNN_FBC_CMD28 6.3E
SNN_FBC_PLLVDD 6.4E
SNN_FBVTT_AA23 6.1E
SNN_FBVTT_AB23 6.1E
SNN_FBVTT_H16 6.1E
SNN_FBVTT_H17 6.1E
SNN_FBVTT_J9 6.1E
SNN_FBVTT_J10 6.1E
SNN_FBVTT_J23 6.1E
SNN_FBVTT_J24 6.1E
SNN_FBVTT_K9 6.1E
SNN_FBVTT_K11 6.1E
SNN_FBVTT_K12 6.1E

4

SNN_FBVTT_K21 6.1E
SNN_FBVTT_K22 6.1E
SNN_FBVTT_K24 6.1E
SNN_FBVTT_L23 6.1E
SNN_FBVTT_M23 6.1E
SNN_FBVTT_T25 6.1E
SNN_FBVTT_U25 6.1E
SNN_G3_RFU1 15.4F
SNN_G3_RFU2 15.4F
SNN_G3_RFU3 15.4F
SNN_G3_RFU4 15.4F
SNN_G3_RFU5 15.4F
SNN_G3_RFU6 15.4F
SNN_G3_RFU7 15.4F
SNN_G3_RFU8 15.4F
SNN_G3_RFU9 14.4A
SNN_G3_RFU10 14.4A
SNN_G3_RFU11 14.4A
SNN_G3_RFU12 14.4A
SNN_G3_RFU13 14.4A
SNN_G3_RFU14 14.4A
SNN_G3_RFU15 14.4A

5

SNN_G3_RFU16 14.4A

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

SNN_GPIO14 13.3D
SNN_HDCP_ROM 14.4D
SNN_ISL9502_NC1 16.4C
SNN_ISL9502_NC2 16.4C
SNN_MIOBCAL_PD_VDD 15.4D
Q
SNN_MIOBCAL_PU_GND 15.4D
SNN_MIOBD<2> 15.3F
SNN_MIOBD<6> 15.4F
SNN_MIOBD<7> 15.4F
SNN_MIOBD<10> 15.4F
SNN_MIOB_CLKOUT 15.4F
SNN_MIOB_CLKOUT* 15.4F
SNN_MIOB_DE 15.4F
SNN_MIOB_VREF 15.4D
SNN_MIOB_VSYNC 15.4F
SNN_MSTRAPSEL0 14.3A
SNN_MSTRAPSEL1 14.3A
SNN_MSTRAPSEL2 14.3A
SNN_MSTRAPSEL3 14.4A
SNN_NTC 16.2B
SNN_POK 17.1F
SNN_RFU 15.2D
SNN_RFU1 2.1D
SNN_RFU2 2.1D
SNN_STEREO 14.4C
SNN_STRAP 14.3A
SNN_THERMAL 13.3C
SNN_VRHOT* 16.3B
SNUB1 16.2F
SNUB2 16.4F
SOFT 16.3B
SPDIF 2.5F
SPDIF_C 2.5H< 12.4C>
SSFOUT 10.4B< 14.1D>
SS_OUT 14.2C
SS_REF 14.2C
TESTMCLK 14.4C
TESTMODE 14.4C
THERM 13.3C
THERM* 13.3C
THERM_ALERT* 12.4C< 13.2H>
THERM_SCL 13.2C
THERM_SDA 13.2C
THERM_VDD 13.1D
TMDSIOVDD_AB__EN* 11.2B
TMDSIOVDD_C 11.4C
TMDSIOVDD_C_EN* 11.4B
TMDSIOVDD_D 11.5C
TMDSIOVDD_D_EN 11.5C
TMDSIOVDD_D_EN* 11.5B
TMDS_LVDS_IOVDD 11.2B
UG1 16.2C
UG1_R 16.2E
UG2 16.2C
UG2_R 16.3E
VDIFF 16.2B
VDIFF_R 16.2A
VID0 16.3B
VID4 16.3B
VID5 16.3B
VO 16.3C
VSEN 16.4C
VSUM 16.3C 16.3F 16.4G
VW 16.2B
XTALIN 10.5C
XTALOUT 10.5D
XTALOUTBUFF 10.4F> 14.2A<

C GE

ASSEMBLY
PAGE DETAIL

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
<edit here to insert page detail>

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

<ENGINEER>

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

1

2

3

4

5

PAGEID
DATE

16-MAR-2007

HFDBA

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

A B C D E F G H

Title: Cref Part
Report
Design: p409
Date: Feb 9
16:02:25 2007

C1 [2.1A]

1

C2 [17.3H]
C3 [17.3G]
C4 [10.5E]
C5 [2.3A]
C6 [11.2C]
C7 [10.5C]
C8 [17.3G]
C9 [14.3F]
C10 [13.2D]
C11 [17.3F]
C12 [11.3F]
C13 [11.5F]
C14 [11.3F]
C15 [15.2A]
C16 [13.2C]
C17 [11.3F]
C18 [11.3F]
C19 [11.5E]
C20 [8.4F]
C21 [5.4F]
C22 [8.4F]

2

C23 [8.4F]
C24 [5.3H]
C25 [5.5G]
C26 [11.5C]
C27 [8.5F]
C28 [5.4G]
C29 [5.5H]
C30 [5.4G]
C31 [11.5D]
C32 [11.5D]
C33 [8.4F]
C34 [11.5D]
C35 [3.2F]
C36 [7.3D]
C37 [5.5G]
C38 [8.4F]
C39 [8.5G]
C40 [17.2F]
C41 [17.2F]
C42 [17.2E]
C43 [5.5F]
C44 [5.3F]

3

C45 [8.4G]
C46 [16.1G]
C47 [16.1G]
C48 [3.2E]
C49 [16.1H]
C50 [5.5G]
C51 [5.4F]
C52 [16.1G]
C53 [5.4F]
C54 [8.5F]
C55 [16.1H]
C56 [16.1H]
C57 [5.3G]
C58 [8.5F]
C59 [5.5G]
C60 [5.4G]
C61 [8.5F]
C62 [5.4G]
C63 [8.4G]
C64 [2.3A]
C65 [17.1H]
C66 [5.3G]

4

C67 [5.5G]
C68 [5.4G]
C69 [8.4F]
C70 [5.5F]
C71 [5.4H]
C72 [5.3G]
C73 [17.1H]
C74 [16.2F]
C75 [4.3E]
C76 [4.3G]
C77 [8.4F]
C78 [8.4F]
C79 [8.5G]
C80 [8.4F]
C81 [8.5G]
C82 [8.4F]
C83 [5.4G]
C84 [8.4G]
C85 [5.4G]
C86 [5.4H]
C87 [5.4G]
C88 [16.2D]

5

C89 [5.3G]

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

C90 [8.5F]
C91 [8.4F]
C92 [8.4G]
C93 [8.5F]
C94 [5.5G]
C95 [8.4F]
C96 [8.4F]
C97 [8.4F]
C98 [5.5G]
C99 [16.1E]
C100 [16.1E]
C101 [8.4G]
C102 [5.5H]
C103 [16.3F]
C104 [16.1E]
C105 [16.1E]
C106 [16.1E]
C107 [16.1E]
C108 [5.5G]
C109 [8.4F]
C110 [8.5G]
C111 [4.4H]
C112 [8.4F]
C113 [8.4G]
C114 [5.4G]
C115 [5.4H]
C116 [5.4G]
C117 [8.5F]
C118 [8.5F]
C119 [4.3H]
C120 [4.3D]
C121 [16.3G]
C501 [16.3F]
C502 [4.3F]
C503 [4.5F]
C504 [4.5G]
C505 [4.4G]
C506 [4.5G]
C507 [4.3G]
C508 [4.5H]
C509 [4.4G]
C510 [4.4G]
C511 [4.5G]
C512 [4.4G]
C513 [4.4H]
C514 [16.2A]
C515 [16.2A]
C516 [4.3H]
C517 [4.4G]
C518 [16.1E]
C519 [16.3F]
C520 [4.4G]
C521 [4.5G]
C522 [16.2A]
C523 [16.3B]
C524 [4.4G]
C525 [16.2B]
C526 [4.5H]
C527 [4.4G]
C528 [16.3F]
C529 [4.1A]
C530 [16.1B]
C531 [16.4D]
C532 [4.4F]
C533 [4.4F]
C534 [4.1D]
C535 [16.4E]
C536 [16.2E]
C537 [16.3D]
C538 [8.4G]
C539 [4.5G]
C540 [16.4G]
C541 [16.4G]
C542 [16.3D]
C543 [4.4G]
C544 [4.5G]
C545 [16.3D]
C546 [17.1G]
C547 [5.4G]
C548 [4.4G]
C549 [4.4G]
C550 [4.4H]
C551 [4.5G]
C552 [4.3G]
C553 [4.5G]
C554 [4.4G]
C555 [4.3G]
C556 [8.4G]
C557 [4.3G]
C558 [4.5F]
C559 [4.4F]
C560 [16.1C]
C561 [16.1D]
C562 [2.2A]
C563 [17.1F]
C564 [16.2D]

C565 [2.2A]
C566 [2.2A]
C567 [3.4F]
C568 [16.2D]
C569 [2.1G]
C570 [3.4E]
C571 [7.4F]
C572 [7.5F]
C573 [7.5G]
C574 [7.5F]
C575 [7.4G]
C576 [7.4G]
C577 [16.2G]
C578 [7.4G]
C579 [12.4B]
C580 [16.2G]
C581 [7.5F]
C582 [2.5D]
C583 [7.5F]
C584 [2.5C]
C585 [2.5D]
C586 [7.4G]
C587 [2.5C]
C588 [2.4D]
C589 [7.3G]
C590 [2.4C]
C591 [3.2E]
C592 [7.3H]
C593 [3.2E]
C594 [6.5D]
C595 [3.2F]
C596 [3.2E]
C597 [2.4D]
C598 [3.2E]
C599 [3.2F]
C600 [7.4F]
C601 [2.4C]
C602 [3.5C]
C603 [2.4D]
C604 [7.4F]
C605 [2.4C]
C606 [2.4D]
C607 [7.4G]
C608 [2.4C]
C609 [2.4D]
C610 [7.4F]
C611 [2.1G]
C612 [3.1G]
C613 [3.1F]
C614 [3.1F]
C615 [2.1G]
C616 [3.2F]
C617 [2.4C]
C618 [3.2F]
C619 [2.3D]
C620 [7.4F]
C621 [3.4F]
C622 [2.4G]
C623 [2.3C]
C624 [2.1G]
C625 [3.1E]
C626 [3.1E]
C627 [3.2F]
C628 [3.1F]
C629 [3.1F]
C630 [2.3D]
C631 [7.4F]
C632 [2.3G]
C633 [3.2F]
C634 [2.1G]
C635 [2.1F]
C636 [2.3C]
C637 [7.5G]
C638 [7.4G]
C639 [2.3D]
C640 [2.1H]
C641 [3.2F]
C642 [2.3G]
C643 [2.2G]
C644 [2.2G]
C645 [3.2E]
C646 [7.1D]
C647 [2.1F]
C648 [2.3C]
C649 [2.1H]
C650 [3.1F]
C651 [2.3H]
C652 [2.3D]
C653 [2.1G]
C654 [2.3G]
C655 [3.2F]
C656 [2.1G]
C657 [3.1F]
C658 [3.1F]
C659 [2.3C]
C660 [2.2G]

C661 [2.2G]
C662 [2.3D]
C663 [3.2F]
C664 [2.1H]
C665 [2.3G]
C666 [2.2G]
C667 [2.3C]
C668 [2.4G]
C669 [2.2D]
C670 [2.2H]
C671 [2.4G]
C672 [2.2H]
C673 [3.2F]
C674 [2.2H]
C675 [2.2G]
C676 [2.2G]
C677 [2.2C]
C678 [2.4G]
C679 [2.1G]
C680 [2.2D]
C681 [2.2G]
C682 [2.2C]
C683 [3.1F]
C684 [2.4G]
C685 [2.2G]
C686 [2.2D]
C687 [2.4G]
C688 [2.2G]
C689 [3.1F]
C690 [2.2G]
C691 [2.2G]
C692 [7.1A]
C693 [2.4F]
C694 [2.1H]
C695 [6.4F]
C696 [2.2G]
C697 [2.2C]
C698 [7.4F]
C699 [3.1F]
C700 [7.5F]
C701 [3.1E]
C702 [6.4F]
C703 [2.2D]
C704 [7.4F]
C705 [2.2G]
C706 [2.4G]
C707 [10.4C]
C708 [7.5F]
C709 [2.2G]
C710 [2.2G]
C711 [2.2C]
C712 [2.2H]
C713 [3.1G]
C714 [10.2B]
C715 [2.4G]
C716 [10.4B]
C717 [10.2C]
C718 [3.2F]
C719 [3.1E]
C720 [2.3G]
C721 [2.3G]
C722 [11.4D]
C723 [11.2D]
C724 [11.2E]
C725 [10.2B]
C726 [5.4G]
C727 [6.4F]
C728 [10.2B]
C729 [15.1B]
C730 [15.1A]
C731 [11.5D]
C732 [7.4G]
C733 [2.4G]
C734 [10.2B]
C735 [7.4F]
C736 [3.2F]
C737 [11.2D]
C738 [2.5G]
C739 [2.3G]
C740 [7.5G]
C741 [11.4D]
C742 [11.4D]
C743 [7.3D]
C744 [15.3D]
C745 [11.4D]
C746 [10.2B]
C747 [11.4D]
C748 [11.5F]
C749 [7.4G]
C750 [7.5F]
C751 [3.2F]
C752 [11.2D]
C753 [11.5F]
C754 [7.4F]
C755 [7.4F]
C756 [17.3D]

C757 [7.4F]
C758 [7.4F]
C759 [17.2A]
C760 [17.3D]
C761 [7.5G]
C762 [7.5F]
C763 [7.4F]
C764 [7.4F]
C765 [7.4F]
C766 [17.3B]
C767 [11.2E]
C768 [10.4B]
C769 [11.4C]
C770 [10.2B]
C771 [10.2B]
C772 [11.2D]
C773 [11.2D]
C774 [17.2E]
C775 [11.4D]
C776 [17.4F]
C777 [10.4B]
C778 [11.2D]
C779 [15.1B]
C780 [11.4D]
C781 [17.2B]
C782 [17.2E]
C783 [17.3C]
C784 [17.4C]
C785 [11.2C]
C786 [14.2C]
C787 [11.2D]
C788 [11.4C]
C789 [2.3G]
C790 [14.2C]
C791 [15.1A]
C792 [14.4D]
C793 [14.2D]
C794 [2.1A]
C795 [11.2B]
C796 [14.2D]
CN1 [2.3B]
CN1 [12.3D]
D1 [17.3E]
D2 [16.2F]
D3 [16.3F]
D501 [13.3H]
D502 [13.3G]
G1 [2.3F]
G1 [3.3D]
G1 [6.3D]
G1 [10.3D 10.2D

10.1D 10.4D]
G1 [11.4E 11.2E]
G1 [13.3D]
G1 [14.3G 14.4B]
G1 [15.4E 15.2C]
L1 [17.2F]
L2 [17.3F]
L3 [16.2G]
L4 [16.2G]
L5 [16.3G]
LB1 [11.5C]
LB2 [11.4D]
LB501 [3.4F]
LB502 [2.4H]
LB503 [6.4F]
LB504 [10.4B]
LB505 [11.3D]
LB506 [10.1B]
LB507 [10.2A]
LB508 [11.3C]
LB509 [11.2C]
LB510 [11.2D]
LB511 [15.1A]
LB512 [11.4D]
M1 [7.4E 7.4C 7.4D

7.2C 7.4D]
M2 [7.5C 7.5D 7.5D

7.5E 7.2F]
M3 [4.2C 4.4C 4.4E

4.4D 4.4E]
M4 [4.5E 4.5E 4.2F

4.5D 4.5C]
M501 [5.5E 5.2F 5.5E

5.5D 5.5C]
M502 [5.4D 5.4C 5.4E

5.2C 5.4E]
M503 [8.2F 8.5D 8.5E

8.5C 8.5D]
M504 [8.4E 8.4C 8.4D

8.2C 8.4D]
MEC1 [18.5G 18.4G

18.4G 18.4G

18.5G 18.5G

18.4G 18.4G]
MEC501 [18.4H 18.4H

C GE

ASSEMBLY
PAGE DETAIL

18.4H 18.5H]
Q1 [11.2B]
Q2 [11.2A 11.3A]
Q3 [13.2E 13.2E]
Q4 [11.5C]
Q5 [17.3E]
Q6 [11.2B]
Q7 [17.2E]
Q8 [7.1G]
Q9 [3.5B]
Q10 [16.3F]
Q11 [16.2F]
Q12 [16.3E]
Q13 [16.2E]
Q14 [16.2F]
Q15 [16.3F]
Q501 [4.2G]
Q502 [4.1G]
Q503 [7.2G]
Q504 [16.5B]
Q505 [17.4F]
Q506 [11.2C]
Q507 [11.2B]
Q508 [11.4A 11.5B]
Q509 [11.4C]
Q510 [13.2F]
R1 [18.1D]
R2 [2.2A]
R3 [18.2D]
R4 [11.2A]
R5 [18.1C]
R6 [2.2A]
R7 [18.2C]
R8 [18.1C]
R9 [18.2C]
R10 [10.4E]
R11 [18.1D]
R12 [14.3E]
R13 [17.3F]
R14 [18.2D]
R15 [13.1F]
R16 [13.2B]
R17 [13.4E]
R18 [13.2B]
R19 [13.1F]
R20 [14.2C]
R21 [14.1C]
R22 [13.3E]
R23 [15.2B]
R24 [18.2D]
R25 [13.1D]
R26 [13.4F]
R27 [14.1C]
R28 [13.1G]
R29 [18.2D]
R30 [15.2A]
R31 [13.1G]
R32 [11.5C]
R33 [18.4D]
R34 [13.1H]
R35 [13.1H]
R36 [13.1G]
R37 [13.2D]
R38 [13.3D]
R39 [10.5E]
R40 [18.3C]
R41 [18.2D]
R42 [18.2D]
R43 [11.5D]
R44 [18.3D]
R45 [11.3G]
R46 [11.3G]
R47 [11.3G]
R48 [11.3G]
R49 [11.3G]
R50 [11.3G]
R51 [11.5G]
R52 [11.5G]
R53 [11.5G]
R54 [11.5G]
R55 [11.3G]
R56 [11.3G]
R57 [13.1F]
R58 [13.2E]
R59 [13.3E]
R61 [12.3F]
R62 [11.2B]
R63 [12.3F]
R64 [18.1C]
R65 [9.2F]
R66 [9.2F]
R67 [7.1G]
R68 [18.4D]
R69 [9.2F]
R70 [7.3D]
R71 [18.3D]

BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
<edit here to insert page detail>

R72 [9.2F]
R73 [18.4D]
R74 [7.3D]
R75 [7.2B]
R76 [8.2B]
R77 [7.1A]
R78 [7.1A]
R79 [7.1D]
R80 [7.1D]
R81 [7.2E]
R82 [9.2F]
R83 [9.2G]
R84 [9.2F]
R85 [9.2G]
R86 [3.5C]
R87 [3.5C]
R88 [3.5C]
R89 [4.3D]
R90 [4.3D]
R91 [4.1G]
R92 [4.1G]
R93 [4.3G]
R94 [4.3G]
R95 [9.2C]
R96 [9.2C]
R97 [9.2C]
R98 [9.2D]
R99 [4.2E]
R100 [4.1E]
R101 [4.1A]
R102 [4.1D]
R103 [4.1A]
R104 [4.2B]
R105 [5.2E]
R106 [4.1G]
R107 [4.3G]
R108 [4.3G]
R109 [4.2G]
R110 [4.3D]
R111 [4.3D]
R501 [9.2C]
R502 [9.2B]
R503 [9.2C]
R504 [9.2C]
R505 [16.2B]
R506 [16.2A]
R507 [4.2B]
R508 [16.2B]
R509 [4.2B]
R510 [16.2B]
R511 [16.4G]
R512 [16.4F]
R513 [16.2B]
R514 [16.3A]
R515 [16.4E]
R516 [16.1C]
R517 [16.3A]
R518 [16.2D]
R519 [4.1D]
R520 [16.4E]
R521 [16.5G]
R522 [4.1A]
R523 [16.4G]
R524 [16.2D]
R525 [16.1B]
R526 [16.3A]
R527 [4.2B]
R528 [16.3G]
R529 [16.3A]
R530 [16.3D]
R531 [16.4D]
R532 [16.3D]
R533 [17.1G]
R534 [16.3B]
R535 [5.2B]
R536 [16.3B]
R537 [17.1G]
R538 [16.4B]
R539 [16.4B]
R540 [16.1D]
R541 [16.4B]
R542 [16.3H]
R543 [16.3G]
R544 [16.2D]
R545 [4.1H]
R546 [16.2F]
R547 [6.4E]
R548 [4.1H]
R549 [12.4B]
R550 [16.2G]
R551 [16.2G]
R552 [16.2G]
R553 [16.2H]
R554 [7.3G]
R555 [7.3G]
R556 [7.1G]

R557 [7.1G]
R558 [7.3G]
R559 [7.3G]
R560 [14.4C]
R561 [6.4F]
R562 [6.4F]
R563 [8.2E]
R564 [7.1D]
R565 [7.2B]
R566 [7.2B]
R567 [7.2B]
R568 [7.1A]
R569 [10.2F]
R570 [13.3B]
R571 [10.2F]
R572 [2.2D]
R573 [10.2E]
R574 [13.3B]
R575 [13.3B]
R576 [10.2C]
R577 [12.3G]
R578 [10.3F]
R579 [12.3G]
R580 [10.3C]
R581 [10.3E]
R582 [10.3C]
R583 [10.3E]
R584 [7.3D]
R585 [7.3D]
R586 [7.1G]
R587 [11.3D]
R588 [11.2D]
R589 [13.3B]
R590 [13.3B]
R591 [16.4B]
R592 [18.3C]
R593 [11.5G]
R594 [11.5G]
R595 [11.5G]
R596 [11.5G]
R597 [13.3H]
R598 [16.3B]
R599 [13.3G]
R600 [17.2D]
R601 [16.5B]
R602 [17.3D]
R603 [17.3B]
R604 [10.1E]
R605 [10.1E]
R606 [17.4E]
R607 [15.2B]
R608 [10.1F]
R609 [10.1F]
R610 [17.4E]
R611 [17.3G]
R612 [17.3B]
R613 [17.2B]
R614 [15.2A]
R615 [13.3G]
R616 [13.3G]
R617 [17.4G]
R618 [14.2D]
R619 [13.4F]
R620 [13.4F]
R621 [13.2E]
R622 [10.3E]
R623 [16.5B]
R624 [16.4B]
R625 [11.1C]
R626 [14.4D]
R627 [13.2H]
R628 [17.2B]
R629 [13.2D]
R630 [14.4C]
R631 [10.3F]
R632 [10.3G]
R633 [13.2G]
R634 [10.3G]
R635 [17.3B]
R636 [14.4C]
R637 [18.2D]
R638 [11.4B]
R639 [17.3G]
R640 [11.2C]
R641 [16.3D]
TP501 [3.4E]
TP502 [13.3B]
TP503 [6.4E]
TP504 [13.3B]
TP505 [13.3B]
TP506 [13.3B]
TP507 [13.3B]
TP508 [15.2D]
TP509 [10.3E]
TP510 [11.3D]
TP511 [11.1D]

TP512 [10.3E]
U1 [14.4D]
U2 [14.3E]
U3 [14.2B]
U4 [13.2C]
U5 [17.1G]
U501 [16.3C]
U502 [17.3C]
Y1 [10.5D]

NVIDIA CORPORATION

2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA

NV_PN

600-10409-xxxx-300 A

<ENGINEER>

NAMEIMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

1

2

3

4

5

PAGEID
DATE

16-MAR-2007

HFDBA

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn