MSI MS-V112 Schematic 10

8

7

6

5

4

3

2

1

+12V_BUS

C1

CAP CER 10UF 20% 16V X5R

10UF

(1206)1.8MM H MAX

+12V_BUS

+12V_BUS

C3

C2

D D

+3.3V_BUS

+3.3V_BUS

C C

B B

150nF_16V

150nF_16V

LF CAP CER 150NF 10% 16V X7R (0603)

CAP CER 10UF 10% 6.3V X6S
(0805)1.4MM MAX THICK

C4
10uF_X6S

C6
1uF_6.3V

C0
10nF

C5
100nF_6.3V

Place these caps as close to the PCIE
connector as possible

TEST_EN_J TEST_EN_J

No JTAG

R1

0R

PETn0_GFXRn0(2)

PETp1_GFXRp1(2)
PETn1_GFXRn1(2)

PETp2_GFXRp2(2)
PETn2_GFXRn2(2)

PETp3_GFXRp3(2)
PETn3_GFXRn3(2)

PETp4_GFXRp4(2)
PETn4_GFXRn4(2)

PETp5_GFXRp5(2)
PETn5_GFXRn5(2)

PETp6_GFXRp6(2)
PETn6_GFXRn6(2)

PETp7_GFXRp7(2)
PETn7_GFXRn7(2)

PETp8_GFXRp8(2)
PETn8_GFXRn8(2)

PETp9_GFXRp9(2)
PETn9_GFXRn9(2)

PETp10_GFXRp10(2)
PETn10_GFXRn10(2)

PETp11_GFXRp11(2)
PETn11_GFXRn11(2)

PETp12_GFXRp12(2)
PETn12_GFXRn12(2)

PETp13_GFXRp13(2)
PETn13_GFXRn13(2)

PETp14_GFXRp14(2)
PETn14_GFXRn14(2)

PETp15_GFXRp15(2)
PETn15_GFXRn15(2)

PRESENCE

PCI-EXPRESS EDGE CONNECTOR

+3.3V_BUS

+12V_BUS

+12V#B1
+12V#B2
+12V#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1

3.3Vaux
WAKE#

RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82

x16 PCIe

Mechanical Key

PRSNT1#A1

+12V#A2
+12V#A3

GND#A4

JTAG2
JTAG3
JTAG4
JTAG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12
REFCLK+
REFCLK­GND#A15

PERp0
PERn0

GND#A18

RSVD#A19

GND#A20

PERp1

PERn1
GND#A23
GND#A24

PERp2

PERn2
GND#A27
GND#A28

PERp3

PERn3
GND#A31

RSVD#A32
RSVD#A33

GND#A34

PERp4

PERn4
GND#A37
GND#A38

PERp5

PERn5
GND#A41
GND#A42

PERp6

PERn6
GND#A45
GND#A46

PERp7

PERn7
GND#A49

RSVD#A50

GND#A51

PERp8

PERn8
GND#A54
GND#A55

PERp9

PERn9
GND#A58
GND#A59

PERp10

PERn10
GND#A62
GND#A63

PERp11

PERn11
GND#A66
GND#A67

PERp12

PERn12
GND#A70
GND#A71

PERp13

PERn13
GND#A74
GND#A75

PERp14

PERn14
GND#A78
GND#A79

PERp15

PERn15
GND#A82

MPCIE1

JTRST

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

PRESENCE

+12V_BUS

JTCK
JTDI
JTDO
JTMS

PERp0
PERn0

PERp1
PERn1

PERp2
PERn2

PERp3
PERn3

PERp4
PERn4

PERp5
PERn5

PERp6
PERn6

PERp7
PERn7

PERp8
PERn8

PERp9
PERn9

PERp10
PERn10

PERp11
PERn11

PERp12
PERn12

PERp13
PERn13

PERp14
PERn14

PERp15
PERn15

+3.3V_BUS

TP4
35mil

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

TP3

TP1

TP2

35mil

35mil

35mil

No JTAG

R2 0R

TDA08H0SB1R

98
107

TSW1

116
125
134
143

2 1345678

152

ON

161

JTRST

PCIE_REFCLKP (2)

C7

C8
100nF_6.3V

C9

C10
100nF_6.3V

C11

C12
100nF_6.3V

C13

C14
100nF_6.3V

C15

C16
100nF_6.3V

C17

C18
100nF_6.3V

C19

C20
100nF_6.3V

C21

C22
100nF_6.3V

C23

C24
100nF_6.3V

C25

C26
100nF_6.3V

C27

C28
100nF_6.3V

C29

C30
100nF_6.3V

C31

C32
100nF_6.3V

C33

C34
100nF_6.3V

C35

C36
100nF_6.3V

C37

C38
100nF_6.3V

PCIE_REFCLKN (2)PETp0_GFXRp0(2)

GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)

GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)

GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)

GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)

GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)

GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)

GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)

GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)

GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)

GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)

GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)

GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)

GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)

GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)

GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)

GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)

TP6
35mil

+3.3V

53

1
2

R_RST

R3 0R

C39
100nF_6.3V

NC7SZ08P5X_NL

4

U5

DNI

PERST#_buf (2)

PERST#

TEST_EN_R (3)

HSYNC1 (3,7,15)

VSYNC1 (3,7,15)

DDC1DATA (3,15)

DDC3CLK (3,18)
DDC1CLK (3,15)

Place R3 in U5

Table 1: Connection for JTAG

Production
(No JTAG)

Internal Use Only

TSW1, R1 & R2 are located on the bottom side of the board close to PCIE connector.

Install R1, R2 & Don't Install TSW1

Install TSW1 & Don't Install R1 & R2

TSW1 Switch #1, 2, 3, 4, 5 and 6 closed (ON)

JTAG

#8 and 7 open

TSW1 Switch #1, 2, 3, 4, 5 and 6 open

NO JTAG

#8 & 7 closed (ON)

SYMBOL LEGEND

DO NOT

DNI

INSTALL
ACTIVE

#

LOW
DIGITAL

GROUND

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

Title

8

7

6

5

4

3

RH RV670 - PCI-E Edge Connector

2

Advanced Micro Devices Inc.
1 Commerce Valley Drive East
Markham, Ontario

Friday, September 07, 2007

Sheet

1 21

of

ANALOG
GROUND

BUO BRING UP

ONLY

Doc No.

105-B340xx-00

1

RevDate:

2

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

D D

4

3

2

1

NOTE: some of the PCIE testpoints will
be available trought via on traces.

PETp0_GFXRp0(1)
PETn0_GFXRn0(1)

PETp1_GFXRp1(1)
PETn1_GFXRn1(1)

PETp2_GFXRp2(1)
PETn2_GFXRn2(1)

PETp3_GFXRp3(1)
PETn3_GFXRn3(1)

PETp4_GFXRp4(1)
PETn4_GFXRn4(1)

PETp5_GFXRp5(1)
PETn5_GFXRn5(1)

PETp6_GFXRp6(1)

C C

B B

PCIE_REFCLKP(1)
PCIE_REFCLKN(1)

PETn6_GFXRn6(1)

PETp7_GFXRp7(1)
PETn7_GFXRn7(1)

PETp8_GFXRp8(1)

PETp9_GFXRp9(1)
PETn9_GFXRn9(1)

PETp10_GFXRp10(1)
PETn10_GFXRn10(1)

PETp11_GFXRp11(1)
PETn11_GFXRn11(1)

PETp12_GFXRp12(1)
PETn12_GFXRn12(1)

PETp13_GFXRp13(1)
PETn13_GFXRn13(1)

PETp14_GFXRp14(1)
PETn14_GFXRn14(1)

PETp15_GFXRp15(1)
PETn15_GFXRn15(1)

DNI DNI

R13

R14

51R

51R

402 402

620NOPN008

TP11

620NOPN008

TP12

620NOPN008

TP13

620NOPN008

TP14

620NOPN008

TP19

620NOPN008

TP20

620NOPN008

TP21

620NOPN008

TP22

620NOPN008

TP27

620NOPN008

TP28

620NOPN008

TP7

620NOPN008

TP8

620NOPN008

TP9

620NOPN008

TP10

620NOPN008

TP15

620NOPN008

TP16

620NOPN008

TP17

620NOPN008

TP18

620NOPN008

TP23

620NOPN008

TP24

620NOPN008

TP25

620NOPN008

TP26

PERST#_buf(1)

AW48
AW46

AV51
AV49

AU48
AU46

AT51
AT49

AR48
AR46

AP51
AP49

AN48
AN46

AM51
AM49

AL48
AL46

AK51
AK49

AH51
AH49

AG48
AG46

AF51
AF49

AE48
AE46

AD51
AD49

AW43
AW42

AP36

AJ48
AJ46

U1A

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

PCIE_RX10P
PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX12P
PCIE_RX12N

PCIE_RX13P
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N

PCIE_RX15P
PCIE_RX15N

Clock

PCIE_REFCLKP
PCIE_REFCLKN

PERSTB

PART 1 OF 10

P
C
I

­E
X
P
R
E
S
S

I
N
T
E
R
F
A
C
E

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

Calibration

PCIE_CALRN
PCIE_CALRP

AU40
AU39

AU43
AU42

AT40
AT39

AT43
AT42

AP40
AP39

AP43
AP42

AN40
AN39

AN43
AN42

AL40
AL39

AL43
AL42

AK40
AK39

AK43
AK42

AH40
AH39

AH43
AH42

AG40
AG39

AG43
AG42

AN37
AP37

GFXTp0_PERp0 (1)
GFXTn0_PERn0 (1)

GFXTp1_PERp1 (1)
GFXTn1_PERn1 (1)

GFXTp2_PERp2 (1)
GFXTn2_PERn2 (1)

GFXTp3_PERp3 (1)
GFXTn3_PERn3 (1)

GFXTp4_PERp4 (1)
GFXTn4_PERn4 (1)

GFXTp5_PERp5 (1)
GFXTn5_PERn5 (1)

GFXTp6_PERp6 (1)
GFXTn6_PERn6 (1)

GFXTp7_PERp7 (1)
GFXTn7_PERn7 (1)

GFXTp8_PERp8 (1)
GFXTn8_PERn8 (1)PETn8_GFXRn8(1)

GFXTp9_PERp9 (1)
GFXTn9_PERn9 (1)

GFXTp10_PERp10 (1)
GFXTn10_PERn10 (1)

GFXTp11_PERp11 (1)
GFXTn11_PERn11 (1)

GFXTp12_PERp12 (1)
GFXTn12_PERn12 (1)

GFXTp13_PERp13 (1)
GFXTn13_PERn13 (1)

GFXTp14_PERp14 (1)
GFXTn14_PERn14 (1)

GFXTp15_PERp15 (1)
GFXTn15_PERn15 (1)

+PCIE_VDDC

402

R82.0K

402

R91.27K

For Tektronix LA only

Place close
to ASIC

A A

5

4

RV670 PRO

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

Title

3

2

RH RV670 - ASIC PCIE_Interface

Advanced Micro Devices Inc.
1 Commerce Valley Drive East
Markham, Ontario

Friday, September 07, 2007

Sheet

2 21

of

1

Doc No.

RevDate:

2

105-B340xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK

4.7uF , X6S/X5R, 0603, 6.3V
1uF, X6S, 0402, 6.3V
100nF, X7R, 0402
10nF , X7R, 0402

Place close to ASIC

NS100

NS_VIA

1 2

GND_T2PVSS

10uF_X6S

DDC3DATA(18)

DDC3CLK(1,18)

3
1

R106 100R

R100 100R

R101 100R

R102 100R

R103 100R

R104 100R

R105 100R

10uF_X6S

C103

R7
1K

OSC_EN

DNI

C100

1uF_6.3V

C106

1uF_6.3V

+3.3V

R40

4.7K

402 402

+1.8V

R43 221R
R44 110R

C46 100nF_6.3V

DNI

NR81 182R
R81 182R

Share one pad

C102

C108

1uF_6.3V

R41

4.7K

TP42

OSC_EN (14)

T2XCM
T2XCP

T2X0M
T2X0P

T2X1M
T2X1P

T2X2M
T2X2P

T2X3M
T2X3P

T2X4M
T2X4P

T2X5M
T2X5P

C101

100nF_6.3V

C109

100nF_6.3V

DDC1DATA(1,15)

DDC2DATA(16)

DDC4DATA
DDC4CLK

GPU_DMINUS(18)
GPU_DPLUS(18)

TS_FDO(18)

D D

+1.8V

B102

BLM15BD121SN1

Q100

SI2304DS

1

+3.3V

TR40

4.7K

402 402

BUO BUO

I2C DEVICE ADDRESS

DEVICE
LM63
ADS1112

XTALOUT_S

C80
100nF_6.3V

32

TR41

4.7K

XTALOUT_S
is done for
ease of layout

C C

LVT_EN(13)

DDC4DATA(13)

DDC4CLK(13)

B B

TEST_EN_R(1)

+3.3V_BUS

B80
BLM15BD121SN1

C81

1uF_6.3V

A A

T2XCM(15)
T2XCP(15)

T2X0M(15)

T2X0P(15)

T2X1M(15)

T2X1P(15)

T2X2M(15)

T2X2P(15)

T2X3M(15)

T2X3P(15)

T2X4M(15)

T2X4P(15)

T2X5M(15)

T2X5P(15)

+T2PVDD

+T2XVDD

B100

26R_600mA
Use 0R

TP41

TP40

ADDRESS
1001 100 (R/W#) --> DDC3
1001 000 (R/W#) --> DDC4 BUO

TR7 0R

DNI

Y81

4

VCC

OUT

2

GND

E/D

27.000MHz

DDC1CLK(1,15)

DDC2CLK(16)

DDC3DATA
DDC3CLK

HPD1(16)

SDA(7)

SCL(7)

PLL_TEST
TEST_EN

4

U1B

Integrated TMDS2

BH35

T2XCM

BF35

T2XCP

BL36

T2X0M

BJ36

T2X0P

BH37

T2X1M

BF37

T2X1P

BL38

T2X2M

BJ38

T2X2P

BH39

T2X3M

BF39

T2X3P

BH41

T2X4M

BF41

T2X4P

BL42

T2X5M

BJ42

T2X5P

BL44

TXOUT_U2N

BJ44

TXOUT_U2P

BL46

TXOUT_U3N

BJ46 BJ30

TXOUT_U3P TXCBP

BJ40

TXCLK_UP

BL40

TXCLK_UN

BE38

LPVDD

BE40

LPVSS

BG34

LVDDC1

BK35

LVDDC2

BL34

LVDDR1

BJ34

LVDDR2

BE36

LVSSR1

BE42

LVSSR2

BL49

LVSSR3

BG36

LVSSR4

BG38

LVSSR5

BG40

LVSSR6

BG42

LVSSR7

BF44

LVSSR8

BK37

LVSSR9

BK39

LVSSR10

BK41

LVSSR11

Monitor Interface

BB45

DDC1DATA

BB47

DDC1CLK

AV36

DDC2DATA

AW36

DDC2CLK

AU32

DDC3DATA

AT32

DDC3CLK

AV35

DDC4DATA

AW35

DDC4CLK

BB29

HPD1

AV27

SDA
SCL

DMINUS
DPLUS
TS_FDO

PLLTEST
TESTEN

VREFG

XTALIN
XTALOUT

RV670 PRO

MMI2C

Thermal
Diode

Test

XTALIN
XTALOUT

VREFG

R82
221R

Share one pad

DNI

MR82
221R

AV29

BC27
BB27
AT21

AU36
AT37

AT20

BF46

BJ49

PART 2 OF 10

V
I
D
E
O

&

M
U
L
T
I
M
E
D
I
A

Integrated TMDS

TXVDDR1
TXVDDR2
TXVDDR3
TXVDDR4

TXVSSR1
TXVSSR2
TXVSSR3
TXVSSR4
TXVSSR5
TXVSSR6
TXVSSR7
TXVSSR8
TXVSSR9

TXVSSR10

DAC / CRT

DAC2 (TV/CRT2)

H2SYNC
V2SYNC

A2VDDQ

A2VSSQ

TXCAM
TXCAP

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TX3M

TX3P

TX4M

TX4P

TX5M

TX5P

TPVDD
TPVSS

TXCBM

HSYNC
VSYNC

RSET
AVDD

AVSSQ

VDD1DI

VSS1DI

COMP

R2SET

VDD2DI

VSS2DI

A2VDD

NC_1
NC_2

NC_3
NC_4
NC_5
NC_6
NC_7

BL26
BJ26

BH27
BF27

BL28
BJ28

BH29
BF29

BH31
BF31

BL32
BJ32

BH33
BF33

BL24
BJ24

BL30

BE26
BF25
BH25
BK25

BE28
BE30
BG26
BG28
BG30
BG32
BK27
BK29
BK31
BK33

BB49

R

BB51

RB

BD49

G

BD51

GB

BF49

B

BF51

BB

BA42
BA43

BB43
BD46
BD44

BA50
BA48

BA39

R2

AY39

R2B

BC39

G2

BB39

G2B

BC37

B2

BB37

B2B

BA36
AY36

AY37

Y

BA37

C

AW37

R2SET GND_A2VSSQ

BA40

BC42
BB41

BC36
BB36

BC41
BC40

BB40
BB32

BE34
BC33
BC32
BE32

3

R1030 499R

R2030 715R

C2030
10nF

C111
100nF_6.3V

C115
100nF_6.3V

C2021
100nF_6.3V

C2024
10nF

C2031
100nF_6.3V

C1023
10nF

T1XCM
T1XCP

T1X0M
T1X0P

T1X1M
T1X1P

T1X2M
T1X2P

T1X3M
T1X3P

T1X4M
T1X4P

T1X5M
T1X5P

C112
1uF_6.3V

C116
1uF_6.3V

GND_AVSSQRSET

DNI

C2025
100nF_6.3V

C2032
1uF_6.3V

C113
10uF_X6S

C1024
100nF_6.3V

C2022
1uF_6.3V

C2026
1uF_6.3V

GND_VSS2DI

C117
10uF_X6S

C1020
10nF

C1025
1uF_6.3V

A_DAC2_R (16)
A_DAC2_RB (16)

A_DAC2_G (16)
A_DAC2_GB (16)

A_DAC2_B (16)
A_DAC2_BB (16)

HSYNC2 (7,16)
VSYNC2 (7,16)

A_DAC2_Y (17)
A_DAC2_C (17)
A_DAC2_COMP (17)

NS2021 NS_VIA

C2033

4.7uF_6.3V

GND_TPVSS

A_DAC1_R (15)
A_DAC1_RB (15)

A_DAC1_G (15)
A_DAC1_GB (15)

A_DAC1_B (15)
A_DAC1_BB (15)

HSYNC1 (1,7,15)
VSYNC1 (1,7,15)

GND_AVSSQ

C1021
100nF_6.3V

GND_A2VSSQ

NS2020 NS_VIA

+VDD2DI

12

Place close to ASIC
DNI

R116 182R

R110 182R

R111 182R

R112 182R

R113 182R

R114 182R

R115 182R

+TPVDD

NS110
NS_VIA

12

+TXVDDR

+AVDD

C1022
1uF_6.3V

+VDD1DI

NS1021NS_VIA

GND_VSS1DI

+A2VDDQ

12

GND_A2VSSQ

+A2VDD

NS1020 NS_VIA

GND_AVSSQ

12

2

T1XCM (16)
T1XCP (16)

T1X0M (16)
T1X0P (16)

T1X1M (16)
T1X1P (16)

T1X2M (16)
T1X2P (16)

T1X3M (16)
T1X3P (16)

T1X4M (16)
T1X4P (16)

T1X5M (16)
T1X5P (16)

B112

BLM15BD121SN1

B110

26R_600mA

B1020

BLM15BD121SN1

12

BLM15BD121SN1

B2020

BLM15BD121SN1

B2021

BLM15BD121SN1

B2030

BLM15BD121SN1

1

+1.8V

B1021

+3.3V

C82

12pF_50V

C83

12pF_50V

2 1
Y82

27.000MHz_10PPM

XTALIN_S

R84

XTALOUT_S

1M

MR86 0R

For Crystal: Adjust C82, C83, R81

5

XTALOUT

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

Title

3

2

RH RV670 - ASIC MAIN

Advanced Micro Devices Inc.
1 Commerce Valley Drive East
Markham, Ontario

Friday, September 07, 2007

Sheet

3 21

of

1

Doc No.

RevDate:

2

105-B340xx-00

C151
1uF_6.3V

C133
1uF_6.3V

C141
1uF_6.3V

C981
1uF_6.3V

C961
1uF_6.3V

C972
100nF_6.3V

MC955

4.7uF_6.3V

C955
10uF_X6S

BLM15BD121SN1

B94

BLM15BD121SN1

B69

BLM15BD121SN1

NS70NS_VIA

1 2

GND_PVSS

B60
BLM15BD121SN1

5

C152
1uF_6.3V

C135
1uF_6.3V

C142
1uF_6.3V

C982
1uF_6.3V

C962
1uF_6.3V

C973
100nF_6.3V

C956
10uF_X6S

C121
1uF_6.3V

Use 0R

MB67

220R_2A

B67

220R_2A
NS64NS_VIA

1 2

GND_MPVSS

5

C153
1uF_6.3V

C143
1uF_6.3V

C963
1uF_6.3V

MC956

4.7uF_6.3V

C958
10uF_X6S

NS122 NS_VIA

1 2

GND_VSSRHC

+DPLL_PVDD

DNI

GND_MPVSS

GND_MPVSS

C136
1uF_6.3V

C983
1uF_6.3V

C964
1uF_6.3V

C974
100nF_6.3V

+3.3V

+DPLL_VDDC

GND_PVSS

C155

C156

C154

1uF_6.3V

1uF_6.3V

C138

C139

1uF_6.3V

1uF_6.3V

C145

C144
1uF_6.3V

MC958

4.7uF_6.3V

C959
10uF_X6S

+MPVDD

C146

1uF_6.3V

1uF_6.3V

C984

C985

1uF_6.3V

1uF_6.3V

C965

C966

1uF_6.3V

1uF_6.3V

C130
100nF_6.3V

MC959

4.7uF_6.3V C940

C126
10uF_X6S

NS123NS_VIA

1 2

GND_VSSRHD

C91
100nF_6.3V

+VDDR_DVP

C94
10uF_X6S

C60

C68

10uF_X6S

1uF_6.3V

C62
10uF_X6S

C67

10uF_X6S

1uF_6.3V

C975
1uF_6.3V

C147
1uF_6.3V

C986
1uF_6.3V

C967
1uF_6.3V

C134

C131

100nF_6.3V

100nF_6.3V

MC126

4.7uF_6.3V

C127
10uF_X6S

C120

1uF_6.3V

NS120 NS_VIA

1 2
GND_VSSRHA

C122
1uF_6.3V

C123
1uF_6.3V

C92
100nF_6.3V

C69
100nF_6.3V

C64

C61

10nF

100nF_6.3V

C66

1uF_6.3V

C157
1uF_6.3V

C976
1uF_6.3V

C148
1uF_6.3V

C987
1uF_6.3V

C968
1uF_6.3V

MC127

4.7uF_6.3V

Overlapped Footprints

C128
10uF_X6S

C93
100nF_6.3V

C95
1uF_6.3V

+DPLL_PVDD

GND_PVSS

C63
1uF_6.3V

C65

100nF_6.3V

+MVDD

C150
1uF_6.3V

C132
1uF_6.3V

D D

C C

B B

A A

C140
1uF_6.3V

C980
1uF_6.3V

C960
1uF_6.3V

C971
100nF_6.3V

MC954

4.7uF_6.3V

10uF_X6S

+MVDD

B120

B121

BLM15BD121SN1

NS121 NS_VIA

1 2

GND_VSSRHB

B122

BLM15BD121SN1

B123

BLM15BD121SN1

+1.8V

+1.1V

+VDDCI_LDO

+VDDC

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK

4.7uF , X6S/X5R, 0603, 6.3V
1uF, X6S, 0402, 6.3V
100nF, X7R, 0402
10nF , X7R, 0402

C158
1uF_6.3V

C977
1uF_6.3V

C149
1uF_6.3V

C988
1uF_6.3V

C969
1uF_6.3V

C137
100nF_6.3V

MC128

4.7uF_6.3V

C97
100nF_6.3V

+DPLL_VDDC

+MPVDD

C159
1uF_6.3V

C989
1uF_6.3V

+VDDRHA

+VDDRHB

C96
1uF_6.3V

4

C978
1uF_6.3V

C979
1uF_6.3V

C970
1uF_6.3V

+VDDRHC

+VDDRHD

4

C98
100nF_6.3V

AD15

AA14
AB45
AA40

AD43
AC37
AB10
AE13

AH11
AF15

AL13
AP12

BC14
AU11

BA10

AW14

AT15

AM12
AM11

AT26
AT27
AT29
AT30

BF23
BH23
BK23

BE22
BG22

BA35

BB35

BC35

W15

W12
W11

BJ22

W20
W19

G14
G18
G22
G26
G30
R34
G40
T15
M26

P29

L38

M39

L10
N19
M32
N16
P25
K35

T19
R22
K43
P41
P45
T12
V38
U40

V45

AB7

AF7

AK7
AP7

AV7

V42
V41

L31

L29

T22

T23

Y19

P7

V7

U1G

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34
VDDR1#35
VDDR1#36
VDDR1#37
VDDR1#38
VDDR1#39
VDDR1#40
VDDR1#41
VDDR1#42
VDDR1#43
VDDR1#44
VDDR1#45
VDDR1#46
VDDR1#47
VDDR1#48
VDDR1#49
VDDR1#50
VDDR1#51
VDDR1#52

VDDRHA
VSSRHA

VDDRHB
VSSRHB

VDDRHC
VSSRHC

VDDRHD
VSSRHD

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

VDDR4#1
VDDR4#2
VDDR4#3

VDDR5#1
VDDR5#2
VDDR5#3

DPLL_PVDD

DPLL_PVSS

DPLL_VDDC

MPVDD

MPVSS

NC_15
NC_16
NC_17

RV670 PRO

Part 7 OF 10

Memory I/O

3

C931

C930

C900
1uF_6.3V

C161
1uF_6.3V

C171
1uF_6.3V

1uF_6.3V

C1125
10uF_X6S

MC1125

4.7uF_6.3V

C1102
1uF_6.3V

C1111
1uF_6.3V

C78
100nF_6.3V

C162
1uF_6.3V

C172
1uF_6.3V

C941
1uF_6.3V

C1136
10uF_X6S

MC1136

4.7uF_6.3V

C1103
1uF_6.3V

C1112
1uF_6.3V

C1123
100nF_6.3V

C913
1uF_6.3V

C79
100nF_6.3V

10nF

C920
1uF_6.3V

C901
100nF_6.3V

AY51

PCIE_PVDD

AF36

PCIE_VDDC1

AF37

PCIE_VDDC2

AG36

PCIE_VDDC3

AG37

PCIE_VDDC4

AH36

PCIE_VDDC5

AH37

PCIE_VDDC6

AK36

PCIE_VDDC7

AK37

PCIE_VDDC8

AL36

PCIE_VDDC9

AL37

PCIE_VDDC10

AN36

PCIE_VDDC11

AF38

PCIE_VDDC12

AW40

PCIE_VDDR1

AW41

PCIE_VDDR2

AY41

PCIE_VDDR3

AY42

PCIE_VDDR4

PCI -Ex press

P
O
W
E
R

Core

PCIE_VDDR5
PCIE_VDDR6
PCIE_VDDR7
PCIE_VDDR8

VDDC0
VDDC1
VDDC2
VDDC3
VDDC4
VDDC5
VDDC6
VDDC7
VDDC8

VDDC9
VDDC10
VDDC11
VDDC12
VDDC13
VDDC14
VDDC15
VDDC16
VDDC17
VDDC18
VDDC19
VDDC20
VDDC21
VDDC22
VDDC23
VDDC24
VDDC25
VDDC26
VDDC27
VDDC28
VDDC29
VDDC30
VDDC31
VDDC32
VDDC33
VDDC34
VDDC35
VDDC36
VDDC37
VDDC38
VDDC39
VDDC40
VDDC41
VDDC42
VDDC43
VDDC44
VDDC45
VDDC46
VDDC47
VDDC48
VDDC49
VDDC50
VDDC51
VDDC52
VDDC53
VDDC54
VDDC55
VDDC56
VDDC57
VDDC58
VDDC59
VDDC60
VDDC61
VDDC62
VDDC63
VDDC64
VDDC65
VDDC66
VDDC67
VDDC68
VDDC69
VDDC70
VDDC71
VDDC72
VDDC73
VDDC74

VDDCI1
VDDCI2
VDDCI3
VDDCI4
VDDCI5
VDDCI6
VDDCI7
VDDCI8

VDD_CT1
VDD_CT2
VDD_CT3

AY43
AY45
AY47
BA46

AM19
W26
W28
W31
W33
Y25
Y27
Y30
Y32
AA24
AA26
AA28
AA31
AA33
AB22
AB25
AB27
AB30
AB32
AD21
AD24
AD26
AD28
AD31
AD33
AE20
AE22
AE25
AE27
AE30
AE32
AF19
AF21
AF24
AF26
AF28
AF31
AF33
AG20
AG22
AG25
AG27
AG30
AG32
AH19
AH21
AH24
AH26
AH28
AH31
AH33
AK20
AK22
AK25
AK27
AK30
AK32
AL19
AL21
AL24
AL26
AL28
AL31
AL33
AM22
AM25
AM27
AM30
AM32
AN21
AN24
AN26
AN28
AN31
AN33

W21
W24
Y20
Y22
AA19
AA21
AB20
AD19

BG14
BJ14
BL14

C911
1uF_6.3V

3

C163
1uF_6.3V

C173
1uF_6.3V

C1104
1uF_6.3V

C1114
1uF_6.3V

C77
1uF_6.3V

100nF_6.3V

C921
1uF_6.3V

C902
1uF_6.3V

C946
1uF_6.3V

C1137
10uF_X6SC954

MC1137

4.7uF_6.3V

C180
100nF_6.3V

C914
100nF_6.3V

C164
1uF_6.3V

C174
1uF_6.3V

C1115
1uF_6.3V

C932
10uF_X6S

C922
1uF_6.3V

C903
1uF_6.3V

C165
1uF_6.3V

C175
1uF_6.3V

C1138
10uF_X6S

MC1138

4.7uF_6.3V

Overlapped Footprints

C1107
1uF_6.3V

C1116
1uF_6.3V

C942
100nF_6.3V

C915
100nF_6.3V

+VDD_CT

C76
1uF_6.3V

+PCIE_PVDD

C933
1uF_6.3V

C923
1uF_6.3V

C904
100nF_6.3V

C166
1uF_6.3V

C176
1uF_6.3V

C948
1uF_6.3V

C1139
10uF_X6S

MC1139

4.7uF_6.3V

C1100
1uF_6.3V

C1117
1uF_6.3V

C1113
100nF_6.3V

C918

4.7uF_6.3V

B76

BLM15BD121SN1

+1.8V

2

C949
1uF_6.3V

C1121
1uF_6.3V

2

C924
1uF_6.3V

C905
1uF_6.3V

C167
1uF_6.3V

C177
1uF_6.3V

C182
10uF_X6S

MC182

4.7uF_6.3V

C947
100nF_6.3V

C919
10uF_X6S

B930

+1.8V

BLM15BD121SN1

C925

C926

1uF_6.3V

10uF_X6S

C907

C906

4.7uF_6.3V

1uF_6.3V

C168

C169

C183
10uF_X6S

1uF_6.3V

C186
1uF_6.3V

MC183

4.7uF_6.3V

C1127
1uF_6.3V

C1130
1uF_6.3V

C178
100nF_6.3V

+VDDCI

C170
1uF_6.3V

C1133
1uF_6.3V

C185
1uF_6.3V

C1131
100nF_6.3V

C1110
1uF_6.3V

1uF_6.3V

C179
1uF_6.3V

C1122
1uF_6.3V

See BOM for qualified option

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

Title

RH RV670 - ASIC Power

+PCIE_VDDC

+PCIE_VDDR

C160
1uF_6.3V

MC187

4.7uF_6.3V

C1128
1uF_6.3V

C1132
1uF_6.3V

B920 220R_2A

26R_600mA

C184
1uF_6.3V

MC181

4.7uF_6.3V

+VDDC

C1129
1uF_6.3V

C1134
1uF_6.3V

C943
100nF_6.3V

+VDDCI_LDO
MR910
0R
MR911
0R

B911 220R_2A

B910 220R_2A

1

+1.8V

B900

+VDDC

+VDDC

Advanced Micro Devices Inc.
1 Commerce Valley Drive East
Markham, Ontario

Friday, September 07, 2007

Sheet

4 21

of

1

+1.1V

Doc No.

RevDate:

2

105-B340xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

4

3

2

1

+MVDD

40.2R

402
1%

R292
100R

402
1%

DQA_[63..0](9)

C291
100nF_6.3VR291

C293
100nF_6.3V

C294
10nF

C292
10nF

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MVREFD_A
MVREFS_A

AD38
AD39
AD40
AD41
AC39

AC46
AC43

AD37
AC36

AB47
AB49
AB51
AA46

AA42

W48
W46

R48
R46

M47

K51
K49
L48
K47

K45
H46
H49
H51
A46
C49
C46
U42
R41
R42
R43

L42
K42
N41
F44
E42
C42
A44
A40
C40
E40
F39
B39
C38
A38
E38
C36
B35
F35
A36

U36
V40

Y51
V47

V49
V51
U46
U50
P49
P47

Y43
Y42
P51
N50
N46

J43

J40

U1C

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MVREFDA
MVREFSA

NC_8
NC_9
NC_31
NC_32

RV670 PRO

Part 3 of 10

MEMORY INTERFA C E

A

DDR1 DDR2 DDR3

bidir. strobe

bidir. differenti al stro be

Not used

For DDR2

read strobe

wri te s trobe

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15

DQMAB_0
DQMAB_1
DQMAB_2
DQMAB_3
DQMAB_4
DQMAB_5
DQMAB_6
DQMAB_7

QSA_0

QSA_1

QSA_2

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B

ODTA0
ODTA1

CLKA0
CLKA0B

CKEA0
RASA0B
CASA0B

WEA0B

CSA0B_0
CSA0B_1

CLKA1

CLKA1B

CKEA1
RASA1B
CASA1B

WEA1B

CSA1B_0
CSA1B_1

U38
U39
R37
Y38
AA37
Y37
Y39
Y40
K39
K38
M38
M37
P38
P39
L40
K40

Y49
T47
AC42
M49
F49
P43
F41
D37

AA50
T51
AC41
L46
C51
N43
A42
E36

Y47
T49
AA43
M51
F46
N42
D41
F37

V37
AA41

V43
U43

R38
P37
R40
Y36
AA38

V36

G38
J39

L37
J37
J35
N37
P40

K37

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9

MAA_10
MAA_11

MAA_BA2
MAA_BA0
MAA_BA1

DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

QSAb_0
QSAb_1
QSAb_2
QSAb_3
QSAb_4
QSAb_5
QSAb_6
QSAb_7

CLKA0 (9)
CLKA0b (9)

CLKA1 (9)
CLKA1b (9)

MAA_BA[2..0] (9)

DQMAb_[7..0] (9)

QSA_[7..0] (9)

QSAb_[7..0] (9)

CKEA0 (9)
RASA0b (9)
CASA0b (9)
WEA0b (9)
CSA0b_0 (9)

CKEA1 (9)
RASA1b (9)
CASA1b (9)
WEA1b (9)
CSA1b_0 (9)

MAA_[11..0] (9)

+MVDD

+MVDD

R391

40.2R

402
1%

R392
100R

402
1%

R393

40.2R

402
1%

R394
100R

402
1%

C391
100nF_6.3V

C393
100nF_6.3V

C392
10nF

C394
10nF

D D

C C

B B

+MVDD

R293

40.2R

402
1%

R294
100R

402
1%

MVREFD_B
MVREFS_B

R495

4.7K

DRAM_RST(9,10)

R395

4.7K

DQB_[63..0](9)

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

+MVDD

R295

4.7K

MR295

2.0K

R296

4.7K

DNI

R297

4.7K

BF11
BL12

BJ12

E34
C34
A34
F33
A32
F31
B31
E30
R35
P35
N35
M35
N34
K32
K31

J31
C30
A30
F29
D29
B27
E26
F27
C26
A26
F25
D25
E24
A22
E22
C22
B23
F21
D21
E20
C20
A18
C18
E18
F17
M23
L25

J25
L23
M22
M20

J20
K20
D17
E16
C16
A16
F13
A14
C14
D13
K17
L17
L19

J16

J13
M17
K14
K13

J34
G34

T35
T34

J29
M29

U1D

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

MVREFDB
MVREFSB

DRAM_RST
TEST_MCLK
TEST_YCLK
NC_10

NC_11
NC_33
NC_34

RV670 PRO

Part 4 of 10

MEMORY INTERFACE

DDR1 DDR2

bid ir. strobe

Not used

For DDR2

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8

MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15

DQMBB_0
DQMBB_1
DQMBB_2

B

DQMBB_3
DQMBB_4
DQMBB_5
DQMBB_6
DQMBB_7

DDR3

QSB_0

QSB_1

QSB_2

QSB_3

QSB_4

QSB_5

QSB_6

QSB_7
QSB_0B

read stro be

QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B

bid ir. diff erential strobe

wri te s trobe

ODTB0

ODTB1

CLKB0
CLKB0B

CKEB0
RASB0B
CASB0B

WEB0B

CSB0B_0
CSB0B_1

CLKB1
CLKB1B

CKEB1
RASB1B
CASB1B

WEB1B

CSB1B_0
CSB1B_1

MAB_1

N28

MAB_2

T29

MAB_3

P31

MAB_4

R32

MAB_5

P32

MAB_6

N32

MAB_7

M31

MAB_8

N22

MAB_9

R23

MAB_10

T25

MAB_11

R26
J26

MAB_BA2

R28

MAB_BA0

P26

MAB_BA1

N23

DQMBb_0

C32

DQMBb_1

L34

DQMBb_2

E28

DQMBb_3

C24

DQMBb_4

A20

DQMBb_5

J23

DQMBb_6

E14

DQMBb_7

J17

QSB_0

D33

QSB_1

K34

QSB_2

A28

QSB_3

F23

QSB_4

B19

QSB_5

K23

QSB_6

F15

QSB_7

K16

QSBb_0

E32

QSBb_1

J32

QSBb_2

C28

QSBb_3

A24

QSBb_4

F19

QSBb_5

K22

QSBb_6

B15

QSBb_7

J14

N20
K25

K28

CLKB0 (9)

J28

CLKB0b (9)

K26
T28
P28
R31
T31

L32
J19

CLKB1 (9)

K19

CLKB1b (9)

R25
N17
P20
N26
M25

P17

MAB_0

L28

MAB_[11..0] (9)

MAB_BA[2..0] (9)

DQMBb_[7..0] (9)

QSB_[7..0] (9)

QSBb_[7..0] (9)

CKEB0 (9)
RASB0b (9)
CASB0b (9)
WEB0b (9)
CSB0b_0 (9)

CKEB1 (9)
RASB1b (9)
CASB1b (9)
WEB1b (9)
CSB1b_0 (9)

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

Title

5

4

3

2

RH RV670 - ASIC Memory Interface (Channel A & B)

Advanced Micro Devices Inc.
1 Commerce Valley Drive East
Markham, Ontario

Friday, September 07, 2007

Sheet

5 21

of

1

Doc No.

RevDate:

2

105-B340xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

4

3

2

1

+MVDD

40.2R

402
1%

R492
100R

402
1%

DQC_[63..0](10)

C491
100nF_6.3V

C493
100nF_6.3V

DQC_0
DQC_1
DQC_2
DQC_3
DQC_4
DQC_5
DQC_6
DQC_7
DQC_8
DQC_9
DQC_10
DQC_11
DQC_12
DQC_13
DQC_14
DQC_15
DQC_16
DQC_17
DQC_18
DQC_19
DQC_20
DQC_21
DQC_22
DQC_23
DQC_24
DQC_25
DQC_26
DQC_27
DQC_28
DQC_29
DQC_30
DQC_31
DQC_32
DQC_33
DQC_34
DQC_35
DQC_36
DQC_37
DQC_38
DQC_39
DQC_40
DQC_41
DQC_42
DQC_43
DQC_44
DQC_45
DQC_46
DQC_47
DQC_48
DQC_49
DQC_50
DQC_51
DQC_52
DQC_53
DQC_54
DQC_55
DQC_56
DQC_57
DQC_58
DQC_59
DQC_60
DQC_61
DQC_62
DQC_63

C492
10nFR491

MVREFS_C

C494
10nF R298

243R

AA10
AA11
AE11

AE10

AB16

E12
C12
A12
F11
A10

G10

K12

L12
P11

P10
R11

AA9
AB9
AF9

AE9

AB5
AB3

AB1
AC6
AC2
AD5
AD3
AD1

AF3

AF1
AG6
AG2

G12

R19

P19

R16

A8
F8
C8
C6
A3
F6
F1
H1
H6
K5

J11

L9

P9

K3
K1

L6

L2
N6
N4
P5
P3
P1
R6
T5
R2
V1
V3
U4
V5

W6
W2

Y5
Y3

J12

U1E

DQC_0
DQC_1
DQC_2
DQC_3
DQC_4
DQC_5
DQC_6
DQC_7
DQC_8
DQC_9
DQC_10
DQC_11
DQC_12
DQC_13
DQC_14
DQC_15
DQC_16
DQC_17
DQC_18
DQC_19
DQC_20
DQC_21
DQC_22
DQC_23
DQC_24
DQC_25
DQC_26
DQC_27
DQC_28
DQC_29
DQC_30
DQC_31
DQC_32
DQC_33
DQC_34
DQC_35
DQC_36
DQC_37
DQC_38
DQC_39
DQC_40
DQC_41
DQC_42
DQC_43
DQC_44
DQC_45
DQC_46
DQC_47
DQC_48
DQC_49
DQC_50
DQC_51
DQC_52
DQC_53
DQC_54
DQC_55
DQC_56
DQC_57
DQC_58
DQC_59
DQC_60
DQC_61
DQC_62
DQC_63

MVREFDC
MVREFSC

MEMTEST

NC_12
NC_35
NC_36

RV670 PRO

Part 5 of 10

DDR1 DDR2

bid ir. strobe

Not used

For DDR2

MAC_0
MAC_1
MAC_2
MAC_3
MAC_4
MAC_5
MAC_6
MAC_7
MAC_8

MAC_9
MAC_10
MAC_11
MAC_12
MAC_13
MAC_14
MAC_15

DQMCB_0
DQMCB_1
DQMCB_2

MEMORY INTERFACE

C

DQMCB_3
DQMCB_4
DQMCB_5
DQMCB_6
DQMCB_7

DDR3

QSC_0

QSC_1

QSC_2

QSC_3

QSC_4

QSC_5

QSC_6

QSC_7

read stro be

QSC_0B
QSC_1B
QSC_2B
QSC_3B
QSC_4B
QSC_5B
QSC_6B

bid ir. diff erential strobe

QSC_7B

wri te s trobe

ODTC0

ODTC1

CLKC0
CLKC0B

CKEC0
RASC0B
CASC0B

WEC0B

CSC0B_0
CSC0B_1

CLKC1
CLKC1B

CKEC1
RASC1B
CASC1B

WEC1B

CSC1B_0
CSC1B_1

T13
R13
M13
L16
R17
M11
M14
AB13
AB14
AB12
AA12
V9
W13
W16
AA15

C10
C3
K9
M5
T3
AD11
AA4
AE6

B11
F3
M9
M1
U6
AD10
Y1
AF5

E10
J10
M10
M3
T1
AD9
AA6
AE4

AA16
V16

R9
R10

T10
V12
T9
L14
P16

V14

W9
W10

AD14
AE14
AD12
V11
V10

V15

MAC_1
MAC_2
MAC_3

MAC_4
MAC_5
MAC_6
MAC_7
MAC_8
MAC_9
MAC_10
MAC_11

MAC_BA2
MAC_BA0
MAC_BA1

DQMCb_0
DQMCb_1
DQMCb_2
DQMCb_3
DQMCb_4
DQMCb_5
DQMCb_6
DQMCb_7

QSC_0
QSC_1
QSC_2
QSC_3
QSC_4
QSC_5
QSC_6
QSC_7

QSCb_0
QSCb_1
QSCb_2
QSCb_3
QSCb_4
QSCb_5
QSCb_6
QSCb_7

CLKC0 (10)
CLKC0b (10)

CKEC0 (10)
RASC0b (10)
CASC0b (10)
WEC0b (10)
CSC0b_0 (10)

CLKC1 (10)
CLKC1b (10)

CKEC1 (10)
RASC1b (10)
CASC1b (10)
WEC1b (10)
CSC1b_0 (10)

MAC_0

R14

MAC_[11..0] (10)

MAC_BA[2..0] (10)

DQMCb_[7..0] (10)

QSC_[7..0] (10)

QSCb_[7..0] (10)

+MVDD

R591

40.2R

402
1%

R592
100R

402
1%

+MVDD

R593

40.2R

402
1%

R594
100R

402
1%

C591
100nF_6.3V

C593
100nF_6.3V

C592
10nF

C594
10nF

D D

C C

B B

+MVDD

R493

40.2R

402
1%

R494
100R

402
1%

MVREFD_D
MVREFS_DMVREFD_C

DQD_[63..0](10)

DQD_0
DQD_1
DQD_2
DQD_3
DQD_4
DQD_5
DQD_6
DQD_7
DQD_8
DQD_9
DQD_10
DQD_11
DQD_12
DQD_13
DQD_14
DQD_15
DQD_16
DQD_17
DQD_18
DQD_19
DQD_20
DQD_21
DQD_22
DQD_23
DQD_24
DQD_25
DQD_26
DQD_27
DQD_28
DQD_29
DQD_30
DQD_31
DQD_32
DQD_33
DQD_34
DQD_35
DQD_36
DQD_37
DQD_38
DQD_39
DQD_40
DQD_41
DQD_42
DQD_43
DQD_44
DQD_45
DQD_46
DQD_47
DQD_48
DQD_49
DQD_50
DQD_51
DQD_52
DQD_53
DQD_54
DQD_55
DQD_56
DQD_57
DQD_58
DQD_59
DQD_60
DQD_61
DQD_62
DQD_63

AF11
AF12
AF13
AH12
AM10

AL11
AL10

AT11
AV10

BB10

AW12

BG10

BL10
BH11

BB14
BB15
BC15
BC10
BC11
AY13
BC13
BE12

AF16
AP15
AT14

AM9

AW2

BJ10

AH5
AH3
AH1

AJ6
AK1
AL6
AL2
AM5
AM3
AM1
AN6
AN4
AR6
AR2
AT5
AT3

AT1
AU6
AY1
AY3

AY5
AV5
AU4
BA6
BB5
BA4
BB3
BD1
BD3
BF3

BJ1
AU9

AV9

BA9
BB9

BC9
BF6

BJ3

BJ6

AJ9
AH9

U1F

DQD_0
DQD_1
DQD_2
DQD_3
DQD_4
DQD_5
DQD_6
DQD_7
DQD_8
DQD_9
DQD_10
DQD_11
DQD_12
DQD_13
DQD_14
DQD_15
DQD_16
DQD_17
DQD_18
DQD_19
DQD_20
DQD_21
DQD_22
DQD_23
DQD_24
DQD_25
DQD_26
DQD_27
DQD_28
DQD_29
DQD_30
DQD_31
DQD_32
DQD_33
DQD_34
DQD_35
DQD_36
DQD_37
DQD_38
DQD_39
DQD_40
DQD_41
DQD_42
DQD_43
DQD_44
DQD_45
DQD_46
DQD_47
DQD_48
DQD_49
DQD_50
DQD_51
DQD_52
DQD_53
DQD_54
DQD_55
DQD_56
DQD_57
DQD_58
DQD_59
DQD_60
DQD_61
DQD_62
DQD_63

MVREFDD
MVREFSD

NC_14
NC_37
NC_38

RV670 PRO

Part 6 of 10

DDR1 DDR2

bid ir. strobe

Not used

For DDR2

MAD_0
MAD_1
MAD_2
MAD_3
MAD_4
MAD_5
MAD_6
MAD_7
MAD_8

MAD_9
MAD_10
MAD_11
MAD_12
MAD_13
MAD_14
MAD_15

DQMDB_0
DQMDB_1
DQMDB_2

MEMORY INTERFACE

D

DQMDB_3
DQMDB_4
DQMDB_5
DQMDB_6
DQMDB_7

DDR3

QSD_0

QSD_1

QSD_2

QSD_3

QSD_4

QSD_5

QSD_6

QSD_7

read stro be

QSD_0B
QSD_1B
QSD_2B
QSD_3B
QSD_4B
QSD_5B
QSD_6B

bid ir. diff erential strobe

QSD_7B

wri te s trobe

ODTD0

ODTD1

CLKD0

CLKD0B

CKED0

RASD0B
CASD0B

WED0B

CSD0B_0
CSD0B_1

CLKD1

CLKD1B

CKED1

RASD1B
CASD1B

WED1BNC_13

CSD1B_0
CSD1B_1

AM14
AM13
AL14
AE15
AH15
AJ13
AJ15
AU15
AW15
AV17
AV14
AT13
AR16
AU14
AT17

AK3
AP5
AJ10
AV3
BB1
AY10
BL8
BB11

AJ4
AP1
AJ12
AW6
BD6
AY11
BL6
BB13

AK5
AP3
AJ11
AV1
BB7
AV11
BF8
BA13

AU17
AV12

AP10
AP9

AP13
AT12
AM15
AH14
AF14

AW17

AT10
AT9

BA14
AY15
BA15
AU12AE16
AM16

AL15

MAD_1
MAD_2
MAD_3
MAD_4
MAD_5
MAD_6
MAD_7
MAD_8
MAD_9
MAD_10
MAD_11

MAD_BA2
MAD_BA0
MAD_BA1

DQMDb_0
DQMDb_1
DQMDb_2
DQMDb_3
DQMDb_4
DQMDb_5
DQMDb_6
DQMDb_7

QSD_0
QSD_1
QSD_2
QSD_3
QSD_4
QSD_5
QSD_6
QSD_7

QSDb_0
QSDb_1
QSDb_2
QSDb_3
QSDb_4
QSDb_5
QSDb_6
QSDb_7

CLKD0 (10)
CLKD0b (10)

CKED0 (10)
RASD0b (10)
CASD0b (10)
WED0b (10)
CSD0b_0 (10)

CLKD1 (10)
CLKD1b (10)

CKED1 (10)
RASD1b (10)
CASD1b (10)
WED1b (10)
CSD1b_0 (10)

MAD_0

AJ16

MAD_[11..0] (10)

MAD_BA[2..0] (10)

DQMDb_[7..0] (10)

QSD_[7..0] (10)

QSDb_[7..0] (10)

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

Title

5

4

3

2

RH RV670 - ASIC Memory Interface (Channel C & D)

Advanced Micro Devices Inc.
1 Commerce Valley Drive East
Markham, Ontario

Friday, September 07, 2007

Sheet

6 21

of

1

Doc No.

RevDate:

2

105-B340xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn

5

U1J

Part 10 OF 10

VID_0

BA33
AY33

AW33

AV33
BA32
AY32

AW32

BA30
BB30

AV30

AW30

BC29
BC30

BF15

BG20

BK15
BB20
BC20

BH15

BG16

BL16
BH17
BF17
BL18

BG18

BK19
BH19
BF19
AY21
BA21
BC21
BB18
BC18
BC17
BK21
BH21
BF21
BL22
AY20
BA20

BJ20

BJ16

BJ18

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7

VPCLK0

VHAD_0
VHAD_1

VPHCTL
VIPCLK

DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_MVP_0
DVPCNTL_MVP_1

DVO
Port

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

RV670 PRO

VIP
Capture

VIP
Host

General
Purpose
I/O

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_14_HPD2

GPIO_15_PWRCNTL_0

GPIO_16_SSIN

GPIO_17_THERMAL_INT

GPIO_18_HPD3

GPIO_19_CTF

GPIO_20_PWRCNTL_1

GPIO_22_ROMCSB

GPIO_23_CLKREQB

GPIO_24_TRST

GPIO_25_TDI

GPIO_26_TCK
GPIO_27_TMS
GPIO_28_TDO

GENERICA
GENERICB
GENERICC

RESERVED

VARY_BL

No
Connect

35mil

35mil
35mil
35mil
35mil
35mil

DVP_MVP_CNTL_0

35mil

DVP_MVP_CNTL_1

35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil
35mil

VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7

DVOCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

VID_1(13)
VID_2(13)
VID_3(13)

For MVDD Setting
(TBD)

D D

CrossFire

DVP_MVP_CNTL_0 : DE for bits D[12..23]
DVP_MVP_CNTL_1 : CLK for bits D[12..23]

C C

B B

TP90

TP84
TP85
TP86
TP87
TP88
TP89

TP60
TP61
TP62
TP63
TP64
TP65
TP66
TP67
TP68
TP69
TP70
TP71
TP72
TP73
TP74
TP75
TP76
TP77
TP78
TP79
TP80
TP81
TP82
TP83

CrossFire Card-Edge

Lower Cable Card Edge

1

DVOCLK
DVPCNTL_2
DVPDATA_1
DVPDATA_3
DVPDATA_5
DVPDATA_7
DVPDATA_9
DVPDATA_11
DVPCNTL_1

A A

GPIO_3

3
5
7

9
11
13
15
17
19
21
23
25
27
29 30
31
33
35
37
39

J8002

2
4
6
8

DVPDATA_0

10
12

DVPDATA_2

14
16

DVPDATA_4

18
20

DVPDATA_6

22
24

DVPDATA_8

26
28

DVPDATA_10

32

DVPCNTL_0

34
36

GPIO_5

38
40

Bundle B

5

Upper Cable Card Edge

DVP_MVP_CNTL_1
DVP_MVP_CNTL_0
DVPDATA_13
DVPDATA_15
DVPDATA_17
DVPDATA_19
DVPDATA_21
DVPDATA_23
GENERICB_R
GPIO_4

Bundle A (closer to the bracket)

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6

GPIO_11
GPIO_12
GPIO_13

GPIO_21

DVALID
PSYNC

DIGON

NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29 30
31
33
35
37
39

J8001

AV18
AU18
AV20
AW18
BB17
BA18
AY24
AU20
AW21
AV21
AU21
BA23
AY23
AW23
AV23
AU23
BB24
AY18
BA17
BH13
BF13
BC24
AW24
AV24
AU24
AY26
AW26
AV26
AW27

BC26
BB23
BB26

BC23
AY29

AW29
AU29

AM20
AN20
AT23
BA26
AU35
AU33
AT33
BA29
AY27
AT24
AU27
AU30
BG24

2
4
6
8
10
12
14
16
18
20
22
24
26
28

32
34
36
38
40

4

GPIO_0
GPIO_1GPIO_1
GPIO_2GPIO_2

GPIO_7GPIO_7
GPIO_8GPIO_8
GPIO_9GPIO_9
GPIO_10GPIO_10
GPIO_11GPIO_11
GPIO_12GPIO_12
GPIO_13GPIO_13

HPD2HPD2
GPIO_15_PWRCNTL_0
EXT_12V_DETb
GPIO_17_INT
GPIO_18
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSb
PCIE_CLK_REQb
JTAG_MODE
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

GENERICA
GENERICB
GENERICC

DVALIDDVALID
PSYNCPSYNC

DVPDATA_12
DVPDATA_14
DVPDATA_16
DVPDATA_18
DVPDATA_20
DVPDATA_22
DVALID_R
GPIO_6

4

CrossFire

FLOW_CONTROL_1 - Lower Cable

GPIO_3

FLOW_CONTROL_2 - Upper Cable

GPIO_4

SWAP_LOCK_1 - Lower Cable

GPIO_5

SWAP_LOCK_2 - Upper Cable

GPIO_6

Place it at top edge of the
board on the bottom side.

+3.3V
TC47
100nF_6.3V

In production, this block
will not be populated.

Mating connector: 6010028300G
(HEADER 2X8 1.27MM PITCH, SMD)
When attaching the daughter card (B176) align it by mounting hole.

RP60A33R

81

RP60B33R

72

RP60C33R

63

RP60D33R

54

HPD2 (15)

EXT_12V_DET (13)

GPIO_19_CTF (13)

R5
1K

TR57 0R

DNI

R8001 0R

DNI

R8002 0R

GENERICB: Generic I2C_SDA
DVALID: Generic I2C_SCL

GPIO_8_R
GPIO_9_R
GPIO_10_R
ROMCSb_R

DNI

JTAG_MODE

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO

DVALID
GENERICB

BUO
TJ47

1
3
5
7

9
11
13
15

2X8SOCKET

GENERICA (17)

3

Place SW1 & SW2 on the bottom side
(easily accessible).
Clearly Mark A & B contacts on the
silkscreen.

R64

0R

MR64

0R

GPIOs for VDDC Setting

GPIO_15_PWRCNTL_0 (13)

GPIO_18 (13)
GPIO_20_PWRCNTL_1 (13)

GPIO_21 (13)

TP47

TP46

35mil

35mil

For wire soldering
EXT_ADJ_1.8V

2

GPIO_8_T

4

ROMCSb_T

6

GPIO_9_T

8

GPIO_10_T

10

SDA

12

SCL

14
16

3

ThermINT (18)

HOT_PLUG_DET (13)

+3.3V

Place TRP61 & TR57 in a way
to minimize the stub when
they are not populated.

TRP61C33R

63

TRP61D33R

54

TRP61B33R

72

TRP61A33R

81

TR50
10K

35mil

GPIO_8_R
ROMCSb_R
GPIO_9_R
GPIO_10_R

TP50

100nF_6.3V

TC46

DNI

DNI

TBD

DNI

MR50 10K

MR51 10K

MR52 10K
MR53 10K

MR54 10K

NR55 1K
MR55 10K

MR56 10K

MR58 10K
MR59 10K
MR63 10K
MR62 10K
MR61 10K

MR65 10K

MR66 10K

MR67 10K

MR68 10K

MR70 10K

MR71 10K

MR72 10K

MR73 10K

MR74 10K

MR75 10K

MR76 10K

MR77 10K

MR78 10K
MR79 10K

MR60 10K

+3.3V+5V

TR48

TR47

4.7K

4.7K
BUOBUO

2

+3.3V

DNI

DNI

BUO

TBD

TBD

DNI

BUO

NTSC

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

R50 10K

R51 10K

R52 10K
R53 10K

R541K

R55 10K
VR55 1K

R56 10K
NR56 1K

R57 10K
R58 10K
R59 10K
R63 10K
R62 10K
R61 10K

R65 10K

R66 10K

R67 10K

R68 10K

R70 10K

R71 10K

R72 10K

R73 10K

R74 10K

R75 10K

R76 10K

R77 10K

R78 10K
R79 10K

R60 10K

PIN BASED STRAPS

GPIO_0

GPIO_1

GPIO_2

GPIO_2
GPIO_3

GPIO_3

SW2B

BUO

DIP_SWX2

GPIO_5

SW2A

BUO

DIP_SWX2

GPIO_6

BUO

SW1B

GPIO_7GPIO_7
GPIO_8_R

DIP_SWX2

GPIO_9_R

CONFIG[3]

GPIO_13

GPIO_13

CONFIG[2]

GPIO_12

GPIO_12

CONFIG[1]

GPIO_11GPIO_11

GPIO_11GPIO_11

CONFIG[0]

GENERICC

VSYNC1 (1,3,15)

VSYNC1

VSYNC1

HSYNC1 (1,3,15)

HSYNC1

PSYNC

PSYNC

VID_0

VID_0

VID_1

VID_1

VID_2

VID_2

VID_3

VID_3

VID_4

VID_4

VID_5

VID_5

VID_6

VID_6

VID_7

VID_7

VSYNC2 (3,16)

VSYNC2

VSYNC2

HSYNC2 (3,16)

HSYNC2

HSYNC2

DVALID

DVALID

41

41

32

SW1A
DIP_SWX2

BUO

32

GPIO_4

Pull-Down Resistors are for BU until built-in pull-downs are verified.

Note: GPIO_21 is also pin strap and must not have pull-up (Default 0). See data book for details

GPIO_22_ROMCSb is pulled high by R46

SDA (3)
SCL (3)

R46
10K

ROMCSb_R
GPIO_8_R

PN 2280007900G for 1Mbit (PM25LV010A-100SCE)

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
?2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

Title

2

RH RV670 - ASIC DVO, VIP & GPIOs

GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)

0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)

0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)

AMD Internal Use Only - Reserved (Default: 00)

DEBUG_ACCESS
AMD Internal Use Only - Reserved (Default: 0)

AMD Board Feature III - Reserved (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

GPIO(9,13, 12,11) - CONFIG[3..0]

0010 - 512Kbit AT25F512A (Atmel)
0011 - 1Mbit AT25F1024A (Atmel)
0100 - 512Kbit M25P05A (ST)
0101 - 1Mbit M25P10A (ST)
0101 - 2Mbit M25P20 (ST)
0100 - 512Kbit Pm25LV512 (Chingis)
0101 - 1Mbit Pm25LV010 (Chingis)

AMD Internal Use Only - Reserved (Default: 0)

VIP_DEVICE_STRAP_EN

0: Slave VIP host port devices present (use if Theater is populated)
1: No slave VIP host port devices reporting presence during reset (use for
configurations without video-in)

AMD Board Feature II - (Default 0)

VGA DISABLE : 1 for disable (set to 0 for normal operation)

AMD Internal Use Only - Reserved (Default: 0)

MSI_DIS (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

AMD Board Feature III - (Default 0)

AMD Internal Use Only - Reserved (Default: 0)

64BAR_EN_A (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

AMD Internal Use Only - Reserved for memory strap

AMD Internal Use Only - Reserved

BIF_CLK_PM_EN (Default 0)
0 - Disable CLKREQ# power management capability
1 - Enable CLKREQ# power management capability

+3.3V

U2
1
2
3
4 5

PM25LV512A-100SCE

CE#
SO

HOLD#
WP#
GND SI

8

VCC

7
6

SCK

Sheet

Advanced Micro Devices Inc.
1 Commerce Valley Drive East
Markham, Ontario

Saturday, September 08, 2007

7 21

GPIO_10_R
GPIO_9_R

of

1

Default: 0

C47
100nF_6.3V

1

1 - NTSC TVO0 - PAL TVO TV OUT STANDARD

BIOS1

BIOS

113-B339XX-XXX
VIDEO BIOS
FIRMWARE

Doc No.

AMD PCIE FEATURE I

AMD PCIE FEATURE II

RevDate:

2

105-B340xx-00

PDF created with pdfFactory Pro trial version www.pdffactory.com

www.vinafix.vn