MSI MS-V110 Schematic 20

8

Share pad

TEST_EN

TEST_EN(3)

D D

JTAG_MODE(3)

+12V_BUS

C C

B B

+12V_BUS

+3.3V_BUS

+3.3V_BUS

C1
10UFC110UF

C2
150nF_16VC2150nF_16V

C4
10uFC410uF

C5
1uF_6.3VC51uF_6.3V

Place these caps last,
ideally as close to the bus
connector as possible

JTAG_MODE JMODE
JTAG_TRST#

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

+12V_BUS

C3

C3
150nF_16V

150nF_16V

LF CAP CER 150NF 10% 16V X7R (0603)

LF CAP CER 150NF 10% 16V X7R (0603)

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

C6
1uF_6.3VC61uF_6.3V

Share pad

MR51KMR5
1K

C0
10nFC010nF

7

+3.3V

1K
NR71KNR7

DNI

1K

R71KR7

MR71KMR7

DNI

1K

+3.3V

DNI

R51KR5

NR51KNR5

1K

1K

TP6TP6

TP5TP5

PETp10_GFXRp10(2)
PETn10_GFXRn10(2)

PETp11_GFXRp11(2)
PETn11_GFXRn11(2)

PETp12_GFXRp12(2)
PETn12_GFXRn12(2)

PETp13_GFXRp13(2)
PETn13_GFXRn13(2)

PETp14_GFXRp14(2)
PETn14_GFXRn14(2)

PETp15_GFXRp15(2)
PETn15_GFXRn15(2)

PETn0_GFXRn0(2)

PETp1_GFXRp1(2)
PETn1_GFXRn1(2)

PETp2_GFXRp2(2)
PETn2_GFXRn2(2)

PETp3_GFXRp3(2)
PETn3_GFXRn3(2)

PETp4_GFXRp4(2)
PETn4_GFXRn4(2)

PETp5_GFXRp5(2)
PETn5_GFXRn5(2)

PETp6_GFXRp6(2)
PETn6_GFXRn6(2)

PETp7_GFXRp7(2)
PETn7_GFXRn7(2)

PETp8_GFXRp8(2)
PETn8_GFXRn8(2)

PETp9_GFXRp9(2)
PETn9_GFXRn9(2)

R4 0RR4 0R

6

JTRST#

PRESENCE

5

4

PCI-EXPRESS EDGE CONNECTOR

+12V_BUS+3.3V_BUS +3.3V_BUS+12V_BUS

x16 PCIe

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

+12V#B1
+12V#B2
+12V#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1

3.3Vaux
WAKE#

RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82

Mechanical Key

Mechanical Key

x16 PCIe

PRSNT1#A1

+12V#A2
+12V#A3
GND#A4

JTAG2
JTAG3
JTAG4
JTAG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12
REFCLK+
REFCLK­GND#A15

PERp0
PERn0

GND#A18

RSVD#A19

GND#A20

PERp1

PERn1
GND#A23
GND#A24

PERp2

PERn2
GND#A27
GND#A28

PERp3

PERn3
GND#A31

RSVD#A32
RSVD#A33

GND#A34

PERp4

PERn4
GND#A37
GND#A38

PERp5

PERn5
GND#A41
GND#A42

PERp6

PERn6
GND#A45
GND#A46

PERp7

PERn7
GND#A49

RSVD#A50

GND#A51

PERp8

PERn8
GND#A54
GND#A55

PERp9

PERn9
GND#A58
GND#A59

PERp10

PERn10
GND#A62
GND#A63

PERp11

PERn11
GND#A66
GND#A67

PERp12

PERn12
GND#A70
GND#A71

PERp13

PERn13
GND#A74
GND#A75

PERp14

PERn14
GND#A78
GND#A79

PERp15

PERn15
GND#A82

MPCIE1

MPCIE1

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

PERp0
PERn0

PERp1
PERn1

PERp2
PERn2

PERp3
PERn3

PERp4
PERn4

PERp5
PERn5

PERp6
PERn6

PERp7
PERn7

PERp8
PERn8

PERp9
PERn9

PERp10
PERn10

PERp11
PERn11

PERp12
PERn12

PERp13
PERn13

PERp14
PERn14

PERp15
PERn15

PRESENCE

JTCK
JTDI
JTDO
JTMS

C7
100nFC7100nF

C9
100nFC9100nF

C11

C11
100nF

100nF

C13

C13
100nF

100nF

C15

C15
100nF

100nF

C17

C17
100nF

100nF

C19

C19
100nF

100nF

C21

C21
100nF

100nF

C23

C23
100nF

100nF

C25

C25
100nF

100nF

C27

C27
100nF

100nF

C29

C29
100nF

100nF

C31

C31
100nF

100nF

C33

C33
100nF

100nF

C35

C35
100nF

100nF

C37

C37
100nF

100nF

C8
100nFC8100nF

C10

C10
100nF

100nF

C12

C12
100nF

100nF

C14

C14
100nF

100nF

C16

C16
100nF

100nF

C18

C18
100nF

100nF

C20

C20
100nF

100nF

C22

C22
100nF

100nF

C24

C24
100nF

100nF

C26

C26
100nF

100nF

C28

C28
100nF

100nF

C30

C30
100nF

100nF

C32

C32
100nF

100nF

C34

C34
100nF

100nF

C36

C36
100nF

100nF

C38

C38
100nF

100nF

3

PCIE_REFCLKP (2)
PCIE_REFCLKN (2)PETp0_GFXRp0(2)

GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)

GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)

GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)

GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)

GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)

GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)

GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)

GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)

GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)

GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)

GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)

GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)

GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)

GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)

GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)

GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)

2

53

1
2

R_RST

R3 0RR3 0R

+3.3V

TP2TP2

TP3TP3

TP1TP1

TP4TP4

PERST#

C39

C39
100nF

100nF

4

U5

U5
NC7SZ08P5X_NL

NC7SZ08P5X_NL

1

PERST#_buf (2)

Place R3 in U5

+12V_BUS+3.3V_BUS +12V_BUS

DNI

R857

R857

4.7K

4.7K

402

Node 1

5%

R8590RR859

Q850

Q850

1

MMBT3904

MMBT3904

0R

DNI

402

2 3

Q851

Q851

1

MMBT3904

MMBT3904

2 3

DNI

DNI

DNI

Q852

Q852

1

MMBT3904

MMBT3904

2 3

DNI

7

R850

R850
475R

475R

402
1%

DNI

R852

R852

1.62K

1.62K

402
1%

DNI

VMON2

Node 3

A A

DNI

R851

R851
200R

200R

402
1%

8

Node 2

R853

R853
200R

200R

402
1%

VMON1

R839 0RR839 0R

DNI

Power Sequence Circuit to ensure SMPS_EN is released after
+12V_BUS and +3.3V_BUS are both in regulation.

VDD_EN (8,16)

When +12V_BUS ramps above min Vbe, SMPS_EN will be held low

Node 1

When +3.3V_BUS gets close to regulation, one of the two

Node 2

conditions of releasing SMPS_EN is active
Target ~ 900mV when +3.3 at min regulation (worse case)

Typical trigger when +3.3V ramps above 2.2V (650mV)

Node 3 When +12V gets close to regulation, one of the two

conditions of releasing SMPS_EN is active
Target ~ 1.25V when +12 at min regulation (worse case)

Typical trigger when +12V ramps above 10V (1.1V)

6

5

www.vinafix.vn

SYMBOL LEGEND

DNI

DO NOT
INSTALL

#

ACTIVE
LOW

DIGITAL
GROUND

ANALOG
GROUND

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

4

3

Date: Sheet

2

105-B170xx-00

105-B170xx-00

105-B170xx-00

21

21

21

of

of

of

119Saturday, April 28, 2007

119Saturday, April 28, 2007

119Saturday, April 28, 2007

1

5

D D

4

3

2

1

NOTE: some of the PCIE testpoints will
be available trought via on traces.

PETp0_GFXRp0(1)
PETn0_GFXRn0(1)

PETp1_GFXRp1(1)
PETn1_GFXRn1(1)

PETp2_GFXRp2(1)
PETn2_GFXRn2(1)

PETp3_GFXRp3(1)
PETn3_GFXRn3(1)

PETp4_GFXRp4(1)
PETn4_GFXRn4(1)

PETp5_GFXRp5(1)
PETn5_GFXRn5(1)

PETp6_GFXRp6(1)

C C

B B

PETn6_GFXRn6(1)

PETp7_GFXRp7(1)
PETn7_GFXRn7(1)

PETp8_GFXRp8(1)
PETn8_GFXRn8(1)

PETp9_GFXRp9(1)
PETn9_GFXRn9(1)

PETp10_GFXRp10(1)
PETn10_GFXRn10(1)

PETp11_GFXRp11(1)
PETn11_GFXRn11(1)

PETp12_GFXRp12(1)
PETn12_GFXRn12(1)

PETp13_GFXRp13(1)
PETn13_GFXRn13(1)

PETp14_GFXRp14(1)
PETn14_GFXRn14(1)

PETp15_GFXRp15(1)
PETn15_GFXRn15(1)

PCIE_REFCLKP(1)
PCIE_REFCLKN(1)

DNI DNI

R13

R13
51R

51R

402 402

R14

R14
51R

51R

TP11TP11

TP12TP12

TP13TP13

TP14TP14

TP19TP19

TP20TP20

TP21TP21

TP22TP22

TP27TP27

TP28TP28

TP7TP7

TP8TP8

TP9TP9

TP10TP10

TP15TP15

TP16TP16

TP17TP17

TP18TP18

TP23TP23

TP24TP24

TP25TP25

TP26TP26

PERST#_buf(1)

U1A

U1A

AC30

PCIE_RX0P

AC31

PCIE_RX0N

AC29

PCIE_RX1P

AB29

PCIE_RX1N

AB31

PCIE_RX2P

AB30

PCIE_RX2N

AA31

PCIE_RX3P

AA30

PCIE_RX3N

W30

PCIE_RX4P

W31

PCIE_RX4N

W29

PCIE_RX5P

V29

PCIE_RX5N

V31

PCIE_RX6P

V30

PCIE_RX6N

U31

PCIE_RX7P

U30

PCIE_RX7N

P30

PCIE_RX8P

P31

PCIE_RX8N

P29

PCIE_RX9P

N29

PCIE_RX9N

N31

PCIE_RX10P

N30

PCIE_RX10N

M31

PCIE_RX11P

M30

PCIE_RX11N

K30

PCIE_RX12P

K31

PCIE_RX12N

K29

PCIE_RX13P

J29

PCIE_RX13N

J31

PCIE_RX14P

J30

PCIE_RX14N

H31

PCIE_RX15P

H30

PCIE_RX15N

AD29

PCIE_REFCLKP

AD30

PCIE_REFCLKN

AC28

RSVD_1

AC27

RSVD_2

AG25

PERSTB

RV610 UNFUSED A11 RH

RV610 UNFUSED A11 RH

Clock

Clock

PART 1 OF 6

PART 1 OF 6

P

P
C

C
I

I

-

­E

E
X

X
P

P
R

R
E

E
S

S
S

S

I

I
N

N
T

T
E

E
R

R
F

F
A

A
C

C
E

E

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

Calibration

Calibration

PCIE_CALRN
PCIE_CALRP

PCIE_CALI

AA28
AA27

AA25
AA24

Y28
Y27

Y25
Y24

V28
V27

V25
V24

T28
T27

T25
T24

P28
P27

P25
P24

M28
M27

M25
M24

L28
L27

L25
L24

J28
J27

G28
G27

AF25
AE25
AE23

GFXTp0_PERp0 (1)
GFXTn0_PERn0 (1)

GFXTp1_PERp1 (1)
GFXTn1_PERn1 (1)

GFXTp2_PERp2 (1)
GFXTn2_PERn2 (1)

GFXTp3_PERp3 (1)
GFXTn3_PERn3 (1)

GFXTp4_PERp4 (1)
GFXTn4_PERn4 (1)

GFXTp5_PERp5 (1)
GFXTn5_PERn5 (1)

GFXTp6_PERp6 (1)
GFXTn6_PERn6 (1)

GFXTp7_PERp7 (1)
GFXTn7_PERn7 (1)

GFXTp8_PERp8 (1)
GFXTn8_PERn8 (1)

GFXTp9_PERp9 (1)
GFXTn9_PERn9 (1)

GFXTp10_PERp10 (1)
GFXTn10_PERn10 (1)

GFXTp11_PERp11 (1)
GFXTn11_PERn11 (1)

GFXTp12_PERp12 (1)
GFXTn12_PERn12 (1)

GFXTp13_PERp13 (1)
GFXTn13_PERn13 (1)

GFXTp14_PERp14 (1)
GFXTn14_PERn14 (1)

GFXTp15_PERp15 (1)

+PCIE_VDDC

402

R82.0K R82.0K

402

R91.27K R91.27K

402

R1010K R1010K

GFXTn15_PERn15 (1)

For Tektronix LA only

Place close
to ASIC

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

5

4

www.vinafix.vn

3

2

Date: Sheet

105-B170xx-00

105-B170xx-00

105-B170xx-00

1

21

21

21

of

of

of

219Saturday, April 28, 2007

219Saturday, April 28, 2007

219Saturday, April 28, 2007

5

VID_[7..0](12)

D D

PLACE TOGETHER

C C

GPIO_[13..0](12)

TP57TP57

C70

C70
10nF

10nF

GND_PVSS

BLM15BD121SN1

BLM15BD121SN1

MB60

MB60

BLM15BD121SN1

BLM15BD121SN1

B60

B60

+VDDC

PWRCNTL_0(10,12)

PWRCNTL_1(10)

C71

C71
100nF

100nF

ThermINT(16)

C931

C931
100nF

100nF

CTFb(16)

C72

C72
10uF_X6S

10uF_X6S

+PCIE_PVDD

C932

C932
10uF_X6S

10uF_X6S

NS64 NS_VIANS64 NS_VIA

1 2

B67 60RB67 60R

GPIO_16 IS OUT ONLY

+DPLL_PVDD

B B

NS70 NS_VIANS70 NS_VIA

1 2

+1.8V_D2

B931

B931

BLM15BD121SN1

BLM15BD121SN1

NS18NS_VIA NS18NS_VIA

1 2

GND_PCIE_PVSS

Note: Verify +MPVDD ripple
is within specification.
(C76 changed from 10uF to 1uF)

+1.1V

+VDDC

Share Pad

A A

+3.3V_BUS

B80

B80
BLM15BD121SN1

BLM15BD121SN1

C81

C81

1uF_6.3V

1uF_6.3V

XTALOUT_S

C80

C80
100nF

100nF

XTALOUT_S
is done for
ease of layout

4
2

5

Y81

Y81

VCC
GND

27.000MHz

27.000MHz

TP47TP47

+3.3V

C933

C933
1uF_6.3V

1uF_6.3V

+MPVDD

GND_MPVSS

OUT

E/D

+3.3V

TP48TP48

TP54TP54

+DPLL_PVDD

GND_PVSS

XTALIN_S

3

OSC_EN

1

TP50TP50

C76

C76
1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C63

C63
10uF_X6S

10uF_X6S

+3.3V

R47

R47

R48

R48

4.7K

4.7K

4.7K

4.7K

FLOW_CONTROL_1 - Lower Cable
FLOW_CONTROL_2 - Upper Cable
SWAP_LOCK_1 - Lower Cable
SWAP_LOCK_2 - Upper Cable

TR50 10KTR50 10K

DNI

C85

C85

C86

C86

100nF

100nF

C62

C62

1uF_6.3V

1uF_6.3V

R81 182RR81 182R

OSC_EN (11)

GPIO21_BB_EN(12)

TP62TP62
TP61TP61
TP64TP64
TP63TP63

+1.8V_D2

C84

C84

10nF

10nF

+DPLL_VDDC

C61

C61

100nF

100nF

PSYNC(12)
DVALID(12)

GPIO_18(12)

GPIO_22(12)

JTAG_MODE(1)

GENERICA(15)
GENERICB(12)
GENERICC(12)

R43 221RR43 221R
R44 110RR44 110R
C46 100nFC46 100nF

+MPVDD

GND_MPVSS

C60

C60

10nF

10nF

GND_PVSS

R82

R82

51.1R

51.1R

GPIO_3
GPIO_4
GPIO_5
GPIO_6

GPIO_15
GPIO_16

XTALIN
XTALOUT

+DPLL_VDDC

R83 0RR83 0R
MR83 0RMR83 0R

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7

PSYNC
DVALID

SCL
SDA

GPIO_0
GPIO_1
GPIO_2

GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13

GPIO_22

PCIE_CLK_REQb

JTAG_MODE

JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

GENERICA
GENERICB
GENERICC

VREFG

4

U1B

U1B

AH7

VID_0

AG9

VID_1

AF9

VID_2

AJ7

VID_3

AG7

VID_4

AF7

VID_5

AH6

VID_6

AG6

VID_7

AL6

VHAD_0

AK6

VHAD_1

AK5

VPHCTL

AJ4

VPCLK0

AJ5

VIPCLK

AL5

PSYNC

AD9

DVALID

AA4

SDA

AA5

SCL

AK4

DVPCNTL_MVP_0

AL3

DVPCNTL_MVP_1

V2

DVPCNTL_0

V1

DVPCNTL_1

W3

DVPCNTL_2

W1

DVPCLK

Y1

DVPDATA_0

Y2

DVPDATA_1

Y3

DVPDATA_2

AA2

DVPDATA_3

AA3

DVPDATA_4

AB1

DVPDATA_5

AB2

DVPDATA_6

AB3

DVPDATA_7

AC1

DVPDATA_8

AC3

DVPDATA_9

AD1

DVPDATA_10

AD2

DVPDATA_11

AD3

DVPDATA_12

AF3

DVPDATA_13

AG3

DVPDATA_14

AH3

DVPDATA_15

AG1

DVPDATA_16

AH2

DVPDATA_17

AH1

DVPDATA_18

AJ3

DVPDATA_19

AJ1

DVPDATA_20

AJ2

DVPDATA_21

AK2

DVPDATA_22

AK3

DVPDATA_23

Y4

GPIO_0

V3

GPIO_1

V4

GPIO_2

V5

GPIO_3

U3

GPIO_4

U2

GPIO_5

T4

GPIO_6

T5

GPIO_7_BLON

T7

GPIO_8_ROMSO

T8

GPIO_9_ROMSI

R1

GPIO_10_ROMSCK

R2

GPIO_11

R3

GPIO_12

P1

GPIO_13

P3

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL0

N2

GPIO_16_SSIN

P4

GPIO_17_THERMAL_INT

P7

GPIO_18_HPD3

P8

GPIO_19_CTFB

P5

GPIO_20_PWRCNTL1

V7

GPIO_21_BB_EN

N3

GPIO_22_ROMCSB

Y5

GPIO_23_CLKREQB

M4

GPIO_24_JMODE

M5

GPIO_25_TDI

M7

GPIO_26_TCK

M8

GPIO_27_TMS

L8

GPIO_28_TDO

Y8

GENERICA

Y7

GENERICB

V8

GENERICC

AC11

VREFG

AH12

DPLL_PVDD

AG12

DPLL_PVSS

AH31

PCIE_PVDD

AH30

PCIE_PVSS

A9

MPVDD

B9

MPVSS

AJ31

XTALIN

AJ30

XTALOUT

AE12

DPLL_VDDC

AD11

NC_10

RV610 UNFUSED A11 RH

RV610 UNFUSED A11 RH

4

VIP / I2C

VIP / I2C

PLL &

PLL &
XTAL

XTAL

XTALIN

XTALOUT

PART 2 OF 6

PART 2 OF 6

External

External
TMDS

TMDS

General

General
Purpose

Purpose
I/O

I/O

Integrated

Integrated
TMDS

TMDS

TXVDDR_1
TXVDDR_2
TXVDDR_3
TXVDDR_4

TXVSS_1
TXVSS_2
TXVSS_3
TXVSS_4
TXVSS_5
TXVSS_6

DAC / CRT

DAC / CRT

DAC2 (TV/CRT2)

DAC2 (TV/CRT2)

V2SYNC
H2SYNC

A2VDDQ
A2VSSQ

DDC1DATA

DDC1CLK

Monitor

Monitor
Interface

Interface

DDC2DATA

DDC2CLK

DDC3DATA

DDC3CLK

TS_FDO

Thermal

Thermal

DMINUS
TESTEN

Test

Test

PLLTEST

TXCM

TXCP
TX0M

TX0P
TX1M

TX1P
TX2M

TX2P

TPVDD

TPVSS

NC_5
NC_6

NC_7
NC_8

NC_9

HSYNC
VSYNC

RSET

AVDD

AVSSQ
VDD1DI
VSS1DI

COMP

A2VDD

VDD2DI
VSS2DI

R2SET

HPD1

DPLUS

R

RB

G

GB

B

BB

R2

R2B

G2

G2B

B2

B2B

C
Y

C82

C82
12pF_50V

12pF_50V

C83

C83
22pF

22pF

AK9
AL9

AJ9
AJ10

AL10
AK10

AL11
AK11

AL7
AK7

AJ12
AJ13
AK13
AL13

AJ8
AH9
AH11
AJ11
AK12
AL12

AE11
AF11

AK8
AL8

AG11

AL28
AK28

AL27
AK27

AL26
AK26

AK29
AK30

AJ28
AL29

AH28
AJ27
AJ26

AL17
AK17

AL15
AK15

AL14
AK14

AJ17
AJ15
AJ14
AE16

AF16
AH14

AH16
AG16
AF18
AE18
AG14
AA8
AJ29

AH29
AC5

AC4
AF4

AH4
AE14
AE5

AE4
AH26
AD12

2 1

+TPVDD

C114

C114
10nF

10nF

A_R_DAC1 (13)

A_RB_DAC1 (13)

A_G_DAC1 (13)

A_GB_DAC1 (13)

A_B_DAC1 (13)

A_BB_DAC1 (13)

A_HSYNC_DAC1 (12,13)
A_VSYNC_DAC1 (12,13)

RSET

R1030 499RR1030 499R

+AVDD

+VDD1DI

A_VSYNC_DAC2 (12,14)
A_HSYNC_DAC2 (12,14)

+A2VDDQ

HPD1 (13)

TEST_EN

Y82

Y82

27.000MHz_10PPM

27.000MHz_10PPM

C110

C110
10nF

10nF

C1020

C1020
10nF

10nF

10V X7R
402 10%

C1023

C1023
10nF

10nF

DAC2_C (15)
DAC2_Y (15)
DAC2_COMP (15)

C2021

C2021
100nF

100nF

C2024

C2024
10nF

10nF

CRT1DDCDATA (13)
CRT1DDCCLK (13)

CRT2DDCDATA (14)
CRT2DDCCLK (14)

TS_FDO (16)

GPU_DPLUS (16)

GPU_DMINUS (16)

TP42TP42

3

+TXVDDR

C2022

C2022
1uF_6.3V

1uF_6.3V

R2SET

XTALIN_S

XTALOUT_S

3

NS110 NS_VIANS110 NS_VIA

GND_TPVSS

NS13 NS_VIANS13 NS_VIA

12

GND_TXVSSR

Place close to ASIC

A_R_DAC1

A_RB_DAC1

C1032 10pF_50VC1032 10pF_50V

A_G_DAC1

A_GB_DAC1

C1035 10pF_50VC1035 10pF_50V

A_B_DAC1

A_BB_DAC1

C1038 10pF_50VC1038 10pF_50V

C1021

C1021

C1022

C1022

100nF

100nF

1uF_6.3V

1uF_6.3V

6.3V X5R

10V X5R

402 10%

402 10%

C1025

C1025

C1024

C1024
100nF

100nF

1uF_6.3V

1uF_6.3V

+A2VDD +3.3V

B2030 120R_300mAB2030 120R_300mA

C2032

C2032
1uF_6.3V

1uF_6.3V

+VDD2DI

C2026

C2026

C2025

C2025
100nF

100nF

1uF_6.3V

1uF_6.3V

R2030 715RR2030 715R

+3.3V

R40

R40

4.7K

4.7K

402 402

TEST_EN (1)

MR85 0RMR85 0R

R841MR84
1M

MR86 0RMR86 0R

12

R1031 75RR1031 75R

R1034 75RR1034 75R

R1037 75RR1037 75R

GND_AVSSQ

NS1020NS_VIANS1020NS_VIA

GND_AVSSQ

NS1021NS_VIANS1021NS_VIA

GND_VSS1DI

C2031

C2031
100nF

100nF

R41

R41

4.7K

4.7K

R1033 75RR1033 75R

R1036 75RR1036 75R

R1039 75RR1039 75R

12

12

Possible alternate 5150005600G

NS2020NS_VIANS2020NS_VIA

12

GND_A2VSSQ

NS2021NS_VIANS2021NS_VIA

12

GND_VSS2DI

GND_A2VSSQ

I2C DEVICE ADDRESS' ON DDC3

DEVICE

ADDRESS

LM63

x100 1100

DDC3DATA (10,16)
DDC3CLK (10,16)

XTALIN

XTALOUT

+LTVDD33

A_R_DAC2 (14)

A_RB_DAC2 (14)

A_G_DAC2 (14)

A_GB_DAC2 (14)

A_B_DAC2 (14)

A_BB_DAC2 (14)

+LTVDD18S

10uF_X6S

10uF_X6S

1 2

C106

C106

1uF_6.3V

1uF_6.3V

C103

C103

C102

C102

10uF_X6S

10uF_X6S

NS100NS_VIA NS100NS_VIA

2

C105

C105

100nF

100nF

C108

C108

1uF_6.3V

1uF_6.3V

+T2PVDD

C101

C101
100nF

100nF

GND_T2PVSS

Place close to ASIC

A_R_DAC2

A_RB_DAC2

A_G_DAC2

A_GB_DAC2

A_B_DAC2

A_BB_DAC2

2

LVT_EN(11)

C104

C104
10nF

10nF

+LTVDD18

C109

C109

100nF

100nF

C100

C100
1uF_6.3V

1uF_6.3V

C2033 10pF_50VC2033 10pF_50V

C2035 10pF_50VC2035 10pF_50V

C2038 10pF_50VC2038 10pF_50V

GPIO_8
GPIO_9
GPIO_10
GPIO_22

+12V_BUS

+3.3V_BUS

AF20
AG20

AJ18
AH20

AF23
AF21
AL18
AJ22
AJ25
AK18
AK23
AK25
AJ21
AL23
AL25

AG18
AH18

R2031 75RR2031 75R

R2034 75RR2034 75R

R2037 75RR2037 75R

+3.3V

+1.8V_D2

MR108

MR108
10K

10K

Share one pad

MR1090RMR109

R1090RR109

0R

0R

DNI

U1F

U1F

PART 6 OF 6

PART 6 OF 6

T2XVDDR_1
T2XVDDR_2

T2XVDDC_1
T2XVDDC_2

T2XVSSR_1
T2XVSSR_2
T2XVSSR_3
T2XVSSR_4
T2XVSSR_5
T2XVSSR_6
T2XVSSR_7
T2XVSSR_8
T2XVSSR_9
T2XVSSR_10
T2XVSSR_11

T2PVDD
T2PVSS

RV610 UNFUSED A11 RH

RV610 UNFUSED A11 RH

R2033 75RR2033 75R

R2036 75RR2036 75R

R2039 75RR2039 75R

R45

R45
10K

10K

MR45

MR45
10K

10K

R107 0RR107 0R

1

1

R108 0RR108 0R

DNI

Control

Control

LVDS channel

LVDS channel

+3.3V

+3.3V

C47

C47
100nF

100nF

1

DNI

32

Q100

Q100

SI2304DS

SI2304DS

SI2304DS

SI2304DS

Q101

Q101

32

AA7

RSVD_7

AC6

RSVD

AD21

RSVD_1

AE21

RSVD_2

AJ24

T2X4P

AJ23

T2X4M

AK24

T2X5P

AL24

T2X5M

AG21

RSVD_4

AH21

RSVD_3

AG23

RSVD_6

AH23

RSVD_5

AL19

T2XCP

AK19

T2XCM

AJ20

T2X0P

AJ19

T2X0M

AK20

T2X1P

AL20

T2X1M

AK21

T2X2P

AL21

T2X2M

AK22

T2X3P

AL22

T2X3M

R46

R46
10K

10K

U2

U2

5

D

6

C

1

S

7

HOLD

3

W

8

VCC

M25P05-AVNM6P

M25P05-AVNM6P

Title

Title

Title
Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

+LTVDD18S

B100

B100

BLM15BD121SN1

BLM15BD121SN1

+LTVDD33

B101

B101

BLM15BD121SN1

BLM15BD121SN1

Place close to ASIC
<7mm

R104 100RR104 100R

TjX4P
TjX4M

R105 100RR105 100R

TjX5P
TjX5M

R106 100RR106 100R

TjXCP
TjXCM

R100 100RR100 100R

TjX0P
TjX0M

R101 100RR101 100R

TjX1P
TjX1M

R102 100RR102 100R

TjX2P
TjX2M

R103 100RR103 100R

TjX3P
TjX3M

2

Q

BIOS1

BIOS1

BIOS

BIOS

4

VSS

113-XXXXXX-XXX

113-XXXXXX-XXX

VIDEO BIOS
FIRMWARE

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

105-B170xx-00

105-B170xx-00

105-B170xx-00

1

TjX4P (13)
TjX4M (13)

TjX5P (13)
TjX5M (13)

TjXCP (13)
TjXCM (13)

TjX0P (13)
TjX0M (13)

TjX1P (13)
TjX1M (13)

TjX2P (13)
TjX2M (13)

TjX3P (13)
TjX3M (13)

21

21

21

of

of

of

319Saturday, April 28, 2007

319Saturday, April 28, 2007

319Saturday, April 28, 2007

www.vinafix.vn

5

+MVDD

C128

C128

C129

C124

C124
10nF

10nF

D D

C C

B B

C134

C134
10uF_X6S

10uF_X6S

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 10%, 0805, 6.3V, 1.4MM MAX THICK
1uF, X6S, 10%, 0402, 6.3V
100nF, X7R, 10%, 0402
10nF , X7R, 10%, 0402

C135

C135
10uF_X6S

10uF_X6S

C136

C136
10uF_X6S

10uF_X6S

C137

C137
10uF_X6S

10uF_X6S

+MVDD

+3.3V

C126

C126

C125

C125

10nF

10nF

10nF

10nF

C139

C138

C138

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

+1.8V_D2

+3.3V

MR94 0RMR94 0R

B120 BLM15BD121SN1B120 BLM15BD121SN1
B121 BLM15BD121SN1B121 BLM15BD121SN1

C120

C120

1uF_6.3V

1uF_6.3V

NS121 NS_VIANS121 NS_VIA

12

GND_VSSRH0

C127

C127
10nF

10nF

C140

C140
1uF_6.3V

1uF_6.3V

B70

B70

BLM15BD121SN1

BLM15BD121SN1

C121

C121

1uF_6.3V

1uF_6.3V

10nF

10nF

C141

C141
1uF_6.3V

1uF_6.3V

C91

C91
1uF_6.3V

1uF_6.3V

+VDDR_DVP

NS122 NS_VIANS122 NS_VIA

12

GND_VSSRH1

C129
100nF

100nF

C142

C142
1uF_6.3V

1uF_6.3V

C68

C68
10uF_X6S

10uF_X6S

C123

C123

1uF_6.3V

1uF_6.3V

+VDD_CT

C92

C92
1uF_6.3V

1uF_6.3V

C94

C94
10uF_X6S

10uF_X6S

C130

C130
100nF

100nF

C143

C143
1uF_6.3V

1uF_6.3V

C69

C69
100nF

100nF

C122

C122

1uF_6.3V

1uF_6.3V

C93

C93
100nF

100nF

C131

C131
100nF

100nF

C144

C144
1uF_6.3V

1uF_6.3V

C78

C78
100nF

100nF

+VDDC

4

C99

C99
100nF

100nF

C95

C95
1uF_6.3V

1uF_6.3V

C132

C132
100nF

100nF

C145

C145
100nF

100nF

C79

C79
100nF

100nF

+VDDR3

C97

C97
100nF

100nF

C133

C133
100nF

100nF

C146

C146
100nF

100nF

C59

C59
100nF

100nF

C96

C96
1uF_6.3V

1uF_6.3V

C98

C98
100nF

100nF

U1D

U1D

A15

VDDR1_1

A22

VDDR1_2

A28

VDDR1_3

A4

VDDR1_4

A8

VDDR1_5

B8

VDDR1_6

C9

VDDR1_7

D1

VDDR1_8

H1

VDDR1_9

H11

VDDR1_10

H12

VDDR1_11

H14

VDDR1_12

H16

VDDR1_13

H18

VDDR1_14

H20

VDDR1_15

H21

VDDR1_16

B31

VDDR1_17

M1

VDDR1_18

AA9

VDD_CT_1

Y9

VDD_CT_2

V9

VDD_CT_3

T9

VDD_CT_4

J11

VDD_CT_5

J20

VDD_CT_6

J21

VDD_CT_7

L9

VDD_CT_8

AC18

VDDR3_1

AC16

VDDR3_2

AC14

VDDR3_3

AC12

VDDR3_4

AF1

VDDR4_1

AF2

VDDR4_2

AE1

VDDR5_1

AE2

VDDR5_2

M2

NC_1

M3

NC_2

L4

NC_3

AE7

NC_4

A10

VDDRH_1

A19

VDDRH_2

B10

VSSRH_1

B19

VSSRH_2

V11

BBN_1

U11

BBN_2

R11

BBP_1

P11

BBP_2

RV610 UNFUSED A11 RH

RV610 UNFUSED A11 RH

PART 4 OF 6

PART 4 OF 6

I/O Internal

I/O Internal

Memory

I/O

Clock

Memory

I/O

Clock

Memory I/O

Memory I/O

P

P
O

O
W

W
E

E
R

R

Back Bias

Back Bias

3

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8

PCIE_VDDC_1
PCIE_VDDC_2
PCIE_VDDC_3
PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8
PCIE_VDDC_9

PCIE_VDDC_10

PCI-Express

PCI-Express

PCIE_VDDC_11
PCIE_VDDC_12

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15

Core

Core

VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33

VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4

AF30
AF31
AF29
AF27
AF28
AG29
AG30
AG31

AA23
AC24
AC25
AE26
AE27
AE28
L23
M23
P23
T23
V23
Y23

L11
L14
L17
L20
M12
M15
M18
M21
AC20
P14
P17
P20
R12
R15
R18
R21
AD20
U14
U17
U20
V12
V15
V18
V21
Y11
Y14
Y17
Y20
AA12
AA15
AA18
AA21
P9

J12
J14
J16
J18

C900

C900
1uF_6.3V

1uF_6.3V

C901

C901
1uF_6.3V

1uF_6.3V

C920

C920
1uF_6.3V

1uF_6.3V

C161

C161
1uF_6.3V

1uF_6.3V

C171

C171
1uF_6.3V

1uF_6.3V

C74

C74
100nF

100nF

C902

C902
1uF_6.3V

1uF_6.3V

C921

C921
1uF_6.3V

1uF_6.3V

C162

C162
1uF_6.3V

1uF_6.3V

C172

C172
1uF_6.3V

1uF_6.3V

C75

C75

1uF_6.3V

1uF_6.3V

+VDDCI

C903

C903
1uF_6.3V

1uF_6.3V

C922

C922
1uF_6.3V

1uF_6.3V

C163

C163
1uF_6.3V

1uF_6.3V

C173

C173
1uF_6.3V

1uF_6.3V

C73

C73

1uF_6.3V

1uF_6.3V

2

C904

C904

C905

C905

10uF_X6S

10uF_X6S

10nF

10nF

C923

C923
1uF_6.3V

1uF_6.3V

C164

C164

C165

C165

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C175

C175

C174

C174

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

Overlap

B78 220R_2AB78 220R_2A
MR78 0RMR78 0R

C924

C924
1uF_6.3V

1uF_6.3V

+PCIE_VDDR

C906

C906
100nF

100nF

C166

C166
1uF_6.3V

1uF_6.3V

C176

C176
1uF_6.3V

1uF_6.3V

C925

C925
1uF_6.3V

1uF_6.3V

R900 0RR900 0R

C167

C167
1uF_6.3V

1uF_6.3V

C177

C177
1uF_6.3V

1uF_6.3V

+VDDC

C77

C77
10uF_X6S

10uF_X6S

C927

C927
1uF_6.3V

1uF_6.3V

C168

C168
1uF_6.3V

1uF_6.3V

C178

C178
1uF_6.3V

1uF_6.3V

+1.8V_D2

+PCIE_VDDC

C928

C928
1uF_6.3V

1uF_6.3V

C169

C169
1uF_6.3V

1uF_6.3V

C179

C179
1uF_6.3V

1uF_6.3V

C170

C170
1uF_6.3V

1uF_6.3V

C180

C180
1uF_6.3V

1uF_6.3V

C926

C926
10uF_X6S

10uF_X6S

B920 220R_2AB920 220R_2AC139

R920 0RR920 0R

C181

C181
10uF_X6S

10uF_X6S

1

Share Pad

C182

C182
10uF_X6S

10uF_X6S

C183

C183
10uF_X6S

10uF_X6S

+VDDC

+1.1V

+VDDC

C184

C184
10uF_X6S

10uF_X6S

C193

C193

C192

C192

100nF

100nF

1uF_6.3V

1uF_6.3V

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

105-B170xx-00

105-B170xx-00

105-B170xx-00

1

21

21

419Saturday, April 28, 2007

419Saturday, April 28, 2007

419Saturday, April 28, 2007

21

of

of

of

www.vinafix.vn

5

4

3

2

1

D D

C C

PLACE MVREF DIVIDERS
AND CAPS CLOSE TO ASIC

+MVDD

R291

R291
100R

100R

1%

C296

R292

+MVDD

R292
100R

100R

1%

R293

R293
100R

100R

1%

R294

R294
100R

100R

1%

B B

C295

C295
100nF

100nF

C297

C297
100nF

100nF

C296
10nF

10nF

C298

C298
10nF

10nF

M_MDA[63..0](7)

U1C

MVREFD_0
MVREFS_0

R296

R296

4.7K

4.7K

M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
M_MDA5
M_MDA6
M_MDA7
M_MDA8

M_MDA9
M_MDA10
M_MDA11
M_MDA12
M_MDA13
M_MDA14
M_MDA15
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
M_MDA21
M_MDA22
M_MDA23
M_MDA24
M_MDA25
M_MDA26
M_MDA27
M_MDA28
M_MDA29
M_MDA30
M_MDA31
M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA63

R297

R297

4.7K

4.7K

R298

R298
243R

243R

E29
E30
E31
D31
C29
B29
B30
A29
E26
D26
E25
D25
G23
G21
E21
D21
C28
B28
B27
A27
C25
A25
C24
B24
C23
B23
A23
B22
C20
B20
A20
C19

C8
C7
B7
A7
A5
C4
B4
A3

G9

E9

D9
G7
G5

F5
G4

F4

B3

B2

C2

C1

E3

F3

F2

F1
G2
G1

H3

H2

K2

L3

L2

L1

F30
F31

L5

L7

J7

U1C

Part 3 of 6

Part 3 of 6

DQ_0
DQ_1
DQ_2
DQ_3
DQ_4

MEMORY

MEMORY

DQ_5

INTERFACE

INTERFACE

DQ_6
DQ_7
DQ_8
DQ_9
DQ_10
DQ_11
DQ_12
DQ_13
DQ_14
DQ_15
DQ_16
DQ_17
DQ_18
DQ_19
DQ_20
DQ_21
DQ_22
DQ_23
DQ_24
DQ_25
DQ_26
DQ_27
DQ_28
DQ_29
DQ_30
DQ_31
DQ_32
DQ_33
DQ_34
DQ_35
DQ_36
DQ_37
DQ_38
DQ_39
DQ_40
DQ_41
DQ_42
DQ_43
DQ_44
DQ_45
DQ_46
DQ_47
DQ_48
DQ_49
DQ_50
DQ_51
DQ_52
DQ_53
DQ_54
DQ_55
DQ_56
DQ_57
DQ_58
DQ_59
DQ_60
DQ_61
DQ_62
DQ_63

MVREFD
MVREFS

TEST_MCLK
TEST_YCLK
MEMTEST

RV610 UNFUSED A11 RH

RV610 UNFUSED A11 RH

MA_0
MA_1
MA_2
MA_3
MA_4
MA_5
MA_6
MA_7
MA_8

MA_9
MA_10
MA_11

MA_BA0
MA_BA1
MA_A12
MA_BA2

DQMb_0
DQMb_1
DQMb_2
DQMb_3
DQMb_4
DQMb_5
DQMb_6
DQMb_7

QS_0

QS_1

QS_2

QS_3

QS_4

QS_5

QS_6

QS_7
QS_0B

QS_1B
QS_2B
QS_3B
QS_4B
QS_5B
QS_6B

write strobe read strobe

write strobe read strobe

QS_7B

ODT0

ODT1

CLK0
CLK1

CLK0b
CLK1b

RAS0b
RAS1b

CAS0b
CAS1b

CS0b_0
CS0b_1

CS1b_0
CS1b_1

CKE0

CKE1

WE0b

WE1b

DRAM_RST

M_MAA0

B14

M_MAA1

A14

M_MAA2

B13

M_MAA3

E14

M_MAA4

B17

M_MAA5

A17

M_MAA6

C15

M_MAA7

G16

M_MAA8

E16

M_MAA9

C14

M_MAA10

A12

M_MAA11

B12

M_MAA14

C12

M_MAA15

D14

M_MAA12

B15

M_MAA13

G14

M_DQMA#0

D30

M_DQMA#1

G25

M_DQMA#2

C26

M_DQMA#3

C21

M_DQMA#4

C5

M_DQMA#5

D6

M_DQMA#6

D2

M_DQMA#7

K3

M_QSA0

C30

M_QSA1

D23

M_QSA2

B26

M_QSA3

B21

M_QSA4

B6

M_QSA5

E7

M_QSA6

E2

M_QSA7

J2
C31

E23
A26
A21
A6
D7
E1
J1

E20
C11

A18

CLKA0 (7)

A11

CLKA1 (7)

B18

CLKA#0 (7)

B11

CLKA#1 (7)

G20

RASA#0 (7)

D12

RASA#1 (7)

D20

CASA#0 (7)

E12

CASA#1 (7)

E18

CSA#0_0 (7)

G18
G11

CSA#1_0 (7)

E11
D18

CKEA0 (7)

G12

CKEA1 (7)

D16

WEA#0 (7)

C10

WEA#1 (7)

J5

ODT (7)

M_MAA[15..0] (7)

M_DQMA#[7..0] (7)

M_QSA[7..0] (7)

SHOULD CS BE RUN DIFFERENTIALLY????

+MVDD

R295

R295

2.0K

2.0K

Overlap

DNI

MR295

MR295

4.7K

4.7K

A A

5

DIVIDER RESISTORS DDR2 GDDR3
MVREF TO 1.8V
MVREF TO GND

40.2R100R
100R100R

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

4

www.vinafix.vn

3

2

Date: Sheet

105-B170xx-00

105-B170xx-00

105-B170xx-00

1

21

21

21

of

of

of

519Saturday, April 28, 2007

519Saturday, April 28, 2007

519Saturday, April 28, 2007

5

D D

C C

B B

A A

5

4

U1E

U1E

AA26

PCIE_VSS_1

AA29

PCIE_VSS_2

AC26

PCIE_VSS_3

AD31

PCIE_VSS_4

AE29

PCIE_VSS_5

AE30

PCIE_VSS_6

AE31

PCIE_VSS_7

F28

PCIE_VSS_8

G26

PCIE_VSS_9

G29

PCIE_VSS_10

G30

PCIE_VSS_11

G31

PCIE_VSS_12

H29

PCIE_VSS_13

J25

PCIE_VSS_14

J26

PCIE_VSS_15

L26

PCIE_VSS_16

L29

PCIE_VSS_17

L30

PCIE_VSS_18

L31

PCIE_VSS_19

M26

PCIE_VSS_20

M29

PCIE_VSS_21

P26

PCIE_VSS_22

R29

PCIE_VSS_23

R30

PCIE_VSS_24

R31

PCIE_VSS_25

T26

PCIE_VSS_26

U29

PCIE_VSS_27

V26

PCIE_VSS_28

Y26

PCIE_VSS_29

Y29

PCIE_VSS_30

Y30

PCIE_VSS_31

Y31

PCIE_VSS_32

A13

VSS_1

A2

VSS_2

C18

VSS_3

A24

VSS_4

A30

VSS_5

AA1

VSS_6

AA11

VSS_7

AA14

VSS_8

AA17

VSS_9

AA20

VSS_10

AA6

VSS_11

AC2

VSS_12

AC7

VSS_13

AE3

VSS_15

AL4

VSS_16

AD14

VSS_17

AF12

VSS_18

AF14

VSS_19

AD16

VSS_20

AD18

VSS_21

AE6

VSS_22

AG2

VSS_23

AE9

VSS_24

AH25

VSS_25

AK1

VSS_26

AK31

VSS_27

AJ6

VSS_28

AL2

VSS_29

AL30

VSS_30

B1

VSS_31

C13

VSS_32

CORE GND

CORE GND

RV610 UNFUSED A11 RH

RV610 UNFUSED A11 RH

4

Part 5 of 6

Part 5 of 6

VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41

PCI-Express GND

PCI-Express GND

VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102

B25
J8
B5
D11
C17
C22
C27
D29
C3
C6
D3
D28
F29
D4
F11
F12
F14
F16
F18
F20
F21
F23
F25
F7
F9
G3
G6
H23
J3
J4
J6
K1
L12
L15
L18
L21
L6
M11
M14
M17
M20
M6
P12
P15
P18
P21
P6
AC21
R14
R17
R20
T6
U1
U12
U15
U18
U21
AE20
V14
V17
V20
P2
V6
W2
Y12
Y15
Y18
Y21
Y6
M9

3

3

2

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

105-B170xx-00

105-B170xx-00

105-B170xx-00

1

21

21

of

of

of

619Saturday, April 28, 2007

619Saturday, April 28, 2007

619Saturday, April 28, 2007

1

21

www.vinafix.vn

8

7

6

5

4

3

2

1

CHANNEL A: RANK 0 128MB DDR2

M_DQMA#[7..0](5)

D D

M_MDA[63..0](5)

M_MAA[15..0](5)

M_MAA[15..0](5)

C C

VREF_A0

+MVDD +MVDD +MVDD

R201

R201

4.99K

4.99K

R202

B B

R202

4.99K

4.99K

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

M_MAA14

L2

M_MAA15

L3

M_MAA12

R2

M_MAA11

P7

M_MAA10

M2

M_MAA9

P3

M_MAA8

P8

M_MAA7

P2

M_MAA6

N7

M_MAA5

N3

M_MAA4

N8

M_MAA3

N2

M_MAA2

M7

M_MAA1

M3

M_MAA0

M8

M_MAA13

TP200TP200

K8

CLKA#0(5)

J8

CLKA0(5)

K2

CKEA0(5)

CSA#0_0(5)

ODT(5) ODT(5) ODT(5) ODT(5)

R211 10RR211 10R

R212 10RR212 10R

VREF_U20

C413

C413
100nF

100nF

L8

WEA#0(5)

K7

RASA#0(5)

L7

CASA#0(5)

M_DQMA#2

F3

M_DQMA#3 M_DQMA#7

B3

K9

M_QSA2

F7
E8

M_QSA3

B7
A8

J2
A2

E2

L1
R3
R7
R8

U201

U201

BA0
BA1

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CK

VDDQ1

CK

VDDQ2
VDDQ3

CKE

VDDQ4
VDDQ5
VDDQ6
VDDQ7

CS

VDDQ8
VDDQ9

WEK3VDDQ10
RAS
CAS
LDM

UDM

VSSDL

ODT

LDQS

VSSQ1

LDQS

VSSQ2
VSSQ3
VSSQ4
VSSQ5

UDQS

VSSQ6

UDQS

VSSQ7
VSSQ8

VREF

VSSQ9

VSSQ10
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

HY5PS561621F-25

HY5PS561621F-25

M_QSA[7..0](5)

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSS1
VSS2
VSS3
VSS4
VSS5

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7

U203

U202

M_MDA27

B9

M_MDA30

B1

M_MDA24

D9

M_MDA29

D1

M_MDA31

D3

M_MDA26

D7

M_MDA28

C2

M_MDA25

C8

M_MDA18

F9

M_MDA21

F1

M_MDA17

H9

M_MDA22

H1

M_MDA23

H3

M_MDA16

H7

M_MDA20

G2

M_MDA19

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

+MVDD

+MVDD

B201

B201
120R_300mA

120R_300mA

Possible alternate 5150005600G Possible alternate 5150005600G Possible alternate 5150005600G Possible alternate 5150005600G

C411

C411

C412

C412

100nF

100nF

1uF_6.3V

1uF_6.3V

VREF_A0

M_MAA14
M_MAA15

M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

CLKA#0(5)
CLKA0(5)

CKEA0(5)

CSA#0_0(5)

WEA#0(5)
RASA#0(5)
CASA#0(5)

M_DQMA#0
M_DQMA#1

M_QSA0

R213 10RR213 10R R215 10RR215 10R

M_QSA1

R214 10RR214 10R R216 10RR216 10R

R203

R203

4.99K

4.99K

VREF_U21

R204

R204

C438

C438

4.99K

4.99K

100nF

100nF

U202

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS
WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

M_MDA14

B9

M_MDA9

B1

M_MDA13

D9

M_MDA8

D1

M_MDA10

D3

M_MDA12

D7

M_MDA11

C2

DQ9

C8

DQ8

M_MDA6

F9

DQ7

M_MDA3

F1

DQ6

M_MDA4

H9

DQ5

M_MDA1

H1

DQ4

M_MDA2

H3

DQ3

M_MDA7

H7

DQ2

M_MDA0

G2

DQ1

M_MDA5

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9

B202

B202

M9

120R_300mA

120R_300mA

R1
J1

J7

C436

C436
100nF

100nF

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

C437

C437
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

VREF_A1

R205

R205

4.99K

4.99K

R206

R206

4.99K

4.99K

VREF_U22

M_MAA14
M_MAA15

M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

CLKA#1(5)
CLKA1(5)

CKEA1(5)

CSA#1_0(5)

WEA#1(5)
RASA#1(5)
CASA#1(5)

M_DQMA#6

M_QSA6

M_QSA7

C463

C463
100nF

100nF

U203

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS
WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

R217 10RR217 10R

R218 10RR218 10R

R207

R207

4.99K

4.99K

VREF_U23

R208

R208

4.99K

4.99K

M_MAA14
M_MAA15

M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

CLKA#1(5)
CLKA1(5)

CKEA1(5)

CSA#1_0(5)

WEA#1(5)
RASA#1(5)
CASA#1(5)

M_DQMA#4
M_DQMA#5

M_QSA4

M_QSA5

C448

C448
100nF

100nF

M_MDA58

B9

M_MDA60

B1

M_MDA57

D9

M_MDA62

D1

M_MDA63

D3

M_MDA56

D7

M_MDA61

C2

DQ9

M_MDA59M_MDA15

C8

DQ8

M_MDA51

F9

DQ7

M_MDA53

F1

DQ6

M_MDA48

H9

DQ5

M_MDA52

H1

DQ4

M_MDA55

H3

DQ3

M_MDA49

H7

DQ2

M_MDA54

G2

DQ1

M_MDA50

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9

B203

B203

M9

120R_300mA

120R_300mA

R1
J1

J7

C461

C461
100nF

100nF

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

C462

C462
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

VREF_A1

+MVDD

U204

U204

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS
WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

M_MDA46

B9

M_MDA40

B1

M_MDA45

D9

M_MDA43

D1

M_MDA41

D3

M_MDA47

D7

M_MDA42

C2

DQ9

M_MDA44

C8

DQ8

M_MDA36

F9

DQ7

M_MDA34

F1

DQ6

M_MDA39

H9

DQ5

M_MDA32

H1

DQ4

M_MDA33

H3

DQ3

M_MDA38

H7

DQ2

M_MDA35

G2

DQ1

M_MDA37

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9

B204

B204

M9

120R_300mA

120R_300mA

R1
J1

J7

C446

C446
100nF

100nF

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

C447

C447
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

+MVDD

C402

C402

C401

C401
1uF_6.3V

1uF_6.3V

+MVDD

C406

C406
1uF_6.3V

1uF_6.3V

402

A A

8

C403

C403

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

402402402

C408

C408

C407

C407

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

402 402 402

7

C409

C409
1uF_6.3V

1uF_6.3V

C410

C410
1uF_6.3V

1uF_6.3V

402

CLKA0(5)

CLKA#0(5)

CLKA1(5)

CLKA#1(5)

R221

R221
56R

56R

402

R222

R222
56R

56R

402 402

R223

R223
56R

56R

402

R224

R224
56R

56R

402 402

6

+MVDD

C426

C426
1uF_6.3V

1uF_6.3V

402 402402

+MVDD

C431

C431
1uF_6.3V

1uF_6.3V

402 402

C499

C499
10nF

10nF

C500

C500
10nF

10nF

C428

C428

C427

C427

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C434

C432

C432
1uF_6.3V

1uF_6.3V

402 402 402 402

C434

C433

C433

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

+MVDD +MVDD

R209

R209

4.99K

4.99K

VREF_A0 VREF_A1

R210

R210

4.99K

4.99K

5

C435

C435
1uF_6.3V

1uF_6.3V

R219

R219

4.99K

4.99K

R220

R220

4.99K

4.99K

+MVDD

C451

C451
1uF_6.3V

1uF_6.3V

402 402402

+MVDD

C456

C456
1uF_6.3V

1uF_6.3V

4

C453

C453

C452

C452

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C458

C458

C457

C457

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

402 402 402

C459

C459
1uF_6.3V

1uF_6.3V

C460

C460
1uF_6.3V

1uF_6.3V

402

3

+MVDD

C477

C477

C476

C476
1uF_6.3V

1uF_6.3V

402 402402

+MVDD

C481

C481
1uF_6.3V

1uF_6.3V

402

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

2

C478

C478

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C484

C482

C482
1uF_6.3V

1uF_6.3V

402 402 402 402

C484

C483

C483

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

105-B170xx-00

105-B170xx-00

105-B170xx-00

C485

C485
1uF_6.3V

1uF_6.3V

1

of

of

of

719Saturday, April 28, 2007

719Saturday, April 28, 2007

719Saturday, April 28, 2007

21

21

21

www.vinafix.vn

8

D D

7

+PW_VDDC_HGD +PW_VDDC_HGDR

6

R621 0RR621 0R

5

Thermal

Thermal

+VDDC_S

Pad

Pad

9

6
7
8

C615

C615

C616

C616

10UF

10UF

10UF

10UF

12061206

on PCB

USE CAP CER 10UF 20% 16V
X7R (1206)

L601

L601
R68UH

R68UH

Q601

Q601

QH

402

4 5
3
2
1

BSC119N03SG

BSC119N03SG

C617

C617

4.7uF_10V

4.7uF_10V

805

Use16V 0805 MLCCMirrored

Mirrored on PCB

4

C619

C619

4.7uF_10V

4.7uF_10V

805

C618

C618
150nF_16V

150nF_16V

603

3

ML602

C627

C627
68uF_16V

68uF_16V

Overlap

ML602

0.47uH

0.47uH

Overlap

L602

L602

IND_0.47uH_7A

IND_0.47uH_7A

7 2

6 3

8 1

5 4

Find 100nH
SM Alt. IND

RP601B 0RRP601B 0R

RP601A 0RRP601A 0R

RP601C 0RRP601C 0R

RP601D 0RRP601D 0R

+12V_BUS

B601

B601
60R

60R

MC627

MC627
180uF_16V

180uF_16V

SM 8mm DiaSM 6.3mm Dia

2

C630

C630

100uF_16V

100uF_16V

C620

C620
10UF

10UF

1206

+VDDC_S

MC620

MC620

4.7uF_10V

4.7uF_10V

805 1206

Overlap

Mirrored on PCB

+VDDC_S

1

MC621

MC621

C621

C621

4.7uF_10V

4.7uF_10V

10UF

10UF

805

Overlap

MULTI FOOTPRINT

Place Rs and Cs across QL

VDDC_FB

+PW_VDDC_LGDR

4 5
3
2
1

5

NL601 2.2uH_13ANL601 2.2uH_13A

1 2

R619

R619
33MOHM

33MOHM

Rs

1210
1%

C608

C608
10nF_25V

10nF_25V

402

Cs

X7R
25V

MQ602

MQ602

Thermal

Thermal

Pad

Pad

FDS7096N3

FDS7096N3

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

9

6
7
8

R1

RFB1

R611

R611

4.99K

4.99K

402
1%

R4

RFB2

R610

R610

3.24K

3.24K

402
1%

C613

C613

3.9nF

3.9nF

402

16V

10%

X7R

R613

R613

3.65K

3.65K

402
5%

Place R1 and
R4 close to
PWM and
routed with
separate
20mil trace to
the ASIC

MULTI FOOTPRINT

4

**

MC623

MC623
22uF_16V

22uF_16V

**

ALT

Over Lap

***

C625

C625
820uF_2.5V

820uF_2.5V

*** ***

8 x 8 mm, TH

C623

C623
10uF

10uF

Over Lap

3

+PW_VDDC_M

Q602

Q602

QL

Thermal

Thermal

Pad

Pad

BSC119N03SG

BSC119N03SG

VDDC_FB(10)

+12V_BUS +5V

MR6060RMR606
0R

402 402

C606

C606
150nF_16V

150nF_16V

+VDDC_B

9

6
7
8

R6060RR606
0R

+PW_VDDC_M

RC snubber values shown
are for reference only,
tuning is required

+PW_VDDC_LGD

C C

B B

1-Position the controller (U703) such that LGate(pin4) is the closet to gate
of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate
of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as
short and as wide as possible to reduce the trace inductance.
2-Place the bypass capacitors for Vcc as well as Boost caps as close to the
controller as possible. They are as follows;
Vcc bypass cap is C703, and Boost cap is C705.
3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place
the rest of the compensation network close to the pins 7 and 6. These are R710,
R711, R713, C713 and R712, C711 and C712.

+VDDC_B

U603

U603

1

+PW_VDDC_HGD

+PW_VDDC_LGD

R615

R615

42.2K

42.2K

List of supported foodprint
The following ICs are not necessarily evaluated by

ATI, please refer to BOM for evaluation status

ANPEC APW7120/APW7065 (12V)
CAT CAT7583 (12V)
INTERSIL ISL6545
NEXSEM NX2114/2307
RICHTEK RT9214/RT8101
OnSemi ON1582
uPI UP6101 (No Ext_Vref in)

Layout guideline for Nexsem NX2114/2307

BOOT

2

UGATE

3

GND
LGATE4VCC

APW7065

APW7065

PHASE

COMP

+PW_VDDC_M

8

VDDC_COMP

7

VDDC_FB

6

FB

5

+VDD_VCC

C603

C603

0.22uF

0.22uF

VDD_EN (1,16)

R608 20KR608 20K

402

COMPENSATION CIRCUIT FILTERED SMPS VCC

402

C612

C612
390pF

390pF

603
NPOX7R

R614 0RR614 0R

R6090RR609
0R

8

VDDC_COMP

C614

C614
100nF

100nF

50V

402

10V

5%

X5R

10%

VDDC_FB

+VDD_VCC

+12V_BUS

7

R607

R607

2.2R

2.2R

C607

C607
100nF

100nF

+5V

603
X7R
5%

C611

C611

A A

15nF

15nF

10V

402

10%

R612

R612

2.94K

2.94K

402
1%

R622 0RR622 0R

MR607

MR607

2.2R

2.2R

+PW_VDDC_LGDR

603

+PW_VDDC_HGDR

4 5
3
2
1

+PW_VDDC_M

MQ601

MQ601

Thermal

Thermal

Pad

Pad

FDS7096N3

FDS7096N3

BOOT CIRCUIT

3

1

2

C605

C605
100nF

100nF

603 X7R

16V

5%

6

4 5
3
2
1

+VDDC_S

9

6
7
8

D601

D601
BAT54A

BAT54A

***

KC625

KC625
470uF_10V

470uF_10V

10 x 12.5 mm, TH

+VDDC

C624

C624
10uF

10uF

CAP CER 10UF 10%

6.3V X5R (0805)1.4MM
MAX THICK

+VDDC

SMPS02- Regulator for VDDC

Vout = 0.9V ~ 1.1V

Vout

Part RFB2RFB1

1.1V

0.8V Ref
(1.98V~2.08V)

1.1V
(1.10V~1.14V)

SMPS02 Specifications

Vin 12V(power stage) +/-8% PCIe ATX12V ver. 2.2 +/-5%

Vout 2V

Vout ripple (DC) 50mVpp

Iout 6Aavg, 8Adc_max

Step load 3Amax

Protections

+/-10% or 200mVpp @ 3A step loadVout ripple (AC)

Title

Title

Title
Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

200R
p/n 3160200000G

10K

Nominal Value Adjustable range / Notes

~300kHzSwitching Freq. TBD

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

C622

C622
10UF

10UF

1206

Tolerance

;

;

+2%/-2%

;

105-B170xx-00

105-B170xx-00

105-B170xx-00

MC622

MC622

4.7uF_10V

4.7uF_10V

805 1206

Overlap

Mirrored on PCB

p/n 3160100200G

1.8V ~ 2.85V

C628

C628

4.7uF_10V

4.7uF_10V

10UF

10UF

511R
p/n 3160511000G

24.9K
p/n 3160249200G

819Saturday, April 28, 2007

819Saturday, April 28, 2007

819Saturday, April 28, 2007

1

MC628

MC628

805

Overlap

of

of

of

21

21

21

www.vinafix.vn

8

7

6

5

4

3

2

1

MEMORY POWER CHANNEL. SEE p. 10 FOR DETAILS.

MEM_PWR_CHANNEL

KC725

KC725
330uF_2.5V

330uF_2.5V

TAN LP
25mOHM

NC725

NC725
330uF_2.5V

330uF_2.5V

TAN LP
25mOHM

Over Lap

MEM_PWR_CHANNEL (10)

+MVDDC_S

MC720

MC720

C720

C720

4.7uF_10V

4.7uF_10V

10UF

10UF

1206

805 1206

Overlap

Mirrored on PCB

+MVDD

*** ***

C723

C723
100uF_6.3V

100uF_6.3V

1210 1210

*** ***

C724

C724
100uF_6.3V

100uF_6.3V

C721

C721
10UF

10UF

MC721

MC721

4.7uF_10V

4.7uF_10V

805

Overlap

Thermal

Thermal

Pad

Pad

9

6
7
8

Place Rs and Cs across QL

RC snubber values shown
are for reference only,
tuning is required

MVDDC_FB

+MVDDC_S

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

NL701

NL701

1 2

PCMC063T-2R2MN

PCMC063T-2R2MN

ML701ML701

1 2

L701 2.2uH_13AL701 2.2uH_13A

1 2

R719

R719
33MOHM

33MOHM

1210
1%

C708

C708
10nF_25V

10nF_25V

402
X7R
25V

C715

C715
10UF

10UF

Rs

Cs

on PCB

C717

MULTI FOOTPRINT

R1

RFB1

R711

R711

4.99K

4.99K

402
1%

R4

RFB2

R710

R710

3.24K

3.24K

402
1%

C717

4.7uF_10V

4.7uF_10V

805 805

C713

C713

3.9nF

3.9nF

402
10%

R713

R713

3.65K

3.65K

402
5%

Place R1 and
R4 close to
PWM and
routed with
separate
20mil trace to
the ASIC

C716

C716
10UF

10UF

12061206

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

4.7uF_10V

4.7uF_10V

Use16V 0805 MLCCMirrored

Mirrored on PCB

16V
X7R

C719

C719

C718

C718

150nF_16V

150nF_16V

603

***

C725

C725
470uF_10V

470uF_10V

***

Over Lap

B701 60RB701 60R
R701 0RR701 0R

Over Lap

***

MC725

MC725
470uF_6.3V

470uF_6.3V

***

ALT POLY

Q701

Q701

QH

+PW_MVDDC_HGD +PW_MVDDC_HGDR

D D

C703

C703

0.22uF

0.22uF

MVDD_EN (10,11)

R708 20KR708 20K

+PW_MVDDC_LGD

402

+PW_MVDDC_M

R722 0RR722 0R

603

+MVDDC_B

U703

U703

1

BOOT

2

UGATE

3

+PW_MVDDC_LGD

R715

R715

42.2K

42.2K

List of supported foodprint
The following ICs are not necessarily evaluated by

ATI, please refer to BOM for evaluation status

ANPEC APW7120/APW7065 (12V)

C C

CAT CAT7583 (12V)
INTERSIL ISL6545
NEXSEM NX2114/2307
RICHTEK RT9214/RT8101
OnSemi ON1582
uPI UP6101 (No Ext_Vref in)
uPI UP6103 (with Ext_Vref in, can use voltage console UP6261 to change Vout)

GND
LGATE4VCC

APW7065

APW7065

PHASE

COMP

FB

8
7
6
5

+PW_MVDDC_M
MVDDC_COMP+PW_MVDDC_HGD

MVDDC_FB

+MVDD_VCC

R721 0RR721 0R

+PW_MVDDC_LGDR

402

Q702

Q702

QL

4 5
3
2
1

BSC119N03SG

BSC119N03SG

Thermal

Thermal

4 5
3
2
1

BSC119N03SG

BSC119N03SG

Pad

Pad

9

6
7
8

MVDDC_FB(10)

+PW_MVDDC_HGDR

MQ701

MQ701

+MVDDC_S

Thermal

B B

COMPENSATION CIRCUIT

402

C712

C712
390pF

390pF

50V

603

5%

NPO

R714 0RR714 0R

R7090RR709
0R

MVDDC_COMP

C714

C714
100nF

100nF

402

10V

X5R

10%

MVDDC_FB

C711

C711
15nF

15nF

10V

402
X7R

10%

R712

A A

R712

2.94K

2.94K

402
1%

8

FILTERED SMPS VCC BOOT CIRCUIT

+12V_BUS

7

+MVDD_VCC

R707

R707

2.2R

2.2R

C707

C707
100nF

100nF

+5V

MR707

MR707

2.2R

2.2R

603
X7R
5%

6

1

3

C705

C705
100nF

100nF

603 X7R
5%

2

16V

D701

D701
BAT54A

BAT54A

Thermal

Pad

Pad

4 5
3
2
1

FDS7096N3

FDS7096N3

+PW_MVDDC_M

+12V_BUS +5V

MR7060RMR706
0R

402

C706

C706
150nF_16V

150nF_16V

+MVDDC_B

+PW_MVDDC_M

R7060RR706
0R

402

9

6
7
8

1-Position the controller (U703) such that LGate(pin4) is the closet to gate
of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate
of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as
short and as wide as possible to reduce the trace inductance.
2-Place the bypass capacitors for Vcc as well as Boost caps as close to the
controller as possible. They are as follows;
Vcc bypass cap is C703, and Boost cap is C705.
3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place
the rest of the compensation network close to the pins 7 and 6. These are R710,
R711, R713, C713 and R712, C711 and C712.

5

+PW_MVDDC_LGDR

MQ702

MQ702

Thermal

Thermal

Pad

Pad

FDS7096N3

FDS7096N3

4

9

6
7
8

4 5
3
2
1

Layout guideline for Nexsem NX2114/2307

MULTI FOOTPRINT
For SO-8

3

SMPS02- Regulator for MVDD

Vout = 1.8V ~ 2.85V

Part RFB2RFB1

Vout

0.8V Ref

2.03V
(1.98V~2.08V)

1.8V
(1.78V~1.86V)

SMPS02 Specifications

Vin 12V(power stage) +/-8% PCIe ATX12V ver. 2.2 +/-5%

Vout 2V

Vout ripple (DC) 50mVpp

Iout 6Aavg, 8Adc_max

Step load 3Amax

Protections

+/-10% or 200mVpp @ 3A step loadVout ripple (AC)

Title

Title

Title
Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

4.99K
p/n 3160499100G

4.99K
p/n 3160499100G

Nominal Value Adjustable range / Notes

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Tolerance

;

;

+2%/-2%

;

~300kHzSwitching Freq. TBD

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

105-B170xx-00

105-B170xx-00

105-B170xx-00

3.24K
p/n 3160324100G

3.92K
p/n 3160392100G

1.8V ~ 2.85V

919Saturday, April 28, 2007

919Saturday, April 28, 2007

919Saturday, April 28, 2007

1

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8

D D

Linear Regulator for +MVDD
Vout = 1.8V ~ 2.1V
Iout = 2.75A MAX
P_REG = 1.35W
Tj(rise)max = 1.35Wx50C/W(50~70mm sq. Cu) = 67.5C

7

6

MEM PWR
INPUT

3.3V BUS
(3V3_BUS_F)

12V
(+VDDC_S)

INSTALL

R801
R802

R602
R701 or B701

5

DO NOT INSTALL

R602
R701 or B701

R801
R802

4

DDC3DATA(3,16)

DDC3CLK(3,16)

DDC3DATA
DDC3CLK

+3.3V_BUS

R1202

R1202

1.8R

1.8R

DCC to control VDDC1 and MVDD Voltage.

3

R1200 200RR1200 200R
R1201 200RR1201 200R

R1207 0RR1207 0R
R1208 0RR1208 0R

C1201

C1201

C1200

C1200

10uF

10uF

100nF

100nF

U1200

U1200

1

SDA

2

SCL
A111NC#12

9

A0

13

VCC

15

EPAD

3

GND

DS4402

DS4402

OUT0
OUT1

NC#14

NC#4
NC#5

2

Should be
placed near
SPMS, NOT
near U1200.

CUR_ADJ_0
CUR_ADJ_1

R1203 10KR1203 10K
R1204 10KR1204 10K

R1205 0RR1205 0R
R1206 0RR1206 0R

VDDC_FB (8)
MVDDC_FB (9)

8
10
12
14

4
5
6

FS1

7

FS0

1

Req = 1R/5 = 0.2R
P_Req = 0.2R * 2.75^2 = 1.5W
P_Reach = 1.5W/5 = 300mW < 500mW * 70%

+3.3V_BUS

C C

+5V

5.1K

5.1K
R872

C880

C880
1uF_6.3V

1uF_6.3V

C859

C859
1uF_6.3V

1uF_6.3V

1
2
3

R872

uP7706U8

uP7706U8

LDO4_POK

TP55TP55

C877

C877

10uF_X6S

10uF_X6S

LDO5_POK

MVDD_EN

10uF_X6S

10uF_X6S

C882

C882

MVDD_EN

C867

C867

10uF_X6S

10uF_X6S

+5V

MVDD_EN(9,11)

LDO4_VIN

LDO4_VO

TP56TP56

B B

MEM_PWR_CHANNEL(9)

LDO4_VIN

R887 0RR887 0R

U852

U852

1

POK

2

EN

3

VIN
CNTL4REFIN

uP7706U8

uP7706U8

U853

U853

8

POK

GND#8

7

EN

FB

6

VIN

VOUT

5

CNTL4REFIN

9

GND#9

Memory Power Channel
Source Selection

R801 0RR801 0R

DNI

GND#8

FB

VOUT

GND#9

R869 0RR869 0R

DNI

MEMORY POWER CHANNEL TO EASE LAYOUT CONGESTION OF LP BOARD. MEMORY
POWER CHANNEL CAN BE USED TO DELIVER SOURCE VOLTAGE TO MVDD SMPS OR
LINEAR REGULATORS (12V IN OR 3.3V IN)

1.0R each
1/2W, 1210

LDO4_VO

LDO4_FB

3V3_MREG_IN

R883R883

1/2W
1210

R862

R862

3.92K_0.1%

3.92K_0.1%

R5

R860

R860
10K_0.1%

10K_0.1%

0.1%

R4

R884R884

R885R885

C860

C860
33pF_50V

33pF_50V

C3

8
7
6
5
9

LDO4_VO

R861 0RR861 0R

DNI

R802 0RR802 0R

DNIDNI

VOUT = Vref x (1 + R5/R4)

C881

LDO5_FB

R870

R870

3.92K_0.1%

3.92K_0.1%

R867

R867
10K_0.1%

10K_0.1%

0.1%

R5

R4

C881
33pF_50V

33pF_50V

C3

C879

C879
10uF_X6S

10uF_X6S

VOUT = Vref x (1 + R5/R4)

R886R886R882R882

C869

C869
22uF_16V

22uF_16V

C884

C884
10uF_X6S

10uF_X6S

NC870

NC870
33uF_16V

33uF_16V

LDO4_VIN

C857

C857
10uF_X6S

10uF_X6S

DNIDNI

DNI

R877 0RR877 0R

C885

C885
100nF_6.3V

100nF_6.3V

+MVDD

PWRCNTL_1 PWRCNTL_0

GPIO_15GPIO_20

0

0

10

01

1

1

PWRCNTL_0(3,12)

PWRCNTL_1(3)

ASIC GPIO(x2) to control VDDC Voltage.

VDDC Voltage Settings Using GPIOs

Rf1=
Rf2=

+3.3V

R1240

R1240
10K

10K

R1248 0RR1248 0R

+3.3V

R1241

R1241
10K

10K

R1247 0RR1247 0R

011

Output Voltage (V)

Rf1=
Rf2=

PWRCNTL_0_S

R1242

R1242
100K

100K

DNI

PWRCNTL_1_SPWRCNTL_1_S

R1243

R1243
100K

100K

DNI

Rf1=
Rf2=

32

1

Rf1 Rf2

R1226

R1226

1.5K

1.5K

1% 1%

32

2N7002E

2N7002E
Q1200

Q1200

1

Power-up Default

R1221 0RR1221 0R

R1225

R1225

1.5K

1.5K

2N7002E

2N7002E
Q1201

Q1201

VDDC_FB (8)

+VDDC_S

A A

8

MEMORY POWER CHANNEL. SEE p. 10 FOR DETAILS.

R602 0RR602 0R

DNI

7

MEM_PWR_CHANNEL (9)

6

5

THESE ARE STITCHING CAPACITORS. THEIR PLACEMENT IS LAYOUT DEPENDANT.

+3.3V+3.3V_BUS +3.3V+VDDC+3.3V_BUS

C301

C301

C300

C300

100nF

100nF

100nF

100nF

4

C303

C303

C302

C302
100nF

100nF

MEM_PWR_CHANNEL(9)

100nF

100nF

C304

C304
100nF

100nF

3

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

105-B170xx-00

105-B170xx-00

105-B170xx-00

of

of

of

10 19Saturday, April 28, 2007

10 19Saturday, April 28, 2007

10 19Saturday, April 28, 2007

1

21

21

21

www.vinafix.vn

8

+VDDC

+12V_BUS

R843

R843

5.1K

5.1K

R842

R842

2.0K

2.0K

DNI

LDO2_POK

5%

Q840

Q840

1

MMBT3904

MMBT3904

2 3

POWER_SHDN(16)

+3.3V

R899

R899

5.1K

5.1K

R8411KR841
1K

D D

C841

C841
1uF_6.3V

1uF_6.3V

C C

R844 5.1KR844 5.1K

R846 5.1KR846 5.1K

R891 5.1KR891 5.1K

7

+5V

5.1K

5.1K
R845

R845

Q841

Q841

1

5%

5%

1

OSC_EN (3)

2 3

Q842

Q842
MMBT3904

MMBT3904

2 3

MMBT3904

MMBT3904

LDO3_EN
LDO2_EN

MVDD_EN (9,10)

6

Power up/down Sequencing

+1.8V_D2

5

R847 10KR847 10K

5%

C844

C844

100nF_6.3V

100nF_6.3V

4

+3.3V_BUS

Install only one of these

R8900RR890

0R
Q845

Q845
SI2304DS

SI2304DS

+12V_BUS

R848

R848

R849

R849

100K

100K

10K

10K

Q843

Q843

1

MMBT3904

MMBT3904

2 3

Q844

Q844

1

MMBT3904

MMBT3904

2 3

C843

C843
100NF

100NF

402
X5R
16V

C842

C842
10uF_X6S

10uF_X6S

3 2

3

+3.3V

1

LVT_EN (3)

R840

R840
100K

100K

Regulators for +5V, +5V_VESA and +5V_VESA2

+12V_BUS

1206

1/4W

5%

C810

C810
100nF

100nF

0603
16V

2

R811

R811

R812

R812
47R

47R

MR8120RMR812
0R

0805

1/8W

5%

1206

1/4W

MR811

MR811
27R

27R

47R

47R

0805

1/8W

Vout(V) = Vref (1+R2/R1)

MU810

MU810
MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

1

U810

U810

1

VIN

VOUT#2

5

NC

VOUT#3

8

NC#8

VOUT#6

ADJ4VOUT

LM317LCDR

LM317LCDR

1

+5V_VESA

3

GND

2
3

R813

R813

6

499R

499R

7

0402

R1

C811

C811

1uF_6.3V

1uF_6.3V

R814

R814

1.5K

1.5K

0402

R2

Overlap

DNIDNI

C852

C852
10uF_X6S

10uF_X6S

+MVDD

C863

C863
22uF_16V

22uF_16V

DNIDNI

C851

C851
10uF_X6S

10uF_X6S

B880 220R_2AB880 220R_2A

0805

MR880 0RMR880 0R

C862

C862
10uF_X6S

10uF_X6S

C854

C854
100nF

100nF

5

C861

C861
10uF_X6S

10uF_X6S

C864

C864
100nF

100nF

BUO

0805

R880 0RR880 0R

Place C490-492 near layer transitions (top/bottom).
THIS IS LAYOUT DEPENDENT.

+MVDD

C491

C491

C490

C490

100nF

100nF

100nF

100nF

4

C492

C492
100nF

100nF

+12V_BUS

R831

R831

MR831

MR8320RMR832

R832

R832

0R

47R

47R

1206

0805

1/4W

1/8W

5%

5%

C830

C830
100nF

100nF

0603
16V

Vout(V) = Vref (1+R2/R1)

3

MR831

47R

47R

27R

27R

1206

0805

1/4W

1/8W

5%

5%

MU830

MU830
MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

U830

U830

1

VIN

5

NC

8

NC#8
ADJ4VOUT

LM317LCDR

LM317LCDR

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

2

GND

1

VOUT#2
VOUT#3
VOUT#6

105-B170xx-00

105-B170xx-00

105-B170xx-00

3

2
3

R833

R833

6

499R

499R

7

0402

R1

C831

C831

1uF_6.3V

1uF_6.3V

R834

R834

1.5K

1.5K

0402

R2

of

of

of

11 19Saturday, April 28, 2007

11 19Saturday, April 28, 2007

11 19Saturday, April 28, 2007

1

+5V

21

21

21

LDO #2: Vout = +1.8V +/- 2%

Vin = 2.1V to 3.6V MAX Iout = 0.8A (TBV) RMS MAX

PCB: 50 to 70mm sq. copper area for cooling

TP861TP861

C868

C868
1uF_6.3V

1uF_6.3V

TP860TP860

U861

U861

1

POK

2

EN

3

VIN
CNTL4REFIN

uP7706U8

uP7706U8

GND#8

VOUT

GND#9

C865

R5
R4

C865
33pF_50V

33pF_50V

C3

R865

R865

12.7K_0.1%

8
7

FB

6

R866 0RR866 0R

5

DNI

9

LDO2_FB

12.7K_0.1%

R864

R864
10K_0.1%

10K_0.1%

0.1%

VOUT = Vref x (1 + R5/R4)

+3.3V_BUS +1.8V_LDO2+5V +1.8V_D2

R868

R868

LDO2_VIN

1206

LDO2_POK

0.50R

0.50R

Use 0.5R

B B

LDO2_EN

10uF_X6S

10uF_X6S

C866

C866

R868 (0.5R 1/2W or 0R 1206), R864, R865 & C865: To Be Verified

LDO #3: Vout = +1.1V +/- 2%

Vin = +1.45V to 2.1VMAX Iout = 1.1A (TBV) RMS MAX

PCB: 50 to 70mm sq. copper area for cooling

TP851TP851

TP850TP850

R858

R858

+MVDD

A A

1206
Use 0R

0.50R

0.50R

LDO3_VIN

LDO3_EN

C856

C856

10uF_X6S

10uF_X6S

C858

C858
1uF_6.3V

1uF_6.3V

U851

U851

1

POK

2

EN

3

VIN
CNTL4REFIN

uP7706U8

uP7706U8

GND#8

VOUT

GND#9

8
7

FB

6

R856 0RR856 0R

5
9

+1.1V+5V +1.1V

LDO3_FB

DNI

VOUT = Vref x (1 + R5/R4)

R855

R855

3.92K_0.1%

3.92K_0.1%

R5

R854

R854
10K_0.1%

10K_0.1%

0.1%

R4

C855

C855
33pF_50V

33pF_50V

C3

C853

C853
22uF_16V

22uF_16V

R854, R855 (3.92K) & C855: To Be Verified

Shared Power Rails

+1.8V_D2

+AVDD

B882

B882
BLM15BD121SN1

BLM15BD121SN1

8

+A2VDDQ

+VDD1DI +VDD2DI +DPLL_PVDD +TPVDD +TXVDDR +T2PVDD

B885

B883

B883
BLM15BD121SN1

BLM15BD121SN1

B884

B884
BLM15BD121SN1

BLM15BD121SN1

B885
BLM15BD121SN1

BLM15BD121SN1

7

B886

B886
BLM15BD121SN1

BLM15BD121SN1

B887

B887
BLM15BD121SN1

BLM15BD121SN1

6

B888

B888
BLM15BD121SN1

BLM15BD121SN1

B889

B889
BLM15BD121SN1

BLM15BD121SN1

www.vinafix.vn

5

D D

C C

B B

4

PSYNC
DVALID

PSYNC (3)
DVALID (3)

VID_[7..0](3)

3

+3.3V

DNI

DNI

DNI

DNI

DNI

NTSC

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

R50 10KR50 10K

R51 10KR51 10K

R52 10KR52 10K
R53 10KR53 10K

R54 10KR54 10K

R55 10KR55 10K
R56 10KR56 10K

R57 10KR57 10K

R58 10KR58 10K

R59 10KR59 10K
R63 10KR63 10K
R62 10KR62 10K
R61 10KR61 10K

R65 10KR65 10K
R64 10KR64 10K

R66 10KR66 10K

R67 10KR67 10K

R68 10KR68 10K

R69 10KR69 10K

R70 10KR70 10K

R71 10KR71 10K

R72 10KR72 10K

R73 10KR73 10K

R74 10KR74 10K

R75 10KR75 10K

R76 10KR76 10K

R77 10KR77 10K

R80 10KR80 10K
R79 10KR79 10K

R60 10KR60 10K

R87 10KR87 10K

R88 10KR88 10K

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

MR50 10KMR50 10K

MR51 10KMR51 10K

MR52 10KMR52 10K
MR53 10KMR53 10K

MR54 10KMR54 10K

MR55 10KMR55 10K
MR56 10KMR56 10K

MR57 10KMR57 10K

MR58 10KMR58 10K

MR59 10KMR59 10K
MR63 10KMR63 10K
MR62 10KMR62 10K
MR61 10KMR61 10K

MR65 10KMR65 10K
MR64 10KMR64 10K

MR66 10KMR66 10K

MR67 10KMR67 10K

MR68 10KMR68 10K

MR69 10KMR69 10K

MR70 10KMR70 10K

MR71 10KMR71 10K

MR72 10KMR72 10K

MR73 10KMR73 10K

MR74 10KMR74 10K

MR75 10KMR75 10K

MR76 10KMR76 10K

MR77 10KMR77 10K

MR80 10KMR80 10K
MR79 10KMR79 10K

MR60 10KMR60 10K

MR87 10KMR87 10K

MR46 10KMR46 10K

MR88 10KMR88 10K

2

PIN BASED STRAPS

GPIO_0

GPIO_1

GPIO_1

GPIO_2

GPIO_2
GPIO_3

GPIO_3

GPIO_4

GPIO_5

GPIO_5
GPIO_6

GPIO_6

GPIO_7GPIO_7

GPIO_7GPIO_7

GPIO_8

GPIO_9

GPIO_13

GPIO_13
GPIO_12

GPIO_12
GPIO_11GPIO_11

GPIO_11GPIO_11

GENERICC
GENERICB

A_VSYNC_DAC1

A_HSYNC_DAC1

PSYNC

PSYNC

GPIO21_BB_EN

VID_0

VID_0

VID_1

VID_1

VID_2

VID_2

VID_3

VID_3

VID_4VID_4

VID_5VID_5

VID_6

VID_6

VID_7

VID_7

A_VSYNC_DAC2
A_HSYNC_DAC2

DVALID

GPIO_22

GENERICC (3)
GENERICB (3)

A_VSYNC_DAC1 (3,13)

A_HSYNC_DAC1 (3,13)

GPIO21_BB_EN (3)

A_VSYNC_DAC2 (3,14)
A_HSYNC_DAC2 (3,14)

PWRCNTL_0 (3,10)

GPIO_22 (3)

GPIO_18 (3)

1

GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)

0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)

0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)

GPIO(3:2) - ATI Internal Use Only - Reserved (Default: 00)

GPIO(4) - DEBUG_ACCESS
ATI Internal Use Only - Reserved (Default: 0)

GPIO(5) - ATI Internal Use Only - Reserved (Default: 0)

GPIO(6) - ATI Internal Use Only - Reserved (Default: 0)

GPIO(7) - TV OUT STANDARD (Jumper position overwrite resistor settings)

0 - PAL TVO (Jumper is closed)
1 - NTSC TVO (Jumper is open)

GPIO(8) - ATI Internal Use Only - Reserved (Default: 0)

GPIO(9,13:11) - CONFIG[3..0] IF
BIOS_ROM_EN=1 [default] (GPIO_22)

M25P10A (1 Mbit) 0101
M25P20 (2 Mbit) 0101
Chingis (formerly PMC) ­ Pm25LV512 (512 kbit) 0100
Pm25LV010 (1 Mbit) 0101

GENERICC, GENERICB - ATI Internal Use Only - Reserved (Default: 0)

VSYNC - VIP_DEVICE_STRAP_EN

0: Slave VIP host port devices present (use if Theater is populated)
1: No slave VIP host port devices reporting presence during reset (use for
configurations without video-in)

HSYNC - ATI Internal Use Only - Reserved (Default 0)

PSYNC - VGA DISABLE : 1 for disable (set to 0 for normal operation)

GPIO_21 - ATI Internal Use Only - Reserved (Default: 0)

VID_0 - ATI Internal Use Only - Reserved (Default: 0)

VID_1 - MSI_DIS (Default: 0)

VID_2 - ATI Internal Use Only - Reserved (Default: 0)

VID_3 - BIF_AUDIO_EN
0 - Disable HD Audio 1- Enable HD Audio

VID_4 - ATI Internal Use Only - Reserved (Default: 0)

VID_5 - 64BAR_EN_A (Default: 0)
Enable 64-bit BARS

VID_6:7 - ATI Internal Use Only - Reserved (Default: 00)

VSYNC - DDR2 VENDOR SELECT
(see GPIO_18)

HSYNC2 - ATI Internal Use Only - Reserved

BIF_CLK_PM_EN
0 - Disable CLKREQ# power management capability
1 - Enable CLKREQ# power management capability

GPIO_15 - FOR FUTURE EXPANSION

GPIO_22_ROMCSb - Enable external BIOS ROM device (Default 1)

GPIO_18 - DDR2 MEM VENDOR [V2SYNC:GPIO_18]
QUIMONDA [0:0]
HYNIX [0:1]
SAMSUNG [1:0]

　tmel - AT25F512A (512 kbit)0010

AT25F1024A (1 Mbit)0011

ST Microelectronics- M25P05A ( 512 kbit) 0100

ATI Board Feature I

ATI PCIE FEATURE I

ATI PCIE FEATURE II

If BIOS_ROM_EN = 0, then Config[2:0]
defines the primary memory aperture size.
(Config 3 = don care).

x000 128MB
x001 256MB
x010 64MB
x011 32MB
x100 512MB
x101 1GB
x110 2GB
x111 4GB

(Default: 0)

ATI Board Feature I

GPIO_[13..0](3)

A A

5

4

www.vinafix.vn

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13

3

Pull-Down Resistors are for BU until built-in pull-downs are verified.

Overlap pads to save space
and to prevent assembly of
both resistors.

Layout

High logic voltageGround

Signal

2

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

105-B170xx-00

105-B170xx-00

105-B170xx-00

1

12 19Saturday, April 28, 2007

12 19Saturday, April 28, 2007

12 19Saturday, April 28, 2007

of

of

of

21

21

21

8

7

6

5

4

3

2

1

Optional ESD Protection Diodes

Place close to Connector
Pseudo differential RGB signals should be routed from the ASIC to the display connector without switching reference plane or running over split plane
Resistors are footprint options for the inductors. Footprints should be overlapped. (R1024-26)

DNI

R1024 0RR1024 0R
R1025 0RR1025 0R

DNI

R1026 0RR1026 0R

A_R_DAC1(3)

A_RB_DAC1(3)

D D

A_G_DAC1(3)

A_GB_DAC1(3)

A_B_DAC1(3)

A_BB_DAC1(3)

R1002

R1002

R1001

R1001

R1003

R1003

75R

75R

75R

75R

75R

R1029

R1029

37.4R

37.4R

R1028

R1028

37.4R

37.4R

R1027

R1027

37.4R

37.4R

75R

A_R_DAC1_M
A_G_DAC1_M
A_B_DAC1_M

C1002

C1002

C1001

C1001

8.0pF

8.0pF

8.0pF

8.0pF

402 402 402

L1004 47nHL1004 47nH
L1005 47nHL1005 47nH
L1006 47nHL1006 47nH

C1003

C1003

8.0pF

8.0pF

DNI

+3.3V +5V_VESA

D1001

D1001

4

CH3

5

Vp

6

CH4

CM1213-04

CM1213-04

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F

DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R

A_VSYNC_DAC1_R

3

CH2

2

Vn

1

CH1

Place close to Connector
SHOULD BE A LOW INDUCTANCE PATH TO PIN 5

D1002

D1002

4
5
6

CM1213-04

CM1213-04

CH3
Vp
CH4

2

Vn

1

CH1

C1010

C1010
68pF

68pF

603

603

+5V_VESA

MJ1001

MJ1001

1

R

2

G

3

B

11

MS0

12

MS1

4

MS2

15

MS3

9

NC

13

HS

14

VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8

10

VSS#10

16

CASE

17

CASE#17

G3179C219-005

G3179C219-005

3

CH2

SLIM VGA

+3.3V

R1004

R1004
10K

10K

C C

CRT1DDCDATA(3)

CRT1DDCCLK(3)

C1999 100nFC1999 100nF

A_HSYNC_DAC1(3,12)

A_VSYNC_DAC1(3,12)

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

B B

402

+3.3V +5V

R1007

R1007
10K

10K

402 402

+5V

U1999A

U1999A

14

2 3

1

7

4

5 6

74AHCT125

74AHCT125
U1999B

U1999B

74AHCT125

74AHCT125

A_HSYNC_DAC1_B

A_VSYNC_DAC1_B

+5V

1

1

R1005

R1005

2.2K

2.2K

402

DDCDATA_DAC1_5V DDCDATA_DAC1_R

32

BSH111

BSH111
Q1001

Q1001

R1008

R1008

2.2K

2.2K

402

DDCCLK_DAC1_5V

32

BSH111

BSH111
Q1002

Q1002

R1006 33RR1006 33R

R1009 33RR1009 33R

R1010

R1010

R1011

R1011

33R

33R

33R

33R

402

DDCCLK_DAC1_R

402

A_HSYNC_DAC1_R

402

A_VSYNC_DAC1_R

TjX2M(3)
TjX2P(3)

TjX4M(3)
TjX4P(3)

DDCCLK_DAC1_R
DDCDATA_DAC1_R
A_VSYNC_DAC1_R

TjX1M(3)

+3.3V

Q1021

Q1021

MMBT3904

MMBT3904

HPD1(3)

2 3

R1023

R1023
10K

10K

R1022 10KR1022 10K

1

TjX1P(3)
TjX3M(3)

TjX3P(3)

HPD_DVI1

TjX0M(3)
TjX0P(3)

TjX5M(3)
TjX5P(3)

TjXCP(3)
TjXCM(3)

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F
A_HSYNC_DAC1_R

DB15 pin

Standard VGA
Monitor ID bit 0

11

Monitor ID bit 1

12

Monitor ID bit 2

4

Monitor ID bit 3

15

N/C

9

Mechanical Key

Hardware
Support

No Yes Yes No Yes

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA

25

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C1
C2
C3
C4
C5
C6

26
27
28
29
30

DDC1 Host
Monitor ID bit 0

Data from display
Monitor ID bit 2
Open
+5V
50mA min
1A max

J1001

J1001

CASE
TMDS Data2-

TMDS Data2+
TMDS Data2/4 Shield
TMDS Data4­TMDS Data4+
DDC Clock
DDC Data
Analog VSYNC
TMDS Data1­TMDS Data1+
TMDS Data1/3 Shield
TMDS Data3­TMDS Data3+
+5V Power
GND (for +5V)
Hot Plug Detect
TMDS Data0­TMDS Data0+
TMDS Data0/5 Shield
TMDS Data5­TMDS Data5+
TMDS Clock Shield
TMDS Clock+
TMDS Clock-

Analog Red
Analog Green
Analog Blue
Analog HYNC
Analog GND
Analog GND#C6

CASE#26
CASE#27
CASE#28
CASE#29
CASE#30

DVI_CONNECTOR

DVI_CONNECTOR

DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max

DDC2AB Host
Monitor ID bit 0

SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max

DDC1/2 Display
Optional

SDA
Optional
SCL

Optional

A A

8

7

TMDS_2(Daul_Link) + DAC_1-CRT

6

5

4

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

3

Date: Sheet

2

105-B170xx-00

105-B170xx-00

105-B170xx-00

21

21

21

of

of

of

13 19Saturday, April 28, 2007

13 19Saturday, April 28, 2007

13 19Saturday, April 28, 2007

1

www.vinafix.vn

8

7

6

5

4

3

2

1

Optional ESD Protection Diods

Place close to Connector
Pseudo differential RGB signals should be routed from the ASIC to the display connector without switching reference plane or running over split plane

DNI

R2024 0RR2024 0R
R2025 0RR2025 0R

DNI

R2026 0RR2026 0R

A_R_DAC2(3)

A_RB_DAC2(3)

D D

A_G_DAC2(3)

A_GB_DAC2(3)

A_B_DAC2(3)

A_BB_DAC2(3)

R2029

R2029

37.4R

37.4R

C C

A_HSYNC_DAC2(3,12)

A_VSYNC_DAC2(3,12)

R2028

R2028

37.4R

37.4R

+3.3V

CRT2DDCDATA(3)

CRT2DDCCLK(3)

+3.3V +5V

9 8

10
13

12 11

R2003

R2003
75R

75R

R2027

R2027

37.4R

37.4R

1

R2004

R2004
10K

10K

402

1

R2007

R2007
10K

10K

402 402

U1999C

U1999C
74AHCT125

74AHCT125

A_HSYNC_DAC2_B

U1999D

U1999D
74AHCT125

74AHCT125

R2001

R2001

R2002

R2002

75R

75R

75R

75R

402

+5V

R2005

R2005

2.2K

2.2K

402

DDCDATA_DAC2_5V DDCDATA_DAC2_R

32

BSH111

BSH111
Q2001

Q2001

R2008

R2008

2.2K

2.2K

402

DDCCLK_DAC2_5V

32

BSH111

BSH111
Q2002

Q2002

C2001

C2001

8.0pF

8.0pF

402 402

C2002

C2002

8.0pF

8.0pF

A_R_DAC2_M
A_G_DAC2_M

A_B_DAC2_M

C2003

C2003

8.0pF

8.0pF

402

R2006 33RR2006 33R

R2009 33RR2009 33R

R2010

R2010

R2011

R2011

DNI

L2004 47nHL2004 47nH
L2005 47nHL2005 47nH
L2006 47nHL2006 47nH

OVERLAP

402

DDCCLK_DAC2_R

402

A_HSYNC_DAC2_R

33R

33R

402

A_VSYNC_DAC2_RA_VSYNC_DAC2_B

33R

33R

+3.3V +5V_VESA

D2001

A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F

DDCDATA_DAC2_R
DDCCLK_DAC2_R
A_HSYNC_DAC2_R

A_VSYNC_DAC2_R

A_R_DAC2_F
A_B_DAC2_F

DDCCLK_DAC2_R

D2001

4
5
6

CM1213-04

CM1213-04

CH3
Vp
CH4

+5V_VESA

3

CH2

2

Vn

1

CH1

J2

J2

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

Header_16_Pin_2X8

Header_16_Pin_2X8

A_G_DAC2_F

DDCDATA_DAC2_R
A_VSYNC_DAC2_RA_HSYNC_DAC2_R

2X8 HEADER FOR VGA RIBBON CONNECTOR

D2002

D2002

4

CH3

5

Vp

6

CH4

CM1213-04

CM1213-04

Place close to Connector

3

CH2

2

Vn

1

CH1

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

B B

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

8

7

6

5

4

3

TMDS_1(Single_Link) + DAC_2-CRT

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

105-B170xx-00

105-B170xx-00

105-B170xx-00

of

of

of

14 19Saturday, April 28, 2007

14 19Saturday, April 28, 2007

14 19Saturday, April 28, 2007

1

21

21

21

www.vinafix.vn

8

D D

7

6

5

4

3

2

1

C C

DAC2_Y(3)

R3001

R3001
75R

75R

DAC2_C(3)

R3002

R3002
75R

75R

DAC2_COMP(3)

R3003

R3003
75R

75R

B B

Install for Dell

R3011 0RR3011 0R

402

Component (Y)
Component (Pr)
Component (Pb)

A A

DAC2_C_F
DAC2_COMP_F

GENERICA(3)

R3004 0RR3004 0R
R3005 0RR3005 0R
R3006 0RR3006 0R

DNI for Dell

Place near connector
0R leaves footprint for Ferrite
Beads if req'd for EMI

+3.3V

Install for Dell

R3010 0RR3010 0R

R3008

R3008
10K

10K

DAC2_Y_DINDAC2_Y_F
DAC2_C_DIN
DAC2_COMP_DIN

402

STV/HDTV#_DET PIN6

402
402
402

C3007

C3007
82pF

82pF

DNI for Dell

R3009 0RR3009 0R

C3008

C3008
82pF

82pF

402

C3009

C3009
82pF

82pF

402402 402

R30070RR3007
0R

DNI for Dell

DNI for Dell

The 7-pin MiniDIN footprint allows one of the two MiniDINs:

- 7-pin Svideo/Composite MiniDIN P/N 6071001500G

- 4-pin Svideo MiniDIN P/N 6070001000G

L3001 470nH_250mAL3001 470nH_250mA

C3001

C3001
47pF_50V

47pF_50V

L3002 470nH_250mAL3002 470nH_250mA

C3002

C3002
47pF_50V

47pF_50V

L3003 470nH_250mAL3003 470nH_250mA

C3003

C3003
47pF_50V

47pF_50V

Install for Dell only when it's needed for EMI

C3010

C3010
82pF

82pF

DAC2_Y_F

C3004

C3004
47pF_50V

47pF_50V

DAC2_C_F

C3005

C3005
47pF_50V

47pF_50V

DAC2_COMP_F

C3006

C3006
47pF_50V

47pF_50V

TV Out

J3001

J3001

6

HDTV_OUT_DET#

3

Y-OUT

4

C-OUT

7

Comp_out

CompIn

5

SYNC

1

GND

2

GND#2

8

Rpin5

CASE

9

CASE#9

10

CASE#10

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

8

7

6

5

www.vinafix.vn

4

3

Date: Sheet

2

105-B170xx-00

105-B170xx-00

105-B170xx-00

21

21

21

of

of

of

15 19Saturday, April 28, 2007

15 19Saturday, April 28, 2007

15 19Saturday, April 28, 2007

1

8

7

6

5

4

3

2

1

LM63 is for RV610 BU, until built-in fan controller is verified.

+3.3V

CAP CER 10UF 10% 6.3V X5R

INTERFACE INFO: SMBUS SLAVE
Clock: Min 10kHz - Max 100kHz
7 bit address: 100 1100

SCL_R
SDA_R
TACH

C4005

C4005
56pF_50V

56pF_50V

402
NPO

(0805)1.4MM MAX THICK

C4006

C4006
56pF_50V

56pF_50V

402
NPO

R4003

R4003
10K

10K

D D

DNI

R4017

R4017
10K

10K

R4001 100RR4001 100R
R4002 100RR4002 100R
R4015 0RR4015 0R

DNI

R4028

R4028
10K

10K

402

402

DDC3CLK(3,10)

DDC3DATA(3,10)

For RV610 BU, to verify built-in fan controller with 2-pin fan

C C

MMBT3906

MMBT3906

Q4002

Q4002

23

Qx

1

+3.3V

C4001

C4001

10uF

10uF

U4001

U4001

8

SMBCLK

7

SMBDAT

6

ALERT
GND5PWM

LM63CIMAX

LM63CIMAX

R4009

R4009
100K

100K

402 402

R4018 0RR4018 0R

1

2 3

C4002

C4002

1uF_6.3V

1uF_6.3V

402 402

6.3V
X5R

VDD

R4011

R4011
100K

100K

Q4003

Q4003
MMBT3904

MMBT3904

R4012 10KR4012 10K

R4013

R4013

1.47K

1.47K

402

C4003

C4003

100pF_50V

100pF_50V

50V
NPO

D+
D-

H2

H2
RV610_LP_HEATSINK

23567

RV610_FANSINK

RV610_FANSINK

RV610_LP_HEATSINK

8

H3B

H3B

9

10111213141516

H3D

H3D

25262728293031

RV610_FANSINK

RV610_FANSINK

RV610_FANSINK

RV610_FANSINK

32

R4004

R4004
10K

10K

H3A

H3A

RV610_FANSINK

RV610_FANSINK

1

H3C

H3C

17181920212223

32

MQ4004

MQ4004

2SB1188

2SB1188

GPU_DPLUS

GPU_DMINUS

1
2
3
4

402

PWM

C4004

C4004

2.2nF_50V

2.2nF_50V

402
50V
X7R

1

+12V_BUS

GPU_DPLUS (3)

GPU_DMINUS (3)ThermINT(3)

B4001

B4001
26R_600mA

26R_600mA

R40140RR4014
0R

402

DNI

C4010

C4010
10uF

10uF

C4008

C4008
1uF

1uF

805
16V
Y5V

JU4001JU4001

1
2

C4007

C4007
1uF

1uF

805
16V
Y5V

R4010 0RR4010 0R

CRITICAL TEMPERATURE FAULT

POWER_SHDN(11)

+3.3V_BUS

C1250

C1250
100nF

100nF

U1250A

U1250A
74LCX74

74LCX74

+3.3V_BUS

+3.3V

1

R1251

R1251
10K

10K

CTFb

CTFb(3)

6

5

www.vinafix.vn

4

3

Q1250

Q1250
BSH111

BSH111

R1253 0RR1253 0R

2

D

3

CP

R1250 10KR1250 10K

12

D

11

CP

+3.3V_BUS

32

DNI

R1252

R1252
10K

10K

4

14

5

S

Q

5V

6

Q

GND7C

1

C1251

C1251

100nF

100nF

10

9

S

C

13

Q

Q

U1250B

U1250B
74LCX74

74LCX74

10K

10K

8

R1259

R1259

R1257

R1257
100K

100K

2

VDD_EN

MMBT3904

MMBT3904

Q1251

Q1251

1

2 3

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

VDD_EN (1,8)

105-B170xx-00

105-B170xx-00

105-B170xx-00

of

of

of

16 19Saturday, April 28, 2007

16 19Saturday, April 28, 2007

16 19Saturday, April 28, 2007

1

21

21

21

Warning: TS_FDO is not 5V
tolerant. MAX sink current

1.65mA

402

PWM

+3.3V

B B

TS_FDO(3)

A A

TP4002TP4002

8

R4032

R4032

2.61K

2.61K

R4016 1KR4016 1K

DNI

R4033

R4033
100R

100R

R40050RR4005
0R

402

Q4001

Q4001

1

MMBT3904

MMBT3904

2 3

+12V_BUS

R4006

R4006

2.61K

2.61K

402

1%

R4008 100KR4008 100K

402

R40071KR4007
1K

402
1%

7

5

DVI/VGA SCREWS

ASSY-SCREW2

ASSY-SCREW1

ASSY-SCREW1

SCREW

SCREW

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

ASSY

ASSY

ASSY-SCREW3

ASSY-SCREW3

SCREW

SCREW

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

D D

ASSY

ASSY

C C

ASSY-SCREW2

SCREW

SCREW

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

ASSY

ASSY

ASSY-SCREW4

ASSY-SCREW4

SCREW

SCREW

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

ASSY

ASSY

ASSY1

ASSY1

BRACKET

BRACKET

8020040100G

8020040100G

ASSY2

ASSY2

BRACKET

BRACKET
LP

LP

8020040400G

8020040400G

ASSY-SCREW5

ASSY-SCREW5

SCREW

SCREW

SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L

SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L

4

MT1

MT1
MT_Hole_0.136_in.

MT_Hole_0.136_in.

DNI DNI

MT2

MT2
MT_Hole_0.136_in_6VIA

MT_Hole_0.136_in_6VIA

3

2

1

B B

A A

<Variant Name>

<Variant Name>

<Variant Name>

5

4

www.vinafix.vn

3

2

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

105-B170xx-00

105-B170xx-00

105-B170xx-00

1

of

of

of

17 19Saturday, April 28, 2007

17 19Saturday, April 28, 2007

17 19Saturday, April 28, 2007

21

21

21

5

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

REVISION HISTORY

REVISION HISTORY

REVISION HISTORY

D D

Sch

Sch

Sch
Rev

Rev

Rev

PCB

PCB

PCB
Rev

Rev

Rev

00B014

Date

Date

Date

2007.02.22

RM C890/MC890, RM B801/L801/ML801

4

NOTE:

NOTE:

NOTE:

3

105-B170xx-00

105-B170xx-00

105-B170xx-00

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU.
For Stuffing options (component values, DNI , ? please consult the product specific BOM.

For Stuffing options (component values, DNI , ? please consult the product specific BOM.　

For Stuffing options (component values, DNI , ? please consult the product specific BOM.　
Please contact ATI representative to obtain latest BOM closest to the application desired.

Please contact ATI representative to obtain latest BOM closest to the application desired.

Please contact ATI representative to obtain latest BOM closest to the application desired.

REVISION DESCRIPTION

REVISION DESCRIPTION

REVISION DESCRIPTION

2

Date:Schematic No.

Date:Schematic No.

Date:Schematic No.

Saturday, April 28, 2007

Saturday, April 28, 2007

Saturday, April 28, 2007

1

Rev

Rev

Rev

21

21

21

015 00B

016

00B

017 00B

00B018

C C

019 00C

00C020

00

021

B B

2007.02.27

2007.02.28

2007.03.06

2007.03.06

2007.04.17

2007.04.19

2007.04.25

ADD R4010 FOR FAN CIRCUIT. ADD STITCHING CAPS C300, C301, C302, C303

CORRECT "300" TO C300; ADD C304, CHNG C301;

POWER SUPPLY CHANGES: ADD MC627, R615, R609, R715, R709, R714, R614; REMOVE MC630, MC624;

DUE TO LAYOUT CONSTRAINTS: RM ML601. CHANGE C627, MC627.

REMOVE R90, Q90 (A12+ ASIC REMOVES NEED FOR THESE PARTS); REMOVE C850 (IS NOT POPULATED ON ANY BOM - WILL CAUSE VDDC TO BE UNSTABLE); ADD C4010 (FOR FAN SPIN UP);

ADD C490, C491, C492 FOR POSSIBLE MEMORY SIGNAL INTEGRITY/EMI IMPROVEMENTS (PER EMI TEAM);

NO NETLIST/LAYOUT CHANGES. SCHEMATIC UPDATE NOTES p.12 (V2SYNC/GPIO_18 CLARIFICATION)

A A

5

4

www.vinafix.vn

3

2

1

5

4

3

2

1

MEMORY CHANNEL A

D D

DDR3 8M/16Mx32

MEMORY CHANNEL B

DDR3 8M/16Mx32

External TMDS

MEM A

POWER
REGULATION

From +12V

VDDC, MVDD

From +12V LINEAR:

+5V, +5V_VESA,

C C

+5V_VESA2, RageTheater

From +12V DIRECT:

FAN

From +3.3V LINEAR:

VDDC_CT, MPVDD, PVDD,
TPVDD, T2PVDD, TXVDDR,
T2XVDDR, AVDD, A2VDD,
VDD1DI, VDD2DI,
PCIE, VDDR3, VDDR4,
VDDR5, VDDRH

MVDD

FAN

Straps

BIOS

Speed control
& temperature
sense

INTERRUPT

Temp. Sensing

GPIO

ROM

DDC3
GPIO17

D+/D-

RV5XX

POWER DELIVERY

+PCIE_SOURCE

B B

+3.3V

3.3V_BUS
delayed circuit

+12V_BUS

PCI-Express

MEM B

Dual-Link LVTM

GPIO14

DAC2

CRT

H/V2Sync

DDC2

TVO

XTALIN/OUT

MPP
VIP

DAC1

CRT

H/VSync

DDC1

Dual-Link TMDS

HPD1

XTAL

Oscillator

TMDS matching

TMDS matching

RBG Filters

TVO Filters

XTALIN/OUT
CLKOUT

RageTheater

RBG Filters

HPD

HPD

DVI-I

&

Slim-VGA

CONN

TVO/VIVO

CONN

DVI-I

&

Slim-VGA

CONN

SMPS Enable
Circuit

+3.3V_BUS
+12V_BUS

PCI-Express Bus

RV610 GDDR3-136 FH 6-Layer

REV 0

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

RH RV610 128MB DDR2-BGA84 16MX16 VO dDVI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

5

4

www.vinafix.vn

3

2

Date: Sheet

105-B170xx-00

105-B170xx-00

105-B170xx-00

1

21

21

21

of

of

of

19 19Saturday, April 28, 2007

19 19Saturday, April 28, 2007

19 19Saturday, April 28, 2007