MSI MS-V099 Schematic 10

8

7

6

5

4

3

2

1

+12V_BUS

C1

CAP CER 10UF 20% 16V X5R

10UFC110UF

(1206)1.8MM H MAX

+12V_BUS

C3

D D

C C

B B

C2

150nF_16V

150nF_16VC2150nF_16V

LF CAP CER 150NF 10% 16V X7R (0603)

+3.3V_BUS

CAP CER 10UF 10% 6.3V X6S (0805)1.4MM MAX THICK

C4 10uF_X6SC410uF_X6S

+3.3V_BUS

C5

C6

100nF_6.3VC5100nF_6.3V

1uF_6.3VC61uF_6.3V

Place these caps as close to the PCIE connector as possible

TEST_EN_R(3)

HSYNC1_TRST(3)

C0 10nFC010nF

TP6

TP6 35mil

35mil

TR150RTR15

0R

DNI

PETn0_GFXRn0(2)

PETp1_GFXRp1(2) PETn1_GFXRn1(2)

PETp2_GFXRp2(2) PETn2_GFXRn2(2)

PETp3_GFXRp3(2) PETn3_GFXRn3(2)

PETp4_GFXRp4(2) PETn4_GFXRn4(2)

PETp5_GFXRp5(2) PETn5_GFXRn5(2)

PETp6_GFXRp6(2) PETn6_GFXRn6(2)

PETp7_GFXRp7(2) PETn7_GFXRn7(2)

PETp8_GFXRp8(2) PETn8_GFXRn8(2)

PETp9_GFXRp9(2) PETn9_GFXRn9(2)

PETp10_GFXRp10(2) PETn10_GFXRn10(2)

PETp11_GFXRp11(2) PETn11_GFXRn11(2)

PETp12_GFXRp12(2) PETn12_GFXRn12(2)

PETp13_GFXRp13(2) PETn13_GFXRn13(2)

PETp14_GFXRp14(2) PETn14_GFXRn14(2)

PETp15_GFXRp15(2) PETn15_GFXRn15(2)

TEST_EN_R JTAG_TRST#

PRESENCE

PCI-EXPRESS EDGE CONNECTOR

+3.3V_BUS

+12V_BUS

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

+12V#B1 +12V#B2 +12V#B3 GND#B4 SMCLK SMDAT GND#B7 +3.3V#B8 JTAG1

3.3Vaux WAKE#

RSVD#B12 GND#B13 PETp0 PETn0 GND#B16 PRSNT2#B17 GND#B18 PETp1 PETn1 GND#B21 GND#B22 PETp2 PETn2 GND#B25 GND#B26 PETp3 PETn3 GND#B29 RSVD#B30 PRSNT2#B31 GND#B32 PETp4 PETn4 GND#B35 GND#B36 PETp5 PETn5 GND#B39 GND#B40 PETp6 PETn6 GND#B43 GND#B44 PETp7 PETn7 GND#B47 PRSNT2#B48 GND#B49 PETp8 PETn8 GND#B52 GND#B53 PETp9 PETn9 GND#B56 GND#B57 PETp10 PETn10 GND#B60 GND#B61 PETp11 PETn11 GND#B64 GND#B65 PETp12 PETn12 GND#B68 GND#B69 PETp13 PETn13 GND#B72 GND#B73 PETp14 PETn14 GND#B76 GND#B77 PETp15 PETn15 GND#B80 PRSNT2#B81 RSVD#B82

x16 PCIe

Mechanical Key

PRSNT1#A1

+12V#A2 +12V#A3 GND#A4

JTAG2 JTAG3 JTAG4 JTAG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12 REFCLK+ REFCLKGND#A15

PERp0 PERn0

GND#A18

RSVD#A19

GND#A20

PERp1

PERn1 GND#A23 GND#A24

PERp2

PERn2 GND#A27 GND#A28

PERp3

PERn3 GND#A31

RSVD#A32 RSVD#A33

GND#A34

PERp4

PERn4 GND#A37 GND#A38

PERp5

PERn5 GND#A41 GND#A42

PERp6

PERn6 GND#A45 GND#A46

PERp7

PERn7 GND#A49

RSVD#A50

GND#A51

PERp8

PERn8 GND#A54 GND#A55

PERp9

PERn9 GND#A58 GND#A59

PERp10

PERn10 GND#A62 GND#A63

PERp11

PERn11 GND#A66 GND#A67

PERp12

PERn12 GND#A70 GND#A71

PERp13

PERn13 GND#A74 GND#A75

PERp14

PERn14 GND#A78 GND#A79

PERp15

PERn15 GND#A82

MPCIE1

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

PERp0 PERn0

PERp1 PERn1

PERp2 PERn2

PERp3 PERn3

PERp4 PERn4

PERp5 PERn5

PERp6 PERn6

PERp7 PERn7

PERp8 PERn8

PERp9 PERn9

PERp10 PERn10

PERp11 PERn11

PERp12 PERn12

PERp13 PERn13

PERp14 PERn14

PERp15 PERn15

+3.3V_BUS+12V_BUS

PRESENCE

JTCK JTDI JTDO JTMS

R2 0RR2 0R

PERST#

C7 100nF_6.3VC7100nF_6.3V

C9 100nF_6.3VC9100nF_6.3V

C11

C11 100nF_6.3V

100nF_6.3V

C13

C13 100nF_6.3V

100nF_6.3V

C15

C15 100nF_6.3V

100nF_6.3V

C17

C17 100nF_6.3V

100nF_6.3V

C19

C19 100nF_6.3V

100nF_6.3V

C21

C21 100nF_6.3V

100nF_6.3V

C23

C23 100nF_6.3V

100nF_6.3V

C25

C25 100nF_6.3V

100nF_6.3V

C27

C27 100nF_6.3V

100nF_6.3V

C29

C29 100nF_6.3V

100nF_6.3V

C31

C31 100nF_6.3V

100nF_6.3V

C33

C33 100nF_6.3V

100nF_6.3V

C35

C35 100nF_6.3V

100nF_6.3V

C37

C37 100nF_6.3V

100nF_6.3V

No JTAG

C8 100nF_6.3VC8100nF_6.3V

C10

C10 100nF_6.3V

100nF_6.3V

C12

C12 100nF_6.3V

100nF_6.3V

C14

C14 100nF_6.3V

100nF_6.3V

C16

C16 100nF_6.3V

100nF_6.3V

C18

C18 100nF_6.3V

100nF_6.3V

C20

C20 100nF_6.3V

100nF_6.3V

C22

C22 100nF_6.3V

100nF_6.3V

C24

C24 100nF_6.3V

100nF_6.3V

C26

C26 100nF_6.3V

100nF_6.3V

C28

C28 100nF_6.3V

100nF_6.3V

C30

C30 100nF_6.3V

100nF_6.3V

C32

C32 100nF_6.3V

100nF_6.3V

C34

C34 100nF_6.3V

100nF_6.3V

C36

C36 100nF_6.3V

100nF_6.3V

C38

C38 100nF_6.3V

100nF_6.3V

JTAG

RP1A0R RP1A0R

8 1

RP1B0R RP1B0R

7 2

RP1C0R RP1C0R

6 3

RP1D0R RP1D0R

5 4

PCIE_REFCLKP (2) PCIE_REFCLKN (2)PETp0_GFXRp0(2)

GFXTp0_PERp0 (2) GFXTn0_PERn0 (2)

GFXTp1_PERp1 (2) GFXTn1_PERn1 (2)

GFXTp2_PERp2 (2) GFXTn2_PERn2 (2)

GFXTp3_PERp3 (2) GFXTn3_PERn3 (2)

GFXTp4_PERp4 (2) GFXTn4_PERn4 (2)

GFXTp5_PERp5 (2) GFXTn5_PERn5 (2)

GFXTp6_PERp6 (2) GFXTn6_PERn6 (2)

GFXTp7_PERp7 (2) GFXTn7_PERn7 (2)

GFXTp8_PERp8 (2) GFXTn8_PERn8 (2)

GFXTp9_PERp9 (2) GFXTn9_PERn9 (2)

GFXTp10_PERp10 (2) GFXTn10_PERn10 (2)

GFXTp11_PERp11 (2) GFXTn11_PERn11 (2)

GFXTp12_PERp12 (2) GFXTn12_PERn12 (2)

GFXTp13_PERp13 (2) GFXTn13_PERn13 (2)

GFXTp14_PERp14 (2) GFXTn14_PERn14 (2)

GFXTp15_PERp15 (2) GFXTn15_PERn15 (2)

TP2TP2

TP1TP1

TP3TP3

TP4TP4

VSYNC1_TCK (3)

DDC1DATA_TDI (3) DDC3CLK_TDO (3) DDC1CLK_TMS (3)

+3.3V

53

1 2

R_RST

R3 0RR3 0R

C39

C39 100nF

100nF

NC7SZ08P5X_NL

4

U5

PERST#_buf (2)

Place R3 in U5

SYMBOL LEGEND

DO NOT

DNI

INSTALL

#

ACTIVE LOW

DIGITAL GROUND

ANALOG

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3 - PCI-E Edge Connector

Size Document Number Rev

C

Date: Sheet

8

7

6

5

www.vinafix.vn

4

3

Date: Sheet

2

105-B148xx-00D

GROUND

BUO BRING UP

ONLY

of

121Wednesday, May 09, 2007

1

3

5

D D

4

3

2

1

NOTE: some of the PCIE testpoints will be available trought via on traces.

PETp0_GFXRp0(1) PETn0_GFXRn0(1)

PETp1_GFXRp1(1) PETn1_GFXRn1(1)

PETp2_GFXRp2(1) PETn2_GFXRn2(1)

PETp3_GFXRp3(1) PETn3_GFXRn3(1)

PETp4_GFXRp4(1) PETn4_GFXRn4(1)

PETp5_GFXRp5(1) PETn5_GFXRn5(1)

PETp6_GFXRp6(1)

C C

B B

PCIE_REFCLKP(1) PCIE_REFCLKN(1)

PETn6_GFXRn6(1)

PETp7_GFXRp7(1) PETn7_GFXRn7(1)

PETp8_GFXRp8(1)

PETp9_GFXRp9(1) PETn9_GFXRn9(1)

PETp10_GFXRp10(1) PETn10_GFXRn10(1)

PETp11_GFXRp11(1) PETn11_GFXRn11(1)

PETp12_GFXRp12(1) PETn12_GFXRn12(1)

PETp13_GFXRp13(1) PETn13_GFXRn13(1)

PETp14_GFXRp14(1) PETn14_GFXRn14(1)

PETp15_GFXRp15(1) PETn15_GFXRn15(1)

DNI DNI

R13

R14

51R

402 402

TP11TP11

TP12TP12

TP13TP13

TP14TP14

TP19TP19

TP20TP20

TP21TP21

TP22TP22

TP27TP27

TP28TP28

TP7TP7

TP8TP8

TP9TP9

TP10TP10

TP15TP15

TP16TP16

TP17TP17

TP18TP18

TP23TP23

TP24TP24

TP25TP25

TP26TP26

PERST#_buf(1)

AK33

AJ33

AJ35 AJ34

AH35 AH34

AG35 AG34

AF33 AE33

AE35 AE34

AD35 AD34

AC35 AC34

AB33 AA33

AA35 AA34

W35 W34

AJ31 AJ30

AM32

Y35 Y34

V33 U33

U35 U34

T35 T34

R35 R34

U1A

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

PCIE_RX8P PCIE_RX8N

PCIE_RX9P PCIE_RX9N

PCIE_RX10P PCIE_RX10N

PCIE_RX11P PCIE_RX11N

PCIE_RX12P PCIE_RX12N

PCIE_RX13P PCIE_RX13N

PCIE_RX14P PCIE_RX14N

PCIE_RX15P PCIE_RX15N

Clock

PCIE_REFCLKP PCIE_REFCLKN

PERSTB

PART 1 OF 7

P

P C

C I

I

-

E

E X

X P

P R

R E

E S

S S

S

I

I N

N T

T E

E R

R F

F A

A C

C E

E

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

Calibration

PCIE_CALRN PCIE_CALRP

PCIE_CALI

AG31 AG30

AF31 AF30

AF28 AF27

AD31 AD30

AD28 AD27

AB31 AB30

AB28 AB27

AA31 AA30

AA28 AA27

W31 W30

W28 W27

V31 V30

V28 V27

U31 U30

U28 U27

R31 R30

AG26 AJ27

AK29

R9

1.27KR91.27K

GFXTp0_PERp0 (1) GFXTn0_PERn0 (1)

GFXTp1_PERp1 (1) GFXTn1_PERn1 (1)

GFXTp2_PERp2 (1) GFXTn2_PERn2 (1)

GFXTp3_PERp3 (1) GFXTn3_PERn3 (1)

GFXTp4_PERp4 (1) GFXTn4_PERn4 (1)

GFXTp5_PERp5 (1) GFXTn5_PERn5 (1)

GFXTp6_PERp6 (1) GFXTn6_PERn6 (1)

GFXTp7_PERp7 (1) GFXTn7_PERn7 (1)

GFXTp8_PERp8 (1) GFXTn8_PERn8 (1)PETn8_GFXRn8(1)

GFXTp9_PERp9 (1) GFXTn9_PERn9 (1)

GFXTp10_PERp10 (1) GFXTn10_PERn10 (1)

GFXTp11_PERp11 (1) GFXTn11_PERn11 (1)

GFXTp12_PERp12 (1) GFXTn12_PERn12 (1)

GFXTp13_PERp13 (1) GFXTn13_PERn13 (1)

GFXTp14_PERp14 (1) GFXTn14_PERn14 (1)

GFXTp15_PERp15 (1) GFXTn15_PERn15 (1)

+PCIE_VDDC

402

R82.0K R82.0K

402

R102.0K R102.0K

For Tektronix LA only

Place close to ASIC

A A

5

4

RV630

www.vinafix.vn

3

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3 - ASIC PCIE_Interface

Size Document Number Rev

C

Date: Sheet

2

Date: Sheet

105-B148xx-00D

1

3

of

221Wednesday, May 09, 2007

5

Recommended caps: (see BOM for qualified values/vendors) 10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK 1uF, X6S, 0402, 6.3V 100nF, X7R, 0402 10nF , X7R, 0402

D D

R107 0RR107 0R

+1.8V

+12V_BUS

MR108

MR108 10K

10K

LVT_EN(14)

+3.3V

C C

MR1090RMR109 0R

Share one pad

B B

SI2304DS

R1090RR109 0R

DNI

SI2304DS

R108 0RDNIR108 0RDNI

+3.3V

TR40

4.7K

BUO

TP40

TP40 TP41

TP41

35mil

35mil 35mil

35mil

TEST_EN_R(1)

DNI

Q100

32

1

32

Q101

I2C DEVICE ADDRESS' ON DDC3

DEVICE LM63

TR41

DP

4.7K

BUO

DDC3CLK_TDO(1) DDC1CLK_TMS(1)

T2XCM(15) T2XCP(15)

T2X0M(15)

T2X0P(15)

T2X1M(15)

T2X1P(15)

T2X2M(15)

T2X2P(15)

T2X3M(15)

T2X3P(15)

T2X4M(15)

T2X4P(15)

T2X5M(15)

T2X5P(15)

+T2PVDD

DDC3DATA(18)

Use 0R

BLM15BD121SN1

ADDRESS x100 1100 TBD

DDC3CLK(18)

TR11 0RTR11 0R TR12 0RTR12 0R

R71KR7 1K

DNI

Share one PAD

C81

C81 1uF_6.3V

1uF_6.3V

XTALOUT_S

C80

C80 100nF_6.3V

100nF_6.3V

XTALOUT_S is done for ease of layout

5

Y81

4

VCC

2

GND

27.000MHz

XTALIN_S

XTALOUT_S

OUT

E/D

+3.3V_BUS

B80

B80 BLM15BD121SN1

BLM15BD121SN1

A A

C82 12pF_50V

12pF_50V

2 1

C83

C83 12pF_50V

12pF_50V

Y82

27.000MHz_10PPM

B100

DNI

R106 100RR106 100R

R100 100RR100 100R

R101 100RR101 100R

R102 100RR102 100R

R103 100RR103 100R

R104 100RR104 100R

R105 100RR105 100R

NS100

10uF_X6S

NS_VIA

1 2

GND_T2PVSS

C108

1uF_6.3V

B101

+3.3V

R40

4.7K

402 402

MR71KMR7 1K

+1.8V

NR81 182RNR81 182R

3 1

R81 182RR81 182R

R841MR84 1M

Place R_RTCLK close to XTAL so the main clock line has shortest stub

C100

C109

10uF_X6S

DDC1DATA_TDI(1)

R41

4.7K

R44 110RR44 110R

Share one pad

OSC_EN

R85 0RR85 0RC82

R_RTCLK

MR86 0RMR86 0R

+LTVDD18

C103

100nF_6.3V

+LTVDD33

C107

1uF_6.3V

CRT1DDCDATA(15)

CRT1DDCCLK(15)

CRT2DDCDATA(16)

CRT2DDCCLK(16)

DDC3DATA DDC3CLK

R43

R43 221R

221R C46

C46 100nF_6.3V

100nF_6.3V

C101

C101 100nF_6.3V

100nF_6.3V

GPU_DMINUS(18) GPU_DPLUS(18)

TS_FDO(18)

TP42

TP42 35mil

35mil

PLL_TEST TEST_EN

T2XCM T2XCP

T2X0M T2X0P

T2X1M T2X1P

T2X2M T2X2P

T2X3M T2X3P

T2X4M T2X4P

T2X5M T2X5P

C102

C102 1uF_6.3V

1uF_6.3V

C105

C105 100nF_6.3V

100nF_6.3V

DNI

TR13 0RTR13 0R

HPD1(16)

SDA(7)

SCL(7)

VREFG

XTALIN XTALOUT

R82

R82 221R

221R

4

AP22 AR22

AN22 AN23

AR23 AP23

AR24 AP24

AR25 AP25

AN26 AN27

AR27 AP27

AK22

AK27

AH26

AN21 AN24 AN25 AN28 AP21 AP26 AR21 AR26

AM22 AM24 AM26 AM27

AM29

AH15

AH14 AG14

AG21

AH19 AM30

AD12

AR33 AP33

MR82

MR82 221R

221R

Share one pad

OSC_EN (14)

4

AL22

AL27

AJ26

AJ22

AJ24

AL29 AJ15

AG6

AK6 AM6

AK4 AM4

AJ5 AJ4

U1B

T2XCM T2XCP

T2X0M T2X0P

T2X1M T2X1P

T2X2M T2X2P

T2X3M T2X3P

T2X4M T2X4P

T2X5M T2X5P

T2PVDD T2PVSS

T2XVDDC_1 T2XVDDC_2

T2XVDDR_1 T2XVDDR_2

T2XVSSR_1 T2XVSSR_2 T2XVSSR_3 T2XVSSR_4 T2XVSSR_5 T2XVSSR_6 T2XVSSR_7 T2XVSSR_8 T2XVSSR_9 T2XVSSR_10 T2XVSSR_11 T2XVSSR_12 T2XVSSR_13 T2XVSSR_14

DDC1DATA DDC1CLK

DDC2DATA DDC2CLK

DDC3DATA DDC3CLK

DDC4DATA DDC4CLK

HPD1

SDA SCL

DMINUS DPLUS TS_FDO

PLLTEST TESTEN

VREFG

XTALIN XTALOUT

RV630

Integrated

Integrated TMDS2

TMDS2

Monitor

Monitor Interface

Interface

MMI2C

Thermal

Thermal Diode

Diode

Test

3

PART 2 OF 7

Integrated

Integrated TMDS

TMDS

V

V I

I D

D E

E O

O

&

M

M U

U L

L T

T I

I M

M E

E D

D I

I A

A

DAC / CRT

DAC2 (TV/CRT2)

www.vinafix.vn

TXCAM TXCAP

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TX3M

TX3P

TX4M

TX4P

TX5M

TX5P

TPVDD TPVSS

TXVDDR_2 TXVDDR_3 TXVDDR_4 TXVDDR_5

TXVSSR_1 TXVSSR_2 TXVSSR_3 TXVSSR_4 TXVSSR_5 TXVSSR_6 TXVSSR_7 TXVSSR_8 TXVSSR_9

TXVSSR_10

HSYNC

VSYNC

RSET AVDD

AVSSQ

VDD1DI VSS1DI

H2SYNC

V2SYNC

COMP

R2SET

A2VDDQ

A2VSSQ

VDD2DI VSS2DI

A2VDD

AN9 AN10

AR10 AP10

AR11 AP11

AR12 AP12

AR15 AP15

AR16 AP16

AR17 AP17

AM14 AL14

AN19 AN20 AP19 AR19

AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AR18 AP18

AR31

R

AP31

RB

AR30

G

AP30

GB

AR29

B

AP29

BB

AN29 AN30

AN31 AR32 AP32

AR28 AP28

AM19

R2

AL19

R2B

AM18

G2

AL18

G2B

AM17

B2

AL17

B2B

AM15 AL15

AK18

Y

AK19

C

AK17

R2SET GND_A2VSSQ

AJ21

AL21 AK21

AH22 AG22

AM21

C110

C110 10nF

10nF

C114

C114 10nF

10nF

R1033 75RR1033 75R

R1036 75RR1036 75R

R1039 75RR1039 75R R1037 75RR1037 75R

R1030 499RR1030 499R

R2033 75RR2033 75R

R2036 75RR2036 75R

R2039 75RR2039 75R

R2030 715RR2030 715R

C2021

C2021 100nF_6.3V

100nF_6.3V

C2024

C2024 10nF

10nF

C2030

C2030 10nF

10nF

3

C1023

C1023 10nF

10nF

C2031

C2031 100nF_6.3V

100nF_6.3V

C111

C111 100nF_6.3V

100nF_6.3V

C115

C115 100nF_6.3V

100nF_6.3V

GND

GND_AVSSQRSET

GND

C2025

C2025 100nF_6.3V

100nF_6.3V

C112

C112 1uF_6.3V

1uF_6.3V

C1024

C1024 100nF_6.3V

100nF_6.3V

C2022

C2022 1uF_6.3V

1uF_6.3V

+VDD2DI

C2026

C2026 1uF_6.3V

1uF_6.3V

GND_VSS2DI

C2032

C2032 1uF_6.3V

1uF_6.3V

C116

C116 1uF_6.3V

1uF_6.3V

C1025

C1025 1uF_6.3V

1uF_6.3V

+A2VDDQ

NS2021 NS_VIANS2021 NS_VIA

C113

C113 10uF_X6S

10uF_X6S

+TXVDDR

C117

C117 10uF_X6S

10uF_X6S

R1032 0RR1032 0R

R1035 0RR1035 0R

R1038 0RR1038 0R

C1020

C1020 10nF

10nF

+VDD1DI

R2032 0RR2032 0R

R2035 0RR2035 0R

R2038 0RR2038 0R

C2033

C2033 10uF_X6S

10uF_X6S

+TPVDD

NS110

NS110 NS_VIA

NS_VIA

GND_TPVSS

C1021

C1021 100nF_6.3V

100nF_6.3V

NS1021 NS_VIANS1021 NS_VIA

GND_VSS1DI

NS2020 NS_VIANS2020 NS_VIA

12

R1031 75RR1031 75R

R1034 75RR1034 75R

C1022

C1022 1uF_6.3V

1uF_6.3V

12

R2031 75RR2031 75R

R2034 75RR2034 75R

R2037 75RR2037 75R

12

GND_A2VSSQ

+A2VDD

T1XCM T1XCP

T1X0M T1X0P

T1X1M T1X1P

T1X2M T1X2P

T1X3M T1X3P

T1X4M T1X4P

T1X5M T1X5P

+AVDD

NS1020 NS_VIANS1020 NS_VIA

2

A_DAC1_R (15) A_DAC1_RB (15)

A_DAC1_G (15) A_DAC1_GB (15)

A_DAC1_B (15) A_DAC1_BB (15)

12

GND_AVSSQ

A_DAC2_R (16) A_DAC2_RB (16)

A_DAC2_G (16) A_DAC2_GB (16)

A_DAC2_B (16) A_DAC2_BB (16)

HSYNC_DAC2 (7,16) VSYNC_DAC2 (7,16)

A_DAC2_Y (17) A_DAC2_C (17) A_DAC2_COMP (17)

B2030 26R_600mAB2030 26R_600mA

2

+3.3V

Place close to ASICPlace close to ASIC

R116 182RR116 182R

R110 182RR110 182R

R111 182RR111 182R

R112 182RR112 182R

R113 182RR113 182R

R114 182RR114 182R

R115 182RR115 182R

TR10 0RTR10 0R

TR14 0RTR14 0R

DNI

1

T1XCM (16) T1XCP (16)

T1X0M (16) T1X0P (16)

T1X1M (16) T1X1P (16)

T1X2M (16) T1X2P (16)

T1X3M (16) T1X3P (16)

T1X4M (16) T1X4P (16)

T1X5M (16) T1X5P (16)

DNI

HSYNC1_TRST (1)

HSYNC_DAC1 (7,15) VSYNC_DAC1 (7,15)

VSYNC1_TCK (1)

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 - ASIC MAIN

Size Document Number Rev

Custom

Date: Sheet

105-B148xx-00D

1

3

of

321Wednesday, May 09, 2007

C151

C151 10nF

10nF

C131

C131 100nF_6.3V

100nF_6.3V

C141

C141 1uF_6.3V

1uF_6.3V

C126

C126 10uF_X6S

10uF_X6S

B120

B121

NS121 NS_VIANS121 NS_VIA

1 2

GND_VSSRHA_2

B122

B123

5

C152

C152 10nF

10nF

C132

C132 100nF_6.3V

100nF_6.3V

C142

C142 1uF_6.3V

1uF_6.3V

NS70 NS_VIANS70 NS_VIA

GND_PVSS

C133

C133 100nF_6.3V

100nF_6.3V

C143

C143 1uF_6.3V

1uF_6.3V

C127

C127 10uF_X6S

10uF_X6S

C121

C121 1uF_6.3V

1uF_6.3V

NS120 NS_VIANS120 NS_VIA

1 2 GND_VSSRHA_1

+3.3V

1 2

C154

C154 10nF

10nF

C134

C134 100nF_6.3V

100nF_6.3V

C144

C144 1uF_6.3V

1uF_6.3V

C128

C128 10uF_X6S

10uF_X6S

C120

1uF_6.3V

C90

C90 1uF_6.3V

1uF_6.3V

+1.8V

+DPLL_PVDD

C155

C155 10nF

10nF

C135

C135 100nF_6.3V

100nF_6.3V

C145

C145 1uF_6.3V

1uF_6.3V

C129

C129 10uF_X6S

10uF_X6S

C91

C91 100nF_6.3V

100nF_6.3V

C94

C94 10uF_X6S

10uF_X6S

C157

C157 10nF

10nF

C136

C137

100nF_6.3V

C146

C146 1uF_6.3V

1uF_6.3V

C122

C122 1uF_6.3V

1uF_6.3V

NS122 NS_VIANS122 NS_VIA

1 2

GND_VSSRHB_1

NS123 NS_VIANS123 NS_VIA

GND_VSSRHB_2

C92

C92 1uF_6.3V

1uF_6.3V

C95

C95 1uF_6.3V

1uF_6.3V

C71

C70

100nF_6.3V

10uF_X6S

C147

C147 1uF_6.3V

1uF_6.3V

1 2

C93

C93 100nF_6.3V

100nF_6.3V

C158

C158 10nF

10nF

C138

C138 100nF_6.3V

100nF_6.3V

C148

C148 1uF_6.3V

1uF_6.3V

C97

C97 100nF_6.3V

100nF_6.3V

C72

C72 1uF_6.3V

1uF_6.3V

Recommended caps: (see BOM for qualified values/vendors) 10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK 1uF, X6S, 0402, 6.3V 100nF, X7R, 0402 10nF , X7R, 0402

+MVDD

C150

C150 10nF

10nF

D D

C156

C130

100nF_6.3V

C140

C153

1uF_6.3V

C125

C124

10uF_X6S

+MVDD

BLM15BD121SN1

C C

B B

A A

BLM15BD121SN1

C123

C123 1uF_6.3V

1uF_6.3V

C96

C96 1uF_6.3V

1uF_6.3V

C159

C159 10nF

10nF

+DPLL_PVDD

GND_PVSS

4

C98

C98 100nF_6.3V

100nF_6.3V

AE14 AE15 AE17

AR20

AP20

AR35

AF12

M10 M35

AP2 AR2

AN1 AP1

AR1

A8 H35 L22

M1

P10

T1

Y1 A12 A16 A20 A24 A28

B1 B35

D1 D35

H1 K10 K12 K24 K26 L14 L15 L17 L18 L19 L21

A25 A32

B2

L1

B25 B32

C2

L2

A35

U1E

VDDR1_1 VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5 VDDR1_6 VDDR1_7 VDDR1_8 VDDR1_9 VDDR1_10 VDDR1_11 VDDR1_12 VDDR1_13 VDDR1_14 VDDR1_15 VDDR1_16 VDDR1_17 VDDR1_18 VDDR1_19 VDDR1_20 VDDR1_21 VDDR1_22 VDDR1_23 VDDR1_24 VDDR1_25 VDDR1_26 VDDR1_27 VDDR1_28 VDDR1_29

VDDRHA_1 VDDRHA_2

VDDRHB_1 VDDRHB_2

VSSRHA_1 VSSRHA_2

VSSRHB_1 VSSRHB_2

VDDR3_1 VDDR3_2 VDDR3_3 VDDR3_4

VDDR4_1 VDDR4_2

VDDR5_1 VDDR5_2

DPLL_PVDD

DPLL_PVSS

MECH_1 MECH_2 MECH_3

RV630

PART 5 OF 7

Memory I/O

Selected PLL's

Mechanical Pins

3

C932

C932 1uF_6.3V

1uF_6.3V

C920

C920 1uF_6.3V

1uF_6.3V

C901

C901 100nF_6.3V

100nF_6.3V

C163

C163 1uF_6.3V

1uF_6.3V

C173

C173 1uF_6.3V

1uF_6.3V

C921

C921 1uF_6.3V

1uF_6.3V

C902

C902 1uF_6.3V

1uF_6.3V

C185

C185 1uF_6.3V

1uF_6.3V

+VDD_CT

C69

C69 100nF_6.3V

100nF_6.3V

C66

C65

C65 1uF_6.3V

1uF_6.3V

100nF_6.3V

C62

C62 1uF_6.3V

1uF_6.3V

+PCIE_PVDD

C933

C933 10uF_X6S

10uF_X6S

C164

C164 1uF_6.3V

1uF_6.3V

C174

C174 1uF_6.3V

1uF_6.3V

C942

C942 1uF_6.3V

1uF_6.3V

BLM15BD121SN1

10uF_X6S

+DPLL_VDDC

C63

C63 10uF_X6S

10uF_X6S

AM35

PCIE_PVDD

AM34

PCIE_PVSS

R26

PCIE_VDDC_1

W25

PCIE_VDDC_2

W26

PCIE_VDDC_3

AA25

PCIE_VDDC_4

AA26

PCIE_VDDC_5

AB25

PCIE_VDDC_6

AB26

PCIE_VDDC_7

AD26

PCIE_VDDC_8

AF26

PCIE_VDDC_9

U26

PCIE_VDDC_10

V25

PCIE_VDDC_11

V26

PCIE_VDDC_12

AL33

PCIE_VDDR_1

AM33

PCIE_VDDR_2

AN33

PCIE_VDDR_3

AN34

PCIE_VDDR_4

AN35

PCIE_VDDR_5

PCI-Express

P

P O

O W

W E

E

Core

R

PCIE_VDDR_6 PCIE_VDDR_7 PCIE_VDDR_8

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33 VDDC_34 VDDC_35 VDDC_36 VDDC_37 VDDC_38 VDDC_39 VDDC_40 VDDC_41 VDDC_42 VDDC_43 VDDC_44

BBP_1 BBP_2

VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4

VDD_CT_1 VDD_CT_2 VDD_CT_3 VDD_CT_4 VDD_CT_5 VDD_CT_6 VDD_CT_7 VDD_CT_8

MPVDD

MPVSS

DPLL_VDDC

AP34 AP35 AR34

N13 R18 W11 AB19 AC23 AE18 AE19 AE21 AE22 N15 N18 N21 N23 P14 P17 P19 P22 R13 R15 R21 R23 U14 U17 U19 U22 V15 V18 V21 V23 W14 W17 W19 W22 AA15 AA18 AA21 AA23 AB14 AB17 AB22 AC13 AC15 AC18 AC21

U13 V13

M12 M24 P11 P25

R11 R25 U11 U25 AA11 AB11 AD10 AF10

A14

B15

AG19

+VDDC

+MPVDD

GND_MPVSS

+DPLL_VDDC

C930

C930 10nF

10nF

C161

C161 1uF_6.3V

1uF_6.3V

C171

C171 1uF_6.3V

1uF_6.3V

C160

C160 1uF_6.3V

1uF_6.3V

C78

C78 100nF_6.3V

100nF_6.3V

C64

10nF

GND_PVSS

C900

C900 10nF

10nF

C931

C931 100nF_6.3V

100nF_6.3V

C162

C162 1uF_6.3V

1uF_6.3V

C172

C172 1uF_6.3V

1uF_6.3V

C184

C184 1uF_6.3V

1uF_6.3V

C941

C941 1uF_6.3V

1uF_6.3V

C68

C68 100nF_6.3V

100nF_6.3V

C61

C61 100nF_6.3V

100nF_6.3V

NS18 NS_VIANS18 NS_VIA

GND_PCIE_PVSS

C922

C922 1uF_6.3V

1uF_6.3V

C903

C903 10nF

10nF

C165

C165 1uF_6.3V

1uF_6.3V

C175

C175 1uF_6.3V

1uF_6.3V

C186

C186 1uF_6.3V

1uF_6.3V

C943

C943 1uF_6.3V

1uF_6.3V

B69

C67

2

B930

BLM15BD121SN1

12

C923

C923 1uF_6.3V

1uF_6.3V

C905

C904

1uF_6.3V

100nF_6.3V

C166

C166 1uF_6.3V

1uF_6.3V

C176

C176 1uF_6.3V

1uF_6.3V

C944

C944 1uF_6.3V

1uF_6.3V

+1.8V

+MPVDD

B67 26R_600mAB67 26R_600mA

GND_MPVSS

C924

C924 1uF_6.3V

1uF_6.3V

C167

C167 1uF_6.3V

1uF_6.3V

C177

C177 1uF_6.3V

1uF_6.3V

NS64NS_VIA NS64NS_VIA

12

+1.8V

C187

C187 10uF_X6S

10uF_X6S

C945

C945 1uF_6.3V

1uF_6.3V

C906

C906 1uF_6.3V

1uF_6.3V

C168

C168 1uF_6.3V

1uF_6.3V

C178

C178 1uF_6.3V

1uF_6.3V

C925

C925 1uF_6.3V

1uF_6.3V

C926

C926 10uF_X6S

10uF_X6S

C907

C907 1uF_6.3V

1uF_6.3V

C169

C170

1uF_6.3V

C180

C179

1uF_6.3V

C188

C188 10uF_X6S

10uF_X6S

C947

C946

1uF_6.3V

+VDDC

Install only one of these two

+PCIE_VDDC

C189

C189 10uF_X6S

10uF_X6S

C73

C73 100nF_6.3V

100nF_6.3V

+PCIE_VDDR

C181

C181 10uF_X6S

10uF_X6S

C948

C948 1uF_6.3V

1uF_6.3V

C74

C75

100nF_6.3V

1uF_6.3V

C76

C76 1uF_6.3V

1uF_6.3V

B60

B60 BLM15BD121SN1

BLM15BD121SN1

MB60

MB60 BLM15BD121SN1

BLM15BD121SN1

Install only one of these two

R9000RR900 0R

+VDDC

C183

C182

10uF_X6S

+VDDCI_1

C77

C77 10uF_X6S

10uF_X6S

+VDDCI_2

C79

C79 10uF_X6S

10uF_X6S

R922

1

R921

0.1R

B921 220R_2AB921 220R_2A

Share one pad

R9200RR920 0R

+1.8V

B77 220R_2AB77 220R_2A

B78 220R_2AB78 220R_2A

+1.1V

+VDDC

1.5R

+VDDC

+1.1V

+VDDC

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

Title Size Document Number Rev

Size Document Number Rev

C

Date: Sheet

5

4

www.vinafix.vn

3

2

Date: Sheet

RV630 GDDR3 - ASIC Power

105-B148xx-00D

1

3

of

421Wednesday, May 09, 2007

5

4

3

2

1

+MVDD

R291

40.2R

402 1%

R292

R292 100R

100R

402 1%

R293

40.2R

402 1%

R294

R294 100R

100R

402 1%

DQA_[63..0](8,9)

MVREFS_0

U1C

DQA_0

P27

C296

C296 10nF

10nF

DQA_0

P28

DQA_1

P31

DQA_2

P32

DQA_3

M27

DQA_4

K29

DQA_5

K31

DQA_6

K32

DQA_7

M33

DQA_8

M34

DQA_9

L34

DQA_10

L35

DQA_11

J33

DQA_12

J34

DQA_13

H33

DQA_14

H34

DQA_15

K27

DQA_16

J29

DQA_17

J30

DQA_18

J31

DQA_19

F29

DQA_20

F32

DQA_21

D30

DQA_22

D32

DQA_23

G33

DQA_24

G34

DQA_25

G35

DQA_26

F34

DQA_27

D34

DQA_28

C34

DQA_29

C35

DQA_30

B34

DQA_31

C24

DQA_32

B24

DQA_33

B23

DQA_34

A23

DQA_35

C21

DQA_36

B21

DQA_37

C20

DQA_38

B20

DQA_39

J22

DQA_40

H22

DQA_41

F22

DQA_42

D21

DQA_43

J19

DQA_44

G19

DQA_45

F19

DQA_46

D19

DQA_47

C19

DQA_48

B19

DQA_49

A19

DQA_50

B18

DQA_51

C16

DQA_52

B16

DQA_53

C15

DQA_54

A15

DQA_55

H18

DQA_56

F18

DQA_57

E18

DQA_58

D18

DQA_59

J17

DQA_60

G15

DQA_61

E15

DQA_62

D15

DQA_63

N35

MVREFDA

N34

MVREFSA

RV630

DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63

C298

C299

10nF

100nF_6.3V

MVREFD_0 MVREFD_1

C297

C297 100nF_6.3V

100nF_6.3V

Part 3 of 7

MEMORY INTERFACE A

DDR1 DDR2 DDR3

bidir. differential strobe

write stroberead strobe

bidir. differential strobe

write stroberead strobe

Not usedbidir. strobe

For DDR2

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8

MAA_9 MAA_10 MAA_11

MAA_A12 MAA_BA0 MAA_BA1

MAA_BA2

DQMAB_0 DQMAB_1 DQMAB_2 DQMAB_3 DQMAB_4 DQMAB_5 DQMAB_6 DQMAB_7

QSA_0

QSA_1

QSA_2

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0B QSA_1B QSA_2B QSA_3B QSA_4B QSA_5B QSA_6B QSA_7B

ODTA0

ODTA1

CLKA0 CLKA0B

CKEA0 RASA0B CASA0B

WEA0B

CSA0B_0 CSA0B_1

CLKA1 CLKA1B

CKEA1 RASA1B CASA1B

WEA1B

CSA1B_0 CSA1B_1

MAA_0

C27

MAA_1

B28

MAA_2

B27

MAA_3

G26

MAA_4

F27

MAA_5

E27

MAA_6

D27

MAA_7

J27

MAA_8

E29

MAA_9

C30

MAA_10

E26

MAA_11

A27 G27

MAA_BA0

C28

MAA_BA1

B29

MAA_BA2

D26

DQMAb_0

M29

DQMAb_1

K33

DQMAb_2

G30

DQMAb_3

E33

DQMAb_4

C22

DQMAb_5

H21

DQMAb_6

C17

DQMAb_7

G17

QSA_0

M30

QSA_1

K34

QSA_2

G31

QSA_3

E34

QSA_4

B22

QSA_5

F21

QSA_6

B17

QSA_7

D17

QSAb_0

M31

QSAb_1

K35

QSAb_2

G32

QSAb_3

E35

QSAb_4

A22

QSAb_5

E21

QSAb_6

A17

QSAb_7

E17 C31

C25

A33

CLKA0 (8,9)

B33

CLKA0b (8,9)

B31

CKEA0 (8,9)

A31

RASA0b (8,9)

C32

CASA0b (8,9)

C29

WEA0b (8,9)

A30

CSA0b_0 (8)

B30

CSA0b_1 (9)

A26

CLKA1 (8,9)

B26

CLKA1b (8,9)

F24

CKEA1 (8,9)

D24

RASA1b (8,9)

H26

CASA1b (8,9)

D22

WEA1b (8,9)

G24

CSA1b_0 (8)

H24

CSA1b_1 (9)

MAA_[11..0] (8,9)

MAA_BA[2..0] (8,9)

DQMAb_[7..0] (8,9)

QSA_[7..0] (8,9)

QSAb_[7..0] (8,9)

+MVDD

R391

40.2R

402 1%

R392

R392 100R

100R

402 1%

R393

40.2R

402 1%

R394

R394 100R

100R

402 1%

C399

C399 100nF_6.3V

100nF_6.3V

C397

C397 100nF_6.3V

100nF_6.3V

C398

C398 10nF

10nF

C396

C396 10nF

10nF

DRAM_RST(8,9)

MVREFS_1

DQB_[63..0](8,9)

+MVDD

R295

2.0K

DNI

MR295

2.0K

R296

4.7K

DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63

R297

4.7K

R298

R298 243R

243R

H15 G14 E14 D14 H12 G12 F12 D10 B13 C12 B12 B11

J10 H10 F10

AA2 AA1

W9

W7

W6

W4

B14 A13

AA4 AA8 AA7 AA5

C9 B9 A9 B8

D9 G7 G6 F6 D6 C8 C7 B7 A7 B5 A5 C4 B4 M3 M2 N2 N1 R3 R2 T3 T2 M8 M7 P5 P4 R9 R8 R6 U4 U3 U2 U1 V2 Y3 Y2

U9 U7 U6 V4

U1D

DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63

MVREFDB MVREFSB

DRAM_RST TEST_MCLK TEST_YCLK MEMTEST

RV630

Part 4 of 7

MEMORY INTERFACE B

DDR1 DDR2 DDR3

write strobe

Not usedbidir. strobe

bidir. differential strobe

For DDR2

read strobe

MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8

MAB_9 MAB_10 MAB_11

MAB_A12 MAB_BA0 MAB_BA1

MAB_BA2

DQMBB_0 DQMBB_1 DQMBB_2 DQMBB_3 DQMBB_4 DQMBB_5 DQMBB_6 DQMBB_7

QSB_0

QSB_1

QSB_2

QSB_3

QSB_4

QSB_5

QSB_6

QSB_7

QSB_0B QSB_1B QSB_2B QSB_3B QSB_4B QSB_5B QSB_6B QSB_7B

ODTB0

ODTB1

CLKB0 CLKB0B

CKEB0 RASB0B CASB0B

WEB0B

CSB0B_0 CSB0B_1

CLKB1 CLKB1B

CKEB1 RASB1B CASB1B

WEB1B

CSB1B_0 CSB1B_1

MAB_0

H2

MAB_1

H3

MAB_2

J3

MAB_3

J5

MAB_4

J4

MAB_5

J6

MAB_6

G5

MAB_7

J9

MAB_8

F3

MAB_9

F4

MAB_10

J1

MAB_11

J2 J7

MAB_BA0

G2

MAB_BA1

G3

MAB_BA2

F1

DQMBb_0

D12

DQMBb_1

C10

DQMBb_2

E7

DQMBb_3

C6

DQMBb_4

P3

DQMBb_5

R4

DQMBb_6

W3

DQMBb_7

V8

QSB_0

J14

QSB_1

B10

QSB_2

F9

QSB_3

B6

QSB_4

P2

QSB_5

P8

QSB_6

W2

QSB_7

V6

QSBb_0

H14

QSBb_1

A10

QSBb_2

E9

QSBb_3

A6

QSBb_4

P1

QSBb_5

P7

QSBb_6

W1

QSBb_7

V5 D2

K5

A3

CLKB0 (8,9)

B3

CLKB0b (8,9)

E3

CKEB0 (8,9)

D3

RASB0b (8,9)

C1

CASB0b (8,9)

F2

WEB0b (8,9)

E1

CSB0b_0 (8,9)

E2

CSB0b_1 (9)

K1

CLKB1 (8,9)

K2

CLKB1b (8,9)

K8

CKEB1 (8,9)

K7

RASB1b (8,9)

K4

CASB1b (8,9)

M6

WEB1b (8,9)

L3

CSB1b_0 (8,9)

M4

CSB1b_1 (9)

MAB_[11..0] (8,9)

MAB_BA[2..0] (8,9)

DQMBb_[7..0] (8,9)

QSB_[7..0] (8,9)

QSBb_[7..0] (8,9)

D D

C C

B B

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3 - ASIC Memory Interface (Channel A & B)

Size Document Number Rev

C

Date: Sheet

5

4

www.vinafix.vn

3

2

Date: Sheet

105-B148xx-00D

1

3

of

521Wednesday, May 09, 2007

5

D D

C C

B B

A A

5

4

U1F

P33

PCIE_VSS_1

V29

PCIE_VSS_2

AB32

PCIE_VSS_3

AG29

PCIE_VSS_4

AJ29

PCIE_VSS_5

AJ32

PCIE_VSS_6

AK32

PCIE_VSS_7

AL34

PCIE_VSS_8

AL35

PCIE_VSS_9

P34

PCIE_VSS_10

P35

PCIE_VSS_11

R27

PCIE_VSS_12

R28

PCIE_VSS_13

R29

PCIE_VSS_14

R32

PCIE_VSS_15

R33

PCIE_VSS_16

T33

PCIE_VSS_17

U29

PCIE_VSS_18

U32

PCIE_VSS_19

V32

PCIE_VSS_20

V34

PCIE_VSS_21

V35

PCIE_VSS_22

W29

PCIE_VSS_23

W32

PCIE_VSS_24

W33

PCIE_VSS_25

Y33

PCIE_VSS_26

AA29

PCIE_VSS_27

AA32

PCIE_VSS_28

AB29

PCIE_VSS_29

AB34

PCIE_VSS_30

AB35

PCIE_VSS_31

AC33

PCIE_VSS_43

AD29

PCIE_VSS_32

AD32

PCIE_VSS_33

AD33

PCIE_VSS_34

AF29

PCIE_VSS_35

AF32

PCIE_VSS_36

AF34

PCIE_VSS_37

AF35

PCIE_VSS_38

AG27

PCIE_VSS_39

AG32

PCIE_VSS_40

AG33

PCIE_VSS_41

AH33

PCIE_VSS_42

A2

VSS_1

P15

VSS_2

R14

VSS_3

V1

VSS_4

W8

VSS_5

AA19

VSS_6

AC17

VSS_7

AF19

VSS_8

AK3

VSS_9

A4

VSS_10

C18

VSS_11

E22

VSS_12

G4

VSS_13

J18

VSS_14

K17

VSS_15

M28

VSS_16

P6

VSS_17

P9

VSS_18

P13

VSS_19

P18

VSS_20

P21

VSS_21

P23

VSS_22

P26

VSS_23

P29

VSS_24

P30

VSS_25

R1

VSS_26

R5

VSS_27

R7

VSS_28

R10

VSS_29

R17

VSS_30

R19

VSS_31

R22

VSS_32

U5

VSS_33

U8

VSS_34

U10

VSS_35

U15

VSS_36

U18

VSS_37

U21

VSS_38

U23

VSS_39

V3

VSS_40

V7

VSS_41

V9

VSS_42

V10

VSS_43

V11

VSS_44

V14

VSS_45

V17

VSS_46

V19

VSS_47

V22

VSS_48

W5

VSS_49

W10

VSS_50

W15

VSS_51

W18

VSS_52

W21

VSS_53

W23

VSS_54

AA3

VSS_55

AA6

VSS_56

AA10

VSS_57

AA14

VSS_58

AA17

VSS_59

AA22

VSS_60

AB5

VSS_61

AB8

VSS_62

AB10

VSS_63

AB13

VSS_64

AB15

VSS_65

AB18

VSS_66

AB21

VSS_67

AB23

VSS_68

AC14

VSS_69

AC19

VSS_70

AC22

VSS_71

AD6

VSS_72

AD24

VSS_73

AF6

VSS_74

AF9

VSS_75

AF14

VSS_76

AF15

VSS_77

AF17

VSS_78

AF18

VSS_79

AF21

VSS_80

AF22

VSS_81

AF24

VSS_82

AG10

VSS_83

AG12

VSS_84

AH21

VSS_85

RV630

4

Part 6 of 7

PCI-Express GND

CORE GND

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3

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166

3

VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

TXCBP TXCBM

BBN_1 BBN_2

AJ14 AJ17 AJ18 AJ19 AK9 AK10 AK12 AK15 AK30 AM1 AN3 AN6 AN32 AR8 A11 A18 A21 A29 A34 C3 C5 C11 C13 C14 C23 C26 C33 D4 D7 D29 D33 E10 E12 E19 E24 F7 F14 F15 F17 F26 F30 F33 F35 G1 G9 G10 G18 G21 G22 G29 H17 H19 J12 J15 J21 J24 J26 J32 J35 K3 K6 K9 K14 K15 K18 K19 K21 K22 K28 K30 L33 M5 M9 M26 M32 N3 N14 N17 N19 N22 N33

AP14 AR14

W13 AA13

2

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

Title Size Document Number Rev

Size Document Number Rev

C

Date: Sheet

2

Date: Sheet

1

RV630 GDDR3 - ASIC Grounds

105-B148xx-00D

1

621Wednesday, May 09, 2007

3

of

5

VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6 VID_7

D D

TP84

TP84 TP85

TP85

35mil

DVOCLK

TP86

35mil

DVPCNTL_0

35mil

TP87

DVPCNTL_1

TP88

35mil

DVPCNTL_2

TP89

35mil

DVP_MVP_CNTL_0

35mil

CrossFire

DVP_MVP_CNTL_0 : DE for bits D[12..23] DVP_MVP_CNTL_1 : CLK for bits D[12..23]

C C

B B

DVP_MVP_CNTL_1

TP60

TP60 TP61

TP61

35mil

35mil TP62

TP62

35mil

35mil 35mil

35mil

TP63

TP63 TP64

TP64

35mil

35mil TP65

TP65

35mil

35mil TP66

TP66

35mil

35mil TP67

TP67

35mil

35mil 35mil

35mil

TP68

TP68 TP69

TP69

35mil

35mil TP70

TP70

35mil

35mil TP71

TP71

35mil

35mil TP72

TP72

35mil

35mil 35mil

35mil

TP73

TP73 TP74

TP74

35mil

35mil TP75

TP75

35mil

35mil TP76

TP76

35mil

35mil TP77

TP77

35mil

35mil 35mil

35mil

TP78

TP78 TP79

TP79

35mil

35mil TP80

TP80

35mil

35mil TP81

TP81

35mil

35mil TP82

TP82

35mil

35mil TP83

TP83

35mil

35mil 35mil

35mil

DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8

DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

AM12

AL12

AJ12 AH12 AM10

AL10

AJ10 AH10

AL7

AM9 AL9

AJ9

AK7

AH1 AG1 AH3 AH2 AN8 AP8

AJ3 AJ2

AJ1 AK2 AK1 AL3 AL2 AL1 AM3 AM2 AN2 AP3 AR3 AN4 AR4 AP4 AN5 AR5 AP5 AP6 AR6 AN7 AP7 AR7

U1G

VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6 VID_7

VPCLK0

VHAD_0 VHAD_1

VPHCTL VIPCLK

DVPCLK DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCNTL_MVP_0 DVPCNTL_MVP_1

DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

RV630

VIP

VIP Capture

Capture

VIP

VIP Host

Host

PART 7 OF 7

General

General Purpose

Purpose I/O

I/O

GPIO_15_PWRCNTL_0

GPIO_17_THERMAL_INT

GPIO_20_PWRCNTL_1

GPIO_23_CLKREQB

RESERVED

No Connect

CrossFire Card-Edge

Lower Cable Card Edge

J8002J8002

1

DVOCLK DVPCNTL_2 DVPDATA_1 DVPDATA_3 DVPDATA_5 DVPDATA_7 DVPDATA_9 DVPDATA_11 DVPCNTL_1

A A

GPIO_3

3 5 7

9 11 13 15 17 19 21 23 25 27 29 30 31 33 35 37 39

2 4 6 8

DVPDATA_0

10 12

DVPDATA_2

14 16

DVPDATA_4

18 20

DVPDATA_6

22 24

DVPDATA_8

26 28

DVPDATA_10

32

DVPCNTL_0

34 36

GPIO_5

38 40

Bundle A

5

Upper Cable Card Edge

DVP_MVP_CNTL_1 DVP_MVP_CNTL_0 DVPDATA_13 DVPDATA_15 DVPDATA_17 DVPDATA_19 DVPDATA_21 DVPDATA_23 GENERICB_R GPIO_4

11 13 15 17 19 21 23 25 27 29 30 31 33 35 37 39

Bundle B (closer to the bracket)

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_11 GPIO_12 GPIO_13

GPIO_14_HPD2

GPIO_16_SSIN

GPIO_18_HPD3 GPIO_19_CTFB

GPIO_21_BB_EN

GPIO_22_ROMCSB

GPIO_24_JMODE

GPIO_25_TDI

GPIO_26_TCK GPIO_27_TMS GPIO_28_TDO

GENERICA GENERICB

GENERICC

DVALID

PSYNC

RSVD_12

RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8

RSVD_9 RSVD_10 RSVD_11

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9

NC_10

J8001J8001

1

2

3

4

5

6

7

8

9

10 12 14 16 18 20 22 24 26 28

32 34 36 38 40

4

GPIO_0

AG2

GPIO_1

AF2

GPIO_2

AF1 AE3 AE2 AE1 AD3

GPIO_7

AD2

GPIO_8

AD1

GPIO_9

AD5

GPIO_10

AD4

GPIO_11

AC3

GPIO_12

AC2

GPIO_13

AC1

HPD2

AB3

PWRCNTL_0

AB2

GPIO_16

AB1

ThermINT

AF5

GPIO_18

AF4

CTFb

AG4

PWRCNTL_1

AG3

GPIO21_BB_EN

AD9

GPIO_22

AD8 AD7 AB4

JTAG_TDI

AB6

JTAG_TCK

AB7

JTAG_TMS

AB9

JTAG_TDO

AA9

GENERICA

AF8

GENERICB

AF7

GENERICC

AG5

DVALID

AJ7

PSYNC

AM7

AJ6

AF3 AH24 AK24 AK26 AK34 AK35 AL24 AL26 AG7 AG9 AG24

AG15 AG17 AG18 AH17 AH18 AP13 AP9 AR13 AR9 AK14

It is not intended for production

+3.3V

TC47

TC47 100nF_6.3V

100nF_6.3V

Mating connector: 6010028300G (HEADER 2X8 1.27MM PITCH, SMD)

Place it at top edge of the board on the bottom side. Mounting hole is needed and must be aligned with B176

DVPDATA_12 DVPDATA_14 DVPDATA_16 DVPDATA_18 DVPDATA_20 DVPDATA_22 DVALID_R GPIO_6

4

FLOW_CONTROL_1 - Lower Cable

GPIO_3

FLOW_CONTROL_2 - Upper Cable

GPIO_4

SWAP_LOCK_1 - Lower Cable

GPIO_5

SWAP_LOCK_2 - Upper Cable

GPIO_6

HPD2 (15) PWRCNTL_0 (13)

ThermINT (18)

CTFb (13)

PCIE_CLK_REQb

JTAG_MODE

Do not install for BU

R8001 0RR8001 0R R8002 0RR8002 0R

GENERICB: Generic I2C_SDA DVALID: Generic I2C_SCL

3

DNI

CrossFire

TP51TP51

MR51KMR5 1K

GENERICA (17)

TR570R TR570R

DNI

BUO

TJ47

1

JTAG_MODE

3 5 7

JTAG_TCK

9

JTAG_TMS

11

JTAG_TDI

13

JTAG_TDO

15

2X8SOCKET

DVALID GENERICB

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+3.3V

BUO

TR50

TP50TP50

10K

TP47TP47

TP46TP46

For wire soldering

+3.3V+5V

TR48

TR47

3

TR47

4.7K

TC46

TC46 100nF_6.3V

100nF_6.3V

4.7K

BUOBUO

SDA (3) SCL (3)

+EXT_ADJ

2

GPIO_8

4

GPIO_22

6

GPIO_9

8

GPIO_10

10

SDA

12

SCL

14 16

DNI

Single Rank

DNI

MR87 10KMR87 10K

MR50 10KMR50 10K

MR51 10KMR51 10K

MR52 10KMR52 10K MR53 10KMR53 10K

MR54 10KMR54 10K

MR55 10KMR55 10K

MR56 10KMR56 10K

MR58 10KMR58 10K MR59 10KMR59 10K MR63 10KMR63 10K MR62 10KMR62 10K MR61 10KMR61 10K

MR65 10KMR65 10K MR64 10KMR64 10K

MR66 10KMR66 10K

MR67 10KMR67 10K

MR68 10KMR68 10K

MR69 10KMR69 10K

MR70 10KMR70 10K

MR71 10KMR71 10K

MR72 10KMR72 10K

MR73 10KMR73 10K

MR74 10KMR74 10K

MR75 10KMR75 10K

MR76 10KMR76 10K

MR77 10KMR77 10K

MR78 10KMR78 10K

MR88 10KMR88 10K

MR79 10KMR79 10K

MR60 10KMR60 10K

+3.3V

Dual Rank

DNI

NTSC

DNI

BUO

DNI

2

R50 10KR50 10K

R51 10KR51 10K

R52 10KR52 10K R53 10KR53 10K

R54 10KR54 10K

R55 10KR55 10K

NR551KNR55 1K

R56 10KR56 10K

R57 10KR57 10K

R58 10KR58 10K R59 10KR59 10K R63 10KR63 10K R62 10KR62 10K R61 10KR61 10K

R65 10KR65 10K R64 10KR64 10K

R66 10KR66 10K

R67 10KR67 10K

R68 10KR68 10K

R69 10KR69 10K

R70 10KR70 10K

R71 10KR71 10K

R72 10KR72 10K

R73 10KR73 10K

R74 10KR74 10K

R75 10KR75 10K

R76 10KR76 10K

R77 10KR77 10K

R78 10KR78 10K

R88 10KR88 10K

R79 10KR79 10K

R60 10KR60 10K

R87 10KR87 10K

GPIO_8 GPIO_9 GPIO_10 GPIO_22

2

PIN BASED STRAPS

GPIO_0

GPIO_1

GPIO_2

GPIO_2 GPIO_3

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7GPIO_7

GPIO_13

GPIO_13 GPIO_12

GPIO_12 GPIO_11

GPIO_11

VSYNC_DAC1

HSYNC_DAC1

PSYNC

GPIO21_BB_EN

VID_0

VID_1

VID_2

VID_3

VID_4

VID_5

VID_6

VID_7

VSYNC_DAC2

HSYNC_DAC2

DVALID

GPIO_8 GPIO_9

GENERICC GENERICB

GPIO_18

GPIO_16

+3.3V

CONFIG[3] CONFIG[2] CONFIG[1] CONFIG[0]

R45

R45 10K

10K

MR45

MR45 10K

10K

SW1A

41

DIP_SWX2

SW1B

32

DIP_SWX2

VSYNC_DAC1 (3,15)

HSYNC_DAC1 (3,15)

VSYNC_DAC2 (3,16)

HSYNC_DAC2 (3,16)

+3.3V

1

GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)

0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)

0: Tx de-emphasis disabled for mobile mode 1: Tx de-emphasis enabled (Default setting for Desktop)

AMD Internal Use Only - Reserved (Default: 00)

DEBUG_ACCESS AMD Internal Use Only - Reserved (Default: 0)

AMD Internal Use Only - Reserved (Default: G1=0, G2=1)

AMD Internal Use Only - Reserved (Default: 0)

TV OUT STANDARD (Jumper position overwrite resistor settings)

0 - PAL TVO (Jumper is closed) 1 - NTSC TVO (Jumper is open)

AMD Internal Use Only - Reserved (Default: 0)

GPIO(9,13:11) - CONFIG[3..0]

0010 - 512Kbit AT25F512A (Atmel) 0011 - 1Mbit AT25F1024A (Atmel) 0100 - 512Kbit M25P05A (ST) 0101 - 1Mbit M25P10A (ST) 0101 - 2Mbit M25P20 (ST) 0100 - 512Kbit Pm25LV512 (Chingis) 0101 - 1Mbit Pm25LV010 (Chingis)

AMD Internal Use Only - Reserved (Default: 0)

VIP_DEVICE_STRAP_EN

0: Slave VIP host port devices present (use if Theater is populated) 1: No slave VIP host port devices reporting presence during reset (use for configurations without video-in)

AMD Internal Use Only - Reserved (HDMI_EN =1 )

VGA DISABLE : 1 for disable (set to 0 for normal operation)

AMD Internal Use Only - Reserved (Default: 0)

MSI_DIS (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

BIF_AUDIO_EN 0 - Disable HD Audio 1- Enable HD Audio

AMD Internal Use Only - Reserved (Default: 0)

64BAR_EN_A (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

MEMORY CONFIG V2SYNC: 0 = 1 rank of memory, 1 = 2 ranks of memory

AMD Internal Use Only - Reserved

BIF_CLK_PM_EN 0 - Disable CLKREQ# power management capability 1 - Enable CLKREQ# power management capability

+3.3V

R46

R46 10K

10K

U2

5

D

6

C

1

S

7

HOLD

3

W

8

VCC

M25P05-AVNM6P

C47

C47 100nF_6.3V

100nF_6.3V

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

Title Size Document Number Rev

Size Document Number Rev

C

Date: Sheet

ATI Board Feature I

Default: 0

2

Q

4

VSS

RV630 GDDR3 - ASIC DVO & GPIOs

BIOS1

BIOS

113-B146XX-XXX

VIDEO BIOS FIRMWARE

105-B148xx-00D

1

ATI PCIE FEATURE I

ATI PCIE FEATURE II

of

721Wednesday, May 09, 2007

3

DQA_9 DQA_11 DQA_10 DQA_12 DQA_8 DQA_13 DQA_15 DQA_14 DQA_31 DQA_28 DQA_29 DQA_30 DQA_27 DQA_26 DQA_24 DQA_25 DQA_2 DQA_4 DQA_1 DQA_3 DQA_7 DQA_5 DQA_0 DQA_6 DQA_16 DQA_17 DQA_23 DQA_18 DQA_21 DQA_19 DQA_22 DQA_20

MAA_BA0 MAA_BA1

MAA_7 MAA_8 MAA_3 MAA_10 MAA_11 MAA_2 MAA_1 MAA_0 MAA_9 MAA_6 MAA_5 MAA_4

MAA_BA2

QSA_1 QSA_3 QSA_0 QSA_2

QSAb_1 QSAb_3 QSAb_0 QSAb_2

DQMAb_1 DQMAb_3 DQMAb_0 DQMAb_2

R218

R218 243R

243R

C239

C239 10nF

10nF

C240

C241

100nF_6.3V

10nF

R208 121RR208 121R R209 121RR209 121R R201 121RR201 121R R202 121RR202 121R

R203 121RR203 121R R204 121RR204 121R R205 121RR205 121R R206 121RR206 121R R207 121RR207 121R

R265 121RR265 121R R266 121RR266 121R R251 121RR251 121R R252 121RR252 121R

R253 121RR253 121R R254 121RR254 121R R255 121RR255 121R R256 121RR256 121R R257 121RR257 121R

C226

C226 100nF_6.3V

100nF_6.3V

C231

C231 1uF_6.3V

1uF_6.3V

5

U201

T3 T2

R3 R2 M3 N2

L3

M2 T10 T11

R10 R11 M10 N11

L10

M11 G10

F11 F10 E11

C10 C11

B10 B11

G3

F2 F3

E2 C3 C2

B3

B2

H10

G9 G4

L4

K2 M9

K11

L9

K10

H11

K9 M4

K3 H2

K4

F9 H9 H3

F4 H4

J10 J11

P3

P10

D10

D3

P2

P11

D11

D2 N3

N10

E10

E3

V9

A4

H1

H12

136BALL-GDDR3

+MVDD

C205

C205 100nF_6.3V

100nF_6.3V

C216

C216 1uF_6.3V

1uF_6.3V

C227

C227 100nF_6.3V

100nF_6.3V

C232

C232 1uF_6.3V

1uF_6.3V

5

BA2 | RAS BA1 | BA0 BA0 | BA1

A11 | A7 A10 | A8 A9 | A3 A8/AP | A10 A7 | A11 A6 | A2 A5 | A1 A4 | A0 A3 | A9 A2 | A6 A1 | A5 A0 | A4

CK RDQS3 | RDQS2

RDQS2 | RDQS3 RDQS1 | RDQS0 RDQS0 | RDQS1

WDQS3 | WDQS2 WDQS2 | WDQS3 WDQS1 | WDQS0 WDQS0 | WDQS1

DM3 | DM2 DM2 | DM3 DM1 | DM0 DM0 | DM1

RESET ZQ

VREF VREF#H12

QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7

+MVDD

QSAb_0 QSAb_1 QSAb_2 QSAb_3 QSAb_4 QSAb_5 QSAb_6 QSAb_7

VDDQ#A12

VDDQ#C12

VDDQ#E12

VDDQ#N12

VDDQ#R12 VDDQ#V12

VSSQ#B12

VSSQ#D12 VSSQ#G11

VSSQ#L11

VSSQ#P12

VSSQ#T12

VDDA#K12

VSSA#J12

C207

C207 100nF_6.3V

100nF_6.3V

C218

C218 1uF_6.3V

1uF_6.3V

C233

C233 10uF_X6S

10uF_X6S

VDDQ

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#E1 VDDQ#E4 VDDQ#E9

VDDQ#J4 VDDQ#J9 VDDQ#N1 VDDQ#N4 VDDQ#N9

VDDQ#R1 VDDQ#R4 VDDQ#R9

VDDQ#V1

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ VSSQ#B4 VSSQ#B9

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#G2

VSSQ#L2

VSSQ#P1 VSSQ#P4 VSSQ#P9

VSSQ#T1 VSSQ#T4 VSSQ#T9

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VSSA

RFU2

RFU1

RFU0

GND | VDD

VDD

VSS

+MVDD A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

+MVDD A2 A11 F1 F12 M1 M12 V2 V11

B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 A3 A10 G1 G12 L1 L12 V3 V10

K1 K12

C242

C243

100nF_6.3V

10nF

J12 J1

J3 J2 V4

A9

MF

+MVDD

QSA_[7..0] (5,9)

In Single Rank Design: Use 60.4R (PN 316060R400G) for: R208, R209, R201, R202 R265, R266, R251, R252

QSAb_[7..0] (5,9)

C209

C210

100nF_6.3V

C220

C221

1uF_6.3V

+MVDD +MVDD

C236

C235

10uF_X6S

Rank 0 Top Layer

+MVDD

B201B201 B202B202

+MVDD

C294

C294 10nF

10nF

+MVDD

C295

C295 10nF

10nF

DQMAb_[7..0](5,9)

DQMBb_[7..0](5,9)

+MVDD

C211

C211 100nF_6.3V

100nF_6.3V

C222

C222 1uF_6.3V

1uF_6.3V

+MVDD

C237

C237 10uF_X6S

10uF_X6S

R259

2.37K

R260

5.49K

+MVDD

R261

2.37K

R262

5.49K

C251

C251 100nF_6.3V

100nF_6.3V

C262

C262 1uF_6.3V

1uF_6.3V

C273

C273 100nF_6.3V

100nF_6.3V

C278

C278 1uF_6.3V

1uF_6.3V

DQA_[63..0](5,9)

D D

RASA0b(5,9)

+MVDD

C244

C244 10nF

10nF

+MVDD

C245

C245 10nF

10nF

C201

C201 100nF_6.3V

100nF_6.3V

C212

C212 1uF_6.3V

1uF_6.3V

C223

C223 100nF_6.3V

100nF_6.3V

C228

C228 1uF_6.3V

1uF_6.3V

R219

2.37K

R220

5.49K

+MVDD

R221

2.37K

R222

5.49K

+MVDD

CLKB0(5,9) CLKB0b(5,9) CLKA0(5,9) CLKA0b(5,9)

CKEA0(5,9) CSA0b_0(5) WEA0b(5,9) RASA0b(5,9) CASA0b(5,9)

CLKB1(5,9) CLKB1b(5,9) CLKA1(5,9) CLKA1b(5,9)

CKEA1(5,9) CSA1b_0(5) WEA1b(5,9) RASA1b(5,9) CASA1b(5,9)

C202

C202 100nF_6.3V

100nF_6.3V

C213

C213 1uF_6.3V

1uF_6.3V

C224

C224 100nF_6.3V

100nF_6.3V

C229

C229 1uF_6.3V

1uF_6.3V

CASA0b(5,9) CKEA0(5,9)

CSA0b_0(5) WEA0b(5,9) CLKA0b(5,9)

CLKA0(5,9)

DRAM_RST(5,9)

C238

C238 100nF_6.3V

100nF_6.3V

C203

C203 100nF_6.3V

100nF_6.3V

C214

C214 1uF_6.3V

1uF_6.3V

C225

C225 100nF_6.3V

100nF_6.3V

C230

C230 1uF_6.3V

1uF_6.3V

C C

B B

+MVDD

A A

+MVDD

CSA1b_0(5)

WEA1b(5,9) RASA1b(5,9) CASA1b(5,9) CKEA1(5,9) CLKA1b(5,9)

CLKA1(5,9)

DRAM_RST(5,9)

C288

C288 100nF_6.3V

100nF_6.3V

DQMAb_0 DQMAb_1 DQMAb_2 DQMAb_3 DQMAb_4 DQMAb_5 DQMAb_6 DQMAb_7

DQMBb_0 DQMBb_1 DQMBb_2 DQMBb_3 DQMBb_4 DQMBb_5 DQMBb_6 DQMBb_7

C252

C252 100nF_6.3V

100nF_6.3V

C263

C263 1uF_6.3V

1uF_6.3V

DQA_63 DQA_56 DQA_62 DQA_60 DQA_58 DQA_57 DQA_59 DQA_61 DQA_54 DQA_52 DQA_53 DQA_50 DQA_55 DQA_51 DQA_48 DQA_49 DQA_47 DQA_46 DQA_40 DQA_45 DQA_42 DQA_43 DQA_41 DQA_44 DQA_32 DQA_34 DQA_35 DQA_33 DQA_38 DQA_37 DQA_39 DQA_36

MAA_BA2 MAA_BA1 MAA_BA0

MAA_11 MAA_10 MAA_9 MAA_8 MAA_7 MAA_6 MAA_5 MAA_4 MAA_3 MAA_2 MAA_1 MAA_0

QSA_7 QSA_6 QSA_5 QSA_4

QSAb_7 QSAb_6 QSAb_5 QSAb_4

DQMAb_7 DQMAb_6 DQMAb_5 DQMAb_4

R210

R210 243R

243R

C290

C290 100nF_6.3V

100nF_6.3V

C253

C253 100nF_6.3V

100nF_6.3V

C264

C264 1uF_6.3V

1uF_6.3V

4

U202

T3

DQ31 | DQ23

T2

VDDQ#C12 DQ25 | DQ17 DQ24 | DQ16 DQ23 | DQ31 DQ22 | DQ30

VDDQ#N12 DQ15 | DQ7 DQ14 | DQ6 DQ13 | DQ5 DQ12 | DQ4

VDDQ#R12 DQ11 | DQ3 DQ10 | DQ2

BA2 | RAS BA1 | BA0

VSSQ#B12 BA0 | BA1

A11 | A7 A10 | A8

VSSQ#D12 A9 | A3 A8/AP | A10

VSSQ#G11 A7 | A11 A6 | A2 A5 | A1 A4 | A0 A3 | A9 A2 | A6

VSSQ#P12 A1 | A5 A0 | A4

CK

VDDA#K12 RDQS3 | RDQS2 RDQS2 | RDQS3 RDQS1 | RDQS0 RDQS0 | RDQS1

WDQS3 | WDQS2 WDQS2 | WDQS3 WDQS1 | WDQS0 WDQS0 | WDQS1

DM3 | DM2 DM2 | DM3 DM1 | DM0 DM0 | DM1

RESET ZQ

VREF VREF#H12

MAA_BA[2..0](5,9)

QSB_[7..0] (5,9)

MAA_[11..0](5,9) MAB_[11..0](5,9)

QSBb_[7..0] (5,9)

C255

C256

100nF_6.3V

C266

C267

1uF_6.3V

C277

C277 100nF_6.3V

100nF_6.3V

C282

C282 1uF_6.3V

1uF_6.3V

VDDQ#A12

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#E1 VDDQ#E4 VDDQ#E9

VDDQ#J4

VDDQ#J9 VDDQ#N1 VDDQ#N4 VDDQ#N9

VDDQ#R1 VDDQ#R4 VDDQ#R9

VDDQ#V1

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4 VSSQ#B9

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#G2

VSSQ#L2

VSSQ#L11

VSSQ#P1 VSSQ#P4 VSSQ#P9

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VSSA#J12

GND | VDD

C257

C257 100nF_6.3V

100nF_6.3V

C268

C268 1uF_6.3V

1uF_6.3V

C283

C283 10uF_X6S

10uF_X6S

R3 R2 M3 N2

L3

M2 T10 T11 R10 R11 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B10 B11

G3

F2 F3

E2 C3 C2

B3

B2

H10

G9 G4

L4

K2 M9

K11

L9

K10 H11

K9 M4

K3 H2

K4

F9 H9 H3

F4 H4 J10

J11

P3

P10 D10

D3

P2

P11 D11

D2 N3

N10 E10

E3

V9

A4

H1

C289

H12

10nF

136BALL-GDDR3

C291

C291 10nF

10nF

QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7

QSBb_0 QSBb_1 QSBb_2 QSBb_3 QSBb_4 QSBb_5 QSBb_6 QSBb_7

C254

C254 100nF_6.3V

100nF_6.3V

C265

C265 1uF_6.3V

1uF_6.3V

C276

C276 100nF_6.3V

100nF_6.3V

C281

C281 1uF_6.3V

1uF_6.3V

4

+MVDD

A1

VDDQ

A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

+MVDD

A2

VDD

A11 F1 F12 M1 M12 V2 V11

B1

VSSQ

B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 A3

VSS

A10 G1 G12 L1 L12 V3

VDDA

VSSA

RFU2 RFU1 RFU0

MF

V10

K1 K12

J12 J1

J3 J2 V4

A9

C284

C284 10uF_X6S

10uF_X6S

C292

C292 100nF

100nF

MAA_BA0 MAA_BA1 MAA_BA2

MAA_11 MAA_10 MAA_9 MAA_8 MAA_7 MAA_6 MAA_5 MAA_4 MAA_3 MAA_2 MAA_1 MAA_0

C259

C259 100nF_6.3V

100nF_6.3V

C270

C270 1uF_6.3V

1uF_6.3V

C285

C285 10uF_X6S

10uF_X6S

C293

C293 10nF

10nF

MAB_BA[2..0](5,9)

C260

C260 100nF_6.3V

100nF_6.3V

C271

C271 1uF_6.3V

1uF_6.3V

C286

C286 10uF_X6S

10uF_X6S

+MVDD

B251B251 B252B252

C261

C261 100nF_6.3V

100nF_6.3V

C272

C272 1uF_6.3V

1uF_6.3V

www.vinafix.vn

3

MAB_BA0 MAB_BA1 MAB_BA2

MAB_11 MAB_10 MAB_9 MAB_8 MAB_7 MAB_6 MAB_5 MAB_4 MAB_3 MAB_2 MAB_1 MAB_0

3

C344

C344 10nF

10nF

C345

C345 10nF

10nF

+MVDD

DQB_[63..0](5,9)

+MVDD

C301

C301 100nF_6.3V

100nF_6.3V

C312

C312 1uF_6.3V

1uF_6.3V

C323

C323 100nF_6.3V

100nF_6.3V

C328

C328 1uF_6.3V

1uF_6.3V

R319

2.37K

R320

5.49K

R321

2.37K

R322

5.49K

+MVDD

2

U301

DQB_26

T3

DQ31 | DQ23

DQB_25

T2

BA2 | RAS BA1 | BA0 BA0 | BA1

A11 | A7 A10 | A8 A9 | A3 A8/AP | A10 A7 | A11 A6 | A2 A5 | A1 A4 | A0 A3 | A9 A2 | A6 A1 | A5 A0 | A4

CK RDQS3 | RDQS2

RDQS2 | RDQS3 RDQS1 | RDQS0 RDQS0 | RDQS1

WDQS3 | WDQS2 WDQS2 | WDQS3 WDQS1 | WDQS0 WDQS0 | WDQS1

DM3 | DM2 DM2 | DM3 DM1 | DM0 DM0 | DM1

RESET ZQ

VREF VREF#H12

C306

C306 100nF_6.3V

100nF_6.3V

C317

C317 1uF_6.3V

1uF_6.3V

VDDQ#A12

VDDQ#C12

VDDQ#E12

VDDQ#N12

VDDQ#R12 VDDQ#V12

VSSQ#B12

VSSQ#D12 VSSQ#G11

VSSQ#L11

VSSQ#P12

VSSQ#T12

VDDA#K12

VSSA#J12

C307

C307 100nF_6.3V

100nF_6.3V

C318

C318 1uF_6.3V

1uF_6.3V

C333

C333 10uF_X6S

10uF_X6S

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#E1 VDDQ#E4 VDDQ#E9

VDDQ#J4

VDDQ#J9 VDDQ#N1 VDDQ#N4 VDDQ#N9

VDDQ#R1 VDDQ#R4 VDDQ#R9

VDDQ#V1

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4 VSSQ#B9

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#G2

VSSQ#L2 VSSQ#P1

VSSQ#P4 VSSQ#P9

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

GND | VDD

DQB_27

R3

DQB_30

R2

DQB_24

M3

DQB_29

N2

DQB_31

L3

DQB_28

M2

DQB_15

T10

DQB_12

T11

DQB_13

R10

DQB_14

R11

DQB_8

M10

DQB_10

N11

DQB_9

L10

DQB_11

M11

DQB_0

G10

DQB_1

F11

DQB_3

F10

DQB_7

E11

DQB_5

C10

DQB_2

C11

DQB_6

B10

DQB_4

B11

DQB_17

G3

DQB_18 DQB_35

F2

DQB_20

F3

DQB_19

E2

DQB_23

C3

DQB_16

C2

DQB_21

B3

DQB_22

B2

QSB_3 QSB_1 QSB_0 QSB_2

QSBb_3 QSBb_1 QSBb_0 QSBb_2

DQMBb_3 DQMBb_1 DQMBb_0 DQMBb_2

C338

C338 100nF_6.3V

100nF_6.3V

C340

C340 100nF_6.3V

100nF_6.3V

C303

C303 100nF_6.3V

100nF_6.3V

C314

C314 1uF_6.3V

1uF_6.3V

MAB_BA0 MAB_BA1

MAB_7 MAB_8 MAB_3 MAB_10 MAB_11 MAB_2 MAB_1 MAB_0 MAB_9 MAB_6 MAB_5 MAB_4

MAB_BA2

R318

R318 243R

243R

C339

C339 10nF

10nF

C304

C304 100nF_6.3V

100nF_6.3V

C315

C315 1uF_6.3V

1uF_6.3V

C341

C341 10nF

10nF

H10

K11 K10

H11

P10 D10

P11 D11

N10 E10

H12

G9 G4

L4 K2

M9

L9

K9

M4

K3

H2

K4

F9 H9 H3

F4 H4 J10

J11

P3

D3

P2

D2 N3

E3

V9

A4

H1

C305

C305 100nF_6.3V

100nF_6.3V

C316

C316 1uF_6.3V

1uF_6.3V

136BALL-GDDR3

RASB0b(5,9)

CASB0b(5,9) CKEB0(5,9)

CSB0b_0(5,9) WEB0b(5,9) CLKB0b(5,9)

CLKB0(5,9)

DRAM_RST(5,9)

+MVDD

C302

C302 100nF_6.3V

100nF_6.3V

C313

C313 1uF_6.3V

1uF_6.3V

C324

C324 100nF_6.3V

100nF_6.3V

C329

C329 1uF_6.3V

1uF_6.3V

VDDQ

VDD

VSSQ

VSS

VDDA

VSSA

RFU2 RFU1 RFU0

MF

C308

C308 100nF_6.3V

100nF_6.3V

C319

C319 1uF_6.3V

1uF_6.3V

C334

C334 10uF_X6S

10uF_X6S

+MVDD A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

+MVDD A2 A11 F1 F12 M1 M12 V2 V11

B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 A3 A10 G1 G12 L1 L12 V3 V10

K1 K12

J12 J1

J3 J2 V4

A9

C309

C309 100nF_6.3V

100nF_6.3V

C320

C320 1uF_6.3V

1uF_6.3V

C335

C335 10uF_X6S

10uF_X6S

2

C342

C342 100nF_6.3V

100nF_6.3V

+MVDD

C336

C336 10uF_X6S

10uF_X6S

+MVDD

B301B301 B302B302

C343

C343 10nF

10nF

C392

C392 10nF

10nF

C393

C393 10nF

10nF

C310

C311

100nF_6.3V

C322

C321

1uF_6.3V

+MVDD +MVDD

+MVDD

R359

2.37K

R360

5.49K

+MVDD

R361

2.37K

R362

5.49K

+MVDD

C351

C351 100nF_6.3V

100nF_6.3V

C362

C362 1uF_6.3V

1uF_6.3V

C373

C373 100nF_6.3V

100nF_6.3V

C378

C378 1uF_6.3V

1uF_6.3V

1

U302

DQB_57

T3

DQ31 | DQ23

DQB_61

T2

DQ30 | DQ22

DQB_63

R3

DQ29 | DQ21

DQB_60

R2

DQ28 | DQ20

DQB_56

M3

DQ27 | DQ19

DQB_59

N2

DQ26 | DQ18

DQB_58

L3

DQ25 | DQ17

DQB_62

M2

DQ24 | DQ16

DQB_55

T10

DQ23 | DQ31

DQB_53

T11

DQ22 | DQ30

DQB_52

R10

DQ21 | DQ29

DQB_48

R11

DQ20 | DQ28

DQB_54

M10

DQ19 | DQ27

DQB_51

N11

DQ18 | DQ26

DQB_49

L10

DQ17 | DQ25

DQB_50

M11

DQ16 | DQ24

DQB_47

G10

DQ15 | DQ7

DQB_46

F11

DQ14 | DQ6

DQB_41

F10

DQ13 | DQ5

DQB_45

E11

DQ12 | DQ4

DQB_44

C10

DQ11 | DQ3

DQB_43

C11

DQ10 | DQ2

DQB_40

B10

DQ9 | DQ1

DQB_42

B11

DQ8 | DQ0

DQB_32

G3

DQ7 | DQ15

F2

DQ6 | DQ14

DQB_33

F3

DQ5 | DQ13

DQB_34

E2

DQ4 | DQ12

DQB_38

C3

DQ3 | DQ11

DQB_36

C2

DQ2 | DQ10

DQB_39

B3

DQ1 | DQ9

DQB_37

B2

DQ0 | DQ8

H10

BA2 | RAS

G9

BA1 | BA0

G4

BA0 | BA1

L4

A11 | A7

K2

A10 | A8

M9

A9 | A3

K11

A8/AP | A10

L9

A7 | A11

K10

A6 | A2

H11

A5 | A1

K9

A4 | A0

M4

A3 | A9

K3

A2 | A6

H2

A1 | A5

K4

A0 | A4

F9

CS | CAS

H9

WE | CKE

H3

RAS | BA2

F4

CAS | CS

H4

CKE | WE

J10

CK

J11

CK

P3

RDQS3 | RDQS2

P10

RDQS2 | RDQS3

D10

RDQS1 | RDQS0

D3

RDQS0 | RDQS1

P2

WDQS3 | WDQS2

P11

WDQS2 | WDQS3

D11

WDQS1 | WDQS0

D2

WDQS0 | WDQS1

N3

DM3 | DM2

N10

DM2 | DM3

E10

DM1 | DM0

E3

DM0 | DM1

V9

RESET

R310

A4

ZQ

243R

H1

VREF

C389

H12

VREF#H12

10nF

136BALL-GDDR3

C391

C391 10nF

10nF

C353

C353 100nF_6.3V

100nF_6.3V

C364

C364 1uF_6.3V

1uF_6.3V

C355

C356

C354

C354 100nF_6.3V

100nF_6.3V

C365

C365 1uF_6.3V

1uF_6.3V

Title

Title Size Document Number Rev

Size Document Number Rev

C

Date: Sheet

C356

100nF_6.3V

C367

C366

1uF_6.3V

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

RV630 GDDR3 - MEM CH A&B 128-bit 256MB RANK 0

CSB1b_0(5,9)

WEB1b(5,9) RASB1b(5,9) CASB1b(5,9) CKEB1(5,9) CLKB1b(5,9)

CLKB1(5,9)

DRAM_RST(5,9)

C388

C388 100nF_6.3V

100nF_6.3V

C390

100nF_6.3V

C352

C352 100nF_6.3V

100nF_6.3V

C363

C363 1uF_6.3V

1uF_6.3V

C374

C374 100nF_6.3V

100nF_6.3V

C379

C379 1uF_6.3V

1uF_6.3V

MAB_BA2 MAB_BA1 MAB_BA0

MAB_11 MAB_10 MAB_9 MAB_8 MAB_7 MAB_6 MAB_5 MAB_4 MAB_3 MAB_2 MAB_1 MAB_0

QSB_7 QSB_6 QSB_5 QSB_4

QSBb_7 QSBb_6 QSBb_5 QSBb_4

DQMBb_7 DQMBb_6 DQMBb_5 DQMBb_4

A1

VDDQ

A12

VDDQ#A12

C1

VDDQ#C1

C4

VDDQ#C4

C9

VDDQ#C9

C12

VDDQ#C12

E1

VDDQ#E1

E4

VDDQ#E4

E9

VDDQ#E9

E12

VDDQ#E12

J4

VDDQ#J4

J9

VDDQ#J9

N1

VDDQ#N1

N4

VDDQ#N4

N9

VDDQ#N9

N12

VDDQ#N12

R1

VDDQ#R1

R4

VDDQ#R4

R9

VDDQ#R9

R12

VDDQ#R12

V1

VDDQ#V1

V12

VDDQ#V12

A2

VDD

A11

VDD#A11

F1

VDD#F1

F12

VDD#F12

M1

VDD#M1

M12

VDD#M12

V2

VDD#V2

V11

VDD#V11

B1

VSSQ

B4

VSSQ#B4

B9

VSSQ#B9

B12

VSSQ#B12

D1

VSSQ#D1

D4

VSSQ#D4

D9

VSSQ#D9

D12

VSSQ#D12

G2

VSSQ#G2

G11

VSSQ#G11

L2

VSSQ#L2

L11

VSSQ#L11

P1

VSSQ#P1

P4

VSSQ#P4

P9

VSSQ#P9

P12

VSSQ#P12

T1

VSSQ#T1

T4

VSSQ#T4

T9

VSSQ#T9

T12

VSSQ#T12

A3

VSS

A10

VSS#A10

G1

VSS#G1

G12

VSS#G12

L1

VSS#L1

L12

VSS#L12

V3

VSS#V3

V10

VSS#V10

K1

VDDA

K12

VDDA#K12

J12

VSSA#J12

J1

VSSA

J3

RFU2

J2

RFU1

V4

RFU0

A9

MF

GND | VDD

C357

C358

100nF_6.3V

C369

C368

1uF_6.3V

C384

C384 10uF_X6S

10uF_X6S

105-B148xx-00D

1

+MVDD

C394

C394 100nF

100nF

C359

C359 100nF_6.3V

100nF_6.3V

C370

C370 1uF_6.3V

1uF_6.3V

C385

C385 10uF_X6S

10uF_X6S

821Wednesday, May 09, 2007

C395

C395 10nF

10nF

C360

C360 100nF_6.3V

100nF_6.3V

C371

C371 1uF_6.3V

1uF_6.3V

C386

C386 10uF_X6S

10uF_X6S

of

+MVDD

B351B351 B352B352

C361

C361 100nF_6.3V

100nF_6.3V

C372

C372 1uF_6.3V

1uF_6.3V

C387

C387 10uF_X6S

10uF_X6S

3

5

DQA_[63..0](5,8)

DQMAb_[7..0](5,8)

CSA0b_1(5) CSA1b_1(5)

C423

C423 100nF_6.3V

100nF_6.3V

C428

C428 1uF_6.3V

1uF_6.3V

QSA_[7..0] (5,8)

QSAb_[7..0] (5,8)

C444

C444 10nF

10nF

C445

C445 10nF

10nF

C402

C402 100nF_6.3V

100nF_6.3V

C413

C413 1uF_6.3V

1uF_6.3V

C426

C426 100nF_6.3V

100nF_6.3V

C431

C431 1uF_6.3V

1uF_6.3V

+MVDD

C403

C403 100nF_6.3V

100nF_6.3V

C414

C414 1uF_6.3V

1uF_6.3V

C427

C427 100nF_6.3V

100nF_6.3V

C432

C432 1uF_6.3V

1uF_6.3V

QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7

QSAb_0

D D

QSAb_1 QSAb_2 QSAb_3 QSAb_4 QSAb_5 QSAb_6 QSAb_7

C C

B B

+MVDD

A A

+MVDD

DQMAb_0 DQMAb_1 DQMAb_2 DQMAb_3 DQMAb_4 DQMAb_5 DQMAb_6 DQMAb_7

R401

2.37K

R402

5.49K

R415

2.37K

R418

5.49K

R428

R428 121R

121R R429

R429 121R

121R

DRAM_RST(5,8)

+MVDD

C404

C404 100nF_6.3V

100nF_6.3V

C415

C415 1uF_6.3V

1uF_6.3V

CSA0b_1(5)

WEA0b(5,8) RASA0b(5,8) CASA0b(5,8) CKEA0(5,8) CLKA0b(5,8)

CLKA0(5,8)

C438

C438 100nF_6.3V

100nF_6.3V

+MVDD

C440

C440 100nF_6.3V

100nF_6.3V

C405

C405 100nF_6.3V

100nF_6.3V

C416

C416 1uF_6.3V

1uF_6.3V

5

DQA_31 DQA_28 DQA_29 DQA_30 DQA_27 DQA_26 DQA_24 DQA_25 DQA_9 DQA_11 DQA_10 DQA_12 DQA_8 DQA_13 DQA_15 DQA_14 DQA_16 DQA_17 DQA_23 DQA_18 DQA_21 DQA_19 DQA_22 DQA_20 DQA_2 DQA_4 DQA_1 DQA_3 DQA_7 DQA_5 DQA_0 DQA_6

MAA_BA2 MAA_BA1 MAA_BA0

MAA_11 MAA_10 MAA_9 MAA_8 MAA_7 MAA_6 MAA_5 MAA_4 MAA_3 MAA_2 MAA_1 MAA_0

QSA_3 QSA_1 QSA_2 QSA_0

QSAb_3 QSAb_1 QSAb_2 QSAb_0

DQMAb_3 DQMAb_1 DQMAb_2 DQMAb_0

R400

R400 243R

243R

C406

C406 100nF_6.3V

100nF_6.3V

C417

C417 1uF_6.3V

1uF_6.3V

C439

C439 10nF

10nF

C441

C441 10nF

10nF

U401

T3 T2

R3 R2 M3 N2

L3

M2 T10 T11 R10 R11

M10 N11

L10

M11 G10

F11 F10

E11 C10 C11 B10 B11

G3

F2 F3

E2 C3 C2

B3

B2

H10

G9 G4

L4

K2 M9

K11

L9

K10 H11

K9 M4

K3 H2

K4

F9 H9 H3

F4 H4

J10 J11

P3

P10 D10

D3

P2

P11 D11

D2 N3

N10 E10

E3

V9

A4

H1

H12

136BALL-GDDR3

C407

C407 100nF_6.3V

100nF_6.3V

C418

C418 1uF_6.3V

1uF_6.3V

C434

C434 10uF_X6S

10uF_X6S

BA2 | RAS BA1 | BA0 BA0 | BA1

A11 | A7 A10 | A8 A9 | A3 A8/AP | A10 A7 | A11 A6 | A2 A5 | A1 A4 | A0 A3 | A9 A2 | A6 A1 | A5 A0 | A4

CK RDQS3 | RDQS2

RDQS2 | RDQS3 RDQS1 | RDQS0 RDQS0 | RDQS1

WDQS3 | WDQS2 WDQS2 | WDQS3 WDQS1 | WDQS0 WDQS0 | WDQS1

DM3 | DM2 DM2 | DM3 DM1 | DM0 DM0 | DM1

RESET ZQ

VREF VREF#H12

+MVDD

CKEB1(5,8) CSB1b_0(5,8) WEB1b(5,8) RASB1b(5,8) CASB1b(5,8)

C408

C408 100nF_6.3V

100nF_6.3V

C419

C419 1uF_6.3V

1uF_6.3V

C435

C435 10uF_X6S

10uF_X6S

VDDQ

VDDQ#A12

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#C12

VDDQ#E1 VDDQ#E4 VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9 VDDQ#N1 VDDQ#N4 VDDQ#N9

VDDQ#N12

VDDQ#R1 VDDQ#R4 VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4 VSSQ#B9

VSSQ#B12

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1 VSSQ#P4 VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

GND | VDD

CLKA0(5,8) CLKA0b(5,8) CLKB0(5,8) CLKB0b(5,8)

CKEB0(5,8) CSB0b_0(5,8) WEB0b(5,8) RASB0b(5,8) CASB0b(5,8)

CLKA1(5,8) CLKA1b(5,8) CLKB1(5,8) CLKB1b(5,8)

C409

C409 100nF_6.3V

100nF_6.3V

C420

C420 1uF_6.3V

1uF_6.3V

+MVDD +MVDD

C436

C436 10uF_X6S

10uF_X6S

VDD

VSSQ

VSS

VDDA

VSSA

RFU2 RFU1 RFU0

MF

C410

C410 100nF_6.3V

100nF_6.3V

C421

C421 1uF_6.3V

1uF_6.3V

C437

C437 10uF_X6S

10uF_X6S

+MVDD A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

+MVDD A2 A11 F1 F12 M1 M12 V2 V11

B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 A3 A10 G1 G12 L1 L12 V3 V10

K1 K12

C442

C442 100nF_6.3V

100nF_6.3V

J12 J1

J3 J2 V4

A9

R437 121RR437 121R R438 121RR438 121R R430 121RR430 121R R431 121RR431 121R

R432 121RR432 121R R433 121RR433 121R R434 121RR434 121R R435 121RR435 121R R436 121RR436 121R

R446 121RR446 121R R447 121RR447 121R R439 121RR439 121R R440 121RR440 121R

R441 121RR441 121R R442 121RR442 121R R443 121RR443 121R R444 121RR444 121R R445 121RR445 121R

+MVDD

C443

C443 10nF

10nF

+MVDD

C473

C473 100nF_6.3V

100nF_6.3V

C478

C478 1uF_6.3V

1uF_6.3V

4

Rank 1 Bottom Layer

RASA1b(5,8)

+MVDD

B401B401 B402B402

+MVDD

C492

R408

10nF

2.37K

R409

5.49K

+MVDD

R410

C493

2.37K

10nF

R411

5.49K

C453

C452

100nF_6.3V

C464

C463

1uF_6.3V

C475

C474

100nF_6.3V

C479

C480

1uF_6.3V

4

CASA1b(5,8) CKEA1(5,8)

CSA1b_1(5) WEA1b(5,8) CLKA1b(5,8)

CLKA1(5,8)

DRAM_RST(5,8)

+MVDD

DQA_54 DQA_52 DQA_53 DQA_50 DQA_55 DQA_51 DQA_48 DQA_49 DQA_63 DQA_56 DQA_62 DQA_60 DQA_58 DQA_57 DQA_59 DQA_61 DQA_32 DQA_34 DQA_35 DQA_33 DQA_38 DQA_37 DQA_39 DQA_36 DQA_47 DQA_46 DQA_40 DQA_45 DQA_42 DQA_43 DQA_41 DQA_44

MAA_BA0 MAA_BA1

MAA_7 MAA_8 MAA_3 MAA_10 MAA_11 MAA_2 MAA_1 MAA_0 MAA_9 MAA_6 MAA_5 MAA_4

QSA_6 QSA_7 QSA_4 QSA_5

QSAb_6 QSAb_7 QSAb_4 QSAb_5

DQMAb_6 DQMAb_7 DQMAb_4 DQMAb_5

C488

C488 100nF_6.3V

100nF_6.3V

C490

C490 100nF_6.3V

100nF_6.3V

C454

C454 100nF_6.3V

100nF_6.3V

C465

C465 1uF_6.3V

1uF_6.3V

C476

C476 100nF_6.3V

100nF_6.3V

C481

C481 1uF_6.3V

1uF_6.3V

MAA_BA2

R407

R407 243R

243R

MAA_BA[2..0](5,8)

C455

C455 100nF_6.3V

100nF_6.3V

C466

C466 1uF_6.3V

1uF_6.3V

C489

C489 10nF

10nF

MAA_[11..0](5,8)

T3

T2 R3 R2 M3 N2

L3 M2

T10 T11 R10 R11 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B10 B11

G3

F2

F3

E2 C3 C2

B3

B2

H10

G9 G4

L4

K2 M9

K11

L9

K10 H11

K9 M4

K3 H2

K4

F9 H9 H3

F4 H4 J10

J11

P3

P10 D10

D3

P2

P11 D11

D2 N3

N10 E10

E3

V9

A4

H1

H12

C491

C491 10nF

10nF

C456

C456 100nF_6.3V

100nF_6.3V

C467

C467 1uF_6.3V

1uF_6.3V

U402

BA2 | RAS BA1 | BA0 BA0 | BA1

A11 | A7 A10 | A8 A9 | A3 A8/AP | A10 A7 | A11 A6 | A2 A5 | A1 A4 | A0 A3 | A9 A2 | A6 A1 | A5 A0 | A4

CK RDQS3 | RDQS2

RDQS2 | RDQS3 RDQS1 | RDQS0 RDQS0 | RDQS1

WDQS3 | WDQS2 WDQS2 | WDQS3 WDQS1 | WDQS0 WDQS0 | WDQS1

DM3 | DM2 DM2 | DM3 DM1 | DM0 DM0 | DM1

RESET ZQ

VREF VREF#H12

136BALL-GDDR3

+MVDD

MAA_BA0 MAA_BA1 MAA_BA2

MAA_11 MAA_10 MAA_9 MAA_8 MAA_7 MAA_6 MAA_5 MAA_4 MAA_3 MAA_2 MAA_1 MAA_0

C457

C457 100nF_6.3V

100nF_6.3V

C468

C468 1uF_6.3V

1uF_6.3V

C484

C483

10uF_X6S

3

QSB_[7..0] (5,8)

B451B451 B452B452

+MVDD

3

DQB_[63..0](5,8)

QSBb_[7..0] (5,8)

DQMBb_0 DQMBb_1 DQMBb_2 DQMBb_3 DQMBb_4 DQMBb_5 DQMBb_6 DQMBb_7

+MVDD

C544

C544 10nF

10nF

C545

C545 10nF

10nF

+MVDD

C501

C501 100nF_6.3V

100nF_6.3V

C512

C512 1uF_6.3V

1uF_6.3V

+MVDD

C528

C528 1uF_6.3V

1uF_6.3V

U501

R500

R500 243R

243R

C539

C539 10nF

10nF

C541

C541 10nF

10nF

C504

C504 100nF_6.3V

100nF_6.3V

C515

C515 1uF_6.3V

1uF_6.3V

T3

T2 R3 R2 M3 N2

L3 M2

T10 T11 R10 R11 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B10 B11

G3

F2

F3

E2 C3 C2

B3

B2

H10

G9 G4

L4

K2 M9

K11

L9

K10 H11

K9 M4

K3 H2

K4

F9 H9 H3

F4 H4 J10

J11

P3

P10 D10

D3

P2

P11 D11

D2 N3

N10 E10

E3

V9

A4

H1

H12

CSB0b_1(5) CSB1b_1(5)

C505

C505 100nF_6.3V

100nF_6.3V

C516

C516 1uF_6.3V

1uF_6.3V

U501

136BALL-GDDR3

DQB_15 DQB_12 DQB_13 DQB_14 DQB_8 DQB_10 DQB_9 DQB_11 DQB_26 DQB_25 DQB_27 DQB_30 DQB_24 DQB_29 DQB_31 DQB_28 DQB_17 DQB_18 DQB_20 DQB_19 DQB_23 DQB_16 DQB_21 DQB_22 DQB_0 DQB_1 DQB_46 DQB_3 DQB_7 DQB_5 DQB_2 DQB_6 DQB_4

MAB_BA2 MAB_BA1 MAB_BA0

MAB_11 MAB_10 MAB_9 MAB_8 MAB_7 MAB_6 MAB_5 MAB_4 MAB_3 MAB_2 MAB_1 MAB_0

CSB0b_1(5)

WEB0b(5,8) RASB0b(5,8) CASB0b(5,8) CKEB0(5,8) CLKB0b(5,8)

CLKB0(5,8)

QSB_1 QSB_3 QSB_2 QSB_0

QSBb_1 QSBb_3 QSBb_2 QSBb_0

DQMBb_1 DQMBb_3 DQMBb_2 DQMBb_0

R501

2.37K

C538

R502

100nF_6.3V

5.49K

+MVDD

R515

2.37K

C540

R518

100nF_6.3V

5.49K

C503

C502

100nF_6.3V

C514

C513

1uF_6.3V

C523

C523 100nF_6.3V

100nF_6.3V

QSB_0

+MVDD

C494

C494 100nF_6.3V

100nF_6.3V

+MVDD

C461

C461 100nF_6.3V

100nF_6.3V

C472

C472 1uF_6.3V

1uF_6.3V

QSBb_0 QSBb_1 QSBb_2 QSBb_3 QSBb_4 QSBb_5 QSBb_6 QSBb_7

C495

C495 10nF

10nF

MAB_BA0 MAB_BA1 MAB_BA2

MAB_11 MAB_10 MAB_9 MAB_8 MAB_7 MAB_6 MAB_5 MAB_4 MAB_3 MAB_2 MAB_1 MAB_0

QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7

DQMBb_[7..0](5,8)

VDDQ#A12

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#C12

VDDQ#E1 VDDQ#E4 VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9 VDDQ#N1 VDDQ#N4 VDDQ#N9

VDDQ#N12

VDDQ#R1 VDDQ#R4 VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F12

VDD#M1

VDD#M12

VDD#V11

VSSQ#B4

VSSQ#B9

VSSQ#B12

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1

VSSQ#P4

VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G12

VSS#L12 VSS#V10

VDDA#K12

VSSA#J12

C458

C458 100nF_6.3V

100nF_6.3V

C469

C469 1uF_6.3V

1uF_6.3V

VDDQ

VDD

VDD#F1

VDD#V2

VSSQ

VSS

VSS#G1

VSS#L1

VSS#V3

VDDA

VSSA

RFU2 RFU1 RFU0

GND | VDD

MAB_BA[2..0](5,8)

C459

C459 100nF_6.3V

100nF_6.3V

C470

C470 1uF_6.3V

1uF_6.3V

C485

C485 10uF_X6S

10uF_X6S

MF

MAB_[11..0](5,8)

C486

C486 10uF_X6S

10uF_X6S

A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

A2 A11 F1 F12 M1 M12 V2 V11

B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 A3 A10 G1 G12 L1 L12 V3 V10

K1 K12

J12 J1

J3 J2 V4

A9

C460

C460 100nF_6.3V

100nF_6.3V

C471

C471 1uF_6.3V

1uF_6.3V

www.vinafix.vn

BA2 | RAS BA1 | BA0 BA0 | BA1

A11 | A7 A10 | A8 A9 | A3 A8/AP | A10 A7 | A11 A6 | A2 A5 | A1 A4 | A0 A3 | A9 A2 | A6 A1 | A5 A0 | A4

CK RDQS3 | RDQS2

RDQS2 | RDQS3 RDQS1 | RDQS0 RDQS0 | RDQS1

WDQS3 | WDQS2 WDQS2 | WDQS3 WDQS1 | WDQS0 WDQS0 | WDQS1

DM3 | DM2 DM2 | DM3 DM1 | DM0 DM0 | DM1

RESET ZQ

VREF VREF#H12

+MVDD

C507

C506

100nF_6.3V

C517

C518

1uF_6.3V

VDDQ#A12

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#C12

VDDQ#E1 VDDQ#E4 VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9 VDDQ#N1 VDDQ#N4 VDDQ#N9

VDDQ#N12

VDDQ#R1 VDDQ#R4 VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4 VSSQ#B9

VSSQ#B12

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1 VSSQ#P4 VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L12

VSS#V10

VDDA#K12

VSSA#J12

GND | VDD

R528

R528 121R

121R R529

R529 121R

121R

C508

C508 100nF_6.3V

100nF_6.3V

C519

C519 1uF_6.3V

1uF_6.3V

C534

C534 10uF_X6S

10uF_X6S

2

+MVDD

A1

VDDQ

A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

+MVDD

A2

VDD

A11 F1

VDD#F1

F12 M1 M12 V2 V11

B1

VSSQ

B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 A3

VSS

A10 G1 G12 L1

VSS#L1

L12 V3

VSS#V3

V10

C543

C543 10nF

10nF

C511

C511 100nF_6.3V

100nF_6.3V

C522

C522 1uF_6.3V

1uF_6.3V

C537

C537 10uF_X6S

10uF_X6S

C592

C592 10nF

10nF

C593

C593 10nF

10nF

B501B501 B502B502

+MVDD

+MVDD+MVDD

+MVDD

K1

VDDA

K12

C542

C542 100nF_6.3V

100nF_6.3V

J12 J1

VSSA

J3

RFU2

J2

RFU1

V4

RFU0

A9

MF

+MVDD

C510

C509

100nF_6.3V

C520

C521

1uF_6.3V

+MVDD +MVDD

C535

C536

10uF_X6S

2

+MVDD

R508

2.37K

R509

5.49K

R510

2.37K

R511

5.49K

C551

C551 100nF_6.3V

100nF_6.3V

C562

C562 1uF_6.3V

1uF_6.3V

C573

C573 100nF_6.3V

100nF_6.3V

C578

C578 1uF_6.3V

1uF_6.3V

RASB1b(5,8)

CASB1b(5,8) CKEB1(5,8)

CSB1b_1(5) WEB1b(5,8) CLKB1b(5,8)

CLKB1(5,8)

DRAM_RST(5,8)DRAM_RST(5,8)

C588

C588 100nF_6.3V

100nF_6.3V

+MVDD

C552

C552 100nF_6.3V

100nF_6.3V

C563

C563 1uF_6.3V

1uF_6.3V

C574

C574 100nF_6.3V

100nF_6.3V

C579

C579 1uF_6.3V

1uF_6.3V

DQB_55 DQB_53 DQB_52 DQB_48 DQB_54 DQB_51 DQB_49 DQB_50 DQB_57 DQB_61 DQB_63 DQB_60 DQB_56 DQB_59 DQB_58 DQB_62 DQB_32 DQB_35 DQB_33 DQB_34 DQB_38 DQB_36 DQB_39 DQB_37 DQB_47

DQB_41 DQB_45 DQB_44 DQB_43 DQB_40 DQB_42

QSB_6 QSB_7 QSB_4 QSB_5

QSBb_6 QSBb_7 QSBb_4 QSBb_5

DQMBb_6 DQMBb_7 DQMBb_4 DQMBb_5

C590

C590 100nF_6.3V

100nF_6.3V

U502

T3

DQ31 | DQ23

T2

DQ30 | DQ22

R3

DQ29 | DQ21

R2

DQ28 | DQ20

M3

DQ27 | DQ19

N2

DQ26 | DQ18

L3

DQ25 | DQ17

M2

DQ24 | DQ16

T10

DQ23 | DQ31

T11

DQ22 | DQ30

R10

DQ21 | DQ29

R11

DQ20 | DQ28

M10

DQ19 | DQ27

N11

DQ18 | DQ26

L10

DQ17 | DQ25

M11

DQ16 | DQ24

G10

DQ15 | DQ7

F11

DQ14 | DQ6

F10

DQ13 | DQ5

E11

DQ12 | DQ4

C10

DQ11 | DQ3

C11

DQ10 | DQ2

B10

DQ9 | DQ1

B11

DQ8 | DQ0

G3

DQ7 | DQ15

F2

DQ6 | DQ14

F3

DQ5 | DQ13

E2

DQ4 | DQ12

C3

DQ3 | DQ11

C2

DQ2 | DQ10

B3

DQ1 | DQ9

B2

DQ0 | DQ8

H10

BA2 | RAS

MAB_BA0

G9

BA1 | BA0

MAB_BA1

G4

BA0 | BA1

MAB_7

L4

A11 | A7

MAB_8

K2

A10 | A8

MAB_3

M9

A9 | A3

MAB_10

K11

A8/AP | A10

MAB_11

L9

A7 | A11

MAB_2

K10

A6 | A2

MAB_1

H11

A5 | A1

MAB_0

K9

A4 | A0

MAB_9

M4

A3 | A9

MAB_6

K3

A2 | A6

MAB_5

H2

A1 | A5

MAB_4

K4

A0 | A4

F9

CS | CAS

H9

WE | CKE

MAB_BA2

H3

RAS | BA2

F4

CAS | CS

H4

CKE | WE

J10

CK

J11

CK

P3

RDQS3 | RDQS2

P10

RDQS2 | RDQS3

D10

RDQS1 | RDQS0

D3

RDQS0 | RDQS1

P2

WDQS3 | WDQS2

P11

WDQS2 | WDQS3

D11

WDQS1 | WDQS0

D2

WDQS0 | WDQS1

N3

DM3 | DM2

N10

DM2 | DM3

E10

DM1 | DM0

E3

DM0 | DM1

V9

RESET

R507

A4

ZQ

243R

H1

VREF

C589

H12

VREF#H12

10nF

136BALL-GDDR3

+MVDD

C591

C591 10nF

10nF

C554

C553

100nF_6.3V

C564

C565

1uF_6.3V

C575

C575 100nF_6.3V

100nF_6.3V

C580

C580 1uF_6.3V

1uF_6.3V

Title

Title Size Document Number Rev

Size Document Number Rev

C

Date: Sheet

C556

C555

100nF_6.3V

C567

C566

1uF_6.3V

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

RV630 GDDR3 - MEM CH A&B 128-bit 256MB RANK 1

105-B148xx-00D

1

VDDQ

VDDQ#A12

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#C12

VDDQ#E1 VDDQ#E4 VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9 VDDQ#N1 VDDQ#N4 VDDQ#N9

VDDQ#N12

VDDQ#R1 VDDQ#R4 VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ VSSQ#B4 VSSQ#B9

VSSQ#B12

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1 VSSQ#P4 VSSQ#P9

VSSQ#P12

VSSQ#T1 VSSQ#T4 VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VDDA#K12

VSSA#J12

VSSA

RFU2

RFU1

RFU0

GND | VDD

C557

C557 100nF_6.3V

100nF_6.3V

C568

C568 1uF_6.3V

1uF_6.3V

C583

C583 10uF_X6S

10uF_X6S

1

VDD

VSS

MF

A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

A2 A11 F1 F12 M1 M12 V2 V11

B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 A3 A10 G1 G12 L1 L12 V3 V10

K1 K12

J12 J1

J3 J2 V4

A9

C558

C558 100nF_6.3V

100nF_6.3V

C569

C569 1uF_6.3V

1uF_6.3V

C584

C584 10uF_X6S

10uF_X6S

+MVDD

C594

C594 100nF_6.3V

100nF_6.3V

+MVDD

C559

C559 100nF_6.3V

100nF_6.3V

C570

C570 1uF_6.3V

1uF_6.3V

C585

C585 10uF_X6S

10uF_X6S

C586

C586 10uF_X6S

10uF_X6S

921Wednesday, May 09, 2007

C595

C595 10nF

10nF

C560

C560 100nF_6.3V

100nF_6.3V

C571

C571 1uF_6.3V

1uF_6.3V

of

+MVDD

B551B551 B552B552

C561

C561 100nF_6.3V

100nF_6.3V

C572

C572 1uF_6.3V

1uF_6.3V

3

8

D D

+PW_VDDC_HGDR

UGATE(11)

+PW_VDDC_M

PHASE(11)

+PW_VDDC_LGDR

LGATE(11)

VDDC2_FB(13)

+VDDC_B

C C

+PW_VDDC_HGD

+PW_VDDC_LGD

R1315

42.2K

place R1315 close to IC pin4

List of supported foodprint The following ICs are not necessarily evaluated by

ATI, please refer to BOM for evaluation status

ANPEC APW7120/APW7065 (12V) CAT CAT7583 (12V) INTERSIL ISL6545 NEXSEM NX2114/2307 RICHTEK RT9214/RT8101 OnSemi ON1582 uPI UP6101 (No Ext_Vref in)

B B

Layout guideline for Nexsem NX2114/2307

1-Position the controller (U703) such that LGate(pin4) is the closet to gate of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as short and as wide as possible to reduce the trace inductance. 2-Place the bypass capacitors for Vcc as well as Boost caps as close to the controller as possible. They are as follows; Vcc bypass cap is C703, and Boost cap is C705. 3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place the rest of the compensation network close to the pins 7 and 6. These are R710, R711, R713, C713 and R712, C711 and C712.

U1303

1

BOOT

2

UGATE

3

GND LGATE4VCC

APW7065

PHASE

COMP

VDDC_FB

FB

8 7 6 5

+PW_VDDC_M VDDC_COMP

VDDC_FB

COMPENSATION CIRCUIT FILTERED SMPS VCC

402

C1311

C1311 15nF

15nF

10V

A A

402

R1312

2.94K

402 1%

10%

VDDC_COMP

C1312

C1314

390pF

100nF

603

402

50V 5%

NPOX7R

X5R

R1314 0RR1314 0R

R13090RR1309 0R

share pad of R1314,R1309

8

10V 10%

VDDC_FB

7

+VDD_VCC

7

C1303

0.22uF

+PW_VDDC_LGD

VDDC_EN (11)

R1308 20KR1308 20K

+12V_BUS

R1307

2.2R

C1307

C1307 100nF

100nF

+PW_VDDC_HGD +PW_VDDC_HGDR

+PW_VDDC_M

+PW_VDDC_LGDR

R13220RR1322

603

0R

402

BOOT CIRCUIT

+5V

MR1307

2.2R

603 X7R 5%

6

R1321 0RR1321 0R

3

D1301

1

BAT54A

C1305

C1305 100nF

100nF

603 X7R 5%

6

402

QL

2

16V

Q1302

Thermal

Pad

4 5 3 2 1

BSC119N03SG

+PW_VDDC_HGDR

+PW_VDDC_M

+12V_BUS +5V

MR13060RMR1306 0R

402

C1306

C1306 150nF_16V

150nF_16V

+VDDC_B

Q1301

QH

Thermal

4 5 3 2 1

BSC119N03SG

9

6 7 8

MQ1301

Thermal

Pad

4 5 3 2 1

FDS7096N3

R13060RR1306 0R

402

+PW_VDDC_M

5

Pad

9

6 7 8

RC snubber values shown are for reference only, tuning is required

VDDC_FB

+VDDC_Source

9

6 7 8

5

ML1301

1 2

R1319

R1319 33MOHM

33MOHM

1210 1%

C1308

C1308 10nF_25V

10nF_25V

402 X7R 25V

Place Rs and Cs across QL

PCMC104T-1R5MN

L1301

1.7UH

Rs

Cs

MULTI FOOTPRINT

12

NS1300

NS1300 NS_VIA

NS_VIA

C1313

3.9nF

402 10%

R1

RFB1

R1313

R1311

3.65K

4.99K

402

5%

1%

R4

Place R1 and R4 close to

RFB2

PWM and

R1310

routed with

3.24K

separate

402

20mil trace to

1%

the ASIC

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

+PW_VDDC_LGDR

MQ1302

Thermal

Pad

4 5 3 2 1

FDS7096N3

4

L1322

R13200RR1320

R13180RR1318 0R

C1349

4.7uF_16V

805

16V X7R

0R

C1339

4.7uF_16V

805

IND_0.47uH_7A

3

+12V_BUS

C1395

100uF_16V

C1343

C1343 10UF_16V

10UF_16V

1206

100uF_16V

SM 6.3mm Dia

C1382

C1344

270uF_16V

180uF_16V

TH 10mm Dia

SM 10mm Dia

+VDDC +VDDC +VDDC

***

C1325

C1325 1500uF_2.5V

1500uF_2.5V

***

Overlap

L1323

0.47uH

Overlap

C1337

C1340

4.7uF_16V

Mirrored on PCBMirrored on PCB Overlap

C1323

Y5V

10uf

6.3V

1206

Mirrored on PCB

4.7uF_16V

C1324

Y5V

10uf

6.3V

1206

C1330

C1330 10UF_16V

10UF_16V

1206805805

Mirrored on PCB

+VDDC

2

+VDDC_Source

***

MC1325

MC1325 1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT8 mm Dia, SMT

***

NC1325

NC1325 820uF_2.5V

820uF_2.5V

***

8 x 8 mm, TH

1

SMPS02- Regulator for VDDC

Vout = 0.9V ~ 1.1V

9

6 7 8

4

MULTI FOOTPRINT

Part RFB2RFB1

0.8V Ref

SMPS02 Specifications

Vin 12V(power stage) +/-8% PCIe ATX12V ver. 2.2 +/-5%

Vout 2V

Vout ripple (DC) 50mVpp

Iout 6Aavg, 8Adc_max

Step load 3Amax

Protections

3

Vout

2.03V (1.98V~2.08V)

Title

Title Size Document Number Rev

Size Document Number Rev

Size Document Number Rev Date: Sheet of

Date: Sheet

2

4.99K p/n 3160499100G

Nominal Value Adjustable range / Notes

+/-10% or 200mVpp @ 3A step loadVout ripple (AC)

RV630 GDDR3 - VDDC SMPS 01

Custom

Tolerance

;

+2%/-2%

;

~300kHzSwitching Freq. TBD

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

105-B148xx-00D

3.24K p/n 3160324100G

1.8V ~ 2.85V

10 21Wednesday, May 09, 2007

1

of

3

www.vinafix.vn

Information on Compatable Controller Parts

Gate drive voltage 5V, 8V, 12V 5V, 8V, 12V 5V only 12V only

Bootstrap diodes Internal

Phase current adjustable (unbalanced between phases) Option Pin Selection

D D

Pin 12 (COMP/DROOP) COMP COMP

Pin 16 (REFOUT/POK)

Pin 21 (VCCDRV/DROOP)

External Detection Circuit and Indication

Cases

External cable not plugged in +12V_BUS not in regulation

External cable not plugged in +12V_BUS in regulation EN1 -> 3V (by Ri1 and Ri2)

External cable plugged in +12V_XXX not in regulation

C C

External cable plugged in 12V_EXT_DETb = "0" +12V_XXX in regulation

B B

Q601

Thermal

UGATE1

BSC119N03SG

PHASE1

A A

Q603

BSC042N03S

LGATE1

8

PWM IC #2 PWM IC #4PWM IC #1 PWM IC #3

0.6V 0.6V 0.6V0.6VVref

(DNP D601, D611)

Yes Yes Yes TBD

IOUT/DROOP (R662)

POK (Open drain)

VCCDRV

Behaviour

12V_EXT_DETb = X EN1 -> "0" (by Ri2) ENb1 -> 3.3V ENBUS = "0"

ENb1 = 0V ENBUS = "1"

12V_EXT_DETb = "0" EN1 < 3V (due to low 12V) ENb1 = 3.3V ENBUS = "0"

EN1 -> 3V ENb1 = 0V ENBUS = "1"

UGATE1

UGATE(10)

PHASE1

PHASE(10)

LGATE1

LGATE(10)

R6080RR608

R6090RR609

0R

C632

C634

4.7uF_16V

805805

Actual Vendor TBD Actual Vendor TBD

Q604

BSC042N03S

LGATE1

8

9

Pad

C635

4.7uF_16V

Mirrored on PCB

678

4 5

567

9

432

123

8

1

Internal (DNP D601, D611)

IOUT/IMAXPin 10 (IOUT/IMAX/DROOP) IOUT IOUT/IMAX

TBD R_RT ~= 18,600,000/FswPin 11 (RT) R_RT ~= 10,000,000/Fsw TBD

DROOP (R663)

GND (SS fixed internally)

IREFOUT/POK POK voltage = 1.2V

VCCDRV

Notifications

VDDC disabled

VDDC enabled12V_EXT_DETb = "1" External Power Missing

VDDC disabled

VDDC enabled Normal Operation

+12V_BUS

L620

L621

0.47uH

IND_0.47uH_7A

Overlap

C633

C621

4.7uF_16V

10UF_16V

805805

Mirrored on PCB

567

8

9

R607R607

432

1

FB_S

1/10W 0603

7

External (Populate D601, D611)

COMP

ICOMP (SS dependent on Fsw)

INREFOUT/POK PGood voltage = 1.25V

DROOP (R664)

C690

100uF_16V

SM 6.3mm Dia

C622

C623

10UF_16V

180uF_16V

12061206

SM 10mm Dia SM 10mm Dia

L601

1 2

PCMB105T-R47MS

ML601

220nH_31A

NL601

1 2

HC1018

KL601

1 2

R604

R604 221R

221R

C604

X7R

1UF_16V

R602R602

CSP1

7

Internal (DNP D601, D611)

SSSS/ENPin 14 (SS/ICOMP)

INREFOUT/PGOOD Vrefout = 0.6V

DROOP (R664)

12V Bus power for 12V Gate Drive

+12V_BUS +12V_BUS

402

+3.3V_BUS

R6801KR680 1K

402 1%

R697 1KR697 1K

R681

2.0K

402 1% DNI

When 12V is > 10V

VDDC_SHDN VDDC_EN

VDDC_SHDN(13)

+VDDC_Source

C680

C680 270uF_16V

270uF_16V

TH 10mm Dia

Overlap

L611

+VDDC

Overlap Overlap

1.7UH

R605

R605 221R

221R

CSN1

ML611

NL611

KL611

1.7UH

X7R

R615

R615 221R

221R

R612R612

CSN2

R670

R670 10R

10R

+12V_BUS

1

EN1 > 3V

C681

C681 270uF_16V

270uF_16V

TH 10mm Dia

Overlap

12

PCMB105T-R47MS

220nH_31A

12

HC1018

12

R614

R614 221R

221R

1/10W 0603

C614

C614 1UF_16V

1UF_16V

CSP2

6

Choosing Different Gate Drive

Gate Drive

5V Gate Drive R630, R670, C660,

8V Gate Drive R631, R632,

12V Gate Drive R630, C660,

Pass Transistor Circuit for 8V Gate Drive

This circuit is only for 8V gate drive application

R682

5.1K

5.1K R683 5.1KR683 5.1K

MMBT3904

Q678

2 3

C636

1uF_6.3V

R6980RR698 0R

C626

C626 180uF_16V

180uF_16V

R617R617

FB_S

6

Assume VCC consumes 200mA total including 5VCC providing buffered output sourcing a minimum 20mA requirement

32

Q661

1

SI2304DS

VCC

EN1

overlap pad

1

Q679

Q679 MMBT3904

MMBT3904

2 3

+12V_BUS

EN1

1206

Mirrored on PCB

678

123

4 5

BSC119N03SG

567

8

9

432

1

5

Populate

Do Not Populate

R631, R632

R661, Q661

R630, C660,

R670

R661, Q661

R631, R632,

R670

R661, Q661

P(Q_8VCC)max = (12V-8V)*0.2A = 800mW

R661

R661 10K

10K

R6860R R6860R R6850R R6850R R6840R R6840R

R666

12.1K

R667

R667 10K

10K

C625

C625 10UF_16V

10UF_16V

9

Q611

Thermal

Pad

UGATE2

Q613

BSC042N03S

VDDC_EN

SS_ICOMP

VDDC_REFIN_EN

C627

C624

4.7uF_16V

10UF_16V

Mirrored on PCB

VCCDRV

VDDC_EN (10)

C628

4.7uF_16V

805805

567

8

432

1

5

9

C670

C670 10UF

10UF

1206 X5R 16V

PHASE2

Q614

BSC042N03S

LGATE2LGATE2

D611

2

3

Overlap

BAT54A

LGATE2

R664

R664 100K

100K

LGATE1

D601

BAT54A

1

C612

C612 1uF

1uF

PHASE2

R6130RR613 0R

VCC

R6030RR603 0R

PHASE1

C602

C602 1uF

1uF

1

2

+VDDC +VDDC

***

C641

C641 1500uF_2.5V

1500uF_2.5V

***

C642

C642 1500uF_2.5V

1500uF_2.5V

***

OPTIONAL

Rdroop

Droop Option

C694

C694 1UF_16V

1UF_16V

X7R 603

OPTIONAL

Populate - For 5V Gate Drive application Remove - For 8V or 12V Gate Drive application

C631

C629

4.7uF_16V

8051206

805

Mirrored on PCB

TP601

TP601 35mil

35mil

UGATE1

UGATE2

19

20

21

22

23

24 25

26 27 28 29

4

POK > 1 used to control other on-board enables

PWRGD1

R634 10KR634 10K

R6110RR611 0R

U601

18

uPI6201Q

UGATE2

PHASE2

LGATE2

VCCDRV/DROOP

VCC

LGATE1

PHASE1 PGND

PGND26 PGND27 PGND28 PGND29

UGATE11BOOT125VCC3AGND4BUSEN5CSP1

R601 0RR601 0R

R632R632

***

MC641

MC641 1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT8 mm Dia, SMT

+VDDC+VDDC

***

MC642

MC642 1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT8 mm Dia, SMT

4

+VDDC

17

BOOT2

5VCC

***

NC641

NC641 820uF_2.5V

820uF_2.5V

***

8 x 8 mm, TH

***

NC642

NC642 820uF_2.5V

820uF_2.5V

***

8 x 8 mm, TH

16

REFOUT/POK

3

5VCC

R6361KR636

External Reference is used when REFIN is driven by voltage ranged from 0.4V to 3.3V

VDDC_REFIN_EN

C659

C659 100nF

100nF

402 10V

Overlap the footprints for MR655 and C655

Current

PGND Option

Compensation

Css if current

C655

comp. not used

SS_ICOMP

14

13

SS/ICOMP

COMP/DROOP

IOUT/IMAX/DROOP

6

C671

C671 100nF

100nF

402 10V X5R

+5V

R6310RR631 0R

C646

Y5V

10uf

1206 6.3V

3

C655

6.8nF

402 25V

FB

RT

CSP2

CSN2

CSN1

VDDC_EN

C647

Y5V

10uf

1206 6.3V

MR6550RMR655

0R

15

REFIN/EN

C660

C660 1uF_6.3V

1uF_6.3V

402

6.3V

Y5V

5VCC applied externally or generated internally from the IC, must be in regulation before IC start soft-start sequence.

For 5V Gate Drive application

External filtered +5V_EXT is applied to this pin

+VDDC

C645

Y5V

10uf

6.3V

1206 6.3V

1K

R654

R654 150R

150R

402

6.3V

C654

C654 470nF

470nF

FB

C607

C607 220pF_50V

220pF_50V

12

R_RT

R655

402

51.1K

11

R662

R662 100K

10

9

8

7

C648

C648 10uf

10uf

1206

100K

C638

C638 100nF

100nF

402 10V X5R

C613

X7R402 50V

1nF

R616R616

C603

R606R606

X7R402 50V

1nF

For 8V or 12V Gate Drive application

+5VCC is generated internally and this is an output with 20mA minimum current capability

+5V_OUT

R6300RR630 0R

+VDDC

R696

Y5V

300R

805

CSP2

CSN2

CSN1

CSP1

TP604

TP604 35mil

35mil

Internal Reference is used when REFIN is pull-up to > 4.5V

Share Pad with R639

VDDC1_FB

R6580RR658 0R

+VDDC

12

NS600

NS600 NS_VIA

NS_VIA

R3

R1

R653

RFB1

2.67K

402

R651

R651 10K

10K

402

C3

C653

2.2nF

402

X7R 50V

COMP_FB

RFB2

R650

R650 20K

20K

402

R663

R663 100K

100K

Rdroop

Droop Option

Iout

Iout (13)

Rdroop

2

FB_S

Type III compensation

COMP_GND

R6570RR657 0R

R6560RR656 0R

R2

R652

3.65K

402

C2 C1

C652

C651

10nF

220pF_50V

402

X7R

402

10V

SMPS03 Specifications

Vin (power stage)

Vout 1.2V

Vout ripple (DC) TBD

Iout

Step load TBD

Protections

2

Nominal Value Adjustable range / Notes

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3 - VDDC SMPS 02

Size Document Number Rev

Custom

Date: Sheet

1

VDDC1_FB (13)

Tolerance

;

12V +/-8% PCIe ATX12V ver. 2.2 +/-5%

;

+2.5%/-2.5%

;

TBD 55A (target 60A) max

TBDVout ripple (AC)

TBDSwitching Freq. 50kHz ~ 1MHz

105-B148xx-00D

0.8V ~ 1.5V

11 21Wednesday, May 09, 2007

1

of

3

www.vinafix.vn

8

7

6

5

4

3

2

+VDDC_Source

1

Thermal

Pad

+MVDDC_S

9

6 7 8

RC snubber values shown are for reference only, tuning is required

MVDDC_FB

C715

C715 10UF

10UF

on PCB

CAP CER 10UF 20% 16V X5R (1206)1.8MM H MAX

NL701 PCMC063T-2R2MNNL701 PCMC063T-2R2MN

1 2

ML701 HAH1030-R47-RML701 HAH1030-R47-R

1 2

L701 2.2uH_13AL701 2.2uH_13A

1 2

R719

R719 33MOHM

33MOHM

1210 1%

C708

C708 10nF_25V

10nF_25V

402 X7R 25V

Place Rs and Cs across QL

C716

C716 10UF

10UF

12061206

Rs

Cs

C717

4.7uF_10V

805

Use16V 0805 MLCCMirrored

Mirrored on PCB

Overlap

C713

3.9nF

402 10%

R1

RFB1

R713

R711

3.65K

4.99K

402

1%

5%

R4

Place R1 and R4 close to

RFB2

PWM and

R710

routed with

3.24K

separate

402

20mil trace to

1%

the ASIC

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

C719

4.7uF_10V

805

16V X7R

R7240RR724 0R

C718

C718 150nF_16V

150nF_16V

603

Q701

QH

+PW_MVDDC_HGD

D D

C703

0.22uF

MVDD_EN (14)

R708 20KR708 20K

+PW_MVDDC_M

402

+PW_MVDDC_LGD

+PW_MVDDC_LGDR

R7220RR722

603

0R

+MVDDC_B

U703

1

BOOT

2

UGATE

3

+PW_MVDDC_LGD

R715

42.2K

C C

List of supported foodprint The following ICs are not necessarily evaluated by

ATI, please refer to BOM for evaluation status

ANPEC APW7120/APW7065 (12V) CAT CAT7583 (12V) INTERSIL ISL6545 NEXSEM NX2114/2307 RICHTEK RT9214/RT8101 OnSemi ON1582 uPI UP6101 (No Ext_Vref in) uPI UP6103 (with Ext_Vref in, can use voltage console UP6261 to change Vout)

GND LGATE4VCC

APW7065

PHASE

COMP

FB

8 7 6 5

+PW_MVDDC_M MVDDC_COMP+PW_MVDDC_HGD

MVDDC_FB

+MVDD_VCC

R721 0RR721 0R

+PW_MVDDC_HGDR

402

QL

4 5 3 2 1

Q702

Thermal

Pad

BSC119N03SG

4 5 3 2 1

BSC119N03SG

9

6 7 8

***

C725

C725 470uF_10V

470uF_10V

***

Over Lap

L702

IND_0.47uH_7A

Overlap

TH 10mm Dia SM 10mm Dia

Overlap

***

MC725

MC725 470uF_6.3V

470uF_6.3V

***

ALT

POLY

ML702

0.47uH

Find 100nH SM Alt. IND

C731

C731 270uF_16V

270uF_16V

KC725

KC725 330uF_2.5V

330uF_2.5V

TAN LP 25mOHM

C732

C732 180uF_16V

180uF_16V

*** ***

C723

C723 100uF_6.3V

100uF_6.3V

1210 1210

*** ***

Over Lap

C730

100uF_16V

MC723

MC723 330uF_2.5V

330uF_2.5V

TAN LP 25mOHM

+MVDD

C724

C724 100uF_6.3V

100uF_6.3V

SMPS02- Regulator for MVDD

Vout = 1.8V ~ 2.85V

+PW_MVDDC_LGDR

MQ702

Thermal

Pad

FDS7096N3

9

6 7 8

4 5 3 2 1

4

MULTI FOOTPRINT For SO-8

3

Part RFB2RFB1

0.8V Ref

SMPS02 Specifications

Vin 12V(power stage) +/-8% PCIe ATX12V ver. 2.2 +/-5%

Vout 2V

Vout ripple (DC) 50mVpp

Iout 6Aavg, 8Adc_max

Step load 3Amax

Protections

Vout

2.03V (1.98V~2.08V)

+/-10% or 200mVpp @ 3A step loadVout ripple (AC)

Title

Title Size Document Number Rev

Size Document Number Rev

Custom

Date: Sheet

2

4.99K p/n 3160499100G

Nominal Value Adjustable range / Notes

RV630 GDDR3 - MVDD SMPS 01

Tolerance

;

+2%/-2%

;

~300kHzSwitching Freq. TBD

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

105-B148xx-00D

3.24K p/n 3160324100G

1.8V ~ 2.85V

12 21Wednesday, May 09, 2007

1

of

3

+5V

R7060RR706 0R

402

+PW_MVDDC_M

+PW_MVDDC_HGDR

MQ701

Thermal

Pad

4 5 3 2 1

FDS7096N3

+PW_MVDDC_M

5

+MVDDC_S

9

6 7 8

Layout guideline for Nexsem NX2114/2307

1-Position the controller (U703) such that LGate(pin4) is the closet to gate of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as short and as wide as possible to reduce the trace inductance. 2-Place the bypass capacitors for Vcc as well as Boost caps as close to the controller as possible. They are as follows; Vcc bypass cap is C703, and Boost cap is C705. 3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place the rest of the compensation network close to the pins 7 and 6. These are R710, R711, R713, C713 and R712, C711 and C712.

B B

COMPENSATION CIRCUIT

402

MVDDC_COMP

C712

C711

A A

C711 15nF

15nF

402 X7R

R712

2.94K

402 1%

10V 10%

8

390pF

603 NPO

R714 0RR714 0R

R7090RR709 0R

C714

C714 100nF

100nF

402

10V

50V

X5R

10%

5%

MVDDC_FB

FILTERED SMPS VCC BOOT CIRCUIT

+12V_BUS

+MVDD_VCC

7

R707

2.2R

C707

C707 100nF

100nF

+5V

MR707

2.2R

603 X7R 5%

6

D701

1

BAT54A

3

C705

C705 100nF

100nF

603 X7R 5%

2

16V

+12V_BUS

+MVDDC_B

MR7060RMR706 0R

402

C706

C706 150nF_16V

150nF_16V

www.vinafix.vn

5

4

3

2

1

R1246 0RR1246 0R

Q1242

Q1242 BSH111

BSH111

LOW

HIGH

R1245

R1245 10K

10K

DNI

R1247 0RR1247 0R

Share Pad

D D

PWRCNTL_0(7)

Buffered VDDC Output Current Monitoring

+12V_BUS

Place caps very close to power pin

C692

C692 100nF

100nF

603

U611

R6400RR640

Iout(11)

0R

C657

C657 1nF

1nF

X7R

402

50V

C C

132For Testing purposes only

+3.3V_BUS

U1250A

C1250

C1250 100nF_6.3V

100nF_6.3V

B B

74LCX74

2

3

4

14

5

S

D

Q

5V

6

CP

Q

GND7C

1

X7R

1

+

4

3

-

LM321MF_NOPB

2 5

R6911KR691 1K

1%

12V Supply Voltage single Op-Amp (U611) :

1. National LM321, SOT23-5, ATI PN - TBD

2. TI alternate? ATI PN - TBD

1

C691

C691 100nF

100nF

603 X7R

C693

C693 10nF

10nF

1%

Q1251

Q1251 MMBT3904

MMBT3904

2 3

TP603

TP603 TP_32mil_SM_top

TP_32mil_SM_top

J601

2 1

header_1x2_2mm_smt

R692

30.1K

VDDC_SHDN (11)

Not intended for production LED off shows the fault

SMPS03- Regulator for VDDC

Vout = .9V ~ 1.2V

0.6V Ref

.9V

1.0V

1.1V

1.2V

VDDC

+3.3V

R1240

R1240 10K

10K

R1243

R1243 100K

100K

DNI

RS1

N/A

59.0K 1%

ATI # 3160590200G

30.9K 1%

ATI # 3160309200G

20.0K 1%

ATI # 3160200200G

1

R1244

30.9K

32

PWRCNTL_0

VDDC1_FB (11)

VDDC2_FB (10)

+3.3V_BUS

R1254

R1254 10K

10K

Q1252

Q1252 MMBT3904

MMBT3904

2 3

R1250 10KR1250 10K

+3.3V

1

Q1250

Q1250 BSH111

BSH111

5

U1250B

U1250B 74LCX74

74LCX74

12

11

+3.3V_BUS

32

C1253

C1253 1nF

1nF

R1252

R1252 10K

10K

D

CP

+3.3V

R1251

10K

1

CTFb(7)

R1255

R1255 100K

A A

100K

C1251

C1251 1uF_6.3V

1uF_6.3V

10

9

S

Q

8

Q

C

13

+3.3V_BUS

R1253

R1256

10K

5.1K

1

Q1253

Q1253 MMBT3904

MMBT3904

2 3

R1259

5.1K

5.1K R1257

R1257 100K

100K

R1260

5.1K

4

TR1257

1

5.1K

POWER_SHDN (14)

+3.3V_BUS

2 3 21

TR1256

TR1256 499R

499R

TQ1250

TQ1250 MMBT3904

MMBT3904

TD1250TD1250

www.vinafix.vn

3

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3 - Power Management

Size Document Number Rev

C

Date: Sheet

2

Date: Sheet

105-B148xx-00D

1

3

of

13 21Wednesday, May 09, 2007

8

+VDDC

+12V_BUS

R843

5.1K

5%

R8411KR841 1K

Q840

1

MMBT3904

D D

C841

C841 1uF_6.3V

1uF_6.3V

R842

2.0K

DNI

LDO1_POK

+3.3V

2 3

POWER_SHDN(13)

R8991KR899 1K

R844 5.1KR844 5.1K

DNI

R846 5.1KR846 5.1K

5%

1

OSC_EN (3)

+5V

2 3

Q842

Q842 MMBT3904

MMBT3904

2 3

7

5.1K

5.1K R845

R845

Q841

Q841 MMBT3904

MMBT3904

LDO3_EN

LDO1_EN

MVDD_EN (12)

6

Power up Sequencing

+1.8V

5

R847 10KR847 10K

C844

C844 100nF_6.3V

100nF_6.3V

4

3

2

1

Regulators for +5V, +5V_VESA and +5V_VESA2

+3.3V_BUS

DNI

R8900RR890 0R

+12V_BUS

R848

R849

100K

10K

Q844

1

MMBT3904

Q843

1

MMBT3904

2 3

C843

C843 100NF

100NF

402 X5R 16V

C842

C842 10uF_X6S

10uF_X6S

3 2

1

Q845

SI2304DS

+3.3V

R840

R840 100K

100K

LVT_EN (3)

+12V_BUS

R812

1206

1/4W

5%

C810

C810 100nF

100nF

0603 16V

R812 47R

47R

MR812

MR812 27R

27R

0805

1/8W

5%

1206

1/4W

R811

R811 47R

47R

Vout(V) = Vref (1+R2/R1)

MR811

MR811 27R

27R

0805

1/8W

MU810

MU810 MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

U810

1

VIN

5

NC

8

NC#8 ADJ4VOUT

LM317LCDR

GND

1

VOUT#2 VOUT#3 VOUT#6

+5V_VESA

3

2 3

R813

6

499R

7

0402

R1

C811

1uF_6.3V

R814

1.5K

0402

R2

LDO #1: PCB: 50 to 70mm sq. copper area for cooling

C C

+3.3V_BUS

LDO1_VIN

R8781RR878 1R

1206 Use 0.5R

LDO1_EN

C876

10uF_X6S

LDO #3: Vout = +1.1V +/- 2%

Vin = +1.45V to 2.1VMAX Iout = 1.1A (TBV) RMS MAX

TP871TP871

TP870TP870

+5V

LDO1_POK

C878

C878 1uF_6.3V

1uF_6.3V

U871

1

POK

2

EN

3

VIN CNTL4REFIN

uP7706U8

GND#8

VOUT

GND#9

8 7

FB

6

R876 0RR876 0R

5

DNI

9

Iout = 0.8A (TBV) RMS MAXVout = +1.8V +/- 2%Vin = 2.1V to 3.6V MAX

+1.8V_LDO1

R875

12.7K_0.1%

LDO1_FB

R874

R874 10K_0.1%

10K_0.1%

0402

0.1%

VOUT = Vref x (1 + R5/R4)

R5

R4

C875

C875 33pF_50V

33pF_50V

C3

+1.8V_LDO1

C873

C873 22uF_16V

22uF_16V

DNIDNI

C872

C872 10uF_X6S

10uF_X6S

+MVDD

C871

C871 10uF_X6S

10uF_X6S

Overlap foorprints

B869

220R_2A

MR8690RMR869 0R

R8690RR869 0R

THIS RESISTOR IS FOR

C874

C874 100nF_6.3V

100nF_6.3V

CURRENT MEASUREMENT

+1.8V

PCB: 50 to 70mm sq. copper area for cooling

B B

TP850TP850

+MVDD

1206 Use 0R

R8581RR858 1R

LDO3_VIN

LDO3_EN

10uF_X6S

C856

TP851TP851

LDO3_POK

C858

C858 1uF_6.3V

1uF_6.3V

U851

1

POK

2

EN

3

VIN CNTL4REFIN

uP7706U8

GND#8

VOUT

GND#9

8 7

FB

6

R856 0RR856 0R

5 9

+1.1V+5V +1.1V

LDO3_FB

DNI

VOUT = Vref x (1 + R5/R4)

R855

3.92K_0.1%

R5

R854

R854 10K_0.1%

10K_0.1%

0.1%

R4

C855

C855 33pF_50V

33pF_50V

C3

C853

C853 22uF_16V

22uF_16V

DNIDNI

C852

C852 10uF_X6S

10uF_X6S

C851

C851 10uF_X6S

10uF_X6S

C854

C854 100nF_6.3V

100nF_6.3V

Shared Power Rails

+VDD1DI +VDD2DI +DPLL_PVDD +TPVDD +TXVDDR +T2PVDD

B883

B883 BLM15BD121SN1

BLM15BD121SN1

B884

B884 BLM15BD121SN1

BLM15BD121SN1

7

B885

B885 BLM15BD121SN1

BLM15BD121SN1

B886

B886 BLM15BD121SN1

BLM15BD121SN1

B887

B887 BLM15BD121SN1

BLM15BD121SN1

6

B888

B888 BLM15BD121SN1

BLM15BD121SN1

B889

B889 BLM15BD121SN1

BLM15BD121SN1

5

4

3

B882

B882 BLM15BD121SN1

BLM15BD121SN1

+A2VDDQ

+AVDD

+1.8V

A A

8

+12V_BUS

R822

MR822

R821

27R

47R

1206

1/4W

5%

C820

C820 100nF

100nF

0603 16V

47R

0805

1/8W

5%

47R

1206 0805

Vout(V) = Vref (1+R2/R1)

R831

MR832

MR832 27R

27R

0805

1/8W

5%

R831 47R

47R

1206

1/4W

5%

1206

1/4W

5%

C830

C830 100nF

100nF

0603 16V

R832

R832 47R

47R

Vout(V) = Vref (1+R2/R1)

+5V_VESA

0R

DNI

R8150RR815

0R

R8350RR835

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3 - Linear Regulators

Size Document Number Rev

C

Date: Sheet

2

MR821

MR821 27R

27R

MR831

MR831 27R

27R

0805

1/8W

5%

+5V_VESA2

+5V

MU820

MU820 MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

U820

1

VIN

5

NC

8

NC#8 ADJ4VOUT

LM317LCDR

MU830

MU830 MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

U830

1

VIN

5

NC

8

NC#8 ADJ4VOUT

LM317LCDR

105-B148xx-00D

GND

1

VOUT#2 VOUT#3 VOUT#6

GND

1

VOUT#2 VOUT#3 VOUT#6

+5V_VESA2

3

2 3

R823

6

499R

7

0402

R1

C821

1uF_6.3V

R824

1.5K

0402

R2

1

R833

R833 499R

499R

0402

R1

R834

1.5K

0402

R2

1uF_6.3V

14 21Wednesday, May 09, 2007

C831

+5V

3

of

3

2 3 6 7

www.vinafix.vn

8

7

6

5

4

3

2

1

A_R_DAC1_M

L1001

A_DAC1_R(3)

A_DAC1_RB(3)

A_DAC1_G(3)

D D

C C

B B

A_DAC1_GB(3)

A_DAC1_B(3)

A_DAC1_BB(3)

CRT1DDCDATA(3)

CRT1DDCCLK(3)

HSYNC_DAC1(3,7)

VSYNC_DAC1(3,7)

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

R1027 37.4RR1027 37.4R

R1028 37.4RR1028 37.4R

R1029 37.4RR1029 37.4R

+3.3V

+3.3V +5V

+5V

C1999

14

100nF_6.3V

2 3

1

7

4

5 6

R1004

R1004 10K

10K

R1007

R1007 10K

10K

U1999A

74VHC125

74VHC125 U1999B

U1999B

74VHC125

C1004

R1001

8.0pF

75R

R1002

C1005

8.0pF

75R

C1006

R1003

8.0pF

75R

Pseudo differential RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane.

+5V

1

32

BSH111

BSH111 Q1001

Q1001

1

32

BSH111

BSH111 Q1002

Q1002

HSYNC_DAC1_B

VSYNC_DAC1_B

L1001 47nH

47nH

C1001

L1002

L1002 47nH

47nH

L1003

L1003 47nH

47nH

C1001 12pF_50V

12pF_50V

A_G_DAC1_M

C1002

C1002 12pF_50V

12pF_50V

A_B_DAC1_M

C1003

C1003 12pF_50V

12pF_50V

R1006 33RR1006 33R

R1009 33RR1009 33R

R1010

R1011

10R

R1024 0RR1024 0R

R1025 0RR1025 0R

R1026 0RR1026 0R

R1005

2.2K

DDCDATA_DAC1_5V DDCDATA_DAC1_R

R1008

2.2K

DDCCLK_DAC1_5V

L1004

L1004 36NH

36NH

L1005

L1005 36NH

36NH

L1006

L1006 36NH

36NH

DDCCLK_DAC1_R

HSYNC_DAC1_R

VSYNC_DAC1_R

A_R_DAC1_F A_G_DAC1_F A_B_DAC1_F

DDCDATA_DAC1_R DDCCLK_DAC1_R HSYNC_DAC1_R

VSYNC_DAC1_R

HPD2(7)

For ESD ProtectionSee BOM for qualified filters

Q1021

MMBT3904

+3.3V

2 3

R1023

R1023 10K

10K

1

+3.3V

R1022 10KR1022 10K

D1001

4 5 6

CM1213-04

CH3 Vp CH4

2

Vn

1

CH1

3

CH2

T2X2M(3) T2X2P(3)

T2X4M(3) T2X4P(3)

T2X1M(3) T2X1P(3)

T2X3M(3) T2X3P(3)

T2X0M(3) T2X0P(3)

T2X5M(3) T2X5P(3)

T2XCP(3) T2XCM(3)

+5V_VESA

4 5 6

DDCCLK_DAC1_R DDCDATA_DAC1_R VSYNC_DAC1_R

HPD_DVI2

A_R_DAC1_F A_G_DAC1_F A_B_DAC1_F HSYNC_DAC1_R

D1002

CH3 Vp CH4

CM1213-04

3

CH2

2

Vn

1

CH1

+5V_VESA

C1010

C1010 68pF

68pF

603

Standard VGA

DB15 pin

11 12 4 15

9

Hardware Support

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA

DDC1 Host

Monitor ID bit 0

Monitor ID bit 1

Data from display

Monitor ID bit 2

Monitor ID bit 3

Open +5V

N/C

50mA min

Mechanical Key

1A max

No Yes Yes No Yes

J1001

25

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C1 C2 C3 C4 C5 C6

26 27 28 29 30

DVI_CONNECTOR

1 2

3 11 12

4 15

9 13 14

5

6

7

8 10 16 17

CASE TMDS Data2-

TMDS Data2+ TMDS Data2/4 Shield TMDS Data4TMDS Data4+ DDC Clock DDC Data Analog VSYNC TMDS Data1TMDS Data1+ TMDS Data1/3 Shield TMDS Data3TMDS Data3+ +5V Power GND (for +5V) Hot Plug Detect TMDS Data0TMDS Data0+ TMDS Data0/5 Shield TMDS Data5TMDS Data5+ TMDS Clock Shield TMDS Clock+ TMDS Clock-

Analog Red Analog Green Analog Blue Analog HYNC Analog GND Analog GND#C6

CASE#26 CASE#27 CASE#28 CASE#29 CASE#30

MJ1001

R G B MS0 MS1 MS2 MS3 NC HS VS VSS VSS#6 VSS#7 VSS#8 VSS#10 CASE CASE#17

G3179C219-005

DDC2B or DDC2B+ Host Monitor ID bit 0 SDA Monitor ID bit 2 SCL +5V 50mA min 1A max

DDC2_MONID0 DDC2_MONID1(SDA) DDC2_MONID2 DDC2_MONID3(SCL)

DDC2AB Host Monitor ID bit 0

SDA Monitor ID bit 2 SCL +5V 300mA min 1A max

DDC1/2 Display Optional

SDA Optional SCL

Optional

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3- DAC1&TMDS2

Size Document Number Rev

Custom

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B148xx-00D

3

of

15 21Wednesday, May 09, 2007

1

www.vinafix.vn

8

7

6

5

4

3

2

1

See BOM for qualified filters

A_R_DAC2_M

L2001

A_DAC2_R(3)

R2027

A_DAC2_RB(3)

A_DAC2_G(3)

D D

A_DAC2_GB(3)

A_DAC2_B(3)

A_DAC2_BB(3)

R2027

37.4R

R2028

37.4R

R2029

37.4R

C2004

R2001

8.0pF

75R

402

C2005

R2002

8.0pF

75R

402

C2006

R2003

8.0pF

75R

402

Pseudo differential RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane.

L2001 47nH

47nH

R20240RR2024 0R

L2002

L2002 47nH

47nH

R20250RR2025 0R

L2003

L2003 47nH

47nH

R20260RR2026 0R

C2001

402

12pF_50V

A_G_DAC2_M

C2002

402

12pF_50V

A_B_DAC2_M

C2003

402402

12pF_50V

L2004

L2004 36NH

36NH

L2005

L2005 36NH

36NH

L2006

L2006 36NH

36NH

A_R_DAC2_F A_G_DAC2_F A_B_DAC2_F

DDCDATA_DAC2_R DDCCLK_DAC2_R

+3.3V

4 5 6

HSYNC_DAC2_R VSYNC_DAC2_R

D2001

CH3 Vp CH4

CM1213-04

3

CH2

2

Vn

1

CH1

+5V_VESA2

4 5 6

For ESD Protection

D2002

CH3 Vp CH4

CM1213-04

3

CH2

2

Vn

1

CH1

C2010

C2010 68pF

68pF

603

+5V_VESA2

MJ2001

1

R

2

G

3

B

11

MS0

12

MS1

4

MS2

15

MS3

9

NC

13

HS

14

VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8

10

VSS#10

16

CASE

17

CASE#17

G3179C219-005

DDC2_MONID0 DDC2_MONID1(SDA) DDC2_MONID2 DDC2_MONID3(SCL)

+3.3V

R2004

R2004 10K

C C

B B

A A

8

CRT2DDCDATA(3)

CRT2DDCCLK(3)

HSYNC_DAC2(3,7)

VSYNC_DAC2(3,7)

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

7

10K

+3.3V +5V

R2007

R2007 10K

10K

U1999C

9 8

74VHC125

10

U1999D

13

12 11

74VHC125

6

1

32

BSH111

BSH111 Q2001

Q2001

1

32

BSH111

BSH111 Q2002

Q2002

HSYNC_DAC2_B

VSYNC_DAC2_B

+5V

R2005

2.2K

402

DDCDATA_DAC2_5V DDCDATA_DAC2_R

R2008

2.2K

402 402

DDCCLK_DAC2_5V

R2010

R2011

R2006 33RR2006 33R

R2009 33RR2009 33R

402

HSYNC_DAC2_R

10R

402

VSYNC_DAC2_R

10R

HPD1(3)

5

DDCCLK_DAC2_R

MMBT3904

55mA current limited for +5V rail DNI

Place C2012 close to J2001

+3.3V

Q2021

DDCCLK_DAC2_R DDCDATA_DAC2_R

HPD_DVI1

4

DB15 pin

Standard VGA Monitor ID bit 0

11

Monitor ID bit 1

12

Monitor ID bit 2

4

Monitor ID bit 3

15

N/C

9

Mechanical Key Hardware Support

No Yes Yes No Yes

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA2

T1X2M(3) T1X2P(3)

T1X4M(3) T1X4P(3)

T1X1M(3) T1X1P(3)

T1X3M(3)

NJ2001

1

GND#20

2

GND#21

3

GND#22

4

GND#23

5

6

7

8

9

9 10 11 12 13 14 15 16 17 18 19

LONG_TYPE-2_HDMI

3

T1X3P(3)

T1X0M(3) T1X0P(3)

T1X5M(3) T1X5P(3)

T1XCP(3) T1XCM(3)

20 21 22 23

R2022 10KR2022 10K

1

2 3

R2023

R2023 10K

10K

+5V_VESA2

R2012

C2012

C2012 100pF_50V

100pF_50V

R2012

4.7K

10 11 12 13 14 15 16 17 18 19

B2012

B2012 220R

220R

T1X2P(3) T1X2M(3)

T1X1P(3) T1X1M(3)

T1X0P(3) T1X0M(3)

T1XCP(3) T1XCM(3)

R2017 0RR2017 0R R2018 0RR2018 0R

DDCCLK_DAC2_R DDCDATA_DAC2_R VSYNC_DAC2_R

R2015 0RR2015 0R R2016 0RR2016 0R

R2013 0RR2013 0R R2014 0RR2014 0R

R2019 0RR2019 0R R2020 0RR2020 0R

A_R_DAC2_F A_G_DAC2_F A_B_DAC2_F HSYNC_DAC2_R

HPD_DVI1

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3-DAC2/TMDS1

Size Document Number Rev

Custom

Date: Sheet

2

DDC1 Host Monitor ID bit 0

Data from display Monitor ID bit 2 Open +5V 50mA min 1A max

25

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C1 C2 C3 C4 C5 C6

26 27 28 29 30

DDC2B or DDC2B+ Host Monitor ID bit 0 SDA Monitor ID bit 2 SCL +5V 50mA min 1A max

J2001

CASE TMDS Data2-

TMDS Data2+ TMDS Data2/4 Shield TMDS Data4TMDS Data4+ DDC Clock DDC Data Analog VSYNC TMDS Data1TMDS Data1+ TMDS Data1/3 Shield TMDS Data3TMDS Data3+ +5V Power GND (for +5V) Hot Plug Detect TMDS Data0TMDS Data0+ TMDS Data0/5 Shield TMDS Data5TMDS Data5+ TMDS Clock Shield TMDS Clock+ TMDS Clock-

Analog Red Analog Green Analog Blue Analog HYNC Analog GND Analog GND#C6

CASE#26 CASE#27 CASE#28 CASE#29 CASE#30

DVI_CONNECTOR

105-B148xx-00D

DDC2AB Host Monitor ID bit 0

SDA Monitor ID bit 2 SCL +5V 300mA min 1A max

1

16 21Wednesday, May 09, 2007

DDC1/2 Display Optional

SDA Optional SCL

Optional

of

3

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8

D D

7

6

5

4

3

2

1

A_DAC2_Y(3)

R3001

R3001 75R

75R

A_DAC2_C(3)

R3002

R3002 75R

75R

A_DAC2_COMP(3)

R3003

R3003 75R

75R

C C

Place near connector 0R leaves footprint for Ferrite Beads if req'd for EMI

DAC2_C_F DAC2_COMP_F

R3011 0RR3011 0R

R3004 0RR3004 0R R3005 0RR3005 0R R3006 0RR3006 0R

Install for Dell

GENERICA(7)

DNI for Dell

402

STV/HDTV#_DET PIN6 DAC2_Y_DINDAC2_Y_F

DAC2_C_DIN DAC2_COMP_DIN

+3.3V

R3008

R3008 10K

10K

C3007

C3007 82pF

82pF

Install for Dell

R3010 0RR3010 0R

R3009 0RR3009 0R

C3008

C3008 82pF

82pF

C3009

C3009 82pF

82pF

L3001 470nH_250mAL3001 470nH_250mA

C3001

C3001 47pF_50V

47pF_50V

L3002 470nH_250mAL3002 470nH_250mA

C3002

C3002 47pF_50V

47pF_50V

L3003 470nH_250mAL3003 470nH_250mA

C3003

C3003 47pF_50V

47pF_50V

R30070RR3007 0R

DNI for Dell

The 7-pin MiniDIN footprint allows one of the two MiniDINs:

B B

- 7-pin Svideo/Composite MiniDIN P/N 6071001500G

- 4-pin Svideo MiniDIN P/N 6070001000G

DAC2_Y_F

C3004

C3004 47pF_50V

47pF_50V

DAC2_C_F

C3005

C3005 47pF_50V

47pF_50V

DAC2_COMP_F

C3006

C3006 47pF_50V

47pF_50V

Install for Dell only when it's needed for EMI

C3010

C3010 82pF

82pF

TV Out

J3001

6

HDTV_OUT_DET#

3

Y-OUT

4

C-OUT

7

Comp_out

CompIn

5

SYNC

1

GND

2

GND#2

8

Rpin5

CASE

9

CASE#9

10

CASE#10

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3 - TVO

Size Document Number Rev

C

Date: Sheet

8

7

6

5

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3

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2

105-B148xx-00D

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8

7

6

5

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1

LM63 is for BU only, until built-in fan controller is verified.

+3.3V +3.3V

C4003

C4002

C4001

R4032

R4003

2.61K

10K

D D

DDC3CLK(3)

DDC3DATA(3)

TS_FDO(3)

Place R4032, and R4033 on the bottom side. Easily accessiable.

10K

R4001 100RR4001 100R R4002 100RR4002 100R R4015 0RR4015 0R

R4033 100KR4033 100K

DNI

SCL_R SDA_R TINT_R

C4001

1uF_6.3V

10uF_X6S

U4001

8

SMBCLK

7

SMBDAT

6

ALERT GND5PWM

LM63CIMAX

VDD

D+

100pF_50V

D-

R4004

R4004 10K

10K

GPU_DPLUS

1 2 3 4

TS_FDO

C4004

2.2nF_50V

LM63_PWM

GPU_DMINUS

GPU_DPLUS (3)

GPU_DMINUS (3)ThermINT(7)

Warning: TS_FDO is not 5V tolerant. MAX sink current 1.65mA

For fan with 3.3V PWM (bypass) install 0R (TBV)

MR4005 10KMR4005 10K

Share one pad Place them on the bottom

R4005 10KR4005 10K

+12V_BUS

B4001

26R_600mA

PWM

For 2-WIRE FAN ONLY

R4011

R4011 100K

100K

32

MQ4004

23

MMBT3906

MMBT3906 Q4002

Q4002

1

2SB1188

402

C C

For 4-WIRE FAN

PWM

1

+5V

MR40061KMR4006 1K

Share one PAD

Q4001

MMBT3904

2 3

+12V_BUS

R4006

2.61K

1%

R4007

R4007 20K

20K

1%

R4008

2.37K

2.37K C4007

C4007 1uF

1uF

805 16V Y5V

R40160RR4016

0R

1

R40140RR4014

0R

For 4-WIRE FAN

C4010

C4010 10uF

10uF

C4008

0805

1uF

16V

+5V

R4036

R4036 10K

10K

TACH

DNI

R4031 15KR4031 15K

DNI

C4030

C4030 47nF_50V

47nF_50V

R4039

1

Q4030

10K

MMBT3904

2 3

B B

MR40360RMR4036

0R

DNI (bypass for fan with 3.3V PWM)

For 4-WIRE FAN ONLY

H1E

H1A

FANSINK

2345678

A A

1

H1B

FANSINK

9

10111213141516

H1C

FANSINK

17181920212223

H1D

FANSINK

24

25262728293031

H1E

FANSINK

32

33343536373839

Header is 2mm, and it does not follow

2.54mm spacing as 4-pin PWM Fan Specification

H1F

FANSINK

40

41424344454647

4 3 2

J4030

1

1X4 3A 2MM

MJ4030MJ4030

1 2

Overlap MJ4030 and J4030

H1G

FANSINK

48

49505152535455

H1H

FANSINK

58596061626364

57

56

FANSINK FOR RV630 DDR2, p/n 7120033200G

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3- Thermal Management

Size Document Number Rev

C

Date: Sheet

8

7

6

5

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4

3

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105-B148xx-00D

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18 21Wednesday, May 09, 2007

1

DVI/DVI SCREWS with top tab

5

4

MT2

MT2 MT_Hole_0.136_in_6VIA

MT_Hole_0.136_in_6VIA

3

2

1

D D

BKT1

BRACKET

80200386B0G

C C

DNI

SK1

RV410SOCKET

PCB1

PCB

109-B14831-00C

B B

A A

5

4

www.vinafix.vn

3

2

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3- Mechanical

Size Document Number Rev

C

Date: Sheet

105-B148xx-00D

1

of

19 21Wednesday, May 09, 2007

3

5

Title

RH PCIE RV630 2x256MB GDDR3 DUAL DL-DVI-I VIVO FH Saturday, May 05, 2007

REVISION HISTORY

D D

Sch

Rev

C C

PCB

Rev

0

00A

1 00B

2 00C

3 00D

Date

07/02/06

04/09/07

04/13/07 (Layout) Enlarged VDDC plane

05/04/07

Initial design for RV630 GDDR3

Added pull down MR5 on JTAG_MODE (pg 7) Connected C239, C241, C289, C291, C339, C341, C389, C391 to GND instead of MVDD (MTAG recommendation) (pg 8/9) Added C244, C245, C292, C293, C344, C345, C394, C395, C444, C445, C492, C493, C544, C545, C592, C593 for noise reduction (pg 8/9) Removed duplicated footprints R723 and B703 on MVDD power supply (pg 12) I2C block removed (pg 13) / Off page connection for MVDDC_FB removed (pg 12) Label changed from LDO2_POK to LDO1_POK (pg 14) HDMI connector (dual footprint for DVI and HDMI) NJ2001 added (pg 16) R2013~R2020 added for TMDS lines (pg 16) C4010 added for ripple reduction when using 2-wire fan (pg 18) Component PN changed to match updated BOM (no footprint changes) (Layout) Q842 moved close to MVDD SMPS block (Layout) Move MVDD caps close to DRAM

(Layout) Update. No Schematic changes.

4

NOTE:

3

Schematic No.

105-B148xx-00D

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU. For Stuffing options (component values, DNI , ? please consult the product specific BOM.　

For Stuffing options (component values, DNI , ? please consult the product specific BOM.　

For Stuffing options (component values, DNI , ? please consult the product specific BOM.　 Please contact ATI representative to obtain latest BOM closest to the application desired.

Please contact ATI representative to obtain latest BOM closest to the application desired.

REVISION DESCRIPTION

2

Date:

1

Rev

3

B B

A A

5

4

www.vinafix.vn

3

2

1

5

4

3

2

1

MEMORY CHANNEL A & B - RANK0

GDDR3 4pcs 16Mx32 (256MB)

D D

External 12V Header

Debug

POWER REGULATORS

From +12V

+VDDC (MPVDD, VDDCI), +MVDD

From +12V LINEAR:

C C

B B

+5V, +5V_VESA, +5V_VESA2,

From +12V DIRECT:

FAN

From +MVDD Linear (1.1V):

PCIE_VDDC, DPLL_VDDC

From +3.3V: Direct or Linear (1.8V)

VDD_CT, DPLL_PVDD, TPVDD, T2PVDD, TXVDDR, T2XVDDR(LTVDD33), T2XVDDC(LTVDD18), AVDD, A2VDD, A2VDDQ, VDD1DI, VDD2DI, PCIE_VDDR, PCIE_PVDD, VDDR3, VDDR4, VDDR5

+PCIE_SOURCE

+3.3V

3.3V_BUS delayed circuit

SMPS Enable Circuit

+12V_BUS

+3.3V_BUS +12V_BUS

CrossFire Interlink Header

FAN

POWER DELIVERY

Connector

Straps

BIOS

Speed control & temperature sense

Built-in PWM

Temperature Critical

PCI-Express Bus

INTERRUPT Temp. Sensing

Dynamic VDDC

RANK0 RANK1

GPIO16 (TBV)12V_EXT_DETb

CrossFire

DVOCLK DVPCNTL_[0..2] DVPDATA[23:0] DVP_MVP_CNTL[1:0] GPIO[6:3] GENERICB, DVALID

TMDS1

DL TMDS1

HPD1

DAC2

H/V2Sync

GPIO

ROM

Thermal

DDC3

GPIO17 D+/D-

TS_FDO

GPIO20

XTALIN/OUT

GENERICA

TMDS2

DL TMDS2

HPD2 (GPIO14)

DAC1

RV630

H/VSync

CTFb

PCI-Express

CRT2

DDC2

TVO

STV/HDTV#_OUT_DET

CRT1

DDC1

MEMORY CHANNEL A & B - RANK1

GDDR3 4pcs 16Mx32 (256MB)

Shunt Resistors

XTAL

Oscillator

Shunt Resistors

HPD1

&DVI-I

RBG Filters

Slim-VGA Connector

TVO Filters

TVO Connector

HPD2

DVI-I

RBG Filters

& Slim-VGA Connector

ORLOFF: RH PCIE RV630 2x256MB GDDR3 DUAL DL-DVI-I VO FH

REV C

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RV630 GDDR3 - BLOCK DIAGRAM

Size Document Number Rev

C

Date: Sheet

5

4

www.vinafix.vn

3

2

Date: Sheet

105-B148xx-00D

1

3

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MSI MS-V099 Schematic 10

Specifications and Main Features

Frequently Asked Questions

User Manual