MSI MS-V098 Schematic 1.1

8

7

6

5

4

3

2

1

+12V_BUS

C1

CAP CER 10UF 20% 16V X5R

10UFC110UF

(1206)1.8MM H MAX

+12V_BUS

C3

D D

C C

B B

C2

150nF_16V

150nF_16VC2150nF_16V

LF CAP CER 150NF 10% 16V X7R (0603)

+3.3V_BUS

CAP CER 10UF 10% 6.3V X6S (0805)1.4MM MAX THICK

C4 10uF_X6SC410uF_X6S

+3.3V_BUS

C6

C5

1uF_6.3VC61uF_6.3V

100nF_6.3VC5100nF_6.3V

Place these caps as close to the PCIE connector as possible

TEST_EN_R(3)

HSYNC1_TRST(3)

C0 10nFC010nF

DNI

PETn0_GFXRn0(2)

PETp1_GFXRp1(2) PETn1_GFXRn1(2)

PETp2_GFXRp2(2) PETn2_GFXRn2(2)

PETp3_GFXRp3(2) PETn3_GFXRn3(2)

PETp4_GFXRp4(2) PETn4_GFXRn4(2)

PETp5_GFXRp5(2) PETn5_GFXRn5(2)

PETp6_GFXRp6(2) PETn6_GFXRn6(2)

PETp7_GFXRp7(2) PETn7_GFXRn7(2)

PETp8_GFXRp8(2) PETn8_GFXRn8(2)

PETp9_GFXRp9(2) PETn9_GFXRn9(2)

PETp10_GFXRp10(2) PETn10_GFXRn10(2)

PETp11_GFXRp11(2) PETn11_GFXRn11(2)

PETp12_GFXRp12(2) PETn12_GFXRn12(2)

PETp13_GFXRp13(2) PETn13_GFXRn13(2)

PETp14_GFXRp14(2) PETn14_GFXRn14(2)

PETp15_GFXRp15(2) PETn15_GFXRn15(2)

JTAG_TRST#

PRESENCE

PCI-EXPRESS EDGE CONNECTOR

+3.3V_BUS

+12V_BUS

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

+12V#B1 +12V#B2 +12V#B3 GND#B4 SMCLK SMDAT GND#B7 +3.3V#B8 JTAG1

3.3Vaux WAKE#

RSVD#B12 GND#B13 PETp0 PETn0 GND#B16 PRSNT2#B17 GND#B18 PETp1 PETn1 GND#B21 GND#B22 PETp2 PETn2 GND#B25 GND#B26 PETp3 PETn3 GND#B29 RSVD#B30 PRSNT2#B31 GND#B32 PETp4 PETn4 GND#B35 GND#B36 PETp5 PETn5 GND#B39 GND#B40 PETp6 PETn6 GND#B43 GND#B44 PETp7 PETn7 GND#B47 PRSNT2#B48 GND#B49 PETp8 PETn8 GND#B52 GND#B53 PETp9 PETn9 GND#B56 GND#B57 PETp10 PETn10 GND#B60 GND#B61 PETp11 PETn11 GND#B64 GND#B65 PETp12 PETn12 GND#B68 GND#B69 PETp13 PETn13 GND#B72 GND#B73 PETp14 PETn14 GND#B76 GND#B77 PETp15 PETn15 GND#B80 PRSNT2#B81 RSVD#B82

x16 PCIe

Mechanical Key

PRSNT1#A1

+12V#A2 +12V#A3 GND#A4

JTAG2 JTAG3 JTAG4 JTAG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12 REFCLK+ REFCLKGND#A15

PERp0 PERn0

GND#A18

RSVD#A19

GND#A20

PERp1

PERn1 GND#A23 GND#A24

PERp2

PERn2 GND#A27 GND#A28

PERp3

PERn3 GND#A31

RSVD#A32 RSVD#A33

GND#A34

PERp4

PERn4 GND#A37 GND#A38

PERp5

PERn5 GND#A41 GND#A42

PERp6

PERn6 GND#A45 GND#A46

PERp7

PERn7 GND#A49

RSVD#A50

GND#A51

PERp8

PERn8 GND#A54 GND#A55

PERp9

PERn9 GND#A58 GND#A59

PERp10

PERn10 GND#A62 GND#A63

PERp11

PERn11 GND#A66 GND#A67

PERp12

PERn12 GND#A70 GND#A71

PERp13

PERn13 GND#A74 GND#A75

PERp14

PERn14 GND#A78 GND#A79

PERp15

PERn15 GND#A82

MPCIE1

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

PERp0 PERn0

PERp1 PERn1

PERp2 PERn2

PERp3 PERn3

PERp4 PERn4

PERp5 PERn5

PERp6 PERn6

PERp7 PERn7

PERp8 PERn8

PERp9 PERn9

PERp10 PERn10

PERp11 PERn11

PERp12 PERn12

PERp13 PERn13

PERp14 PERn14

PERp15 PERn15

+3.3V_BUS+12V_BUS

PRESENCE

JTCK JTDI JTDOTEST_EN_R JTMS

R2 0RR2 0R

C7 100nF_6.3VC7100nF_6.3V

C9 100nF_6.3VC9100nF_6.3V

C11

C11 100nF_6.3V

100nF_6.3V

C13

C13 100nF_6.3V

100nF_6.3V

C15

C15 100nF_6.3V

100nF_6.3V

C17

C17 100nF_6.3V

100nF_6.3V

C19

C19 100nF_6.3V

100nF_6.3V

C21

C21 100nF_6.3V

100nF_6.3V

C23

C23 100nF_6.3V

100nF_6.3V

C25

C25 100nF_6.3V

100nF_6.3V

C27

C27 100nF_6.3V

100nF_6.3V

C29

C29 100nF_6.3V

100nF_6.3V

C31

C31 100nF_6.3V

100nF_6.3V

C33

C33 100nF_6.3V

100nF_6.3V

C35

C35 100nF_6.3V

100nF_6.3V

C37

C37 100nF_6.3V

100nF_6.3V

PERST#

C8 100nF_6.3VC8100nF_6.3V

C10

C10 100nF_6.3V

100nF_6.3V

C12

C12 100nF_6.3V

100nF_6.3V

C14

C14 100nF_6.3V

100nF_6.3V

C16

C16 100nF_6.3V

100nF_6.3V

C18

C18 100nF_6.3V

100nF_6.3V

C20

C20 100nF_6.3V

100nF_6.3V

C22

C22 100nF_6.3V

100nF_6.3V

C24

C24 100nF_6.3V

100nF_6.3V

C26

C26 100nF_6.3V

100nF_6.3V

C28

C28 100nF_6.3V

100nF_6.3V

C30

C30 100nF_6.3V

100nF_6.3V

C32

C32 100nF_6.3V

100nF_6.3V

C34

C34 100nF_6.3V

100nF_6.3V

C36

C36 100nF_6.3V

100nF_6.3V

C38

C38 100nF_6.3V

100nF_6.3V

No JTAG

JTAG

PCIE_REFCLKP (2) PCIE_REFCLKN (2)PETp0_GFXRp0(2)

GFXTp0_PERp0 (2) GFXTn0_PERn0 (2)

GFXTp1_PERp1 (2) GFXTn1_PERn1 (2)

GFXTp2_PERp2 (2) GFXTn2_PERn2 (2)

GFXTp3_PERp3 (2) GFXTn3_PERn3 (2)

GFXTp4_PERp4 (2) GFXTn4_PERn4 (2)

GFXTp5_PERp5 (2) GFXTn5_PERn5 (2)

GFXTp6_PERp6 (2) GFXTn6_PERn6 (2)

GFXTp7_PERp7 (2) GFXTn7_PERn7 (2)

GFXTp8_PERp8 (2) GFXTn8_PERn8 (2)

GFXTp9_PERp9 (2) GFXTn9_PERn9 (2)

GFXTp10_PERp10 (2) GFXTn10_PERn10 (2)

GFXTp11_PERp11 (2) GFXTn11_PERn11 (2)

GFXTp12_PERp12 (2) GFXTn12_PERn12 (2)

GFXTp13_PERp13 (2) GFXTn13_PERn13 (2)

GFXTp14_PERp14 (2) GFXTn14_PERn14 (2)

GFXTp15_PERp15 (2) GFXTn15_PERn15 (2)

VSYNC1_TCK (3)

DDC1DATA_TDI (3) DDC3CLK_TDO (3) DDC1CLK_TMS (3)

1 2

+3.3V

53

R_RST

C39

C39 100nF_6.3V

100nF_6.3V

NC7SZ08P5X_NL

4

U5

Place R3 in U5

PERST#_buf (2,17)

SYMBOL LEGEND

DO NOT

DNI

INSTALL

#

ACTIVE LOW

DIGITAL GROUND

ANALOG

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - PCI-E Edge Connector

Size Document Number Rev

C

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B101XX-00

GROUND

BUO BRING UP

ONLY

of

121Tuesday, April 10, 2007

1

4

www.vinafix.vn

5

D D

4

3

2

1

NOTE: some of the PCIE testpoints will be available trought via on traces.

PETp0_GFXRp0(1) PETn0_GFXRn0(1)

PETp1_GFXRp1(1) PETn1_GFXRn1(1)

PETp2_GFXRp2(1) PETn2_GFXRn2(1)

PETp3_GFXRp3(1) PETn3_GFXRn3(1)

PETp4_GFXRp4(1) PETn4_GFXRn4(1)

PETp5_GFXRp5(1) PETn5_GFXRn5(1)

PETp6_GFXRp6(1)

C C

B B

PCIE_REFCLKP(1) PCIE_REFCLKN(1)

PETn6_GFXRn6(1)

PETp7_GFXRp7(1) PETn7_GFXRn7(1)

PETp8_GFXRp8(1)

PETp9_GFXRp9(1) PETn9_GFXRn9(1)

PETp10_GFXRp10(1) PETn10_GFXRn10(1)

PETp11_GFXRp11(1) PETn11_GFXRn11(1)

PETp12_GFXRp12(1) PETn12_GFXRn12(1)

PETp13_GFXRp13(1) PETn13_GFXRn13(1)

PETp14_GFXRp14(1) PETn14_GFXRn14(1)

PETp15_GFXRp15(1) PETn15_GFXRn15(1)

DNI DNI

402 402

TP11TP11

TP12TP12

TP13TP13

TP14TP14

TP19TP19

TP20TP20

TP21TP21

TP22TP22

TP27TP27

TP28TP28

TP7TP7

TP8TP8

TP9TP9

TP10TP10

ٛٛ

TP16TP16

TP17TP17

TP18TP18

TP23TP23

TP24TP24

TP25TP25

TP26TP26

PERST#_buf(1,17)

AK33

AH35 AH34

AG35 AG34

AF33 AE33

AE35 AE34

AD35 AD34

AC35 AC34

AB33 AA33

AA35 AA34

AM32

AJ33

AJ35 AJ34

Y35 Y34

W35 W34

V33 U33

U35 U34

T35 T34

R35 R34

AJ31 AJ30

U1A

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

PCIE_RX8P PCIE_RX8N

PCIE_RX9P PCIE_RX9N

PCIE_RX10P PCIE_RX10N

PCIE_RX11P PCIE_RX11N

PCIE_RX12P PCIE_RX12N

PCIE_RX13P PCIE_RX13N

PCIE_RX14P PCIE_RX14N

PCIE_RX15P PCIE_RX15N

Clock

PCIE_REFCLKP PCIE_REFCLKN

PERSTB

PART 1 OF 7

P

P C

C I

I

-

E

E X

X P

P R

R E

E S

S S

S

I

I N

N T

T E

E R

R F

F A

A C

C E

E

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

Calibration

PCIE_CALRN PCIE_CALRP

PCIE_CALI

AG31 AG30

AF31 AF30

AF28 AF27

AD31 AD30

AD28 AD27

AB31 AB30

AB28 AB27

AA31 AA30

AA28 AA27

W31 W30

W28 W27

V31 V30

V28 V27

U31 U30

U28 U27

R31 R30

AG26 AJ27

AK29

GFXTp0_PERp0 (1) GFXTn0_PERn0 (1)

GFXTp1_PERp1 (1) GFXTn1_PERn1 (1)

GFXTp2_PERp2 (1) GFXTn2_PERn2 (1)

GFXTp3_PERp3 (1) GFXTn3_PERn3 (1)

GFXTp4_PERp4 (1) GFXTn4_PERn4 (1)

GFXTp5_PERp5 (1) GFXTn5_PERn5 (1)

GFXTp6_PERp6 (1) GFXTn6_PERn6 (1)

GFXTp7_PERp7 (1) GFXTn7_PERn7 (1)

GFXTp8_PERp8 (1) GFXTn8_PERn8 (1)PETn8_GFXRn8(1)

GFXTp9_PERp9 (1) GFXTn9_PERn9 (1)

GFXTp10_PERp10 (1) GFXTn10_PERn10 (1)

GFXTp11_PERp11 (1) GFXTn11_PERn11 (1)

GFXTp12_PERp12 (1) GFXTn12_PERn12 (1)

GFXTp13_PERp13 (1) GFXTn13_PERn13 (1)

GFXTp14_PERp14 (1) GFXTn14_PERn14 (1)

GFXTp15_PERp15 (1) GFXTn15_PERn15 (1)

+PCIE_VDDC

402

R82.0K R82.0K

402

R91.27K R91.27K

402

R102.0K R102.0K

For Tektronix LA only

Place close to ASIC

A A

5

4

RV630XT A14 RH

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - ASIC PCIE_Interface

Size Document Number Rev

C

Date: Sheet

3

2

Date: Sheet

105-B101XX-00

1

4

of

221Tuesday, April 10, 2007

www.vinafix.vn

5

Recommended caps: (see BOM for qualified values/vendors) 10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK 1uF, X6S, 0402, 6.3V 100nF, X7R, 0402 10nF , X7R, 0402

D D

DNI

+1.8V

+12V_BUS

MR108

MR108 10K

10K

LVT_EN(14)

+3.3V

C C

MR1090RMR109 0R

Share one pad

BUO

TP40TP40 TP41TP41

B B

SI2304DS

DNI

BSH111

DNI DNI

+3.3V

402 402

BUO

TEST_EN_R(1)

T2XCM(15) T2XCP(15)

T2X0M(15)

T2X0P(15)

T2X1M(15)

T2X1P(15)

T2X2M(15)

T2X2P(15)

T2X3M(15)

T2X3P(15)

T2X4M(15)

T2X4P(15)

Q100

T2X5M(15)

T2X5P(15)

32

+T2PVDD

1

Q101

I2C DEVICE ADDRESS' ON DDC3

DEVICE LM63 DP

Use 0R

32

0R

ADDRESS x100 1100 TBD

DDC3DATA(11,13,18)

DDC3CLK_TDO(1) DDC1CLK_TMS(1)

0R

B1010RB101

DDC3CLK(11,13,18)

DNI

Share one PAD

+3.3V_BUS

B80

B80 BLM15BD121SN1

BLM15BD121SN1

C81

1uF_6.3V

A A

XTALOUT_S is done for ease of layout

XTALOUT_S

C80

C80 100nF_6.3V

100nF_6.3V

4 2

XTALIN_S

XTALOUT_S

5

Y81

VCC GND

27.000MHz

OUT

E/D

B1000RB100

R106 100RR106 100R

R100 100RR100 100R

R101 100RR101 100R

R102 100RR102 100R

R103 100RR103 100R

R104 100RR104 100R

R105 100RR105 100R

NS100

10uF_X6S

NS_VIA

1 2

GND_T2PVSS

C103

10uF_X6S

+LTVDD33

C106

1uF_6.3V

+3.3V

R40

4.7K

402 402

DNI

MR71KMR7 1K

+1.8V

RTCLK(17)

3 1

R81 182RR81 182R

Place R_RTCLK close to XTAL so the main clock line has shortest stub

C100

C102

1uF_6.3V

C108

1uF_6.3V

C105

100nF_6.3V

DDC1DATA_TDI(1)

CRT1DDCDATA(15)

CRT1DDCCLK(15)

R41

4.7K

DDC3DATA DDC3CLK

TP42TP42

R43 221RR43 221R R44 110RR44 110R

C46 100nF_6.3VC46 100nF_6.3V

DNI

Share one pad

OSC_EN

R_RTCLK

C109

100nF_6.3V

GPU_DMINUS(18) GPU_DPLUS(18)

TS_FDO(18)

XTALOUT

C101

100nF_6.3V

CRT2DDCDATA(16)

PLL_TEST TEST_EN

CRT2DDCCLK(16)

HPD1(16)

SDA(7)

T2XCM T2XCP

T2X0M T2X0P

T2X1M T2X1P

T2X2M T2X2P

T2X3M T2X3P

T2X4M T2X4P

T2X5M T2X5P

SCL(7)

+LTVDD18

XTALIN XTALOUT

4

VREFG

R82

R82 221R

221R

OSC_EN (14,17)

RTXTALIN (17)

RTXTALOUT (17)

4

AP22 AR22

AN22 AN23

AR23 AP23

AR24 AP24

AR25 AP25

AN26 AN27

AR27 AP27

AL22

AK22

AK27

AL27

AJ26

AH26

AJ22 AN21 AN24 AN25 AN28 AP21 AP26 AR21 AR26

AJ24 AM22 AM24 AM26 AM27

AM29

AL29

AJ15 AH15

AJ5 AJ4

AH14 AG14

AG6

AK6 AM6

AK4 AM4

AG21

AH19 AM30

AD12

AR33 AP33

Share one pad

U1B

Integrated

T2XCM

TMDS2

T2XCP T2X0M

T2X0P T2X1M

T2X1P T2X2M

T2X2P T2X3M

T2X3P T2X4M

T2X4P T2X5M

T2X5P T2PVDD

T2PVSS

T2XVDDC_1 T2XVDDC_2

T2XVDDR_1 T2XVDDR_2

T2XVSSR_1 T2XVSSR_2 T2XVSSR_3 T2XVSSR_4 T2XVSSR_5 T2XVSSR_6 T2XVSSR_7 T2XVSSR_8 T2XVSSR_9 T2XVSSR_10 T2XVSSR_11 T2XVSSR_12 T2XVSSR_13 T2XVSSR_14

DDC1DATA DDC1CLK

DDC2DATA DDC2CLK

DDC3DATA DDC3CLK

DDC4DATA DDC4CLK

HPD1

SDA SCL

DMINUS DPLUS TS_FDO

PLLTEST TESTEN

VREFG

XTALIN XTALOUT

RV630XT A14 RH

Monitor

Monitor Interface

Interface

MMI2C

Thermal

Thermal Diode

Diode

Test

PART 2 OF 7

V

V I

I D

D E

E O

O

&

M

M U

U L

L T

T I

I M

M E

E D

D I

I A

A

Integrated

Integrated TMDS

TMDS

TXVDDR_2 TXVDDR_3 TXVDDR_4 TXVDDR_5

TXVSSR_1 TXVSSR_2 TXVSSR_3 TXVSSR_4 TXVSSR_5 TXVSSR_6 TXVSSR_7 TXVSSR_8 TXVSSR_9

TXVSSR_10

DAC / CRT

DAC2 (TV/CRT2)

TXCAM TXCAP

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TX3M

TX3P

TX4M

TX4P

TX5M

TX5P

TPVDD TPVSS

HSYNC

VSYNC

RSET AVDD

AVSSQ

VDD1DI VSS1DI

H2SYNC

V2SYNC

COMP

R2SET

A2VDDQ

A2VSSQ

VDD2DI VSS2DI

A2VDD

AN9 AN10

AR10 AP10

AR11 AP11

AR12 AP12

AR15 AP15

AR16 AP16

AR17 AP17

AM14 AL14

AN19 AN20 AP19 AR19

AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AR18 AP18

AR31

R

AP31

RB

AR30

G

AP30

GB

AR29

B

AP29

BB

AN29 AN30

AN31 AR32 AP32

AR28 AP28

AM19

R2

AL19

R2B

AM18

G2

AL18

G2B

AM17

B2

AL17

B2B

AM15 AL15

AK18

Y

AK19

C

AK17

R2SET GND_A2VSSQ

AJ21

AL21 AK21

AH22 AG22

AM21

3

C110

C110 10nF

10nF

C114

C114 10nF

10nF

R1030 499RR1030 499R

C1023

C1023 10nF

10nF

R2030 715RR2030 715R

C2021

C2021 100nF_6.3V

100nF_6.3V

C2024

C2024 10nF

10nF

C2030

C2030 10nF

10nF

3

C111

C111 100nF

100nF

C115

C115 100nF

100nF

DNI

C2025

C2025 100nF_6.3V

100nF_6.3V

C2031

C2031 100nF_6.3V

100nF_6.3V

GND

GND_AVSSQRSET

C1024

C1024 100nF_6.3V

100nF_6.3V

GND

GND_VSS2DI

C2032

C2032 1uF_6.3V

1uF_6.3V

C112

C112 1uF_6.3V

1uF_6.3V

C116

C116 1uF_6.3V

1uF_6.3V

+VDD2DI

C2026

C2026 1uF_6.3V

1uF_6.3V

C113

C113 10uF_X6S

10uF_X6S

+TXVDDR

C117

C117 10uF_X6S

10uF_X6S

C1020

C1020 10nF

10nF

+VDD1DI

C1025

C1025 1uF_6.3V

1uF_6.3V

+A2VDDQ

NS2021 NS_VIANS2021 NS_VIA

C2033

C2033 10uF_X6S

10uF_X6S

+TPVDD

NS110

NS110 NS_VIA

NS_VIA

GND_TPVSS

C1021

C1021 100nF_6.3V

100nF_6.3V

NS1021 NS_VIANS1021 NS_VIA

GND_VSS1DI

NS2020 NS_VIANS2020 NS_VIA

12

C1022

C1022 1uF_6.3V

1uF_6.3V

12

GND_A2VSSQ

+A2VDD

T1XCM T1XCP

T1X0M T1X0P

T1X1M T1X1P

T1X2M T1X2P

T1X3M T1X3P

T1X4M T1X4P

T1X5M T1X5P

12

A_DAC1_R (15) A_DAC1_RB (15)

A_DAC1_G (15) A_DAC1_GB (15)

A_DAC1_B (15) A_DAC1_BB (15)

+AVDD

NS1020 NS_VIANS1020 NS_VIA

GND_AVSSQ

A_DAC2_R (16) A_DAC2_RB (16)

A_DAC2_G (16) A_DAC2_GB (16)

A_DAC2_B (16) A_DAC2_BB (16)

HSYNC_DAC2 (7,16) VSYNC_DAC2 (7,16)

A_DAC2_Y (17) A_DAC2_C (17) A_DAC2_COMP (17)

B2030 0RB2030 0R

2

Place close to ASICPlace close to ASIC

R116 182RR116 182R

R110 182RR110 182R

R111 182RR111 182R

R112 182RR112 182R

R113 182RR113 182R

R114 182RR114 182R

R115 182RR115 182R

HSYNC_DAC1 (7,15) VSYNC_DAC1 (7,15)

VSYNC1_TCK (1)

12

+3.3V

2

T1XCM (16) T1XCP (16)

T1X0M (16) T1X0P (16)

T1X1M (16) T1X1P (16)

T1X2M (16) T1X2P (16)

T1X3M (16) T1X3P (16)

T1X4M (16) T1X4P (16)

T1X5M (16) T1X5P (16)

HSYNC1_TRST (1)

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - ASIC MAIN

Size Document Number Rev

Custom

Date: Sheet

1

105-B101XX-00

1

4

of

321Tuesday, April 10, 2007

www.vinafix.vn

R940RR94

C151

C151 1uF_6.3V

1uF_6.3V

C131

C131 100nF_6.3V

100nF_6.3V

C141

C141 1uF_6.3V

1uF_6.3V

C121

C121 1uF_6.3V

1uF_6.3V

0R

5

C125

C125 10uF_X6S

10uF_X6S

C951

C951 10uF_X6S

10uF_X6S

C152

C152 1uF_6.3V

1uF_6.3V

C132

C132 100nF_6.3V

100nF_6.3V

C142

C142 1uF_6.3V

1uF_6.3V

C126

C126 10uF_X6S

10uF_X6S

C120

1uF_6.3V

NS70 NS_VIANS70 NS_VIA

1 2

GND_PVSS

C154

C154 1uF_6.3V

1uF_6.3V

C133

C134

100nF_6.3V

C143

C144

1uF_6.3V

C127

C127 10uF_X6S

10uF_X6S

C950

C950 10uF_X6S

10uF_X6S

NS120 NS_VIANS120 NS_VIA

1 2 GND_VSSRHA_1

+3.3V

C90

C90 1uF_6.3V

1uF_6.3V

+VDDR_DVP

+DPLL_PVDD

C155

C155 1uF_6.3V

1uF_6.3V

C135

C135 100nF_6.3V

100nF_6.3V

C145

C145 1uF_6.3V

1uF_6.3V

C128

C128 10uF_X6S

10uF_X6S

C91

C91 100nF_6.3V

100nF_6.3V

C94

C94 10uF_X6S

10uF_X6S

C136

C136 100nF_6.3V

100nF_6.3V

C146

C146 1uF_6.3V

1uF_6.3V

C952

C122

C122 1uF_6.3V

1uF_6.3V

NS122 NS_VIANS122 NS_VIA

1 2

GND_VSSRHB_1

C92

C92 1uF_6.3V

1uF_6.3V

C70

C70 1uF_6.3V

1uF_6.3V

C157

C157 1uF_6.3V

1uF_6.3V

C137

C137 100nF_6.3V

100nF_6.3V

C147

C147 1uF_6.3V

1uF_6.3V

C129

C129 10uF_X6S

10uF_X6S

NS123 NS_VIANS123 NS_VIA

1 2

GND_VSSRHB_2

C93

C93 100nF_6.3V

100nF_6.3V

C95

C95 1uF_6.3V

1uF_6.3V

C71

C71 100nF_6.3V

100nF_6.3V

C158

C158 1uF_6.3V

1uF_6.3V

C138

C138 100nF_6.3V

100nF_6.3V

C148

C148 1uF_6.3V

1uF_6.3V

C97

C97 100nF_6.3V

100nF_6.3V

C72

C72 10uF_X6S

10uF_X6S

Recommended caps: (see BOM for qualified values/vendors) 10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK 1uF, X6S, 0402, 6.3V 100nF, X7R, 0402 10nF , X7R, 0402

+MVDD

C150

C150 1uF_6.3V

1uF_6.3V

D D

C156

C130

100nF_6.3V

C140

C153

1uF_6.3V

C124

C124 10uF_X6S

10uF_X6S

+MVDD

B120

BLM15BD121SN1

B121

BLM15BD121SN1

C C

NS121 NS_VIANS121 NS_VIA

1 2

GND_VSSRHA_2

B122

BLM15BD121SN1

B123

BLM15BD121SN1

+1.8V +3.3V

B B

A A

C123

C123 1uF_6.3V

1uF_6.3V

C159

C159 1uF_6.3V

1uF_6.3V

C139

C139 100nF_6.3V

100nF_6.3V

C96

C96 1uF_6.3V

1uF_6.3V

4

C149

C149 1uF_6.3V

1uF_6.3V

C953

C953 10uF_X6S

10uF_X6S

C98

C98 100nF_6.3V

100nF_6.3V

+DPLL_PVDD

GND_PVSS

AE14 AE15 AE17

AR20

AP20

AR35

AF12

A8 H35 L22

M1

M10 M35

P10

T1

Y1 A12 A16 A20 A24 A28

B1 B35

D1 D35

H1 K10 K12 K24 K26 L14 L15 L17 L18 L19 L21

A25 A32

B2

L1

B25 B32

C2

L2

AP2 AR2

AN1 AP1

A35

AR1

U1E

VDDR1_1 VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5 VDDR1_6 VDDR1_7 VDDR1_8 VDDR1_9 VDDR1_10 VDDR1_11 VDDR1_12 VDDR1_13 VDDR1_14 VDDR1_15 VDDR1_16 VDDR1_17 VDDR1_18 VDDR1_19 VDDR1_20 VDDR1_21 VDDR1_22 VDDR1_23 VDDR1_24 VDDR1_25 VDDR1_26 VDDR1_27 VDDR1_28 VDDR1_29

VDDRHA_1 VDDRHA_2

VDDRHB_1 VDDRHB_2

VSSRHA_1 VSSRHA_2

VSSRHB_1 VSSRHB_2

VDDR3_1 VDDR3_2 VDDR3_3 VDDR3_4

VDDR4_1 VDDR4_2

VDDR5_1 VDDR5_2

DPLL_PVDD

DPLL_PVSS

MECH_1 MECH_2 MECH_3

RV630XT A14 RH

PART 5 OF 7

Memory I/O

Selected PLL's

Mechanical Pins

3

C932

C932 10uF_X6S

10uF_X6S

C920

C920 1uF_6.3V

1uF_6.3V

C901

C901 100nF_6.3V

100nF_6.3V

C163

C163 1uF_6.3V

1uF_6.3V

C173

C173 1uF_6.3V

1uF_6.3V

C66

1uF_6.3V

C921

C921 1uF_6.3V

1uF_6.3V

C902

C902 1uF_6.3V

1uF_6.3V

C185

C185 1uF_6.3V

1uF_6.3V

C942

C942 1uF_6.3V

1uF_6.3V

+VDD_CT

C69

C69 100nF_6.3V

100nF_6.3V

C62

C62 10uF_X6S

10uF_X6S

+PCIE_PVDD

C933

C933 1uF_6.3V

1uF_6.3V

C164

C164 1uF_6.3V

1uF_6.3V

C174

C174 1uF_6.3V

1uF_6.3V

BLM15BD121SN1

C67

10uF_X6S

+DPLL_VDDC

C63

C63 1uF_6.3V

1uF_6.3V

AM35

PCIE_PVDD

AM34

PCIE_PVSS

R26

PCIE_VDDC_1

W25

PCIE_VDDC_2

W26

PCIE_VDDC_3

AA25

PCIE_VDDC_4

AA26

PCIE_VDDC_5

AB25

PCIE_VDDC_6

AB26

PCIE_VDDC_7

AD26

PCIE_VDDC_8

AF26

PCIE_VDDC_9

U26

PCIE_VDDC_10

V25

PCIE_VDDC_11

V26

PCIE_VDDC_12

AL33

PCIE_VDDR_1

AM33

PCIE_VDDR_2

AN33

PCIE_VDDR_3

AN34

PCIE_VDDR_4

AN35

PCIE_VDDR_5

PCI-Express

P

P O

O W

W E

E

Core

R

PCIE_VDDR_6 PCIE_VDDR_7 PCIE_VDDR_8

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33 VDDC_34 VDDC_35 VDDC_36 VDDC_37 VDDC_38 VDDC_39 VDDC_40 VDDC_41 VDDC_42 VDDC_43 VDDC_44

BBP_1 BBP_2

VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4

VDD_CT_1 VDD_CT_2 VDD_CT_3 VDD_CT_4 VDD_CT_5 VDD_CT_6 VDD_CT_7 VDD_CT_8

MPVDD

MPVSS

DPLL_VDDC

AP34 AP35 AR34

N13 R18 W11 AB19 AC23 AE18 AE19 AE21 AE22 N15 N18 N21 N23 P14 P17 P19 P22 R13 R15 R21 R23 U14 U17 U19 U22 V15 V18 V21 V23 W14 W17 W19 W22 AA15 AA18 AA21 AA23 AB14 AB17 AB22 AC13 AC15 AC18 AC21

U13 V13

M12 M24 P11 P25

R11 R25 U11 U25 AA11 AB11 AD10 AF10

A14

B15

AG19

+MPVDD

GND_MPVSS

+DPLL_VDDC

+VDDC

C78

C78 100nF_6.3V

100nF_6.3V

C930

C930 10nF

10nF

C161

C161 1uF_6.3V

1uF_6.3V

C171

C171 1uF_6.3V

1uF_6.3V

C160

C160 1uF_6.3V

1uF_6.3V

C64

10nF

GND_PVSS

C900

C900 10nF

10nF

C940

C940 1uF_6.3V

1uF_6.3V

C79

C79 100nF_6.3V

100nF_6.3V

C60

C60 10nF

10nF

C931

C931 100nF_6.3V

100nF_6.3V

C162

C162 1uF_6.3V

1uF_6.3V

C172

C172 1uF_6.3V

1uF_6.3V

C184

C184 1uF_6.3V

1uF_6.3V

C65

C941

C941 1uF_6.3V

1uF_6.3V

C68

C68 100nF_6.3V

100nF_6.3V

C61

C61 100nF_6.3V

100nF_6.3V

NS18 NS_VIANS18 NS_VIA

12

GND_PCIE_PVSS

C923

C922

1uF_6.3V

C903

C904

10nF

100nF_6.3V

C166

C165

1uF_6.3V

C176

C175

1uF_6.3V

C186

C186 1uF_6.3V

1uF_6.3V

C943

C943 1uF_6.3V

1uF_6.3V

B69

+1.8V

+MPVDD

B67 26R_600mAB67 26R_600mA

GND_MPVSS

2

B930

BLM15BD121SN1

C924

C924 1uF_6.3V

1uF_6.3V

C905

C905 1uF_6.3V

1uF_6.3V

C167

C167 1uF_6.3V

1uF_6.3V

C177

C177 1uF_6.3V

1uF_6.3V

NS64NS_VIA NS64NS_VIA

12

+1.8V

C925

C925 1uF_6.3V

1uF_6.3V

C906

C906 1uF_6.3V

1uF_6.3V

C168

C169

1uF_6.3V

C178

C179

1uF_6.3V

C188

+VDDC

C188 10uF_X6S

10uF_X6S

C946

C946 1uF_6.3V

1uF_6.3V

C73

C73 100nF_6.3V

100nF_6.3V

C187

C187 10uF_X6S

10uF_X6S

Install only one of these two

See BOM for qualified option

C926

C926 10uF_X6S

10uF_X6S

C907

C907 1uF_6.3V

1uF_6.3V

C74

C74 100nF_6.3V

100nF_6.3V

B60

B60 BLM15BD121SN1

BLM15BD121SN1

C170

C170 1uF_6.3V

1uF_6.3V

C180

C180 1uF_6.3V

1uF_6.3V

C947

C947 1uF_6.3V

1uF_6.3V

C76

C76 1uF_6.3V

1uF_6.3V

C189

C189 10uF_X6S

10uF_X6S

C75

C75 1uF_6.3V

1uF_6.3V

+PCIE_VDDC

+PCIE_VDDR

C181

C181 10uF_X6S

10uF_X6S

C948

C948 1uF_6.3V

1uF_6.3V

+1.1V

+VDDC

C77

C77 10uF_X6S

10uF_X6S

C99

C99 10uF_X6S

10uF_X6S

Install only one of these two

See BOM for qualified option

R9000RR900

+1.8V

0R

+VDDC

C183

C182

10uF_X6S

C949

C949 1uF_6.3V

1uF_6.3V

+VDDCI_1

+VDDCI_2

1

+VDDC

R9200RR920

0R

B77 220R_2AB77 220R_2A

B78 220R_2AB78 220R_2A

+1.1V

+VDDC

+VDDCI_LDO

See BOM for qualified option

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - ASIC Power

Size Document Number Rev

C

Date: Sheet

5

4

3

2

Date: Sheet

105-B101XX-00

1

4

of

421Tuesday, April 10, 2007

www.vinafix.vn

5

4

3

2

1

+MVDD

R291

40.2R

402 1%

R292

R292 100R

100R

402 1%

R293

40.2R

402 1%

R294

R294 100R

100R

402 1%

DQA_[63..0](8,9)

MVREFS_0

U1C

DQA_0

P27

C294

C294 10nF

10nF

P28 P31 P32

M27

K29 K31

K32 M33 M34

L34

L35

J33

J34 H33 H34

K27

J29

J30

J31

F29

F32 D30 D32 G33 G34 G35

F34 D34 C34 C35

B34 C24

B24

B23

A23 C21

B21 C20

B20

J22 H22

F22 D21

J19 G19

F19 D19 C19

B19

A19

B18 C16

B16 C15

A15 H18

F18

E18 D18

J17 G15

E15 D15

N35 N34

RV630XT A14 RH

DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63

MVREFDA MVREFSA

DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63

C292

C291

10nF

100nF_6.3V

MVREFD_0 MVREFD_1

C293

C293 100nF_6.3V

100nF_6.3V

Part 3 of 7

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8

MAA_9 MAA_10 MAA_11

MAA_A12 MAA_BA0 MAA_BA1

MAA_BA2

DQMAB_0 DQMAB_1 DQMAB_2 DQMAB_3 DQMAB_4 DQMAB_5 DQMAB_6 DQMAB_7

MEMORY INTERFACE A

DDR1 DDR2 DDR3

Not usedbidir. strobe

QSA_0

QSA_1

QSA_2

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0B QSA_1B QSA_2B QSA_3B QSA_4B QSA_5B QSA_6B

bidir. differential strobe

write stroberead strobe

bidir. differential strobe

write stroberead strobe

QSA_7B

ODTA0

For DDR2

ODTA1

CLKA0 CLKA0B

CKEA0 RASA0B CASA0B

WEA0B

CSA0B_0 CSA0B_1

CLKA1 CLKA1B

CKEA1 RASA1B CASA1B

WEA1B

CSA1B_0 CSA1B_1

MAA_0

C27

MAA_1

B28

MAA_2

B27

MAA_3

G26

MAA_4

F27

MAA_5

E27

MAA_6

D27

MAA_7

J27

MAA_8

E29

MAA_9

C30

MAA_10

E26

MAA_11

A27

MAA_12

G27

MAA_14

C28

MAA_15

B29

MAA_13

D26

DQMAb_0

M29

DQMAb_1

K33

DQMAb_2

G30

DQMAb_3

E33

DQMAb_4

C22

DQMAb_5

H21

DQMAb_6

C17

DQMAb_7

G17

QSA_0

M30

QSA_1

K34

QSA_2

G31

QSA_3

E34

QSA_4

B22

QSA_5

F21

QSA_6

B17

QSA_7

D17

QSAb_0

M31

QSAb_1

K35

QSAb_2

G32

QSAb_3

E35

QSAb_4

A22

QSAb_5

E21

QSAb_6

A17

QSAb_7

E17 C31

C25

A33

CLKA0 (8,9)

B33

CLKA0b (8,9)

B31

CKEA0 (8,9)

A31

RASA0b (8,9)

C32

CASA0b (8,9)

C29

WEA0b (8,9)

A30

CSA0b_0 (8)

B30

CSA0b_1 (9)

A26

CLKA1 (8,9)

B26

CLKA1b (8,9)

F24

CKEA1 (8,9)

D24

RASA1b (8,9)

H26

CASA1b (8,9)

D22

WEA1b (8,9)

G24

CSA1b_0 (8)

H24

CSA1b_1 (9)

MAA_[15..0] (8,9)

DQMAb_[7..0] (8,9)

QSA_[7..0] (8,9)

QSAb_[7..0] (8,9)

+MVDD

R391

40.2R

402 1%

R392

R392 100R

100R

402 1%

+MVDD

R393

40.2R

402 1%

R394

R394 100R

100R

402 1%

C391

C391 100nF_6.3V

100nF_6.3V

C393

C393 100nF_6.3V

100nF_6.3V

C392

C392 10nF

10nF

C394

C394 10nF

10nF

DRAM_RST(8,9)

MVREFS_1

DQB_[63..0](8,9)

+MVDD

R295

2.0K

DNI

R296

4.7K

DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63

R297

4.7K

R298

R298 243R

243R

U1D

H15

DQB_0

G14

DQB_1

E14

DQB_2

D14

DQB_3

H12

DQB_4

G12

DQB_5

F12

DQB_6

D10

DQB_7

B13

DQB_8

C12

DQB_9

B12

DQB_10

B11

DQB_11

C9

DQB_12

B9

DQB_13

A9

DQB_14

B8

DQB_15

J10

DQB_16

H10

DQB_17

F10

DQB_18

D9

DQB_19

G7

DQB_20

G6

DQB_21

F6

DQB_22

D6

DQB_23

C8

DQB_24

C7

DQB_25

B7

DQB_26

A7

DQB_27

B5

DQB_28

A5

DQB_29

C4

DQB_30

B4

DQB_31

M3

DQB_32

M2

DQB_33

N2

DQB_34

N1

DQB_35

R3

DQB_36

R2

DQB_37

T3

DQB_38

T2

DQB_39

M8

DQB_40

M7

DQB_41

P5

DQB_42

P4

DQB_43

R9

DQB_44

R8

DQB_45

R6

DQB_46

U4

DQB_47

U3

DQB_48

U2

DQB_49

U1

DQB_50

V2

DQB_51

Y3

DQB_52

Y2

DQB_53

AA2

DQB_54

AA1

DQB_55

U9

DQB_56

U7

DQB_57

U6

DQB_58

V4

DQB_59

W9

DQB_60

W7

DQB_61

W6

DQB_62

W4

DQB_63

B14

MVREFDB

A13

MVREFSB

AA4

DRAM_RST

AA8

TEST_MCLK

AA7

TEST_YCLK

AA5

MEMTEST

RV630XT A14 RH

Part 4 of 7

MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8

MAB_9 MAB_10 MAB_11

MAB_A12 MAB_BA0 MAB_BA1

MAB_BA2

DQMBB_0 DQMBB_1 DQMBB_2 DQMBB_3 DQMBB_4 DQMBB_5 DQMBB_6 DQMBB_7

MEMORY INTERFACE B

DDR1 DDR2 DDR3

Not usedbidir. strobe

QSB_0

QSB_1

QSB_2

QSB_3

QSB_4

QSB_5

QSB_6

QSB_7

QSB_0B QSB_1B QSB_2B QSB_3B QSB_4B QSB_5B QSB_6B

write strobe

QSB_7B

bidir. differential strobe

ODTB0

For DDR2

ODTB1

CLKB0 CLKB0B

CKEB0 RASB0B CASB0B

WEB0B

read strobe

CSB0B_0 CSB0B_1

CLKB1 CLKB1B

CKEB1 RASB1B CASB1B

WEB1B

CSB1B_0 CSB1B_1

MAB_0

H2

MAB_1

H3

MAB_2

J3

MAB_3

J5

MAB_4

J4

MAB_5

J6

MAB_6

G5

MAB_7

J9

MAB_8

F3

MAB_9

F4

MAB_10

J1

MAB_11

J2

MAB_12

J7

MAB_14

G2

MAB_15

G3

MAB_13

F1

DQMBb_0

D12

DQMBb_1

C10

DQMBb_2

E7

DQMBb_3

C6

DQMBb_4

P3

DQMBb_5

R4

DQMBb_6

W3

DQMBb_7

V8

QSB_0

J14

QSB_1

B10

QSB_2

F9

QSB_3

B6

QSB_4

P2

QSB_5

P8

QSB_6

W2

QSB_7

V6

QSBb_0

H14

QSBb_1

A10

QSBb_2

E9

QSBb_3

A6

QSBb_4

P1

QSBb_5

P7

QSBb_6

W1

QSBb_7

V5 D2

K5

A3

CLKB0 (8,9)

B3

CLKB0b (8,9)

E3

CKEB0 (8,9)

D3

RASB0b (8,9)

C1

CASB0b (8,9)

F2

WEB0b (8,9)

E1

CSB0b_0 (8)

E2

CSB0b_1 (9)

K1

CLKB1 (8,9)

K2

CLKB1b (8,9)

K8

CKEB1 (8,9)

K7

RASB1b (8,9)

K4

CASB1b (8,9)

M6

WEB1b (8,9)

L3

CSB1b_0 (8)

M4

CSB1b_1 (9)

MAB_[15..0] (8,9)

DQMBb_[7..0] (8,9)

QSB_[7..0] (8,9)

QSBb_[7..0] (8,9)

D D

C C

B B

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - ASIC Memory Interface (Channel A & B)

Size Document Number Rev

C

Date: Sheet

5

4

3

2

Date: Sheet

105-B101XX-00

1

4

of

521Tuesday, April 10, 2007

www.vinafix.vn

5

D D

C C

B B

A A

5

4

U1F

P33

PCIE_VSS_1

V29

PCIE_VSS_2

AB32

PCIE_VSS_3

AG29

PCIE_VSS_4

AJ29

PCIE_VSS_5

AJ32

PCIE_VSS_6

AK32

PCIE_VSS_7

AL34

PCIE_VSS_8

AL35

PCIE_VSS_9

P34

PCIE_VSS_10

P35

PCIE_VSS_11

R27

PCIE_VSS_12

R28

PCIE_VSS_13

R29

PCIE_VSS_14

R32

PCIE_VSS_15

R33

PCIE_VSS_16

T33

PCIE_VSS_17

U29

PCIE_VSS_18

U32

PCIE_VSS_19

V32

PCIE_VSS_20

V34

PCIE_VSS_21

V35

PCIE_VSS_22

W29

PCIE_VSS_23

W32

PCIE_VSS_24

W33

PCIE_VSS_25

Y33

PCIE_VSS_26

AA29

PCIE_VSS_27

AA32

PCIE_VSS_28

AB29

PCIE_VSS_29

AB34

PCIE_VSS_30

AB35

PCIE_VSS_31

AC33

PCIE_VSS_43

AD29

PCIE_VSS_32

AD32

PCIE_VSS_33

AD33

PCIE_VSS_34

AF29

PCIE_VSS_35

AF32

PCIE_VSS_36

AF34

PCIE_VSS_37

AF35

PCIE_VSS_38

AG27

PCIE_VSS_39

AG32

PCIE_VSS_40

AG33

PCIE_VSS_41

AH33

PCIE_VSS_42

A2

VSS_1

P15

VSS_2

R14

VSS_3

V1

VSS_4

W8

VSS_5

AA19

VSS_6

AC17

VSS_7

AF19

VSS_8

AK3

VSS_9

A4

VSS_10

C18

VSS_11

E22

VSS_12

G4

VSS_13

J18

VSS_14

K17

VSS_15

M28

VSS_16

P6

VSS_17

P9

VSS_18

P13

VSS_19

P18

VSS_20

P21

VSS_21

P23

VSS_22

P26

VSS_23

P29

VSS_24

P30

VSS_25

R1

VSS_26

R5

VSS_27

R7

VSS_28

R10

VSS_29

R17

VSS_30

R19

VSS_31

R22

VSS_32

U5

VSS_33

U8

VSS_34

U10

VSS_35

U15

VSS_36

U18

VSS_37

U21

VSS_38

U23

VSS_39

V3

VSS_40

V7

VSS_41

V9

VSS_42

V10

VSS_43

V11

VSS_44

V14

VSS_45

V17

VSS_46

V19

VSS_47

V22

VSS_48

W5

VSS_49

W10

VSS_50

W15

VSS_51

W18

VSS_52

W21

VSS_53

W23

VSS_54

AA3

VSS_55

AA6

VSS_56

AA10

VSS_57

AA14

VSS_58

AA17

VSS_59

AA22

VSS_60

AB5

VSS_61

AB8

VSS_62

AB10

VSS_63

AB13

VSS_64

AB15

VSS_65

AB18

VSS_66

AB21

VSS_67

AB23

VSS_68

AC14

VSS_69

AC19

VSS_70

AC22

VSS_71

AD6

VSS_72

AD24

VSS_73

AF6

VSS_74

AF9

VSS_75

AF14

VSS_76

AF15

VSS_77

AF17

VSS_78

AF18

VSS_79

AF21

VSS_80

AF22

VSS_81

AF24

VSS_82

AG10

VSS_83

AG12

VSS_84

AH21

VSS_85

RV630XT A14 RH

4

Part 6 of 7

PCI-Express GND

CORE GND

3

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166

3

VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

TXCBP TXCBM

BBN_1 BBN_2

AJ14 AJ17 AJ18 AJ19 AK9 AK10 AK12 AK15 AK30 AM1 AN3 AN6 AN32 AR8 A11 A18 A21 A29 A34 C3 C5 C11 C13 C14 C23 C26 C33 D4 D7 D29 D33 E10 E12 E19 E24 F7 F14 F15 F17 F26 F30 F33 F35 G1 G9 G10 G18 G21 G22 G29 H17 H19 J12 J15 J21 J24 J26 J32 J35 K3 K6 K9 K14 K15 K18 K19 K21 K22 K28 K30 L33 M5 M9 M26 M32 N3 N14 N17 N19 N22 N33

AP14 AR14

W13 AA13

2

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - ASIC Grounds

Size Document Number Rev

C

Date: Sheet

2

Date: Sheet

1

105-B101XX-00

1

4

of

621Tuesday, April 10, 2007

www.vinafix.vn

5

VID_[7..0](17)

D D

CrossFire

DVP_MVP_CNTL_0 : DE for bits D[12..23] DVP_MVP_CNTL_1 : CLK for bits D[12..23]

C C

VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6 VID_7

VPCLK0(17)

VHAD_0(17) VHAD_1(17)

VPHCTL(17) VIPCLK(17)

DVOCLK DVPCNTL_0 DVPCNTL_1

DVPCNTL_2 DVP_MVP_CNTL_0 DVP_MVP_CNTL_1

DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8

DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

AM12

AL12

AJ12 AH12 AM10

AL10

AJ10 AH10

AL7

AM9 AL9

AJ9

AK7

AH1 AG1 AH3 AH2 AN8 AP8

AJ3 AJ2

AJ1 AK2 AK1 AL3 AL2 AL1 AM3 AM2 AN2 AP3 AR3 AN4 AR4 AP4 AN5 AR5 AP5 AP6 AR6 AN7 AP7 AR7

U1G

VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6 VID_7

VPCLK0

VHAD_0 VHAD_1

VPHCTL VIPCLK

DVPCLK DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCNTL_MVP_0 DVPCNTL_MVP_1

DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

RV630XT A14 RH

VIP

VIP Capture

Capture

VIP

VIP Host

Host

PART 7 OF 7

General

General Purpose

Purpose I/O

I/O

GPIO_15_PWRCNTL_0

GPIO_17_THERMAL_INT

GPIO_20_PWRCNTL_1

GPIO_23_CLKREQB

RESERVED

No Connect

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_11 GPIO_12 GPIO_13

GPIO_14_HPD2

GPIO_16_SSIN

GPIO_18_HPD3 GPIO_19_CTFB

GPIO_21_BB_EN

GPIO_22_ROMCSB

GPIO_24_JMODE

GPIO_25_TDI

GPIO_26_TCK GPIO_27_TMS GPIO_28_TDO

GENERICA GENERICB

GENERICC

DVALID

PSYNC

RSVD_12

RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8

RSVD_9 RSVD_10 RSVD_11

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9

NC_10

4

GPIO_0

AG2

GPIO_1

AF2 AF1 AE3 AE2 AE1 AD3 AD2 AD1 AD5 AD4 AC3 AC2 AC1 AB3 AB2 AB1 AF5 AF4 AG4 AG3 AD9 AD8 AD7 AB4 AB6 AB7 AB9 AA9

AF8 AF7 AG5

AJ7 AM7

AJ6

AF3 AH24 AK24 AK26 AK34 AK35 AL24 AL26 AG7 AG9 AG24

AG15 AG17 AG18 AH17 AH18 AP13 AP9 AR13 AR9 AK14

PWRCNTL_0 GPIO16 ThermINT GPIO18_HPD3 CTFb PWRCNTL_1 GPIO21_BB_EN GPIO_22

JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

GENERICA GENERICB GENERICC

DVALID PSYNC

GPIO_2

GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 HPD2

GPIO_3 GPIO_4 GPIO_5 GPIO_6

FLOW_CONTROL_1 - Lower Cable FLOW_CONTROL_2 - Upper Cable SWAP_LOCK_1 - Lower Cable SWAP_LOCK_2 - Upper Cable

HPD2 (15) PWRCNTL_0 (13)

ThermINT (18)

CTFb (13) PWRCNTL_1 (13)

PCIE_CLK_REQb

CrossFire

JTAG_MODE

MR51KMR5 1K

3

EXT_12V_DETb (10)

+3.3V

BUO

GENERICA_R (17)

DNI

Single Rank

MR52 10KMR52 10K MR53 10KMR53 10K

MR54 10KMR54 10K

MR55 10KMR55 10K

MR56 10KMR56 10K

MR58 10KMR58 10K MR59 10KMR59 10K

MR62 10KMR62 10K MR61 10KMR61 10K

MR65 10KMR65 10K

MR66 10KMR66 10K

MR67 10KMR67 10K

MR68 10KMR68 10K

MR69 10KMR69 10K

MR70 10KMR70 10K

MR71 10KMR71 10K

MR72 10KMR72 10K

MR74 10KMR74 10K

MR75 10KMR75 10K

MR76 10KMR76 10K

MR77 10KMR77 10K

MR78 10KMR78 10K MR79 10KMR79 10K

MR60 10KMR60 10K

+3.3V

Dual Rank

DNI

BUO

DNI

NTSC

DNI

BUO

DNI

2

R50 10KR50 10K

R51 10KR51 10K

R57 10KR57 10K

R63 10KR63 10K

R73 10KR73 10K

PIN BASED STRAPS

GPIO_0

GPIO_1

GPIO_2

GPIO_2 GPIO_3

GPIO_3

GPIO_5

GPIO_6

GPIO_7GPIO_7

GPIO_8 GPIO_9

GPIO_13

GPIO_13 GPIO_12

GPIO_12 GPIO_11

GPIO_11

GENERICC GENERICB

VSYNC_DAC1

HSYNC_DAC1

PSYNC

GPIO21_BB_EN

VID_0

VID_1

VID_2

VID_3

VID_4

VID_5

VID_6

VID_7

VSYNC_DAC2

VSYNC_DAC2 HSYNC_DAC2

HSYNC_DAC2

DVALID

CONFIG[3] CONFIG[2] CONFIG[1] CONFIG[0]

BUO

VSYNC_DAC1 (3,15)

HSYNC_DAC1 (3,15)

VSYNC_DAC2 (3,16) HSYNC_DAC2 (3,16)

GPIO_4

1

GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)

0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)

0: Tx de-emphasis disabled for mobile mode 1: Tx de-emphasis enabled (Default setting for Desktop)

AMD Internal Use Only - Reserved (Default: 00)

DEBUG_ACCESS AMD Internal Use Only - Reserved (Default: 0)

AMD Board Feature III - Reserved (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

TV OUT STANDARD (Jumper position overwrite resistor settings)

0 - PAL TVO (Jumper is closed) 1 - NTSC TVO (Jumper is open)

AMD Internal Use Only - Reserved (Default: 0)

GPIO(9,13:11) - CONFIG[3..0]

0010 - 512Kbit AT25F512A (Atmel) 0011 - 1Mbit AT25F1024A (Atmel) 0100 - 512Kbit M25P05A (ST) 0101 - 1Mbit M25P10A (ST) 0101 - 2Mbit M25P20 (ST) 0100 - 512Kbit Pm25LV512 (Chingis) 0101 - 1Mbit Pm25LV010 (Chingis)

AMD Internal Use Only - Reserved (Default: 0)

VIP_DEVICE_STRAP_EN

0: Slave VIP host port devices present (use if Theater is populated) 1: No slave VIP host port devices reporting presence during reset (use for configurations without video-in)

AMD Board Feature II - Reserved (HDMI_EN)

VGA DISABLE : 1 for disable (set to 0 for normal operation)

AMD Internal Use Only - Reserved (Default: 0)

MSI_DIS (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

BIF_AUDIO_EN 0 - Disable HD Audio 1- Enable HD Audio

AMD Internal Use Only - Reserved (Default: 0)

64BAR_EN_A (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

MEMORY CONFIG V2SYNC: 0 = 1 rank of memory, 1 = 2 ranks of memory

AMD Internal Use Only - Reserved

BIF_CLK_PM_EN 0 - Disable CLKREQ# power management capability 1 - Enable CLKREQ# power management capability

AMD Board Feature I

Default: 0

ATI PCIE FEATURE I

ATI PCIE FEATURE II

Pull-Down Resistors are for BU until built-in pull-downs are verified.

B B

Place it at top edge of the board on the bottom side.

CrossFire Card-Edge

Lower Cable Card Edge

1

DVOCLK DVPCNTL_2 DVPDATA_1 DVPDATA_3 DVPDATA_5 DVPDATA_7 DVPDATA_9 DVPDATA_11 DVPCNTL_1

A A

GPIO_3

3 5 7

9 11 13 15 17 19 21 23 25 27 29 30 31 33 35 37 39

J8002J8002

2 4 6 8

DVPDATA_0

10 12

DVPDATA_2

14 16

DVPDATA_4

18 20

DVPDATA_6

22 24

DVPDATA_8

26 28

DVPDATA_10

32

DVPCNTL_0

34 36

GPIO_5

38 40

Bundle A

5

Upper Cable Card Edge

1

DVP_MVP_CNTL_1 DVP_MVP_CNTL_0 DVPDATA_13 DVPDATA_15 DVPDATA_17 DVPDATA_19 DVPDATA_21 DVPDATA_23 GENERICB_R GPIO_4

3 5 7

9 11 13 15 17 19 21 23 25 27 29 30 31 33 35 37 39

J8001J8001

2 4 6 8

DVPDATA_12

10 12

DVPDATA_14

14 16

DVPDATA_16

18 20

DVPDATA_18

22 24

DVPDATA_20

26 28

DVPDATA_22

32

DVALID_R

34 36

GPIO_6

38 40

Bundle B (closer to the bracket)

4

+3.3V

In production, this block will not be populated.

Mating connector: 6010028300G (HEADER 2X8 1.27MM PITCH, SMD) When attaching the daughter card (B176) align it by mounting hole.

Do not install for BU

GENERICB: Generic I2C_SDA DVALID: Generic I2C_SCL

DVALID GENERICB

DNI

JTAG_MODE

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO

For wire soldering

EXT_ADJ_1.8V

BUO

GPIO_8 GPIO_22 GPIO_9 GPIO_10 SDA SCL

3

+3.3V+5V

BUOBUO

SDA (3) SCL (3)

GPIO_22

Place SW1 on the bottom side (easily accessible). Clearly Mark A & B on silkscreen. Place TR46 next to SW1

TR46 0RTR46 0R

BUO

GPIO_8 GPIO_9 GPIO_10 ROMCSb

BIOS_ROM_EN

For NO ROM keep SW1B open without R46. For normal operation close SW1B or install TR46.

2

+3.3V

R45

R45 10K

10K

DNI

+3.3V

R46

R46 10K

10K

U2

D C S HOLD W VCC

VSS

M25P05-AVNM6P

2

Q

4

105-B101XX-00

1

BIOS1

BIOS

113-XXXXXX-XXX

VIDEO BIOS FIRMWARE

721Tuesday, April 10, 2007

of

5 6 1

+3.3V

7 3 8

C47

C47 100nF_6.3V

100nF_6.3V

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - ASIC DVO & GPIOs

Size Document Number Rev

C

Date: Sheet

4

www.vinafix.vn

DQA_[63..0](5,9)

MAA_[15..0](5,9)

D D

DQMAb_[7..0](5,9)

C C

In Single Rank Design: Use 60.4R (PN 316060R400G) for: R203, R202, R204, R205 R303, R302, R304, R305

+MVDD

R214

B B

2.37K

1%

R218

5.49K

1%

+MVDD

MAA_13 MAA_15 MAA_14 MAA_12 MAA_11 MAA_10 MAA_9 MAA_8 MAA_7 MAA_6 MAA_5 MAA_4 MAA_3 MAA_2 MAA_1 MAA_0

CLKA0(5,9) CLKA0b(5,9)

+MVDD

R206

2.37K

1%

R212

5.49K

1%

5

U201

DQA_13

T3

DQ31 | DQ23

DQA_12

T2

DQ30 | DQ22

DQA_14

R3

DQ29 | DQ21

DQA_15

R2

DQ28 | DQ20

DQA_10

M3

DQ27 | DQ19

DQA_11

N2

DQ26 | DQ18

DQA_8

L3

DQ25 | DQ17

DQA_9

M2

DQ24 | DQ16

DQA_31

T10

DQ23 | DQ31

DQA_28

T11

DQ22 | DQ30

DQA_29

R10

DQ21 | DQ29

DQA_30

R11

DQ20 | DQ28

DQA_27

M10

DQ19 | DQ27

DQA_26

N11

DQ18 | DQ26

DQA_24

L10

DQ17 | DQ25

DQA_25

M11

DQ16 | DQ24

DQA_5

G10

DQ15 | DQ7

DQA_6

F11

DQ14 | DQ6

DQA_7

F10

DQ13 | DQ5

DQA_4

E11

DQ12 | DQ4

DQA_1

C10

DQ11 | DQ3

DQA_0

C11

DQ10 | DQ2

DQA_2

B10

DQ9 | DQ1

DQA_3

B11

DQ8 | DQ0

DQA_16

G3

DQ7 | DQ15

DQA_17

F2

DQ6 | DQ14

DQA_19

F3

DQ5 | DQ13

DQA_18

E2

DQ4 | DQ12

DQA_22

C3

DQ3 | DQ11

DQA_21

C2

DQ2 | DQ10

DQA_23

B3

DQ1 | DQ9

DQA_20

B2

DQMAb_0 DQMAb_1 DQMAb_2 DQMAb_3 DQMAb_4 DQMAb_5 DQMAb_6 DQMAb_7

RASA0b(5,9)

CASA0b(5,9) CSA0b_0(5)

CKEA0(5,9) WEA0b(5,9)

+MVDD

R20360.4R R20360.4R R20260.4R R20260.4R

CLKA0b(5,9) CLKA0(5,9)

QSA_1 QSA_3 QSA_0 QSA_2

QSAb_1 QSAb_3 QSAb_0 QSAb_2

DQMAb_1 DQMAb_3 DQMAb_0 DQMAb_2

DRAM_RST(5,9) DRAM_RST(5,9)

R207 243RR207 243R

C200

C200 100nF_6.3V

100nF_6.3V

+MVDD

C204

C204 100nF_6.3V

100nF_6.3V

DQ0 | DQ8

MAA_4

K2

A0/A10 | A4/A8

MAA_5

H4

A1/BA0 | A5/BA1

MAA_6

K3

A2 /A12 | A6/BA2

MAA_7

L4

A3/A11 | A7/A9

MAA_0 MAA_8

K11

A4/A8 | A0/A10

MAA_1

H9

A5/BA1 | A1/BA0

MAA_2

K10

A6/BA2 | A2/A12

MAA_3

L9

A7/A9 | A3/A11

H2

RAS# | RFM

H11

RFM | RAS#

G9

CS# | CAS#

G4

CAS# | CS#

H10

WE# | CKE#

H3

CKE# | WE#

J10

CK

J11

CK

P3

RDQS3 | RDQS2

P10

RDQS2 | RDQS3

D10

RDQS1 | RDQS0

D3

RDQS0 | RDQS1

P2

WDQS3 | WDQS2

P11

WDQS2 | WDQS3

D11

WDQS1 | WDQS0

D2

WDQS0 | WDQS1

N3

DM3 | DM2

N10

DM2 | DM3

E10

DM1 | DM0

E3

DM0 | DM1

V9

RESET

A4

ZQ

1%

J4

VREFC

C201

J9

VREFD

10nF

23D41287QE09B

C205

C205 10nF

10nF

+MVDD +MVDD

VDDQ

VDDQ#A12

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#C12

VDDQ#E1 VDDQ#E4

VDDQ#E9 VDDQ#E12 VDDQ#H12

VDDQ#H1

VDDQ#N1

VDDQ#N4

VDDQ#N9 VDDQ#N12

VDDQ#R1

VDDQ#R4

VDDQ#R9 VDDQ#R12

VDDQ#V1 VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VDD#K1

VDD#K12

VSSQ VSSQ#B4 VSSQ#B9

VSSQ#B12

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1 VSSQ#P4 VSSQ#P9

VSSQ#P12

VSSQ#T1 VSSQ#T4 VSSQ#T9

VSSQ#T12

VSSQ#M4 VSSQ#M9

VSSQ#F4 VSSQ#F9

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VSS#J12

VSS#J1 VSS#K4 VSS#K9

RFU1

RFU0

GND | VDD

VDD

VSS

SEN

MF

+MVDD A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 H12 H1 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

A2 A11 F1 F12 M1 M12 V2 V11 K1 K12

B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 M4 M9 F4 F9

A3 A10 G1 G12 L1 L12 V3 V10 J12 J1 K4 K9

J2 V4 J3

A9

QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7

QSAb_0 QSAb_1 QSAb_2 QSAb_3 QSAb_4 QSAb_5 QSAb_6 QSAb_7

+MVDDC

+MVDD +MVDD

+MVDD

R216

2.37K

1%

R219

5.49K

1%

+MVDD

CLKA1(5,9) CLKA1b(5,9)

R209

2.37K

1%

R213

5.49K

1%

4

QSA_[7..0] (5,9)

QSAb_[7..0] (5,9)

+MVDD

DQA_33 DQA_32 DQA_34 DQA_35 DQA_37 DQA_36 DQA_39 DQA_38 DQA_54 DQA_53 DQA_55 DQA_52 DQA_50 DQA_51 DQA_48 DQA_49 DQA_44 DQA_46 DQA_47 DQA_45 DQA_42 DQA_40 DQA_41 DQA_43 DQA_60 DQA_58 DQA_56 DQA_59 DQA_61 DQA_57 DQA_62 DQA_63

MAA_12 MAA_13 MAA_14 MAA_15

MAA_9 MAA_10 MAA_11

RASA1b(5,9) CASA1b(5,9)

CSA1b_0(5) CKEA1(5,9)

WEA1b(5,9)

+MVDD

R20560.4R R20560.4R R20460.4R R20460.4R

CLKA1b(5,9) CLKA1(5,9)

QSA_4 QSA_6 QSA_5 QSA_7

QSAb_4 QSAb_6 QSAb_5 QSAb_7

DQMAb_4 DQMAb_6 DQMAb_5 DQMAb_7

R210 243RR210 243R

1%

C202

C203

100nF_6.3V

10nF

+MVDD

C207

C206

10nF

100nF_6.3V

T3 T2 R3 R2

M3

N2 L3

M2 T10 T11 R10 R11

M10

N11 L10

M11

G10 F11 F10 E11 C10 C11 B10 B11

G3 F2 F3 E2 C3 C2 B3 B2

K2 H4 K3 L4

K11

H9

K10

L9 H2

H11

G9 G4

H10

H3

J10 J11

P3 P10 D10

D3

P2 P11 D11

D2

N3 N10 E10

E3

V9

A4

J4

J9

U202

RAS# | RFM RFM | RAS#

CS# | CAS# CAS# | CS#

WE# | CKE# CKE# | WE#

CK CK

RDQS3 | RDQS2 RDQS2 | RDQS3 RDQS1 | RDQS0 RDQS0 | RDQS1

WDQS3 | WDQS2 WDQS2 | WDQS3 WDQS1 | WDQS0 WDQS0 | WDQS1

DM3 | DM2 DM2 | DM3 DM1 | DM0 DM0 | DM1

RESET ZQ

VREFC VREFD

23D41287QE09B

VDDQ

VDDQ#A12

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#C12

VDDQ#E1 VDDQ#E4

VDDQ#E9 VDDQ#E12 VDDQ#H12

VDDQ#H1

VDDQ#N1

VDDQ#N4

VDDQ#N9 VDDQ#N12

VDDQ#R1

VDDQ#R4

VDDQ#R9 VDDQ#R12

VDDQ#V1 VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VDD#K1

VDD#K12

VSSQ VSSQ#B4 VSSQ#B9

VSSQ#B12

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1 VSSQ#P4 VSSQ#P9

VSSQ#P12

VSSQ#T1 VSSQ#T4 VSSQ#T9

VSSQ#T12

VSSQ#M4 VSSQ#M9

VSSQ#F4 VSSQ#F9

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VSS#J12

VSS#J1 VSS#K4 VSS#K9

RFU1

RFU0

GND | VDD

3

MAB_[15..0](5,9)

CLKB0(5,9) CLKB0b(5,9)

+MVDD

R314

2.37K

1%

R318

5.49K

1%

+MVDD

R306

2.37K

1%

R312

5.49K

1%

DQB_[63..0](5,9)

+MVDD

MAB_13 MAB_15 MAB_14 MAB_12 MAB_11 MAB_10 MAB_9 MAB_8 MAB_7 MAB_6 MAB_5 MAB_4 MAB_3 MAB_2 MAB_1 MAB_0

R307 243RR307 243R

C300

C300 100nF_6.3V

100nF_6.3V

C304

C304 100nF_6.3V

100nF_6.3V

U301

DQB_24

T3

DQ31 | DQ23

DQB_27

T2

DQ30 | DQ22

DQB_26

R3

DQ29 | DQ21

DQB_25

R2

DQ28 | DQ20

DQB_30

M3

DQ27 | DQ19

DQB_29

N2

DQ26 | DQ18

DQB_31

L3

DQ25 | DQ17

DQB_28

M2

DQ24 | DQ16

DQB_15

T10

DQ23 | DQ31

DQB_12

T11

DQ22 | DQ30

DQB_13

R10

DQ21 | DQ29

DQB_14

R11

DQ20 | DQ28

DQB_8

M10

DQ19 | DQ27

DQB_10

N11

DQ18 | DQ26

DQB_9

L10

DQ17 | DQ25

DQB_11

M11

DQ16 | DQ24

DQB_4

G10

DQ15 | DQ7

DQB_6

F11

DQ14 | DQ6

DQB_7

F10

DQ13 | DQ5

DQB_5

E11

DQ12 | DQ4

DQB_3

C10

DQ11 | DQ3

DQB_0

C11

DQ10 | DQ2

DQB_2

B10

DQ9 | DQ1

DQB_1

B11

DQ8 | DQ0

DQB_17

G3

DQ7 | DQ15

DQB_16

F2

DQ6 | DQ14

DQB_18

F3

DQ5 | DQ13

DQB_19

E2

DQ4 | DQ12

DQB_21

C3

DQ3 | DQ11

DQB_23

C2

DQ2 | DQ10

DQB_20

B3

DQ1 | DQ9

DQB_22

B2

DQ0 | DQ8

+MVDD

R30360.4R R30360.4R R30260.4R R30260.4R

MAB_4

K2

A0/A10 | A4/A8

MAB_5 MAB_13

H4

A1/BA0 | A5/BA1

MAB_6

K3

A2 /A12 | A6/BA2

MAB_7

L4

A3/A11 | A7/A9

K11

A4/A8 | A0/A10

MAB_1

H9

A5/BA1 | A1/BA0

MAB_2

K10

A6/BA2 | A2/A12

MAB_3

L9

A7/A9 | A3/A11

H2

RAS# | RFM

QSB_3 QSB_1 QSB_0 QSB_2

QSBb_3 QSBb_1 QSBb_0 QSBb_2

DQMBb_3 DQMBb_1 DQMBb_0 DQMBb_2

C301

C301 10nF

10nF

+MVDD

1%

C305

C305 10nF

10nF

+MVDD

H11

G9 G4

H10

H3

J10 J11

P3 P10 D10

D3

P2 P11 D11

D2

N3 N10 E10

E3 V9 A4

J4 J9

23D41287QE09B

RFM | RAS# CS# | CAS#

CAS# | CS# WE# | CKE#

CKE# | WE#

CK CK

RDQS3 | RDQS2 RDQS2 | RDQS3 RDQS1 | RDQS0 RDQS0 | RDQS1

WDQS3 | WDQS2 WDQS2 | WDQS3 WDQS1 | WDQS0 WDQS0 | WDQS1

DM3 | DM2 DM2 | DM3 DM1 | DM0 DM0 | DM1

RESET ZQ

VREFC VREFD

RASB0b(5,9) CASB0b(5,9)

CSB0b_0(5) CKEB0(5,9)

WEB0b(5,9)

CLKB0b(5,9) CLKB0(5,9)

DRAM_RST(5,9)

VDDQ

VDDQ#A12

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#C12

VDDQ#E1 VDDQ#E4

VDDQ#E9 VDDQ#E12 VDDQ#H12

VDDQ#H1

VDDQ#N1

VDDQ#N4

VDDQ#N9 VDDQ#N12

VDDQ#R1

VDDQ#R4

VDDQ#R9 VDDQ#R12

VDDQ#V1 VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VDD#K1

VDD#K12

VSSQ VSSQ#B4 VSSQ#B9

VSSQ#B12

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1 VSSQ#P4 VSSQ#P9

VSSQ#P12

VSSQ#T1 VSSQ#T4 VSSQ#T9

VSSQ#T12

VSSQ#M4 VSSQ#M9

VSSQ#F4 VSSQ#F9

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VSS#J12

VSS#J1 VSS#K4 VSS#K9

RFU1

RFU0

GND | VDD

+MVDD A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 H12 H1 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

+MVDDC A2

VDD

A11 F1 F12 M1 M12 V2 V11 K1 K12

B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 M4 M9 F4 F9

A3

VSS

A10 G1 G12 L1 L12 V3 V10 J12 J1 K4 K9

J2 V4

SEN

J3

A9

MF

2

+MVDD A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 H12 H1 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

A2

VDD

A11 F1 F12 M1 M12 V2 V11 K1 K12

B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 M4 M9 F4 F9

A3

VSS

A10 G1 G12 L1 L12 V3 V10 J12 J1 K4 K9

J2 V4

SEN

J3

A9

MF

QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7

QSBb_0 QSBb_1 QSBb_2 QSBb_3 QSBb_4 QSBb_5 QSBb_6 QSBb_7

+MVDDC

CLKB1(5,9) CLKB1b(5,9)

In Single Rank Design: Use 60.4R (PN 316060R400G) for: R203, R202, R204, R205 R303, R302, R304, R305

+MVDD +MVDD

DQMBb_[7..0](5,9)

+MVDD

R316

2.37K

1%

R319

5.49K

1%

+MVDD

QSB_[7..0] (5,9)

QSBb_[7..0] (5,9)

+MVDD

R309

2.37K

1%

R313

5.49K

1%

DQMBb_0 DQMBb_1 DQMBb_2 DQMBb_3 DQMBb_4 DQMBb_5 DQMBb_6 DQMBb_7

RASB1b(5,9) CASB1b(5,9)

CSB1b_0(5) CKEB1(5,9)

WEB1b(5,9)

+MVDD

R30560.4R R30560.4R R30460.4R R30460.4R

CLKB1b(5,9) CLKB1(5,9)

DRAM_RST(5,9)

R310 243RR310 243R

C302

C302 100nF_6.3V

100nF_6.3V

C306

C306 100nF_6.3V

100nF_6.3V

QSB_7 QSB_6 QSB_5 QSB_4

QSBb_7 QSBb_6 QSBb_5 QSBb_4

DQMBb_7 DQMBb_6 DQMBb_5 DQMBb_4

DQB_62 DQB_61 DQB_63 DQB_60 DQB_57 DQB_59 DQB_56 DQB_58 DQB_55 DQB_54 DQB_53 DQB_52 DQB_49 DQB_51 DQB_48 DQB_50 DQB_44 DQB_46 DQB_47 DQB_45 DQB_41 DQB_43 DQB_40 DQB_42 DQB_39 DQB_34 DQB_35 DQB_33 DQB_38 DQB_32 DQB_37 DQB_36

MAB_12 MAB_14

MAB_15 MAB_8MAB_0 MAB_9 MAB_10 MAB_11

C303

C303 10nF

10nF

+MVDD

1%

C307

C307 10nF

10nF

U302

T3 T2 R3 R2 M3 N2 L3 M2

T10 T11 R10 R11 M10 N11

L10 M11 G10

F11

F10 E11 C10 C11 B10 B11

G3 F2 F3 E2 C3 C2 B3 B2

K2 H4 K3 L4

K11

H9

K10

L9 H2

H11

G9 G4

H10

H3

J10

J11

P3 P10 D10

D3

P2 P11 D11

D2

N3 N10 E10

E3

V9

A4

J4

J9

23D41287QE09B

RAS# | RFM RFM | RAS#

CS# | CAS# CAS# | CS#

WE# | CKE# CKE# | WE#

CK CK

RDQS3 | RDQS2 RDQS2 | RDQS3 RDQS1 | RDQS0 RDQS0 | RDQS1

WDQS3 | WDQS2 WDQS2 | WDQS3 WDQS1 | WDQS0 WDQS0 | WDQS1

DM3 | DM2 DM2 | DM3 DM1 | DM0 DM0 | DM1

RESET ZQ

VREFC VREFD

1

VDDQ

VDDQ#A12

VDDQ#C1 VDDQ#C4 VDDQ#C9

VDDQ#C12

VDDQ#E1 VDDQ#E4

VDDQ#E9 VDDQ#E12 VDDQ#H12

VDDQ#H1

VDDQ#N1

VDDQ#N4

VDDQ#N9 VDDQ#N12

VDDQ#R1

VDDQ#R4

VDDQ#R9 VDDQ#R12

VDDQ#V1 VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VDD#K1

VDD#K12

VSSQ VSSQ#B4 VSSQ#B9

VSSQ#B12

VSSQ#D1 VSSQ#D4 VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1 VSSQ#P4 VSSQ#P9

VSSQ#P12

VSSQ#T1 VSSQ#T4 VSSQ#T9

VSSQ#T12

VSSQ#M4 VSSQ#M9

VSSQ#F4 VSSQ#F9

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VSS#J12

VSS#J1 VSS#K4 VSS#K9

RFU1

RFU0

GND | VDD

+MVDD A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 H12 H1 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12

+MVDDC A2

VDD

A11 F1 F12 M1 M12 V2 V11 K1 K12

B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 M4 M9 F4 F9

A3

VSS

A10 G1 G12 L1 L12 V3 V10 J12 J1 K4 K9

J2 V4

SEN

J3

A9

MF

+MVDD

C363

C362

10uF_X6S

C323

C354

C216

C212

C255 100nF_6.3V

100nF_6.3V

C269

C269 1uF_6.3V

1uF_6.3V

+MVDDC

A A

B201 220R_2AB201 220R_2A

B202 220R_2AB202 220R_2A

100nF_6.3V

C272

C272 1uF_6.3V

1uF_6.3V

C214

C214 100nF_6.3V

100nF_6.3V

C230

C230 1uF_6.3V

1uF_6.3V

100nF_6.3V

C232

C232 1uF_6.3V

1uF_6.3V

C253

C253 100nF_6.3V

100nF_6.3V

C235

C235 1uF_6.3V

1uF_6.3V

C210

C209

C255

C212

C211

100nF_6.3V

C233

C234

1uF_6.3V

C217

C208

100nF_6.3V

C239

C237

1uF_6.3V

+MVDD+MVDDC +MVDD+MVDDC

5

C254

C252

100nF_6.3V

C240

C236

1uF_6.3V

C213

C256

100nF_6.3V

C231

C271

1uF_6.3V

B203 220R_2AB203 220R_2A

B204 220R_2AB204 220R_2A

C218

C218 100nF_6.3V

100nF_6.3V

C270

C270 1uF_6.3V

1uF_6.3V

C215

C215 100nF_6.3V

100nF_6.3V

C216 100nF_6.3V

100nF_6.3V

C238

C238 1uF_6.3V

1uF_6.3V

+MVDD +MVDD +MVDD +MVDD

C262

C262 10uF_X6S

10uF_X6S

C263

C263 10uF_X6S

10uF_X6S

+MVDDC

C261

C261 100nF_6.3V

100nF_6.3V

C241

C241 1uF_6.3V

1uF_6.3V

C257

C257 100nF_6.3V

100nF_6.3V

C278

C278 1uF_6.3V

1uF_6.3V

C226

C226 100nF_6.3V

100nF_6.3V

C247

C247 1uF_6.3V

1uF_6.3V

C264

C264 10uF_X6S

10uF_X6S

C265

C265 10uF_X6S

10uF_X6S

4

C221

C221 100nF_6.3V

100nF_6.3V

C243

C243 1uF_6.3V

1uF_6.3V

C228

C228 100nF_6.3V

100nF_6.3V

C248

C248 1uF_6.3V

1uF_6.3V

C222

C222 100nF_6.3V

100nF_6.3V

C244

C244 1uF_6.3V

1uF_6.3V

C219

C219 100nF_6.3V

100nF_6.3V

C250

C250 1uF_6.3V

1uF_6.3V

C266

C266 10uF_X6S

10uF_X6S

C223

C223 100nF_6.3V

100nF_6.3V

C245

C245 1uF_6.3V

1uF_6.3V

C225

C225 100nF_6.3V

100nF_6.3V

C242

C242 1uF_6.3V

1uF_6.3V

C224

C224 100nF_6.3V

100nF_6.3V

C246

C246 1uF_6.3V

1uF_6.3V

C259

C259 100nF_6.3V

100nF_6.3V

C273

C273 1uF_6.3V

1uF_6.3V

C229

C229 100nF_6.3V

100nF_6.3V

C279

C279 1uF_6.3V

1uF_6.3V

C220

C220 100nF_6.3V

100nF_6.3V

C274

C274 1uF_6.3V

1uF_6.3V

C227

C227 100nF_6.3V

100nF_6.3V

C280

C280 1uF_6.3V

1uF_6.3V

C260

C260 100nF_6.3V

100nF_6.3V

C249

C249 1uF_6.3V

1uF_6.3V

C258

C258 100nF_6.3V

100nF_6.3V

C281

C281 1uF_6.3V

1uF_6.3V

C267

C267 10uF_X6S

10uF_X6S

C251

C251 1uF_6.3V

1uF_6.3V

C268

C268 10uF_X6S

10uF_X6S

+MVDDC

C275

C275 10uF_X6S

10uF_X6S

3

C352

C352 100nF_6.3V

100nF_6.3V

C369

C369 1uF_6.3V

1uF_6.3V

C276

C276 10uF_X6S

10uF_X6S

C309

C309 100nF_6.3V

100nF_6.3V

C367

C367 1uF_6.3V

1uF_6.3V

C314

C314 100nF_6.3V

100nF_6.3V

C330

C330 1uF_6.3V

1uF_6.3V

C277

C277 10uF_X6S

10uF_X6S

C310

C310 100nF_6.3V

100nF_6.3V

C332

C332 1uF_6.3V

1uF_6.3V

C353

C353 100nF_6.3V

100nF_6.3V

C368

C368 1uF_6.3V

1uF_6.3V

C311

C311 100nF_6.3V

100nF_6.3V

C333

C333 1uF_6.3V

1uF_6.3V

C308

C308 100nF_6.3V

100nF_6.3V

C335

C335 1uF_6.3V

1uF_6.3V

C354

C312

100nF_6.3V

C334

C370

1uF_6.3V

C317

C356

100nF_6.3V

C371

C339

1uF_6.3V

+MVDD +MVDD

C377

C377 10uF_X6S

10uF_X6S

C355

C355 100nF_6.3V

100nF_6.3V

C336

C336 1uF_6.3V

1uF_6.3V

C313

C313 100nF_6.3V

100nF_6.3V

C331

C331 1uF_6.3V

1uF_6.3V

C378

C378 10uF_X6S

10uF_X6S

C316

C316 100nF_6.3V

100nF_6.3V

C340

C340 1uF_6.3V

1uF_6.3V

C315

C315 100nF_6.3V

100nF_6.3V

C337

C337 1uF_6.3V

1uF_6.3V

C379

C379 10uF_X6S

10uF_X6S

C318

C318 100nF_6.3V

100nF_6.3V

C338

C338 1uF_6.3V

1uF_6.3V

C380

C380 10uF_X6S

10uF_X6S

2

C381

C381 10uF_X6S

10uF_X6S

+MVDDC

C357

C357 100nF_6.3V

100nF_6.3V

C341

C341 1uF_6.3V

1uF_6.3V

C326

C326 100nF_6.3V

100nF_6.3V

C347

C347 1uF_6.3V

1uF_6.3V

C327

C327 100nF_6.3V

100nF_6.3V

C375

C375 1uF_6.3V

1uF_6.3V

C328

C328 100nF_6.3V

100nF_6.3V

C348

C348 1uF_6.3V

1uF_6.3V

C321

C321 100nF_6.3V

100nF_6.3V

C343

C343 1uF_6.3V

1uF_6.3V

C323

C322

100nF_6.3V

C345

C344

1uF_6.3V

C319

C325

100nF_6.3V

C350

C374

1uF_6.3V

Title

RH RV630- GDDR4 136p 256MB 128bit (Ch A & B) - Rank 0

Size Document Number Rev

C

Date: Sheet

C329

C324

100nF_6.3V

C372

C346

1uF_6.3V

C358

C358 100nF_6.3V

100nF_6.3V

C373

C373 1uF_6.3V

1uF_6.3V

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

C359

C359 100nF_6.3V

100nF_6.3V

C342

C342 1uF_6.3V

1uF_6.3V

C320

C320 100nF_6.3V

100nF_6.3V

105-B101XX-00

C376

C376 1uF_6.3V

1uF_6.3V

1

C349

C349 1uF_6.3V

1uF_6.3V

+MVDD

C360

C360 100nF_6.3V

100nF_6.3V

C361

C361 1uF_6.3V

1uF_6.3V

C364

C364 10uF_X6S

10uF_X6S

821Tuesday, April 10, 2007

C351

C351 1uF_6.3V

1uF_6.3V

C365

C365 10uF_X6S

10uF_X6S

of

C366

C366 10uF_X6S

10uF_X6S

4

www.vinafix.vn

DQA_[63..0](5,8)

D D

MAA_[15..0](5,8)

DQMAb_[7..0](5,8)

C C

CLKA0(5,8) CLKA0b(5,8)

+MVDD

B B

1%

+MVDD

MAA_13 MAA_15 MAA_14 MAA_12 MAA_11 MAA_10 MAA_9 MAA_8 MAA_7 MAA_6 MAA_5 MAA_4 MAA_3 MAA_2 MAA_1 MAA_0

5

DQA_31 DQA_28 DQA_29 DQA_30 DQA_27 DQA_26 DQA_24 DQA_25 DQA_13 DQA_12 DQA_14 DQA_15 DQA_10 DQA_11 DQA_8 DQA_9 DQA_16 DQA_17 DQA_19 DQA_18 DQA_22 DQA_21 DQA_23 DQA_20 DQA_5 DQA_6 DQA_7 DQA_4 DQA_1 DQA_0 DQA_2 DQA_3

DQMAb_0 DQMAb_1 DQMAb_2 DQMAb_3 DQMAb_4 DQMAb_5

MAA_0

DQMAb_6

MAA_1

DQMAb_7

MAA_2 MAA_3 MAA_4 MAA_12 MAA_5 MAA_6 MAA_7

RASA0b(5,8)

CSA0b_1(5) CASA0b(5,8)

WEA0b(5,8) CKEA0(5,8)

+MVDD

CLKA0b(5,8) CLKA0(5,8)

QSA_3 QSA_1 QSA_2 QSA_0

QSAb_3 QSAb_1 QSAb_2 QSAb_0

DQMAb_3 DQMAb_1 DQMAb_2 DQMAb_0

DRAM_RST(5,8) DRAM_RST(5,8)

1%

+MVDD +MVDD

+MVDD

QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7

QSAb_0 QSAb_1 QSAb_2 QSAb_3 QSAb_4 QSAb_5 QSAb_6 QSAb_7

+MVDDC +MVDDC

CLKA1(5,8) CLKA1b(5,8)

+MVDD

1%

QSA_[7..0] (5,8)

QSAb_[7..0] (5,8)

+MVDD

1%

4

DQA_54 DQA_53 DQA_55 DQA_52 DQA_50 DQA_51 DQA_48 DQA_49 DQA_33 DQA_32 DQA_34 DQA_35 DQA_37 DQA_36 DQA_39 DQA_38 DQA_60 DQA_58 DQA_56 DQA_59 DQA_61 DQA_57 DQA_62 DQA_63 DQA_44 DQA_46 DQA_47 DQA_45 DQA_42 DQA_40 DQA_41 DQA_43

+MVDD

MAA_8 MAA_9 MAA_10 MAA_11

MAA_13 MAA_14 MAA_15

RASA1b(5,8)

CSA1b_1(5) CASA1b(5,8)

WEA1b(5,8) CKEA1(5,8)

CLKA1b(5,8) CLKA1(5,8)

QSA_6 QSA_4 QSA_7 QSA_5

QSAb_6 QSAb_4 QSAb_7 QSAb_5

DQMAb_6 DQMAb_4 DQMAb_7 DQMAb_5

1%

+MVDD

+MVDDC

3

DQB_[63..0](5,8)

DQB_15 DQB_12 DQB_13 DQB_14 DQB_8 DQB_10 DQB_9 DQB_11 DQB_24 DQB_27 DQB_26 DQB_25 DQB_30 DQB_29 DQB_31

MAB_[15..0](5,8)

CLKB0(5,8) CLKB0b(5,8)

1%

+MVDD

1%

+MVDD

MAB_13 MAB_15 MAB_14 MAB_12 MAB_11 MAB_10 MAB_9 MAB_8 MAB_7 MAB_6 MAB_5 MAB_4 MAB_3 MAB_2 MAB_1 MAB_0

DQB_28 DQB_17 DQB_16 DQB_18 DQB_19 DQB_21 DQB_23 DQB_20 DQB_22 DQB_4 DQB_6 DQB_7 DQB_5 DQB_3 DQB_0 DQB_2 DQB_1

+MVDD

MAB_0 MAB_1 MAB_9 MAB_2 MAB_3

MAB_5 MAB_6 MAB_7

RASB0b(5,8)

CSB0b_1(5) CASB0b(5,8)

WEB0b(5,8) CKEB0(5,8)

CLKB0b(5,8) CLKB0(5,8)

QSB_1 QSB_3 QSB_2 QSB_0

QSBb_1 QSBb_3 QSBb_2 QSBb_0

DQMBb_1 DQMBb_3 DQMBb_2 DQMBb_0

DRAM_RST(5,8)

1%

+MVDD

2

+MVDD

QSBb_0 QSBb_1 QSBb_2 QSBb_3 QSBb_4 QSBb_5 QSBb_6 QSBb_7

QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7

DQMBb_[7..0](5,8)

+MVDD

1%

CLKB1(5,8) CLKB1b(5,8)

QSB_[7..0] (5,8)

QSBb_[7..0] (5,8)

DQMBb_0 DQMBb_1 DQMBb_2 DQMBb_3 DQMBb_4 DQMBb_5 DQMBb_6 DQMBb_7

+MVDD

1%

DQB_55 DQB_54 DQB_53 DQB_52 DQB_49 DQB_51 DQB_48 DQB_50 DQB_62 DQB_61 DQB_63 DQB_60 DQB_57 DQB_59 DQB_56 DQB_58 DQB_39 DQB_34 DQB_35 DQB_33 DQB_38 DQB_32 DQB_37 DQB_36 DQB_44 DQB_46 DQB_47 DQB_45 DQB_41 DQB_43 DQB_40 DQB_42

+MVDD

MAB_8 MAB_10

MAB_11 MAB_12MAB_4 MAB_13 MAB_14 MAB_15

RASB1b(5,8)

CSB1b_1(5) CASB1b(5,8)

WEB1b(5,8) CKEB1(5,8)

CLKB1b(5,8) CLKB1(5,8)

QSB_6 QSB_7 QSB_4 QSB_5

QSBb_6 QSBb_7 QSBb_4 QSBb_5

DQMBb_6 DQMBb_7 DQMBb_4 DQMBb_5

DRAM_RST(5,8)

1%

+MVDD

1

+MVDD

+MVDDC

1%

+MVDD

A A

+MVDD

1%

+MVDD

+MVDD +MVDD

5

+MVDD

+MVDD +MVDD

4

1%

+MVDD

3

+MVDD

+MVDD +MVDD

1%

+MVDD

2

+MVDD

+MVDD +MVDD

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630- GDDR4 136p 256MB 128bit (Ch A & B) - Rank 1

Size Document Number Rev

C

Date: Sheet

105-B101XX-00

1

of

921Tuesday, April 10, 2007

4

www.vinafix.vn

Information on Compatable Controller Parts

Gate drive voltage 5V, 8V, 12V 5V, 8V, 12V 5V only 12V only

Bootstrap diodes Internal

Phase current adjustable (unbalanced between phases) Option Pin Selection

D D

Pin 12 (COMP/DROOP) COMP COMP

Pin 16 (REFOUT/POK)

Pin 21 (VCCDRV/DROOP)

External Detection Circuit and Indication

External cable not plugged in +12V_BUS not in regulation

External cable not plugged in +12V_BUS in regulation EN1 -> 3V (by Ri1 and Ri2)

External cable plugged in +12V_XXX not in regulation

External cable plugged in 12V_EXT_DETb = "0"

C C

+12V_XXX in regulation

+12V_EXT

Overlap J1601 and C630

+12V_BUS

B B

C635

4.7uF_16V

Use16V 0805 MLCC

Mirrored on PCB

UGATE1 UGATE1

PHASE1

A A

Q603

Q603 Si7634DP

Si7634DP

LGATE1

8

PWM IC #2 PWM IC #4PWM IC #1 PWM IC #3

0.6V 0.6V 0.6V0.6VVref

(DNP D601, D611)

Yes Yes Yes TBD

IOUT/DROOP (R662)

POK (Open drain)

VCCDRV

Behaviour NotificationsCases

12V_EXT_DETb = X EN1 -> "0" (by Ri2) ENb1 -> 3.3V ENBUS = "0"

ENb1 = 0V ENBUS = "1"

12V_EXT_DETb = "0" EN1 < 3V (due to low 12V) ENb1 = 3.3V ENBUS = "0"

EN1 -> 3V ENb1 = 0V ENBUS = "1"

C630

C630 270uF_16V

270uF_16V

TH 10mm Dia

12V_EXT_DETb

- Pull-up to 3.3V when external connector is not plugged in.

- Grounded by external cable when plugged in.

L621

IND_0.47uH_7A

DUAL FOOTPRINT

C633

123

8

1

Q601

Q601 SI7682DP

SI7682DP

8

C632

C632 1UF_16V

1UF_16V

Q604

Q604 Si7634DP

Si7634DP

C633 1UF_16V

1UF_16V

LGATE1

C634

4.7uF_16V

805805 805 805

678

9

Pad

Thermal

4 5

567

9

432

Internal (DNP D601, D611)

IOUT/IMAXPin 10 (IOUT/IMAX/DROOP) IOUT IOUT/IMAX

TBD R_RT ~= 18,600,000/FswPin 11 (RT) R_RT ~= 10,000,000/Fsw TBD

DROOP (R663)

GND (SS fixed internally)

IREFOUT/POK POK voltage = 1.2V

VCCDRV

+12V_EXT

TP600TP600

+12V_BUS

Find 100nH SM Alt. IND

C621

C622

10UF_16V

12061206 12061206 603 603603 603

Mirrored on PCB

567

8

9

432

1

7

External (Populate D601, D611)

COMP

ICOMP (SS dependent on Fsw)

INREFOUT/POK PGood voltage = 1.25V

DROOP (R664)

VDDC disabled

VDDC enabled12V_EXT_DETb = "1" External Power Missing

VDDC disabled

VDDC enabled Normal Operation

+12V_EXT

402 1%

402 1% DNI

+3.3V

R668

R668 10K

10K

C690

100uF

+VDDC_Source

C623

C623 68uF_16V

68uF_16V

L601

1 2

PCMB103T-R47MS

L602

1 2

PCMB103T-R47MS

R604

2.43K

1/10W 0603

C604 100nFC604 100nF

FB_S

CSP1

7

+12V_BUS

When 12V is > 10V

EXT_12V_DETb (7)

MRP623D 0RMRP623D 0R MRP623C 0RMRP623C 0R MRP623B 0RMRP623B 0R MRP623A 0RMRP623A 0R

MRP622D 0RMRP622D 0R MRP622C 0RMRP622C 0R MRP622B 0RMRP622B 0R MRP622A 0RMRP622A 0R

MRP621D 0RMRP621D 0R MRP621C 0RMRP621C 0R MRP621B 0RMRP621B 0R MRP621A 0RMRP621A 0R

Overlap

X7R

R6051KR605 1K

CSN1

Internal (DNP D601, D611)

SSSS/ENPin 14 (SS/ICOMP)

INREFOUT/PGOOD Vrefout = 0.6V

DROOP (R664)

12V Bus power for 12V Gate Drive

+12V_BUS +12V_BUS

402

EN1 VDDC_SHDN

EN1 > 3V

+3.3V_BUS

R680

1.5K

402

R6970RR697

1%

0R

402 1% DNI

54 63 72 81

Overlap

+VDDC

Overlap

C614 100nFC614 100nF

X7R

R6151KR615 1K

CSN2

6

Pass Transistor Circuit for 8V Gate Drive

This circuit is only for 8V gate drive application

VDDC_SHDN(13)

EXT_12V_DETb_REXT_12V_DETb_R

+12V_BUS

R682

5.1K

5.1K R683 5.1KR683 5.1K

MMBT3904

1

Q678

2 3

100nF

C626

68uF_16V

OverlapOverlap

L611

12

PCMB103T-R47MS

L612

PCMB103T-R47MS

12

R614

2.43K

1/10W 0603

FB_S

CSP2

6

Choosing Different Gate Drive

5V Gate Drive R630, R670, C660,

8V Gate Drive R631, R632,

12V Gate Drive R630, C660,

Assume VCC consumes 200mA total including 5VCC providing buffered output sourcing a minimum 20mA requirement

P(Q_8VCC)max = (12V-8V)*0.2A = 800mW

32

R661

R661 10K

10K

1

SI2304DS

SI2304DS Q661

Q661

VCC

R698 0RR698 0R

+12V_BUS

EN1 VDDC_EN

R685 0RR685 0R

overlap pad

1

Q679

C636

MMBT3904

2 3

+12V_EXT

C625

C624

10UF_16V

Mirrored on PCB

678

9

Thermal

Pad

123

4 5

SI7682DP

UGATE2 UGATE2

567

8

9

Q613

Si7634DP

432

1

Populate Do Not PopulateGate Drive

R631, R632

R630, C660, R661, Q661

R670

VDDC_EN

R6670RR667 0R

SS_ICOMP

VDDC_REFIN_EN

C628

C627

1UF_16V

Q611

EN1

R661, Q661

R670

R631, R632, R661, Q661

VCCDRV

VDDC_EN (11)

C629

4.7uF_16V

Use16V 0805 MLCC

8

1

5

4.7uF_16V

Mirrored on PCB

567

9

Q614

Si7634DP

432

LGATE2LGATE2

5

1206 X5R 16V

C631

PHASE2

TP601TP601

OPTIONAL

UGATE2

C612

C612 1uF

1uF

PHASE2

LGATE2

Rdroop

Droop Option

C694

C694 1UF_16V

1UF_16V

X7R

LGATE1

603

OPTIONAL

+VDDC +VDDC

***

Overlap

H < 10 mm, SMT

+VDDC

***

Overlap

H < 10 mm, SMT

***

Overlap

H < 10 mm, SMT 8 x 8 mm, THSP/POSCAP, SMT

19

0R R6130RR613

20

21

VCC

22

0R

23

R6030RR603

PHASE1

24 25

26 27

C602

28

1uF

29

UGATE1

Populate - For 5V Gate Drive application Remove - For 8V or 12V Gate Drive application

***

MC641

MC641 1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT

***

MC642

MC642 1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT

***

4

POK > 1 used to control other on-board enables

PWRGD1

R6110RR611 0R

U601

18

uPI6201AQ

UGATE2

PHASE2

LGATE2

VCCDRV/DROOP

VCC

LGATE1

PHASE1 PGND

PGND26 PGND27 PGND28 PGND29

UGATE11BOOT125VCC3AGND4BUSEN5CSP1

R601 0RR601 0R

+VDDC

5VCC

16

17

BOOT2

REFOUT/POK

***

H < 10 mm, TH

+VDDC+VDDC

+VDDC+VDDC+VDDC

- Bulk Cap ¨C SMT, H<10mm (C641, C642, C643)

1. UCC APXE2R5ARA102MH80G, 8x7.7mm, 1000uF, 12mR, 2.5V, 4260mArms, ATI PN - ?

2. UCC APXE2R5ARA152MHA0G, 8x10mm, 1500uF, 10mR, 2.5V, 5220mArms, ATI PN - ?

***

- Bulk Cap ¨C TH, H<10mm (NC641, NC642, NC643)

1. Fujitsu FP-2R5RE102M-L8xx, 8x8mm, 1000uF, 6mR, 2.5V, 5600mArms, ATI PN - ?

***

2. Fujitsu FP-2R5RE152M-L8xx, 8x8mm, 1500uF, 6mR, 2.5V, 5600mArms, ATI PN - ?

8 x 8 mm, TH

- SP/TANT/POS Cap ¨C SMT (MC641, MC642, MC643)

1. Sanyo 2R5TPD1000M5, POSCAP, 4mmH, 1000uF, 5mR, 2.5V, 6100mArms, 4230010800G

2. NEC/TOKIN TEPSGD0E108M5-12R, SPCAP?, 3mmH, 1000uF, 5mR, 2.5V, 5477mArms, 4230010801G

+VDDC

***

C645

***

4

C645 10uf

10uf

1206 6.3V

3

5VCC

+VDDC

402

6.3V

R655

30.1K

R696

R696 300R

300R

805

C638

C638 1nF

1nF

402 10V X5R

X7R402 50V

R6361KR636 1K

Iout

X7R402 50V

TP604

TP604 TP_32mil_SM_top

TP_32mil_SM_top

Internal Reference is used when REFIN is pull-up to > 4.5V

Share Pad with R639

+VDDC

R1 RFB1

R651

5.11K

402

RFB2

R650

4.64K

402

R6620RR662 0R

Rdroop

CSP2

CSN2

CSN1

CSP1

VDDC1_REFIN

External Reference is used when

C659

C659 100nF

100nF

REFIN is driven by voltage ranged

402

from 0.4V to 3.3V

10V

VDDC_REFIN_EN

Overlap the footprints for MR655 and C655

Current

PGND Option

Compensation

Css if current

C655

comp.

47nF_16V

not

402

used

25V

SS_ICOMP

15

14

REFIN/EN

SS/ICOMP

IOUT/IMAX/DROOP

C660

C660 1uF_6.3V

1uF_6.3V

402

6.3V

Y5V

402 10V X5R

5VCC applied externally or generated internally from the IC, must be in regulation before IC start soft-start sequence.

For 5V Gate Drive application

External filtered +5V_EXT is applied to this pin

+5V

C647

C646

Y5V

10uf

6.3V

1206 6.3V

13

FB

COMP/DROOP

6

VDDC_EN

C648

Y5V

10uf

1206

3

RT

CSP2

CSN2

CSN1

Y5V

FB

12

R_RT 402

11

10

9

8

7

For 8V or 12V Gate Drive application

+5VCC is generated internally and this is an output with 20mA minimum current capability

+5V_OUT

2

VDDC1_FB

FB_S

Type III compensation

R3

402

C3

402

X7R 50V

COMP_FB

Rdroop

X7R

Droop Option

10V

Iout (13)

Vin (power stage)

Vout 1.2V

Vout ripple (DC) TBD

Iout

Step load TBD

Protections

2

1

VDDC1_FB (13)

COMP_GND

R6570RR657 0R

R2

R652

R652 10K

10K

402

C2 C1

C652

C651

10nF

33pF_50V

402

VID0(11,13) VID1(11,13) VID2(11,13) VID3(11,13) VID4(11,13)

VREF

Reference Voltage Outputs

TBD

Place these parts close to the regulators that use the references

1.8V_REF VDDC1_REFIN

+5V

402 10V X5R

VID[4:0] to control VDDC1 Voltage.

SMPS03 Specifications

Title

Title Size Document Number Rev

Size Document Number Rev

Custom

Date: Sheet of

;

Nominal Value Adjustable range / Notes

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

RH RV630 - VDDC SMPS03

Tolerance

12V +/-8% PCIe ATX12V ver. 2.2 +/-5%

;

+2.5%/-2.5%

;

TBD 55A (target 60A) max

TBDVout ripple (AC)

TBDSwitching Freq. 50kHz ~ 1MHz

105-B101XX-00

0.8V ~ 1.5V

10 21Tuesday, April 10, 2007

1

4

www.vinafix.vn

5

+3.3V_BUS

INTERFACE INFO: SMBUS SLAVE Clock: Min 10kHz - Max 100kHz 8 bit address:

- Reading 1110 0[BUS_ADD1][BUS_AADD0]1

- Writing 1110 0[BUS_ADD1][BUS_AADD0]0

DDC3DATA(3,13,18)

DDC3CLK(3,13,18)

D D

VID0

VID0(10,13)

VID1

VID1(10,13)

VID2

VID2(10,13)

VID3

VID3(10,13)

VID4

VID4(10,13)

VID5

VID5(13)

VDDC_EN(10)

VAMP_OUT1

VAMP_OUT2

C C

DNI

IN_UVLO

10.2V UVLO

VDDC_EN

DNI

+VDDC_Source

14.4V OVLO

SD

SC

VAMP_OUT1 VAMP_OUT2 VAMP_IN

VID_SEL

VR 10.X

402 10V X5R

VAMP_IN

IN_OVLO

+VDDC_VDD

SLWCLK

IREPORT

ADC_BIAS

DR_COMP

FREQ

OCS_BIAS

IN_UVLO

4

VDDC REGULATOR 55A MAXIMUM CURRENT

DBO_M DBO_S5

VDDC_IDES_P

SPHASE

0.5%

IN_OVLO

VDDC_IDES_N

DIFF PAIR

SENSE+ SENSE-

DIFF PAIR

PWRGD2

VDDC_IDES_P VDDC_IDES_P_S1 VDDC_IDES_N

+3.3V_BUS

VDDC_IDES_P

DBO_M DBO_S1

TP602TP602

Option for current unbalance

SPHASE

+3.3V_BUS

DBO_S1 DBO_S5

SPHASE

3

Option for current unbalance

+3.3V_BUS

VDDC_IDES_N_S1

VDD_PHASE0

VDDC_IDES_P_S0 VDDC_IDES_N_S0VDDC_IDES_N

VDDC_SPHASE0

VDDC_FAULT#

VDD_PHASE1

VDDC_SPHASE1

VDDC_FAULT#

DNI

VT1135S

DNI

2

BST_SPHASE0

Use16V 0805 MLCC

Mirrored on PCB

VDDC_PHASE1

BST_SPHASE1

805

Use16V 0805 MLCC

Mirrored on PCB

VDDC_PHASE0

805805

SENSE+ SENSE-

603 603

603

1

+VDDC_Source

SENSE+_R SENSE-_R

+VDDC

DNI DNI

603805

+VDDC

+12V_EXT

VT1135S

VDDC_FAULTb (13)

+VDDC

VDDC_PHASE0

VDDC_PHASE1

- VU602 overlap with VU604

- VU603 overlap with VU605

DNI

VDDC_PHASE0

+3.3V_BUS +3.3V_BUS

B B

VDD_PHASE0

VDDC_IDES_P_S0 VDDC_IDES_N_S0

DBO_M DBO_S1

VDDC_SPHASE0

VDDC_FAULT#

A A

5

BST_SPHASE0

+VDDC_Source

VDD_PHASE1

VDDC_IDES_P_S1 VDDC_IDES_N_S1

DBO_S1 DBO_S5

VDDC_SPHASE1

VDDC_FAULT#

4

VDDC_PHASE1

+VDDC

BST_SPHASE1

+12V_EXT

3

+VDDC

2

Place near VL601

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - VDDC SMPS04

Size Document Number Rev

Custom

Date: Sheet

+VDDC

105-B101XX-00

1

4

of

11 21Tuesday, April 10, 2007

www.vinafix.vn

8

7

6

5

4

3

+MVDDC_S_IN

2

1

Thermal

Pad

+MVDDC_S

9

6 7 8

CAP CER 10UF 20% 16V X5R (1206)1.8MM H MAX

Place Rs and Cs across QL

RC snubber values shown are for reference only, tuning is required

MVDDC_FB

C715

C715 10UF

10UF

on PCB

L701 1.7UHL701 1.7UH

1 2

1210 1%

402 X7R 25V

C716

C716 10UF

10UF

12061206

Rs

Cs

C717

4.7uF_16V

805

Use16V 0805 MLCCMirrored

Mirrored on PCB

MULTI FOOTPRINT

C713

3.3nF_50V

402 10%

R1

RFB1

R711

R713

10K

1.5K

402

1%

5%

R4

Place R1 and R4 close to

RFB2

PWM and

R710

routed with

7.15K

separate

402

20mil trace to

1%

the ASIC

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

C719

4.7uF_16V

805

16V X7R

TAN LP 25mOHM

C718

C718 150nF_16V

150nF_16V

603

TAN LP 25mOHM

Overlap

***

1210

***

Find 100nH SM Alt. IND

+MVDD

TAN LP 25mOHM

OverlapOverlap

+MVDD +MVDD +MVDD+MVDD

***

H < 10 mm, SMT 8 mm Dia

***

Find 470uF, Low ESR, H<=10 mm, TH/SMT

C730

68uF_16V

Overlap

***

1210

***

C725

C725 820uF_2.5V

820uF_2.5V

***

8 x 8 mm, THSP/POSCAP, SMT

Find 16V Part

Q701

QH

+PW_MVDDC_HGD

D D

C703

0.22uF

MVDD_EN (14)

402

+PW_MVDDC_LGD

+PW_MVDDC_M

R722 0RR722 0R

603

+PW_MVDDC_LGDR

+MVDDC_B

U703

1

+PW_MVDDC_HGD

+PW_MVDDC_LGD

List of supported foodprint The following ICs are not necessarily evaluated by

AMD, please refer to BOM for evaluation status

C C

place R715 close to IC pin4

ANPEC APW7120/APW7065 (12V) CAT CAT7583 (12V) INTERSIL ISL6545 NEXSEM NX2114/2307 RICHTEK RT9214/RT8101 OnSemi ON1582 uPI UP6101 (No Ext_Vref in) uPI UP6103 (with Ext_Vref in, can use voltage console UP6261 to change Vout)

BOOT

2

UGATE

3

GND LGATE4VCC

NX2124CSTR

PHASE

COMP

+PW_MVDDC_M

8

MVDDC_COMP

7

MVDDC_FB

6

FB

5

+MVDD_VCC

R721 0RR721 0R

+PW_MVDDC_HGDR

402

QL

4 5 3 2 1

Q702

Thermal

Si7634DP

Pad

MVDDC_FB(13)

4 5 3 2 1

SI7682DP

9

6 7 8

SMPS02- Regulator for MVDD

+PW_MVDDC_HGDR

B B

Layout guideline for Nexsem NX2114/2307

1-Position the controller (U703) such that LGate(pin4) is the closet to gate of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as short and as wide as possible to reduce the trace inductance. 2-Place the bypass capacitors for Vcc as well as Boost caps as close to the controller as possible. They are as follows; Vcc bypass cap is C703, and Boost cap is C705. 3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place the rest of the compensation network close to the pins 7 and 6. These are R710, R711, R713, C713 and R712, C711 and C712.

+PW_MVDDC_M

+MVDDC_S

+PW_MVDDC_LGDR

MULTI FOOTPRINT

COMPENSATION CIRCUIT FILTERED SMPS VCC BOOT CIRCUIT

+12V_BUS

+5V

R7060RR706 0R

402

D701

D701 BAT54A

BAT54A

+MVDDC_B

402

C706

C706 150nF_16V

150nF_16V

+PW_MVDDC_M

5

4

3

402

A A

C711

6.8nF_25V

402

10V 10%

R712

R712 10K

10K

402 1%

MVDDC_COMP

C712

C712 100pF_50V

100pF_50V

603

50V

NPOX7R

5%

R714 0RR714 0R

share pad of R714,R709

8

402 X5R

MVDDC_FB

+12V_BUS

10V 10%

+MVDD_VCC

7

+5V

MR707

2.2R

603 X7R 5%

1

3

C705

C705 100nF

100nF

603 X7R 5%

6

2

16V

Vout = 1.8V ~ 2.85V

Part RFB2RFB1

0.8V Ref

SMPS02 Specifications

Vin 12V(power stage) +/-8% PCIe ATX12V ver. 2.2 +/-5%

Vout 2V

Vout ripple (DC) 50mVpp

Iout 6Aavg, 8Adc_max

Step load 3Amax

Protections

Vout

2.03V (1.98V~2.08V)

+/-10% or 200mVpp @ 3A step loadVout ripple (AC)

Title

Title Size Document Number Rev

Size Document Number Rev

Custom

Date: Sheet

2

4.99K p/n 3160499100G

Nominal Value Adjustable range / Notes

RH RV630 - MVDD SMPS02

Tolerance

;

+2%/-2%

;

~300kHzSwitching Freq. TBD

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

1.8V ~ 2.85V

105-B101XX-00

3.24K p/n 3160324100G

12 21Tuesday, April 10, 2007

1

of

4

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5

DDC3DATA

DDC3DATA(3,11,18)

DDC3CLK

DDC3CLK(3,11,18)

+3.3V_BUS

D D

CUR_ADJ_0 CUR_ADJ_1

DCC to control VDDC1 and MVDD Voltage.

+3.3V_BUS

DDC3DATA DDC3CLK

I2C Debugging Header for testing purpose

C C

132For Testing purposes only

DNI

10x Buffered VDDC Output Current Monitoring

+12V_BUS

Place caps very close to power pin

603

X7R

Iout(10)

X7R

402

50V

X7R

1%

12V Supply Voltage single Op-Amp (U611) :

1. National LM321, SOT23-5, ATI PN - TBD

2. TI alternate? ATI PN - TBD

1%

TP603

TP603 TP_32mil_SM_top

TP_32mil_SM_top

4

VDDC1_FB (10) MVDDC_FB (12)

3

VDDC_FAULTb

+3.3V_BUS

+3.3V

R1251

10K

CTFb(7)

+3.3V_BUS

+3.3V

VDDC_FAULTb (11)

VDDC_SHDN

Not intended for production

When LED is off there is a fault

VDDC_SHDN (10)

+3.3V_BUS

POWER_SHDN (14)

+3.3V_BUS

PWRCNTL_0(7)

PWRCNTL_1(7)

VID Settings Using GPIO (see BOM for qulified voltage settings, below values are only samples to show the config)

See BOM foe qualified option.

2

R1240

R1240 10K

10K

R1241

R1241 10K

10K

+3.3V_BUS

VID3

VID4

1

001 1.150V

0

1

VID2

0

1

Output Voltage GPIO_20 GPIO_15

VID CODE SET FOR +VDDC = 1.2V

DNI DNI DNI DNI DNI

+3.3V

PWRCNTL_1 PWRCNTL_0

0

01 110 1.250V

10

101

132VID ~ Vout Setting for VDDC

0.950V

1.050V

+3.3V_BUS

PWRCNTL_0_B

PWRCNTL_1_B

DNI

1

Power-up Default

VID4 (10,11)

VID2 (10,11)

VID3 (10,11)

VID0

VID0 (10,11)

VID1

VID1 (10,11)

VID2

VID2 (10,11)

VID3

VID3 (10,11)

VID4

VID4 (10,11)

VID5

VID5 (11)

B B

+12V_BUS +12V_EXT

DUAL FOOTPRINT

Option

Normal Operation

Option #1

External cable plugged in

Populate:

A A

B701 D702

Power On When

D703

External cable not plugged in

Normal Operation

Option #2

External cable plugged in Populate: B702

Power On When

External cable not plugged in

5

SMPS Input Switch Circuit

+MVDDC_S_IN

FDS6675, -10A, -30V, SO-8 (2020002200) Alt. FDS7779Z, -16A, -30V, SO-8 (2020013800)

DNI

Alt. HAT1072H, -40A, -30V, LFPAK (2020013900)

Put copper area under Q1230/1231 for heat dissipation.

VDDC, MVDD SMPS Input Options

VDDC Input MVDD InputCases

Phase 1 powered from +12V_BUS Phase 2 powered from +12V_EXT

Powered from +12V_EXT

Powered from +12V_BUS

Powered from +12V_BUS Board works properly

Powered from +12V_BUS Bootup to Dos warning

+12V_BUS

+12V_EXT

8 1

6 3

7 2

5 4

RP1200A 0RRP1200A 0R

RP1200B 0RRP1200B 0R

RP1200C 0RRP1200C 0R

Status

Board works properly

Bootup to Dos warning Message Screen

Message Screen

+VDDC_Source

8 1

6 3

7 2

5 4

+MVDDC_S

RP1201A 0RRP1201A 0R

RP1201B 0RRP1201B 0R

RP1201C 0RRP1201C 0R

RP1200D 0RRP1200D 0R

RP1201D 0RRP1201D 0R

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - Power Management

Size Document Number Rev

Custom

Date: Sheet of

4

3

2

Date: Sheet of

105-B101XX-00

1

4

13 21Tuesday, April 10, 2007

4

www.vinafix.vn

8

+VDDC

+12V_BUS

R843

5.1K

DNI

LDO2_POK

5%

Q840

1

MMBT3904

2 3

POWER_SHDN(13)

+3.3V

R899

5.1K

R8411KR841 1K

D D

C841

C841 1uF_6.3V

1uF_6.3V

R844 5.1KR844 5.1K

DNI

R846 5.1KR846 5.1K

5%

7

+5V

5.1K

5.1K R845

R845

Q841

1

MMBT3904

2 3

Q842

1

MMBT3904

2 3

OSC_EN (3,17)

RTAVDD_ENb (3,17)

LDO3_EN LDO2_EN LDO5_EN

MVDD_EN (12)

6

Power up Sequencing

+1.8V

R847 10KR847 10K

C844

100nF_6.3V

5

+12V_BUS

R848

R848 100K

100K

Q843

1

2 3

MMBT3904

1

2 3

R849

R849 10K

10K

Q844

Q844 MMBT3904

MMBT3904

C843

C843 100NF

100NF

402 X5R 16V

4

+3.3V_BUS

C842

C842 10uF_X6S

10uF_X6S

Install only one of these

Q845

Q845 BSH111

BSH111

3 2

1

3

+3.3V

LVT_EN (3)

R840

R840 100K

100K

2

1

Regulators for +5V, +5V_VESA and +5V_VESA2

+12V_BUS

R812

R812 47R

47R

1206

0805

1206

1/4W

1/8W

5%

C810

C810 100nF

100nF

0603 16V

Vout(V) = Vref (1+R2/R1)

0805

1/4W

1/8W

U810

1

VIN

5

NC

8

NC#8 ADJ4VOUT

LM317LCDR

VOUT#2 VOUT#3 VOUT#6

2 3

R813

6

499R

7

0402

R1

1uF_6.3V

R814

1.5K

0402

R2

+5V_VESA

C811

LDO #6: PCB: 50 to 70mm sq. copper area for cooling

C C

+MVDD

LDO5_VIN

1206 Use 0R

LDO5_EN

LDO #2: Vout = +1.8V +/- 2%

Vin = 2.1V to 3.6V MAX Iout = 0.8A (TBV) RMS MAX

+5V

DNI

Iout = 1.5A (TBV) RMS MAXVout = +1.25V +/- 2%Vin = 1.6V to 2.1V MAX

+VDDCI_LDO

LDO5_FB

VOUT = Vref x (1 + R5/R4)

0402

0.1%

R5

C3

R4

+VDDCI_LDO

DNIDNI

+12V_BUS

R822

R822 47R

47R

1206

0805

1/4W

5%

C820

C820 100nF

100nF

0603 16V

1206 0805

1/8W

5%

Vout(V) = Vref (1+R2/R1)

U820

1

VIN

5

NC

8

NC#8 ADJ4VOUT

LM317LCDR

VOUT#2 VOUT#3 VOUT#6

+5V_VESA2

2 3

R823

6

499R

7

0402

R1

C821

1uF_6.3V

R824

1.5K

0402

R2

PCB: 50 to 70mm sq. copper area for cooling

+3.3V_BUS +1.8V+5V +1.8V

R868

LDO2_VIN

1206

LDO2_POK

0.50R

Use 0.5R

B B

LDO #3: Vout = +1.1V +/- 2%

LDO2_EN

C866

10uF_X6S

Vin = +1.45V to 2.1VMAX Iout = 1.1A (TBV) RMS MAX

C868

C868 1uF_6.3V

1uF_6.3V

U861

1

POK

2

EN

3

VIN CNTL4REFIN

uP7706U8

GND#8

VOUT

GND#9

R865

12.7K_0.1%

8 7

FB

6 5

DNI

9

LDO2_FB

12.7K_0.1%

R864

R864 10K_0.1%

10K_0.1%

0.1%

R5

R4

C865

C865 33pF_50V

33pF_50V

C3

C861

C864

10uF_X6S

100nF

DNIDNI

100nF

VOUT = Vref x (1 + R5/R4)

PCB: 50 to 70mm sq. copper area for cooling

R8580RR858

+MVDD

A A

1206 Use 0R

LDO3_VIN

0R

LDO3_EN

C856

10uF_X6S

C858

C858 1uF_6.3V

1uF_6.3V

U851

1

POK

2

EN

3

VIN CNTL4REFIN

uP7706U8

GND#8

VOUT

GND#9

8 7

FB

6 5 9

+1.1V+5V +1.1V

LDO3_FB

DNI

VOUT = Vref x (1 + R5/R4)

R855

3.92K_0.1%

R5

R854

R854 10K_0.1%

10K_0.1%

0.1%

R4

C855

C855 33pF_50V

33pF_50V

C3

C851

C854

10uF_X6S

100nF

DNIDNI

100nF

+12V_BUS

R832

R832 47R

47R

1206

1/4W

5%

C830

C830 100nF

100nF

0603 16V

0805

1/8W

5%

1206

1/4W

5%

Vout(V) = Vref (1+R2/R1)

0805

1/8W

5%

U830

1

VIN

5

NC

8

NC#8 ADJ4VOUT

LM317LCDR

VOUT#2 VOUT#3 VOUT#6

+5V

2 3

R833

6

499R

7

0402

R1

C831

1uF_6.3V

R834

1.5K

0402

R2

Shared Power Rails

+1.8V +AVDD

B882

B882 BLM15BD121SN1

BLM15BD121SN1

8

+A2VDDQ

B883

B883 BLM15BD121SN1

BLM15BD121SN1

+VDD1DI +VDD2DI +DPLL_PVDD +TPVDD +TXVDDR +T2PVDD

B884

B884 BLM15BD121SN1

BLM15BD121SN1

7

B885

B885 BLM15BD121SN1

BLM15BD121SN1

B886

B886 BLM15BD121SN1

BLM15BD121SN1

B887

B887 BLM15BD121SN1

BLM15BD121SN1

6

B888

B888 BLM15BD121SN1

BLM15BD121SN1

B889

B889 BLM15BD121SN1

BLM15BD121SN1

5

4

www.vinafix.vn

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - Linear Regulators

Size Document Number Rev

C

Date: Sheet

3

Date: Sheet

2

105-B101XX-00

4

of

14 21Tuesday, April 10, 2007

1

8

7

6

5

4

3

2

1

10R

402

L10040RL1004

0R

L10050RL1005

0R

L10060RL1006

0R

DDCCLK_DAC1_R

HSYNC_DAC1_R

VSYNC_DAC1_R

A_R_DAC1_F A_G_DAC1_F A_B_DAC1_F

DDCDATA_DAC1_R DDCCLK_DAC1_R HSYNC_DAC1_R

VSYNC_DAC1_R

HPD2(7)

L1001

A_DAC1_R(3)

R1027

A_DAC1_RB(3)

A_DAC1_G(3)

D D

C C

B B

A_DAC1_GB(3)

A_DAC1_B(3)

A_DAC1_BB(3)

CRT1DDCDATA(3)

CRT1DDCCLK(3)

C1999 100nF_6.3VC1999 100nF_6.3V

HSYNC_DAC1(3,7)

VSYNC_DAC1(3,7)

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

R1027

37.4R

R1028

37.4R

R1029

37.4R

+3.3V

+3.3V +5V

+5V

14

2 3

U1999A

U1999A 74VHC125

74VHC125

1

7

4

74VHC125

74VHC125 U1999B

U1999B

5 6

R1001

R1001 75R

75R

402

R1002

R1002 75R

75R

402

R1003

R1003 75R

75R

Pseudo differential RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane.

1

R1004

R1004 10K

10K

R1007

R1007 10K

10K

1

HSYNC_DAC1_B

VSYNC_DAC1_B

32

BSH111

BSH111 Q1001

Q1001

32

BSH111

BSH111 Q1002

Q1002

L1001

47nH

402

L1002

47nH

402

L1003

47nH

402

+5V

R1005

4.7K

DDCDATA_DAC1_5V DDCDATA_DAC1_R

R1008

4.7K

DDCCLK_DAC1_5V

A_R_DAC1_M

402

A_G_DAC1_M

402

A_B_DAC1_M

402402

R1006 33RR1006 33R

R1009 33RR1009 33R

R1010

R1011

For ESD ProtectionSee BOM for qualified filters

Q1021

MMBT3904

+3.3V

2 3

R1023

R1023 10K

10K

R1022 10KR1022 10K

1

+3.3V

T2X2M(3) T2X2P(3)

T2X4M(3) T2X4P(3)

T2X1M(3) T2X1P(3)

T2X3M(3) T2X3P(3)

T2X0M(3) T2X0P(3)

T2X5M(3) T2X5P(3)

T2XCP(3) T2XCM(3)

+5V_VESA

DDCCLK_DAC1_R DDCDATA_DAC1_R VSYNC_DAC1_R

HPD_DVI2

A_R_DAC1_F A_G_DAC1_F A_B_DAC1_F HSYNC_DAC1_R

+5V_VESA

DDC2_MONID0 DDC2_MONID1(SDA) DDC2_MONID2 DDC2_MONID3(SCL)

603

DB15 pin

Standard VGA Monitor ID bit 0

11

Monitor ID bit 1

12

Monitor ID bit 2

4

Monitor ID bit 3

15

N/C

9

Mechanical Key Hardware Support

No Yes Yes No Yes

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA

25

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C1 C2 C3 C4 C5 C6

26 27 28 29 30

DDC1 Host Monitor ID bit 0

Data from display Monitor ID bit 2 Open +5V 50mA min 1A max

J1001

CASE TMDS Data2-

TMDS Data2+ TMDS Data2/4 Shield TMDS Data4TMDS Data4+ DDC Clock DDC Data Analog VSYNC TMDS Data1TMDS Data1+ TMDS Data1/3 Shield TMDS Data3TMDS Data3+ +5V Power GND (for +5V) Hot Plug Detect TMDS Data0TMDS Data0+ TMDS Data0/5 Shield TMDS Data5TMDS Data5+ TMDS Clock Shield TMDS Clock+ TMDS Clock-

Analog Red Analog Green Analog Blue Analog HYNC Analog GND Analog GND#C6

CASE#26 CASE#27 CASE#28 CASE#29 CASE#30

DVI_CONNECTOR

DDC2B or DDC2B+ Host Monitor ID bit 0 SDA Monitor ID bit 2 SCL +5V 50mA min 1A max

DDC2AB Host Monitor ID bit 0

SDA Monitor ID bit 2 SCL +5V 300mA min 1A max

DDC1/2 Display Optional

SDA Optional SCL

Optional

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - DAC1/TMDS2

Size Document Number Rev

Custom

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B101XX-00

4

of

15 21Tuesday, April 10, 2007

1

www.vinafix.vn

8

7

6

5

4

3

2

1

See BOM for qualified filters

L2001

A_DAC2_R(3)

R2027

A_DAC2_RB(3)

A_DAC2_G(3)

D D

A_DAC2_GB(3)

A_DAC2_B(3)

A_DAC2_BB(3)

R2027

37.4R

R2028

37.4R

R2029

37.4R

R2001

R2001 75R

75R

402

R2002

R2002 75R

75R

402

R2003

R2003 75R

75R

L2001

47nH

402

L2002

47nH

402

L2003

47nH

402

Pseudo differential RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane.

A_R_DAC2_M

402

A_G_DAC2_M

402

A_B_DAC2_M

402402

L20040RL2004

0R

L20050RL2005

0R

L20060RL2006

0R

A_R_DAC2_F A_G_DAC2_F A_B_DAC2_F

DDCDATA_DAC2_R DDCCLK_DAC2_R

+3.3V

HSYNC_DAC2_R VSYNC_DAC2_R

+5V_VESA2

For ESD Protection

603

+5V_VESA2

DDC2_MONID0 DDC2_MONID1(SDA) DDC2_MONID2 DDC2_MONID3(SCL)

+3.3V

R2004

R2004 10K

C C

B B

CRT2DDCDATA(3)

CRT2DDCCLK(3)

HSYNC_DAC2(3,7)

VSYNC_DAC2(3,7)

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

10K

+3.3V +5V

R2007

R2007 10K

10K

9 8

U1999C

U1999C 74VHC125

74VHC125

10 13

74VHC125

74VHC125 U1999D

U1999D

12 11

1

32

BSH111

BSH111 Q2001

Q2001

1

32

BSH111

BSH111 Q2002

Q2002

HSYNC_DAC2_B

VSYNC_DAC2_B

+5V

R2005

4.7K

402

DDCDATA_DAC2_5V DDCDATA_DAC2_R

R2008

4.7K

402 402

DDCCLK_DAC2_5V

R2010

R2011

R2006 33RR2006 33R

R2009 33RR2009 33R

402

HSYNC_DAC2_R

10R

402

VSYNC_DAC2_R

10R

HPD1(3)

DDCCLK_DAC2_R

Q2021

MMBT3904

+3.3V

2 3

R2023

R2023 10K

10K

R2022 10KR2022 10K

1

T1X2M(3) T1X2P(3)

T1X4M(3) T1X4P(3)

T1X1M(3) T1X1P(3)

T1X3M(3) T1X3P(3)

T1X0M(3) T1X0P(3)

T1X5M(3) T1X5P(3)

T1XCP(3) T1XCM(3)

DDCCLK_DAC2_R DDCDATA_DAC2_R VSYNC_DAC2_R

HPD_DVI1

A_R_DAC2_F A_G_DAC2_F A_B_DAC2_F HSYNC_DAC2_R

DB15 pin

Standard VGA Monitor ID bit 0

11

Monitor ID bit 1

12

Monitor ID bit 2

4

Monitor ID bit 3

15

N/C

9

Mechanical Key Hardware Support

No Yes Yes No Yes

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA2

DDC1 Host Monitor ID bit 0

Data from display Monitor ID bit 2 Open +5V 50mA min 1A max

25

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C1 C2 C3 C4 C5 C6

26 27 28 29 30

DDC2B or DDC2B+ Host Monitor ID bit 0 SDA Monitor ID bit 2 SCL +5V 50mA min 1A max

J2001

CASE TMDS Data2-

TMDS Data2+ TMDS Data2/4 Shield TMDS Data4TMDS Data4+ DDC Clock DDC Data Analog VSYNC TMDS Data1TMDS Data1+ TMDS Data1/3 Shield TMDS Data3TMDS Data3+ +5V Power GND (for +5V) Hot Plug Detect TMDS Data0TMDS Data0+ TMDS Data0/5 Shield TMDS Data5TMDS Data5+ TMDS Clock Shield TMDS Clock+ TMDS Clock-

Analog Red Analog Green Analog Blue Analog HYNC Analog GND Analog GND#C6

CASE#26 CASE#27 CASE#28 CASE#29 CASE#30

DVI_CONNECTOR

DDC2AB Host Monitor ID bit 0

SDA Monitor ID bit 2 SCL +5V 300mA min 1A max

DDC1/2 Display Optional

SDA Optional SCL

Optional

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - DAC2/TMDS1

Size Document Number Rev

Custom

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B101XX-00

4

of

16 21Tuesday, April 10, 2007

1

www.vinafix.vn

8

D D

7

+RTAVDD

6

5

402 402 402 402 402402 402 402

+3.3V

4

3

CompIn_R

LumaIn_R ChromaIn_R

CompIn

LumaIn ChromaIn

2

PIN6 DAC2_Y_DIN

DAC2_C_DIN DAC2_COMP_DIN

1

CompIn_R

LumaIn_R

C C

ChromaIn_R

B B

+RTAVDD

1206

402

1206

402

1206

402

As close as possible to pin 56 of Rage Theater

402

RTXTALIN(3)

PERST#_buf(1,2)

GND_VIN

402

NS3201 NS_VIANS3201 NS_VIA

Regulator for +RTAVDD Vout = 3.3V

+12V_BUS

0402

1/10W

RTAVDD_ENb(3,14)

A A

8

0603

0805

1206

1/4W

1/8W

5%

0603 16V

Vout(V) = Vref (1+R2/R1)

7

402

VADCFILTERVADCFILTER

402

VIPCLK (7)

5%

VADCFILTER VADCFILTER

12

402 5%

Place near connector 0R leaves footprint for Ferrite Beads if req'd for EMI

402 1%

Place near U3201 Install it only if RTCLK is used. R3119 + MR81 = 182R

5%

Please close to RT

DAC2_C_F DAC2_COMP_F

+3.3V

402 1%

VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6 VID_7

5%

Install for Dell

GENERICA_R(7)

R3004 0RR3004 0R R3005 0RR3005 0R R3006 0RR3006 0R

DNI for Dell

0805

1206

1/4W

1/8W

5%

6

R1

R2

+RTAVDD

**

ALT

DUAL FOOTPRINT

CAP CER 10UF 10% 6.3V X6S (0805)1.4MM MAX THICK

5

**

ALT

DUAL FOOTPRINT

CAP CER 10UF 10% 6.3V X6S (0805)1.4MM MAX THICK

4

VPHCTL (7)

VHAD_0 (7)

VHAD_1 (7)

A_DAC2_Y(3)

R3001

R3001 75R

402402 1%5%

RTCLK (3)

VID_[7..0] (7)

VPCLK0 (7)

402

STV/HDTV#_DET PIN6

402

DAC2_Y_DINDAC2_Y_F

402

DAC2_C_DIN

402

DAC2_COMP_DIN

+3.3V

The 7-pin MiniDIN footprint allows one of the two MiniDINs:

- 7-pin Svideo/Composite MiniDIN P/N 6071001500G

- 4-pin Svideo MiniDIN P/N 6070001000G

A_DAC2_C(3)

A_DAC2_COMP(3)RTXTALOUT(3)

Install for Dell

R3008

R3008 10K

10K

402 402

R3009 0RR3009 0R

402402 402

3

75R

R3002

R3002 75R

75R

R3003

R3003 75R

75R

402

R30070RR3007 0R

402

DNI for Dell

Title

Title Size Document Number Rev

Size Document Number Rev

Size Document Number Rev Date: Sheet

Date: Sheet

2

L3001 470nH_250mAL3001 470nH_250mA

C3001

C3001 47pF_50V

47pF_50V

L3002 470nH_250mAL3002 470nH_250mA

C3002

C3002 47pF_50V

47pF_50V

L3003 470nH_250mAL3003 470nH_250mA

C3003

C3003 47pF_50V

47pF_50V

Install for Dell only when it's needed for EMI

402

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

RH RV630 - RageTheater & TVO/VIVO

C

Overlap with Rpin5

DAC2_Y_F

C3004

C3004 47pF_50V

47pF_50V

DAC2_C_F

C3005

C3005 47pF_50V

47pF_50V

DAC2_COMP_F

C3006

C3006 47pF_50V

47pF_50V

TV Out

J3001

6

HDTV_OUT_DET#

3

Y-OUT

4

C-OUT

7

Comp_out

CompIn

5

SYNC

1

GND

2

GND#2

8

Rpin5

CASE

9

CASE#9

10

CASE#10

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

105-B101XX-00

4

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17 21Tuesday, April 10, 2007

1

www.vinafix.vn

8

7

6

5

4

3

2

1

External thermal sensor is for testing, and will not be populated in production.

+3.3V +3.3V

C4002

C4003

1uF_6.3V

SMBCLK SMBDAT ALERT GND5PWM

VDD

D+

C4003

100pF_50V

D-

1 2 3 4

TS_FDO

R4004

R4004 10K

10K

LM63_PWM

C4004

2.2nF_50V

GPU_DPLUS

GPU_DMINUS

GPU_DPLUS (3)

GPU_DMINUS (3)ThermINT(7)

+12V_BUS

B4001

26R_600mA

Share one pad Place them on the bottom

R4005 10KR4005 10K

For fan with 3.3V PWM (bypass) install 0R

PWM

C4001

R4032

R4003

2.61K

10K

D D

DDC3CLK(3,11,13)

DDC3DATA(3,11,13)

TS_FDO(3)

R4001 100RR4001 100R R4002 100RR4002 100R R4015 0RR4015 0R

DNI

SCL_R SDA_R TINT_R

C4001 10uF_X6S

10uF_X6S

U4001

8 7 6

LM63CIMAX

Warning: TS_FDO is not 5V tolerant. MAX sink current 1.65mA

For 2-WIRE FAN

R40140RR4014 0R

402

+5V

MR40061KMR4006

For 4-WIRE

C C

FAN

1K

Share one PAD

+12V_BUS

1%

For 4-WIRE FAN

C4008

C4008 1uF

1uF

0805 16V

1

805 16V Y5V

+5V

Q4030

Q4030 MMBT3904

MMBT3904

2 3

RV630_FANSINK

RV630_FANSINK H1C

H1C

17181920212223

DNI (bypass for fan with 3.3V PWM)

RV630_FANSINK

RV630_FANSINK H1D

H1D

24

25262728293031

32

TACH

DNI

RV630_FANSINK

RV630_FANSINK H1E

H1E

33343536373839

Header is 2mm, and it does not follow

2.54mm spacing as 4-pin PWM Fan Specification

4

DNI

RV630_FANSINK

RV630_FANSINK H1F

H1F

41424344454647

40

48

3 2

J4030

1

1X4 3A 2MM

Overlap MJ4030 and J4030

RV630_FANSINK

RV630_FANSINK H1G

H1G

49505152535455

56

RV630_FANSINK

RV630_FANSINK H1H

H1H

58596061626364

57

PWM

B B

RV630_FANSINK

RV630_FANSINK H1A

H1A

A A

2345678

1

Q4001

1

MMBT3904

2 3

RV630_FANSINK

RV630_FANSINK H1B

H1B

9

1%

R4039

10K

For 4-WIRE FAN

See BOM for qualified config

10111213141516

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - Thermal Management

Size Document Number Rev

C

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B101XX-00

4

of

18 21Tuesday, April 10, 2007

1

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5

DVI/DVI SCREWS with top tab

ASSY-SCREW1

SCREW

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

<3rd part field>

ASSY-SCREW3

D D

SCREW

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

<3rd part field>

ASSY1

ANTISTATIC

ANTISTATIC BAG

BAG

6_X_11

C C

ASSY-SCREW2

SCREW

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

<3rd part field>

ASSY-SCREW4

SCREW

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

<3rd part field>

BKT1

BRACKET

8020044300G

ASSY-SCREW5

SCREW

SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L

4

MT2

MT2 MT_Hole_0.136_in_6VIA

MT_Hole_0.136_in_6VIA

DNI

PCB1

PCB

109-B10131-00D

3

2

1

B B

A A

5

4

3

2

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH RV630 - Mechanical

Size Document Number Rev

C

Date: Sheet

105-B101XX-00

1

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19 21Tuesday, April 10, 2007

4

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5

Title

RH PCIE RV630 2x256MB GDDR4 DUAL DL-DVI-I VIVO FH Tuesday, April 10, 2007

REVISION HISTORY

D D

Sch

Sch Rev

Rev

PCB

PCB Rev

Rev

0

00A

1

00B

Date

06/11/08

06/11/18

Initial design for RV630 pipe cleaner

Regrouping of parts (Cosmetic) Power-up sequecning updated VID control and EXT detection are updated VDDC SMPS updated

4

NOTE:

3

105-B101XX-00

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU. For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.

For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.

For Stuffing options (component values, DNI’s, …) please consult the product specific BOM. Please contact ATI representative to obtain latest BOM closest to the application desired.

Please contact ATI representative to obtain latest BOM closest to the application desired.

REVISION DESCRIPTION

2

Date:Schematic No.

1

Rev

4

2 00C

C C

3 00D

400

B B

06/12/08

07/02/06 Removing some of test featuers

03/09/07 Release to production.

(pg 05) Re-assignment of MAA_13, MAA_14, MAA_15, MAB_13, MAB_14, and MAB_15 (pg 10) SMPS updated (pg 11) SMPS updated (pg 12) SMPS updated - Adding +5V option (pg 14) Adding R891 (pg 18) Adding Heatsink symbols H1 and H2 (pg 49) Adding MT1 (Layout) Heatsink mounting holes modified and one added.

(pg 14) Renaming LDO1 to LDO5 and for connecting to VDDCI if needed (pg 18) Merging 2-wire and 4-wire fan buffer circuitry (pg 3, 4) Adding 10uF caps to VDDRH, VDDCI, T2XVDDR, T2PVDD, and PLL rails (pg 10) Adding buffer for EXT_DETECT line, R1229 and C630 (pg 13) Adding option to control shut down circuitry for critical temperature (pg 14) Removing R891 (pg 7) Adding DIP switch to GPIO7 and GPIO5 (pg 1, 3) Adding TR10 to TR15 to support legacy JTAG for internal testing.

A A

5

4

3

2

1

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5

4

3

2

1

MEMORY CHANNEL A & B - RANK0

GDDR4 4pcs 16Mx32 (256MB)

D D

External 12V Header

Debug

POWER REGULATORS

From +12V

+VDDC (MPVDD, VDDCI), +MVDD (MVDDC)

From +12V LINEAR:

C C

B B

+5V, +5V_VESA, +5V_VESA2, +3.3VA for RageTheater

From +12V DIRECT:

FAN

From +MVDD Linear (1.1V):

PCIE_VDDC, DPLL_VDDC

From +3.3V: Direct or Linear (1.8V)

VDD_CT, DPLL_PVDD, TPVDD, T2PVDD, TXVDDR, T2XVDDR(LTVDD18), T2XVDDC(LTVDD33), AVDD, A2VDD, VDD1DI, VDD2DI, PCIE_VDDR, PCIE_PLL, VDDR3, VDDR4, VDDR5

+PCIE_SOURCE

+3.3V

3.3V_BUS delayed circuit

SMPS Enable Circuit

+12V_BUS

CrossFire Interlink Header

FAN

POWER DELIVERY

Connector

Straps

BIOS

Speed control & temperature sense

INTERRUPT Temp. Sensing

Built-in PWM

Dynamic VDDC

Temperature Critical

RANK0 RANK1

GPIO16 (TBV)12V_EXT_DETb

CrossFire

DVOCLK DVPCNTL_[0..2] DVPDATA[23:0] DVP_MVP_CNTL[1:0] GPIO[6:3] GENERICB, DVALID

TMDS1

DL TMDS1

HPD1

DAC2

H/V2Sync

GPIO

ROM

Thermal

DDC3

GPIO17 D+/D-

TS_FDO

GPIO15 GPIO20

XTALIN/OUT

Capture

GENERICA

TMDS2

DL TMDS2

HPD2 (GPIO14)

DAC1

RV630

H/VSync

CTFb

PCI-Express

CRT2

DDC2

TVO

MPP

VIP

STV/HDTV#_OUT_DET

CRT1

DDC1

MEMORY CHANNEL A & B - RANK1

GDDR4 4pcs 16Mx32 (256MB)

Shunt Resistors

XTAL

Oscillator

Shunt Resistors

RBG Filters

TVO Filters

XTALIN/OUT CLKOUT

RageTheater

RBG Filters

HPD2

Slim-VGA Connector

TVO/VIVO Connector

HPD1

DVI-I Slim-VGA Connector

&DVI-I

&

+3.3V_BUS +12V_BUS

PCI-Express Bus

RH PCIE RV630 2x256MB GDDR4 DUAL DL-DVI-I VIVO FH

REV 1

A A

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East Markham, Ontario

Markham, Ontario

Markham, Ontario Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6 (905) 882-2600

(905) 882-2600

Title

RH PCIE-2 RV630 2x256MB GDDR4 DUAL DL-DVI-I VIVO FH

Size Document Number Rev

C

Date: Sheet

5

4

3

2

Date: Sheet

105-B101XX-00

1

4

of

21 21Tuesday, April 10, 2007

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MSI MS-V098 Schematic 1.1

Specifications and Main Features

Frequently Asked Questions

User Manual