MSI MS-V095 Schematic 1.0
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
ASSEMBLYNVPNVARIANT
B
1
2
SKU
3
4
5
6
12
13
14
7
8
9
10
11
15
P401-A02 -- G84-400, 700/100MHz, 256MB 16Mx32 BGA136 GDDR3,
DVI-I-DL, DVI-I-DL, VIVO/TV-Out/Stereo
BASE
SKU0000
SKU0010
SKU9100
SKU9200
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
600-10401-base-200
600-10401-0000-200
600-10401-0010-200
600-10401-9100-200
600-10401-9200-200
<UNDEFINED>
<UNDEFINED>
<UNDEFINED> <UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
G84-400 700/1000GHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+HDTV-Out
G84-400 700/1000MHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+VIVO
G84-400 700/1000MHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+VIVO FOR SAMSUNG MEMORY
G84-400 700/1000MHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+VIVO FOR HYNIX MEMORY
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
Table of Contents:
Page 1: Title Page
Page 2: PEX Interface, NVVDD Decaps, PEX Decaps
Page 3: FrameBuffer - GPU Partition A and FBVDDQ Decaps
Page 4: FrameBuffer - Partition A 16Mx32 BGA136 GDDR3
Page 5: FrameBuffer - Partition A Decaps
Page 6: FrameBuffer - GPU Partition C and FBVDDQ Decaps
Page 7: FrameBuffer - Partition C 16Mx32 BGA136 GDDR3
Page 8: FrameBuffer - Partition C Decaps
Page 9: DACA Interface
Page 10: DACC Interface
Page 11: IFP A/B Interface
Page 12: IFP C/D Interface
Page 13: MIOA & MIOB and SLI Connector
Page 14: Video Capture (Philips 7115)
Page 15: DACB, TV-Out, and Stereo Interface
Page 16: XTAL/PLLVDD and SPDIF Connector
Page 17: GPIO, JTAG, BIOS ROM, HDCP ROM, and 2-Pin/4-Pin Fan Control
Page 18: Strap Configuration and Mechnicals & Thermals
Page 19: PowerSupply I - 5V, DDC5V, TMDS_PLL, TMDS_IOVDD, and MIOA_2V5
Page 20: PowerSupply II - FBVDDQ and PEXVDD
Page 21: PowerSupply III - PEX12V & EXT12V and NVVDD VID Control
Page 22: PowerSupply IV - NVVDD
G84-400 700/1000GHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+HDTV-Out
Title Page
www.vinafix.vn
600-10401-0000-200 B
p401_a02
APATEL
1 OF 22
16-JAN-2007
BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI
OUT
OUT
IN
1/14 PCI_EXPRESS
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
VDD
VDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD_LP
VDD_LP
VDD_LP
VDD_LP
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD_LP
VDD_LP
VDD_SENSE
GND_SENSE
VDD33
VDD33
PEX_PLLGND
PEX_PLLDVDD
PEX_PLLAVDD
SPDIF
PEX_RST
RFU
RFU
PEX_RX1
PEX_TX1
PEX_TX1
PEX_RX0
PEX_RX0
PEX_TX0
PEX_TX0
PEX_REFCLK
PEX_REFCLK
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
PEX_RX1
PEX_TX2
PEX_RX4
PEX_RX4
PEX_RX3
PEX_RX3
PEX_TX4
PEX_TX4
PEX_TX3
PEX_TX3
PEX_RX2
PEX_RX2
PEX_TX2
PEX_TX5
PEX_TX5
PEX_RX5
PEX_TX8
PEX_TX8
PEX_RX7
PEX_RX7
PEX_TX7
PEX_TX7
PEX_RX6
PEX_RX6
PEX_TX6
PEX_TX6
PEX_RX5
PEX_RX8
PEX_RX8
PEX_TX9
PEX_TX9
PEX_TX11
PEX_TX11
PEX_RX11
PEX_RX11
PEX_RX10
PEX_RX10
PEX_TX10
PEX_TX10
PEX_RX9
PEX_RX9
PEX_TX12
PEX_TX12
PEX_RX12
PEX_RX12
PEX_TX15
PEX_TX15
PEX_RX14
PEX_RX14
PEX_TX14
PEX_TX14
PEX_RX13
PEX_RX13
PEX_TX13
PEX_TX13
PEX_RX15
PEX_RX15
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
END OF X8
END OF X16
END OF X1
END OF X4
TCLK JTAG2
TMS JTAG5
TDO JTAG4
TDI JTAG3
WAKE
SMDAT
SMCLK
PERN0
PERP0
REFCLK
PERST
REFCLK
PETN1
PERP2
PETN0
PERP1
PERN1
PETP0
PETP1
PERN3
PETP3
PETN3
PETP2
PERP3
PETN2
PERN2
PERP4
PERN4
PETN4
PERP5
PETP4
PERN5
PETP5
PETP6
PERN6
PERP6
PETN5
PERP7
PETN6
PERN7
PETN8
PETP8
PERP8
PETN7
PETP7
PERN8
PERN9
PERP9
PERP10
PERN10
PETP10
PETP9
PETN9
PETN10
PETN11
PERP12
PERN12
PERP11
PERN11
PETP11
PETN12
PETP12
PETN13
PERP13
PERN13
PETP13
PERP14
PERN15
PETP15
PETN15
PERN14
PETN14
PETP14
PERP15
TRST* JTAG1+12V
+12V/RSVD
+3V3AUX
+12V
+12V
+12V
+3V3
+3V3
+3V3
PRSNT2
PRSNT1
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
GND
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
G1
G84-400-A1
BGA820
COMMON
AD23
AF23
AF24
AF25
AG24
AG25
AC16
AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18
AH15
AG12
AH13
AM12
AM11
AH14
AJ14
AJ15
AK15
AK13
AK14
AH16
AG16
AM14
AM15
AG17
AH17
AL15
AL16
AG18
AH18
AK16
AK17
AK18
AJ18
AL17
AL18
AJ19
AH19
AM18
AM19
AG20
AH20
AK19
AK20
AG21
AH21
AL20
AL21
AK21
AJ21
AM21
AM22
AJ22
AH22
AK22
AK23
AG23
AH23
AL23
AL24
AK24
AJ24
AM24
AM25
AJ25
AH25
AK25
AK26
AH26
AG26
AL26
AL27
AK27
AJ27
AM27
AM28
AJ28
AH27
AL28
AL29
G84-400 700/1000GHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+HDTV-Out
PEX Interface, NVVDD Decaps, PEX Decaps
AF21
AF22
K16
K17
N13
N14
N16
N17
N19
P13
P14
P16
P17
P19
R16
R17
T13
T14
T15
T18
T19
U13
U14
U15
U18
U19
V16
V17
W13
W14
W16
W17
W19
Y13
Y14
Y16
Y17
Y19
Y20
P20
T20
T23
U20
U23
W20
N20
M21
AC11
AC12
AC24
AD24
AE11
AE12
H7
J7
K7
L10
L7
L8
M10
AF15
AE15
AE16
J6
F_SPDIFIN
www.vinafix.vn
NVVDD_SENSE
NVVDD_GND_SENSE
GND
Place near balls
C649
.022UF
16V
10%
X7R
0402
COMMON
C671
.022UF
16V
10%
X7R
0402
COMMON
Place near balls
C696
4700PF
10%
25V
X7R
0402
COMMON
C757
C745
C735
10%
C722
10%
C704
10%
C694
10%
C683
C672
C662
C651
10%
C635
10%
C624
10%
C619
10%
C615
C605
10%
C598
10%
1
17<
17<
17<
17<
17<
PEX_RST_GPU*
0
R628
COMMON
0402
5%
SNN_PEXCAPD_VDDQ
SNN_PEXCALPD_GND
200
R38
0402 COMMON
5%
PEX_TEST_PLLCLK_OUT
PEX_TEST_PLLCLK_OUT_N
PEX_TX0
PEX_TX0*
X7R COMMON
10%
PEX_TX1
PEX_TX1*
X7R
COMMON10%
PEX_TX2
PEX_TX2*
X7R
COMMON
10%
PEX_TX3
PEX_TX3*
X7R COMMON
10%
PEX_TX4
PEX_TX4*
X7R
COMMON10%
PEX_TX5
PEX_TX5*
X7R
COMMON
10%
PEX_TX6
PEX_TX6*
X7R COMMON
10%
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
X7R
COMMON10%
PEX_TX9
PEX_TX9*
X7R
COMMON
10%
PEX_TX10
PEX_TX10*
X7R COMMON
10%
PEX_TX11
PEX_TX11*
X7R
COMMON10%
PEX_TX12
PEX_TX12*
X7R
COMMON
10%
PEX_TX13
PEX_TX13*
X7R COMMON
10%
PEX_TX14
PEX_TX14*
X7R
COMMON10%
PEX_TX15
PEX_TX15*
X7R COMMON
10%
040210%
040210%
0402
0402
0402
0402
040210%
040210%X7RCOMMON
040210%
0402
0402
0402
0402
040210%
0402
0402
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
18<
C751
C741
0402
C728
0402
C713
0402
0402
C686
0402
C676
0402
C668
C658
C645
0402
C633
0402
C621
0402
C616
0402
C613
C603
0402
C595
0402
.1UF
16V0402
.1UF
16V
.1UF
16V
.1UF
16V
.1UFC701
16V
.1UF
16V
.1UF
16V
.1UF
16V0402 X7R10% COMMON
.1UF
16V0402
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V
.1UF
16V0402
.1UF
16V
.1UF
16V
Page2: PEX Interface,.NVVDD Decaps, PEX Decaps
PEX3V3
C825
.01UF
16V
10%
X7R
3V3AUX
0402
COMMON
Place Close to fingers
C814
10UF
16V
20%
X5R
1206
COMMON
GND
PRSNT
SNN_PE_PRSNT2_A
SNN_PE_RSVD2
SNN_PE_PRSNT2_B
SNN_PE_RSVD3
SNN_PE_RSVD4
SNN_PE_RSVD5
SNN_PE_PRSNT2_C
SNN_PE_RSVD6
PRSNT
SNN_PE_RSVD7
SNN_PE_RSVD8
C29
.1UF
16V
10%
X5R
0402
COMMON
GND
C823
.1UF
16V
10%
X7R
0402
COMMON
PEX12V
GND
GND
GND
CN2
CON_X16
CON_PCIEXP_X16_EDGE
COMMON
B1
B2
A2
A3
B3
B8
A9
A10
B10
A1
B17
B12
B4
A4
B7
A12
B13
A15
B16
B18
A18
B31
A19
B30
A32
A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32
GND
B48
A33
A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49
B81
A50
B82
A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82
NONPHY-X16
C23
.01UF
25V
10%
X7R
0402
COMMON
B9
A5
A6
A7
A8
B5
B6
A11
A13
A14
A16
A17
B14
B15
A21
A22
B19
B20
A25
A26
B23
B24
A29
A30
B27
B28
A35
A36
B33
B34
A39
A40
B37
B38
A43
A44
B41
B42
A47
A48
B45
B46
A52
A53
B50
B51
A56
A57
B54
B55
A60
A61
B58
B59
A64
A65
B62
B63
A68
A69
B66
B67
A72
A73
B70
B71
A76
A77
B74
B75
A80
A81
B78
B79
PEX_TRST*
PEX_TCLK
PEX_TDI
PEX_TDO
PEX_TMS
I2CS_SCL
I2CS_SDA
SNN_PEX_WAKE*B11
C25 C26
.1UF
16V
10%
X7R
0603
COMMON
PEX_REFCLK
PEX_REFCLK*
PEX_TXX0
PEX_TXX0*
PEX_RX0
PEX_RX0*
PEX_TXX1
PEX_TXX1*
PEX_RX1
PEX_RX1*
PEX_TXX2
PEX_TXX2*
PEX_RX2
PEX_RX2*
PEX_TXX3
PEX_TXX3*
PEX_RX3
PEX_RX3*
PEX_TXX4
PEX_TXX4*
PEX_RX4
PEX_RX4*
PEX_TXX5
PEX_TXX5*
PEX_RX5
PEX_RX5*
PEX_TXX6
PEX_TXX6*
PEX_RX6
PEX_RX6*
PEX_TXX7
PEX_TXX7*
PEX_RX7
PEX_RX7*
PEX_TXX8
PEX_TXX8*
PEX_RX8
PEX_RX8*
PEX_TXX9
PEX_TXX9*
PEX_RX9
PEX_RX9*
PEX_TXX10
PEX_TXX10*
PEX_RX10
PEX_RX10*
PEX_TXX11
PEX_TXX11*
PEX_RX11
PEX_RX11*
PEX_TXX12
PEX_TXX12*
PEX_RX12
PEX_RX12*
PEX_TXX13
PEX_TXX13*
PEX_RX13
PEX_RX13*
PEX_TXX14
PEX_TXX14*
PEX_RX14
PEX_RX14*
PEX_TXX15
PEX_TXX15*
PEX_RX15
PEX_RX15*
PEX_RST*
GND
R662
0
5%
0402
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
10UF
16V
20%
X5R
1206
COMMON
17<
17<>
X7R
X7R
X7R
X7RCOMMON
X7R
X7R
X7RCOMMON
X7R
X7R
X7RCOMMON
X7R
X7R
X7RCOMMON
X7R
X7RCOMMON
VALUES TBD
C639
.022UF
16V
10%
X7R
0402
COMMON
VALUES TBD
Place near balls
C698
.022UF
16V
10%
X7R
0402
COMMON
Place near balls
C691
C692
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C684
C653
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C688
C703
.47UF
.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C680
C678
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
Place near balls
C710
.1UF
10V
10%
X5R
0402
C702
.1UF
10V
10%
0402
PEX_PLLVDD
C697
470PF
16V
10%
X7R
0402
COMMON
16> 16<
C661
.01UF
16V
10%
X7R
0402
COMMON
C673
.1UF
16V
10%
X7R
0402
COMMON
C706
.1UF .47UF.47UF
16V
10%
X7R
0402
COMMON
C689
.47UF
6.3V
10%
X5R
0402
COMMON
C656
1UF
6.3V
10%
X5R
0402
COMMON
22<
22<
C685
.1UF
10%
16V
X7R
0402
COMMON
C665
.01UF
16V
10%
X7R
0402
COMMON
C738
4700PF
25V
10%
X7R
0402
COMMONCOMMON
C724
4700PF
25V
10%
X7RX5R
0402
COMMONCOMMON
C675
.01UF
16V
10%
X7R
0402
COMMON
C654
.1UF
16V
10%
X7R
0402
COMMON
C670
6.3V
10%
X5R
0402
COMMON
C700
.47UF
6.3V
10%
X5R X5R
0402
COMMON
C667
10UF
6.3V
20%
X5R
0805
COMMON
C634
.022UF
16V
10%
X7R
0402
COMMON
C714
.022UF
16V
10%
X7R
0402
COMMON
C695
.01UF
16V
10%
X7R
0402
COMMON
Place Close to GPU
Place Close to GPU
C663
.1UF
16V
10%
X7R
0402
COMMON
C693
6.3V
10%
X5R
0402
COMMON
C642
.47UF
6.3V
10%
0402
COMMON
C709
10UF
6.3V
20%
X5R
0805
COMMON
C747
.022UF
16V
10%
X7R
0402
COMMON
C630
.022UF
16V
10%
X7R
0402
COMMON
GND
Place Near BGA
C682
4.7UF
6.3V
X5R
0603
COMMON
GND
PEXVDD
C606
4.7UF
10%
6.3V
X5R
0603
COMMON
PEXVDD
C655
22UF
20%
6.3V
X5R
0805
COMMON
GND
NVVDD
C669
C687
.1UF
.1UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C640
C643
.47UF .47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C679
C705
1UF
.47UF
6.3V
6.3V
10%
10%
X5R X5R
0402
0402
COMMON
COMMON
C677
10UF
6.3V
20%
X5R
0805
COMMON
PEX3V3
C764
1UF
6.3V
10%
X7R
0603
COMMON
GND
180R@100MHz
LB502
COMMONBEAD_0603
10%
C610
4.7UF
6.3V
X5R
0603
COMMON
C607
22UF
6.3V
X5R
0805
COMMON
PEX_REFCLKPEX_REFCLK
MIN_LINE_WIDTH
10MIL
30MIL
20MIL
PEX_REFCLK
PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7PEX_TX7*
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15
PEX_TXX0
PEX_TXX0
PEX_TXX1
PEX_TXX1
PEX_TXX2
PEX_TXX2
PEX_TXX3
PEX_TXX3
PEX_TXX4
PEX_TXX4
PEX_TXX5
PEX_TXX5
PEX_TXX6
PEX_TXX6
PEX_TXX7
PEX_TXX7
PEX_TXX8
PEX_TXX8
PEX_TXX9
PEX_TXX9
PEX_TXX10
PEX_TXX10
PEX_TXX11
PEX_TXX11
PEX_TXX12
PEX_TXX12
PEX_TXX13
PEX_TXX13
PEX_TXX14
PEX_TXX14
PEX_TXX15
PEX_TXX15
PEX_RX0
PEX_RX0
PEX_RX1
PEX_RX1
PEX_RX2
PEX_RX2
PEX_RX3
PEX_RX3
PEX_RX4
PEX_RX4
PEX_RX5
PEX_RX5
PEX_RX6
PEX_RX6
PEX_RX7
PEX_RX7
PEX_RX8
PEX_RX8
PEX_RX9
PEX_RX9
PEX_RX10
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_RX12
PEX_RX13
PEX_RX13
PEX_RX14
PEX_RX14
PEX_RX15
PEX_RX15
VOLTAGE
1.2V
VOLTAGEMIN_LINE_WIDTH
12V
3.3V
PEX_REFCLK*
10%
GND
20%
GND
PEXVDD
C650
4.7UF
10%
6.3V
X5R
0603
COMMON
GND
PEX12V
PEX3V3
PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
PEX_TXX0
PEX_TXX0*
PEX_TXX1
PEX_TXX1*
PEX_TXX2
PEX_TXX2*
PEX_TXX3
PEX_TXX3*
PEX_TXX4
PEX_TXX4*
PEX_TXX5
PEX_TXX5*
PEX_TXX6
PEX_TXX6*
PEX_TXX7
PEX_TXX7*
PEX_TXX8
PEX_TXX8*
PEX_TXX9
PEX_TXX9*
PEX_TXX10
PEX_TXX10*
PEX_TXX11
PEX_TXX11*
PEX_TXX12
PEX_TXX12*
PEX_TXX13
PEX_TXX13*
PEX_TXX14
PEX_TXX14*
PEX_TXX15
PEX_TXX15*
PEX_RX0
PEX_RX0*
PEX_RX1
PEX_RX1*
PEX_RX2
PEX_RX2*
PEX_RX3
PEX_RX3*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_RX14
PEX_RX14*
PEX_RX15
PEX_RX15*
NET
PEX_PLLVDD
PEX12V
PEX3V3
NET
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
NV_NET_MAX_CURRENT
NV_NET_MAX_CURRENT
5.5A
3A
0.200A
NV_CRITICALNV_IMPEDANCEDIFFPAIRNET
1100DIFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1100DIFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1100DIFF
1
1100DIFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1100DIFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
600-10401-0000-200 B
p401_a02
APATEL
2 OF 22
16-JAN-2007
Page3: FrameBuffer - GPU Partition A and FBVDDQ Decaps
BIBIOUT
OUT
OUT
OUT
OUT
BI
2/14 FBA
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBA_CMD0
FBA_CMD2
FBA_CMD3
FBVDDQ
FBA_CMD1
FBA_CMD4
FBA_CMD5
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD11
FBA_CMD13
FBA_CMD15
FBA_CMD16
FBA_CMD19
FBA_CMD21
FBA_CMD22
FBA_CMD24
FBA_CMD25
FBA_CMD20
FBA_CMD17
FBA_CMD14
FBA_CMD10
FBA_CMD6
FBA_CMD12
FBA_CMD18
FBA_CMD23
FBA_CMD26
FBA_DEBUG
FBA_CLK0
FBA_PLLAVDD
H_PLLAVDD
FBA_CLK1
FBA_CLK1
FBA_CLK0
FBA_CMD28
FBA_CMD27
NC1
NC2
FBA_PLLGND
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD44
FBAD47
FBAD49
FBAD51
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD45
FBAD46
FBAD48
FBAD50
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN7
FBADQS_RN6
FBADQS_RN5
FB_VREF1
OUTBIBI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
2
4<>
Rtop
Rbot
FBVDDQ
634
R5851.3K
R586
GND
4<>
4<>
4<>
NO STUFF
1%
0402
NO STUFF
1%
0402
DDR3:
FBAD<63..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
FBADQM<7..0>
FBADQS_WP<7..0>
FBADQS_RN<7..0>
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
C609
.1UF
16V
10%
X7R
0402
NO STUFF
VREF = FBVDDQ * Rbot/(Rtop + Rbot)
VREF = 0.70 * FBVDDQ
1.33V = 1.9V * 1.3K/(549 + 1.3K)
FBAD<0>
FBAD<1>
FBAD<2>
FBAD<3>
FBAD<4>
FBAD<5>
FBAD<6>
FBAD<7>
FBAD<8>
FBAD<9>
FBAD<10>
FBAD<11>
FBAD<12>
FBAD<13>
FBAD<14>
FBAD<15>
FBAD<16>
FBAD<17>
FBAD<18>
FBAD<19>
FBAD<20>
FBAD<21>
FBAD<22>
FBAD<23>
FBAD<24>
FBAD<25>
FBAD<26>
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30> E28
FBAD<31>
FBAD<32>
FBAD<33>
FBAD<34>
FBAD<35>
FBAD<36>
FBAD<37>
FBAD<38>
FBAD<39>
FBAD<40> AM30
FBAD<41>
FBAD<42>
FBAD<43>
FBAD<44>
FBAD<45>
FBAD<46>
FBAD<47>
FBAD<48>
FBAD<49>
FBAD<50>
FBAD<51>
FBAD<52>
FBAD<53>
FBAD<54>
FBAD<55>
FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<61>
FBAD<62>
FBAD<63>
FBADQM<0>
FBADQM<1>
FBADQM<2>
FBADQM<3>
FBADQM<4>
FBADQM<5>
FBADQM<6>
FBADQM<7>
FBADQS_WP<0>
FBADQS_WP<1>
FBADQS_WP<2>
FBADQS_WP<3>
FBADQS_WP<4>
FBADQS_WP<5>
FBADQS_WP<6>
FBADQS_WP<7>
FBADQS_RN<0>
FBADQS_RN<1>
FBADQS_RN<2>
FBADQS_RN<3>
FBADQS_RN<4>
FBADQS_RN<5>
FBADQS_RN<6>
FBADQS_RN<7>
N27
M27
N28
L29
K27
K28
J29
J28
P30
N31
N30
N32
L31
L30
J30
L32
H30
K30
H31
F30
H32
E31
D30
E30
H28
H29
E29
J27
F27
E27
F28
AD29
AE29
AD28
AC28
AB29
AA30
Y28
AB30
AF30
AJ31
AJ30
AJ32
AK29
AM31
AL30
AE32
AE30
AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28
AG29FBAD<60>
AD27
AF27
AE28
M29
M30
G30
F29
AA29
AK30
AC30
AG30
L28
K31
G32
G28
AB28
AL32
AF32
AH30
M28
K32
G31
G27
AA28
AL31
AF31
AH29
E32FBA_VREF
G1
G84-400-A1
BGA820
COMMON
A12
A18
A21
A24
A27
A3
A30
A6
A9
AA32
AD32
AG32
AK32
C32
F32
J32
M32
R32
AA25
AA26
AB25
AB26
G11
G12
G15
G18
G21
G22
H11
H12
H15
H18
H21
H22
L25
L26
M25
M26
R25
R26
V25
V26
FBA_CMD<0>
P32
FBA_CMD<1>
U27
FBA_CMD<2>
P31
FBA_CMD<3>
U30
FBA_CMD<4>
Y31
FBA_CMD<5>
W32
FBA_CMD<6>
W31
FBA_CMD<7>
T32
FBA_CMD<8>
V27
FBA_CMD<9>
T28
FBA_CMD<10>
T31
FBA_CMD<11>
U32
FBA_CMD<12>
W29
FBA_CMD<13>
W30
SNN_FBA_CMD<14>
T27
FBA_CMD<15>
V28
FBA_CMD<16>
V30
FBA_CMD<17>
U31
FBA_CMD<18>
R27
FBA_CMD<19>
V29
FBA_CMD<20>
T30
FBA_CMD<21>
W28
FBA_CMD<22>
R29
FBA_CMD<23>
R30
FBA_CMD<24>
P29
FBA_CMD<25>
U28
SNN_FBA_CMD<26>
Y32
SNN_FBA_CMD<27>
Y30
SNN_FBA_CMD<28>
V32
FBA_CLK0
P28
FBA_CLK0*
R28
FBA_CLK1
Y27
FBA_CLK1*
AA27
FBA_DEBUG
AC27
G23
H_PLLVDD
G25
G24
GND
D31 SNN_GPU_NC1_D31
D32
SNN_GPU_NC2_D32
C600
.1UF
16V
10%
X7R
0402
COMMON
C699
.47UF
6.3V
10%
X5R
0402
COMMON
C622
6.3V
10%
X5R
0402
COMMON
C681
1UF
6.3V
10%
X7R
0603
COMMON
C631
4.7UF
6.3V
10%
X5R
0603
COMMON
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
TP100
PLACE BELOW GPU
C674
.1UF
16V
10%
X7R
COMMON
C627
.47UF
6.3V
10%
X5R
0402
COMMON
C768
.47UF .47UF .47UF.47UF
6.3V
10%
X5R
0402
COMMON
C625
1UF
6.3V 6.3V
10%
X7R
0603
COMMON
C611
4.7UF
6.3V
10%
0603 0603
FBA_CMD<26..0>
4<
4<
4<
4<
.1UF
16V
10%
X7R
04020402
COMMON
C641
.47UF
6.3V
10%
X5R
0402
COMMON
C727
6.3V
10%
X5R
0402
COMMON
C594
1UF
10%
X7R
0603
COMMON
C657
4.7UF
6.3V
10%
X5RX5R
COMMONCOMMON
.1UF
16V
10%
X7R
0402
COMMON
C659
.47UF
6.3V
10%
X5R
0402
COMMON
C707
6.3V
10%
X5R
0402
COMMON
C725
1UF
6.3V
10%
X7R
0603
COMMON
4<> 4<
.1UF
16V
10%
X7R
0402
COMMON
C666
.47UF
6.3V
10%
X5R
0402
COMMON
C664
.47UF
6.3V
10%
X5R
0402
COMMON
C614
1UF
6.3V
10%
X7R
0603
COMMON
.1UF
16V
10%
X7R
0402
COMMON
C628
.47UF
6.3V
10%
X5R
0402
COMMON
C746
.47UF
6.3V
10%
X5R
0402
COMMON
.1UF
16V
10%
X7R
0402
COMMON
C690
C644
C597
C608
C636
PLACE close to balls
C648
.01UF
16V
10%
X7R
0402
COMMON
C647
.1UF
16V
10%
X7R
0402
COMMON
G84-400 700/1000GHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+HDTV-Out
FrameBuffer - GPU Partition A and FBVDDQ Decaps
www.vinafix.vn
FBVDDQ
GND
C599
.1UF
16V
10%
X7R
0402
COMMON
240R@100MHz
LB501
C646
1UF
6.3V
10%
0402
COMMON
COMMONBEAD_0402
FBVDDQ
C583
10UF
6.3V
20%
X5R
COMMON
C586
10UF
6.3V
20%
X5R
08050805
COMMON
PLACE MIDWAY BETWEEN GPU AND MEMORY
PEXVDD
C652
4.7UF
6.3V
10%
X5RX5R
0603
COMMON
GND
C596
10UF
6.3V
20%
X5R
0805
COMMON
GND
C800
10UF
6.3V
20%
X5R
0805
COMMON
NET
H_PLLVDD
FBA_VREF
12MIL
12MIL
p401_a02
APATEL
1.2V
600-10401-0000-200 B
NV_NET_MAX_CURRENTMIN_LINE_WIDTH VOLTAGE
0.120A
3 OF 22
16-JAN-2007
ININININBIBIBIBIBIBIBIBIBIBIBIBIBI
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
IN
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
FBVDDQ
136BGA CMD Mapping
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4K2
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
CMD
CMD1
CMD10
CMD11
CMD18
CMD15
CMD8
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD12
CMD3
CMD7
GND
FBA_VREF0
FBA_VREF1
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQ
1.33V = 2.0V * 1.3K/(634 + 1.3K)
FBAD<0>
0
FBAD<1>
1
FBAD<2>
2
FBAD<3>
3
FBAD<4>
4
FBAD<5>
5
FBAD<6>
6
FBAD<7>
7
FBADQM<0>
FBADQS_RN<0>
FBADQS_WP<0>
FBAD<32>
32
FBAD<33>
33
FBAD<34>
34
FBAD<35>
35
FBAD<36>
36
FBAD<37>
37
FBAD<38>
38
FBAD<39>
39
FBADQM<4>
FBADQS_RN<4>
FBADQS_WP<4>
FBA Partition
ADDR
RAS*
CAS*
WE*
CKE
RESET
CS0*
A<0>
A<1>
A<2>
Low Sub-Partition
A<3>
A<4>
A<5>
A<2>
Hi Sub-Partition
A<3>
A<4>
A<5>
A<6>
A<7>
A<8>
A<9>
A<10
A<11>
BA0
BA1
BA2
FBVDDQ
R564
634
R1
1%
0402
COMMON
R565
1.3K
COMMON
R11
T11
R10
T10
N11
M11
L10
M10
N10
P10
P11
L3
M2
M3
N2
T3
R2
T2
R3
N3
P3
P2
0402
1%
GND
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
C580
.1UF
R2
16V
10%
X7R
0402
COMMON
COMMON
COMMON
R540
80.6
0402
121
0402
COMMON
FBVDDQ
1%
1%
FBA_CLK0_TERM
4<> 3>
C540R547 R548
.01UF
6.3V
10%
X5R
0402
COMMON
GND
FBA_CMD<26..0>
Low Sub-Partition
121
1%
0402
COMMON
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
15
FBA_CMD<1>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<8>
CS0
FBA_CMD<19>
FBA_CMD<25>
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
FBA_CMD<21>
FBA_CMD<16>
FBA_CMD<23>
FBA_CMD<20>
FBA_CMD<17>
FBA_CMD<9>
FBA_CMD<12>
FBA_CMD<3>
FBA_CMD<7>
FBA_CMD<18>
FBA_CLK0
FBA_CLK0*
FBA_CMD<15>
SNN_FBA0_NC1
SNN_FBA0_NC2
A-CS0-LOW-32bit
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
Page4: FrameBuffer - Partition A 16Mx32 BGA136 GDDR3
NO STUFF
4< 3>
4< 3>
A9
A4
ZQ = 6x desired output
DDR3:
Impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
DDR3: CKE DETERMINES THE ODT VALUE FOR CMD PINS
CKE = 0 --> ODT = ZQ/2
CKE = 1 --> ODT = ZQ
FBVDDQ
4<>
4<>
4<>
4<>
R559
10K
5%
0402
COMMON
GND
3<>
3<>
3<>
3>
GND
C538
.047UF
16V
10%
X7R
COMMON
R555
10K
5%
0402
COMMON
FBA_ZQ0
R557
243
1%
0402
COMMON
GND
K12
C581
.047UF
16V
10%
X7R
04020402
COMMON
J12
FBAD<63..0>
FBADQM<7..0>
FBADQS_RN<7..0>
FBADQS_WP<7..0>
K1
J1
DDR3:
FBADQM<0>
0
FBADQM<1>
1
FBADQM<2>
2
FBADQM<3>
3
FBADQM<4>
4
FBADQM<5>
5
FBADQM<6>
6
FBADQM<7>
7
FBADQS_RN<0>
0
FBADQS_RN<1>
1
FBADQS_RN<2>
2
FBADQS_RN<3>
3
FBADQS_RN<4>
4
FBADQS_RN<5>
5
FBADQS_RN<6>
6
FBADQS_RN<7>
7
FBADQS_WP<0>
0
FBADQS_WP<1>
1
FBADQS_WP<2>
2
FBADQS_WP<3>
3
FBADQS_WP<4>
4
FBADQS_WP<5>
5
FBADQS_WP<6>
6
FBADQS_WP<7>
7
FBVDDQ
R562
80.6
1%
0402
4<
3>
3>
4<
R41
634
0402
R42
1.3K
0402
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
NO STUFF
COMMON
FBVDDQ
1%
GND
FBA_CLK1_TERM
121
1%
0402
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
R1
C41
.1UF
R2
16V1%
10%
X7R
0402
COMMON
FBAD<8>
FBAD<9>
FBAD<10>
FBAD<11>
FBAD<12>
FBAD<13>
FBAD<14>
FBAD<15>
FBADQS_RN<1>
FBADQS_WP<1>
FBAD<40>
FBAD<41>
FBAD<42> F10
FBAD<43>
FBAD<44>
FBAD<45>
FBAD<46>
FBAD<47>
FBADQM<5>
FBADQS_RN<5>
FBADQS_WP<5>
B10
G10
E11
F11
C10
C11
B11
E10
D10
D11
GND
T3
R2
R3
T2
M2
N2
L3
M3
N3FBADQM<1>
P3
P2
FBA_CMD<26..0>
Hi Sub-Partition
C570R563
.01UF
6.3V
10%
X5R
0402
COMMON
FBVDDQ
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
R561
121
1%
0402
COMMON
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
7
CS0
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
12
1
11
15
FBVDDQ
C582
.047UF
16V
10%
X7R
0402
COMMON
GND
FBAD<16>
FBAD<17>
FBAD<18>
FBAD<19>
FBAD<20>
FBAD<21>
FBAD<22>
FBAD<23>
FBADQM<2>
FBADQS_RN<2>
FBADQS_WP<2>
FBAD<48>
FBAD<49>
FBAD<50>
FBAD<51>
FBAD<52>
FBAD<53>
FBAD<54>
FBAD<55>
FBADQM<6>
FBADQS_RN<6>
FBADQS_WP<6>
FBA_CMD<7>
FBA_CMD<8>
FBA_CMD<18>
FBA_CMD<10>
FBA_CMD<5>
FBA_CMD<13>
FBA_CMD<21>
FBA_CMD<20>
FBA_CMD<19>
FBA_CMD<25>
FBA_CMD<4>
FBA_CMD<9>
FBA_CMD<17>
FBA_CMD<6>
FBA_CMD<23>
FBA_CMD<16>
FBA_CMD<3>
FBA_CMD<12>
FBA_CMD<1>
FBA_CMD<11>
FBA_CLK1
FBA_CLK1*
SNN_FBA1_NC1
SNN_FBA1_NC2
FBA_CMD<15>
FBA_ZQ1
R550
243
1%
0402
COMMON
GND
R10
M11
R11
T11
N11
T10
M10
L10
N10
P10
P11
B2
E2
C2
B3
C3
F3
G3
F2
E3
D3
D2
C42
.047UF
16V
10%
X7R
0402
COMMON
A-CS0-HI-32bit
M4
DDR3BGA136
VERSION=BGA136
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
A9
A4
K1
K12
J1
J12
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
PACK_TYPE=BGA136
24
25
26
27
28
29
30
31
56
57
58
59
60
61
62
63
FBAD<24>
FBAD<25>
FBAD<26>
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30>
FBAD<31>
FBADQM<3>
FBADQS_RN<3>
FBADQS_WP<3>
FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<60>
FBAD<61>
FBAD<62>
FBAD<63>
FBADQM<7>
FBADQS_RN<7>
FBADQS_WP<7>
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
F11
F10
B11
B10
C11
E11
G10
C10
E10
D10
D11
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
GND
FBA_VREF2
FBA_VREF3
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQDDR3:
1.33V = 2.0V * 1.3K/(634 + 1.3K)
M3
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
B3
F3
C2
C3
F2
E2
B2
G3
E3
D3
D2
R44
634
0402
COMMON
R43
1.3K
0402
COMMON
FBVDDQ
1%
1%
GND
NET
3> 4<
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
FBAD<63..0>
FBADQM<7..0>
FBADQS_RN<7..0>
FBADQS_WP<7..0>
FBA_CMD<26..0>
FBA_VREF0
FBA_VREF1
FBA_VREF2
FBA_VREF3
4< 3>
4< 3>
4< 3>
3<>
4<>
3>
4<>
3<>
4<>
3<>
4<>
3>
4<
NET
FBA_VDDA0
FBA_VDDA1
FBA_VDDA2
FBA_VDDA3
DIFFPAIR
FBA_CLK0 80DIFF
MIN_LINE_WIDTH
12MIL
12MIL
12MIL
12MIL
MIN_LINE_WIDTH
12MIL 2.1V
12MIL
12MIL
NV_IMPEDANCE
80DIFFFBA_CLK0
80DIFFFBA_CLK1
80DIFFFBA_CLK1
40OHM
40OHM
40OHM
40OHM
40OHM
VOLTAGE
2.1V
2.1V
2.1V12MIL
NV_CRITICAL_NET
1
1
1
1
1
1
1
1
1
NV_NET_MAX_CURRENT
0.020A
0.020A
0.020A
0.020A
R1
C43
.1UF
16V
R2
10%
X7R
0402
COMMON
FBVDDQ
R568
634
1%
0402
COMMON
R567
1.3K
1%
0402
COMMON
GND
FBA_CMD<26..0>
R1
C578
.1UF
R2
16V
10%
X7R
0402
COMMON
Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
FBA_CMD<2>
2
0
24
22
13
4
5
6
FBA_CMD<0>
FBA_CMD<24>
FBA_CMD<22>
FBA_CMD<13>
FBA_CMD<4>
FBA_CMD<5>
FBA_CMD<6>
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
5%
5%
5%
5%
5%
5%
5%
5%
R546
0402
R553
0402
R558
0402
R554
0402
R549
0402
R552
0402
R551
0402
R556
0402
FBVDDQ
G84-400 700/1000GHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+HDTV-Out
FrameBuffer - Partition A 16Mx32 BGA136 GDDR3
www.vinafix.vn
600-10401-0000-200 B
p401_a02
APATEL
4 OF 22
16-JAN-2007
Page5: FrameBuffer - GPU Partition A Decaps
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
Decoupling for FBA 32..0
FBVDDQ
PLACE NEAR MEMORY FBVDD PINS
C562
.1UF
16V
10%
X7R
0402
COMMON
C573
.01UF
16V
10%
X7R
0402
COMMON
C552
.01UF
25V
10%
X7R
0402
COMMON
C544
4.7UF 4.7UF 4.7UF4.7UF
6.3V
10%
X5R
0603
COMMON
C543
.1UF
16V
10%
X7R
0402 0402 0402
COMMON
C572
.01UF
25V
10%
X7R
0402
COMMON
C574
.01UF
25V
10%
X7R
0402
COMMON
C569
6.3V
10%
X5R
0603
COMMON COMMON
C550
.1UF
16V
10%
X7R
COMMON
C555
.01UF
25V
10%
X7R
0402
COMMON
C563
6.3V
10%
X5R
0603
C579
.1UF
16V
10%
X7R
COMMON
C545
.01UF
25V
10%
X7R
0402
COMMON
C564
6.3V
10%
X5R
0603
COMMON
C554
.1UF
16V
10%
X7R
0402
COMMON
C548
4.7UF 4.7UF4.7UF4.7UF 4.7UF4.7UF 4.7UF 4.7UF
6.3V
10%
X5R
0603
COMMON COMMON
C566
6.3V
10%
X5R
0603
GND
Decoupling for FBA 63..32
FBVDDQ
PLACE NEAR MEMORY FBVDD PINS
C549
.1UF
16V
10%
X7R
0402
COMMON
C577
.01UF
16V
10%
X7R
0402
COMMON
C559
.01UF
25V
10%
X7R
0402
COMMON
C560
6.3V
10%
X5R
0603
COMMON
C568
.1UF
16V
10%
X7R
COMMON
C547
.01UF
25V
10%
X7R
0402
COMMON
C571
.01UF
25V
10%
X7R
0402
COMMON
C553
6.3V
10%
X5R
0603
COMMON
C556
.1UF
16V
10%
X7R
COMMON
C542
.01UF
25V
10%
X7R
0402
COMMON
C567
6.3V
10%
X5R
0603
COMMON COMMON
C546
.1UF
16V
10%
X7R
040204020402
COMMON
C576
.01UF
25V
10%
X7R
0402
COMMON
C584
6.3V
10%
X5R
0603
C575
.1UF
16V
10%
X7R
0402
COMMON
C561
6.3V
10%
X5R
0603
COMMON
C551
6.3V
10%
X5R
0603
COMMON
GND
G84-400 700/1000GHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+HDTV-Out
FrameBuffer - Partition A Decaps
www.vinafix.vn
600-10401-0000-200 B
p401_a02
APATEL
5 OF 22
16-JAN-2007
Page6: FrameBuffer - GPU Partition C and FBVDDQ Decaps
BIBIBI
OUT
OUT
OUT
OUT
OUT
BI
3/14 FBC
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBC_CMD0
FBC_CMD4
FBC_CMD3
FBC_CMD2
FBC_CMD1
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_PLLAVDD
FBC_PLLVDD
FBC_DEBUG
FBC_CLK1
FBC_CLK1
FBC_CLK0
FBC_CLK0
FBC_CMD28
FBC_CMD27
FBCAL_TERM_GND
FBCAL_PU_GND
FBCAL_PD_VDDQ
FBC_PLLGND
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63
FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7
FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7
FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN7
FBCDQS_RN6
FBCDQS_RN5
FB_VREF2
OUTBIBI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
NET
FBC_PLLVDD
FBC_PLLAVDD
FBC_VREF
12MIL
12MIL 2.1V
12MIL
2.1V
NV_NET_MAX_CURRENTVOLTAGEMIN_LINE_WIDTH
0.120A
0.120A
G1
G84-400-A1
BGA820
COMMON
3
AA23
AB23
H16
H17
J10
J23
J24
J9
K11
K12
K21
K22
K24
K9
L23
M23
T25
U25
C13
A16
A13
B17
B20
A19
B19
E16
A14
C15
B16
F17
C19
SNN_FBC_CMD<14>
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20
C20
E13
F13
F18
E17
F12
G8
G10
G9
K26
H26
J26
SNN_FBVTT_AA23
SNN_FBVTT_AB23
SNN_FBVTT_H16
SNN_FBVTT_H17
SNN_FBVTT_J10
SNN_FBVTT_J23
SNN_FBVTT_J24
SNN_FBVTT_J9
SNN_FBVTT_K11
SNN_FBVTT_K12
SNN_FBVTT_K21
SNN_FBVTT_K22
SNN_FBVTT_K24
SNN_FBVTT_K9
SNN_FBVTT_L23
SNN_FBVTT_M23
SNN_FBVTT_T25
SNN_FBVTT_U25
FBC_CMD<0>
FBC_CMD<1>
FBC_CMD<2>
FBC_CMD<3>
FBC_CMD<4>
FBC_CMD<5>
FBC_CMD<6>
FBC_CMD<7>B14
FBC_CMD<8>
FBC_CMD<9>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<12>
FBC_CMD<13>
FBC_CMD<15>
FBC_CMD<16>
FBC_CMD<17>
FBC_CMD<18>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<21>
FBC_CMD<22>
FBC_CMD<23>
FBC_CMD<24>
FBC_CMD<25>
SNN_FBC_CMD<26>
SNN_FBC_CMD<27>
SNN_FBC_CMD<28>A15
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
FBC_DEBUG
SNN_FBC_PLLVDD
FBC_PLLAVDD
GND
FBCAL_PD
FBCAL_PU
FBCAL_TERM
FBC_CMD<26..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
TP101
7<
7<
7<
7<
7<> 7<
PLACE close to balls
C717
.01UF
16V 16V 6.3V
10%
X7R
0402
COMMON
R600
0402
R601
0402
R599
0402
FBVDDQ
60.4
COMMON
1%
40.2
COMMON
1%
40.2
2
1
COMMON
1%
GNDGND
G84-400 700/1000GHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+HDTV-Out
FrameBuffer - GPU Partition C and FBVDDQ Decaps
www.vinafix.vn
C716
.1UF
10%
X7R
0402
COMMON
C715
1UF
10%
X5R
0402
COMMON
NO STUFF
634
1%
0402
R592
NO STUFF
1.3K
1%
0402
R591
FBCD<63..0>
FBCDQM<7..0>
FBCDQS_WP<7..0>
FBCDQS_RN<7..0>
C617
.1UF
16V
10%
X7R
0402
NO STUFF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBCD<0>
FBCD<1>
FBCD<2>
FBCD<3>
FBCD<4>
FBCD<5>
FBCD<6>
FBCD<7>
FBCD<8>
FBCD<9>
FBCD<10>
FBCD<11>
FBCD<12>
FBCD<13>
FBCD<14>
FBCD<15>
FBCD<16>
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>
FBCD<24>
FBCD<25>
FBCD<26>
FBCD<27>
FBCD<28>
FBCD<29>
FBCD<30>
FBCD<31>
FBCD<32>
FBCD<33>
FBCD<34>
FBCD<35>
FBCD<36>
FBCD<37>
FBCD<38>
FBCD<39> A31
FBCD<40>
FBCD<41>
FBCD<42>
FBCD<43>
FBCD<44>
FBCD<45>
FBCD<46>
FBCD<47>
FBCD<48>
FBCD<49>
FBCD<50>
FBCD<51>
FBCD<52>
FBCD<53>
FBCD<54>
FBCD<55>
FBCD<56>
FBCD<57>
FBCD<58>
FBCD<59>
FBCD<60>
FBCD<61>
FBCD<62>
FBCD<63>
FBCDQM<0>
FBCDQM<1>
FBCDQM<2>
FBCDQM<3>
FBCDQM<4>
FBCDQM<5>
FBCDQM<6>
FBCDQM<7>
FBCDQS_WP<0>
FBCDQS_WP<1>
FBCDQS_WP<2>
FBCDQS_WP<3>
FBCDQS_WP<4> A29
FBCDQS_WP<5>
FBCDQS_WP<6>
FBCDQS_WP<7>
FBCDQS_RN<0>
FBCDQS_RN<1>
FBCDQS_RN<2>
FBCDQS_RN<3>
FBCDQS_RN<4>
FBCDQS_RN<6>
FBCDQS_RN<7>
FBC_VREF A28
DDR3:
B7
A7
C7
A2
B2
C4
A5
B5
F9
F10
D12
D9
E12
D11
E8
D8
E7
F7
D6
D5
D3
E4
C3
B4
C10
B10
C8
A10
C11
C12
A11
B11
B28
C27
C26
B26
C30
B31
C29
D28
D27
F26
D24
E23
E26
E24
F23
B23
A23
C25
C23
A22
C22
C21
B22
E22
D22
D21
E21
E18
D19
D18
E19
A4
E11
F5
C9
C28
F24
C24
E20
C5
E10
E5
B8
D25
B25
F20
C6
E9
E6
A8
B29
E25FBCDQS_RN<5>
A25
F21
VREF = FBVDDQ * Rbot/(Rtop + Rbot)
VREF = 0.70 * FBVDDQ
1.33V = 1.9V * 1.3K/(549 + 1.3K)
7<>
7<>
7<>
7<>
FBVDDQ
Rtop
Rbot
GND
240R@100MHz
LB503
PEXVDD
COMMONBEAD_0402
C719
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
600-10401-0000-200 B
p401_a02
APATEL
6 OF 22
16-JAN-2007
Page7: FrameBuffer - Partion C 16Mx32 BGA136 GDD3
ININININBIBIBIBIBIBIBIBIBIBIBIBIBI
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
IN
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
7<
DDR3:
DDR3: CKE DETERMINES THE ODT VALUE FOR CMD PINS
FBVDDQ
R622
80.6
1%
0402
NO STUFF
121
1%
0402
COMMON
6>
6> 7<
ZQ = 6x desired output
Impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
CKE = 0 --> ODT = ZQ/2
CKE = 1 --> ODT = ZQ
7<> 6>
FBC_CLK0_TERM
GND
FBC_CMD<26..0>
Low Sub-Partition
C771 R619R626
.01UF
6.3V
10%
X5R
0402
COMMON
121
1%
0402
COMMON
FBVDDQ
7<>
7<>
7<>
7<>
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
15
R603
10K
5%
0402
COMMON
GND
6<>
6>
6<>
6<>
C754
.047UF
16V
10%
X7R
0402
COMMON
FBC_CMD<1>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<8>
CS0
FBC_CMD<19>
FBC_CMD<25>
FBC_CMD<22>
FBC_CMD<24>
FBC_CMD<0>
FBC_CMD<2>
FBC_CMD<21>
FBC_CMD<16>
FBC_CMD<23>
FBC_CMD<20> V1M9
FBC_CMD<17>
FBC_CMD<9>
FBC_CMD<12>
FBC_CMD<3>
FBC_CMD<7>
FBC_CMD<18>
FBC_CLK0
FBC_CLK0*
SNN_FBC0_NC1
SNN_FBC0_NC2
FBC_CMD<15>
R602
10K
5%
0402
COMMON
GND
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
A9
FBC_ZQ0
A4
R635
243
1%
0402
COMMON
GND
K1
K12
C758
.047UF
16V
10%
X7R
0402
COMMON
J1
J12
FBCD<63..0>
FBCDQM<7..0>
FBCDQS_RN<7..0>
FBCDQS_WP<7..0>
A-CS0-LOW-32bit
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
FBCDQM<0>
0
FBCDQM<1>
1
FBCDQM<2>
2
FBCDQM<3>
3
FBCDQM<4>
4
FBCDQM<5>
5
FBCDQM<6>
6
FBCDQM<7>
7
FBCDQS_RN<0>
0
FBCDQS_RN<1>
1
FBCDQS_RN<2>
2
FBCDQS_RN<3>
3
FBCDQS_RN<4>
4
FBCDQS_RN<5>
5
FBCDQS_RN<6>
6
FBCDQS_RN<7>
7
FBCDQS_WP<0>
0
FBCDQS_WP<1>
1
FBCDQS_WP<2>
2
FBCDQS_WP<3>
3
FBCDQS_WP<4>
4
FBCDQS_WP<5>
5
FBCDQS_WP<6>
6
FBCDQS_WP<7>
7
FBA Partition
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
DDR3:
136BGA CMD Mapping
CMD
CMD1
CMD10
CMD11
CMD18
CMD15
CMD8
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD17
CMD9
CMD12
CMD3
CMD7
GND
FBC_VREF0
FBC_VREF1
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQ
1.33V = 2.0V * 1.3K/(634 + 1.3K)
FBCD<0>
0
FBCD<1>
1
FBCD<2>
2
FBCD<3>
3
FBCD<4>
4
FBCD<5>
5
FBCD<6>
6
FBCD<7>
7
FBCDQM<0>
FBCDQS_RN<0>
FBCDQS_WP<0>
FBCD<32>
32
FBCD<33>
33
FBCD<34>
34
FBCD<35>
35
FBCD<36>
36
FBCD<37>
37
FBCD<38>
38
FBCD<39>
39
FBCDQM<4>
FBCDQS_RN<4>
FBCDQS_WP<4>
ADDR
RAS*
CAS*
WE*
CKE
RESET
CS0*
A<0>
A<1>
A<2>
A<3>
A<4>
A<5>
A<2>
A<3>
A<4>
A<5>
A<6>
A<7>
A<8>
A<9>CMD20
A<10
A<11>
BA0
BA1
BA2
R631
COMMON
R627
1.3K
COMMON
B2
C2
E2
F2
G3
F3
C3
B3
E3
D3
D2
E11
F11
F10
G10
B11
C10
C11
B10
E10
D10
D11
634
0402
0402
FBVDDQ
1%
1%
Low Sub-Partition
Hi Sub-Partition
R1
R2
GND
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
C766
.1UF
16V
10%
X7R
0402
COMMON
7<
6>
6> 7<
COMMON
1.3K
COMMON
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
R597
80.6
NO STUFF
R596
COMMON
FBVDDQ
R36
634
1%
0402
R37
1%
0402
GND
FBCD<8>
FBCD<9>
FBCD<10>
FBCD<11>
FBCD<12>
FBCD<13>
FBCD<14>
FBCD<15>
FBCDQM<1>
FBCDQS_RN<1>
FBCDQS_WP<1>
FBCD<40>
FBCD<41>
FBCD<42>
FBCD<43>
FBCD<44>
FBCD<45>
FBCD<46>
FBCD<47>
FBCDQM<5>
FBCDQS_RN<5>
FBCDQS_WP<5>
FBVDDQ
1%
0402
FBC_CLK1_TERM
121
1%
0402
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
R1
C36
.1UF
R2
16V
10%
X7R
0402
COMMON
M11
T10
R11
N11
T11
R10
L10
M10
N10
P10
P11
Hi Sub-Partition
C629
.01UF
6.3V
10%
X5R
0402
COMMON
GND
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
E2
B2
B3
F3
F2
C3
C2
G3
E3
D3
D2
FBC_CMD<26..0>
R595
121
1%
0402
COMMON
FBVDDQ
FBVDDQ
16
17
18
19
20
21
22
23
FBCDQM<2>
FBCDQS_RN<2>
FBCDQS_WP<2>
48
49
50
51
52
53
54
55
FBCDQM<6>
FBCDQS_RN<6>
FBCDQS_WP<6>
G84-400 700/1000GHz 256MB 16Mx32 BGA136 GDDR3 DVI-I-DL+DVI-I-DL+HDTV-Out
FrameBuffer - Partition C 16MX32 BGA136 GDDR3
FBC_CMD<7>
7
FBC_CMD<8>
CS0
8
FBC_CMD<18>
18
FBC_CMD<10>
10
FBC_CMD<5>
5
FBC_CMD<13>
13
FBC_CMD<21>
21
FBC_CMD<20>
20
FBC_CMD<19>
19
FBC_CMD<25>
25
FBC_CMD<4>
4
FBC_CMD<9>
9
17
FBC_CMD<6> M9
6
FBC_CMD<23>
23
FBC_CMD<16>
16
FBC_CMD<3>
3
FBC_CMD<12>
12
FBC_CMD<1>
1
FBC_CMD<11>
11
FBC_CLK1
FBC_CLK1*
SNN_FBC1_NC1
SNN_FBC1_NC2
FBC_CMD<15>
15
FBC_ZQ1
R584
243
1%
0402
COMMON
GND
C618
.047UF
16V
10%
X7R
0402
COMMON
GND
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>
FBCD<48>
FBCD<49>
FBCD<50>
FBCD<51>
FBCD<52>
FBCD<53>
FBCD<54>
FBCD<55>
www.vinafix.vn
T10
T11
M11
R11
N11
R10
L10
M10
N10
P10
P11
B10FBCD<16>
G10
F11
F10
C11
E11
B11
C10
E10
D10
D11
C37
.047UF
16V
10%
X7R
0402
COMMON
A-CS0-HI-32bit
M2
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11FBC_CMD<17>
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
A9
A4
K1
K12
J1
J12
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
24
25
26
27
28
29
30
31
FBCDQM<3>
FBCDQS_RN<3>
FBCDQS_WP<3>
56
57
58
59
60
61
62
63
FBCD<24>
FBCD<25>
FBCD<26>
FBCD<27>
FBCD<28>
FBCD<29>
FBCD<30>
FBCD<31>
FBCD<56>
FBCD<57>
FBCD<58>
FBCD<59>
FBCD<60>
FBCD<61>
FBCD<62>
FBCD<63>
FBCDQM<7>
FBCDQS_RN<7>
FBCDQS_WP<7>
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
M2
N2
L3
M3
R2
R3
T2
T3
N3
P3
P2
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
GND
FBC_VREF2
FBC_VREF3
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQDDR3:
1.33V = 2.0V * 1.3K/(634 + 1.3K)
M1
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
N2
M2
L3
M3
R2
R3
T2
T3
N3
P3
P2
R40
634
0402
COMMON
R39
1.3K
0402
COMMON
FBVDDQ
1%
1%
GND
NET
7< 6>
7< 6>
7< 6>
6> 7<
6<>
7<>
6>
7<>
6<>
7<>
6<>
7<>
6> 7<
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
FBCD<63..0>
FBCDQM<7..0>
FBCDQS_RN<7..0>
FBCDQS_WP<7..0>
FBC_CMD<26..0>
FBC_VREF0
FBC_VREF1
FBC_VREF2
FBC_VREF3
NET
FBC_VDDA0
FBC_VDDA1
FBC_VDDA2
FBC_VDDA3
DIFFPAIR
FBC_CLK0 80DIFF
FBC_CLK0 80DIFF
FBC_CLK1 80DIFF
MIN_LINE_WIDTH
12MIL
12MIL
12MIL
12MIL
MIN_LINE_WIDTH
12MIL
12MIL
NV_IMPEDANCE
80DIFFFBC_CLK1
40OHM
40OHM
40OHM
40OHM
40OHM
VOLTAGE
2.1V12MIL
2.1V
2.1V
2.1V12MIL
NV_CRITICAL_NET
1
1
1
1
1
1
1
1
1
NV_NET_MAX_CURRENT
0.020A
0.020A
0.020A
0.020A
R1
C38
.1UF
16V
R2
10%
X7R
0402
COMMON
FBVDDQ
R588
634
1%
0402
COMMON
R587
1.3K
1%
0402
COMMON
GND
FBC_CMD<26..0>
R1
C612
.1UF
R2
16V
10%
X7R
0402
COMMON
Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
FBC_CMD<2>
2
FBC_CMD<0>
0
FBC_CMD<24>
24
FBC_CMD<22>
22
FBC_CMD<13>
13
FBC_CMD<4>
4
FBC_CMD<5>
5
FBC_CMD<6>
6
120 R623
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
FBVDDQ
0402
5%
R620
0402
5%
R611
0402
5%
R615
0402
5%
R590
0402
5%
R589
0402
5%
R593
0402
5%
R594
0402
5%
600-10401-0000-200 B
p401_a02
APATEL
7 OF 22
16-JAN-2007
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