MSI MS-V093 Schematic 2.0

5

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

RV630 DDR2-REVISION HISTORY Friday, April 13, 2007

RV630 DDR2-REVISION HISTORY Friday, April 13, 2007

RV630 DDR2-REVISION HISTORY Friday, April 13, 2007

REVISION HISTORY

REVISION HISTORY

REVISION HISTORY

D D

PCB

PCB

Sch

Sch

Sch
Rev

Rev

Rev

1 00B

PCB
Rev

Rev

Rev

0

00A

Date

Date

Date

06/11/17

07/01/26

Initial design for RV630 DDR2

THIS IS A TEST BOARD, WE WILL BASE ON THIS ONE TO DECIDE WHICH WAY WE SHOULD GO

1) CHANGING RGB CONFIGURATION FOR BOTH DAC1 AND DAC2 (PAGE 3, 14 AND 15)

2) ADD-IN Q102 AND R49 FOR VDDR3 POWER SEQUENCE CONTROL

3) CONNECT R847 TO +1.8V_D1 INSTEAD OF +1.8V_LDO2 (PAGE 13)

4) LVTM LAYOUT CHANGES TO IMPROVE SI

4

NOTE:

NOTE:

NOTE:

3

105-B149xx-00

105-B149xx-00

105-B149xx-00

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU.
For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.

For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.

For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.
Please contact ATI representative to obtain latest BOM closest to the application desired.

Please contact ATI representative to obtain latest BOM closest to the application desired.

Please contact ATI representative to obtain latest BOM closest to the application desired.

REVISION DESCRIPTION

REVISION DESCRIPTION

REVISION DESCRIPTION

2

Date:Schematic No.

Date:Schematic No.

Date:Schematic No.

1

Rev

Rev

Rev

4

4

4

2 00C

C C

3 00D

400

B B

07/02/08 1) COME BACK AND START AS REV. A SINCE REV. B DOES NOT WORK ON CRT SIGNALS, EXCEPT THE LAYOUT ON LVTM TO IMPROVE SI

07/03/12 1) REMOVE RP702 AND RP703. REPLACE BY R724 (PAGE12). IT'S FOR DFM RECOMMENDATION (NO TECHNICAL REASON)

07/04/02 1) NO SCHEMATIC CHANGE. ONLY MOVE R1206 CLOSE TO U703 TO IMPROVE THE FB LINE (TOO LONG). R1206 IS NOT POPULATED ON BOM

2) ADD-IN Q102 AND R49 FOR VDDR3 POWER SEQUENCE CONTROL

3) CONNECT R847 TO +1.8V_D1 INSTEAD OF +1.8V_LDO2 (PAGE 14)

4) ADD-IN SINGLE PHASE POWER SUPPLY DUE TO POWER MEASUREMENT IS LOWER THAN ESTIMATE (PAGE 10)

5) REMOVE JU57 AND ADD-IN SW1 TO SUPPORT JTAG CONNECTOR TJ47 (GPIO5) (PAGE 7)

2) ADD-IN R4010 AND C4010 FOR 2-PIN CONTROLLER TO USE INTERNAL PWM (PAGE 18)

A A

5

4

3

2

1

www.vinafix.vn

5

4

3

2

1

MEMORY CHANNEL A

DDR2 4pcs 16Mx32 (256MB)

D D

MEMORY CHANNEL B

DDR2 4pcs 16Mx32 (256MB)

Channel A Channel B

TMDS1

Oscillator

Shunt Resistors

Shunt Resistors

RBG Filters

TVO Filters

XTALIN/OUT

RBG Filters

SEFADU: RH PCIE RV630

HPD2

Slim-VGA

Connector

TVO

Connector

HPD1

DVI-I

Slim-VGA

Connector

&DVI-I

&

DL TMDS1

POWER REGULATORS

From +12V

+VDDC (MPVDD, VDDCI),
+MVDD

From +12V LINEAR:

C C

B B

+5V, +5V_VESA,
+5V_VESA2,
+3.3VA for RageTheater

From +12V DIRECT:

FAN

From +MVDD Linear (1.1V):

PCIE_VDDC, DPLL_VDDC

From +3.3V:
Direct or Linear (1.8V)

VDD_CT, DPLL_PVDD,
TPVDD, T2PVDD, TXVDDR,
T2XVDDR(LTVDD18),
T2XVDDC(LTVDD33), AVDD,
A2VDD, VDD1DI, VDD2DI,
PCIE_VDDR, PCIE_PLL,
VDDR3, VDDR4, VDDR5

+PCIE_SOURCE

+3.3V

3.3V_BUS
delayed circuit

SMPS Enable
Circuit

+12V_BUS

FAN

POWER DELIVERY

Straps

BIOS

Speed control
& temperature
sense

INTERRUPT

Temp. Sensing

Built-in PWM

Dynamic VDDC

Temperature Critical

GPIO

ROM

Thermal

DDC3

GPIO17

D+/D-

TS_FDO

GPIO15

RV630

CTFb

PCI-Express

HPD1

DAC2

CRT2

H/V2Sync

DDC2

XTALIN/OUT

GENERICA

TMDS2

DL TMDS2

HPD2
(GPIO14)

DAC1

CRT1

H/VSync

DDC1

TVO

XTAL

STV/HDTV#_OUT_DET

256MB/512MB DDR2

+3.3V_BUS
+12V_BUS

PCI-Express Bus

DUAL DL-DVI-I TVO FH

REV 0

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2-BLOCK DIAGRAM

RV630 DDR2-BLOCK DIAGRAM

RV630 DDR2-BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

4

4

21 21Friday, April 13, 2007

21 21Friday, April 13, 2007

21 21Friday, April 13, 2007

4

of

of

of

www.vinafix.vn

8

7

6

5

4

3

2

1

+12V_BUS

C1

CAP CER 10UF 20% 16V X5R

10UFC110UF

(1206)1.8MM H MAX

+12V_BUS

+12V_BUS

C2

D D

+3.3V_BUS

+3.3V_BUS

C C

B B

C3

150nF_16VC2150nF_16VC3150nF_16V

150nF_16V
LF CAP CER 150NF 10% 16V X7R (0603)

LF CAP CER 150NF 10% 16V X7R (0603)

CAP CER 10UF 10% 6.3V X6S
(0805)1.4MM MAX THICK

C4
10uF_X6SC410uF_X6S

C6

C0

1uF_6.3VC61uF_6.3V

C5
100nFC5100nF

Place these caps as close to the PCIE
connector as possible

10nFC010nF

TEST_EN

TEST_EN3,7

JTAG_MODE

JTAG_TRST#

Share one PAD

MR71KMR7
1K

Share one pad

MR51KMR5
1K

PETn0_GFXRn02

PETp1_GFXRp12
PETn1_GFXRn12

PETp2_GFXRp22
PETn2_GFXRn22

PETp3_GFXRp32
PETn3_GFXRn32

PETp4_GFXRp42
PETn4_GFXRn42

PETp5_GFXRp52
PETn5_GFXRn52

PETp6_GFXRp62
PETn6_GFXRn62

PETp7_GFXRp72
PETn7_GFXRn72

PETp8_GFXRp82
PETn8_GFXRn82

PETp9_GFXRp92
PETn9_GFXRn92

PETp10_GFXRp102
PETn10_GFXRn102

PETp11_GFXRp112
PETn11_GFXRn112

PETp12_GFXRp122
PETn12_GFXRn122

PETp13_GFXRp132
PETn13_GFXRn132

PETp14_GFXRp142
PETn14_GFXRn142

PETp15_GFXRp152
PETn15_GFXRn152

R7 1KR7 1K

TP6

TP6

TP5

TP5

35mil

35mil

35mil

35mil

DNI

PRESENCE

PCI-EXPRESS EDGE CONNECTOR

+3.3V_BUS

+12V_BUS

x16 PCIe

+12V#B1
+12V#B2
+12V#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1

3.3Vaux
WAKE#

RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82

x16 PCIe

Mechanical Key

Mechanical Key

B1
B2
B3
B4
B5

R51KR5
1K

JTRST#

B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

PRSNT1#A1

+12V#A2
+12V#A3
GND#A4

JTAG2
JTAG3
JTAG4
JTAG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12
REFCLK+
REFCLK­GND#A15

PERp0
PERn0

GND#A18

RSVD#A19

GND#A20

PERp1

PERn1
GND#A23
GND#A24

PERp2

PERn2
GND#A27
GND#A28

PERp3

PERn3
GND#A31

RSVD#A32
RSVD#A33

GND#A34

PERp4

PERn4
GND#A37
GND#A38

PERp5

PERn5
GND#A41
GND#A42

PERp6

PERn6
GND#A45
GND#A46

PERp7

PERn7
GND#A49

RSVD#A50

GND#A51

PERp8

PERn8
GND#A54
GND#A55

PERp9

PERn9
GND#A58
GND#A59

PERp10

PERn10
GND#A62
GND#A63

PERp11

PERn11
GND#A66
GND#A67

PERp12

PERn12
GND#A70
GND#A71

PERp13

PERn13
GND#A74
GND#A75

PERp14

PERn14
GND#A78
GND#A79

PERp15

PERn15
GND#A82

MPCIE1

MPCIE1

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

PERp0
PERn0

PERp1
PERn1

PERp2
PERn2

PERp3
PERn3

PERp4
PERn4

PERp5
PERn5

PERp6
PERn6

PERp7
PERn7

PERp8
PERn8

PERp9
PERn9

PERp10
PERn10

PERp11
PERn11

PERp12
PERn12

PERp13
PERn13

PERp14
PERn14

PERp15
PERn15

+3.3V_BUS+12V_BUS

PRESENCE

JTCK
JTDI
JTDOJMODE
JTMS

R2 0RR2 0R

C7
100nFC7100nF

C9
100nFC9100nF

C11

C11
100nF

100nF

C13

C13
100nF

100nF

C15

C15
100nF

100nF

C17

C17
100nF

100nF

C19

C19
100nF

100nF

C21

C21
100nF

100nF

C23

C23
100nF

100nF

C25

C25
100nF

100nF

C27

C27
100nF

100nF

C29

C29
100nF

100nF

C31

C31
100nF

100nF

C33

C33
100nF

100nF

C35

C35
100nF

100nF

C37

C37
100nF

100nF

PERST#

C8
100nFC8100nF

C10

C10
100nF

100nF

C12

C12
100nF

100nF

C14

C14
100nF

100nF

C16

C16
100nF

100nF

C18

C18
100nF

100nF

C20

C20
100nF

100nF

C22

C22
100nF

100nF

C24

C24
100nF

100nF

C26

C26
100nF

100nF

C28

C28
100nF

100nF

C30

C30
100nF

100nF

C32

C32
100nF

100nF

C34

C34
100nF

100nF

C36

C36
100nF

100nF

C38

C38
100nF

100nF

No JTAG

JTAG

8 1
7 2
6 3
5 4

PCIE_REFCLKP 2
PCIE_REFCLKN 2PETp0_GFXRp02

GFXTp0_PERp0 2
GFXTn0_PERn0 2

GFXTp1_PERp1 2
GFXTn1_PERn1 2

GFXTp2_PERp2 2
GFXTn2_PERn2 2

GFXTp3_PERp3 2
GFXTn3_PERn3 2

GFXTp4_PERp4 2
GFXTn4_PERn4 2

GFXTp5_PERp5 2
GFXTn5_PERn5 2

GFXTp6_PERp6 2
GFXTn6_PERn6 2

GFXTp7_PERp7 2
GFXTn7_PERn7 2

GFXTp8_PERp8 2
GFXTn8_PERn8 2

GFXTp9_PERp9 2
GFXTn9_PERn9 2

GFXTp10_PERp10 2
GFXTn10_PERn10 2

GFXTp11_PERp11 2
GFXTn11_PERn11 2

GFXTp12_PERp12 2
GFXTn12_PERn12 2

GFXTp13_PERp13 2
GFXTn13_PERn13 2

GFXTp14_PERp14 2
GFXTn14_PERn14 2

GFXTp15_PERp15 2
GFXTn15_PERn15 2

TP2

TP2

TP4

35mil

35mil

TP3

TP3
35mil

35mil

TP4
35mil

35mil

JTAG_TCK 7

JTAG_TDI 7
JTAG_TDO 7JTAG_MODE7
JTAG_TMS 7

TP1

TP1
35mil

35mil

RP1A0R RP1A0R
RP1B0R RP1B0R
RP1C0R RP1C0R
RP1D0R RP1D0R

+3.3V

1

2

R3 0RDNIR3 0RDNI

53

R_RST

C39

C39
100nF

100nF

NC7SZ08P5X_NL

NC7SZ08P5X_NL

4

U5

U5

Place R3 in U5

PERST#_buf 2

SYMBOL LEGEND

DO NOT

DNI

INSTALL

ACTIVE

#

LOW

DIGITAL
GROUND

ANALOG

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RH PCIE RV630 DDR2- PCIE CONNECTOR

RH PCIE RV630 DDR2- PCIE CONNECTOR

RH PCIE RV630 DDR2- PCIE CONNECTOR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B149xx-00

105-B149xx-00

105-B149xx-00

GROUND

BUO BRING UP

ONLY

121Friday, April 13, 2007

121Friday, April 13, 2007

121Friday, April 13, 2007

of

of

of

1

4

4

4

www.vinafix.vn

5

D D

NOTE: some of the PCIE testpoints will
be available trought via on traces.

PETp0_GFXRp01
PETn0_GFXRn01

PETp1_GFXRp11
PETn1_GFXRn11

PETp2_GFXRp21
PETn2_GFXRn21

PETp3_GFXRp31
PETn3_GFXRn31

PETp4_GFXRp41
PETn4_GFXRn41

PETp5_GFXRp51
PETn5_GFXRn51

PETp6_GFXRp61

C C

B B

PCIE_REFCLKP1
PCIE_REFCLKN1

PETn6_GFXRn61

PETp7_GFXRp71
PETn7_GFXRn71

PETp8_GFXRp81

PETp9_GFXRp91
PETn9_GFXRn91

PETp10_GFXRp101
PETn10_GFXRn101

PETp11_GFXRp111
PETn11_GFXRn111

PETp12_GFXRp121
PETn12_GFXRn121

PETp13_GFXRp131
PETn13_GFXRn131

PETp14_GFXRp141
PETn14_GFXRn141

PETp15_GFXRp151
PETn15_GFXRn151

R13

R13

R14

R14

51R

51R

51R

51R

DNI

DNI

DNI

DNI

TP11

TP11
35mil

35mil

TP12

TP12
35mil

35mil

TP13

TP13
35mil

35mil

TP14

TP14
35mil

35mil

TP19

TP19
35mil

35mil

TP20

TP20
35mil

35mil

TP21

TP21
35mil

35mil

TP22

TP22
35mil

35mil

TP27

TP27
35mil

35mil

TP28

TP28
35mil

35mil

4

U1A

AK33

AJ33

AJ35
AJ34

AH35

AH34

AG35
AG34

AF33
AE33

AE35
AE34

AD35
AD34

AC35
AC34

AB33
AA33

AA35
AA34

AJ31
AJ30

AM32

Y35
Y34

W35
W34

V33
U33

U35
U34

T35
T34

R35
R34

U1A

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

PCIE_RX10P
PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX12P
PCIE_RX12N

PCIE_RX13P
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N

PCIE_RX15P
PCIE_RX15N

Clock

Clock

PCIE_REFCLKP
PCIE_REFCLKN

PERSTB

PART 1 OF 7

PART 1 OF 7

P

P
C

C
I

I

-

­E

E
X

X
P

P
R

R
E

E
S

S
S

S

I

I
N

N
T

T
E

E
R

R
F

F
A

A
C

C
E

E

TP7

TP7
35mil

35mil

TP8

TP8
35mil

35mil

TP9

TP9
35mil

35mil

TP10

TP10
35mil

35mil

TP15

TP15
35mil

35mil

TP16

TP16
35mil

35mil

TP17

TP17
35mil

35mil

TP18

TP18
35mil

35mil

TP23

TP23
35mil

35mil

TP24

TP24
35mil

35mil

TP25

TP25
35mil

35mil

TP26

TP26
35mil

35mil

PERST#_buf1

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

PCIE_TX8P

PCIE_TX8N

PCIE_TX9P

PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

Calibration

Calibration

PCIE_CALRN
PCIE_CALRP

PCIE_CALI

3

AG31
AG30

AF31
AF30

AF28
AF27

AD31
AD30

AD28
AD27

AB31
AB30

AB28
AB27

AA31
AA30

AA28
AA27

W31
W30

W28
W27

V31
V30

V28
V27

U31
U30

U28
U27

R31
R30

AG26
AJ27

AK29

R8 2.0KR8 2.0K
R9 1.27KR9 1.27K

R10 2.0KR10 2.0K

+PCIE_VDDC

2

GFXTp0_PERp0 1
GFXTn0_PERn0 1

GFXTp1_PERp1 1
GFXTn1_PERn1 1

GFXTp2_PERp2 1
GFXTn2_PERn2 1

GFXTp3_PERp3 1
GFXTn3_PERn3 1

GFXTp4_PERp4 1
GFXTn4_PERn4 1

GFXTp5_PERp5 1
GFXTn5_PERn5 1

GFXTp6_PERp6 1
GFXTn6_PERn6 1

GFXTp7_PERp7 1
GFXTn7_PERn7 1

GFXTp8_PERp8 1
GFXTn8_PERn8 1PETn8_GFXRn81

GFXTp9_PERp9 1
GFXTn9_PERn9 1

GFXTp10_PERp10 1
GFXTn10_PERn10 1

GFXTp11_PERp11 1
GFXTn11_PERn11 1

GFXTp12_PERp12 1
GFXTn12_PERn12 1

GFXTp13_PERp13 1
GFXTn13_PERn13 1

GFXTp14_PERp14 1
GFXTn14_PERn14 1

GFXTp15_PERp15 1
GFXTn15_PERn15 1

1

For Tektronix LA only

Place close
to ASIC

A A

5

4

RV630

RV630

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- ASIC PCIE I/F

RV630 DDR2- ASIC PCIE I/F

RV630 DDR2- ASIC PCIE I/F

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

3

2

Date: Sheet

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

4

4

221Friday, April 13, 2007

221Friday, April 13, 2007

221Friday, April 13, 2007

4

of

of

of

www.vinafix.vn

5

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 10%, 0805, 6.3V, 1.4MM MAX THICK
1uF, X6S, 10%, 0402, 6.3V
100nF, X7R, 10%, 0402
10nF , X7R, 10%, 0402

D D

R107 0RR107 0R

+1.8V

+12V_BUS

MR108

MR108
10K

10K

LVT_EN4,14

+3.3V

C C

MR1090RMR109
0R

Share one pad

B B

+3.3V_BUS

B80

B80
BLM15BD121SN1

BLM15BD121SN1

1uF_6.3V

1uF_6.3V

A A

R1090RR109
0R
DNI

+3.3V

BUO

TP40

TP40
35mil

35mil

TP41

TP41
35mil

35mil

C81

C81

C82

C82
12pF

12pF

2 1

C83

C83
12pF

12pF

Y82

Y82

27.000MHz_10PPM

27.000MHz_10PPM

SI2304DS

SI2304DS

SI2304DS

SI2304DS

R108 0RDNIR108 0RDNI

TR40

TR40

4.7K

4.7K

DNI

Q100

Q100

32

1

1

32

Q101

Q101

I2C DEVICE ADDRESS' ON DDC3

DEVICE
LM63

TR41

TR41

DP

4.7K

4.7K

BUO

XTALOUT_S
is done for
ease of layout

XTALOUT_S

4

2

C80

C80
100nF

100nF

XTALIN_S

XTALOUT_S

5

T2XCM15
T2XCP15

T2X0M15

T2X0P15

T2X1M15

T2X1P15

T2X2M15

T2X2P15

T2X3M15

T2X3P15

T2X4M15

T2X4P15

T2X5M15

T2X5P15

+T2PVDD

DDC3DATA13,18

Y81

Y81

VCC

GND

27.000MHz

27.000MHz

Use 0R

BLM15BD121SN1

BLM15BD121SN1

BLM15BD121SN1

BLM15BD121SN1

ADDRESS
x100 1100
TBD

DDC3CLK13,18

OUT

E/D

B100

B100

R106 100RR106 100R

R100 100RR100 100R

R101 100RR101 100R

R102 100RR102 100R

R103 100RR103 100R

R104 100RR104 100R

R105 100RR105 100R

NS100

NS100

NS_VIA

NS_VIA

10uF_X6S

10uF_X6S

1 2

GND_T2PVSS

C108

C108

1uF_6.3V

1uF_6.3V

B101

B101

+3.3V

R40

R40

4.7K

4.7K

402 402

TP42

TP42
35mil

35mil

+1.8V

NR81 182RNR81 182R

3

1

R81 182RR81 182R

R841MR84
1M

Place R_RTCLK close to XTAL so the
main clock line has shortest stub

C100

C100

C109

C109

10uF_X6S

10uF_X6S

100nF

100nF

1uF_6.3V

1uF_6.3V

R41

R41

4.7K

4.7K

TEST_EN1,7

R44 110RR44 110R
C46 100nFC46 100nF

Share one pad

OSC_EN

R85 0RR85 0R

R_RTCLK

MR86 0RMR86 0R

C101

C101

100nF

100nF

R43

R43
221R

221R

C103

C103

C107

C107

+LTVDD18

+LTVDD33

CRT1DDCDATA15

CRT1DDCCLK15

CRT2DDCDATA16

CRT2DDCCLK16

DDC3DATA
DDC3CLK

GPU_DMINUS18
GPU_DPLUS18

TS_FDO18

C105

C105

100nF

100nF

PLL_TEST
TEST_EN

HPD116

SDA7

T2XCM
T2XCP

T2X0M
T2X0P

T2X1M
T2X1P

T2X2M
T2X2P

T2X3M
T2X3P

T2X4M
T2X4P

T2X5M
T2X5P

C102

C102
1uF_6.3V

1uF_6.3V

SCL7

VREFG

XTALIN
XTALOUT

R82

R82
221R

221R

4

MR82

MR82
221R

221R

Share one pad

OSC_EN 14

4

AP22
AR22

AN22
AN23

AR23
AP23

AR24
AP24

AR25
AP25

AN26
AN27

AR27
AP27

AL22

AK22

AK27

AL27

AJ26

AH26

AJ22
AN21
AN24
AN25
AN28
AP21
AP26
AR21
AR26

AJ24
AM22
AM24
AM26
AM27

AM29

AL29

AJ15
AH15

AH14
AG14

AG21

AH19
AM30

AD12

AR33
AP33

AJ5
AJ4

AG6

AK6
AM6

AK4
AM4

U1B

U1B

T2XCM
T2XCP

T2X0M
T2X0P

T2X1M
T2X1P

T2X2M
T2X2P

T2X3M
T2X3P

T2X4M
T2X4P

T2X5M
T2X5P

T2PVDD
T2PVSS

T2XVDDC_1
T2XVDDC_2

T2XVDDR_1
T2XVDDR_2

T2XVSSR_1
T2XVSSR_2
T2XVSSR_3
T2XVSSR_4
T2XVSSR_5
T2XVSSR_6
T2XVSSR_7
T2XVSSR_8
T2XVSSR_9
T2XVSSR_10
T2XVSSR_11
T2XVSSR_12
T2XVSSR_13
T2XVSSR_14

DDC1DATA
DDC1CLK

DDC2DATA
DDC2CLK

DDC3DATA
DDC3CLK

DDC4DATA
DDC4CLK

HPD1

SDA
SCL

DMINUS
DPLUS
TS_FDO

PLLTEST
TESTEN

VREFG

XTALIN
XTALOUT

RV630

RV630

Integrated

Integrated
TMDS2

TMDS2

Monitor

Monitor
Interface

Interface

MMI2C

MMI2C

Thermal

Thermal
Diode

Diode

Test

Test

PART 2 OF 7

PART 2 OF 7

V

V
I

I
D

D
E

E
O

O

&

&

M

M
U

U
L

L
T

T
I

I
M

M
E

E
D

D
I

I
A

A

Integrated

Integrated
TMDS

TMDS

TXVDDR_2
TXVDDR_3
TXVDDR_4
TXVDDR_5

TXVSSR_1
TXVSSR_2
TXVSSR_3
TXVSSR_4
TXVSSR_5
TXVSSR_6
TXVSSR_7
TXVSSR_8
TXVSSR_9

TXVSSR_10

DAC / CRT

DAC / CRT

DAC2 (TV/CRT2)

DAC2 (TV/CRT2)

TXCAM
TXCAP

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TX3M

TX3P

TX4M

TX4P

TX5M

TX5P

TPVDD

TPVSS

HSYNC
VSYNC

RSET

AVDD

AVSSQ

VDD1DI

VSS1DI

H2SYNC
V2SYNC

COMP

R2SET

A2VDDQ

A2VSSQ

VDD2DI

VSS2DI

A2VDD

AN9
AN10

AR10
AP10

AR11
AP11

AR12
AP12

AR15
AP15

AR16
AP16

AR17
AP17

AM14
AL14

AN19
AN20
AP19
AR19

AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AR18
AP18

AR31

R

AP31

RB

AR30

G

AP30

GB

AR29

B

AP29

BB

AN29
AN30

AN31

AR32

AP32

AR28

AP28

AM19

R2

AL19

R2B

AM18

G2

AL18

G2B

AM17

B2

AL17

B2B

AM15
AL15

AK18

Y

AK19

C

AK17

R2SET GND_A2VSSQ

AJ21

AL21

AK21

AH22

AG22

AM21

3

C110

C110
10nF

10nF

C114

C114
10nF

10nF

R1033 75RR1033 75R

R1036 75RR1036 75R

R1039 75RR1039 75R

R1030 499RR1030 499R

C1023

C1023
10nF

10nF

R2033 75RR2033 75R

R2036 75RR2036 75R

R2039 75RR2039 75R

R2030 715RR2030 715R

C2021

C2021
100nF

100nF

C2024

C2024
10nF

10nF

C2030

C2030
10nF

10nF

3

C2031

C2031
100nF

100nF

C111

C111
100nF

100nF

C2025

C2025
100nF

100nF

C115

C115
100nF

100nF

GND

GND

GND

GND_AVSSQRSET

C1024

C1024
100nF

100nF

GND

GND

GND

C112

C112

C113

C113

1uF_6.3V

1uF_6.3V

10uF_X6S

10uF_X6S

+TXVDDR

C117

C117

C116

C116

10uF_X6S

10uF_X6S

1uF_6.3V

1uF_6.3V

R1032 0RR1032 0R R1031 75RR1031 75R

R1035 0RR1035 0R

R1038 0RR1038 0R

C1020

C1020
10nF

10nF

+VDD1DI

C1025

C1025
1uF_6.3V

1uF_6.3V

R2032 0RR2032 0R

R2035 0RR2035 0R

R2038 0RR2038 0R

+A2VDDQ

C2022

C2022
1uF_6.3V

1uF_6.3V

+VDD2DI

NS2021 NS_VIANS2021 NS_VIA

C2026

C2026
1uF_6.3V

1uF_6.3V

GND_VSS2DI

C2033

C2033

C2032

C2032

10uF_X6S

10uF_X6S

1uF_6.3V

1uF_6.3V

+TPVDD

NS110

NS110
NS_VIA

NS_VIA

GND_TPVSS

C1021

C1021
100nF

100nF

NS1021 NS_VIANS1021 NS_VIA

GND_VSS1DI

NS2020 NS_VIANS2020 NS_VIA

12

T1XCM
T1XCP

T1X0M
T1X0P

T1X1M
T1X1P

T1X2M
T1X2P

T1X3M
T1X3P

T1X4M
T1X4P

T1X5M
T1X5P

12

R1034 75RR1034 75R

R1037 75RR1037 75R

C1022

C1022
1uF_6.3V

1uF_6.3V

12

R2031 75RR2031 75R

R2034 75RR2034 75R

R2037 75RR2037 75R

12

GND_A2VSSQ

+A2VDD

A_DAC1_R 15
A_DAC1_RB 15

A_DAC1_G 15
A_DAC1_GB 15

A_DAC1_B 15
A_DAC1_BB 15

HSYNC_DAC1 7,15
VSYNC_DAC1 7,15

+AVDD

NS1020 NS_VIANS1020 NS_VIA

GND_AVSSQ

A_DAC2_R 16
A_DAC2_RB 16

A_DAC2_G 16
A_DAC2_GB 16

A_DAC2_B 16
A_DAC2_BB 16

HSYNC_DAC2 7,16
VSYNC_DAC2 7,16

A_DAC2_Y 17
A_DAC2_C 17
A_DAC2_COMP 17

B2030 26R_600mAB2030 26R_600mA

2

Place close to ASICPlace close to ASIC

R116 182RR116 182R

R110 182RR110 182R

R111 182RR111 182R

R112 182RR112 182R

R113 182RR113 182R

R114 182RR114 182R

R115 182RR115 182R

12

+3.3V

2

T1XCM 16
T1XCP 16

T1X0M 16
T1X0P 16

T1X1M 16
T1X1P 16

T1X2M 16
T1X2P 16

T1X3M 16
T1X3P 16

T1X4M 16
T1X4P 16

T1X5M 16
T1X5P 16

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

TR RV630 - ASIC MAIN

TR RV630 - ASIC MAIN

TR RV630 - ASIC MAIN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

4

4

321Friday, April 13, 2007

321Friday, April 13, 2007

321Friday, April 13, 2007

4

of

of

of

www.vinafix.vn

C151

C151
10nF

10nF

C131

C131
100nF

100nF

C141

C141
1uF_6.3V

1uF_6.3V

B120

B120

B123

B123

R90 0RR90 0R

1

5

C152

C152
10nF

10nF

C132

C132
100nF

100nF

C142

C142
1uF_6.3V

1uF_6.3V

C125

C125
10uF_X6S

10uF_X6S

NS120 NS_VIANS120 NS_VIA

32

Q90

Q90
SI2304DS

SI2304DS

NS70 NS_VIANS70 NS_VIA

GND_PVSS

C133

C133
100nF

100nF

C126

C126
10uF_X6S

10uF_X6S

1uF_6.3V

1uF_6.3V

1 2

GND_VSSRHA

1 2

C143

C143
1uF_6.3V

1uF_6.3V

C120

C120

NS123 NS_VIANS123 NS_VIA

C154

C154
10nF

10nF

C134

C134
100nF

100nF

C144

C144
1uF_6.3V

1uF_6.3V

C127

C127
10uF_X6S

10uF_X6S

1 2

GND_VSSRHB

+DPLL_PVDD

+3.3V

C155

C155
10nF

10nF

C135

C135
100nF

100nF

C145

C145
1uF_6.3V

1uF_6.3V

C94

C94
10uF_X6S

10uF_X6S

C128

C128
10uF_X6S

10uF_X6S

C123

C123
1uF_6.3V

1uF_6.3V

C90

C90
1uF_6.3V

1uF_6.3V

C136

C136
100nF

100nF

C146

C146
1uF_6.3V

1uF_6.3V

+VDDR_3

C70

C70
1uF_6.3V

1uF_6.3V

C157

C157
10nF

10nF

C137

C137
100nF

100nF

C147

C147
1uF_6.3V

1uF_6.3V

C129

C129
10uF_X6S

10uF_X6S

C91

C91
100nF

100nF

C95

C95
1uF_6.3V

1uF_6.3V

C71

C71
100nF

100nF

C158

C158
10nF

10nF

C138

C138
100nF

100nF

C92

C92
1uF_6.3V

1uF_6.3V

C97

C97
100nF

100nF

C72

C72
10uF_X6S

10uF_X6S

C148

C148
1uF_6.3V

1uF_6.3V

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 10%, 0805, 6.3V, 1.4MM MAX THICK
1uF, X6S, 10%, 0402, 6.3V
100nF, X7R, 10%, 0402
10nF , X7R, 10%, 0402

+MVDD

C150

C150
10nF

10nF

D D

C C

B B

A A

C156

C156
100nF

100nF

C153

C153
1uF_6.3V

1uF_6.3V

+MVDD

+3.3V

C130

C130
100nF

100nF

C140

C140
1uF_6.3V

1uF_6.3V

C124

C124
10uF_X6S

10uF_X6S

BLM15BD121SN1

BLM15BD121SN1

BLM15BD121SN1

BLM15BD121SN1

LVT_EN3,14

C159

C159
10nF

10nF

C139

C139
100nF

100nF

C93

C93
100nF

100nF

C96

C96
1uF_6.3V

1uF_6.3V

4

C149

C149
1uF_6.3V

1uF_6.3V

C98

C98
100nF

100nF

+DPLL_PVDD

GND_PVSS

AE14
AE15
AE17
AF12

AR20

AP20

AR35

H35

M10
M35

D35

AP2
AR2

AN1
AP1

AR1

L22

P10

A12
A16
A20
A24
A28

B35

K10
K12
K24
K26
L14
L15
L17
L18
L19
L21

A25
A32

B25
B32

A35

A8

M1

T1
Y1

B1

D1

H1

B2
L1

C2
L2

U1E

U1E

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29

VDDRHA_1
VDDRHA_2

VDDRHB_1
VDDRHB_2

VSSRHA_1
VSSRHA_2

VSSRHB_1
VSSRHB_2

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4

VDDR4_1
VDDR4_2

VDDR5_1
VDDR5_2

DPLL_PVDD

DPLL_PVSS

MECH_1
MECH_2
MECH_3

RV630

RV630

PART 5 OF 7

PART 5 OF 7

Memory I/O

Memory I/O

Selected PLL's

Selected PLL's

Mechanical Pins

Mechanical Pins

3

C900

C900
10nF

10nF

C931

C931
100nF

100nF

C162

C162
1uF_6.3V

1uF_6.3V

C172

C172
1uF_6.3V

1uF_6.3V

C184

C184
1uF_6.3V

1uF_6.3V

C64

C64
10nF

10nF

10uF_X6S

10uF_X6S

C920

C920
1uF_6.3V

1uF_6.3V

C901

C901
100nF

100nF

C68

C68
100nF

100nF

+DPLL_VDDC

C61

C61
100nF

100nF

+PCIE_PVDD

C932

C932

GND_PCIE_PVSS

C921

C921
1uF_6.3V

1uF_6.3V

C902

C902
1uF_6.3V

1uF_6.3V

C163

C163
1uF_6.3V

1uF_6.3V

C173

C173
1uF_6.3V

1uF_6.3V

C185

C185
1uF_6.3V

1uF_6.3V

C69

C69
100nF

100nF

C65

C65
100nF

100nF

1uF_6.3V

1uF_6.3V

C62

C62
10uF_X6S

10uF_X6S

C164

C164
1uF_6.3V

1uF_6.3V

C174

C174
1uF_6.3V

1uF_6.3V

+1.8V

C66

C66

NS18 NS_VIANS18 NS_VIA

AM35

PCIE_PVDD

AM34

PCIE_PVSS

R26

PCIE_VDDC_1

W25

PCIE_VDDC_2

W26

PCIE_VDDC_3

AA25

PCIE_VDDC_4

AA26

PCIE_VDDC_5

AB25

PCIE_VDDC_6

AB26

PCIE_VDDC_7

AD26

PCIE_VDDC_8

AF26

PCIE_VDDC_9

U26

PCIE_VDDC_10

V25

PCIE_VDDC_11

V26

PCIE_VDDC_12

AL33

PCIE_VDDR_1

AM33

PCIE_VDDR_2

AN33

PCIE_VDDR_3

AN34

PCIE_VDDR_4

AN35

PCIE_VDDR_5

PCI-Express

PCI-Express

P

P
O

O
W

W
E

E

Core

Core

R

R

PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40
VDDC_41
VDDC_42
VDDC_43
VDDC_44

BBP_1
BBP_2

VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4

VDD_CT_1
VDD_CT_2
VDD_CT_3
VDD_CT_4
VDD_CT_5
VDD_CT_6
VDD_CT_7
VDD_CT_8

MPVDD

MPVSS

DPLL_VDDC

AP34
AP35
AR34

N13
R18
W11
AB19
AC23
AE18
AE19
AE21
AE22
N15
N18
N21
N23
P14
P17
P19
P22
R13
R15
R21
R23
U14
U17
U19
U22
V15
V18
V21
V23
W14
W17
W19
W22
AA15
AA18
AA21
AA23
AB14
AB17
AB22
AC13
AC15
AC18
AC21

U13
V13

M12
M24
P11
P25

R11
R25
U11
U25
AA11
AB11
AD10
AF10

A14

B15

AG19

+DPLL_VDDC

C78

C78
100nF

100nF

+MPVDD

GND_MPVSS

C930

C930
1uF_6.3V

1uF_6.3V

C161

C161
1uF_6.3V

1uF_6.3V

C171

C171
1uF_6.3V

1uF_6.3V

C160

C160
1uF_6.3V

1uF_6.3V

+VDDC

GND_PVSS

C79

C79
100nF

100nF

C60

C60
1uF_6.3V

1uF_6.3V

B930

B930

BLM15BD121SN1

BLM15BD121SN1

12

C922

C922
1uF_6.3V

1uF_6.3V

C903

C903
10nF

10nF

C165

C165
1uF_6.3V

1uF_6.3V

C175

C175
1uF_6.3V

1uF_6.3V

C186

C186
1uF_6.3V

1uF_6.3V

C67

C67

10uF_X6S

10uF_X6S

2

+1.8V

C923

C923
1uF_6.3V

1uF_6.3V

C905

C905

C904

C904

1uF_6.3V

1uF_6.3V

100nF

100nF

C166

C166
1uF_6.3V

1uF_6.3V

C176

C176
1uF_6.3V

1uF_6.3V

C73

C73
100nF

100nF

+MPVDD

B67 26R_600mAB67 26R_600mA

GND_MPVSS

C924

C924
1uF_6.3V

1uF_6.3V

C167

C167
1uF_6.3V

1uF_6.3V

C177

C177
1uF_6.3V

1uF_6.3V

C76

C76
1uF_6.3V

1uF_6.3V

NS64NS_VIA NS64NS_VIA

12

C187

C187
10uF_X6S

10uF_X6S

C906

C906
1uF_6.3V

1uF_6.3V

C168

C168
1uF_6.3V

1uF_6.3V

C178

C178
1uF_6.3V

1uF_6.3V

C74

C74
100nF

100nF

C925

C925
1uF_6.3V

1uF_6.3V

+VDDCI

C926

C926
10uF_X6S

10uF_X6S

C907

C907
1uF_6.3V

1uF_6.3V

C170

C170

C169

C169

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C180

C180

C179

C179

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C188

C188
10uF_X6S

10uF_X6S

B77 220R_2AB77 220R_2A

C75

C75
1uF_6.3V

1uF_6.3V

+VDDC

Install only one of these two

+PCIE_VDDC

C189

C189
10uF_X6S

10uF_X6S

+PCIE_VDDR

C181

C181
10uF_X6S

10uF_X6S

+VDDC

C77

C77
10uF_X6S

10uF_X6S

B60

B60
BLM15BD121SN1

BLM15BD121SN1

MB60

MB60
BLM15BD121SN1

BLM15BD121SN1

Install only one of these two

R9000RR900
0R

+VDDC

C182

C182

C183

C183

10uF_X6S

10uF_X6S

10uF_X6S

10uF_X6S

+1.1V

+VDDC

1

B920 220R_2AB920 220R_2A

R920 0RR920 0R

+1.8V

+VDDC

+1.1V

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- ASIC POWERS

RV630 DDR2- ASIC POWERS

RV630 DDR2- ASIC POWERS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

4

4

421Friday, April 13, 2007

421Friday, April 13, 2007

421Friday, April 13, 2007

4

of

of

of

www.vinafix.vn

5

4

3

2

1

+MVDD

+MVDD

R291

R291
100R

100R

1%

R292

R292
100R

100R

1%

R293

R293
100R

100R

1%

R294

R294
100R

100R

1%

DQA_[63..0]8

U1C

U1C

DQA_0

P27
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MVREFD_0 MVREFD_1

C292

C292

C291

C291

10nF

10nF

100nF

100nF

MVREFS_0

C294

C294

C293

C293

10nF

10nF

100nF

100nF

DQA_0

P28

DQA_1

P31

DQA_2

P32

DQA_3

M27

DQA_4

K29

DQA_5

K31

DQA_6

K32

DQA_7

M33

DQA_8

M34

DQA_9

L34

DQA_10

L35

DQA_11

J33

DQA_12

J34

DQA_13

H33

DQA_14

H34

DQA_15

K27

DQA_16

J29

DQA_17

J30

DQA_18

J31

DQA_19

F29

DQA_20

F32

DQA_21

D30

DQA_22

D32

DQA_23

G33

DQA_24

G34

DQA_25

G35

DQA_26

F34

DQA_27

D34

DQA_28

C34

DQA_29

C35

DQA_30

B34

DQA_31

C24

DQA_32

B24

DQA_33

B23

DQA_34

A23

DQA_35

C21

DQA_36

B21

DQA_37

C20

DQA_38

B20

DQA_39

J22

DQA_40

H22

DQA_41

F22

DQA_42

D21

DQA_43

J19

DQA_44

G19

DQA_45

F19

DQA_46

D19

DQA_47

C19

DQA_48

B19

DQA_49

A19

DQA_50

B18

DQA_51

C16

DQA_52

B16

DQA_53

C15

DQA_54

A15

DQA_55

H18

DQA_56

F18

DQA_57

E18

DQA_58

D18

DQA_59

J17

DQA_60

G15

DQA_61

E15

DQA_62

D15

DQA_63

N35

MVREFDA

N34

MVREFSA

RV630

RV630

Part 3 of 7

Part 3 of 7

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9
MAA_10
MAA_11

MAA_A12
MAA_BA0
MAA_BA1
MAA_BA2

DQMAB_0
DQMAB_1
DQMAB_2
DQMAB_3
DQMAB_4
DQMAB_5
DQMAB_6
DQMAB_7

MEMORY INTERFACE A

MEMORY INTERFACE A

DDR1 DDR2 DDR3

DDR1 DDR2 DDR3

Not usedbidir. strobe

Not usedbidir. strobe

bidir. differential strobe

bidir. differential strobe

For DDR2

For DDR2

write stroberead strobe

write stroberead strobe

QSA_0

QSA_1

QSA_2

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B

ODTA0

ODTA1

CLKA0

CLKA0B

CKEA0

RASA0B

CASA0B

WEA0B

CSA0B_0
CSA0B_1

CLKA1

CLKA1B

CKEA1

RASA1B

CASA1B

WEA1B

CSA1B_0
CSA1B_1

MAA_0

C27

MAA_1

B28

MAA_2

B27

MAA_3

G26

MAA_4

F27

MAA_5

E27

MAA_6

D27

MAA_7

J27

MAA_8

E29

MAA_9

C30

MAA_10

E26

MAA_11

A27

MAA_12

G27

MAA_BA0

TP200

MAA_BA1

DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

ODTA0 8

CLKA0 8
CLKA0b 8

CKEA0 8

RASA0b 8

CASA0b 8

WEA0b 8

CSA0b_0 8

CLKA1 8
CLKA1b 8

CKEA1 8

RASA1b 8

CASA1b 8

WEA1b 8

CSA1b_0 8

TP200
35mil

35mil

C28
B29
D26

M29
K33
G30
E33
C22
H21
C17
G17

M30
K34
G31
E34
B22
F21
B17
D17

M31
K35
G32
E35
A22
E21
A17
E17

C31
C25

A33
B33

B31

A31

C32

C29

A30
B30

A26
B26

F24

D24

H26

D22

G24
H24

MAA_[12..0] 8

MAA_BA[1..0] 8

DQMAb_[7..0] 8

QSA_[7..0] 8

+MVDD

+MVDD

R391

R391
100R

100R

1%

R392

R392
100R

100R

1%

R393

R393
100R

100R

1%

R394

R394
100R

100R

1%

C391

C391
100nF

100nF

C393

C393
100nF

100nF

C392

C392
10nF

10nF

C394

C394
10nF

10nF

MVREFS_1

DQB_[63..0]9

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

R296

R296

R297

R297

4.7K

4.7K

4.7K

4.7K

R298

R298
243R

243R

H15
G14
E14
D14
H12
G12
F12
D10
B13
C12
B12
B11

J10
H10
F10

AA2
AA1

W9

W7

W6

W4

B14
A13

AA4

AA8

AA7

AA5

C9
B9
A9
B8

D9
G7
G6
F6
D6
C8
C7
B7
A7
B5
A5
C4
B4
M3
M2
N2
N1
R3
R2
T3
T2
M8
M7
P5
P4
R9
R8
R6
U4
U3
U2
U1
V2
Y3
Y2

U9
U7
U6
V4

U1D

U1D

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

MVREFDB
MVREFSB

DRAM_RST

TEST_MCLK

TEST_YCLK

MEMTEST

RV630

RV630

Part 4 of 7

Part 4 of 7

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8

MAB_9
MAB_10
MAB_11

MAB_A12
MAB_BA0
MAB_BA1
MAB_BA2

DQMBB_0
DQMBB_1
DQMBB_2
DQMBB_3
DQMBB_4
DQMBB_5
DQMBB_6
DQMBB_7

MEMORY INTERFACE B

MEMORY INTERFACE B

DDR1 DDR2 DDR3

DDR1 DDR2 DDR3

Not usedbidir. strobe

Not usedbidir. strobe

bidir. differential strobe

bidir. differential strobe

For DDR2

For DDR2

write strobe

write strobe

read strobe

read strobe

QSB_0

QSB_1

QSB_2

QSB_3

QSB_4

QSB_5

QSB_6

QSB_7

QSB_0B
QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B

ODTB0

ODTB1

CLKB0
CLKB0B

CKEB0

RASB0B

CASB0B

WEB0B

CSB0B_0
CSB0B_1

CLKB1
CLKB1B

CKEB1

RASB1B

CASB1B

WEB1B

CSB1B_0
CSB1B_1

MAB_0

H2

MAB_1

H3

MAB_2

J3

MAB_3

J5

MAB_4

J4

MAB_5

J6

MAB_6

G5

MAB_7

J9

MAB_8

F3

MAB_9

F4

MAB_10

J1

MAB_11

J2

MAB_12

J7

MAB_BA0

TP300

TP300

G2

MAB_BA1

35mil

35mil

G3
F1

DQMBb_0

D12

DQMBb_1

C10

DQMBb_2

E7

DQMBb_3

C6

DQMBb_4

P3

DQMBb_5

R4

DQMBb_6

W3

DQMBb_7

V8

QSB_0

J14

QSB_1

B10

QSB_2

F9

QSB_3

B6

QSB_4

P2

QSB_5

P8

QSB_6

W2

QSB_7

V6

H14
A10
E9
A6
P1
P7
W1
V5

D2

ODTB0 9

K5

A3

CLKB0 9

B3

CLKB0b 9

E3

CKEB0 9

D3

RASB0b 9

C1

CASB0b 9

F2

WEB0b 9

E1

CSB0b_0 9

E2

K1

CLKB1 9

K2

CLKB1b 9

K8

CKEB1 9

K7

RASB1b 9

K4

CASB1b 9

M6

WEB1b 9

L3

CSB1b_0 9

M4

MAB_[12..0] 9

MAB_BA[1..0] 9

DQMBb_[7..0] 9

QSB_[7..0] 9

D D

C C

B B

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- ASIC MEM

RV630 DDR2- ASIC MEM

RV630 DDR2- ASIC MEM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

4

4

521Friday, April 13, 2007

521Friday, April 13, 2007

521Friday, April 13, 2007

4

of

of

of

www.vinafix.vn

5

D D

C C

B B

A A

5

4

U1F

U1F

P33

PCIE_VSS_1

V29

PCIE_VSS_2

AB32

PCIE_VSS_3

AG29

PCIE_VSS_4

AJ29

PCIE_VSS_5

AJ32

PCIE_VSS_6

AK32

PCIE_VSS_7

AL34

PCIE_VSS_8

AL35

PCIE_VSS_9

P34

PCIE_VSS_10

P35

PCIE_VSS_11

R27

PCIE_VSS_12

R28

PCIE_VSS_13

R29

PCIE_VSS_14

R32

PCIE_VSS_15

R33

PCIE_VSS_16

T33

PCIE_VSS_17

U29

PCIE_VSS_18

U32

PCIE_VSS_19

V32

PCIE_VSS_20

V34

PCIE_VSS_21

V35

PCIE_VSS_22

W29

PCIE_VSS_23

W32

PCIE_VSS_24

W33

PCIE_VSS_25

Y33

PCIE_VSS_26

AA29

PCIE_VSS_27

AA32

PCIE_VSS_28

AB29

PCIE_VSS_29

AB34

PCIE_VSS_30

AB35

PCIE_VSS_31

AC33

PCIE_VSS_43

AD29

PCIE_VSS_32

AD32

PCIE_VSS_33

AD33

PCIE_VSS_34

AF29

PCIE_VSS_35

AF32

PCIE_VSS_36

AF34

PCIE_VSS_37

AF35

PCIE_VSS_38

AG27

PCIE_VSS_39

AG32

PCIE_VSS_40

AG33

PCIE_VSS_41

AH33

PCIE_VSS_42

A2

VSS_1

P15

VSS_2

R14

VSS_3

V1

VSS_4

W8

VSS_5

AA19

VSS_6

AC17

VSS_7

AF19

VSS_8

AK3

VSS_9

A4

VSS_10

C18

VSS_11

E22

VSS_12

G4

VSS_13

J18

VSS_14

K17

VSS_15

M28

VSS_16

P6

VSS_17

P9

VSS_18

P13

VSS_19

P18

VSS_20

P21

VSS_21

P23

VSS_22

P26

VSS_23

P29

VSS_24

P30

VSS_25

R1

VSS_26

R5

VSS_27

R7

VSS_28

R10

VSS_29

R17

VSS_30

R19

VSS_31

R22

VSS_32

U5

VSS_33

U8

VSS_34

U10

VSS_35

U15

VSS_36

U18

VSS_37

U21

VSS_38

U23

VSS_39

V3

VSS_40

V7

VSS_41

V9

VSS_42

V10

VSS_43

V11

VSS_44

V14

VSS_45

V17

VSS_46

V19

VSS_47

V22

VSS_48

W5

VSS_49

W10

VSS_50

W15

VSS_51

W18

VSS_52

W21

VSS_53

W23

VSS_54

AA3

VSS_55

AA6

VSS_56

AA10

VSS_57

AA14

VSS_58

AA17

VSS_59

AA22

VSS_60

AB5

VSS_61

AB8

VSS_62

AB10

VSS_63

AB13

VSS_64

AB15

VSS_65

AB18

VSS_66

AB21

VSS_67

AB23

VSS_68

AC14

VSS_69

AC19

VSS_70

AC22

VSS_71

AD6

VSS_72

AD24

VSS_73

AF6

VSS_74

AF9

VSS_75

AF14

VSS_76

AF15

VSS_77

AF17

VSS_78

AF18

VSS_79

AF21

VSS_80

AF22

VSS_81

AF24

VSS_82

AG10

VSS_83

AG12

VSS_84

AH21

VSS_85

RV630

RV630

4

Part 6 of 7

Part 6 of 7

PCI-Express GND

PCI-Express GND

CORE GND

CORE GND

3

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166

3

VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

TXCBP
TXCBM

BBN_1
BBN_2

AJ14
AJ17
AJ18
AJ19
AK9
AK10
AK12
AK15
AK30
AM1
AN3
AN6
AN32
AR8
A11
A18
A21
A29
A34
C3
C5
C11
C13
C14
C23
C26
C33
D4
D7
D29
D33
E10
E12
E19
E24
F7
F14
F15
F17
F26
F30
F33
F35
G1
G9
G10
G18
G21
G22
G29
H17
H19
J12
J15
J21
J24
J26
J32
J35
K3
K6
K9
K14
K15
K18
K19
K21
K22
K28
K30
L33
M5
M9
M26
M32
N3
N14
N17
N19
N22
N33

AP14
AR14

W13
AA13

2

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- ASIC GROUNDS

RV630 DDR2- ASIC GROUNDS

RV630 DDR2- ASIC GROUNDS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

1

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

4

4

621Friday, April 13, 2007

621Friday, April 13, 2007

621Friday, April 13, 2007

4

of

of

of

www.vinafix.vn

5

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7

D D

TP84

TP84
35mil

35mil

TP85

TP85

DVOCLK

35mil

35mil

TP86

TP86

DVPCNTL_0

35mil

35mil

TP87

TP87

DVPCNTL_1

35mil

35mil

TP88

TP88

DVPCNTL_2

35mil

35mil

TP89

TP89

DVP_MVP_CNTL_0

35mil

35mil

DVP_MVP_CNTL_1

TP60

TP60
35mil

35mil

TP61

TP61

DVPDATA_0

35mil

35mil

TP62

TP62

DVPDATA_1

TP63

TP63

35mil

35mil

DVPDATA_2

35mil

35mil

TP64

TP64

DVPDATA_3

35mil

35mil

TP65

TP65

DVPDATA_4

TP66

TP66

35mil

35mil

DVPDATA_5

35mil

35mil

TP67

TP67

DVPDATA_6

TP68

TP68

35mil

35mil

DVPDATA_7

35mil

35mil

TP69

TP69

DVPDATA_8

35mil

35mil

TP70

TP70

DVPDATA_9

35mil

35mil

TP71

TP71

DVPDATA_10

35mil

35mil

TP72

TP72

DVPDATA_11

35mil

35mil

TP73

TP73

DVPDATA_12

35mil

35mil

TP74

TP74

DVPDATA_13

TP75

TP75

35mil

35mil

DVPDATA_14

35mil

35mil

TP76

TP76

DVPDATA_15

35mil

35mil

TP77

TP77

DVPDATA_16

TP78

TP78

35mil

35mil

C C

B B

35mil

35mil

TP79

TP79
TP80

TP80

35mil

35mil
35mil

35mil

TP81

TP81
35mil

35mil

TP82

TP82
35mil

35mil

TP83

TP83
35mil

35mil

DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

AM12

AL12

AJ12
AH12
AM10

AL10

AJ10
AH10

AL7

AM9
AL9

AJ9

AK7

AH1
AG1
AH3
AH2
AN8
AP8

AJ3
AJ2

AJ1
AK2
AK1
AL3
AL2
AL1
AM3
AM2
AN2
AP3
AR3
AN4
AR4
AP4
AN5
AR5
AP5
AP6
AR6
AN7
AP7
AR7

U1G

U1G

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7

VPCLK0

VHAD_0
VHAD_1

VPHCTL

VIPCLK

DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_MVP_0
DVPCNTL_MVP_1

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

RV630

RV630

VIP

VIP
Capture

Capture

VIP

VIP
Host

Host

PART7OF7

PART7OF7

General

General
Purpose

Purpose
I/O

I/O

GPIO_15_PWRCNTL_0

GPIO_17_THERMAL_INT

GPIO_20_PWRCNTL_1

GPIO_23_CLKREQB

RESERVED

RESERVED

No Connect

No Connect

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_11
GPIO_12
GPIO_13

GPIO_14_HPD2

GPIO_16_SSIN

GPIO_18_HPD3
GPIO_19_CTFB

GPIO_21_BB_EN

GPIO_22_ROMCSB

GPIO_24_JMODE

GPIO_25_TDI

GPIO_26_TCK
GPIO_27_TMS
GPIO_28_TDO

GENERICA
GENERICB

GENERICC

DVALID

PSYNC

RSVD_12

RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8

RSVD_9
RSVD_10
RSVD_11

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9

NC_10

4

GPIO_0

AG2

GPIO_1

AF2

GPIO_2

AF1
AE3
AE2
AE1
AD3
AD2
AD1
AD5
AD4
AC3
AC2
AC1
AB3
AB2
AB1
AF5
AF4
AG4
AG3
AD9
AD8
AD7
AB4
AB6
AB7
AB9
AA9

AF8
AF7
AG5

AJ7
AM7

AJ6

AF3
AH24
AK24
AK26
AK34
AK35
AL24
AL26
AG7
AG9
AG24

AG15
AG17
AG18
AH17
AH18
AP13
AP9
AR13
AR9
AK14

JTAG_MODE
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13

HPD2
PWRCNTL_0
GPIO_16
ThermINT
GPIO_18
CTFb
PWRCNTL_1
GPIO21_BB_EN
GPIO_22

GENERICB
GENERICC

DVALID
PSYNC

GPIO_3
GPIO_4
GPIO_5
GPIO_6

PCIE_CLK_REQb

JTAG_MODE 1
JTAG_TDI 1
JTAG_TCK 1
JTAG_TMS 1

JTAG_TDO 1

GENERICA 17

HPD2 15
PWRCNTL_0 13

ThermINT 18

CTFb 13

TP51

TP51
35mil

35mil
TP52

TP52
35mil

35mil

3

DNI

MR50 10KMR50 10K

DNI

MR51 10KMR51 10K

MR52 10KMR52 10K

MR53 10KMR53 10K

MR54 10KMR54 10K

+3.3V

BUO

TR50

TR50

TP50

TP50
35mil

35mil

10K

10K

MR55 10KMR55 10K

MR56 10KMR56 10K

MR58 10KMR58 10K

MR59 10KMR59 10K

MR63 10KMR63 10K

MR62 10KMR62 10K

MR61 10KMR61 10K

MR65 10KMR65 10K

DNI

MR64 10KMR64 10K

MR66 10KMR66 10K

MR67 10KMR67 10K

MR68 10KMR68 10K

MR69 10KMR69 10K

MR70 10KMR70 10K

MR71 10KMR71 10K

MR72 10KMR72 10K

MR73 10KMR73 10K

MR74 10KMR74 10K

MR75 10KMR75 10K

MR76 10KMR76 10K

MR77 10KMR77 10K

MR78 10KMR78 10K

MR88 10KMR88 10K

MR79 10KMR79 10K

MR60 10KMR60 10K

DNI

MR87 10KMR87 10K

+3.3V

DNI

DNI

DNI

DNI

NR55 1KNR55 1K

DNI

NTSC
DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

TBD

DNI

DNI

DNI

DNI

DNI

2

R50 10KR50 10K

R51 10KR51 10K

R52 10KR52 10K

R53 10KR53 10K

R54 10KR54 10K

R55 10KR55 10K

R56 10KR56 10K

R57 10KR57 10K
R58 10KR58 10K

R59 10KR59 10K

R63 10KR63 10K

R62 10KR62 10K

R61 10KR61 10K

R65 10KR65 10K

R64 10KR64 10K

R66 10KR66 10K

R67 10KR67 10K

R68 10KR68 10K

R69 10KR69 10K

R70 10KR70 10K

R71 10KR71 10K

R72 10KR72 10K

R73 10KR73 10K

R74 10KR74 10K

R75 10KR75 10K

R76 10KR76 10K

R77 10KR77 10K

R78 10KR78 10K

R88 10KR88 10K

R79 10KR79 10K

R60 10KR60 10K

R87 10KR87 10K

PIN BASED STRAPS

GPIO_0

GPIO_1

GPIO_1

GPIO_2

GPIO_2

GPIO_3

GPIO_3

GPIO_4

GPIO_5GPIO_5

GPIO_6

GPIO_7GPIO_7

GPIO_8

GPIO_9

GPIO_13

GPIO_13

GPIO_12

GPIO_12

GPIO_11

GPIO_11

GENERICC

GENERICB

VSYNC_DAC1

VSYNC_DAC1

HSYNC_DAC1

PSYNC

PSYNC

GPIO21_BB_EN

GPIO21_BB_EN

VID_0

VID_0

VID_1

VID_1

VID_2

VID_2

VID_3

VID_3

VID_4

VID_4

VID_5

VID_5

VID_6

VID_6

VID_7

VID_7

DVALID

DVALID

GPIO_16

CONFIG[3]

CONFIG[2]

CONFIG[1]

CONFIG[0]

GPIO_18

SW1A

SW1A

41

DIP_SWX2

DIP_SWX2

VSYNC_DAC1 3,15

HSYNC_DAC1 3,15

VSYNC_DAC2 3,16

HSYNC_DAC2 3,16

SW1B

SW1B

32

DIP_SWX2

DIP_SWX2

1

GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)

0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)

0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)

ATI Internal Use Only - Reserved (Default: 00)

DEBUG_ACCESS
ATI Internal Use Only - Reserved (Default: 0)

ATI Internal Use Only - Reserved (Default: 0)

ATI Internal Use Only - Reserved (Default: 0)

TV OUT STANDARD (Jumper position overwrite resistor settings)

0 - PAL TVO (Jumper is closed)
1 - NTSC TVO (Jumper is open)

ATI Internal Use Only - Reserved (Default: 0)

GPIO(9,13:11) - CONFIG[3..0]

0010 - 512Kbit AT25F512A (Atmel)
0011 - 1Mbit AT25F1024A (Atmel)
0100 - 512Kbit M25P05A (ST)
0101 - 1Mbit M25P10A (ST)
0101 - 2Mbit M25P20 (ST)
0100 - 512Kbit Pm25LV512 (Chingis)
0101 - 1Mbit Pm25LV010 (Chingis)

ATI Internal Use Only - Reserved (Default: 0)

VIP_DEVICE_STRAP_EN

0: Slave VIP host port devices present (use if Theater is populated)
1: No slave VIP host port devices reporting presence during reset (use for
configurations without video-in)

ATI Internal Use Only - Reserved

VGA DISABLE : 1 for disable (set to 0 for normal operation)

ATI Internal Use Only - Reserved (Default: 0)

ATI Internal Use Only - Reserved (Default: 0)

MSI_DIS (Default: 0)

ATI Internal Use Only - Reserved (Default: 0)

BIF_AUDIO_EN
0 - Disable HD Audio 1- Enable HD Audio

ATI Internal Use Only - Reserved (Default: 0)

64BAR_EN_A (Default: 0)

ATI Internal Use Only - Reserved (Default: 0)

ATI Internal Use Only - Reserved (Default: 0)

ATI Board Feature IMEMORY CONFIG

VSYNC_DAC2

CHECK ATI MEMORY
TUNING DOCUMENT

GPIO18

BIF_CLK_PM_EN
0 - Disable CLKREQ# power management capability
1 - Enable CLKREQ# power management capability

ATI PCIE FEATURE I

ATI PCIE FEATURE II

Pull-Down Resistors are for BU until built-in pull-downs are verified.

TR58 0RTR58 0R

TP47

TP47

TP46

TP46

35mil

35mil

35mil

35mil

Place it at top edge of the
board on the bottom side.

It is not intended for
production

+3.3V

TC47

TC47

100nF

100nF

A A

Mating connector: 6010028300G
(HEADER 2X8 1.27MM PITCH, SMD)

5

JTAG_MODE

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO

1
3
5
7

9
11
13
15

BUO

TJ47

TJ47

2
4
6
8
10
12
14
16

2X8SOCKET

2X8SOCKET

+EXT_ADJ
GPIO_8
GPIO_22
GPIO_9
GPIO_10
SDA
SCL

TC46

TC46

100nF

100nF

TR47

TR47

4.7K

4.7K

+3.3V+5V

TEST_EN 1,3

TR48

TR48

4.7K

4.7K
BUOBUO

4

SDA 3

SCL 3

GPIO_8

GPIO_9

GPIO_10

GPIO_22

+3.3V

R45

R45
10K

10K

MR45

MR45
10K

10K

+3.3V

C47

C47
100nF

100nF

+3.3V

3

R46

R46
10K

10K

U2

U2

5

6

1

7

3

8

M25P05-AVNM6P

M25P05-AVNM6P

D

C

S

HOLD

W

VCC

2

Q

4

VSS

BIOS1

BIOS1

BIOS

BIOS

113-B149XX-XXX

113-B149XX-XXX
VIDEO BIOS
FIRMWARE

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- ASIC DVO-BOOT SRAPS

RV630 DDR2- ASIC DVO-BOOT SRAPS

RV630 DDR2- ASIC DVO-BOOT SRAPS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

4

4

721Friday, April 13, 2007

721Friday, April 13, 2007

721Friday, April 13, 2007

4

of

of

of

www.vinafix.vn

8

7

6

5

4

3

2

1

CHANNEL A: 128MB/256MB DDR2

DQA_[63..0]5

D D

MAA_BA[1..0]5

MAA_[12..0]5

C C

+MVDD +MVDD +MVDD

R201

R201

4.99K

4.99K

R202

R202

4.99K

4.99K

VREF_A0

VREF_A0

VREF_U201

C202

C202
100nF_6.3V

100nF_6.3V

MAA_BA0
MAA_BA1

MAA_12
MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

CLKA0b5
CLKA05

CKEA05

CSA0b_05

WEA0b5

RASA0b5

CASA0b5

DQMAb_3
DQMAb_0

ODTA05

QSA_3

QSA_0

U201

U201

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

U202

DQA_3

B9

DQA_5

B1

DQA_0

D9

DQA_4

D1

DQA_7

D3

DQA_1

D7

DQA_6

C2

DQ9

DQA_2

C8

DQ8

DQA_27

F9

DQ7

DQA_28

F1

DQ6

DQA_26

H9

DQ5

DQA_31

H1

DQ4

DQA_30

H3

DQ3

DQA_24

H7

DQ2

DQA_29

G2

DQ1

DQA_25

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

B201

B201
220R_200mA

220R_200mA

C200

C200
100nF_6.3V

100nF_6.3V

C201

C201
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

MAA_BA0
MAA_BA1

MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

CLKA0b5
CLKA05

CKEA05

CSA0b_05

WEA0b5

RASA0b5

CASA0b5

DQMAb_1
DQMAb_2

ODTA05 ODTA05 ODTA05

QSA_1 QSA_5

VREF_A0

QSA_2

VREF_A0

R203

R203

4.99K

4.99K

VREF_U202

R204

R204

C205

C205

4.99K

4.99K

100nF_6.3V

100nF_6.3V

U202

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

DQA_18

B9

DQA_23

B1

DQA_16

D9

DQA_19MAA_12

D1

DQA_22

D3

DQA_17

D7

DQA_21

C2

DQ9

DQA_20

C8

DQ8

DQA_12

F9

DQ7

DQA_11

F1

DQ6

DQA_15

H9

DQ5

DQA_9

H1

DQ4

DQA_8

H3

DQ3

DQA_14

H7

DQ2

DQA_10

G2

DQ1

DQA_13

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

C203

C203
100nF_6.3V

100nF_6.3V

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

B202

B202
220R_200mA

220R_200mA

C204

C204
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

MAA_BA0
MAA_BA1

MAA_12
MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

CLKA1b5
CLKA15

CKEA15

CSA1b_05

WEA1b5

RASA1b5

CASA1b5

DQMAb_4 DQMAb_7

VREF_A1

QSA_4

VREF_A1

R205

R205

4.99K

4.99K

VREF_U203

C208

C208

R206

R206

100nF_6.3V

100nF_6.3V

4.99K

4.99K

U203

U203

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

DQA_34

B9

DQA_38

B1

DQA_33

D9

DQA_37

D1

DQA_39

D3

DQA_32

D7

DQA_36

C2

DQ9

DQA_35

C8

DQ8

DQA_43

F9

DQ7

DQA_45

F1

DQ6

DQA_41

H9

DQ5

DQA_47

H1

DQ4

DQA_46

H3

DQ3

DQA_42

H7

DQ2

DQA_44

G2

DQ1

DQA_40

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

C206

C206
100nF_6.3V

100nF_6.3V

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

B203

B203
220R_200mA

220R_200mA

C207

C207
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

+MVDD

R207

R207

4.99K

4.99K

R208

R208

4.99K

4.99K

VREF_A1

VREF_A1

VREF_U204

MAA_BA0
MAA_BA1

MAA_12
MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

CLKA1b5
CLKA15

CKEA15

CSA1b_05

WEA1b5

RASA1b5

CASA1b5

DQMAb_6DQMAb_5

QSA_6

QSA_7

C211

C211
100nF_6.3V

100nF_6.3V

U204

U204

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

DQA_61

B9

DQA_57

B1

DQA_60

D9

DQA_59

D1

DQA_56

D3

DQA_63

D7

DQA_58

C2

DQ9

DQA_62

C8

DQ8

DQA_52

F9

DQ7

DQA_51

F1

DQ6

DQA_55

H9

DQ5

DQA_50

H1

DQ4

DQA_48

H3

DQ3

DQA_54

H7

DQ2

DQA_49

G2

DQ1

DQA_53

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9

B204

B204

M9

220R_200mA

220R_200mA

R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

C209

C209
100nF_6.3V

100nF_6.3V

C210

C210
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

DQMAb_[7..0]5

B B

+MVDD

C239

C239
1uF_6.3V

1uF_6.3V

+MVDD

A A

C228

C228
1uF_6.3V

1uF_6.3V

+MVDD

C231

C231
1uF_6.3V

1uF_6.3V

C240

C240
1uF_6.3V

1uF_6.3V

C229

C229
1uF_6.3V

1uF_6.3V

C232

C232
1uF_6.3V

1uF_6.3V

8

DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

C241

C241
1uF_6.3V

1uF_6.3V

C230

C230
1uF_6.3V

1uF_6.3V

C233

C233
1uF_6.3V

1uF_6.3V

C242

C242
1uF_6.3V

1uF_6.3V

C234

C234
1uF_6.3V

1uF_6.3V

QSA_[7..0]5

C243

C243
1uF_6.3V

1uF_6.3V

C235

C235
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

+MVDD

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

C236

C236
1uF_6.3V

1uF_6.3V

C220

C220
1uF_6.3V

1uF_6.3V

C223

C223
1uF_6.3V

1uF_6.3V

7

C237

C237
1uF_6.3V

1uF_6.3V

C221

C221
1uF_6.3V

1uF_6.3V

C224

C224
1uF_6.3V

1uF_6.3V

C238

C238
1uF_6.3V

1uF_6.3V

C222

C222
1uF_6.3V

1uF_6.3V

C225

C225
1uF_6.3V

1uF_6.3V

C226

C226
1uF_6.3V

1uF_6.3V

C227

C227
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

6

C212

C212
1uF_6.3V

1uF_6.3V

C215

C215
1uF_6.3V

1uF_6.3V

C213

C213
1uF_6.3V

1uF_6.3V

C216

C216
1uF_6.3V

1uF_6.3V

C214

C214
1uF_6.3V

1uF_6.3V

C217

C217
1uF_6.3V

1uF_6.3V

C218

C218
1uF_6.3V

1uF_6.3V

C219

C219
1uF_6.3V

1uF_6.3V

CLKA05

CLKA0b5

CLKA15

CLKA1b5

5

R221

R221
56R

56R

R222

R222
56R

56R

R223

R223
56R

56R

R224

R224
56R

56R

C244 10nFC244 10nF

C245 10nFC245 10nF

+MVDD +MVDD

R209

R209

4.99K

4.99K

VREF_A0 VREF_A1

R210

R210

4.99K

4.99K

4

R219

R219

4.99K

4.99K

R220

R220

4.99K

4.99K

3

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- MEM CH. A

RV630 DDR2- MEM CH. A

RV630 DDR2- MEM CH. A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

105-B149xx-00

105-B149xx-00

105-B149xx-00

of

of

of

821Friday, April 13, 2007

821Friday, April 13, 2007

821Friday, April 13, 2007

1

4

4

4

www.vinafix.vn

8

7

6

5

4

3

2

1

CHANNEL B: 128MB/256MB DDR2

DQB_[63..0]5

D D

C C

MAB_BA[1..0]5

MAB_[12..0]5

+MVDD

MAB_BA0
MAB_BA1

MAB_12
MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

CLKB0b5
CLKB05

CKEB05

CSB0b_05

WEB0b5

RASB0b5

CASB0b5

DQMBb_3
DQMBb_0

ODTB05

QSB_3

VREF_B0

QSB_0

VREF_B0

R301

R301

4.99K

4.99K

VREF_U301 VREF_U302 VREF_U303 VREF_U304

R302

R302

C302

C302

4.99K

4.99K

100nF_6.3V

100nF_6.3V

U301

U301

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

U302

DQB_3

B9

DQB_5

B1

DQB_0

D9

DQB_4

D1

DQB_7

D3

DQB_1

D7

DQB_6

C2

DQ9

DQB_2

C8

DQ8

DQB_27

F9

DQ7

DQB_28

F1

DQ6

DQB_26

H9

DQ5

H1

DQ4

DQB_30

H3

DQ3

DQB_24

H7

DQ2

DQB_29

G2

DQ1

DQB_25

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9

B301

B301

M9

220R_200mA

220R_200mA

R1

J1
J7

C300

C300
100nF_6.3V

100nF_6.3V

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

C301

C301
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

+MVDD

MAB_BA0
MAB_BA1

MAB_12
MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

CLKB0b5
CLKB05

CKEB05

CSB0b_05

WEB0b5

RASB0b5

CASB0b5

DQMBb_1
DQMBb_2

ODTB05 ODTB05 ODTB05

QSB_1 QSB_5

VREF_B0

QSB_2

VREF_B0

R303

R303

4.99K

4.99K

R304

R304

C305

C305

4.99K

4.99K

100nF_6.3V

100nF_6.3V

U302

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

DQB_23

B9

DQB_17

B1

DQB_21

D9

DQB_16 DQB_37

D1

DQB_18

D3

DQB_22

D7

DQB_19

C2

DQ9

DQB_20 DQB_35

C8

DQ8

F9

DQ7

DQB_11

F1

DQ6

DQB_15

H9

DQ5

DQB_9DQB_31

H1

DQ4

DQB_8

H3

DQ3

DQB_13

H7

DQ2

DQB_10

G2

DQ1

DQB_14

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

B302

B302
220R_200mA

220R_200mA

C303

C303
100nF_6.3V

100nF_6.3V

C304

C304
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

+MVDD

MAB_BA0
MAB_BA1

MAB_12
MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

CLKB1b5
CLKB15

CKEB15

CSB1b_05

WEB1b5

RASB1b5

CASB1b5

DQMBb_4 DQMBb_7

VREF_B1

QSB_4

VREF_B1

R305

R305

4.99K

4.99K

R306

R306

C308

C308

4.99K

4.99K

100nF_6.3V

100nF_6.3V

U303

U303

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

U304

DQB_34

B9

DQB_38

B1

DQB_33

D9
D1

DQB_39

D3

DQB_32

D7

DQB_36

C2

DQ9

C8

DQ8

DQB_43

F9

DQ7

DQB_46

F1

DQ6

DQB_40

H9

DQ5

DQB_47

H1

DQ4

DQB_44

H3

DQ3

DQB_41

H7

DQ2

DQB_45

G2

DQ1

DQB_42

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

C306

C306
100nF_6.3V

100nF_6.3V

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

B303

B303
220R_200mA

220R_200mA

C307

C307
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

+MVDD

R307

R307

4.99K

4.99K

R308

R308

4.99K

4.99K

MAB_BA0
MAB_BA1

MAB_12
MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

CLKB1b5
CLKB15

CKEB15

CSB1b_05

WEB1b5

RASB1b5

CASB1b5

DQMBb_6DQMBb_5

QSB_6

VREF_B1

QSB_7

VREF_B1

C587

C587
100nF_6.3V

100nF_6.3V

U304

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

WEK3VDDQ10

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25

HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

DQB_60

B9

DQB_57

B1

DQB_61

D9

DQB_59

D1

DQB_56

D3

DQB_62

D7

DQB_58

C2

DQ9

DQB_63

C8

DQ8

DQB_53DQB_12

F9

DQ7

DQB_51

F1

DQ6

DQB_54

H9

DQ5

DQB_50

H1

DQ4

DQB_48

H3

DQ3

DQB_55

H7

DQ2

DQB_49

G2

DQ1

DQB_52

G8

DQ0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

B304

B304
220R_200mA

220R_200mA

C309

C309
100nF_6.3V

100nF_6.3V

+MVDD

+MVDD

C310

C310
1uF_6.3V

1uF_6.3V

DQMBb_[7..0]5

B B

+MVDD +MVDD

C339

C339
1uF_6.3V

1uF_6.3V

+MVDD

A A

+MVDD

C312

C312
1uF_6.3V

1uF_6.3V

C315

C315
1uF_6.3V

1uF_6.3V

C340

C340
1uF_6.3V

1uF_6.3V

C313

C313
1uF_6.3V

1uF_6.3V

C316

C316
1uF_6.3V

1uF_6.3V

8

DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7

C341

C341
1uF_6.3V

1uF_6.3V

C314

C314
1uF_6.3V

1uF_6.3V

C317

C317
1uF_6.3V

1uF_6.3V

C342

C342
1uF_6.3V

1uF_6.3V

C318

C318
1uF_6.3V

1uF_6.3V

QSB_[7..0]5

C343

C343
1uF_6.3V

1uF_6.3V

C319

C319
1uF_6.3V

1uF_6.3V

+MVDD

+MVDD

C336

C336
1uF_6.3V

1uF_6.3V

C320

C320
1uF_6.3V

1uF_6.3V

C323

C323
1uF_6.3V

1uF_6.3V

QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7

C338

C338

C337

C337

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

+MVDD

C330

C330

C329

+MVDD

6

C328

C328
1uF_6.3V

1uF_6.3V

C331

C331
1uF_6.3V

1uF_6.3V

C329
1uF_6.3V

1uF_6.3V

C332

C332
1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C333

C333
1uF_6.3V

1uF_6.3V

C334

C334
1uF_6.3V

1uF_6.3V

C335

C335
1uF_6.3V

1uF_6.3V

C322

C322

C321

C321

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C327

C327

C326

C325

C325
1uF_6.3V

1uF_6.3V

C326
1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C324

C324
1uF_6.3V

1uF_6.3V

7

CLKB05

CLKB0b5

CLKB15

CLKB1b5

5

R321

R321
56R

56R

R322

R322
56R

56R

R323

R323
56R

56R

R324

R324
56R

56R

C344 10nFC344 10nF

C345 10nFC345 10nF

4

+MVDD +MVDD

R309

R309

4.99K

4.99K

VREF_B0 VREF_B1

R310

R310

4.99K

4.99K

R319

R319

4.99K

4.99K

R320

R320

4.99K

4.99K

3

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- MEM CH. B

RV630 DDR2- MEM CH. B

RV630 DDR2- MEM CH. B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

2

105-B149xx-00

105-B149xx-00

105-B149xx-00

of

of

of

921Friday, April 13, 2007

921Friday, April 13, 2007

921Friday, April 13, 2007

1

4

4

4

www.vinafix.vn

8

D D

+PW_VDDC_HGDR

UGATE11

+PW_VDDC_M

PHASE11

+PW_VDDC_LGDR

LGATE11

VDDC2_FB13

+VDDC_B

C C

+PW_VDDC_HGD

+PW_VDDC_LGD

R1315

R1315

42.2K

42.2K

place R1315 close to IC pin4

List of supported foodprint

The following ICs are not necessarily evaluated by
ATI, please refer to BOM for evaluation status

ANPEC APW7120/APW7065 (12V)

CAT CAT7583 (12V)

INTERSIL ISL6545

NEXSEM NX2114/2307

RICHTEK RT9214/RT8101

OnSemi ON1582

uPI UP6101 (No Ext_Vref in)

B B

Layout guideline for Nexsem NX2114/2307

1-Position the controller (U703) such that LGate(pin4) is the closet to gate
of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate
of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as
short and as wide as possible to reduce the trace inductance.
2-Place the bypass capacitors for Vcc as well as Boost caps as close to the
controller as possible. They are as follows;
Vcc bypass cap is C703, and Boost cap is C705.
3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place
the rest of the compensation network close to the pins 7 and 6. These are R710,
R711, R713, C713 and R712, C711 and C712.

U1303

U1303

1

BOOT

2

UGATE

3

GND

LGATE4VCC

APW7065

APW7065

PHASE

COMP

VDDC_FB

FB

8

7

6

5

+PW_VDDC_M

VDDC_COMP

VDDC_FB

COMPENSATION CIRCUIT FILTERED SMPS VCC

402

C1311

C1311
15nF

15nF

402

A A

R1312

R1312

2.94K

2.94K

402
1%

10V
10%

VDDC_COMP

C1312

C1312
390pF

390pF

603

50V

NPOX7R

5%

R1314 0RR1314 0R

R13090RR1309
0R

share pad of R1314,R1309

8

C1314

C1314
100nF

100nF

402
X5R

10V
10%

VDDC_FB

+VDD_VCC

+VDD_VCC

7

C1303

C1303

0.22uF

0.22uF

7

+PW_VDDC_LGD

VDDC_EN 11

R1308 20KR1308 20K

+12V_BUS

R1307

R1307

2.2R

2.2R

C1307

C1307
100nF

100nF

+PW_VDDC_HGD +PW_VDDC_HGDR

+PW_VDDC_M

+PW_VDDC_LGDR

R13220RR1322

603

0R

402

BOOT CIRCUIT

+5V

MR1307

MR1307

2.2R

2.2R

603
X7R
5%

6

R1321 0RR1321 0R

3

D1301

D1301

1

BAT54A

BAT54A

C1305

C1305
100nF

100nF

603 X7R
5%

6

402

QL

2

16V

Q1302

Q1302

Thermal

Thermal

Pad

Pad

4 5
3
2
1

BSC119N03SG

BSC119N03SG

+PW_VDDC_HGDR

+PW_VDDC_M

+12V_BUS +5V

MR13060RMR1306
0R

402

C1306

C1306
150nF_16V

150nF_16V

+VDDC_B

Q1301

Q1301

QH

Thermal

Thermal

4 5
3
2
1

BSC119N03SG

BSC119N03SG

9

6
7
8

MQ1301

MQ1301

Thermal

Thermal

Pad

Pad

4 5
3
2
1

FDS7096N3

FDS7096N3

R13060RR1306
0R

402

+PW_VDDC_M

5

Pad

Pad

9

6
7
8

RC snubber values shown
are for reference only,
tuning is required

VDDC_FB

+VDDC_Source

9

6
7
8

5

ML1301

ML1301

1 2

1 2

R1319

R1319
33MOHM

33MOHM

1210
1%

C1308

C1308
10nF_25V

10nF_25V

402
X7R
25V

Place Rs and Cs across QL

PCMC104T-1R5MN

PCMC104T-1R5MN

L1301

L1301

1.7UH

1.7UH

Rs

Cs

MULTI FOOTPRINT

12

NS1300

NS1300
NS_VIA

NS_VIA

C1313

C1313

3.9nF

3.9nF

402
10%

R1

RFB1

R1313

R1313

R1311

R1311

3.65K

3.65K

4.99K

4.99K

402

402

5%

1%

R4

Place R1 and
R4 close to

RFB2

PWM and

R1310

R1310

routed with

3.24K

3.24K

separate

402

20mil trace to

1%

the ASIC

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

+PW_VDDC_LGDR

MQ1302

MQ1302

Thermal

Thermal

Pad

Pad

4 5
3
2
1

FDS7096N3

FDS7096N3

4

L1322

L1322

R13200RR1320

R13180RR1318
0R

C1349

C1349

4.7uF_16V

4.7uF_16V

805

16V
X7R

0R

C1339

C1339

4.7uF_16V

4.7uF_16V

805

IND_0.47uH_7A

IND_0.47uH_7A

3

+12V_BUS

C1395

C1395

100uF_16V

C1343

C1343
10UF_16V

10UF_16V

1206

100uF_16V
SM 6.3mm Dia

C1344

C1344

C1382

C1382

180uF_16V

180uF_16V

270uF_16V

270uF_16V

TH 10mm Dia

SM 10mm Dia

+VDDC +VDDC +VDDC

***

C1325

C1325
1500uF_2.5V

1500uF_2.5V

***

Overlap

L1323

L1323

B1301

B1301

0.47uH

0.47uH
60R

C1337

C1337

4.7uF_16V

4.7uF_16V

C1324

C1324

Y5V

10uf

10uf

1206

60R

C1330

C1330
10UF_16V

10UF_16V

1206805805

Mirrored on PCB

+VDDC

Overlap

C1340

C1340

4.7uF_16V

4.7uF_16V

Mirrored on PCBMirrored on PCB Overlap

C1323

C1323

Y5V

10uf

10uf

6.3V

1206 6.3V

Mirrored on PCB

2

+VDDC_Source

***

MC1325

MC1325
1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT8 mm Dia, SMT 8 x 8 mm, TH

***

NC1325

NC1325
820uF_2.5V

820uF_2.5V

***

1

SMPS02- Regulator for VDDC

Vout = 0.9V ~ 1.1V

9

6
7
8

4

MULTI FOOTPRINT

Part RFB2RFB1

0.8V Ref

SMPS02 Specifications

Vin 12V(power stage) +/-8% PCIe ATX12V ver. 2.2 +/-5%

Vout 2V

Vout ripple (DC) 50mVpp

Iout 6Aavg, 8Adc_max

Step load 3Amax

Protections

3

Vout

2.03V
(1.98V~2.08V)

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

2

4.99K
p/n 3160499100G

Nominal Value Adjustable range / Notes

+/-10% or 200mVpp @ 3A step loadVout ripple (AC)

TR RV630 - MVDD SMPS02

TR RV630 - MVDD SMPS02

TR RV630 - MVDD SMPS02

Custom

Custom

Custom

;

Tolerance

;

;

+2%/-2%

~300kHzSwitching Freq. TBD

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

105-B149xx-00

105-B149xx-00

105-B149xx-00

3.24K
p/n 3160324100G

1.8V ~ 2.85V

10 21Friday, April 13, 2007

10 21Friday, April 13, 2007

10 21Friday, April 13, 2007

1

of

of

of

4

4

4

www.vinafix.vn

Information on Compatable Controller Parts

Gate drive voltage 5V, 8V, 12V 5V, 8V, 12V 5V only 12V only

Bootstrap diodes Internal

Phase current adjustable
(unbalanced between phases)
Option Pin Selection

D D

Pin 12 (COMP/DROOP) COMP COMP

Pin 16 (REFOUT/POK)

Pin 21 (VCCDRV/DROOP)

External Detection Circuit and Indication

External cable not plugged in
+12V_BUS not in regulation

External cable not plugged in
+12V_BUS in regulation EN1 -> 3V (by Ri1 and Ri2)

External cable plugged in
+12V_XXX not in regulation

C C

External cable plugged in 12V_EXT_DETb = "0"
+12V_XXX in regulation

B B

Q601

Q601

UGATE1

BSC119N03SG

BSC119N03SG

PHASE1

A A

Q603

Q603

BSC042N03S

BSC042N03S

LGATE1

8

PWM IC #2 PWM IC #4PWM IC #1 PWM IC #3

0.6V 0.6V 0.6V0.6VVref

(DNP D601, D611)

Yes Yes Yes TBD

IOUT/DROOP (R662)

POK
(Open drain)

VCCDRV

Behaviour NotificationsCases

12V_EXT_DETb = X
EN1 -> "0" (by Ri2)
ENb1 -> 3.3V
ENBUS = "0"

ENb1 = 0V
ENBUS = "1"

12V_EXT_DETb = "0"
EN1<3V(duetolow12V)
ENb1 = 3.3V
ENBUS = "0"

EN1->3V
ENb1 = 0V
ENBUS = "1"

UGATE1

UGATE10

PHASE1

PHASE10

LGATE1

LGATE10

R6080RR608

R6090RR609

0R

0R

C632

C632

C634

C634

4.7uF_16V

4.7uF_16V

4.7uF_16V

4.7uF_16V

805805

123

Actual Vendor TBD Actual Vendor TBD

8

Q604

Q604

1

BSC042N03S

BSC042N03S

LGATE1

8

Thermal

Thermal

9

Pad

Pad

C635

C635

4.7uF_16V

4.7uF_16V

Mirrored on PCB

678

4 5

567

9

432

Internal
(DNP D601, D611)

IOUT/IMAXPin 10 (IOUT/IMAX/DROOP) IOUT IOUT/IMAX

TBD R_RT ~= 18,600,000/FswPin 11 (RT) R_RT ~= 10,000,000/Fsw TBD

DROOP (R663)

GND
(SS fixed internally)

IREFOUT/POK
POK voltage = 1.2V

VCCDRV

+12V_BUS

L621

L621

L620

L620

IND_0.47uH_7A

IND_0.47uH_7A

0.47uH

0.47uH

Overlap

C633

C633

C621

C621

4.7uF_16V

4.7uF_16V

10UF_16V

10UF_16V

805805

Mirrored on PCB

Mirrored on PCB

567

8

9

R607R607

432

1

7

External
(Populate D601, D611)

COMP

ICOMP
(SS dependent on Fsw)

INREFOUT/POK
PGood voltage = 1.25V

DROOP (R664)

VDDC disabled

VDDC enabled12V_EXT_DETb = "1"
External Power Missing

VDDC disabled

VDDC enabled
Normal Operation

SM 6.3mm Dia

B600

B600
60R

60R

C622

C622
10UF_16V

10UF_16V

12061206

1 2

ML601

ML601

1 2

1 2

R604

R604
221R

221R

1/10W
0603

X7R

FB_S

CSP1

7

6

Internal
(DNP D601, D611)

SSSS/ENPin 14 (SS/ICOMP)

INREFOUT/PGOOD
Vrefout = 0.6V

DROOP (R664)

12V Bus power for 12V
Gate Drive

+12V_BUS +12V_BUS

402

+3.3V_BUS

R6801KR680
1K

402
1%

R697 1KR697 1K

R681

R681

2.0K

2.0K

402
1%
DNI

When 12V is > 10V

VDDC_SHDN VDDC_EN

VDDC_SHDN13

C690

C690

100uF_16V

100uF_16V

+VDDC_Source

C680

C680

C623

C623

270uF_16V

270uF_16V

180uF_16V

180uF_16V

TH 10mm Dia

SM 10mm Dia SM 10mm Dia

L601

L601

NL601

NL601

KL601

KL601

R602R602

Overlap

PCMB105T-R47MS

PCMB105T-R47MS

+VDDC

220nH_31A

220nH_31A

HC1018

HC1018

Overlap Overlap

1.7UH

1.7UH

C604

C604
1UF_16V

1UF_16V

R605

R605
221R

221R

CSN1

KL611

KL611

1.7UH

1.7UH

X7R

R615

R615
221R

221R

CSN2

L611

L611

ML611

ML611

NL611

NL611

R612R612

Pass Transistor Circuit for 8V Gate Drive

This circuit is only for 8V
gate drive application

R670

R670
10R

10R

+12V_BUS

R682

R682

5.1K

5.1K

R683 5.1KR683 5.1K

MMBT3904

MMBT3904

1

Q678

Q678

2 3

1uF_6.3V

1uF_6.3V

EN1>3V

R6980RR698
0R

C681

C681

C626

C626

270uF_16V

270uF_16V R6300RR630

180uF_16V

180uF_16V

TH 10mm Dia

Overlap

12

PCMB105T-R47MS

PCMB105T-R47MS

220nH_31A

220nH_31A

12

HC1018

HC1018

12

R614

R614
221R

221R

1/10W
0603

C614

C614
1UF_16V

1UF_16V

CSP2

6

Choosing Different Gate Drive

5V Gate Drive R630, R670, C660,

8V Gate Drive R631, R632,

12V Gate Drive R630, C660,

Assume VCC consumes 200mA total including
5VCC providing buffered output sourcing a
minimum 20mA requirement

P(Q_8VCC)max = (12V-8V)*0.2A = 800mW

32

R661

R661

Q661

Q661

10K

10K

1

SI2304DS

SI2304DS

VCC

EN1

R6860R R6860R
R6850R R6850R
R6840R R6840R

overlap pad

1

Q679

Q679

C636

C636

MMBT3904

MMBT3904

2 3

+12V_BUS

R666

R666

12.1K

1206

Mirrored on PCB

678

123

BSC119N03SG

BSC119N03SG

8

1

4 5

567

9

432

12.1K

R667

R667
10K

10K

C625

C625
10UF_16V

10UF_16V

9

Q611

Q611

Thermal

Thermal

Pad

Pad

UGATE2

Q613

Q613

BSC042N03S

BSC042N03S

EN1

R617R617

FB_S

Populate Do Not PopulateGate Drive

R631, R632

R630, C660,
R661, Q661

R670

VDDC_EN

SS_ICOMP

VDDC_REFIN_EN

C627

C627

C624

C624

4.7uF_16V

4.7uF_16V

10UF_16V

10UF_16V

Mirrored on PCB

R661, Q661

R670

R631, R632,
R661, Q661

VCCDRV

VDDC_EN 10

C628

C628

4.7uF_16V

4.7uF_16V

805805

8

1

5

D611

D611

3

OPTIONAL

BAT54A

BAT54A

LGATE2

R664

R664

Rdroop

100K

100K

Droop Option

C670

C670
10UF

10UF

C694

C694

1206

1UF_16V

1UF_16V

X5R

X7R

16V

C629

C629

4.7uF_16V

4.7uF_16V

805

Mirrored on PCB

PHASE2

567

9

Q614

Q614

BSC042N03S

BSC042N03S

432

LGATE2LGATE2

5

LGATE1

603

D601

D601

3

OPTIONAL

BAT54A

BAT54A

Populate - For 5V Gate Drive application
Remove - For 8V or 12V Gate Drive application

C631

C631

4.7uF_16V

4.7uF_16V

8051206

+VDDC +VDDC

Overlap

Overlap

2

1

C612

C612
1uF

1uF

PHASE2

R6130RR613
0R

VCC

R6030RR603
0R

PHASE1

C602

C602
1uF

1uF

1

2

***

C641

C641
1500uF_2.5V

1500uF_2.5V

***

***

C642

C642
1500uF_2.5V

1500uF_2.5V

***

UGATE1

TP601

TP601
35mil

35mil

UGATE2

19

20

21

22

23

24

25
26
27
28
29

4

POK > 1 used to control
other on-board enables

PWRGD1

R634 10KR634 10K

R6110RR611
0R

U601

U601

uPI6201Q

uPI6201Q

PHASE2

LGATE2

VCCDRV/DROOP

VCC

LGATE1

PHASE1

PGND
PGND26
PGND27
PGND28
PGND29

R601 0RR601 0R

R632R632

***

MC641

MC641
1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT8 mm Dia, SMT

+VDDC+VDDC

***

MC642

MC642
1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT8 mm Dia, SMT

4

17

18

UGATE2

UGATE11BOOT125VCC3AGND4BUSEN5CSP1

+VDDC

+VDDC

BOOT2

5VCC

***

NC641

NC641
820uF_2.5V

820uF_2.5V

***

8 x 8 mm, TH

***

NC642

NC642
820uF_2.5V

820uF_2.5V

***

8 x 8 mm, TH

16

REFOUT/POK

3

External Reference is used when
REFIN is driven by voltage ranged
from 0.4V to 3.3V

VDDC_REFIN_EN

C659

C659
100nF

100nF

402
10V

Overlap the footprints
for MR655 and C655

Current

PGND Option

Compensation

Css if
current

MR6550RMR655

0R

15

REFIN/EN

C660

C660
1uF_6.3V

1uF_6.3V

402

6.3V

Y5V

5VCC applied externally or generated internally from the IC, must

be in regulation before IC start soft-start sequence.

For 5V Gate Drive application

External filtered +5V_EXT
is applied to this pin

+VDDC

C645

C645

Y5V

10uf

10uf

6.3V

1206 6.3V

comp.
not
used

SS_ICOMP

13

14

SS/ICOMP

COMP/DROOP

IOUT/IMAX/DROOP

6

C671

C671
100nF

100nF

402 10V
X5R

+5V

R6310RR631
0R

C646

C646

Y5V

10uf

10uf

1206 6.3V

3

C655

C655

6.8nF

6.8nF

402
25V

FB

RT

CSP2

CSN2

CSN1

VDDC_EN

C647

C647

Y5V

10uf

10uf

1206 6.3V

R6361KR636
1K

R654

R654
150R

150R

402

402

6.3V

C654

C654
470nF

470nF

FB

C607

C607
220pF_50V

220pF_50V

12

R_RT

R655

R655

402

51.1K

51.1K

11

10

C638

C638
100nF

100nF

402 10V
X5R

9

C613

C613

X7R402
50V

1nF

1nF

8

R616R616

7

C603

C603

R606R606

X7R402
50V

1nF

1nF

For 8V or 12V Gate Drive application

+5VCC is generated internally
and this is an output with
20mA minimum current
capability

+5V_OUT

0R

+VDDC

C648

C648

Y5V

10uf

10uf

1206

5VCC

Internal Reference is
used when REFIN is
pull-up to > 4.5V

Share Pad with R639

+VDDC

R1
RFB1

R651

R651
10K

10K

402

RFB2

R650

R650
20K

20K

402

Iout

R662

R662
100K

100K

CSP2

CSN2

CSN1

CSP1

TP604

TP604
35mil

35mil

R696

R696
300R

300R

805

12

Rdroop

NS600

NS600
NS_VIA

NS_VIA

VDDC1_FB

FB_S

R6580RR658
0R

R3

R653

R653

2.67K

2.67K

402

C3

C653

C653

2.2nF

2.2nF

402

X7R
50V

COMP_FB

R663

R663
100K

100K

Rdroop

Droop Option

Iout 13

2

VDDC1_FB 13

Type III compensation

COMP_GND

R6570RR657
0R

R6560RR656
0R

R2

R652

R652

3.65K

3.65K

402

C2 C1

C651

C651

C652

C652

220pF_50V

220pF_50V

10nF

10nF

X7R

402

402

10V

SMPS03 Specifications

Vin (power stage)

Vout 1.2V

Vout ripple (DC) TBD

Iout

Step load TBD

Protections

2

Nominal Value Adjustable range / Notes

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- VDDC SMPS

RV630 DDR2- VDDC SMPS

RV630 DDR2- VDDC SMPS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tolerance

;

12V +/-8% PCIe ATX12V ver. 2.2 +/-5%

;

+2.5%/-2.5%

;

TBD 55A (target 60A) max

TBDVout ripple (AC)

TBDSwitching Freq. 50kHz ~ 1MHz

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

0.8V ~ 1.5V

11 21Friday, April 13, 2007

11 21Friday, April 13, 2007

11 21Friday, April 13, 2007

1

4

4

4

www.vinafix.vn

8

7

6

5

4

3

2

+12V_BUS

1

Thermal

Thermal

Pad

Pad

+MVDDC_S

9

6
7
8

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

Place Rs and Cs across QL

RC snubber values shown
are for reference only,
tuning is required

MVDDC_FB

C715

C715

C716

C716

10UF

10UF

10UF

10UF

12061206

on PCB

NL701 PCMC063T-2R2MNNL701 PCMC063T-2R2MN

1 2

ML701 HAH1030-R47-RML701 HAH1030-R47-R

1 2

L701 2.2uH_13AL701 2.2uH_13A

1 2

R719

R719
33MOHM

33MOHM

Rs

1210
1%

C708

C708
10nF_25V

10nF_25V

402

Cs

X7R
25V

C717

C717

4.7uF_10V

4.7uF_10V

805

Use16V 0805 MLCCMirrored

Mirrored on PCB

Overlap

C713

C713

3.9nF

3.9nF

402
10%

R1

RFB1
R711

R711

R713

R713

4.99K

4.99K

3.65K

3.65K

402

402

5%

1%

R4

Place R1 and
R4 close to

RFB2

PWM and

R710

R710

routed with

3.24K

3.24K

separate

402

20mil trace to

1%

the ASIC

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

C719

C719

4.7uF_10V

4.7uF_10V

805

16V
X7R

R7230RR723
0R

C718

C718
150nF_16V

150nF_16V

603

Q701

Q701

QH

+PW_MVDDC_HGD

D D

C703

C703

0.22uF

0.22uF

MVDD_EN 14

R708 20KR708 20K

+PW_MVDDC_M

402

+PW_MVDDC_LGD

R7220RR722

603

0R

+PW_MVDDC_LGDR

+MVDDC_B

U703

U703

1

BOOT

2

UGATE

3

+PW_MVDDC_LGD

R715

R715

42.2K

C C

List of supported foodprint

The following ICs are not necessarily evaluated by
ATI, please refer to BOM for evaluation status

42.2K

ANPEC APW7120/APW7065 (12V)

CAT CAT7583 (12V)

INTERSIL ISL6545

NEXSEM NX2114/2307

RICHTEK RT9214/RT8101

OnSemi ON1582

uPI UP6101 (No Ext_Vref in)

uPI UP6103 (with Ext_Vref in, can use voltage console UP6261 to change Vout)

GND

LGATE4VCC

APW7065

APW7065

PHASE

COMP

+PW_MVDDC_M

8

MVDDC_COMP+PW_MVDDC_HGD

7

MVDDC_FB

6

FB

5

+MVDD_VCC

R721 0RR721 0R

+PW_MVDDC_HGDR

402

QL

4 5
3
2
1

Q702

Q702

Thermal

Thermal

Pad

Pad

BSC119N03SG

BSC119N03SG

MVDDC_FB13

4 5
3
2
1

BSC119N03SG

BSC119N03SG

9

6
7
8

***

C725

C725
470uF_10V

470uF_10V

***

Over Lap

L702

L702

IND_0.47uH_7A

IND_0.47uH_7A

Overlap

TH 10mm Dia SM 10mm Dia

Overlap

***

MC725

MC725
470uF_6.3V

470uF_6.3V

***

ALT POLY

ML702

ML702

0.47uH

0.47uH

Find 100nH
SM Alt. IND

C731

C731
270uF_16V

270uF_16V

Overlap

B701

B701
60R

60R

KC725

KC725
330uF_2.5V

330uF_2.5V

TAN LP
25mOHM

B703

B703
60R

60R

C732

C732
180uF_16V

180uF_16V

+VDDC_Source

R7240RR724
0R

*** ***

C723

C723
100uF_6.3V

100uF_6.3V

1210 1210

*** ***

Over Lap

100uF_16V

100uF_16V

+MVDDC_S

MC723

MC723
330uF_2.5V

330uF_2.5V

TAN LP
25mOHM

C730

C730

+MVDD

C724

C724
100uF_6.3V

100uF_6.3V

SMPS02- Regulator for MVDD

Vout = 1.8V ~ 2.85V

+PW_MVDDC_LGDR

MQ702

MQ702

Thermal

Thermal

Pad

Pad

FDS7096N3

FDS7096N3

9

6
7
8

4 5
3
2
1

4

MULTI FOOTPRINT
For SO-8

3

Part RFB2RFB1

0.8V Ref

SMPS02 Specifications

Vin 12V(power stage) +/-8% PCIe ATX12V ver. 2.2 +/-5%

Vout 2V

Vout ripple (DC) 50mVpp

Iout 6Aavg, 8Adc_max

Step load 3Amax

Protections

Vout

2.03V
(1.98V~2.08V)

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet

Date: Sheet

2

4.99K
p/n 3160499100G

Nominal Value Adjustable range / Notes

+/-10% or 200mVpp @ 3A step loadVout ripple (AC)

TR RV630 - MVDD SMPS02

TR RV630 - MVDD SMPS02

TR RV630 - MVDD SMPS02

Custom

Custom

Custom

;

Tolerance

;

;

+2%/-2%

~300kHzSwitching Freq. TBD

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

105-B149xx-00

105-B149xx-00

105-B149xx-00

3.24K
p/n 3160324100G

1.8V ~ 2.85V

12 21Friday, April 13, 2007

12 21Friday, April 13, 2007

12 21Friday, April 13, 2007

1

of

of

4

4

4

+5V

R7060RR706
0R

402

+PW_MVDDC_M

+PW_MVDDC_HGDR

MQ701

MQ701

Thermal

Thermal

Pad

Pad

4 5
3
2
1

FDS7096N3

FDS7096N3

+PW_MVDDC_M

5

+MVDDC_S

9

6
7
8

Layout guideline for Nexsem NX2114/2307

1-Position the controller (U703) such that LGate(pin4) is the closet to gate
of the MOSFETs. You can place the gate resistors R721 and R722 next to the gate
of the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as
short and as wide as possible to reduce the trace inductance.
2-Place the bypass capacitors for Vcc as well as Boost caps as close to the
controller as possible. They are as follows;
Vcc bypass cap is C703, and Boost cap is C705.
3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place
the rest of the compensation network close to the pins 7 and 6. These are R710,
R711, R713, C713 and R712, C711 and C712.

B B

COMPENSATION CIRCUIT

402

MVDDC_COMP

C714

C714

C712

C712

C711

A A

C711
15nF

15nF

402
X7R

R712

R712

2.94K

2.94K

402
1%

10%

8

NPO

R714 0RR714 0R

R7090RR709
0R

X5R

10%

5%

MVDDC_FB

100nF

100nF

390pF

390pF

402

10V

50V

603

10V

FILTERED SMPS VCC BOOT CIRCUIT

+12V_BUS

+MVDD_VCC

7

R707

R707

2.2R

2.2R

C707

C707
100nF

100nF

+5V

MR707

MR707

2.2R

2.2R

603
X7R
5%

6

D701

D701

1

BAT54A

BAT54A

3

C705

C705
100nF

100nF

603 X7R
5%

2

16V

+12V_BUS

+MVDDC_B

MR7060RMR706
0R

402

C706

C706
150nF_16V

150nF_16V

www.vinafix.vn

5

U1200

DDC3DATA3,18

DDC3CLK3,18

D D

DDC3DATA

DDC3CLK

R1202

R1202

1.8R

1.8R

C1201

C1201
10uF

10uF

DCC to control VDDC1 and MVDD Voltage.

+3.3V_BUS

R1210 0RR1210 0R

DDC3DATA

R1211 0RR1211 0R

DDC3CLK

R1212 0RR1212 0R

I2C Debugging
Header for testing purpose

C C

132­For Testing purposes only

JU1210

JU1210
1
2

DNI

3
4

1X4 3A 2MM

1X4 3A 2MM

U1200

R1200

R1200

1

SDA

2

SCL

A111NC#12

9

A0

13

VCC

15

EPAD

3

GND

DS4402

DS4402

OUT0

OUT1

NC#14

NC#4

NC#5

FS1

FS0

200R

200R
R1201

R1201
200R

200R
R12070RR1207
0R
R12080RR1208
0R

C1200

C1200
100nF

100nF

Buffered VDDC Output Current Monitoring

+12V_BUS

R6400RR640

C657

C657
1nF

1nF

X7R
50V

1

+

+

0R

3

-

-

2 5

R6911KR691
1K

1%

Iout11

402

4

CUR_ADJ_0

CUR_ADJ_1

C691

C691
100nF

100nF

603

U611

U611

X7R

4

LMV321

LMV321

C693

C693
10nF

10nF

1%

R1203

R1203
10K

10K
R1204

R1204
10K

10K

R1205 0RR1205 0R
R1209 0RR1209 0R

share pad

R1206 0RR1206 0R

TP603

TP603
TP_32mil_SM_top

TP_32mil_SM_top

J601

J601

2 1

header_1x2_2mm_smt

header_1x2_2mm_smt

R692

R692

9.09K

9.09K

8

10

12

14

4

5

6

7

Place caps very
close to power pin

C692

C692
100nF

100nF

603
X7R

12V Supply Voltage single Op-Amp (U611) :

1. National LM321, SOT23-5, ATI PN - TBD

2. TI alternate? ATI PN - TBD

VDDC1_FB 11
VDDC2_FB 10

MVDDC_FB 12

3

+3.3V+3.3V_BUS

R1240

R1240
10K

PWRCNTL_07

10K

R1243

R1243
100K

100K
DNI

DNI

2

RS1

1

R1246 0RR1246 0R

R1247 0RR1247 0R

Q1242

Q1242
BSH111

BSH111

R1245

R1245
10K

10K
DNI

DNI

Share Pad

32

1

R1244

R1244

30.9K

30.9K

VDDC1_FB 11

VDDC2_FB 10

SMPS03- Regulator for VDDC

Vout = .9V ~ 1.2V

0.6V Ref

VDDC

.9V

1.0V

1.1V

1.2V HIGH

RS1

N/A

59.0K 1%

ATI # 3160590200G

30.9K 1%

ATI # 3160309200G

20.0K 1%

ATI # 3160200200G

PWRCNTL_0

LOW

HIGH

HIGH

B B

C1250

C1250
100nF

100nF

+3.3V_BUS

+3.3V

R1251

R1251

A A

CTFb

CTFb7

10K

10K

R1253 0RR1253 0R

1

Q1250

Q1250
BSH111

BSH111

5

+3.3V_BUS

U1250A

U1250A
74LCX74

74LCX74

2

D

3

CP

R1250 10KR1250 10K

U1250B

U1250B
74LCX74

74LCX74

12

D

11

CP

+3.3V_BUS

R1252

R1252
10K

10K

32

POWER_SHDN14

1

4

14

5

S

Q

5V

6

Q

GND7C

1

C1251

C1251

100nF

100nF

10

9

S

Q

R1259 10KR1259 10K

8

Q

C

13

R1257

R1257
100K

100K

VDDC_SHDN 11

Q1251

Q1251
MMBT3904

MMBT3904

2 3

Not intended for production

LED off shows the fault

TR1257

TR1257

1

5.1K

5.1K

+3.3V_BUS

2 3
21

TR1256

TR1256
499R

499R

TQ1250

TQ1250
MMBT3904

MMBT3904

TD1250TD1250

4

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- POWER MANAGMENT

RV630 DDR2- POWER MANAGMENT

RV630 DDR2- POWER MANAGMENT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

3

2

Date: Sheet

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

4

4

13 21Friday, April 13, 2007

13 21Friday, April 13, 2007

13 21Friday, April 13, 2007

4

of

of

of

www.vinafix.vn

8

+VDDC

+12V_BUS

R843

R843

5.1K

5.1K

R842

R842

2.0K

2.0K

DNI

LDO1_POK

5%

Q840

Q840

1

MMBT3904

MMBT3904

2 3

POWER_SHDN13

+3.3V

R899

R899

5.1K

5.1K

R8411KR841
1K

D D

C841

C841
1uF_6.3V

1uF_6.3V

R844 5.1KR844 5.1K

R846 5.1KR846 5.1K

R891 5.1KR891 5.1K

5%

1

1

OSC_EN 3

+5V

2 3

Q842

Q842
MMBT3904

MMBT3904

2 3

7

5.1K

5.1K
R845

R845

Q841

Q841
MMBT3904

MMBT3904

LDO3_EN

LDO1_EN

MVDD_EN 12

6

Power up/down Sequencing

+1.8V

R847 10KR847 10K

5

1

C844

C844
100nF_6.3V

100nF_6.3V

Q843

Q843
MMBT3904

MMBT3904

2 3

R848

R848
100K

100K

1

+12V_BUS

2 3

R849

R849
10K

10K

Q844

Q844

MMBT3904

MMBT3904

C843

C843
100NF

100NF

402
X5R
16V

4

+3.3V_BUS

Install only one of these

R8900RR890
0R

Q845

Q845

3 2

SI2304DS

C842

C842
10uF_X6S

10uF_X6S

R8960RR896
0R

R8970RR897
0R

SI2304DS

1

3

+3.3V

LVT_EN 3,4

R840

R840
100K

100K

2

1

Regulators for +5V, +5V_VESA and +5V_VESA2

+12V_BUS

MR811

R812

R812

MR812

MR812
27R

27R
47R

47R

0805

1206

1/4W

1/8W

5%

5%

C810

C810
100nF

100nF

0603
16V

Vout(V) = Vref (1+R2/R1)

1206

1/4W

R811

R811
47R

47R

MR811
27R

27R

0805

1/8W

MU810

MU810
MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

U810

U810

1

VIN

5

NC

8

NC#8
ADJ4VOUT

LM317LCDR

LM317LCDR

GND

1

VOUT#2
VOUT#3
VOUT#6

3

2
3

R813

R813

6

499R

499R

7

0402

R1

1uF_6.3V

1uF_6.3V

R814

R814

0402

1.5K

1.5K

R2

+5V_VESA

C811

C811

LDO #1:

PCB: 50 to 70mm sq. copper area for cooling

C C

+3.3V_BUS

1206
Use 0.5R

R8781RR878
1R

LDO1_VIN

LDO1_EN

10uF_X6S

10uF_X6S

C876

C876

TP871

TP871
35mil

35mil

TP870

TP870
35mil

35mil

+5V

LDO1_POK

C878

C878
1uF_6.3V

1uF_6.3V

U871

U871

1

POK

2

EN

3

VIN
CNTL4REFIN

uP7706U8

uP7706U8

GND#8

VOUT

GND#9

8
7

FB

6

R876 0RR876 0R

5

DNI

9

Iout = 0.8A (TBV) RMS MAXVout = +1.8V +/- 2%Vin = 2.1V to 3.6V MAX

+1.8V_LDO1

C875

R5

R4

C875
33pF_50V

33pF_50V

C3

R875

R875

12.7K_0.1%

12.7K_0.1%

LDO1_FB

R874

R874
10K_0.1%

10K_0.1%

0402

0.1%

VOUT = Vref x (1 + R5/R4)

+1.8V_LDO1

C873

C873
22uF_16V

22uF_16V

C871

C871

C872

C872
10uF_X6S

10uF_X6S

DNIDNI

10uF_X6S

10uF_X6S

C874

C874
100nF_6.3V

100nF_6.3V

+MVDD

B879 220R_2AB879 220R_2A

Overlap foorprints

MR879 0RMR879 0R

+1.8V_LDO1 +1.8V

R879 0RR879 0R

+12V_BUS

MR822

MR822

R822

1206

1/4W

5%

C820

C820
100nF

100nF

0603
16V

R822
47R

47R

27R

27R

0805

1/8W

5%

R821

R821
47R

47R

1206 0805

Vout(V) = Vref (1+R2/R1)

MR821

MR821
27R

27R

MU820

MU820
MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

U820

U820

1

VIN

5

NC

8

NC#8
ADJ4VOUT

LM317LCDR

LM317LCDR

GND

1

VOUT#2
VOUT#3
VOUT#6

+5V_VESA2

3

2
3

R823

R823

6

499R

499R

7

0402

R1

C821

C821

1uF_6.3V

1uF_6.3V

R824

R824

0402

1.5K

1.5K

R2

DELETE LDO2

+12V_BUS

B B

LDO #3: Vout = +1.1V +/- 2%

Vin = +1.45V to 2.1VMAX Iout = 1.1A (TBV) RMS MAX

PCB: 50 to 70mm sq. copper area for cooling

TP851

TP851

TP850

TP850

35mil

35mil

35mil

+MVDD

A A

1206
Use 0R

R8581RR858
1R

LDO3_VIN

LDO3_EN

C856

C856

10uF_X6S

10uF_X6S

35mil

LDO3_POK

C858

C858
1uF_6.3V

1uF_6.3V

U851

U851

1

POK

2

EN

3

VIN
CNTL4REFIN

uP7706U8

uP7706U8

GND#8

VOUT

GND#9

8
7

FB

6

R856 0RR856 0R

5
9

+1.1V+5V +1.1V

LDO3_FB

DNI

VOUT = Vref x (1 + R5/R4)

R855

R855

3.92K_0.1%

3.92K_0.1%

R5

R854

R854
10K_0.1%

10K_0.1%

0.1%

R4

C855

C855
33pF_50V

33pF_50V

C3

C853

C853
22uF_16V

22uF_16V

DNIDNI

C852

C852
10uF_X6S

10uF_X6S

C851

C851
10uF_X6S

10uF_X6S

C854

C854
100nF_6.3V

100nF_6.3V

MR832

MR832

R832

R832

27R

27R
47R

47R

1206

0805

1/4W

1/8W

5%

5%

C830

C830
100nF

100nF

0603
16V

Vout(V) = Vref (1+R2/R1)

Shared Power Rails

+1.8V +AVDD

R8800RR880
0R

8

B882

B882
BLM15BD121SN1

BLM15BD121SN1

+A2VDDQ

+VDD1DI +VDD2DI +DPLL_PVDD +TPVDD +TXVDDR +T2PVDD

B886

B883

B883
BLM15BD121SN1

BLM15BD121SN1

B884

B884
BLM15BD121SN1

BLM15BD121SN1

7

B885

B885
BLM15BD121SN1

BLM15BD121SN1

B886
BLM15BD121SN1

BLM15BD121SN1

B887

B887
BLM15BD121SN1

BLM15BD121SN1

6

B888

B888
BLM15BD121SN1

BLM15BD121SN1

B889

B889
BLM15BD121SN1

BLM15BD121SN1

5

4

3

MR831

MR831

R831

R831

27R

27R

47R

47R

1206

0805

1/4W

1/8W

5%

5%

MU830

MU830
MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

U830

U830

1

VIN

5

NC

8

NC#8
ADJ4VOUT

LM317LCDR

LM317LCDR

+5V_VESA2+5V_VESA

DNI

R815 0RR815 0R

R835 0RR835 0R

Title

Title

Title

TR RV630 - Linear Regulators

TR RV630 - Linear Regulators

TR RV630 - Linear Regulators

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

2

+5V

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

3

GND

1

2

VOUT#2

3

VOUT#3

6

VOUT#6

7

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

R833

R833
499R

499R

0402

R1

R834

R834

1.5K

1.5K

0402

R2

1uF_6.3V

1uF_6.3V

14 21Friday, April 13, 2007

14 21Friday, April 13, 2007

14 21Friday, April 13, 2007

C831

C831

of

of

of

+5V

4

4

4

www.vinafix.vn

8

7

6

5

4

3

2

1

L1001

A_DAC1_R3

C1999 100nFC1999 100nF

R1027 37.4RR1027 37.4R

R1028 37.4RR1028 37.4R

R1029 37.4RR1029 37.4R

+3.3V

+3.3V +5V

+5V

14

2 3

1

7

A_DAC1_RB3

A_DAC1_G3

D D

C C

A_DAC1_GB3

A_DAC1_B3

A_DAC1_BB3

CRT1DDCDATA3

CRT1DDCCLK3

HSYNC_DAC13,7

4

VSYNC_DAC13,7

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

B B

5 6

R1001

R1001
75R

75R

R1002

R1002
75R

75R

R1003

R1003
75R

75R

Pseudo differential RGB should be routed from the ASIC to the display
connector without switching reference plane or running over split plane.

1

R1004

R1004
10K

10K

R1007

R1007
10K

10K

U1999A

U1999A

74VHC125

74VHC125

U1999B

U1999B

74VHC125

74VHC125

1

HSYNC_DAC1_B

VSYNC_DAC1_B

32

BSH111

BSH111
Q1001

Q1001

32

BSH111

BSH111
Q1002

Q1002

L1001

68nH_300mA

68nH_300mA

C1004

C1004

8.0pF

8.0pF
R1024 0RR1024 0R

L1002

L1002

68nH_300mA

68nH_300mA

C1005

C1005

8.0pF

8.0pF
R1025 0RR1025 0R

L1003

L1003

68nH_300mA

68nH_300mA

C1006

C1006

8.0pF

8.0pF
R1026 0RR1026 0R

+5V

R1005

R1005

2.2K

2.2K
DDCDATA_DAC1_5V DDCDATA_DAC1_R

R1008

R1008

2.2K

2.2K
DDCCLK_DAC1_5V

A_R_DAC1_M

C1001

C1001
12pF_50V

12pF_50V

A_G_DAC1_M

C1002

C1002
12pF_50V

12pF_50V

A_B_DAC1_M

C1003

C1003
12pF_50V

12pF_50V

R1006 33RR1006 33R

R1009 33RR1009 33R

R1010

R1010

R1011

R1011

10R

10R

10R

10R

L1004

L1004
36NH

36NH

L1005

L1005
36NH

36NH

L1006

L1006
36NH

36NH

DDCCLK_DAC1_R

HSYNC_DAC1_R

VSYNC_DAC1_R

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F

DDCDATA_DAC1_R

DDCCLK_DAC1_R

HSYNC_DAC1_R
VSYNC_DAC1_R

HPD27

For ESD ProtectionSee BOM for qualified filters

Q1021

Q1021

MMBT3904

MMBT3904

+3.3V

2 3

R1023

R1023
10K

10K

R1022 10KR1022 10K

1

+3.3V

D1001

D1001

4

5

6

CM1213-04

CM1213-04

CH3

Vp

CH4

2

Vn

1

CH1

3

CH2

T2X2M3
T2X2P3

T2X4M3
T2X4P3

T2X1M3
T2X1P3

T2X3M3
T2X3P3

T2X0M3
T2X0P3

T2X5M3
T2X5P3

T2XCP3
T2XCM3

+5V_VESA

4

5

6

DDCCLK_DAC1_R
DDCDATA_DAC1_R
VSYNC_DAC1_R

HPD_DVI2

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F
HSYNC_DAC1_R

D1002

D1002

CH3

Vp

CH4

CM1213-04

CM1213-04

3

CH2

2

Vn

1

CH1

+5V_VESA

C1010

C1010
68pF

68pF

603

Standard VGA

DB15 pin

11
12
4
15

9

Hardware
Support

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA

DDC1 Host

Monitor ID bit 0

Monitor ID bit 0

Monitor ID bit 1

Data from display

Monitor ID bit 2

Monitor ID bit 2

Monitor ID bit 3

Open
+5V

N/C

50mA min

Mechanical Key

1A max

No Yes Yes No Yes

J1001

J1001

25

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C1
C2
C3
C4
C5
C6

26
27
28
29
30

DVI_CONNECTOR

DVI_CONNECTOR

1
2

3
11
12

4
15

9
13
14

5

6

7

8
10
16
17

DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max

CASE

TMDS Data2­TMDS Data2+
TMDS Data2/4 Shield
TMDS Data4­TMDS Data4+
DDC Clock
DDC Data
Analog VSYNC
TMDS Data1­TMDS Data1+
TMDS Data1/3 Shield
TMDS Data3­TMDS Data3+
+5V Power
GND (for +5V)
Hot Plug Detect
TMDS Data0­TMDS Data0+
TMDS Data0/5 Shield
TMDS Data5­TMDS Data5+
TMDS Clock Shield
TMDS Clock+
TMDS Clock-

Analog Red
Analog Green
Analog Blue
Analog HYNC
Analog GND
Analog GND#C6

CASE#26
CASE#27
CASE#28
CASE#29
CASE#30

MJ1001

MJ1001

R
G
B
MS0
MS1
MS2
MS3
NC
HS
VS
VSS
VSS#6
VSS#7
VSS#8
VSS#10
CASE
CASE#17

G3179C219-005

G3179C219-005

DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)

DDC2AB Host

Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max

DDC1/2 Display

Optional
SDA
Optional
SCL

Optional

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2- DAC1&TMDS2

RV630 DDR2- DAC1&TMDS2

RV630 DDR2- DAC1&TMDS2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B149xx-00

105-B149xx-00

105-B149xx-00

4

4

4

of

of

of

15 21Friday, April 13, 2007

15 21Friday, April 13, 2007

15 21Friday, April 13, 2007

1

www.vinafix.vn

8

7

6

5

4

3

2

1

See BOM for qualified filters

L2001

A_DAC2_R3

A_DAC2_RB3

A_DAC2_G3

D D

A_DAC2_GB3

A_DAC2_B3

A_DAC2_BB3

R2027

R2027

37.4R

37.4R

R2028

R2028

37.4R

37.4R

R2029

R2029

37.4R

37.4R

R2001

R2001
75R

75R

402

R2002

R2002
75R

75R

402

R2003

R2003
75R

75R

L2001

C2004

C2004

68nH_300mA

68nH_300mA

8.0pF

8.0pF

402

L2002

L2002

C2005

C2005

68nH_300mA

68nH_300mA

8.0pF

8.0pF

402

L2003

L2003

C2006

C2006

68nH_300mA

68nH_300mA

8.0pF

8.0pF

402

Pseudo differential RGB should be routed from the ASIC to the display
connector without switching reference plane or running over split plane.

R20240RR2024
0R

R20250RR2025
0R

R20260RR2026
0R

A_R_DAC2_M

C2001

C2001

402

12pF_50V

12pF_50V

A_G_DAC2_M

C2002

C2002

402

12pF_50V

12pF_50V

A_B_DAC2_M

C2003

C2003

402402

12pF_50V

12pF_50V

L2004

L2004
36NH

36NH

L2005

L2005
36NH

36NH

L2006

L2006
36NH

36NH

A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F

DDCDATA_DAC2_R

DDCCLK_DAC2_R

+3.3V

4

5

6

HSYNC_DAC2_R
VSYNC_DAC2_R

D2001

D2001

CH3

Vp

CH4

CM1213-04

CM1213-04

3

CH2

2

Vn

1

CH1

+5V_VESA2

4

5

6

For ESD Protection

D2002

D2002

CH3

Vp

CH4

CM1213-04

CM1213-04

3

CH2

2

Vn

1

CH1

C2010

C2010
68pF

68pF

603

+5V_VESA2

MJ2001

MJ2001

1

R

2

G

3

B

11

MS0

12

MS1

4

MS2

15

MS3

9

NC

13

HS

14

VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8

10

VSS#10

16

CASE

17

CASE#17

G3179C219-005

G3179C219-005

DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)

+3.3V

R2004

R2004
10K

C C

B B

CRT2DDCDATA3

CRT2DDCCLK3

HSYNC_DAC23,7

VSYNC_DAC23,7

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

10K

+3.3V +5V

R2007

R2007
10K

10K

U1999C

U1999C

9 8

74VHC125

74VHC125

10

U1999D

U1999D

13

12 11

74VHC125

74VHC125

1

32

BSH111

BSH111
Q2001

Q2001

1

32

BSH111

BSH111
Q2002

Q2002

HSYNC_DAC2_B

VSYNC_DAC2_B

+5V

R2005

R2005

2.2K

2.2K

402

DDCDATA_DAC2_5V DDCDATA_DAC2_R

R2008

R2008

2.2K

2.2K

402 402

DDCCLK_DAC2_5V

R2006 33RR2006 33R

R2009 33RR2009 33R

R2010

R2010

R2011

R2011

402

402

10R

10R

HSYNC_DAC2_R

402

VSYNC_DAC2_R

10R

10R

HPD13

DDCCLK_DAC2_R

Q2021

Q2021

MMBT3904

MMBT3904

+3.3V

2 3

R2023

R2023
10K

10K

R2022 10KR2022 10K

1

T1XCP3
T1XCM3

T1X2M3
T1X2P3

T1X4M3
T1X4P3

T1X1M3
T1X1P3

T1X3M3
T1X3P3

T1X0M3
T1X0P3

T1X5M3
T1X5P3

DDCCLK_DAC2_R
DDCDATA_DAC2_R
VSYNC_DAC2_R

HPD_DVI1

A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F
HSYNC_DAC2_R

DB15 pin

Standard VGA

Monitor ID bit 0

11

Monitor ID bit 1

12

Monitor ID bit 2

4

Monitor ID bit 3

15

N/C

9

Mechanical Key

Hardware

No Yes Yes No Yes

Support

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA2

DDC1 Host

Monitor ID bit 0
Data from display
Monitor ID bit 2
Open
+5V
50mA min
1A max

25

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C1
C2
C3
C4
C5
C6

26
27
28
29
30

DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max

J2001

J2001

CASE

TMDS Data2­TMDS Data2+
TMDS Data2/4 Shield
TMDS Data4­TMDS Data4+
DDC Clock
DDC Data
Analog VSYNC
TMDS Data1­TMDS Data1+
TMDS Data1/3 Shield
TMDS Data3­TMDS Data3+
+5V Power
GND (for +5V)
Hot Plug Detect
TMDS Data0­TMDS Data0+
TMDS Data0/5 Shield
TMDS Data5­TMDS Data5+
TMDS Clock Shield
TMDS Clock+
TMDS Clock-

Analog Red
Analog Green
Analog Blue
Analog HYNC
Analog GND
Analog GND#C6

CASE#26
CASE#27
CASE#28
CASE#29
CASE#30

DVI_CONNECTOR

DVI_CONNECTOR

DDC2AB Host

Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max

DDC1/2 Display

Optional
SDA
Optional
SCL

Optional

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2-DAC2/TMDS1

RV630 DDR2-DAC2/TMDS1

RV630 DDR2-DAC2/TMDS1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B149xx-00

105-B149xx-00

105-B149xx-00

4

4

4

of

of

of

16 21Friday, April 13, 2007

16 21Friday, April 13, 2007

16 21Friday, April 13, 2007

1

www.vinafix.vn

8

D D

7

6

5

4

3

2

1

A_DAC2_Y3

R3001

R3001
75R

75R

A_DAC2_C3

R3002

R3002
75R

75R

A_DAC2_COMP3

R3003

R3003
75R

75R

C C

Place near connector
0R leaves footprint for Ferrite
Beads if req'd for EMI

DAC2_C_F
DAC2_COMP_F

R3011 0RR3011 0R

R3004 0RR3004 0R
R3005 0RR3005 0R
R3006 0RR3006 0R

Install for Dell

GENERICA7

DNI for Dell

402

STV/HDTV#_DET PIN6

DAC2_Y_DINDAC2_Y_F
DAC2_C_DIN
DAC2_COMP_DIN

+3.3V

R3008

R3008
10K

10K

C3007

C3007
82pF

82pF

Install for Dell

R3010 0RR3010 0R

R3009 0RR3009 0R

C3008

C3008

C3009

C3009

82pF

82pF

82pF

82pF

L3001 470nH_250mAL3001 470nH_250mA

C3001

C3001
47pF_50V

47pF_50V

L3002 470nH_250mAL3002 470nH_250mA

C3002

C3002
47pF_50V

47pF_50V

L3003 470nH_250mAL3003 470nH_250mA

C3003

C3003
47pF_50V

47pF_50V

R30070RR3007
0R

DNI for Dell

The 7-pin MiniDIN footprint allows one of the two MiniDINs:

B B

- 7-pin Svideo/Composite MiniDIN P/N 6071001500G

- 4-pin Svideo MiniDIN P/N 6070001000G

DAC2_Y_F

C3004

C3004
47pF_50V

47pF_50V

DAC2_C_F

C3005

C3005
47pF_50V

47pF_50V

DAC2_COMP_F

C3006

C3006
47pF_50V

47pF_50V

Install for Dell only when it's needed for EMI

C3010

C3010
82pF

82pF

TV Out

J3001

J3001

6

HDTV_OUT_DET#

3

Y-OUT

4

C-OUT

7

Comp_out

CompIn

5

SYNC

1

GND

2

GND#2

8

Rpin5

CASE

9

CASE#9

10

CASE#10

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

A A

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2 - TVO

RV630 DDR2 - TVO

RV630 DDR2 - TVO

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B149xx-00

105-B149xx-00

105-B149xx-00

4

4

17 21Friday, April 13, 2007

17 21Friday, April 13, 2007

17 21Friday, April 13, 2007

1

4

of

of

of

www.vinafix.vn

8

R4032

R4032

2.61K

2.61K

PWM

DDC3CLK3,13

DDC3DATA3,13

TS_FDO3

Place R4032, and R4033 on
the bottom side. Easily
accessiable.

For 4-WIRE
FAN

1

+5V

MR40061KMR4006
1K

Share one PAD

Q4001

Q4001

MMBT3904

MMBT3904

2 3

R4033 100KR4033 100K

+12V_BUS

D D

C C

7

+3.3V

R4003

R4003
10K

10K

R4001 100RR4001 100R

R4002 100RR4002 100R

R4015 0RR4015 0R

For 2-WIRE FAN ONLY

R4006

R4006

2.61K

2.61K

1%

R4008 100KR4008 100K

R40071KR4007
1K

1%

6

LM63 is for BU only, until built-in fan controller is verified.

+3.3V

C4002

C4002

C4003

1uF_6.3V

1uF_6.3V

SMBCLK

SMBDAT

ALERT

GND5PWM

VDD

C4003

100pF_50V

100pF_50V

D+

D-

R4004

R4004
10K

10K

1

2

3

4

TS_FDO

C4004

C4004

2.2nF_50V

2.2nF_50V

LM63_PWM

GPU_DPLUS

GPU_DMINUS

SCL_R

SDA_R

TINT_R

C4001

C4001
10uF_X6S

10uF_X6S

U4001

U4001

8

7

6

LM63CIMAX

LM63CIMAX

Warning: TS_FDO is not 5V tolerant. MAX sink current 1.65mA

R4010 0RR4010 0R

R40140RR4014

0R

MMBT3906

MMBT3906
Q4002

Q4002

1

C4007

C4007
1uF

1uF

805
16V
Y5V

R4011

R4011
100K

100K

32

MQ4004

R4009

R4009
100K

100K

402

23

Q4003

Q4003

1

MMBT3904

MMBT3904

2 3

R4013

R4013

1.47K

1.47K

1

R4012 10KR4012 10K

402

MQ4004

2SB1188

2SB1188

5

GPU_DPLUS 3

GPU_DMINUS 3ThermINT7

26R_600mA

26R_600mA

For 4-WIRE
FAN

B4001

B4001

C4010

C4010
10uF

10uF

+12V_BUS

For fan with 3.3V PWM (bypass) install 0R (TBV)

MR4005 10KMR4005 10K

Share one pad
Place them on the bottom

R4005 10KR4005 10K

C4008

C4008
1uF

1uF

0805
16V

4

PWM

3

2

1

+5V

R4036

R4036
10K

10K

TACH

R4039

R4039

1

Q4030

Q4030

10K

10K

MMBT3904

MMBT3904

2 3

B B

H1A

H1A

FANSINK

FANSINK

2345678

1

A A

For 4-WIRE FAN ONLY

H1B

H1B

FANSINK

FANSINK

9

10111213141516

MR40360RMR4036

0R

DNI (bypass for fan
with 3.3V PWM)

H1C

H1C

FANSINK

FANSINK

17181920212223

H1D

H1D

FANSINK

FANSINK

24

25262728293031

R4031 15KR4031 15K

DNI

C4030

C4030

47nF

47nF

DNI

DNI

32

H1E

H1E

FANSINK

FANSINK

33343536373839

Header is 2mm, and
it does not follow

2.54mm spacing as 4-pin
PWM Fan Specification

Overlap MJ4030 and J4030

H1F

H1F

FANSINK

FANSINK

41424344454647

40

4
3
2

J4030

J4030

1

1X4 3A 2MM

1X4 3A 2MM

MJ4030MJ4030

1
2

48

H1G

H1G

FANSINK

FANSINK

49505152535455

H1H

H1H

FANSINK

FANSINK

58596061626364

57

56

FANSINK FOR RV630 DDR2, p/n 7120033200G

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2-THERMAL MANAGEMENT

RV630 DDR2-THERMAL MANAGEMENT

RV630 DDR2-THERMAL MANAGEMENT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

105-B149xx-00

105-B149xx-00

105-B149xx-00

4

4

18 21Friday, April 13, 2007

18 21Friday, April 13, 2007

18 21Friday, April 13, 2007

1

4

of

of

of

www.vinafix.vn

5

DVI/DVI SCREWS with top tab

ASSY-SCREW2

BRACKET

BRACKET

ASSY-SCREW2

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

ASSY-SCREW4

ASSY-SCREW4

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
ASSY-SCREW

ASSY-SCREW

ASSY-SCREW1

ASSY-SCREW1

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

ASSY-SCREW3

ASSY-SCREW3

SCREW

SCREW

D D

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

ASSY2

ASSY1

ASSY1

ANTISTATIC

ANTISTATIC
BAG

BAG

6_X_11

6_X_11

C C

ASSY2

8020038600G

8020038600G

4

MT1

MT1
MT_Hole_0.136_in.

MT_Hole_0.136_in.

SK1

SK1

RV410SOCKET

RV410SOCKET

MT2

MT2
MT_Hole_0.136_in_6VIA

MT_Hole_0.136_in_6VIA

PCB1

PCB1

PCB

PCB

109-B14931-00C

109-B14931-00C

3

2

1

B B

A A

<Variant Name>

<Variant Name>

<Variant Name>

5

4

3

2

ATI Technologies Inc.

ATI Technologies Inc.

ATI Technologies Inc.

1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario
Canada, L3T 7X6

Canada, L3T 7X6

Canada, L3T 7X6
[phone]

[phone]

[phone]

Title

Title

Title

RV630 DDR2-MECHANICAL

RV630 DDR2-MECHANICAL

RV630 DDR2-MECHANICAL

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

105-B149xx-00

105-B149xx-00

105-B149xx-00

1

19 21Friday, April 13, 2007

19 21Friday, April 13, 2007

19 21Friday, April 13, 2007

of

of

of

4

4

4

www.vinafix.vn

www.vinafix.vn

www.vinafix.vn