8
7
6
5
4
3
2
1
+12V_BUS
CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX
+12V_BUS
+12V_BUS
C2
D D
+3.3V_BUS
+3.3V_BUS
C C
POWER SEQUENCING
B B
C3
150nF_16V
150nF_16V
LF CAP CER 150NF 10% 16V X7R (0603)
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
+3.3V_BUS
C5
C6
1uF_6.3V
1uF_6.3V
Place these caps last,
ideally as close to the bus
connector as possible
VMON1
VMON2
U41_VCC
U41_PGOOD
APL6535
+3.3V_BUS
U41_VCC
U41_PGOODU41_PGOOD SMPS_EN1
VMON1
VMON2
DNI
R6 0R
A_HSYNC_DAC1(3,7,14)
TP5 TP6
PETn0_GFXRn0(2)
PETp1_GFXRp1(2)
PETn1_GFXRn1(2)
PETp2_GFXRp2(2)
PETn2_GFXRn2(2)
PETp3_GFXRp3(2)
PETn3_GFXRn3(2)
PETp4_GFXRp4(2)
PETn4_GFXRn4(2)
PETp5_GFXRp5(2)
PETn5_GFXRn5(2)
PETp6_GFXRp6(2)
PETn6_GFXRn6(2)
PETp7_GFXRp7(2)
PETn7_GFXRn7(2)
PETp8_GFXRp8(2)
PETn8_GFXRn8(2)
PETp9_GFXRp9(2)
PETn9_GFXRn9(2)
PETp10_GFXRp10(2)
PETn10_GFXRn10(2)
PETp11_GFXRp11(2)
PETn11_GFXRn11(2)
PETp12_GFXRp12(2)
PETn12_GFXRn12(2)
PETp13_GFXRp13(2)
PETn13_GFXRn13(2)
PETp14_GFXRp14(2)
PETn14_GFXRn14(2)
PETp15_GFXRp15(2)
PETn15_GFXRn15(2)
+12V_BUS+3.3V_BUS
402
402
1%
1%
PRESENCE
PCI-EXPRESS EDGE CONNECTOR
+12V_BUS+3.3V_BUS +3.3V_BUS+12V_BUS
TESTEN_GND
JTAG_TRST#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
+12V#B1
+12V#B2
+12V#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1
3.3Vaux
WAKE#
RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82
Mechanical Key
x16 PCIe
PRSNT1#A1
+12V#A2
+12V#A3
GND#A4
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V#A9
+3.3V#A10
PERST#
GND#A12
REFCLK+
REFCLKGND#A15
PERp0
PERn0
GND#A18
RSVD#A19
GND#A20
PERp1
PERn1
GND#A23
GND#A24
PERp2
PERn2
GND#A27
GND#A28
PERp3
PERn3
GND#A31
RSVD#A32
RSVD#A33
GND#A34
PERp4
PERn4
GND#A37
GND#A38
PERp5
PERn5
GND#A41
GND#A42
PERp6
PERn6
GND#A45
GND#A46
PERp7
PERn7
GND#A49
RSVD#A50
GND#A51
PERp8
PERn8
GND#A54
GND#A55
PERp9
PERn9
GND#A58
GND#A59
PERp10
PERn10
GND#A62
GND#A63
PERp11
PERn11
GND#A66
GND#A67
PERp12
PERn12
GND#A70
GND#A71
PERp13
PERn13
GND#A74
GND#A75
PERp14
PERn14
GND#A78
GND#A79
PERp15
PERn15
GND#A82
MPCIE1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
PERp0
PERn0
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PERp4
PERn4
PERp5
PERn5
PERp6
PERn6
PERp7
PERn7
PERp8
PERn8
PERp9
PERn9
PERp10
PERn10
PERp11
PERn11
PERp12
PERn12
PERp13
PERn13
PERp14
PERn14
PERp15
PERn15
PRESENCE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
R2 0R
C7
100nF
C9
100nF
C11
100nF
C13
100nF
C15
100nF
C17
100nF
C19
100nF
C21
100nF
C23
100nF
C25
100nF
C27
100nF
C29
100nF
C31
100nF
C33
100nF
C35
100nF
C37
100nF
DNI
PERST#
C8
100nF
C10
100nF
C12
100nF
C14
100nF
C16
100nF
C18
100nF
C20
100nF
C22
100nF
C24
100nF
C26
100nF
C28
100nF
C30
100nF
C32
100nF
C34
100nF
C36
100nF
C38
100nF
R1 0R
TP1
PCIE_REFCLKP (2)
PCIE_REFCLKN (2)PETp0_GFXRp0(2)
GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)
GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)
GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)
GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)
GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)
GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)
GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)
GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)
GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)
GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)
GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)
GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)
GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)
GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)
GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)
GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)
TP2
TP3
TP4
A_VSYNC_DAC1 (3,7,14)
CRT1DDCDATA (3,14)
CRT3DDCCLK (3,17)TESTEN(3)
CRT1DDCCLK (3,14)
+3.3V
53
1
2
R_RST
Place R_RST in U_RST
C39
100nF
4
U5
NC7SZ08P5X_NL
PERST#_buf (2,16)
402
APL6536
ISL6536
+12V_BUS+3.3V_BUS +12V_BUS
R45
4.7K
402
Node 1
R41
475R
402
1%
A A
R42
200R
402
1%
R43
1.62K
402
1%
VMON2
Node 3
VMON1
Node 2
R44
200R
402
1%
8
5%
Q41
1
MMBT3904
2 3
Q42
1
MMBT3904
2 3
402
DNI
1
5mA
SMPS_EN1 SMPS_EN2
Q43
MMBT3904
2 3
7
402
1%
1%
SMPS_EN1 (8) SMPS_EN2 (9)
Q44
1
C43
100nF
MMBT3904
2 3
C44
100nF
6
Power Sequence Circuit to ensure SMPS_EN is released after
+12V_BUS and +3.3V_BUS are both in regulation.
Pull-up may or may not be required on SMPS_EN signal depending
on SMPS design.
Node 1 When +12V ramps above min Vbe, SMPS_EN will be helt low
When +3.3V gets close to regulation, one of the two
Node 2
conditions of releasing SMPS_EN is active
Target ~ 900mV when +3.3 at min regulation (worse case)
Typical trigger when +3.3V ramps above 2.2V (650mV)
Node 3 When +12V gets close to regulation, one of the two
conditions of releasing SMPS_EN is active
Target ~ 1.25V when +12 at min regulation (worse case)
Typical trigger when +12V ramps above 10V (1.1V)
5
4
SYMBOL LEGEND
DNI
DO NOT
INSTALL
#
ACTIVE
LOW
DIGITAL
GROUND
ANALOG
GROUND
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
3
Date: Sheet
2
105-A676xx-21
8
of
120Thursday, May 11, 2006
1
www.vinafix.vn
5
D D
4
3
2
1
NOTE: some of the PCIE testpoints will
be available trought via on traces.
PETp0_GFXRp0(1)
PETn0_GFXRn0(1)
PETp1_GFXRp1(1)
PETn1_GFXRn1(1)
PETp2_GFXRp2(1)
PETn2_GFXRn2(1)
PETp3_GFXRp3(1)
PETn3_GFXRn3(1)
PETp4_GFXRp4(1)
PETn4_GFXRn4(1)
PETp5_GFXRp5(1)
PETn5_GFXRn5(1)
PETp6_GFXRp6(1)
C C
B B
PETn6_GFXRn6(1)
PETp7_GFXRp7(1)
PETn7_GFXRn7(1)
PETp8_GFXRp8(1)
PETp9_GFXRp9(1)
PETn9_GFXRn9(1)
PETp10_GFXRp10(1)
PETn10_GFXRn10(1)
PETp11_GFXRp11(1)
PETn11_GFXRn11(1)
PETp12_GFXRp12(1)
PETn12_GFXRn12(1)
PETp13_GFXRp13(1)
PETn13_GFXRn13(1)
PETp14_GFXRp14(1)
PETn14_GFXRn14(1)
PETp15_GFXRp15(1)
PETn15_GFXRn15(1)
PCIE_REFCLKP(1)
PCIE_REFCLKN(1)
DNI DNI
402 402
PERST#_buf(1,16)
For Tektronix LA only
Place close
to ASIC
TP7
TP8
TP9
TP11
TP10
TP12
TP13
TP14
TP15
TP16
TP17
TP19 TP18
TP20
TP21
TP22
TP23
TP24
TP25
TP27
TP26
TP28
+3.3V
DNI
402
U1A
AJ31
AH31
AH30
AG30
AG32
AF32
AF31
AE31
AE30
AD30
AD32
AC32
AC31
AB31
AB30
AA30
AA32
Y32
Y31
W31
W30
V30
V32
U32
U31
T31
T30
R30
R32
P32
P31
N31
AL28
AK28
AG24
AA24
AF24
RV516 PRO A12 RH
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
Clock
PCIE_REFCLKP
PCIE_REFCLKN
PERSTB
PCIE_TEST
NC
PART 1 OF 7
P
C
I
E
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
Calibration
PCIE_CALRN
PCIE_CALRP
PCIE_CALI
AK27
AJ27
AJ25
AH25
AH28
AG28
AG27
AF27
AF25
AE25
AE28
AD28
AD27
AC27
AC25
AB25
AB28
AA28
AA27
Y27
Y25
W25
W28
V28
V27
U27
U25
T25
T28
R28
R27
P27
AE24
AD24
AB24
GFXTp0_PERp0 (1)
GFXTn0_PERn0 (1)
GFXTp1_PERp1 (1)
GFXTn1_PERn1 (1)
GFXTp2_PERp2 (1)
GFXTn2_PERn2 (1)
GFXTp3_PERp3 (1)
GFXTn3_PERn3 (1)
GFXTp4_PERp4 (1)
GFXTn4_PERn4 (1)
GFXTp5_PERp5 (1)
GFXTn5_PERn5 (1)
GFXTp6_PERp6 (1)
GFXTn6_PERn6 (1)
GFXTp7_PERp7 (1)
GFXTn7_PERn7 (1)
GFXTp8_PERp8 (1)
GFXTn8_PERn8 (1)PETn8_GFXRn8(1)
GFXTp9_PERp9 (1)
GFXTn9_PERn9 (1)
GFXTp10_PERp10 (1)
GFXTn10_PERn10 (1)
GFXTp11_PERp11 (1)
GFXTn11_PERn11 (1)
GFXTp12_PERp12 (1)
GFXTn12_PERn12 (1)
GFXTp13_PERp13 (1)
GFXTn13_PERn13 (1)
GFXTp14_PERp14 (1)
GFXTn14_PERn14 (1)
GFXTp15_PERp15 (1)
GFXTn15_PERn15 (1)
+PCIE
402
R82.0K
402
R9562R
402
R101.47K
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
5
4
3
2
Date: Sheet
105-A676xx-21
1
8
of
220Thursday, May 11, 2006
www.vinafix.vn
5
4
3
2
1
D D
C C
I2C DEVICE ADDRESS' ON DDC3
DEVICE
LM63
B B
+T2XVDDR
NS19NS_VIA
1 2
CRT3DDCDATA(17)
402
GND_T2XVSSR
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
ADDRESS
x100 1100
CRT3DDCCLK(1,17)
TESTEN(1)
TMDS2(LVTM) is not connected
NS15NS_VIA
1 2
+3.3V
R33
4.7K
402 402
+3.3V
+3.3V
+T2PVDD
GND_T2PVSS
CRT1DDCDATA(1,14)
R34
CRT2DDCDATA(15)
4.7K
R24 10K
Overlap Footprints
R25 499R
R26 499R
T2XCM
T2XCP
T2X0M
T2X0P
T2X1M
T2X1P
T2X2M
T2X2P
T2X3M
T2X3P
T2X4M
T2X4P
T2X5M
T2X5P
C226
100nF
C221
100nF
CRT1DDCCLK(1,14)
CRT2DDCCLK(15)
HPD1(14)
GPU_DPLUS(17)
GPU_DMINUS(17)
TP30
TESTEN
VREFG
XTALIN
XTALOUT
U1B
AL18
AM18
AK19
AL19
AL20
AM20
AL21
AM21
AK18
AJ18
AH18
AG18
AJ20
AK20
AE19
AE18
AF20
AE20
AF19
AC21
AC22
AD22
AE21
AD21
AE22
AF22
AF17
AF21
AK17
AJ19
AF18
AH17
AG17
AG19
AH19
AH22
AH23
AH13
AG13
AE12
AF12
AF11
AE13
AF13
AG12
AH12
AG14
AG22
AC8
AL26
AM26
RV516 PRO A12 RH
T2XCM
T2XCP
T2X0M
T2X0P
T2X1M
T2X1P
T2X2M
T2X2P
T2X3M
T2X3P
T2X4M
T2X4P
T2X5M
T2X5P
T2PVDD
T2PVSS
T2XVDDR_1
T2XVDDR_2
T2XVDDR_3
T2XVDDR_4
T2XVDDR_5
T2XVDDR_6
T2XVDDR_7
T2XVDDR_8
T2XVDDR_9
T2XVSSR_1
T2XVSSR_2
T2XVSSR_3
T2XVSSR_4
T2XVSSR_5
T2XVSSR_6
T2XVSSR_7
T2XVSSR_8
T2XVSSR_9
T2XVSSR_10
DDC1DATA
DDC1CLK
DDC2DATA
DDC2CLK
DDC3DATA
DDC3CLK
HPD1
SDA
SCL
DPLUS
DMINUS
PLLTEST
TESTEN
VREFG
XTALIN
XTALOUT
Integrated
TMDS2
Monitor
Interface
MMI2C
Thermal
Diode
Test
XTAL
PART 2 OF 7
V
I
D
E
O
&
M
U
L
T
I
M
E
D
I
A
Integrated
TMDS
DAC / CRT
DAC2 (TV/CRT2)
TMDS1 is routed through on the PCB, no 0R is needed.
AL9
TXCM
AM9
TXCP
AK10
TX0M
AL10
TX0P
AL11
TX1M
AM11
TX1P
AL12
TX2M
AM12
TX2P
AK9
TX3M
AJ9
TX3P
AK11
TX4M
AJ11
TX4P
AK12
TX5M
AJ12
TX5P
AM8
TPVDD
AL8
TPVSS
TXVDDR_1
TXVDDR_2
TXVDDR_3
TXVDDR_4
TXVSSR_1
TXVSSR_2
TXVSSR_3
TXVSSR_4
TXVSSR_5
HSYNC
VSYNC
RSET
AVDD_1
AVDD_2
AVSSQ
AVSSN_1
AVSSN_2
VDD1DI
VSS1DI
H2SYNC
V2SYNC
COMP
R2SET
A2VDD_1
A2VDD_2
A2VSSN_1
A2VSSN_2
A2VSSQ
VDD2DI
VSS2DI
NC_A2VDDQ
AJ6
AK6
AL6
AM6
AJ7
AK7
AL7
AM7
AK8
AK24
R
AM24
G
AL24
B
AJ23
AJ22
AL22
AL25
AM25
AK23
AK25
AJ24
AM23
AL23
AK15
R2
AM15
G2
AL15
B2
AF15
AG15
AJ15
Y
AJ13
C
AH15
AK14
AM16
AL16
AM17
AL17
AK13
AJ16
AJ17
AL14
C246
1uF_6.3V
C249
1uF_6.3V
A_R_DAC1 (14)
A_G_DAC1 (14)
A_B_DAC1 (14)
A_HSYNC_DAC1 (1,7,14)
A_VSYNC_DAC1 (1,7,14)
RSET
R31 499R
+AVDD
GND_AVSSQ
+VDD1DI
A_R_DAC2 (15)
A_G_DAC2 (15)
A_B_DAC2 (15)
A_HSYNC_DAC2 (7,15)
A_VSYNC_DAC2 (7,15)
DAC2_Y (16)
DAC2_C (16)
+A2VDD
+VDD2DI
R32 715R
C56
10nF
C59
10nF
DAC2_COMP (16)
C57
100nF
C60
1uF_6.3V
R2SET GND_A2VSSQ
TjXCM
TjXCP
TjX0M
TjX0P
TjX1M
TjX1P
TjX2M
TjX2P
TjX3M
TjX3P
TjX4M
TjX4P
TjX5M
TjX5P
C247
1uF_6.3V
C250
1uF_6.3V
C62
10nF
10V X7R
402 10%
C53
10nF
+TXVDDR
GND_AVSSQ
C63
100nF
10V X5R
402 10%
C54
100nF
C58
1uF_6.3V
+TPVDD
NS14 NS_VIA
12
GND_TPVSS
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
C251
NS13 NS_VIA
10uF
GND_TXVSSR
C64
1uF_6.3V
6.3V X5R
402 10%
C55
1uF_6.3V
12
NS5 NS_VIA
GND_AVSSQ
NS6 NS_VIA
GND_AVSSN
NS7 NS_VIA
GND_VSS1DI
NS8 NS_VIA
GND_A2VSSN
NS9 NS_VIA
GND_A2VSSQ
NS10 NS_VIA
GND_VSS2DI
Place close to ASIC
12
12
12
12
12
12
R136 182R
R132 182R
R133 182R
R134 182R
TjXCM (14)
TjXCP (14)
TjX0M (14)
TjX0P (14)
TjX1M (14)
TjX1P (14)
TjX2M (14)
TjX2P (14)
TjX3M (14)
TjX3P (14)
TjX4M (14)
TjX4P (14)
TjX5M (14)
TjX5P (14)
RTCLK(16)
+3.3V
A A
XTAL
XTAL_EN
5
XTALIN_S
XTALIN
C82
Y82
12pF_50V
XTALOUT
4
27.000MHz_10PPM
2 1
Change to 10ppm/10ppm p/n 5028270000G
C83
12pF_50V
XTALIN_S
XTALOUT_S
3
R_RTCLK
MR85 0R
R84
1M
MR86 0R
Place R_RTCLK close to XTAL so the
main clock line has shortest stub
XTALIN
XTALOUT
RTXTALIN (16)
RTXTALOUT (16)
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
Custom
2
Date: Sheet
105-A676xx-30
1
9
of
320Thursday, May 11, 2006
www.vinafix.vn
5
+MVDD
C301
1uF_6.3V
C311
D D
C C
B B
1uF_6.3V
C321
1uF_6.3V
C341
10uF
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
C303
C302
1uF_6.3V
1uF_6.3V
C312
C313
1uF_6.3V
1uF_6.3V
C326
C322
1uF_6.3V
1uF_6.3V
C343
C342
10uF
10uF
+MVDD
NS12 NS_VIA
1 2
GND_PVSS +PCIE
C305
C304
1uF_6.3V
C314
1uF_6.3V
C327
1uF_6.3V
C344
10uF
Possible alternate 5150005600G
NS16 NS_VIA
1uF_6.3V
C315
1uF_6.3V
C328
1uF_6.3V
C345
10uF
B54 BLM15BD121SN1
B55 BLM15BD121SN1
12
GND_VSSRH0
+3.3V
C241
1uF_6.3V
+3.3V
C236
1uF_6.3V
C306
1uF_6.3V
C316
1uF_6.3V
C329
1uF_6.3V
+PVDD
C231
1uF_6.3V
C242
1uF_6.3V
C237
1uF_6.3V
C69
10nF
C307
1uF_6.3V
C317
1uF_6.3V
C330
1uF_6.3V
C308
1uF_6.3V
C318
1uF_6.3V
C232
1uF_6.3V
NS17 NS_VIA
12
GND_VSSRH1
C243
1uF_6.3V
C238
1uF_6.3V
C70
100nF
4
C309
1uF_6.3V
C319
1uF_6.3V
C233
1uF_6.3V
C244
1uF_6.3V
CAP CER 10UF 10%
6.3V X5R (0805)1.4MM
MAX THICK
C239
1uF_6.3V
C71
1uF_6.3V
C310
1uF_6.3V
C320
1uF_6.3V
C245
10uF
C234
1uF_6.3V
+PVDD
GND_PVSS
U1E
C1
J1
M1
R1
V1
AA1
A3
P9
J10
N9
P10
A9
Y10
P8
R9
Y9
J11
A21
M10
N10
Y8
J18
J19
K21
A12
H13
A15
J20
J13
K11
K19
A18
L23
K20
K24
L24
H19
A24
K13
J32
A30
C32
F32
L32
A27
F1
A28
E1
AB9
AB10
AA9
AC19
AD18
AC20
AD19
AD20
AJ5
AM5
AL5
AK5
AE2
AE3
AE4
AE5
AJ14
AH14
RV516 PRO A12 RH
VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32
VDDR1_33
VDDR1_34
VDDR1_35
VDDR1_36
VDDR1_37
VDDR1_38
VDDR1_39
VDDR1_40
VDDR1_41
VDDR1_42
VDDR1_43
VDDR1_45
VDDR1_46
VDDRH0
VDDRH1
VSSRH0
VSSRH1
VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR3_8
VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4
VDDR5_1
VDDR5_2
VDDR5_3
VDDR5_4
PVDD
PVSS
Memory I/O
I/O
Clock
PART 5 OF 7
Memory
Selected PLL's
3
PCIE_PVSS
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
BBP_4
BBP_3
BBP_2
BBP_1
VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4
VDDCI_6
VDDCI_7
VDDCI_8
VDD25_1
VDD25_2
VDD25_3
VDD25_4
VDD25_5
VDD25_6
MPVDD
MPVSS
VDDPLL
V23
N23
P23
U23
W23
N29
N28
N27
N26
N25
AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27
AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18
V18
P18
P19
R19
W19
AD11
AC14
M23
V10
K18
W10
T14
W17
P16
T23
K14
U19
AC13
AC16
AC18
L10
K22
AA10
A6
A5
AC15
+VDDC
+MPVDD
GND_MPVSS
+VDDPLL
C214
1uF_6.3V
C202
C201
1uF_6.3V
1uF_6.3V
C191
C192
1uF_6.3V
1uF_6.3V
C162
C161
1uF_6.3V
1uF_6.3V
C172
C171
1uF_6.3V
1uF_6.3V
C211
1uF_6.3V
C206
1uF_6.3V
C67
1uF_6.3V
B56
C215
1uF_6.3V
BLM15BD121SN1
Possible alternate 5150005600G
PCIE_PVDD_12_1
PCIE_PVDD_12_2
PCIE_PVDD_12_3
PCIE_PVDD_12_4
PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4
PCIE_VDDR_12_5
PCIE_VDDR_12_6
PCIE_VDDR_12_7
PCIE_VDDR_12_8
PCIE_VDDR_12_9
PCIE_VDDR_12_10
PCIE_VDDR_12_11
PCIE_VDDR_12_12
PCIE_VDDR_12_13
PCI-Express
PCIE_VDDR_12_14
P
O
Core
W
E
R
I/0
I/O Internal
100nF
C203
1uF_6.3V
C193
1uF_6.3V
C163
1uF_6.3V
C173
1uF_6.3V
C66
C212
1uF_6.3V
C207
1uF_6.3V
2
+PCIE
C204
1uF_6.3V
GND_PCIE_PVSS
C194
1uF_6.3V
C164
1uF_6.3V
C174
1uF_6.3V
+VDDC
C208
1uF_6.3V
C65
10nF
C213
10uF
22uF_16V
NS18 NS_VIA
C195
1uF_6.3V
C165
1uF_6.3V
C175
1uF_6.3V
C209
1uF_6.3V
+MPVDD
C68
12
C196
1uF_6.3V
C166
1uF_6.3V
C177
1uF_6.3V
C197
1uF_6.3V
C167
1uF_6.3V
C178
1uF_6.3V
+VDDC_CT
C210
10uF
NS11NS_VIA
GND_MPVSS
1
+PCIE
C198
1uF_6.3V
C168
1uF_6.3V
C179
1uF_6.3V
12
C199
C200
10uF
10uF
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
C169
C170
1uF_6.3V
1uF_6.3V
C180
1uF_6.3V
C183
C181
C182
10uF
10uF
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
C184
10uF
10uF
+VDDC
C185
10uF
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
5
4
3
2
Date: Sheet
105-A676xx-21
1
8
of
420Thursday, May 11, 2006
www.vinafix.vn
5
4
3
2
1
RV530 MEMORY CHANNELS A and B
D D
C352
10nF
U1C
M31
DQA_0
M30
DQA_1
L31
DQA_2
L30
DQA_3
H30
DQA_4
G31
DQA_5
G30
DQA_6
F31
DQA_7
M27
DQA_8
M29
DQA_9
L28
DQA_10
L27
DQA_11
J27
DQA_12
H29
DQA_13
G29
DQA_14
G27
DQA_15
M26
DQA_16
L26
DQA_17
M25
DQA_18
L25
DQA_19
J25
DQA_20
G28
DQA_21
H27
DQA_22
H26
DQA_23
F26
DQA_24
G26
DQA_25
H25
DQA_26
H24
DQA_27
H23
DQA_28
H22
DQA_29
J23
DQA_30
J22
DQA_31
E23
DQA_32
D22
DQA_33
D23
DQA_34
E22
DQA_35
E20
DQA_36
F20
DQA_37
D19
DQA_38
D18
DQA_39
B19
DQA_40
B18
DQA_41
C17
DQA_42
B17
DQA_43
C14
DQA_44
B14
DQA_45
C13
DQA_46
B13
DQA_47
D17
DQA_48
E18
DQA_49
E17
DQA_50
F17
DQA_51
E15
DQA_52
E14
DQA_53
F14
DQA_54
D13
DQA_55
H18
DQA_56
H17
DQA_57
G18
DQA_58
G17
DQA_59
G15
DQA_60
G14
DQA_61
H14
DQA_62
J14
DQA_63
C31
MVREFD_0
C30
MVREFS_0
RV516 PRO A12 RH
M_MDA[63..0](12)
M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
M_MDA5
M_MDA6
M_MDA7
M_MDA8
M_MDA9
M_MDA10
M_MDA11
M_MDA12
M_MDA13
M_MDA14
M_MDA15
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
M_MDA21
M_MDA22
M_MDA23
M_MDA24
M_MDA25
M_MDA26
M_MDA27
M_MDA28
M_MDA29
MVREF_0
C351
100nF
M_MDA30
M_MDA31
M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA63
C C
+MVDD
R161
100R
1%
B B
R162
100R
1%
Channel A
Part 3 of 7
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7
MEMORY INTERFACE A
DDR1 DDR2 DDR3
Not usedbidir. strobe
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
bidir. differential strobe
QSA_7B
write stroberead strobe
ODTA0
For DDR2
ODTA1
CLKA0
CLKA0b
CKEA0
RASA0b
CASA0b
WEA0b
CSA0b_0
CSA0b_1
CLKA1
CLKA1b
CKEA1
RASA1b
CASA1b
WEA1b
CSA1b_0
CSA1b_1
R169
243R
U1D
B12
DQB_0
C12
DQB_1
B11
DQB_2
C11
DQB_3
C8
DQB_4
B7
DQB_5
C7
DQB_6
B6
DQB_7
F12
DQB_8
D12
DQB_9
E11
DQB_10
F11
DQB_11
F9
DQB_12
D8
DQB_13
D7
DQB_14
F7
DQB_15
G12
DQB_16
G11
DQB_17
H12
DQB_18
H11
DQB_19
H9
DQB_20
E7
DQB_21
F8
DQB_22
G8
DQB_23
G6
DQB_24
G7
DQB_25
H8
DQB_26
J8
DQB_27
K8
DQB_28
L8
DQB_29
K9
DQB_30
L9
DQB_31
K5
DQB_32
L4
DQB_33
K4
DQB_34
L5
DQB_35
N5
DQB_36
N6
DQB_37
P4
DQB_38
R4
DQB_39
P2
DQB_40
R2
DQB_41
T3
DQB_42
T2
DQB_43
W3
DQB_44
W2
DQB_45
Y3
DQB_46
Y2
DQB_47
T4
DQB_48
R5
DQB_49
T5
DQB_50
T6
DQB_51
V5
DQB_52
W5
DQB_53
W6
DQB_54
Y4
DQB_55
R8
DQB_56
T8
DQB_57
R7
DQB_58
T7
DQB_59
V7
DQB_60
W7
DQB_61
W8
DQB_62
W9
DQB_63
B3
MVREFD_1
C3
MVREFS_1
AA3
DRAM_RST
AA5
TEST_MCLK
AA2
TEST_YCLK
AA7
MEMTEST
RV516 PRO A12 RH
C356
10nF
M_MDB[63..0](13)
M_MDB0
M_MDB1
M_MDB2
M_MDB3
M_MDB4
M_MDB5
M_MDB6
M_MDB7
M_MDB8
M_MDB9
M_MDB10
M_MDB11
M_MDB12
M_MDB13
M_MDB14
M_MDB15
M_MDB16
M_MDB17
M_MDB18
M_MDB19
M_MDB20
M_MDB21
M_MDB22
M_MDB23
M_MDB24
M_MDB25
M_MDB26
M_MDB27
M_MDB28
M_MDB29
M_MDB30
M_MDB31
M_MDB32
M_MDB33
M_MDB34
M_MDB35
M_MDB36
M_MDB37
M_MDB38
M_MDB39
M_MDB40
M_MDB41
M_MDB42
M_MDB43
M_MDB44
M_MDB45
M_MDB46
M_MDB47
M_MDB48
M_MDB49
M_MDB50
M_MDB51
M_MDB52
M_MDB53
M_MDB54
M_MDB55
M_MDB56
M_MDB57
M_MDB58
M_MDB59
M_MDB60
M_MDB61
M_MDB62
M_MDB63
R172
R171
4.7K
R170
4.7K
4.7K
M_MAA0
D26
M_MAA1
F28
M_MAA2
D28
M_MAA3
D25
M_MAA4
E24
M_MAA5
E26
M_MAA6
D27
M_MAA7
F25
M_MAA8
C26
M_MAA9
B26
M_MAA10
D29
M_MAA11
B27
M_MAA12
E27
E29
M_MAA14
B25
M_MAA15
C25
M_DQMA#0
H31
M_DQMA#1
J29
M_DQMA#2
J26
M_DQMA#3
G23
M_DQMA#4
E21
M_DQMA#5
B15
M_DQMA#6
D14
M_DQMA#7
J17
M_QSA0
J31
M_QSA1
K29
M_QSA2
K25
M_QSA3
F23
M_QSA4
D20
M_QSA5
B16
M_QSA6
D16
M_QSA7
H15
K31
K28
K26
G24
D21
C16
D15
J15
F29
ODTA0 (12)
D24
D31
CLKA0 (12)
E31
CLKA#0 (12)
B30
CKEA0 (12)
B28
RASA#0 (12)
C29
CASA#0 (12)
B31
WEA#0 (12)
B29
CSA#0_0 (12)
C28
B20
CLKA1 (12)
C19
CLKA#1 (12)
C22
CKEA1 (12)
B24
RASA#1 (12)
B22
CASA#1 (12)
B21
WEA#1 (12)
B23
CSA#1_0 (12)
C23
M_MAA[12..0] (12)
M_MAA[15..14] (12)
M_DQMA#[7..0] (12)
M_QSA[7..0] (12)
+MVDD
R165
100R
1%
R166
100R
1%
MVREF_1
C355
100nF
Channel B
Part 4 of 7
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15
DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7
MEMORY INTERFACE B
DDR1 DDR2 DDR3
Not used bidir. strobe
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
QSB_0B
QSB_1B
QSB_2B
read strobe
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B
bidir. differential strobe
write strobe
ODTB0
For DDR2
ODTB1
CLKB0
CLKB0b
CKEB0
RASB0b
CASB0b
WEB0b
CSB0b_0
CSB0b_1
CLKB1
CLKB1b
CKEB1
RASB1b
CASB1b
WEB1b
CSB1b_0
CSB1b_1
G4
E6
E4
H4
J5
G5
F4
H6
G3
G2
D4
F2
F5
D5
H2
H3
B8
D9
G9
K7
M5
V2
W4
T9
B9
D10
H10
K6
N4
U2
U4
V8
B10
E10
G10
J7
M4
U3
V4
V9
D6
J4
B4
B5
C2
E2
D3
B2
D2
E3
N2
P3
L3
J2
L2
M2
K2
K3
M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB14
M_MAB15
M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7
M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7
ODTB0 (13)
CLKB0 (13)
CLKB#0 (13)
CKEB0 (13)
RASB#0 (13)
CASB#0 (13)
WEB#0 (13)
CSB#0_0 (13)
CLKB1 (13)
CLKB#1 (13)
CKEB1 (13)
RASB#1 (13)
CASB#1 (13)
WEB#1 (13)
CSB#1_0 (13)
M_MAB[12..0] (13)
M_MAB[15..14] (13)
M_DQMB#[7..0] (13)
M_QSB[7..0] (13)
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
5
4
3
2
Date: Sheet
105-A676xx-21
1
8
of
520Thursday, May 11, 2006
www.vinafix.vn
5
4
3
2
1
U1F
AH27
PCIE_VSS_1
AC23
PCIE_VSS_2
AL27
PCIE_VSS_3
R23
PCIE_VSS_4
P25
PCIE_VSS_5
R25
PCIE_VSS_6
T26
PCIE_VSS_7
D D
C C
B B
A A
5
4
U26
W26
Y26
AB26
AC26
AD25
AE26
AF26
AD26
AG25
AH26
AC28
Y28
U28
P28
AH29
AF28
V29
AC29
W27
AB27
V26
AJ26
AJ32
AK29
P26
P29
R29
T29
U29
W29
Y29
AA29
AB29
AD29
AE29
AF29
AG29
AJ29
AK26
AK30
AG26
N30
R31
AF30
AC30
V31
P30
AA31
U30
AD31
AK32
AJ28
Y30
AJ30
AK31
AA23
AG31
N24
AB23
P24
R24
T24
U24
V24
W24
Y24
AC24
AH24
V25
AA25
R26
AA26
T27
AE27
B1
H1
L1
P1
U1
Y1
AD7
AE8
AL1
A2
AM2
AD10
E8
H5
K10
M8
T10
E12
AC9
AF14
AD8
C5
F10
J3
L6
M6
P6
AA4
AG11
V3
AG16
R3
C6
C9
F6
H7
J6
RV516 PRO A12 RH
Y23
K15
R10
AC17
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
PCIE_VSS_33
PCIE_VSS_34
PCIE_VSS_35
PCIE_VSS_36
PCIE_VSS_37
PCIE_VSS_38
PCIE_VSS_39
PCIE_VSS_40
PCIE_VSS_41
PCIE_VSS_42
PCIE_VSS_43
PCIE_VSS_44
PCIE_VSS_45
PCIE_VSS_46
PCIE_VSS_47
PCIE_VSS_48
PCIE_VSS_49
PCIE_VSS_50
PCIE_VSS_51
PCIE_VSS_52
PCIE_VSS_53
PCIE_VSS_54
PCIE_VSS_55
PCIE_VSS_56
PCIE_VSS_57
PCIE_VSS_58
PCIE_VSS_59
PCIE_VSS_60
PCIE_VSS_61
PCIE_VSS_62
PCIE_VSS_63
PCIE_VSS_64
PCIE_VSS_65
PCIE_VSS_66
PCIE_VSS_69
PCIE_VSS_70
PCIE_VSS_71
PCIE_VSS_72
PCIE_VSS_73
PCIE_VSS_74
PCIE_VSS_75
PCIE_VSS_76
PCIE_VSS_77
PCIE_VSS_78
PCIE_VSS_79
PCIE_VSS_80
PCIE_VSS_81
PCIE_VSS_82
PCIE_VSS_83
PCIE_VSS_84
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
BBN_4
BBN_3
BBN_2
BBN_1
Part 6 of 7
CORE GND
VSS_45
VSS_44
VSS_43
VSS_42
VSS_41
VSS_40
VSS_39
VSS_38
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
PCI-Express GND
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_163
VSS_164
VSS_165
VEFUSE
3
AD16
AA6
P7
P5
M3
M9
L7
M7
AD17
AH11
A8
U7
C10
E9
F3
J9
N7
N3
Y5
AM13
AC10
Y6
U6
E5
AL13
A11
U8
U9
U10
R6
AD6
V6
AD14
AD13
D11
J12
K12
A13
F13
E13
F15
K16
J21
H16
T15
V17
C15
C4
U14
P15
A16
E16
G13
G16
P17
R16
R14
W16
C18
F16
W18
U18
AE16
AE17
A19
H32
F19
G19
N8
Y7
T19
V19
G21
C21
F21
AE14
AK16
U5
F22
F18
K30
C24
F24
M24
A25
D30
E25
G25
G20
G22
F27
E28
H21
C27
E32
H28
J30
K17
K27
M32
A22
C20
E19
H20
J24
M28
J28
J16
F30
L29
A31
B32
E30
AE15
AG23
AD9
AF16
AH10
AJ10
AD15
AH16
K23
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
2
Date: Sheet
105-A676xx-21
1
8
of
620Thursday, May 11, 2006
www.vinafix.vn
5
4
3
2
1
U1G
VID_[7..0](16)
D D
DVPDATA
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
C C
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
ALTERNATE USE
-
-
-
-
-
-
-
-
-
-
-
-
-
STV/HDTV#_OUT_DET (INPUT)
TESTOUT(0) (OUTPUT)
TESTOUT(1) (OUTPUT)
TESTOUT(2) (OUTPUT) / NTSC/PAL#_TVO_DET (INPUT)
TESTOUT(3) (OUTPUT)
TESTOUT(4) (OUTPUT)
TESTOUT(5) (OUTPUT)
TESTOUT(6) (OUTPUT)
TESTOUT(7) (OUTPUT)
STV/HDTV#_OUT_DET(16)
DEBUG BUS
No testpoint means the net
can be accessed from a pad
somewhere else
DVPDATA_16
TP31
DVPDATA_17
TP32
DVPDATA_18
TP33
DVPDATA_19
TP34
DVPDATA_20
TP35
DVPDATA_21
TP36
DVPDATA_22
TP37
DVPDATA_23
TP38
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7
VPCLK0(16)
VHAD_0(16)
VHAD_1(16)
VPHCTL(16)
VIPCLK(16)
DVPDATA_14
AF10
AG10
AE10
AH9
AJ8
AH8
AG9
AH7
AG8
AF7
AE9
AG7
AF9
AG1
AF2
AF1
AF3
AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7
VPCLK0
VHAD_0
VHAD_1
VPHCTL
VIPCLK
DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
VIP
Capture
VIP
Host
PART 7 OF 7
Zoom Video Port
General
Purpose
I/O
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GENERICA
GENERICB
GENERICC
GENERICD
ROMCSb
VARY_BL
No Connect
NC_DVOVMODE_0
NC_DVOVMODE_1
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
DVALID
PSYNC
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_22
AD4
AD2
AD1
AD3
AC1
AC2
AC3
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
AK22
AF23
AE23
AD23
AH6
AF8
AC7
AD12
AE11
AJ21
AK21
AH21
AG21
AG20
AH20
AB6
AK4
AL4
GENERICC
DVALID
PSYNC
ROMCSb
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
DEBUG BUS
No testpoint means the net
can be accessed from a pad
somewhere else
GPIO_10
GPIO_11
GPIO_12
GPIO_13
HPD2 (14)
GPIO_15 (10)
ThermINT (17)
GENERICA (14)
GENERICB (14)
GPIO PIN STRAP ALTERNATE USE
GPIO_0 YES VIDB_0 (OUTPUT)
GPIO_1 YES VIDB_1 (OUTPUT)
GPIO_2 YES VIDB_2 (OUTPUT)
GPIO_3 YES VIDB_3 (OUTPUT)
GPIO_4 YES VIDB_4 (OUTPUT)
GPIO_5 YES VIDB_5 (OUTPUT)
GPIO_6 YES LDAC (OUTPUT)
GPIO_7 NO PAL/NTSC TV (INPUT)
GPIO_8 YES GPIO_9 YES FLOW_CNTL_EN (OUTPUT)
GPIO_10 NO TESTOUT(8) (OUTPUT)
GPIO_11 YES TESTOUT(9) (OUTPUT)
GPIO_12 YES TESTOUT(10) (OUTPUT)
GPIO_13 YES TESTOUT(11 (OUTPUT))
GPIO_14 NO HPD_DVI1 (HPD2) (INPUT)
GPIO_15 NO VIDA#/B (OUTPUT)
GPIO_16 NO 12VEXT_DETECT (INPUT)
GPIO_17 NO T_INT#(INPUT) & 12VEXT_DETECT# (INPUT)
RV516 PRO A12 RH
PIN BASED STRAPS
+3.3V
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
R51 10K
R52 10K
R57 10K
R59 10K
R60 10K
R63 10K
R64 10K
R69 10K
R70 10K
MR53 10K
MR54 10K
MR55 10K
MR56 10K
MR58 10K
MR61 10K
MR62 10K
MR65 10K
MR66 10K
MR67 10K
MR68 10K
GPIO_0
GPIO_1
GPIO_3
B B
GPIO_2
GPIO_4
GPIO_6
GPIO_5
GPIO_8
GPIO_9
GPIO_13
GPIO_12
GPIO_11
A_VSYNC_DAC1(1,3,14)
A_HSYNC_DAC1(1,3,14)
A_VSYNC_DAC2(3,15)
A A
A_HSYNC_DAC2(3,15)
A_VSYNC_DAC1
A_HSYNC_DAC1
A_VSYNC_DAC2
A_HSYNC_DAC2
GENERICC
DVALID
PSYNC
GPIO_7
5
4
DNI
GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)
DNI
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)
GPIO(3:2) - Miscellaneous PCI-Express Modes
00: Halt impedance calibration before transmitter is enabled and enable receiver detection (Default
setting for Desktop)
01: Allow impedance calibration to continue on in the background AFTER transmitter has
been enabled and enable receive detection.
10: Bypass common-mode detection & receiver detection and halt impedance calibration before TX_EN.
11: Short-circuit internal loopback and halt impedance calibration before TX_EN and enable
receiver detection.
GPIO(4) - DEBUG_ACCESS: 0 for normal operation, 1 for debug mode
GPIO(6:5) - PLL_IBIAS_RD (Reduced mirror bias setting for PHY PLL)
DNI
Provide 4 different IBIAS settings - Set to 00 for R520
GPIO(8) - FORCE_COMPLIANCE: 0 for Normal operation, 1 for Force into Compliance Mode
DNI
GPIO(9,13:11) - ROMIDCFG[3..0]
1001 - 1M AT25F1024 ROM (Atmel)
1010 - 1M AT45DB011 ROM (Atmel)
DNI
1011 - 1M M25P10 ROM (ST)
1100 - 512K M25P05 ROM (ST) (ATI default)
1101 - 1M SST45LF010 ROM (SST), 1M W45B512 ROM (WinBond), 512K W45B012 ROM (WinBond)
1110 - 1M SST25VF010 ROM (SST), 512K SST25VF512 ROM (SST)
1111 - 1M NX25F011B ROM (NexFlash)
VSYNC - VIP_DEVICE
0: Slave VIP host port devices present (use if Theater is populated)
1: No slave VIP host port devices reporting presence during reset (use for configurations without video-in)
HSYNC - DWNGRD
DNI
This straps allow a Workstation bonded part to be downgraded to a normal part on a board. This
allow inventory management to better balance demand.
0 - Device remain a Workstation grade part
1 - Part is downgraded to a Normal part
H2SYNC, V2SYNC, GENERICC - Star Memory System repair mode
000 - Default
Memory Vendor Straps for DDR2 16Mx16 and 32Mx16: ------------->
TV OUT STANDARD (Jumper position overwrite resistor settings)
0 - PAL TVO (Jumper position 2-3)
1 - NTSC TVO (Jumper position 1-2)
3
ATI Feature I
ATI Board Feature II
ATI Board Feature II
ATI PCIE FEATURE I
ATI PCIE FEATURE II
ATI PCIE FEATURE III
ATI Feature II
GPIO_8
GPIO_9
GPIO_10
ROMCSb
+3.3V
R36
10K
[31:24]@ MEMTYPE[1:0]
MC_MISC_0 [PSYNC:DVAILD] Memory
___________________________________________________________________
20h [ 0 : 0 ] Common and Infineon 16Mx16 2.0V
21h [ 0 : 1 ] Samsung 16Mx16
22h [ 1 : 0 ] Infineon 16Mx16 1.8V
23h [ 1 : 1 ] Hynix 16Mx16
24h [ 0 : 0 ] Micron 16Mx16
25h [ 0 : 1 ] Elpida 16Mx16
26h [ 1 : 0 ] Reserved
27h [ 1 : 1 ] Reserved
28h [ 0 : 0 ] Common 32Mx16
29h [ 0 : 1 ] Samsung 32Mx16
2Ah [ 1 : 0 ] Infineon 32Mx16
2Bh [ 1 : 1 ] Hynix 32Mx16
2Ch [ 0 : 0 ] Micron 32Mx16
2Dh [ 0 : 1 ] Elpida 32Mx16
2Eh [ 1 : 0 ] Reserved
2Fh [ 1 : 1 ] Reserved
2
+3.3V
R35
10K
U2
D
C
S
HOLD
W
VCC
VSS
M25P05-AVNM6P
105-A676xx-30
2
Q
4
VIDEO BIOS
FIRMWARE
of
1
720Thursday, May 11, 2006
5
6
1
+3.3V
7
3
8
C51
100nF
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
Date: Sheet
9
www.vinafix.vn
8
7
6
5
4
3
2
1
VDDC-PWM1
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
VCC
+VDDC_B
+PW_VDDC_LGD
+PW_VDDC_HGD
+VDDC_VCC
14
13
12
11
10
9
8
+12V_BUS_F1
C604
0.22uF
+VDDC_B
+PW_VDDC_LGD
+PW_VDDC_HGD
+PW_VDDC_M
SMPS_EN1 (1)
+PW_VDDC_HGD
+PW_VDDC_M
+PW_VDDC_LGD
R621 0R
R622 0R
+PW_VDDC_HGDR
402
+PW_VDDC_LGDR
402
VDDC_SS
VDDC_FB
+VDDC_S
VDDC_COMP
VDDC_FB
1% 1%
R602 30.1K
C602 1nF
R603 2.37K
R604 0R
D D
+VDDC_S
C601
15nF_50V
603
C C
VDDC_UVIN
402402
+3.3V_BUS
X7R 10V
402
402
VDDC_RT
402
VDDC_OCS
VDDC_SS
VDDC_COMP_U601
VDDC_COMP_U601
+PW_VDDC_M
R601 10K
SIPEX SP6132A p/n 2480054700G
402
VDDC_EN
VDDC-PWM2
U601
1
RT
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
RT9232A
INTERSIL ISL6522/ISL6535
RICHTEK RT9232/RT9232A
ANPEC APW7062A
ANPEC APW7062B
QH
Q603
4 5
3
2
1
BSC119N03SG
Q602
QL
4 5
3
2
1
BSC032N03S G
Thermal
Thermal
Pad
9
6
7
8
Pad
9
6
7
8
VDDC-PWM3
VDDC_FB
VDDC_COMP
+12V_BUS_F1
+PW_VDDC_HGD
+VDDC_B
+PW_VDDC_LGD
VDDC_COMP_U104
RICHTEK RT9214
INTERSIL ISL6545
VDDC-PWM4
+PW_VDDC_M
VDDC_EN
VDDC_FB
+VDDC_B
+12V_BUS_F1
402
402
+PW_VDDC_LGD
+PW_VDDC_HGD
+PW_VDDC_M
+PW_VDDC_HGDR +PW_VDDC_LGDR
+VDDC_S +VDDC_S
+PW_VDDC_M
CAP CER 10UF 20% 16V X5R
+VDDC_S
(1206)1.8MM H MAX
C615
10UF
NL601 1.7UH
1 2
1210
1%
402
X7R
25V
Place Rs and Cs across QL
RC snubber values shown
are for reference only,
tuning is required
MULTI FOOTPRINT
1210
1%
Cs
C616
10UF
Rs
1206
MULTI FOOTPRINT
VDDC_FB(10)
VDDC_FB
***
C621
C622
10UF
10UF
1206
1206 1206120612061206
***
C618
150nF_16V
603
**
**
ALT ALT
R1
R611
200R
402
1%
R4
R610
324R
402
1%
Place R1 and
R4 close to
PWM and
routed with
separate
20mil trace to
the ASIC
0.8V Ref
R4 = (R1 x 0.8V) / (Vout1 - 0.8V)
***
C625
470uF_10V
***
TH TH
+12V_BUS
B601
60R_6A
***
***
+VDDC
**
**
CAP CER 10UF 10%
6.3V X5R (0805)1.4MM
MAX THICK
DUAL FOOTPRINT DUAL FOOTPRINT
+VDDC
***
***
ALT
POLY
DUAL FOOTPRINT
***
C626
470uF_10V
***
DUAL FOOTPRINT
***
***
ALT
POLY
ANPEC APW7061A
B B
This symbol is used for 103 SMPS p/n.
VDDC1
402
VDDC_EN
VDDC_COMP
Regulator for VDDC (ASIC Core)
Vout = 1V ~ 1.3V
COMPENSATION CIRCUIT FILTERED +12V_BUS BOOT CIRCUIT
MR606
0R
402 402
R605
0R
16V
+5V+12V_BUS
402
C606
150nF_16V
+PW_VDDC_M
+VDDC_VCC
+VDDC_B
Part
0.8V Ref 1.2Vmin/1.22Vnorm/1.24Vmax
5
4
3
Vout
200R
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
Custom
Date: Sheet
2
105-A676xx-21
R2R1
383R
p/n 3160383000G (402 1%)p/n 3160200000G (402 1%)
8
of
820Thursday, May 11, 2006
1
+12V_BUS
402
C612
390pF
603
50V
10%
NPOX5R
R616 0R
402
VDDC_COMP
VDDC_FB
402
7
+12V_BUS_F1
+12V_BUS
R607
2.2R
C607
100nF
MD601
BAT54S
603
X7R
5%
C605
100nF
603
X7R
5%
6
C611
100nF
10V
A A
402
R612
1.3K
402
1%
10%
8
www.vinafix.vn
8
7
6
5
4
3
2
1
Thermal
Thermal
+MVDDC_S
Pad
9
6
7
8
CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX
*** ***
C716
C715
10UF
10UF
*** ***
L701 2.2uH_13A
1 2
1206
603
Rs
Pad
9
6
7
8
R719
0.51R
1210
1%
C708
10nF_25V
Cs
402
X7R
25V
Place Rs and Cs across QL
MVDDC_FB
R1
R711
1.78K
402
1%
R4
R710
1.37K
402
1%
RC snubber values shown
are for reference only,
tuning is required
MULTI FOOTPRINT
Place R1 and
R4 close to
PWM and
routed with
separate
20mil trace to
the ASIC
+12V_BUS
B701
60R_6A
***
+MVDD
***
C725
470uF_10V
***
DUAL FOOTPRINT
0.8V Ref
R4 = (R1 x 0.8V) / (Vout1 - 0.8V)
***
***
ALT
POLY
*** ***
1210 1210
*** ***
Q701
QH
MVDDC-PWM1
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
VCC
+PW_MVDDC_HGD
+PW_MVDDC_LGD
+MVDDC_VCC
+12V_BUS_F2
14
13
12
+MVDDC_B
11
10
9
8
C704
0.22uF
+PW_MVDDC_LGD
+PW_MVDDC_HGD
+PW_MVDDC_M
SMPS_EN2 (1)
+MVDDC_S
603
1%
D D
C C
402
X7R
+MVDDC_S
MVDDC_COMP
C701
22nF
603
R702 30.1K
C702 1nF
R703 2.37K
402
NPO
5%
402
402
R704 0R
402
MVDDC_EN
MVDDC_FB
+PW_MVDDC_M
+MVDDC_B
+3.3V_BUS
R701 10K
MVDDC_RT
402
X7R10V
MVDDC_OCS
MVDDC_SS
MVDDC_COMP_U1049
MVDDC_FB
HSD
MAXIM MAX1954
MAXIM MAX1954A
MVDDC_EN
402
MVDDC-PWM2
U701
1
RT
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
RT9232PS
INTERSIL ISL6522
RICHTEK RT9232A
ANPEC APW7062A
ANPEC APW7062B
+PW_MVDDC_HGD
+PW_MVDDC_M
+PW_MVDDC_LGD
+PW_MVDDC_HGDR
R721 0R
R722 0R
+MVDDC_S
+PW_MVDDC_HGDR
402
+PW_MVDDC_LGDR
402
4 5
3
2
1
BSO119N03S
Q702
QL
4 5
3
2
1
BSO119N03S
+PW_MVDDC_LGDR
MVDDC-PWM3
+PW_MVDDC_HGD
+MVDDC_B
+PW_MVDDC_LGD
RICHTEK RT9214
INTERSIL ISL6545
+PW_MVDDC_M
MVDDC_EN
MVDDC_FB
+12V_BUS_F2
402
+PW_MVDDC_M
B B
MVDDC_FB
MVDDC_COMP
+12V_BUS_F2
MVDDC_COMP_U204
402
+MVDDC_B
+PW_MVDDC_LGD
+PW_MVDDC_HGD
+PW_MVDDC_M
402
ANPEC APW7061A
MVDDC-PWM4
MVDDC_EN MVDDC_COMP
402
This symbol is used for 103 SMPS p/n.
MVDD1
RV410SOCKET
Regulator for MVDD
Vout = 1.8V ~ 2.85V
COMPENSATION CIRCUIT FILTERED +12V_BUS BOOT CIRCUIT
MR706
0R
402 402
R705
0R
16V
+5V+12V_BUS
402
C706
150nF_16V
+MVDDC_VCC
+MVDDC_B
+PW_MVDDC_M
5
4
3
+12V_BUS
402402
A A
C711
10nF
402
10V
10%
R712
6.81K
402
1%
C712
33pF
603
50V
NPOX7R
10%
R716 0R
402
8
MVDDC_COMP
MVDDC_FB
402
+12V_BUS_F2
7
+12V_BUS
R707
2.2R
C707
100nF
MD701
BAT54S
603
X7R
5%
C705
100nF
603
X7R
5%
6
Part R2R1
0.8V Ref
Vout
1.9V
2.0V 1.69K 1.1K
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
Custom
Date: Sheet
2
1.78K 1.3K
1.78K 1.21K
105-A676xx-21
8
of
920Thursday, May 11, 2006
1
www.vinafix.vn
8
D D
C C
7
Regulator for +MVDDQ
Vout = 1.85V ~ 2.65V
Iout = 2.5A MAX
+MVDD_Source
6
+3.3V
1/4W
1/4W
1206
1206
1/4W
1206
5
1/4W
1/4W
1/4W
1/4W
1206
1206
MVDD_EN(11)
1206
1206
1/4W
1206
4
Place Big Copper Area Under QMVDD
pin 2 and 4 for Heat Dissipation.
3
2
1
12A 60V
Rds(on) = 0.15R MAX
Rm1
Rm2
QMVDD
402
1%
R6 = (R5 x Vref) / (Vout - Vref)
603
1%
+MVDD
**
**
ALT
DUAL FOOTPRINT
CAP CER 10UF 10% 6.3V X5R
B B
(0805)1.4MM MAX THICK
**
**
ALT
DUAL FOOTPRINT
MVDD_G
MVDD_FB
Option for Dynamic VDDC
+5V
GPIO15 LO = LED "OFF" AND 1.2V VDDC
GPIO15 HI = LED "ON" AND 1.0V VDDC
A A
GPIO_15(7)
+12V_BUS
1/4W
1206
5%
VDDC_FB(8)
Install a 0 Ohm resistor for
Rx for regular operation
Voltage Req.
2.85V
2.55V 316022R100G22.1R
2.5V
402
VCORE_PLAY
402
Rx
Rm1 Rm2
1.1K
0R 3150000000 DNI
681R 3160681000G 953R 3240953000
3160681000G681R2.0V min
562R1.9V min, 1.94V nom. 1K
3240110100G
1.1K 3240110100G
2.5V Ref.
2.5V Ref.
1.24V Ref.2.1V min
1.24V Ref.
1.24V Ref.3160562000G 3160100100G
402
402 402
+3.3V
8
7
6
5
4
3
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
Custom
Date: Sheet
2
105-A676xx-21
of
10 20Thursday, May 11, 2006
1
8
www.vinafix.vn
8
+3.3V_BUS
+2.5V_REF
4
1
2
5V_EN
8
C901
10uF
+2.5V
+12V_BUS
3
2
1%
DNI
5
6
R923
1K
1%
10
9
R933
1K
1%
12
13
R943
1K
1%
+
-
+
-
R922 1K
+
-
R932 1K
+
-
R942 1K
ALT
Possible alternate
5150005600G
Place caps very
close to power pin
C902
C903
100nF
100nF
603
603
X7R
X7R
411
R910 0R
1
U901A
LM324MX_NL
R912 0R
R920 0R
7
U901B
LM324MX_NL
1%
Req = 120.7R
Use 845R, 1206, 1/4W
8
U901C
LM324MX_NL
1%
Req = 120.7R
Use 845R, 1206, 1/4W
14
U901D
LM324MX_NL
1%
R901
33R
402
REG901
TL431C
D D
+2.5V_REF
+VDDC
C C
B B
A A
+2.5V_REF
+2.5V_REF
+2.5V_REF
NC
NC
5 3
R911 1K
R921 1K
R931 1K
R941 1K
7
Alt regulator for +MPVDD
Vout = 1.2V (not tracking to VDDC)
Iout = 10mA MAX
+3.3V
+3.3V
Q911
1
MMBT3904
200mA, SOT-23
2 3
CMPT3904: 40V 200mA
R914
4.99R
R924 40.2R
+MPVDD
1%
1%
~ 2.5V Drop MAX
200mW MAX
+VDDC
ALT
Possible alternate 5150005600G
Rt1
402
Rt2
402
GND_MPVSS
C916
10uF
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
+MPVDD
C911
10uF
1/4 W
270mW MAX for 60mA
Q921
1
R930 0R
R925 0R
1
1
2 3
7
MMBT3904
200mA, SOT-23
2 3
CMPT3904: 40V 200mA
R934
845R
Q931
MMBT3904
200mA, SOT-23
2 3
CMPT3904: 40V 200mA
R945
R944
845R
845R
Q941
MMBT3904
200mA, SOT-23
CMPT3904: 40V 200mA
R935
845R
C921
10uF
R946
845R
R936
845R
+5V
R937
845R
+5V_VESA
Multi-footprint
C931
10uF
R947
845R
+5V_VESA2
Multi-footprint
C941
10uF
6
Rt1
1.61V 432R
1.69V
1.718V
562R
1.75V
C928
100nF
603
16V 16V
X7R X7R
+5V
5V
60mA MAX
R940
R939
R948
845R
R938
845R
R949
845R
845R
845R
R950
845R
6
32404320001.52V 432R
3160432000 3160215100
3240432000
3240432000432R
3240562000
3160604000604R
3160604000 604R1.8V
+12V_BUS
C927
100nF
603
603
16V 16V
X7R X7R
603
16V 16V
X7R X7R
+2.5V +AVDD +A2VDD
B921
0R
Rt2
2.15K
1.5K
3230015200
1.5K 3160150100
3240121100
1.21K
32300152001.5K
1.5K 3160150100
32300152001.5K
1.5K 3160150100
31601371001.37K
C926
10UF
CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX
+12V_BUS
603
CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX
+12V_BUS
603
CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX
B922
BLM15BD121SN1
Possible alternate 5150005600G
5
Optional regulator for +PCIE
Vout = 1.2V ~1.25V
Iout = 1.2A MAX
+PCIE_SOURCE
+3.3V +2.5V
+5V
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
Optional regulator for I/O
Vout = 2.5V~2.65V
Iout = 1A MAX
+5V
C968
1uF_6.3V
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
Optional regulator for +VDDC_CT
Vout = 2.5V ~ 2.85V
Iout = 100mA MAX for 2.85V or
C966
10uF
U951_VCNTL
U951_VIN
U961_VCNTL
U961_VIN
+2.5V_REF
R961
0R
4
+2.5V_REF
+5V
1A MAX for 2.5V~2.65V
+3.3V +VDDC_CT
+VDDC
R981
1K
402
1%
C979
402
1uF_6.3V
1%
DNI
+VDD1DI +VDD2DI +PVDD
B923
BLM15BD121SN1
B924
BLM15BD121SN1
5
+5V
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
+12V_BUS
R983
5.1K
402
5%
R986 5.1K
Q991
1
MMBT3904
2 3
B925
BLM15BD121SN1
U971_VCNTL
U971_VIN
+3.3V
402
5%
+5V
5V_EN
1
2 3
B926
BLM15BD121SN1
4
U951_REFEN
U961_REFEN
C964
1uF_6.3V
U971_REFEN
Q992
MMBT3904
402
5%
+TPVDD +TXVDDR
B927
BLM15BD121SN1
3
+VDDC +PCIE
RP951A 0R
8 1
RP951B 0R
7 2
RP951C 0R
6 3
RP951D 0R
5 4
+PCIE
U951_VOUT
CAP CER 10UF 10%
6.3V X5R (0805)1.4MM
MAX THICK
+MVDD
U961_VOUT
R963
1K
CAP CER 10UF 10%
6.3V X5R (0805)1.4MM
MAX THICK
+MVDD +VDDC_CT
U971_VOUT
CAP CER 10UF 10%
6.3V X5R (0805)1.4MM
MAX THICK
R988 5.1K
B929
0R
+12V_BUS
1
402
5%
2 3
B930
0R
3
MVDD_EN (10)
B928
BLM15BD121SN1
+T2PVDD +T2XVDDR
2
RT9199 p/n 2480054800G (480mR RdsON Max)
RT9199A (300mR RdsON Max)
RT9173C (250mR RdsON Max)
APL5331 p/n 2480054200G (350mR MAX for 2A)
U951_VIN
U951_REFEN U951_VCNTL
U951_VOUT
Supported footprint:
RT9173C/RT9199A/RT9199
APL5331
+2.5V
U961_VIN
U961_REFEN
U961_VOUT
C961
10uF
U971_VIN
U971_REFEN
U971_VOUT
+3.3V_BUS +PCIE_SOURCE
R984
10K
Q994
MMBT3904
U961
1
VIN
NC#8
2
GND
NC#7
3
VREF
VCNTL
VOUT4NC
THM
RT9199
Supported footprint:
RT9173C/RT9199A/RT9199
APL5331
RP972A 0R
8 1
RP972B 0R
7 2
RP972C 0R
6 3
RP972D 0R
5 4
Supported footprint:
RT9173C/RT9199A/RT9199
APL5331
C992
10uf
1206
Y5V
6.3V
Q995_G
C991
100NF
402
X5R
16V
Q995
IRF7413TRPBF
678
123
4 5
2
8
7
U961_VCNTL
6
5
9
+2.5V
U971_VCNTL
+3.3V
1/4W 1/4W 1/4W 1/4W 1/4W1/4W
ALT
Req ~= 0.78R
R985
Vdrop_max = 0.95V @ 1.2A
100K
+PCIE_SOURCE ~= 2.35V
For 1.2A, each resistor (250mW
rated) dissipates 0.2A or 190mW
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
Date: Sheet
105-A676xx-30
1
11 20Thursday, May 11, 2006
1
9
of
www.vinafix.vn
8
7
6
5
4
3
2
1
CHANNEL A: RANK 0 128MB DDR2
M_DQMA#[7..0](5)
D D
M_MDA[63..0](5)
M_MAA[15..14](5)
M_MAA[12..0](5)
C C
VREF_A0
+MVDD +MVDD +MVDD
R201
4.99K
B B
R202
4.99K
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7
M_MAA14
M_MAA15
M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0
CLKA#0(5)
CLKA0(5)
CKEA0(5)
CSA#0_0(5)
WEA#0(5)
RASA#0(5)
CASA#0(5)
M_DQMA#2
M_DQMA#3
ODTA0(5)
M_QSA2
R211 10R
M_QSA3
R212 10R
VREF_U20
C413
100nF
L2
L3
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
K8
J8
K2
L8
K7
L7
F3
B3
K9
F7
E8
B7
A8
J2
A2
E2
L1
R3
R7
R8
M_QSA[7..0](5)
U201
BA0
BA1
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CK
VDDQ1
CK
VDDQ2
VDDQ3
CKE
VDDQ4
VDDQ5
VDDQ6
VDDQ7
CS
VDDQ8
VDDQ9
WEK3VDDQ10
RAS
CAS
LDM
UDM
VSSDL
ODT
LDQS
VSSQ1
LDQS
VSSQ2
VSSQ3
VSSQ4
VSSQ5
UDQS
VSSQ6
UDQS
VSSQ7
VSSQ8
VREF
VSSQ9
VSSQ10
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
HYB18T256161AFL-25
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSS1
VSS2
VSS3
VSS4
VSS5
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_MDA27
B9
M_MDA30
B1
M_MDA24
D9
M_MDA29
D1
M_MDA31
D3
M_MDA25
D7
M_MDA28
C2
DQ9
M_MDA26
C8
DQ8
M_MDA19
F9
DQ7
M_MDA20
F1
DQ6
M_MDA16
H9
DQ5
M_MDA23
H1
DQ4
M_MDA22
H3
DQ3
M_MDA17
H7
DQ2
M_MDA21
G2
DQ1
M_MDA18
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
+MVDD
+MVDD
B201
BLM15BD121SN1
Possible alternate 5150005600G Possible alternate 5150005600G Possible alternate 5150005600G Possible alternate 5150005600G
C411
C412
100nF
1uF_6.3V
VREF_A0
M_MAA14
M_MAA15
M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0
CLKA#0(5)
CLKA0(5)
CKEA0(5)
CSA#0_0(5)
WEA#0(5)
RASA#0(5)
CASA#0(5)
M_DQMA#0
M_DQMA#1
ODTA0(5) ODTA0(5) ODTA0(5)
M_QSA0 M_QSA5
R213 10R
M_QSA1
R214 10R R218 10R
R203
4.99K
VREF_U21
R204
C438
4.99K
100nF
U202
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HYB18T256161AFL-25
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
M_MDA12
B9
M_MDA11
B1
M_MDA15
D9
M_MDA8
D1
M_MDA9
D3
M_MDA14
D7
M_MDA10
C2
DQ9
M_MDA13
C8
DQ8
M_MDA4
F9
DQ7
M_MDA3
F1
DQ6
M_MDA7
H9
DQ5
M_MDA0
H1
DQ4
M_MDA1
H3
DQ3
M_MDA6
H7
DQ2
M_MDA2
G2
DQ1
M_MDA5
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
B202
BLM15BD121SN1
C437
C436
1uF_6.3V
100nF
+MVDD
+MVDD
VREF_A1
M_MAA14
M_MAA15
M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0
CLKA#1(5)
CLKA1(5)
CKEA1(5)
CSA#1_0(5)
WEA#1(5)
RASA#1(5)
CASA#1(5)
M_DQMA#7 M_DQMA#4
R215 10R
M_QSA7
R216 10R
R205
4.99K
VREF_U22
R206
C463
4.99K
100nF
U203
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HYB18T256161AFL-25
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
U204
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HYB18T256161AFL-25
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
M_MDA35
B9
M_MDA36
B1
M_MDA32
D9
M_MDA39
D1
M_MDA38
D3
M_MDA34
D7
M_MDA37
C2
DQ9
M_MDA33
C8
DQ8
M_MDA51
F9
DQ7
M_MDA52
F1
DQ6
M_MDA50
H9
DQ5
M_MDA55
H1
DQ4
M_MDA54
H3
DQ3
M_MDA48
H7
DQ2
M_MDA53
G2
DQ1
M_MDA49
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
B204
BLM15BD121SN1
C447
C446
1uF_6.3V
100nF
+MVDD
+MVDD
R217 10R
R207
4.99K
VREF_U23
R208
4.99K
M_MAA14
M_MAA15
M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0
CSA#1_0(5)
M_DQMA#6M_DQMA#5
M_QSA6
M_QSA4
C448
100nF
CLKA#1(5)
CLKA1(5)
CKEA1(5)
WEA#1(5)
RASA#1(5)
CASA#1(5)
M_MDA61
B9
M_MDA59
B1
M_MDA63
D9
M_MDA56
D1
M_MDA57
D3
M_MDA62
D7
M_MDA58
C2
DQ9
M_MDA60
C8
DQ8
M_MDA45
F9
DQ7
M_MDA42
F1
DQ6
M_MDA46
H9
DQ5
M_MDA40
H1
DQ4
M_MDA41
H3
DQ3
M_MDA47
H7
DQ2
M_MDA43
G2
DQ1
M_MDA44
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
B203
M9
BLM15BD121SN1
R1
J1
J7
C461
100nF
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
C462
1uF_6.3V
+MVDD
+MVDD
VREF_A1
+MVDD
+MVDD
C402
C401
1uF_6.3V
+MVDD
C406
1uF_6.3V
402
A A
8
C403
1uF_6.3V
1uF_6.3V
402402402
C407
C408
1uF_6.3V
1uF_6.3V
402 402 402
7
C409
1uF_6.3V
C410
1uF_6.3V
402
CLKA0(5)
CLKA#0(5)
CLKA1(5)
CLKA#1(5)
R221
56R
402
R222
56R
402 402
R223
56R
402
R224
56R
402 402
6
+MVDD
C427
C426
1uF_6.3V
402 402402
+MVDD
C431
1uF_6.3V
402 402
C499
10nF
C500
10nF
C428
1uF_6.3V
1uF_6.3V
C432
C433
1uF_6.3V
402 402 402 402
C434
1uF_6.3V
1uF_6.3V
+MVDD +MVDD
R209
4.99K
VREF_A0 VREF_A1
R210
4.99K
5
C435
1uF_6.3V
R219
4.99K
R220
4.99K
+MVDD
C451
1uF_6.3V
402 402402
+MVDD
C456
1uF_6.3V
4
C453
C452
1uF_6.3V
1uF_6.3V
C458
C457
1uF_6.3V
1uF_6.3V
402 402 402
C459
1uF_6.3V
C460
1uF_6.3V
402
3
+MVDD
C478
C477
C476
1uF_6.3V
402 402402
+MVDD
C481
1uF_6.3V
402
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
Date: Sheet
2
1uF_6.3V
1uF_6.3V
C482
1uF_6.3V
402 402 402 402
C483
1uF_6.3V
C484
1uF_6.3V
105-A676xx-21
C485
1uF_6.3V
1
of
12 20Thursday, May 11, 2006
8
www.vinafix.vn
8
7
6
5
4
3
2
1
CHANNEL B: RANK 0 128MB DDR2
M_DQMB#[7..0](5)
D D
M_MDB[63..0](5)
M_MAB[15..14](5)
M_MAB[12..0](5)
C C
R311 10R
VREF_B0
R312 10R
+MVDD
R301
4.99K
VREF_U24 VREF_U25 VREF_U26 VREF_U27
R302
4.99K
B B
M_MAB14
M_MAB15
M_MAB12
M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0
CLKB#0(5)
CLKB0(5)
CKEB0(5)
CSB#0_0(5)
WEB#0(5)
RASB#0(5)
CASB#0(5)
M_DQMB#2
M_DQMB#3
ODTB0(5)
M_QSB2
M_QSB3
C513
100nF
M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7
U301
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HYB18T256161AFL-25
+MVDD
C501
1uF_6.3V
402 402402
+MVDD
C506
1uF_6.3V
402
M_QSB[7..0](5)
M_MDB27
B9
DQ15
M_MDB28
B1
DQ14
M_MDB24
D9
DQ13
M_MDB31
D1
DQ12
M_MDB29
D3
DQ11
M_MDB25
D7
DQ10
M_MDB30
C2
DQ9
M_MDB26
C8
DQ8
M_MDB19
F9
DQ7
M_MDB20
F1
DQ6
M_MDB16
H9
DQ5
H1
DQ4
M_MDB22
H3
DQ3
M_MDB17
H7
DQ2
M_MDB21
G2
DQ1
M_MDB18
G8
DQ0
A9
VDDQ1
C1
VDDQ2
C3
VDDQ3
C7
VDDQ4
C9
VDDQ5
E9
VDDQ6
G1
VDDQ7
G3
VDDQ8
G7
VDDQ9
G9
A1
VDD1
E1
VDD2
J9
VDD3
M9
VDD4
R1
VDD5
J1
VDDL
J7
VSSDL
A7
VSSQ1
B2
VSSQ2
B8
VSSQ3
D2
VSSQ4
D8
VSSQ5
E7
VSSQ6
F2
VSSQ7
F8
VSSQ8
H2
VSSQ9
H8
VSSQ10
A3
VSS1
E3
VSS2
J3
VSS3
N1
VSS4
P9
VSS5
C503
C502
1uF_6.3V
1uF_6.3V
C508
C507
1uF_6.3V
1uF_6.3V
402 402 402
M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7
M_MAB14
M_MAB15
M_MAB12
M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0
+MVDD
C510
1uF_6.3V
C512
1uF_6.3V
+MVDD
VREF_B0
+MVDD
B301
BLM15BD121SN1
Possible alternate 5150005600G Possible alternate 5150005600G Possible alternate 5150005600G Possible alternate 5150005600G
C511
100nF
C509
1uF_6.3V
CLKB#0(5)
CLKB0(5)
CKEB0(5)
CSB#0_0(5)
WEB#0(5)
RASB#0(5)
CASB#0(5)
M_DQMB#0
M_DQMB#1
ODTB0(5) ODTB0(5) ODTB0(5)
M_QSB0 M_QSB5
R313 10R
M_QSB1
R314 10R
R303
4.99K
C538
R304
100nF
4.99K
U302
L2
BA0
L3
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
K8
J8
K2
L8
K7
L7
F3
B3
K9
F7
E8
B7
A8
J2
A2
E2
L1
R3
R7
R8
HYB18T256161AFL-25
+MVDD +MVDD
DQ15
DQ14
BA1
DQ13
DQ12
A12
DQ11
A11
DQ10
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CK
VDDQ1
CK
VDDQ2
VDDQ3
CKE
VDDQ4
VDDQ5
VDDQ6
VDDQ7
CS
VDDQ8
VDDQ9
WEK3VDDQ10
RAS
VDD1
VDD2
CAS
VDD3
VDD4
LDM
VDD5
UDM
VDDL
VSSDL
ODT
LDQS
VSSQ1
LDQS
VSSQ2
VSSQ3
VSSQ4
VSSQ5
UDQS
VSSQ6
UDQS
VSSQ7
VSSQ8
VREF
VSSQ9
VSSQ10
NC#A2
VSS1
NC#E2
VSS2
NC#L1
VSS3
NC#R3
VSS4
NC#R7
VSS5
NC#R8
C526
C527
1uF_6.3V
1uF_6.3V
402 402402
C532
C531
1uF_6.3V
1uF_6.3V
M_MDB12
B9
M_MDB11
B1
M_MDB15
D9
M_MDB9 M_MDB56
D1
M_MDB8
D3
M_MDB14
D7
M_MDB10
C2
DQ9
M_MDB13 M_MDB60
C8
DQ8
F9
DQ7
M_MDB3
F1
DQ6
M_MDB7
H9
DQ5
M_MDB0M_MDB23
H1
DQ4
M_MDB1
H3
DQ3
M_MDB6
H7
DQ2
M_MDB2
G2
DQ1
M_MDB5
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
C528
1uF_6.3V
C533
1uF_6.3V
C534
1uF_6.3V
B302
BLM15BD121SN1
C537
C536
1uF_6.3V
100nF
C535
1uF_6.3V
+MVDD
+MVDD
VREF_B1
+MVDD
M_MAB14
M_MAB15
M_MAB12
M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0
CLKB#1(5)
CLKB1(5)
CKEB1(5)
CSB#1_0(5)
WEB#1(5)
RASB#1(5)
CASB#1(5)
M_DQMB#7 M_DQMB#4
R315 10R
M_QSB7
R316 10R
R305
4.99K
R306
C563
100nF
4.99K
U303
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HYB18T256161AFL-25
+MVDD
C551
1uF_6.3V
402
+MVDD
C556
1uF_6.3V
402 402
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
C552
1uF_6.3V
C557
1uF_6.3V
402402402402402 402 402402402402
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
C553
1uF_6.3V
C558
1uF_6.3V
M_MDB61
M_MDB59
M_MDB62
M_MDB57
M_MDB63
M_MDB58
M_MDB44
M_MDB43
M_MDB47
M_MDB40
M_MDB41
M_MDB46
M_MDB42
M_MDB45
C559
1uF_6.3V
402
B303
BLM15BD121SN1
C561
C562
100nF
1uF_6.3V
C560
1uF_6.3V
+MVDD
+MVDD
VREF_B1
+MVDD
R317 10R
R318 10R
R307
4.99K
R308
4.99K
C587
100nF
M_MAB14
M_MAB15
M_MAB12
M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0
CLKB#1(5)
CLKB1(5)
CKEB1(5)
CSB#1_0(5)
WEB#1(5)
RASB#1(5)
CASB#1(5)
M_DQMB#6M_DQMB#5
M_QSB6
M_QSB4
U304
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HYB18T256161AFL-25
+MVDD+MVDD
C576
1uF_6.3V
402 402402402
C580
1uF_6.3V
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
C577
1uF_6.3V
402
C581
1uF_6.3V
M_MDB35
B9
M_MDB36
B1
M_MDB32
D9
M_MDB39
D1
M_MDB38
D3
M_MDB34
D7
M_MDB37
C2
DQ9
M_MDB33
C8
DQ8
M_MDB51M_MDB4
F9
DQ7
M_MDB52
F1
DQ6
M_MDB50
H9
DQ5
M_MDB55
H1
DQ4
M_MDB54
H3
DQ3
M_MDB48
H7
DQ2
M_MDB53
G2
DQ1
M_MDB49
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
C578
1uF_6.3V
C582
1uF_6.3V
B304
BLM15BD121SN1
C585
C586
100nF
1uF_6.3V
C583
C584
1uF_6.3V
1uF_6.3V
402
+MVDD
+MVDD
CLKB0(5)
A A
8
7
6
CLKB#0(5)
CLKB1(5)
CLKB#1(5)
5
R321
56R
402
R322
56R
402 402
R323
56R
402
R324
56R
402 402
C599
10nF
C600
10nF
+MVDD +MVDD
R309
4.99K
VREF_B0 VREF_B1
R310
4.99K
4
R319
4.99K
R320
4.99K
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
3
Date: Sheet
2
105-A676xx-21
8
of
13 20Thursday, May 11, 2006
1
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8
D D
A_R_DAC1(3)
A_G_DAC1(3)
A_B_DAC1(3)
7
L1001 47nH
L1002 47nH
L1003 47nH
A_R_DAC1_M
A_G_DAC1_M
A_B_DAC1_M
6
L1004 47nH
L1005 47nH
L1006 47nH
5
A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F
DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
4
+3.3V +12V_BUS
3
2
+5V_VESA
1
DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)
R1001 75R
R1002 75R
R1003 75R
RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane
C C
B B
CRT1DDCDATA(1,3)
CRT1DDCCLK(1,3)
GENERICA(7)
A_HSYNC_DAC1(1,3,7)
A_VSYNC_DAC1(1,3,7)
GENERICB(7)
SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane
402
C1004
C1006
C1005
15pF
15pF
15pF
402 402 402
+3.3V
R1004
4.7K
402
+3.3V +5V
R1007
4.7K
402 402
C1999 100nF
+5V
14
2 3
1
7
4
5 6
1
1
U1999A
74AHCT125
74AHCT125
U1999B
32
BSH111
Q1001
32
BSH111
Q1002
+5V
R1005
2.2K
402
R1008
2.2K
402
A_HSYNC_DAC1_B
A_VSYNC_DAC1_B
C1002
C1003
C1001
10pF_50V
10pF_50V
10pF_50V
402402 402
DDCDATA_DAC1_5V DDCDATA_DAC1_R
DDCCLK_DAC1_5V
R1006 33R
R1009 33R
402
R1010
R1011
DDCCLK_DAC1_R
402
10R
402
10R
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
HPD1(3)
HPD2(7)
R1024 0R
These resistors can be
placed close to the ASIC so
single net is needed
Q1021
MMBT3904
+3.3V
2 3
R1023
10K
1
R1022 10K
603603 603 603
805805805
DB15 pin
TjX2M(3)
TjX2P(3)
TjX4M(3)
TjX4P(3)
TjX1M(3)
TjX1P(3)
TjX3M(3)
TjX3P(3)
TjX0M(3)
TjX0P(3)
TjX5M(3)
TjX5P(3)
TjXCP(3)
TjXCM(3)
DDCCLK_DAC1_R
DDCDATA_DAC1_R
A_VSYNC_DAC1_R
HPD_DVI
A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F
A_HSYNC_DAC1_R
Standard VGA
Monitor ID bit 0
11
Monitor ID bit 1
12
Monitor ID bit 2
4
Monitor ID bit 3
15
N/C
9
Mechanical Key
Hardware
Support
No Yes Yes No Yes
Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997
+5V_VESA
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C1
C2
C3
C4
C5
C6
26
27
28
29
30
DDC1 Host
Monitor ID bit 0
Data from display
Monitor ID bit 2
Open
+5V
50mA min
1A max
J1001
CASE
TMDS Data2-
TMDS Data2+
TMDS Data2/4 Shield
TMDS Data4TMDS Data4+
DDC Clock
DDC Data
Analog VSYNC
TMDS Data1TMDS Data1+
TMDS Data1/3 Shield
TMDS Data3TMDS Data3+
+5V Power
GND (for +5V)
Hot Plug Detect
TMDS Data0TMDS Data0+
TMDS Data0/5 Shield
TMDS Data5TMDS Data5+
TMDS Clock Shield
TMDS Clock+
TMDS Clock-
Analog Red
Analog Green
Analog Blue
Analog HYNC
Analog GND
Analog GND#C6
CASE#26
CASE#27
CASE#28
CASE#29
CASE#30
DVI_CONNECTOR
DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max
DDC2AB Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max
DDC1/2 Display
Optional
SDA
Optional
SCL
Optional
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
105-A676xx-30
9
of
14 20Thursday, May 11, 2006
1
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8
7
6
5
4
+3.3V +12V_BUS
3
2
1
+5V_VESA2
C2001
15pF
C2002
15pF
A_R_DAC2_M
A_G_DAC2_M
A_B_DAC2_M
C2003
15pF
402402 402
D D
C C
A_R_DAC2(3)
A_G_DAC2(3)
A_B_DAC2(3)
R2001 75R
R2002 75R
R2003 75R
402
RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane
CRT2DDCDATA(3)
CRT2DDCCLK(3)
A_HSYNC_DAC2(3,7)
A_VSYNC_DAC2(3,7)
C2005
C2004
10pF_50V
10pF_50V
+3.3V
R2004
4.7K
402
+3.3V +5V
R2007
4.7K
402 402
L2001 47nH
L2002 47nH
L2003 47nH
C2006
10pF_50V
402 402 402
+5V
9 8
10
13
12 11
1
1
U1999C
74AHCT125
74AHCT125
U1999D
32
BSH111
Q2001
32
BSH111
Q2002
R2005
2.2K
402
DDCDATA_DAC2_5V
R2008
2.2K
402
DDCCLK_DAC2_5V
A_HSYNC_DAC2_B
A_VSYNC_DAC2_B
R2006 33R
R2009 33R
R2010
R2011
L2004 47nH
L2005 47nH
L2006 47nH
402
DDCDATA_DAC2_R
DDCCLK_DAC2_R
402
A_HSYNC_DAC2_R
33R
402
A_VSYNC_DAC2_R
33R
A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F
DDCDATA_DAC2_R
DDCCLK_DAC2_R
A_HSYNC_DAC2_R
A_VSYNC_DAC2_R
603603 603 603
805805805
DB15 pin
Standard VGA
DDC1 Host
Monitor ID bit 0
11
12
4
15
9
Hardware
Support
Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997
Monitor ID bit 0
Monitor ID bit 1
Data from display
Monitor ID bit 2
Monitor ID bit 2
Monitor ID bit 3
Open
+5V
N/C
50mA min
Mechanical Key
1A max
No Yes Yes No Yes
J2001
1
R
2
G
3
B
11
MS0
DDC2_MONID0
12
MS1
DDC2_MONID1(SDA)
4
MS2
DDC2_MONID2
15
MS3
DDC2_MONID3(SCL)
9
NC
13
HS
14
VS
5
VSS
6
VSS#6
7
VSS#7
8
VSS#8
10
VSS#10
16
CASE
17
CASE#17
Connector_DB15_Female_VGA_Blue
DDC2B or
DDC2AB Host
DDC2B+ Host
Monitor ID bit 0
Monitor ID bit 0
SDA
SDA
Monitor ID bit 2
Monitor ID bit 2
SCL
SCL
+5V
+5V
50mA min
300mA min
1A max
1A max
DDC1/2 Display
Optional
SDA
Optional
SCL
Optional
SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane
B B
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
105-A676xx-30
9
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15 20Thursday, May 11, 2006
1
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8
7
6
5
4
3
2
1
+RTAVDD
Vout = 3.3V
Iout = 125mA MAX, 80mA RMS
+RTAVDD+12V_BUS
These capacitors are for clossing references
D D
603
1%
402
CompIn_R
LumaIn_R
C C
ChromaIn_R
B B
A A
1206
1206
1206
+RTAVDD
402
402
1%
402
402
402
As close as possible to
pin 56 of Rage Theater
RTXTALIN(3)
PERST#_buf(1,2)
+RTAVDD
402
402
402
GND_VIN
402
NS3201 NS_VIA
402
402
VADCFILTERVADCFILTER
402
VADCFILTER
VADCFILTER
12
402
5%
+VDDC
Component (Y)
Component (Pr)
Component (Pb)
+3.3V_BUS
402 402 402 402 402402 402 402
DAC2_Y_DIN
DAC2_C_DIN
DAC2_COMP_DIN
CompIn_R
LumaIn_R
ChromaIn_R
CompIn
LumaIn
ChromaIn
PIN6
Overlap with Rpin5
5%
5%
402
1%
5%
Please close to RT
5%
Place near connector
0R leaves footprint for Ferrite
Beads if req'd for EMI
Component (Y)
Component (Pr)
Component (Pb)
402
1%
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7
+3.3V_BUS
DAC2_C_F
DAC2_COMP_F
402402
1%5%
VIPCLK (7)
VPHCTL (7)
VHAD_0 (7)
VHAD_1 (7)
RTCLK (3)
VID_[7..0] (7)
VPCLK0 (7)
Install for Dell
R3011 0R
402
STV/HDTV#_OUT_DET(7)
R3004 0R
R3005 0R
DNI for Dell
402
402
402
Component (Y)
Component (Pr)
Component (Pb)
DAC2_COMP(3)RTXTALOUT(3)
+3.3V
R3008
10K
DAC2_Y_DINDAC2_Y_F
DAC2_C_DIN
DAC2_COMP_DIN
DAC2_Y(3)
DAC2_C(3)
Install for Dell
R3010 0R
R3001
75R
R3002
75R
R3003
75R
L3001 470nH_250mA
C3001
47pF_50V
L3002 470nH_250mA
C3002
47pF_50V
L3003 470nH_250mA
C3003
47pF_50V
DAC2_Y_F
C3004
47pF_50V
DAC2_C_F
C3005
47pF_50V
DAC2_COMP_F
C3006
47pF_50V
Install for Dell only when it's needed for EMI
DNI for Dell
402
402
402402 402
DNI for Dell
DNI for Dell
The 7-pin MiniDIN footprint allows one of the two MiniDINs:
- 7-pin Svideo/Composite MiniDIN P/N 6071001500G
- 4-pin Svideo MiniDIN P/N 6070001000G
TV Out
J3001
PIN6
6
HDTV_OUT_DET#
3
Y-OUT
4
C-OUT
7
Comp_out
CompIn
5
SYNC
1
GND
2
GND#2
8
Rpin5
CASE
9
CASE#9
10
CASE#10
Conn_DIN_Mini_Circular_7_Pin_with_O_Ring
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
8
7
6
5
4
3
Date: Sheet
2
105-A676xx-21
8
of
16 20Thursday, May 11, 2006
1
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8
7
6
5
4
3
2
1
+3.3V
CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK
D D
CRT3DDCCLK(1,3)
CRT3DDCDATA(3)
PWM
H1
C C
HEATSINK
COOLING SOLUTION GENERIC KEEP-OUT
COOLING SOLUTION GENERIC KEEP-OUT
+12V_BUS
402
402
INTERFACE INFO: SMBUS SLAVE
Clock: Min 10kHz - Max 100kHz
7 bit address: 100 1100
SCL_R
SDA_R
Tach
402
NPO
Rx can overlap QxQxRx
402
NPO
+3.3V
402 402
DNI
402 402
6.3V
50V
X5R
NPO
PWM
402
402
GPU_DPLUS
402
GPU_DMINUS
50V
X7R
402
DNI
GPU_DPLUS (3)
GPU_DMINUS (3)ThermINT(7)
+12V_BUS
805
16V
Y5V
Tach
402
SCL_R
PWM
B B
A A
402
8
1%
402
1%
7
402
805
16V
Y5V
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
6
5
4
3
Date: Sheet
2
105-A676xx-21
8
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5
DVI/VGA SCREWS
ASSY-SCREW1
SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
ASSY
ASSY-SCREW3
SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
D D
ASSY
C C
ASSY-SCREW2
SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
ASSY
ASSY-SCREW4
SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
ASSY
ASSY-SCREW5
SCREW
SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L
4
MT1
MT_Hole_0.136_in.
DNI DNI
DNI
PCB1
109-A67631-30
MT2
MT_Hole_0.136_in_6VIA
3
2
1
B B
A A
<Variant Name>
5
4
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
Date: Sheet
105-A676xx-21
1
of
18 20Thursday, May 11, 2006
8
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5
<Variant Name>
Title
4
3
2
1
Date:Schematic No.
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
REVISION HISTORY
NOTE:
D D
Sch
Rev
C C
B B
PCB
Rev
0
00A
1 00B
2 00C
300
410
511
612
720
821
Date
05/05/01
05/07/14
05/07/29 (Layout) Critical layout change
05/08/24 (Layout) Move +PW_VDDC_HGDR trace on layer 3 slightly to avoid long overlap with VDDC_FB
05/09/09
05/11/29
06/01/04 (Layout) Minor change only.
06/02/20 (Layout) Increasing test point coverage
06/02/22 (pg 3) Removing MR139, MR140, MR141, MR142, MR143, MR144, MR145, MR146, MR147, MR148, MR149, MR150, MR151, MR152
New design from scratch
(Layout) Critical layout change
(L1) Reduce +PW_MVDDC_M planes and replace it with GND
(L1) Correct silkscreen "SMPS A601-00A TILE"
(L3) Replace +PW_VDDC_M, +VDDC_S and +MVDDC_S planes with GND
(pg 01) Correct clock circuitry to support RT
(pg 08) Swap R603 and R604 to match layout for documentation purposes
(pg 09) Swap R703 and R704 to match layout for documentation purposes
(pg 10) Add MVDD linear regulator option
(pg 11) Add R986, R987, R988; replace redundant power sequence circuit with +5V_EN and MVDD_EN
(pg 11) Add MR911, R918 for +MPVDD for no-tracking option
(pg 16) Change C3103 to 603 footprint, change RT to power from 3.3V_BUS to avoid leakage, remove redundant RT clock resistors
Add 2 to 3 more power vias for MOSFET source pin of VDDC
(L3) Remove ground planes under the PWM IC
Remove +MVDDC/+MVDDQ reference, use only +MVDD
(pg 09) Add dynamic VDDC circuit for socket screening purposes
(pg 11) Add MR961 for higher than 2.5V I/O voltage support
(pg 14) Adding circuitry required for CrossFire ready
Moved VGA connector 1mm in to align with bracket
(Layout) Minor changes only.
1. A square pad fiducial has been added on the top side.
2. Mark for pin #1 for U3201 has been added
3. Lines have been added to define a minus polarity of the electrolytic caps
Adding Microvision Certification Logo for TVO on the Silkscreen
(pg 07) Updating the text description of PIN Straps DVALID & PSYNC to match MTAG definition for DDR2 memory.
(pg 07) Adding HDCP support (R36 and MR36)
(pg 11) Adding C979 for power up sequencing
(pg 14) Removing GPIO_9 connection to U1999 to eliminate conflict with HDCP, hardware CF support is no longer needed.
(pg 16) Adding R3011, R3010, and C3010 to address new DIN connector pin assignment required by DELL
(pg 17) Adding MQ4004 multi-footprint - Cost reduction
(pg 17) Adding MR4027, MR4005, R4027, and Q4021 to provide option of running the fan at fixed voltage but lower than 12V
, and disconnecting TMDS2 lines
This schematic represents the PCB, it does not represent any specific SKU.
For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.
Please contact ATI representative to obtain latest BOM closest to the application desired.
REVISION DESCRIPTION
105-A676xx-21
Thursday, May 11, 2006
Rev
8
A A
5
4
3
2
1
www.vinafix.vn
5
4
3
2
1
MEMORY CHANNEL A
D D
POWER
REGULATION
From +12V
VDDC, MVDD
From +12V LINEAR:
+5V, +5V_VESA,
C C
+5V_VESA2, RageTheater
From +12V DIRECT:
FAN
From +3.3V LINEAR:
VDDC_CT, MPVDD, PVDD,
TPVDD, T2PVDD, TXVDDR,
T2XVDDR, AVDD, A2VDD,
VDD1DI, VDD2DI,
PCIE, VDDR3, VDDR4,
VDDR5, VDDRH
MVDD
DDR2 16M/32Mx16
FAN
Straps
BIOS
(HDCP)
Speed control
& temperature
sense
INTERRUPT
Temp. Sensing
MEM A MEM B
DAC2
GPIO
H/V2Sync
DDC2
ROM
DDC3
GPIO17
XTALIN/OUT
D+/D-
RV5XX
DAC1
CRT
Composite, SVideo and Component TVO
TVO
XTAL
MPP
VIP
CRT
H/VSync
DDC1
POWER DELIVERY
+PCIE_SOURCE
B B
+3.3V
3.3V_BUS
delayed circuit
+12V_BUS
Dual-Link TMDS
Dual-Link LVTM
PCI-Express
HPD1
GPIO14
MEMORY CHANNEL B
DDR2 16M/32Mx16
Oscillator
TMDS matching
RBG Filters
TVO Filters
XTALIN/OUT
CLKOUT
RageTheater
RBG Filters
TVO/VIVO
HPD
VGA
CONN
CONN
DVI-I
&
Slim-VGA
CONN
SMPS Enable
Circuit
+3.3V_BUS
+12V_BUS
A A
5
PCI-Express Bus
4
RV5XX DDR2 FH 4-Layer
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
RV5xx 512MB DDR2 VGA 2xDVI VIVO FH
Size Document Number Rev
C
3
2
Date: Sheet
105-A676xx-21
1
8
of
20 20Thursday, May 11, 2006
www.vinafix.vn
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