1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
ASSEMBLYNVPNVARIANT
B
1
2
SKU
3
4
5
6
12
13
14
7
8
9
10
11
15
P455-A01 DT SKU2
P455-A01, G71-A02, 256MB 8Mx32 GDDR3 (700Mhz),
DVI-I-DL, DVI-I-DL, HDTV-Out for Dell HMGA
Table of Contents:
Page 1: Overview
Page 2: PCI Express 1.0
Page 3: MEMORY: GPU Partition A/B
Page 4: MEMORY: GPU Partition C/D
Page 5: FBA Partition
Page 6: FBB Partition
Page 7: FBC Partition
Page 8: FBD Partition
Page 9: FrameBuffer Net Properties
Page 10: DACA Interface
Page 11: DACC Interface
Page 12: IFP A/B and C/D Interface
Page 13: DACB and Stereo Interface
Page 14: Video Capture (Philips SAA7115)
Page 15: Multi-use IO(MIO) Interface
Page 16: GPIO, I2C, ROM, HDMI, and XTAL
Page 17: Strapping Configuration
Page 18: Power/GND and Decoupling
Page 19: Power Supply I: A2V5, DDC5V, SAA7115, TMDS Supplies
Page 20: Power Supply II: PEX Input Filters, External 12V Power, NVVDD VID Control
Page 21: Power Supply III: FBVDDQ and PEX1V2
Page 22: Power Supply IV: NVVDD
Page 23: Thermal Diode, Fan Control
Page 24: Mechanical: Bracket/Thermal Solution
REVISION HISTORY:
X1
RevA: Initial Release
BASE
SKU0000
SKU0002
SKU0500
SKU0501
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Overview
www.vinafix.vn
<UNDEFINED>
600-10455-base-001
600-10455-0000-001
600-10455-0002-001
600-50455-0500-001
600-50455-0501-001
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
P455 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
G71-GT - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
G71GL-U - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + STEREO, 450/700 MHz
G71GL-Std - 256MB 8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 375/600 MHz
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
600-10455-0002-001
design
LFarasati
1 OF 24
9-FEB-2006
J501
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
23/24 JTAG
JTAG_TRST
JTAG_TDO
JTAG_TMS
JTAG_TCLK
JTAG_TDI
KEY
TRST*
GND
TCK
TMS
TDI
VCC
TDO
1/24 PCI EXPRESS
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_PLLAVDD
RFU
RFU
PEX_PLLDGND
PEX_PLLDVDD
PEX_PLLAGND
PEX_TEST_PLL_CLK_OUT
PEX_TEST_PLL_CLK_OUT
PEX_TX0
PEX_RST
PEX_REFCLK
PEX_REFCLK
PEX_TX0
PEX_TX2
PEX_RX2
PEX_TX3
PEX_RX1
PEX_RX0
PEX_TX1
PEX_RX1
PEX_TX2
PEX_RX2
PEX_RX0
PEX_TX1
PEX_RX3
PEX_RX3
PEX_TX3
PEX_TX7
PEX_RX6
PEX_TX4
PEX_RX6
PEX_TX6
PEX_RX5
PEX_TX5
PEX_TX5
PEX_RX4
PEX_RX5
PEX_TX6
PEX_RX4
PEX_TX4
PEX_TX7
PEX_RX7
PEX_TX9
PEX_TX10
PEX_RX8
PEX_TX9
PEX_RX9
PEX_TX8
PEX_RX10
PEX_RX8
PEX_RX9
PEX_TX10
PEX_TX8
PEX_RX7
PEX_TX11
PEX_RX13
PEX_RX13
PEX_RX11
PEX_TX12
PEX_RX10
PEX_TX11
PEX_RX11
PEX_TX12
PEX_RX12
PEX_RX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_RX15
PEX_TX14
PEX_RX14
PEX_RX14
PEX_RX15
PEX_TX15
PEX_TX15
END OF X8
END OF X16
END OF X1
END OF X4
TCLK JTAG2
TMS JTAG5
TDO JTAG4
TDI JTAG3
WAKE
SMDAT
SMCLK
PERN0
PERP0
REFCLK
PERST
REFCLK
PETN1
PERP2
PETN0
PERP1
PERN1
PETP0
PETP1
PERN3
PETP3
PETN3
PETP2
PERP3
PETN2
PERN2
PERP4
PERN4
PETN4
PERP5
PETP4
PERN5
PETP5
PETP6
PERN6
PERP6
PETN5
PERP7
PETN6
PERN7
PETN8
PETP8
PERP8
PETN7
PETP7
PERN8
PERN9
PERP9
PERP10
PERN10
PETP10
PETP9
PETN9
PETN10
PETN11
PERP12
PERN12
PERP11
PERN11
PETP11
PETN12
PETP12
PETN13
PERP13
PERN13
PETP13
PERP14
PERN15
PETP15
PETN15
PERN14
PETN14
PETP14
PERP15
TRST* JTAG1+12V
+12V/RSVD
+3V3AUX
+12V
+12V
+12V
+3V3
+3V3
+3V3
PRSNT2
PRSNT1
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
GND
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
HDR_2F4
FEMALE
PEX_TRST*
B9
PEX_TCLK
A5
PEX_TDI
A6
PEX_TDO
A7
PEX_TMS
A8
B5
B6
B11
A11
A13
A14
A16
A17
B14
B15
A21
A22
B19
B20
A25
A26
B23
B24
A29
A30
B27
B28
A35
A36
B33
B34
A39
A40
B37
B38
A43
A44
B41
B42
A47
A48
B45
B46
A52
A53
B50
B51
A56
A57
B54
B55
A60
A61
B58
B59
A64
A65
B62
B63
A68
A69
B66
B67
A72
A73
B70
B71
A76
A77
B74
B75
A80
A81
B78
B79
SNN_PEX_SMCLK
SNN_PEX_SMDAT
SNN_PEX_WAKE*
PEX_RST*
PEX_REFCLK
PEX_REFCLK*
PEX_TXX0
PEX_TXX0*
PEX_RX0
PEX_RX0*
PEX_TXX1
PEX_TXX1*
PEX_RX1
PEX_RX1*
PEX_TXX2
PEX_TXX2*
PEX_RX2
PEX_RX2*
PEX_TXX3
PEX_TXX3*
PEX_RX3
PEX_RX3*
PEX_TXX4
PEX_TXX4*
PEX_RX4
PEX_RX4*
PEX_TXX5
PEX_TXX5*
PEX_RX5
PEX_RX5*
PEX_TXX6
PEX_TXX6*
PEX_RX6
PEX_RX6*
PEX_TXX7
PEX_TXX7*
PEX_RX7
PEX_RX7*
PEX_TXX8
PEX_TXX8*
PEX_RX8
PEX_RX8*
PEX_TXX9
PEX_TXX9*
PEX_RX9
PEX_RX9*
PEX_TXX10
PEX_TXX10*
PEX_RX10
PEX_RX10*
PEX_TXX11
PEX_TXX11*
PEX_RX11
PEX_RX11*
PEX_TXX12
PEX_TXX12*
PEX_RX12
PEX_RX12*
PEX_TXX13
PEX_TXX13*
PEX_RX13
PEX_RX13*
PEX_TXX14
PEX_TXX14*
PEX_RX14
PEX_RX14*
PEX_TXX15
PEX_TXX15*
PEX_RX15
PEX_RX15*
R692
0
5%
0402
COMMON
C838
0402
COMMON
X5R
C828
0402 10V .1UFC817
COMMON
X5R
C800
0402
COMMON
X5R
C773
0402
COMMON
X5R
C747
0402
COMMON
X5R
C716
0402
COMMON
X5R
C701
0402
COMMON
X5R
C673
0402
COMMON
X5R
0402
COMMON
X5R
C645
0402
COMMON
X5R
C637
0402
COMMON
X5R
C631
0402
COMMON
X5R X5R
C626
0402
COMMON
X5R
C621
0402
COMMON
X5R
C615
0402
COMMON
X5R
C611
0402
COMMON
X5R
.1UF
10V
10%
.1UF
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UFC657
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
C835
0402
0402
C794
0402
C766
0402
C743
0402
C713
0402
C696
0402
0402
C652
0402
C642
0402
C635
0402
C629
0402
0402
0402
C614
0402
C608
0402
.1UF
10V
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UFC667
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UFC625
10V
.1UFC620
10V
.1UF
10V
.1UF
10V
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
10%
X5R
10%
X5R
10%
X5R
10%
X5R
R670
0402
5%
0402
5%
R691
0402
5%
R693
0402
5%
R688
0402
5%
PEX_TX0
PEX_TX0*
COMMON
PEX_TX1
PEX_TX1* AN11
COMMON
PEX_TX2
PEX_TX2*
COMMON
PEX_TX3
PEX_TX3*
COMMON
PEX_TX4
PEX_TX4*
COMMON
PEX_TX5
PEX_TX5*
COMMON
PEX_TX6
PEX_TX6*
COMMON
PEX_TX7
PEX_TX7*
COMMON
PEX_TX8 AM16
PEX_TX8*
COMMON
PEX_TX9
PEX_TX9*
COMMON
PEX_TX10
PEX_TX10*
COMMON
PEX_TX11
PEX_TX11*
COMMON
PEX_TX12
PEX_TX12*
COMMON
PEX_TX13
PEX_TX13*
COMMON
PEX_TX14
PEX_TX14*
COMMON
PEX_TX15
PEX_TX15*
COMMON
0
NO STUFF
0R674
NO STUFF
0
NO STUFF
0
NO STUFF
0
NO STUFF
AR9
AK10
AL10
AM11
AM10
AP9
AP10
AN10
AR10
AR11
AN12
AM12
AT11
AT12
AL12
AK12
AP12
AP13
AM14
AM13
AR13
AR14
AN13
AN14
AT14
AT15
AN15
AM15
AP15
AP16
AL15
AK15
AR16
AR17
AN16
AT17
AT18
AN17
AN18
AP18
AP19
AM18
AM17
AR19
AR20
AL18
AK18
AT20
AT21
AM19
AN19
AP21
AP22
AN20
AN21
AR22
AR23
AM21
AM20
AT23
AT24
AL21
AK21
AR24
AR25
JTAG_TRST*
JTAG_TCLK
JTAG_TDI
JTAG_TDO
JTAG_TMS
U8
G71-N-A2
BGA1148
CHANGED
www.vinafix.vn
C860
4.7UF
16V
20%
X7R
1206
COMMON
C856
4.7UF
6.3V
10%
X5R
0603
COMMON
C892
4.7UF
16V
20%
X7R
1206
COMMON
C857
.1UF
16V
10%
X7R
0402
COMMON
SNN_PE_PRSNT2_A
SNN_PE_RSVD2
PRSNT*
C868
.1UF
16V
10%
X7R
0402
COMMON
SNN_3V3AUX
CN2
CON_X16
COMMON
CON_PCIEXP_X16_EDGE
B1
B2
A2
A3
B3
B8
A9
A10
B10
A1
B17
B12
B4
A4
B7
A12
B13
A15
B16
B18
A18
Page2: PCI Express 1.0
12V
GND
3V3
GND
SNN_PE_PRSNT2_B
SNN_PE_RSVD3
SNN_PE_RSVD4
SNN_PE_RSVD5
SNN_PE_PRSNT2_C
SNN_PE_RSVD6
PRSNT*
SNN_PE_RSVD7
SNN_PE_RSVD8
GND
B31
A19
B30
A32
A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32
B48
GND
A33
A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49
GND
B81
A50
B82
A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82
GND
3V3
1
3
5
7
1.274MM
0
KEY6_JTAG_SMALL
NO STUFF
2
4
8
Place near balls
AH21
AJ21
AH22
AJ22
AH23
AJ23
AH16
AF17
AH17
AF18
AH18
AF19
AH19
AE20
AF20
AH20
AJ20
Matching Rule of Thumb
4 inch from Top of Gold Fingers to GPU
*2 inch Lane to Lane Skew
*No real Skew rule, but reducing the skew will minimize latency
PEX_PLL_CLK_OUT
AM9
PEX_PLL_CLK_OUT*
AN9
SNN_GPU_AK19
AK19
SNN_GPU_AK20
AK20
AE15
AF15
AE17
AE16
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
PCI Express 1.0
3V3
R672
R689
R690
10K
5%
0402
COMMON
GND
C739
.01UF
16V
10%
X5R
0402
COMMON
C693
.1UF
10V
10%
X5R
0402
COMMON
C729
.1UF.1UF
10V
10%
X5R
0402
COMMON
C742
.1UF
16V
10%
X5R
0603
COMMON
C702
.1UF
10V
10%
X5R
0402
COMMON
C714
10V
10%
X5R
0402
COMMON
PEX_TEST_PLL_CLK_OUT Termination = 200ohm
AVDD & DVDD route separate first from the balls
then join at the first cap
PEX_PLLVDD
10K
5%
0402
COMMON
R671
10K
5%
0402
COMMON
R628
200
5%
0402
COMMON
C695
1UF
10V
10%
X5R
0603
COMMON
C715
1UF
10V
10%
X5R
0603
COMMON
C89
1UF
10V
10%
X5R
0603
COMMON
GND
180
5%
0402
COMMON
JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
R673
270
5%
0402
COMMON
C92
4.7UF
6.3V
10%
X5R
0603
COMMON
C680
1UF
10V
10%
X5R
0603
C704
1UF 4.7UF
10V
10%
X5R
0603
GND
LB23
JTAG
U8
G71-N-A2
BGA1148
CHANGED
AK6
AL8
AL7
AK7
AL9
220R@100MHz
COMMONBEAD_0603
C681
4.7UF
6.3V
10%
X5R
0603
COMMONCOMMON
C678
6.3V
10%
X5R
0603
COMMONCOMMON
PEX NET RULES
NET NV_CRITICAL
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
50OHM
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT
C689
10UF
6.3V
20%
X5R
0805
COMMON
C91
10UF
6.3V
20%
X5R
0805
COMMON
PEX_REFCLK 1
PEX_REFCLK*
PEX_TXX0
PEX_TXX0*
PEX_TXX1
PEX_TXX1*
PEX_TXX2
PEX_TXX2*
PEX_TXX3
PEX_TXX3*
PEX_TXX4
PEX_TXX4*
PEX_TXX5
PEX_TXX5*
PEX_TXX6
PEX_TXX6*
PEX_TXX7
PEX_TXX7*
PEX_TXX8
PEX_TXX8*
PEX_VDD
PEX_VDD
GND
GND
PEX_TXX9
PEX_TXX9*
PEX_TXX10
PEX_TXX10*
PEX_TXX11
PEX_TXX11*
PEX_TXX12
PEX_TXX12*
PEX_TXX13
PEX_TXX13*
PEX_TXX14
PEX_TXX14*
PEX_TXX15
PEX_TXX15*
PEX_RX0
PEX_RX0*
PEX_RX1
PEX_RX2
PEX_RX2*
PEX_RX3
PEX_RX3*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_RX14
PEX_RX14*
PEX_RX15
PEX_RX15*
PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
PEX_PLL_CLK_OUT*
PEX_RST*
PRSNT*
PEX_TRST*
PEX_TCLK
PEX_TDI
PEX_TDO
PEX_TMS
JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1PEX_RX1*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1PEX_TX5*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1PEX_PLL_CLK_OUT
1
1
PEX_VDD
NV_SOURCE_POWER_NET
12V
C90
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
3V3
GND
12V
3V3
GND
PEX_PLLVDD
NV_SOURCE_POWER_NET
12V
3.3VNV_SOURCE_POWER_NET
0V
1.2V
5.5A
3.0A
8.5A
0.16A
600-10455-0002-001
design
LFarasati
DIFFPAIRNV_IMPEDANCE
PEX_REFCLK
PEX_REFCLK
PEX_TXX0
PEX_TXX0
PEX_TXX1
PEX_TXX1
PEX_TXX2
PEX_TXX2
PEX_TXX3
PEX_TXX3
PEX_TXX4
PEX_TXX4
PEX_TXX5
PEX_TXX5
PEX_TXX6
PEX_TXX6
PEX_TXX7
PEX_TXX7
PEX_TXX8
PEX_TXX8
PEX_TXX9
PEX_TXX9
PEX_TXX10
PEX_TXX10
PEX_TXX11
PEX_TXX11
PEX_TXX12
PEX_TXX12
PEX_TXX13
PEX_TXX13
PEX_TXX14
PEX_TXX14
PEX_TXX15
PEX_TXX15
PEX_RX0
PEX_RX0
PEX_RX1
PEX_RX1
PEX_RX2
PEX_RX2
PEX_RX3
PEX_RX3
PEX_RX4
PEX_RX4
PEX_RX5
PEX_RX5
PEX_RX6
PEX_RX6
PEX_RX7
PEX_RX7
PEX_RX8
PEX_RX8
PEX_RX9
PEX_RX9
PEX_RX10
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_RX12
PEX_RX13
PEX_RX13
PEX_RX14
PEX_RX14
PEX_RX15
PEX_RX15
PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15
MIN_WIDTHVOLTAGE MAX_CURRENTNET
24MIL
20MIL
16MIL
12MIL
2 OF 24
9-FEB-2006
Page3: MEMORY: GPU Partition A/B
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBI
3/24 MEM_B
FBB_CMD6
FBB_CMD4
FBB_CMD5
FBB_CMD3
FBB_CMD1
FBB_CMD2
FBB_CMD0
FBB_CMD7
FBB_CMD26
FBB_CMD24
FBB_CMD25
FBB_CMD23
FBB_CMD21
FBB_CMD22
FBB_CMD19
FBB_CMD20
FBB_CMD18
FBB_CMD17
FBB_CMD16
FBB_CMD14
FBB_CMD15
FBB_CMD13
FBB_CMD12
FBB_CMD11
FBB_CMD9
FBB_CMD10
FBB_CMD8
FBB_CLK1
FBB_CLK0
FBB_CLK0
FBB_CLK1
RFU
RFU
FBB_DEBUG
FBB_REFCLK
FBCAL1_PD_VDDQ
FBB_REFCLK
FBCAL1_TERM_GND
FBCAL1_PU_GND
FBB_PLLAVDD
FBB_PLLVDD
FBB_PLLGND
FBBD6
FBBD4
FBBD5
FBBD3
FBBD2
FBBD1
FBBD0
FBBD7
FBBD27
FBBD26
FBBD25
FBBD24
FBBD23
FBBD22
FBBD21
FBBD19
FBBD20
FBBD17
FBBD16
FBBD15
FBBD13
FBBD12
FBBD11
FBBD9
FBBD10
FBBD8
FBBD14
FBBD18
FBBD47
FBBD46
FBBD45
FBBD44
FBBD42
FBBD43
FBBD41
FBBD40
FBBD39
FBBD37
FBBD38
FBBD36
FBBD35
FBBD34
FBBD32
FBBD33
FBBD31
FBBD30
FBBD29
FBBD28
FBBD48
FBBDQM2
FBBDQM1
FBBDQM0
FBBD62
FBBD63
FBBD60
FBBD61
FBBD59
FBBD57
FBBD58
FBBD55
FBBD56
FBBD54
FBBD53
FBBD52
FBBD50
FBBD51
FBBD49
FBBDQS_WP2
FBBDQS_WP1
FBBDQS_WP0
FBBDQS_RN7
FBBDQS_RN4
FBBDQS_RN5
FBBDQS_RN6
FBBDQS_RN3
FBBDQS_RN2
FBBDQS_RN1
FBBDQS_RN0
FBBDQM7
FBBDQM6
FBBDQM4
FBBDQM5
FBBDQM3
FBBDQS_WP3
FB_VREF2
FBBDQS_WP7
FBBDQS_WP6
FBBDQS_WP5
FBBDQS_WP4
BI
OUT
OUT
OUT
OUT
OUT
OUTINOUTBIBIBIBIBIBI
BI
2/24 MEM_A
FBA_CMD0
FBA_CMD2
FBA_CMD1
FBA_CMD3
FBA_CMD5
FBA_CMD4
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD10
FBA_CMD9
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD15
FBA_CMD14
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD20
FBA_CMD19
FBA_CMD22
FBA_CMD21
FBA_CMD23
FBA_CMD25
FBA_CMD24
FBA_CMD26
FBA_CLK1
FBA_CLK1
FBA_CLK0
FBA_CLK0
RFU
RFU
FBA_DEBUG
FBA_REFCLK
FBA_PLLAVDD
FBA_REFCLK
FBA_PLLVDD
FBCAL0_TERM_GND
FBCAL0_PU_GND
FBCAL0_PD_VDDQ
FBA_PLLGND
FBAD0
FBAD1
FBAD2
FBAD3
FBAD5
FBAD4
FBAD6
FBAD7
FBAD8
FBAD10
FBAD9
FBAD11
FBAD13
FBAD12
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD20
FBAD19
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD40
FBAD46
FBAD47
FBAD28
FBAD29
FBAD30
FBAD31
FBAD33
FBAD32
FBAD34
FBAD35
FBAD36
FBAD38
FBAD37
FBAD39
FBAD41
FBAD43
FBAD42
FBAD44
FBAD45
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD56
FBAD55
FBAD57
FBAD58
FBAD61
FBAD63
FBAD62
FBADQM0
FBADQM1
FBADQM2
FBAD60
FBAD59
FBADQM3
FBADQM5
FBADQM4
FBADQM6
FBADQM7
FBADQS_RN1
FBADQS_RN0
FBADQS_RN2
FBADQS_RN3
FBADQS_RN6
FBADQS_RN5
FBADQS_RN4
FBADQS_RN7
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP6
FBADQS_WP5
FBADQS_WP7
FB_VREF1
OUTINOUT
BI
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
U8
G71-N-A2
BGA1148
AH35
AH36
AH34
AJ34
AK36
AJ36
AK34
AL34
AH32
AK33
AJ33
AH33
AL33
AN32
AN33
AN31
AE32
AF30
AF32
AE30
AE31
AC30
AC32
AD30
AG36
AG34
AF36
AD36
AD34
AD35
AE34
AP36
AN35
AM34
AP35
AP34
AP33
AT34
AR34
AM22
AM25
AN26
AN24
AK24
AL22
AK23
AM23
AT32
AT33
AR33
AP31
AR30
AT30
AP30
AT29
AP26
AP27
AT25
AP25
AR28
AP28
AT28
AP29
AK35
AF33
AF34
AN34
AM24
AP32
AR27
AL35
AK32
AG33
AE36
AM36
AN22
AR31
AT27
AL36
AL32
AG32
AE35
AN36
AN23
AT31
AT26
J29FB_VREF1
CHANGED
CALIBRATION PIN
FB_CALx_PD_VDDQ
FB_CALx_PU_GND
FB_CALx_TERM_GND
VREF RATIO
DDR3
60
40
40
0.7 FBVDDQ
FBA_CMD<0>
AK28
FBA_CMD<1>
AK29
FBA_CMD<2>
AN30
FBA_CMD<3>
AM27
FBA_CMD<4>
AN28
FBA_CMD<5>
AL29
AM30
FBA_CMD<6>
FBA_CMD<7>
AJ31
FBA_CMD<8>
AK31
FBA_CMD<9>
AH31
FBA_CMD<10>AK25
FBA_CMD<11>
AM26
FBA_CMD<12>
AL31
FBA_CMD<13>
AN29
SNN_FBA_CMD14
AK27
FBA_CMD<15>
AK26
FBA_CMD<16>
AN27
FBA_CMD<17>
AL25
FBA_CMD<18>
AJ30
FBA_CMD<19>
AM31
FBA_CMD<20>
AH30
FBA_CMD<21>
AL30
FBA_CMD<22>
AH29
FBA_CMD<23>
AL28
FBA_CMD<24>
AH28
FBA_CMD<25>
AM28
SNN_FBA_CMD_26AG30
FBA_CLK0
AH26
FBA_CLK0*
AH27
FBA_CLK1
AJ29
FBA_CLK1*
AJ28
SNN_GPU_AJ24
AJ24
SNN_GPU_AH24AH24
FBA_DEBUG
AH25
SNN_FBA_REFCLK
AF28
SNN_FBA_REFCLK*
AG28
FBCAL0_PD_VDDQ
J28
FBCAL0_PU_GND
H28
FBCAL0_TERM_GND
H29
AF29 IS NC FOR G71
FBAB_PLLVDD
AF29
FBAB_PLLAVDD
AD29
AE29
GND
GND
C634
.1UF
10V
10%
X5R
0402
NO STUFF
GND
FBAD<63..0>
FBADQM<7..0>
FBADQS_RN<7..0>
FBADQS_WP<7..0>
FBVDDQ
R598
511
1%
0402
NO STUFF
R597
1.18K
1%
0402
NO STUFF
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBAD<0>
FBAD<1>
FBAD<2>
FBAD<3>
FBAD<4>
FBAD<5>
FBAD<6>
FBAD<7>
FBAD<8>
FBAD<9>
FBAD<10>
FBAD<11>
FBAD<12>
FBAD<13>
FBAD<14>
FBAD<15>
FBAD<16>
FBAD<17>
FBAD<18>
FBAD<19>
FBAD<20>
FBAD<21>
FBAD<22>
FBAD<23>
FBAD<24>
FBAD<25>
FBAD<26> AG35
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30>
FBAD<31>
FBAD<32>
FBAD<33>
FBAD<34>
FBAD<35>
FBAD<36>
FBAD<37>
FBAD<38>
FBAD<39>
FBAD<40>
FBAD<41>
FBAD<42>
FBAD<43>
FBAD<44>
FBAD<45>
FBAD<46>
FBAD<47>
FBAD<48>
FBAD<49>
FBAD<50>
FBAD<51>
FBAD<52>
FBAD<53>
FBAD<54>
FBAD<55>
FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<60>
FBAD<61>
FBAD<62>
FBAD<63>
FBADQM<0>
FBADQM<1> AM33
FBADQM<2>
FBADQM<3>
FBADQM<4>
FBADQM<5>
FBADQM<6>
FBADQM<7>
FBADQS_RN<0>
FBADQS_RN<1>
FBADQS_RN<2>
FBADQS_RN<3>
FBADQS_RN<4>
FBADQS_RN<5>
FBADQS_RN<6>
FBADQS_RN<7>
FBADQS_WP<0>
FBADQS_WP<1>
FBADQS_WP<2>
FBADQS_WP<3>
FBADQS_WP<4>
FBADQS_WP<5>
FBADQS_WP<6>
FBADQS_WP<7>
PIN IS NC IN G71
9<> 5<>
9> 5<>
9< 5<>
5<>
9>
NO STUFF FOR G71
9<>
DDR3: VREF = 0.7 * FBVDDQ, FBVDDQ = 1.8V
1.26V = 1.8V * 1.18K / (511 + 1.18K)
FBA_CMD<26..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
9>
5<
9>
5<
9>
5<
9>
5<
9<>
TP7
NO STUFF
9<> 3<>
NO STUFF FOR G71
C654 C661 C648
.01UF
16V
10%
X7R
0402
NO STUFF
GND
C655
.01UF
16V
10%
X7R
0402
COMMON
GND
.1UF
10V
10%
X5R
0402
NO STUFF
C660
.1UF
10V
10%
X5R
0402
COMMON
www.vinafix.vn
136BGA CMD Mapping
CMD
CMD0
CMD1 RAS*
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11 WE*
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21
CMD22
CMD23
CMD25
CMD26
R603
0402
1%
R600
04021%COMMON
R599
0402
1%
180R@100MHz
LB503
NO STUFF
BEAD_0603
4.7UF
6.3V
10%
X5R
0603
NO STUFF
GND
180R@100MHz
LB502
COMMON
BEAD_0603
C633
4.7UF
6.3V
10%
X5R
0603
COMMON
6<> 9<>
ADDR
A<4>
A<5>
BA1
A<2>
A<4>
A<3>
BA2
CS0*
A<11>
CAS*
BA0
A<5>
A<12>
RST
A<7>
A<10>
CKE
A<0>
A<9>
A<6>
A<2>
A<8>
A<3>CMD24
A<1>
A<13>
9> 5<
9> 6<>
9<>
9<>
9<>
60.4
COMMON
40.2
40.2
COMMON
GND
F3V3
C632
4.7UF
6.3V
10%
X5R
0603
NO STUFF
GND
PEX_VDD
C630
4.7UF
6.3V
10%
X5R
0603
COMMON
GNDGNDGND
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
MEMORY: GPU Partition A/B
FBVDDQ
6<>
9<
6<>
9>
NO STUFF FOR G71
9<>
FBBD<63..0>
FBBDQM<7..0>
FBBDQS_RN<7..0>
FBBDQS_WP<7..0>
C662
.1UF
10V
10%
X5R
0402
NO STUFF
GND
FBVDDQ
GND
R608
511
1%
0402
NO STUFF
R607
1.18K
1%
0402
NO STUFF
U8
G71-N-A2
BGA1148
CHANGED
FBBD<0>
0
FBBD<1>
1
FBBD<2>
2
FBBD<3>
3
FBBD<4>
4
FBBD<5>
5
FBBD<6>
6
FBBD<7>
7
FBBD<8>
8
FBBD<9>
9
FBBD<10>
10
FBBD<11>
11
FBBD<12>
12
FBBD<13>
13
FBBD<14>
14
FBBD<15>
15
FBBD<16>
16
FBBD<17>
17
FBBD<18>
18
FBBD<19>
19
FBBD<20>
20
FBBD<21>
21
FBBD<22>
22
FBBD<23>
23
FBBD<24>
24
FBBD<25>
25
FBBD<26>
26
FBBD<27>
27
FBBD<28>
28
FBBD<29>
29
FBBD<30>
30
FBBD<31>
31
FBBD<32>
32
FBBD<33>
33
FBBD<34>
34
FBBD<35>
35
FBBD<36>
36
FBBD<37>
37
FBBD<38>
38
FBBD<39>
39
FBBD<40>
40
FBBD<41>
41
FBBD<42>
42
FBBD<43>
43
FBBD<44>
44
FBBD<45>
45
FBBD<46>
46
FBBD<47>
47
FBBD<48>
48
FBBD<49>
49
FBBD<50>
50
FBBD<51>
51
FBBD<52>
52
FBBD<53>
53
FBBD<54>
54
FBBD<55>
55
FBBD<56>
56
FBBD<57>
57
FBBD<58>
58
FBBD<59>
59
FBBD<60>
60
FBBD<61>
61
FBBD<62>
62
FBBD<63>
63
FBBDQM<0>
0
FBBDQM<1>
1
FBBDQM<2>
2
FBBDQM<3>
3
FBBDQM<4>
4
FBBDQM<5>
5
FBBDQM<6>
6
FBBDQM<7>
7
FBBDQS_RN<0>
0
FBBDQS_RN<1>
1
FBBDQS_RN<2>
2
FBBDQS_RN<3>
3
FBBDQS_RN<4>
4
FBBDQS_RN<5>
5
FBBDQS_RN<6>
6
FBBDQS_RN<7>
7
FBBDQS_WP<0>
0
FBBDQS_WP<1>
1
FBBDQS_WP<2>
2
FBBDQS_WP<3>
3
FBBDQS_WP<4>
4
FBBDQS_WP<5>
5
FBBDQS_WP<6>
6
FBBDQS_WP<7>
7
FB_VREF2
PIN IS NC IN G71
DDR3: VREF = 0.7 * FBVDDQ, FBVDDQ = 1.8V
1.26V = 1.8V * 1.18K / (511 + 1.18K)
G36
G35
H36
H34
J35
J34
K34 T30
K35
J31
K32
J30
H30
L32
K30
M31
L30
G31
J32
J33
F33
H31
E33
F31
F32
F35
G34
F36
F34
C35
D34
C36
D35
N35
M34
L34
N36
P36
P34
R36
R34
AC33
Y33
Y30
AB30
AA32
AD32
AD33
AA33
T36
R35
T34
U36
W35
U34
V34
W36
AC36
AA36
AC34
AB34
AA35
Y34
Y36
W34
J36
M32
H33
E34
N34
Y32
T35
AA34
L36
K33
G32
E36
M36
AB32
V35
AB35
K36
L33
G33
D36
M35
AB31
V36
AB36
J27
FBB_CMD<0>
P33
FBB_CMD<1>
N33
FBB_CMD<2>
R31
FBB_CMD<3>
U33
FBB_CMD<4>
V30
FBB_CMD<5>
T33
FBB_CMD<6>
FBB_CMD<7>
N32
FBB_CMD<8>
R32
FBB_CMD<9>
P32
FBB_CMD<10>
U32
FBB_CMD<11>
U30
FBB_CMD<12>
P30
FBB_CMD<13>
V31
SNN_FBB_CMD14
T28
FBB_CMD<15>
W30
FBB_CMD<16>
V32
FBB_CMD<17>
T32
FBB_CMD<18>
N30
FBB_CMD<19>
P28
FBB_CMD<20>
P29
FBB_CMD<21>
U29
FBB_CMD<22>
N28
FBB_CMD<23>
R30
FBB_CMD<24>
M30
FBB_CMD<25>
T29
SNN_FBB_CMD26
N29
FBB_CLK0
M28
FBB_CLK0*
L28
FBB_CLK1
W31
FBB_CLK1*
W32
SNN_GPU_R28
R28
SNN_GPU_K29
K29
FBB_DEBUG
C34
SNN_FBB_REFCLK
AA30
SNN_FBB_REFCLK*
Y29
FBCAL1_PD_VDDQ
H27
FBCAL1_PU_GND
H26
FBCAL1_TERM_GND
J26
AB28 IS NC FOR G71
FBAB_PLLVDD
AB28
FBAB_PLLAVDD
AC29
AC28
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
FBB_CMD<26..0>
9>
6<
9>
6<
9>
6<
9>
6<
6< 9>
9<>
TP8
NO STUFF
3<>
3<>
9<>
9<>
3<>
R609
0402
R612
0402
R613
0402
9<>
1%
1%
1%
9<>
9<>
9<>
60.4
NO STUFF
40.2
NO STUFF
40.2
NO STUFF
600-10455-0002-001
design
LFarasati
GND
3 OF 24
9-FEB-2006
FBVDDQ
Page4: MEMORY: GPU Partition C/D
OUT
OUT
OUT
OUT
OUTBIBI
BI
5/24 MEM_D
FBD_CMD6
FBD_CMD4
FBD_CMD5
FBD_CMD3
FBD_CMD2
FBD_CMD1
FBD_CMD0
FBD_CMD7
FBD_CMD26
FBD_CMD24
FBD_CMD25
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD20
FBD_CMD19
FBD_CMD18
FBD_CMD17
FBD_CMD16
FBD_CMD15
FBD_CMD14
FBD_CMD13
FBD_CMD12
FBD_CMD11
FBD_CMD9
FBD_CMD10
FBD_CMD8
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
RFU
RFU
FBD_REFCLK
FBD_DEBUG
FBD_PLLVDD
FBD_PLLAVDD
FBD_REFCLK
FBD_PLLGND
FBDD6
FBDD5
FBDD4
FBDD3
FBDD2
FBDD1
FBDD0
FBDD7
FBDD27
FBDD26
FBDD24
FBDD23
FBDD22
FBDD19
FBDD20
FBDD18
FBDD17
FBDD16
FBDD14
FBDD15
FBDD13
FBDD12
FBDD11
FBDD9
FBDD10
FBDD8
FBDD25
FBDD21
FBDD47
FBDD46
FBDD45
FBDD44
FBDD43
FBDD42
FBDD39
FBDD41
FBDD40
FBDD37
FBDD38
FBDD35
FBDD36
FBDD34
FBDD32
FBDD33
FBDD31
FBDD30
FBDD29
FBDD28
FBDD48
FBDDQM2
FBDDQM1
FBDDQM0
FBDD63
FBDD62
FBDD60
FBDD61
FBDD59
FBDD58
FBDD57
FBDD55
FBDD56
FBDD54
FBDD53
FBDD52
FBDD51
FBDD50
FBDD49
FBDDQS_WP2
FBDDQS_WP1
FBDDQS_WP0
FBDDQS_RN7
FBDDQS_RN4
FBDDQS_RN5
FBDDQS_RN6
FBDDQS_RN3
FBDDQS_RN2
FBDDQS_RN1
FBDDQS_RN0
FBDDQM7
FBDDQM6
FBDDQM4
FBDDQM5
FBDDQM3
FBDDQS_WP3
FBDDQS_WP7
FBDDQS_WP6
FBDDQS_WP5
FBDDQS_WP4
BI
OUT
OUT
OUT
OUT
OUT
OUTINOUTBIBI
BI
4/24 MEM_C
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD23
FBC_CMD22
FBC_CMD21
FBC_CMD25
FBC_CMD24
FBC_CMD26
FBC_CLK1
FBC_CLK0
FBC_CLK1
FBC_CLK0
RFU
RFU
FBC_DEBUG
FBC_REFCLK
FBC_REFCLK
FBC_PLLAVDD
FBC_PLLVDD
FBC_PLLGND
FBCD0
FBCD2
FBCD4
FBCD6
FBCD1
FBCD3
FBCD5
FBCD7
FBCD10
FBCD11
FBCD18
FBCD21
FBCD24
FBCD12
FBCD17
FBCD15
FBCD14
FBCD8
FBCD9
FBCD13
FBCD20
FBCD23
FBCD22
FBCD25
FBCD26
FBCD27
FBCD19
FBCD16
FBCD31
FBCD34
FBCD36
FBCD38
FBCD28
FBCD30
FBCD29
FBCD32
FBCD37
FBCD40
FBCD41
FBCD39
FBCD42
FBCD43
FBCD44
FBCD46
FBCD45
FBCD47
FBCD35
FBCD33
FBCD48
FBCD52
FBCD49
FBCD50
FBCD51
FBCD54
FBCD53
FBCD56
FBCD55
FBCD59
FBCD58
FBCD57
FBCD60
FBCD61
FBCD63
FBCD62
FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM5
FBCDQM4
FBCDQM6
FBCDQM7
FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN6
FBCDQS_RN5
FBCDQS_RN4
FBCDQS_RN7
FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7
OUTINOUT
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
U8
G71-N-A2
BGA1148
C18
C17
A17
B16
C14
A16
C15
A14
A18
A19
B19
B18
B21
C19
B22
C21
E15
D16
D17
G16
E16
E14
G13
D13
A22
C22
A23
A24
C24
C25
B24
C28
B27
C27
B28
C29
A29
B30
A30
E31
E28
D28
F29
F30
D33
D32
D31
G27
F25
G26
D26
G29
G28
E27
F28
A34
C32
B34
C33
C31
B31
A31
C30
C16
G14
C26
A28
D29
D27
B33
B15
A21
D14
B25
A27
E30
E25
A33
A15
A20
E13
A25
A26
D30
E26
A32
CHANGED
FBC_CMD<0>
F18
FBC_CMD<1>
H20
FBC_CMD<2>
E18
FBC_CMD<3>
E20
FBC_CMD<4>
D23
FBC_CMD<5>
G24
D24
FBC_CMD<6>
FBC_CMD<7>
G23
FBC_CMD<8>
D20
FBC_CMD<9>
E22
FBC_CMD<10>
J21
FBC_CMD<11>
E21
FBC_CMD<12>
G20
FBC_CMD<13>
F22
SNN_FBC_CMD14
H21
FBC_CMD<15>
E17
FBC_CMD<16>
E19
FBC_CMD<17>
D21
FBC_CMD<18>
E23
FBC_CMD<19>
F19
FBC_CMD<20>
E24
FBC_CMD<21>
G21
FBC_CMD<22>
G19
FBC_CMD<23>
G25
FBC_CMD<24>
G18
FBC_CMD<25>
G22
SNN_FBC_CMD_26G17
FBC_CLK0H17
FBC_CLK0*
J16
FBC_CLK1
J24
FBC_CLK1*
H23
SNN_GPU_H24
H24
SNN_GPU_J25J25
FBC_DEBUG
H16
SNN_FBC_REFCLK
F15
SNN_FBC_REFCLK*G15
H13 IS NC FOR G71
FBCD_PLLVDD
H13
FBCD_PLLAVDD
J12
J13
GND
FBCD<63..0>
FBCDQM<7..0>
FBCDQS_RN<7..0>
FBCDQS_WP<7..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBCD<0>
FBCD<1>
FBCD<2>
FBCD<3>
FBCD<4>
FBCD<5>
FBCD<6>
FBCD<7>
FBCD<8>
FBCD<9>
FBCD<10>
FBCD<11>
FBCD<12>
FBCD<13>
FBCD<14>
FBCD<15>
FBCD<16>
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>
FBCD<24>
FBCD<25>
FBCD<26> C23
FBCD<27>
FBCD<28>
FBCD<29>
FBCD<30>
FBCD<31>
FBCD<32>
FBCD<33>
FBCD<34>
FBCD<35>
FBCD<36>
FBCD<37>
FBCD<38>
FBCD<39>
FBCD<40>
FBCD<41>
FBCD<42>
FBCD<43>
FBCD<44>
FBCD<45>
FBCD<46>
FBCD<47>
FBCD<48>
FBCD<49>
FBCD<50>
FBCD<51>
FBCD<52>
FBCD<53>
FBCD<54>
FBCD<55>
FBCD<56>
FBCD<57>
FBCD<58>
FBCD<59>
FBCD<60>
FBCD<61>
FBCD<62>
FBCD<63>
FBCDQM<0>
FBCDQM<1> C20
FBCDQM<2>
FBCDQM<3>
FBCDQM<4>
FBCDQM<5>
FBCDQM<6>
FBCDQM<7>
FBCDQS_RN<0>
FBCDQS_RN<1>
FBCDQS_RN<2>
FBCDQS_RN<3>
FBCDQS_RN<4>
FBCDQS_RN<5>
FBCDQS_RN<6>
FBCDQS_RN<7>
FBCDQS_WP<0>
FBCDQS_WP<1>
FBCDQS_WP<2>
FBCDQS_WP<3>
FBCDQS_WP<4>
FBCDQS_WP<5>
FBCDQS_WP<6>
FBCDQS_WP<7>
7<> 9<>
7<> 9>
7<> 9<
7<> 9>
FBC_CMD<26..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
9>
7<
9>
7<
9>
7<
9>
7<
9<>
TP6
NO STUFF
9<> 4<>
NO STUFF FOR G71
C760 C761 C765
.01UF
16V
10%
X7R
0402
NO STUFF
GND
C762
.01UF
16V
10%
X7R
0402
COMMON
GND
.1UF
10V
10%
X5R
0402
NO STUFF
GND
C775
.1UF
10V
10%
X5R
0402
COMMON
GND GND
www.vinafix.vn
136BGA CMD Mapping
ADDR
CMD
A<4>CMD0
RAS*CMD1
A<5>
CMD2
BA1
CMD3
A<2>
CMD4
A<4>
CMD5
A<3>
CMD6
BA2
CMD7
CS0*
CMD8
A<11>
CMD9
CAS*
CMD10
CMD11 WE*
BA0
CMD12
A<5>
CMD13
A<12>
CMD14
RST
CMD15
A<7>
CMD16
A<10>
CMD17
CKE
CMD18
A<0>
CMD19
A<9>
CMD20
A<6>
CMD21
A<2>
CMD22
A<8>
CMD23
A<3>
CMD24
A<1>
CMD25
A<13>
CMD26
180R@100MHz
LB504
NO STUFF
BEAD_0603
4.7UF
6.3V
10%
X5R
0603
NO STUFF
GND
180R@100MHz
LB18
CHANGED
BEAD_0603
C781
4.7UF
6.3V
10%
X5R
0603
COMMON
9> 7<
8<> 9<>
8<> 9>
8<>
9<
8<>
9>
F3V3
C780
4.7UF
6.3V
10%
X5R
0603
NO STUFF
GND
PEX_VDD
C62
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
MEMORY: GPU Partition C/D
FBDD<63..0>
FBDDQM<7..0>
FBDDQS_RN<7..0>
FBDDQS_WP<7..0>
U8
G71-N-A2
BGA1148
CHANGED
FBD_CMD<0>
FBDD<0>
0
FBDD<1>
1
FBDD<2>
2
FBDD<3>
3
FBDD<4>
4
FBDD<5>
5
FBDD<6>
6
FBDD<7>
7
FBDD<8>
8
FBDD<9>
9
FBDD<10>
10
FBDD<11>
11
FBDD<12>
12
FBDD<13>
13
FBDD<14>
14
FBDD<15>
15
FBDD<16>
16
FBDD<17>
17
FBDD<18>
18
FBDD<19>
19
FBDD<20>
20
FBDD<21>
21
FBDD<22>
22
FBDD<23>
23
FBDD<24>
24
FBDD<25>
25
FBDD<26>
26
FBDD<27>
27
FBDD<28>
28
FBDD<29>
29
FBDD<30>
30
FBDD<31>
31
FBDD<32>
32
FBDD<33>
33
FBDD<34>
34
FBDD<35>
35
FBDD<36>
36
FBDD<37>
37
FBDD<38>
38
FBDD<39>
39
FBDD<40>
40
FBDD<41>
41
FBDD<42>
42
FBDD<43>
43
FBDD<44>
44
FBDD<45>
45
FBDD<46>
46
FBDD<47>
47
FBDD<48>
48
FBDD<49>
49
FBDD<50>
50
FBDD<51>
51
FBDD<52>
52
FBDD<53>
53
FBDD<54>
54
FBDD<55>
55
FBDD<56>
56
FBDD<57>
57
FBDD<58>
58
FBDD<59>
59
FBDD<60>
60
FBDD<61>
61
FBDD<62>
62
FBDD<63>
63
FBDDQM<0>
0
FBDDQM<1>
1
FBDDQM<2>
2
FBDDQM<3>
3
FBDDQM<4>
4
FBDDQM<5>
5
FBDDQM<6>
6
FBDDQM<7>
7
FBDDQS_RN<0>
0
FBDDQS_RN<1>
1
FBDDQS_RN<2>
2
FBDDQS_RN<3>
3
FBDDQS_RN<4>
4
FBDDQS_RN<5>
5
FBDDQS_RN<6>
6
FBDDQS_RN<7>
7
FBDDQS_WP<0>
0
FBDDQS_WP<1>
1
FBDDQS_WP<2>
2
FBDDQS_WP<3>
3
FBDDQS_WP<4>
4
FBDDQS_WP<5>
5
FBDDQS_WP<6>
6
FBDDQS_WP<7>
7
H3
J3
J1
J2
M3
K3
L3 F8
M1
H1
G3
G1
G2
F3
E1
D1
D2
P4
N7
M7
N5
P5
R7
T7
P7
C1
C5
C2
B4
A3
B3
C4
C3
A8
C6
C7
A7
C8
C9
A9
B9
E12
E9
F9
G10
D10
G12
F12
D11
F4
E4
D4
D5
D8
E7
D7
D9
B13
C11
A13
C13
A11
A10
B10
C10
K2
E3
N4
D3
B7
G11
F5
C12
K1
F2
R6
A4
B6
E10
E6
A12
L1
F1
R5
A5
A6
E11
D6
B12
M6
FBD_CMD<1>
G5
FBD_CMD<2>
L7
FBD_CMD<3>
K5
FBD_CMD<4>
J10
FBD_CMD<5>
G8
FBD_CMD<6>
FBD_CMD<7>
G6
FBD_CMD<8>
H6
FBD_CMD<9>
F6
FBD_CMD<10>
K8
FBD_CMD<11>
L5
FBD_CMD<12>
H4
FBD_CMD<13>
G4
SNN_FBD_CMD14
K9
FBD_CMD<15>
L4
FBD_CMD<16>
K4
FBD_CMD<17>
K7
FBD_CMD<18>
G7
FBD_CMD<19>
J4
FBD_CMD<20>
F7
FBD_CMD<21>
J5
FBD_CMD<22>
J6
FBD_CMD<23>
H7
FBD_CMD<24>
L8
FBD_CMD<25>
J7
SNN_FBD_CMD_26
M5
FBD_CLK0
L9
FBD_CLK0*
M9
FBD_CLK1
J9
FBD_CLK1*
J8
SNN_GPU_H10
H10
SNN_GPU_L11
L11
FBD_DEBUG
N8
SNN_FBD_REFCLK
G9
SNN_FBD_REFCLK*
H9
H11 IS NC FOR G71
FBCD_PLLVDD
H11
FBCD_PLLAVDD
J11
H12
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
FBD_CMD<26..0>
8<
8<
8<
8<
9<>
TP5
NO STUFF
4<>
4<>
9>
9>
9>
9>
9<>
9<>
4<> 9<>
9> 8<
600-10455-0002-001
design
LFarasati
4 OF 24
9-FEB-2006
Page5: FBA Partition
OUT
OUTINININOUTININ
OUT
MIRRORNONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS
RAS
BA0
BA1
A7
A8/AP
A3
A11
A2
A1
A0
A9
A6
A5
A4
A10
RAS
CAS
A0
CS
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
CKE
CLK
CLK
NC/RFU
NC/RFU
NC/RFU
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
OUT
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
ININOUTININININ
MIRRORNONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS
RAS
BA0
BA1
A7
A8/AP
A3
A11
A2
A1
A0
A9
A6
A5
A4
A10
RAS
CAS
A0
CS
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
CKE
CLK
CLK
NC/RFU
NC/RFU
NC/RFU
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
BIBIBI
BI
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
STUFF CAP FOR G71, 0R FOR G70
3> 9>
FBVDDQ
R566
0
5%
0402
NO STUFF
C578
.01UF
25V
10%
X7R
0402
COMMON
FBA_CLK0_TERM
R563
R562
40.2
40.2
GND
0402
COMMON
3> 9>
3>
9>
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
1%
1%
0402
COMMON
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
FBVDDQ
0LB27
CHANGED
0603
0LB32
CHANGED
0603
9<
9>
3<> 9<>
3> 9>
3<
3>
FBAD<63..0>
FBADQM<7..0>
FBADQS_RN<7..0>
FBADQS_WP<7..0>
CMD-Addr Mapping
144 136 ADDR
CMD15 CMD1 RAS*
CMD25 CMD10 CAS*
CMD9 CMD11 WE*
CMD8 CMD8 CS0*
CMD7 CMD7 BA2
CMD1 CMD19 A<0>
CMD3 CMD25 A<1>
CMD2 CMD22 0A<2>
CMD0 CMD24 0A<3>
CMD24 CMD0 0A<4>
CMD22 CMD2 0A<5>
CMD13 CMD4 1A<2>
CMD4 CMD6 1A<3>
CMD5 CMD5 1A<4>
CMD6 CMD13 1A<5>
CMD21 CMD21 A<6>
CMD23 CMD16 A<7>
CMD19 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD16 CMD9 A<11>
CMD10 CMD12 BA0
CMD18 CMD3 BA1
CMD11 CMD18 CKE
CMD12 CMD15 RST
9<>
9<>
9<>
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBA_CMD<26..0>
FBADQM<0>
FBADQM<1>
FBADQM<2>
FBADQM<3>
FBADQM<4>
FBADQM<5>
FBADQM<6>
FBADQM<7>
FBADQS_RN<0>
FBADQS_RN<1>
FBADQS_RN<2>
FBADQS_RN<3>
FBADQS_RN<4>
FBADQS_RN<5>
FBADQS_RN<6>
FBADQS_RN<7>
FBADQS_WP<0>
FBADQS_WP<1>
FBADQS_WP<2>
FBADQS_WP<3>
FBADQS_WP<4>
FBADQS_WP<5>
FBADQS_WP<6>
FBADQS_WP<7>
U11
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
GND
FBA_CMD<1>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<8>
FBA_CMD<19>
FBA_CMD<25>
FBA_CMD<21>
FBA_CMD<16>
FBA_CMD<23>
FBA_CMD<20>
FBA_CMD<17>
FBA_CMD<9>
FBA_CMD<12>
FBA_CMD<3>
FBA_CMD<7>
FBA_CMD<18>
FBA_CLK0
FBA_CLK0*
SNN_FBA0_NC1
SNN_FBA0_NC2
FBA_CMD<15>
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
15
A9
A4
FBA_ZQ0
GND
R583
10K
5%
0402
COMMON
GND
FBA_VDDA0
FBA_VDDA1
C113
.047UF
16V
10%
X7R
0402
COMMON
R557
10K
5%
0402
COMMON
GND
GND
C102
.047UF
16V
10%
X7R
0402
COMMON
R85
240
5%
0603
COMMON
K12
J12
K1
J1
GND
U11
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
0
1
2
3
4
5
6
7
32
33
34
35
36
37
38
39
FBAD<0>
FBAD<1>
FBAD<2>
FBAD<3>
FBAD<4>
FBAD<5>
FBAD<6>
FBAD<7>
FBADQM<0>
FBADQS_RN<0>
FBAD<32>
FBAD<33>
FBAD<34>
FBAD<35>
FBAD<36>
FBAD<37>
FBAD<38>
FBAD<39>
FBADQM<4>
FBADQS_RN<4>
FBADQS_WP<4>
L10
T10
M10
R11
T11
R10
N11
M11
N10
P10
P11FBADQS_WP<0>
U12
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
L3
R3
T3
M3
M2
N2
T2
R2
N3
P3
P2
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
GND
GND
FBA_VREF0
FBA_VREF2
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBAD<8>
FBAD<9>
FBAD<10>
FBAD<11>
FBAD<12>
FBAD<13>
FBAD<14>
FBAD<15>
FBADQM<1>
FBADQS_RN<1>
FBADQS_WP<1>
FBAD<40>
FBAD<41>
FBAD<42>
FBAD<43>
FBAD<44>
FBAD<45> G10
FBAD<46>
FBAD<47>
FBADQM<5>
FBADQS_RN<5>
FBADQS_WP<5>
STUFF CAP FOR G71, 0R FOR G70
9>
GND
9>
9>
FBVDDQ
R81
511
R1
1%
0402
COMMON
R79
1.3K
R2
1%
0402
COMMON
GND
U11
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
R3
T2
R2
N2
T3
M3
M2
L3
N3
P3
P2
U12
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
B10
E11
F11
C10
C11
F10
B11
E10
D10
D11
FBVDDQ
R567
0
5%
0402
NO STUFF
C579
.01UF
25V
10%
X7R
0402
COMMON
FBA_CLK1_TERM
R579
R578
40.2
40.2
0402
COMMON
3>
3>
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
C101
.1UF
10V
10%
X5R
0402
COMMON
1%
1%
0402
COMMON
9<>
FBVDDQ
FBVDDQ
R90
511
R1
1%
0402
COMMON
R93
1.3K
R2
1%
0402
COMMON
GND
FBAD<16>
16
FBAD<17>
17
FBAD<18>
18
FBAD<19>
19
FBAD<20>
20
FBAD<21>
21
FBAD<22>
22
FBAD<23>
23
FBADQM<2>
FBADQS_RN<2>
FBAD<48>
48
49
FBAD<50>
50
FBAD<51>
51
FBAD<52>
52
FBAD<53> E2
53
FBAD<54>
54
FBAD<55>
55
FBADQM<6>
FBADQS_RN<6>
FBADQS_WP<6>
F2
G3
F3
C2
E2
C3
B3
B2
E3
D3
D2FBADQS_WP<2>
B3
C3FBAD<49>
F3
C2
F2
B2
G3
E3
D3
D2
CMD-Addr Mapping
144 136 ADDR
CMD15 CMD1 RAS*
CMD25 CMD10 CAS*
CMD9 CMD11 WE*
CMD8 CMD8 CS0*
CMD7 CMD7 BA2
CMD1 CMD19 A<0>
CMD3 CMD25 A<1>
CMD2 CMD22 0A<2>
CMD0 CMD24 0A<3>
CMD24 CMD0 0A<4>
CMD22 CMD2 0A<5>
CMD13 CMD4 1A<2>
CMD4 CMD6 1A<3>
CMD5 CMD5 1A<4>
CMD6 CMD13 1A<5>
CMD21 CMD21 A<6>
CMD23 CMD16 A<7>
CMD19 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD16 CMD9 A<11>
CMD10 CMD12 BA0
CMD18 CMD3 BA1
CMD11 CMD18 CKE
CMD12 CMD15 RST
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
LB501
LB28
0
CHANGED0603
0
CHANGED0603
9<>
C112
.1UF
10V
10%
X5R
0402
COMMON
U11
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
U12
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
9<>
9<>
24
25
26
27
28
29
30
31
56
57
58
59
60
61
62
63
FBVDDQ
9<>
FBAD<24>
FBAD<25>
FBAD<26>
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30>
FBAD<31>
FBADQM<3>
FBADQS_RN<3>
FBADQS_WP<3>
FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<60>
FBAD<61>
FBAD<62>
FBAD<63>
FBADQM<7>
FBADQS_RN<7>
FBADQS_WP<7>
U12
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
7
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
12
1
11
GND
15
FBA_CMD<7>
FBA_CMD<8>
FBA_CMD<18>
FBA_CMD<10>
FBA_CMD<5>
FBA_CMD<13>
FBA_CMD<21>
FBA_CMD<20>
FBA_CMD<19>
FBA_CMD<25>
FBA_CMD<4>
FBA_CMD<9>
FBA_CMD<17>
FBA_CMD<6>
FBA_CMD<23>
FBA_CMD<16>
FBA_CMD<3>
FBA_CMD<12>
FBA_CMD<1>
FBA_CMD<11>
FBA_CLK1
FBA_CLK1*
SNN_FBA1_NC1
SNN_FBA1_NC2
FBA_CMD<15>
A9
FBA_ZQ1 A4
R86
240
5%
0603
COMMON
GND
C557
.047UF
16V
10%
X7R
0402
COMMON
K12
J12
K1
J1
FBA_VDDA2
FBA_VDDA3
C103
.047UF
16V
10%
X7R
0402
COMMON
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBA_VREF1
FBA_VREF3
FBVDDQ
GND
GND
FBA_CMD<4>
FBA_CMD<6>
FBA_CMD<5>
FBA_CMD<13>
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQ
DDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBVDDQ
R89
511
R1
1%
0402
COMMON
R92
1.3K
R2
1%
COMMON
GND
C111
.1UF
10V
X5R
0402
COMMON
9<>
R574
0402
R575
0402
R565
0402
R556
0402
R576
0402
R571
0402
R564
0402
R552
0402
FBVDDQ
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
FBVDDQ
R82
511
R1
1%
0402
COMMON
9<>
R80
1.3K
04020402
COMMON
R2
1%
C104
.1UF
10V
10%10%
X5R
0402
COMMON
GND
GND
Decoupling for FBA 0..31
FBVDDQ
C604
4.7UF
6.3V
10%
X5R
0805
COMMON
C599
4.7UF
6.3V
10%
X5R
0805
COMMON
C551
4.7UF
6.3V
10%
X5R
0805
COMMON
C545
4.7UF
6.3V
10%
X5R
0805
COMMON
C550
.1UF
10V
10%
X5R
0402
COMMON
C589
.1UF
10V
10%
X5R
0402
COMMON
C596
.1UF
10V
10%
X5R
0402
COMMON
C587
4.7UF
6.3V
10%
X5R
0805
COMMON
C554
.1UF
10V
10%
0402
COMMON
C562
.1UF
10V
10%
X5R
0402
COMMON
C585
.022UF
16V
10%
X7R
0402
COMMON
C574
4.7UF
6.3V
10%
X5R
0805
COMMON
GND
C594
4.7UF
6.3V
10%
X5RX5R
0805
COMMON
C553
.1UF
10V
10%
X5R
0402
COMMON
C566
4.7UF
6.3V
10%
X5R
0805
COMMON
C573
.1UF
10V
10%
X5R
0402
COMMON
C556
.022UF
16V
10%
X7R
0402
COMMON
C576
.022UF
16V
10%
X7R
0402
COMMON
C590
.022UF
16V
10%
X7R
0402
COMMON
C572
.022UF
16V
10%
X7R
0402
COMMON
C564
.022UF
16V
10%
X7R
0402
COMMON
C593
.01UF
25V
10%
X7R
0402
COMMON
C544
4.7UF
6.3V
10%
X5R
0805
COMMON
C558
.022UF
16V
10%
X7R
0402
COMMON
C588
.1UF
10V
10%
X5R X5R
0402
COMMON
C559
.1UF
10V
10%
X5R
0402
COMMON
C549
4.7UF
6.3V
10%
X5R
0805
COMMON
C552
4.7UF
6.3V
10%
0805
COMMON
C583
4.7UF
6.3V
10%
X5R
0805
COMMON
C586
.01UF
25V
10%
X7R
0402
COMMON
C591
.01UF
25V
10%
X7R
0402
COMMON
C584
.01UF
25V
10%
X7R
0402
COMMON
C595
4.7UF
6.3V
10%
X5R
0805
COMMON
C561
.022UF
16V
10%
X7R
0402
COMMON
C560
.1UF
10V
10%
X5R
0402
COMMON
C605
4.7UF
6.3V
10%
X5R
0805
COMMON
GND
GND
GND
E11
B11
F11
G10
C10
C11
B10
F10
E10
D10
D11
M11
N11
M10
L10
T10
R11
T11
R10
N10
P10
P11
U11
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
U12
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
www.vinafix.vn
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
FBA Partition
600-10455-0002-001
design
LFarasati
5 OF 24
9-FEB-2006
OUT
OUTINININOUTININ
OUT
MIRRORNONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS
RAS
BA0
BA1
A7
A8/AP
A3
A11
A2
A1
A0
A9
A6
A5
A4
A10
RAS
CAS
A0
CS
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
CKE
CLK
CLK
NC/RFU
NC/RFU
NC/RFU
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
OUT
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
ININININOUTININ
MIRRORNONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS
RAS
BA0
BA1
A7
A8/AP
A3
A11
A2
A1
A0
A9
A6
A5
A4
A10
RAS
CAS
A0
CS
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
CKE
CLK
CLK
NC/RFU
NC/RFU
NC/RFU
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
BIBIBI
BI
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
Page6: FBB Partition
STUFF CAP FOR G71, 0R FOR G70
FBVDDQ
9>
C616
.01UF
25V
10%
X7R
FBB_CLK0_TERM
0402
COMMON
R591
40.2
9>
9>
GND
1%
0402
COMMON
3>
3>
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
R593
40.2
0402
COMMON
R595
0
5%
0402
NO STUFF
1%
3> 9>
CMD-Addr Mapping
144 136 ADDR
CMD15 CMD1 RAS*
CMD25 CMD10 CAS*
CMD9 CMD11 WE*
CMD8 CMD8 CS0*
CMD7 CMD7 BA2
CMD1 CMD19 A<0>
CMD3 CMD25 A<1>
CMD2 CMD22 0A<2>
CMD0 CMD24 0A<3>
CMD24 CMD0 0A<4>
CMD22 CMD2 0A<5>
CMD13 CMD4 1A<2>
CMD4 CMD6 1A<3>
CMD5 CMD5 1A<4>
CMD6 CMD13 1A<5>
CMD21 CMD21 A<6>
CMD23 CMD16 A<7>
CMD19 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD16 CMD9 A<11>
CMD10 CMD12 BA0
CMD18 CMD3 BA1
CMD11 CMD18 CKE
CMD12 CMD15 RST
FBB_CMD<26..0>
9<>
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
FBVDDQ
9<>
9<>
0LB26
CHANGED
0603
CHANGED
0603
FBBD<63..0>
FBBDQM<7..0>
FBBDQS_RN<7..0>
FBBDQS_WP<7..0>
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
9<>
LB29
3<>
3> 9>
3< 9<
3> 9>
U10
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
15
FBB_CMD<1>
FBB_CMD<10>
FBB_CMD<11>
FBB_CMD<8>
FBB_CMD<19>
FBB_CMD<25>
FBB_CMD<22>
FBB_CMD<24>
FBB_CMD<0>
FBB_CMD<2>
FBB_CMD<21>
FBB_CMD<16>
FBB_CMD<23>
FBB_CMD<20>
FBB_CMD<17>
FBB_CMD<9>
FBB_CMD<12>
FBB_CMD<3>
FBB_CMD<7>
FBB_CMD<18>
FBB_CLK0
FBB_CLK0*
SNN_FBB0_NC1
SNN_FBB0_NC2
GND
FBB_CMD<15>
A9
A4FBB_ZQ0
GND
GND
C98
.047UF
16V
10%
X7R
0402
COMMON
R74
240
5%
0603
COMMON
K12
J12
K1
J1
R590
10K
5%
0402
COMMON
GNDGND
FBB_VDDA0
FBB_VDDA1
C100
.047UF
16V
10%
X7R
0402
COMMON
R587
10K
5%
0402
COMMON
GND
L10
R10
M10
R11
T11
T10
M11
N11
N10
P10
P11
L3
R3
T3
M2FBBD<35>
T2
R2
N2
N3
P3
P2
FBBDQM<0>
FBBDQM<1>
FBBDQM<2>
FBBDQM<3>
FBBDQM<4>
FBBDQM<5>
FBBDQM<6>
FBBDQM<7>
FBBDQS_RN<0>
FBBDQS_RN<1>
FBBDQS_RN<2>
FBBDQS_RN<3>
FBBDQS_RN<4>
FBBDQS_RN<5>
FBBDQS_RN<6>
FBBDQS_RN<7>
FBBDQS_WP<0>
FBBDQS_WP<1>
FBBDQS_WP<2>
FBBDQS_WP<3>
FBBDQS_WP<4>
FBBDQS_WP<5>
FBBDQS_WP<6>
FBBDQS_WP<7>
FBBD<0>
0
FBBD<1>
1
FBBD<2>
2
FBBD<3>
3
FBBD<4>
4
FBBD<5>
5
FBBD<6>
6
FBBD<7>
7
FBBDQM<0>
FBBDQS_RN<0>
FBBDQS_WP<0>
FBBD<32>
32
FBBD<33>
33
FBBD<34>
34
35
FBBD<36> M3
36
FBBD<37>
37
FBBD<38>
38
FBBD<39>
39
FBBDQM<4>
FBBDQS_RN<4>
FBBDQS_WP<4>
U10
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
U13
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
VREF = FBVDDQ * R2/(R1 + R2)
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
GND
GND
FBB_VREF0
FBB_VREF2
VREF = 0.70 * FBVDDQ
DDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBBD<8>
FBBD<9>
FBBD<10>
FBBD<11>
FBBD<12>
FBBD<13>
FBBD<14>
FBBD<15>
FBBDQM<1>
FBBDQS_RN<1>
FBBDQS_WP<1>
FBBD<40>
FBBD<41>
FBBD<42>
FBBD<44>
FBBD<46>
FBBD<47>
FBBDQM<5>
FBBDQS_RN<5>
FBBDQS_WP<5>
STUFF CAP FOR G71, 0R FOR G70
FBVDDQ
9>
C571
.01UF
25V
10%
X7R
FBB_CLK1_TERM
0402
COMMON
GND
3>
9>
3>
9>
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
R577
40.2
1%
0402
COMMON
FBVDDQ
R75
511
R1
1%
0402
COMMON
R76
1.3K
R2
1% 10V
0402
COMMON
C97
.1UF
10%
X5R
0402
COMMON
GND
U10
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
M2
T3
R2
N2
R3
T2
M3
L3
N3
P3
P2
U13
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
F10
E11
F11
B10FBBD<43>
B11
C10FBBD<45>
G10
C11
E10
D10
D11
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBBD<16>
FBBD<17>
FBBD<18>
FBBD<19>
FBBD<20>
FBBD<21>
FBBD<22>
FBBD<23>
FBBDQM<2>
FBBDQS_RN<2>
FBBDQS_WP<2>
FBBD<48>
FBBD<49>
FBBD<50>
FBBD<51>
FBBD<52>
FBBD<53>
FBBD<54>
FBBD<55>
FBBDQM<6>
FBBDQS_RN<6>
FBBDQS_WP<6>
9<>
R561
0
5%
0402
NO STUFF
R77
511
0402
COMMON
R78
1.3K
0402
COMMON
FBVDDQ
1%
1%
GND
R573
40.2
1%
0402
COMMON
FBVDDQ
R1
R2
R11
R10
T10
N11
M10
T11
M11
L10
N10
P10
P11
CMD-Addr Mapping
144 136 ADDR
CMD15 CMD1 RAS*
CMD25 CMD10 CAS*
CMD9 CMD11 WE*
CMD8 CMD8 CS0*
CMD7 CMD7 BA2
CMD1 CMD19 A<0>
CMD3 CMD25 A<1>
CMD2 CMD22 0A<2>
CMD0 CMD24 0A<3>
CMD24 CMD0 0A<4>
CMD22 CMD2 0A<5>
CMD13 CMD4 1A<2>
CMD4 CMD6 1A<3>
CMD5 CMD5 1A<4>
CMD6 CMD13 1A<5>
CMD21 CMD21 A<6>
CMD23 CMD16 A<7>
CMD19 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD16 CMD9 A<11>
CMD10 CMD12 BA0
CMD18 CMD3 BA1
CMD11 CMD18 CKE
CMD12 CMD15 RST
LB30
U10
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
G3
C3
B3
E2
F3
C2
B2
F2
E3
D3
D2
U13
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
FBVDDQ
9<>
ZQ = 6x desired outputDDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
9<>
9<>
0LB31
CHANGED
0603
0
CHANGED
0603
9<>
C99
.1UF
10V
10%
X5R
0402
COMMON
24
25
26
27
28
29
30
31
56
57
58
59
60
61
62
63
GND
FBBD<24>
FBBD<25>
FBBD<26>
FBBD<27>
FBBD<28>
FBBD<29>
FBBD<30>
FBBD<31>
FBBDQM<3>
FBBDQS_RN<3>
FBBDQS_WP<3>
FBBD<56>
FBBD<57>
FBBD<58>
FBBD<59>
FBBD<60>
FBBD<61>
FBBD<62>
FBBD<63>
FBBDQM<7>
FBBDQS_RN<7>
FBBDQS_WP<7>
7
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
12
1
11
GND
15
FBB_CMD<7>
FBB_CMD<8>
FBB_CMD<18>
FBB_CMD<10>
FBB_CMD<5>
FBB_CMD<13>
FBB_CMD<21>
FBB_CMD<20>
FBB_CMD<19>
FBB_CMD<25>
FBB_CMD<4>
FBB_CMD<9>
FBB_CMD<17>
FBB_CMD<6>
FBB_CMD<23>
FBB_CMD<16>
FBB_CMD<3>
FBB_CMD<12>
FBB_CMD<1>
FBB_CMD<11>
FBB_CLK1
FBB_CLK1*
SNN_FBB1_NC1
SNN_FBB1_NC2
FBB_CMD<15>
FBB_VDDA2
FBB_VDDA3
C105
.047UF
16V
10%
X7R
0402
COMMON
E11
B11
F11
C11
B10
C10
G10
F10
E10
D10
D11
E2
C2
G3
F2
B3
F3
B2
C3
E3
D3
D2
H11
K10
K11
H10
J11
J10
FBB_ZQ1
R91
240
5%
0603
COMMON
GND
K12
C109
.047UF
16V
10%
X7R
0402
COMMON
J12
U10
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
U13
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
U13
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
K1
J1
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
GND
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQ
DDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBVDDQ
R88
511
R1
1%
0402
COMMON
FBB_CMD<4>
FBB_CMD<6>
FBB_CMD<5>
FBB_CMD<13>
FBB_CMD<22>
FBB_CMD<24>
FBB_CMD<0>
FBB_CMD<2>
R584
0402
R582
0402
R568
0402
R560
0402
R596
0402
R592
0402
R594
0402
R589
0402
COMMON
R84
511
0402
1%
1%
1%
1%
1%
1%
1%
1%
FBVDDQ
1%
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
R1
FBVDDQ
9<>
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBB_VREF1
FBB_VREF3
GND
R87
1.3K
0402
COMMON
GND
C110
R2
.1UF
10%
X5R
0402
COMMON
R83
1.3K
R2
1%1% 10V 10V
0402
COMMON
GND
C106
.1UF
10%
X5R
0402
COMMON
Decoupling for FBB 0..31
FBVDDQ
C624
C568
C581
C575
C602
C592
C563
C598
4.7UF
6.3V
10%
X5R
0805
COMMON
C627
4.7UF
6.3V
10%
X5R
0805
COMMON
C567
4.7UF
6.3V
10%
X5R
0805
COMMON
C603
4.7UF
6.3V
10%
X5R
0805
COMMON
C548
.022UF
16V
10%
X7R
0402
COMMON
C555
.1UF
10V
10%
X5R
0402
COMMON
C612
.1UF
10V
10%
X5R
0402
COMMON
C597
.1UF
10V
10%
X5R
0402
COMMON
.1UF
10V
10%
X5R
0402
COMMON
C540
.1UF
10V
10%
X5R
0402
COMMON
C607
.022UF
16V
10%
X7R
0402
COMMON
C622
4.7UF
6.3V
10%
X5R
0805
COMMON
.01UF
16V
10% 10%
X7R
0402
COMMON
C582
4.7UF
6.3V
10%
X5R
0805
COMMON
C610
4.7UF
6.3V
10%
X5R
0805
COMMON
GND
4.7UF
6.3V
X5R
0805
COMMON
C570
.022UF
16V
10%
X7R
0402
COMMON
C601
.022UF
16V
10%
X7R
0402
COMMON
.022UF
16V
10%
X7R
0402
COMMON
C609
.01UF
16V
10%
X7R
0402
COMMON
C613
.022UF
16V
10%
X7R
0402
COMMON
.1UF
10V
10%
X5R
0402
COMMON
C577
.1UF
10V
10%
X5R
0402
COMMON
C628
4.7UF
6.3V
10%
X5R
0805
COMMON
.022UF
16V
10%
X7R
0402
COMMON
C580
4.7UF
6.3V
10%
X5R
0805
COMMON
C600
4.7UF
6.3V
10%
X5R
0805
COMMON
.01UF
25V
10%
X7R
0402
COMMON
C618
.022UF
16V
10%
X7R
0402
COMMON
C606
.1UF
10V
10%
X5R
0402
COMMON
9<>
C569
.01UF
25V
10%
X7R
0402
COMMON
C565
4.7UF
6.3V
10%
X5R
0805
COMMON
C619
.1UF
10V
10%
X5R
0402
COMMON
C543
4.7UF
6.3V
10%
X5R
0805
COMMON
C617
4.7UF
6.3V
10%
X5R
0805
COMMON
C623
.1UF
10V
10%
X5R
0402
COMMON
GND
GND
GND
www.vinafix.vn
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
FBB Partition
600-10455-0002-001
design
LFarasati
6 OF 24
9-FEB-2006
OUT
OUTINININOUTININ
OUT
MIRRORNONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS
RAS
BA0
BA1
A7
A8/AP
A3
A11
A2
A1
A0
A9
A6
A5
A4
A10
RAS
CAS
A0
CS
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
CKE
CLK
CLK
NC/RFU
NC/RFU
NC/RFU
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
OUT
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
ININININOUTININ
MIRRORNONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS
RAS
BA0
BA1
A7
A8/AP
A3
A11
A2
A1
A0
A9
A6
A5
A4
A10
RAS
CAS
A0
CS
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
CKE
CLK
CLK
NC/RFU
NC/RFU
NC/RFU
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
BIBIBI
BI
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
Page7: FBC Partition
STUFF CAP FOR G71, OR FOR G70
9>
GND
4>
9>
4>
9>
FBVDDQ
R648
0
5%
0402
NO STUFF
C806
.01UF
25V
10%
X7R
0402
COMMON
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
R647
40.2
0402
COMMON
FBC_CLK0_TERM
1%
R637
40.2
0402
COMMON
1%
4> 9>
CMD-Addr Mapping
144 136 ADDR
CMD15 CMD1 RAS*
CMD25 CMD10 CAS*
CMD9 CMD11 WE*
CMD8 CMD8 CS0*
CMD7 CMD7 BA2
CMD1 CMD19 A<0>
CMD3 CMD25 A<1>
CMD2 CMD22 0A<2>
CMD0 CMD24 0A<3>
CMD24 CMD0 0A<4>
CMD22 CMD2 0A<5>
CMD13 CMD4 1A<2>
CMD4 CMD6 1A<3>
CMD5 CMD5 1A<4>
CMD6 CMD13 1A<5>
CMD21 CMD21 A<6>
CMD23 CMD16 A<7>
CMD19 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD16 CMD9 A<11>
CMD10 CMD12 BA0
CMD18 CMD3 BA1
CMD11 CMD18 CKE
CMD12 CMD15 RST
FBC_CMD<26..0>
9<>
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
9<>
9>
9<
9>
4<>
4>
4<
4>
FBVDDQ
LB22
LB21
0
CHANGED0603
0
CHANGED0603
FBCD<63..0>
FBCDQM<7..0>
FBCDQS_RN<7..0>
FBCDQS_WP<7..0>
9<>
9<>
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
U7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
15
FBC_CMD<1>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<8>
FBC_CMD<19>
FBC_CMD<25>
FBC_CMD<22>
FBC_CMD<24>
FBC_CMD<0>
FBC_CMD<2>
FBC_CMD<21>
FBC_CMD<16>
FBC_CMD<23>
FBC_CMD<20>
FBC_CMD<17>
FBC_CMD<9>
FBC_CMD<12>
FBC_CMD<3>
FBC_CMD<7>
FBC_CMD<18>
FBC_CLK0
FBC_CLK0*
SNN_FBC0_NC1
SNN_FBC0_NC2
GND
FBC_CMD<15>
A9
A4
FBC_ZQ0
GND
R614
10K
5%
0402
COMMON
GND
FBC_VDDA0
FBC_VDDA1
C87
.047UF
16V
10%
X7R
0402
COMMON
R618
10K
5%
0402
COMMON
GND
GND
C88
.047UF
16V
10%
X7R
0402
COMMON
R64
240
5%
0603
COMMON
K12
J12
K1
J1
GND
FBCD<0>
0
FBCD<1>
1
FBCD<2>
2
FBCD<3>
3
FBCD<4>
4
FBCDQM<0>
FBCDQM<1>
FBCDQM<2>
FBCDQM<3>
FBCDQM<4>
FBCDQM<5>
FBCDQM<6>
FBCDQM<7>
FBCDQS_RN<0>
FBCDQS_RN<1>
FBCDQS_RN<2>
FBCDQS_RN<3>
FBCDQS_RN<4>
FBCDQS_RN<5>
FBCDQS_RN<6>
FBCDQS_RN<7>
FBCDQS_WP<0>
FBCDQS_WP<1>
FBCDQS_WP<2>
FBCDQS_WP<3>
FBCDQS_WP<4>
FBCDQS_WP<5>
FBCDQS_WP<6>
FBCDQS_WP<7>
5
6
7
32
33
34
35
36
37
38
39
FBCD<5>
FBCD<6>
FBCD<7>
FBCDQM<0>
FBCDQS_RN<0>
FBCDQS_WP<0>
FBCD<32>
FBCD<33>
FBCD<34>
FBCD<35>
FBCD<36>
FBCD<37>
FBCD<38>
FBCD<39>
FBCDQM<4>
FBCDQS_RN<4>
FBCDQS_WP<4>
U7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
B11
C11
F11
G10
C10
E11
F10
B10
E10
D10
D11
U9
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
M2
R3
T3
M3
L3
N2
R2
T2
N3
P3
P2
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
VREF = FBVDDQ * R2/(R1 + R2)
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
GND
GND
FBC_VREF0
FBC_VREF2
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.18K/(511K + 1.18K)
FBCD<8>
FBCD<9>
FBCD<10>
FBCD<11>
FBCD<12>
FBCD<13>
FBCD<14>
FBCD<15>
FBCDQM<1>
FBCDQS_RN<1>
FBCDQS_WP<1>
FBCD<40>
FBCD<41>
FBCD<42>
FBCD<43>
FBCD<44>
FBCD<45> G10
FBCD<46>
FBCD<47>
FBCDQM<5>
FBCDQS_RN<5>
FBCDQS_WP<5>
STUFF CAP FOR G71, OR FOR G70
FBVDDQ
9>
C656
.01UF
25V
10%
X7R
FBC_CLK1_TERM
0402
COMMON
R601
GND
4>
9>
4> 9>
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
40.2
1%
0402
COMMON
FBVDDQ
R66
511
R1
1%
0402
COMMON
R68
1.3K
0402
COMMON
R2
1%
C86
.1UF
10V
10%
X5R
0402
COMMON
GND
U7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
M2
T2
R2
N2
R3
T3
L3
M3
N3
P3
P2
U9
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
B10
E11
F11
C11
B11
F10
C10
E10
D10
D11
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBCD<16>
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>
FBCDQM<2>
FBCDQS_RN<2>
FBCDQS_WP<2>
FBCD<48>
FBCD<49>
FBCD<50>
FBCD<51>
FBCD<53>
FBCD<54>
FBCD<55>
FBCDQM<6>
FBCDQS_RN<6>
R602
0
5%
0402
NO STUFF
9<>
COMMON
1.3K
COMMON
FBVDDQ
R65
511
1%
0402
R67
1%
0402
R605
40.2
1%
0402
COMMON
GND
CMD-Addr Mapping
144 136 ADDR
CMD15 CMD1 RAS*
CMD25 CMD10 CAS*
CMD9 CMD11 WE*
CMD8 CMD8 CS0*
CMD7 CMD7 BA2
CMD1 CMD19 A<0>
CMD3 CMD25 A<1>
CMD2 CMD22 0A<2>
CMD0 CMD24 0A<3>
CMD24 CMD0 0A<4>
CMD22 CMD2 0A<5>
CMD13 CMD4 1A<2>
CMD4 CMD6 1A<3>
CMD5 CMD5 1A<4>
CMD6 CMD13 1A<5>
CMD21 CMD21 A<6>
CMD23 CMD16 A<7>
CMD19 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD16 CMD9 A<11>
CMD10 CMD12 BA0
CMD18 CMD3 BA1
CMD11 CMD18 CKE
CMD12 CMD15 RST
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
FBVDDQ
LB25
LB24
R1
C85
U7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
C2
G3
F3
E2
F2
B2
B3
C3
E3
D3
D2
U9
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
L10
M11
R11
T11
R10FBCD<52>
M10
N11
T10
N10
P10
P11FBCDQS_WP<6>
.1UF
10V
10%
X5R
0402
COMMON
R2
U9
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
FBVDDQ
7
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
12
1
11
GND
15
FBC_CMD<7>
FBC_CMD<8>
FBC_CMD<18>
FBC_CMD<10>
FBC_CMD<5>
FBC_CMD<13>
FBC_CMD<21>
FBC_CMD<20>
FBC_CMD<19>
FBC_CMD<25>
FBC_CMD<4>
FBC_CMD<9>
FBC_CMD<17>
FBC_CMD<6>
FBC_CMD<23>
FBC_CMD<16>
FBC_CMD<3>
FBC_CMD<12>
FBC_CMD<1>
FBC_CMD<11>
FBC_CLK1
FBC_CLK1*
SNN_FBC1_NC1
SNN_FBC1_NC2
FBC_CMD<15>
A9
FBC_VDDA2
FBC_VDDA3
FBC_ZQ1 A4
R73
240
5%
0603
COMMON
GND
C93
.047UF
16V
10%
X7R
0402
COMMON
K12
J12
K1
J1
9<>
9<>
9<>
0
CHANGED0603
0
CHANGED0603
C94
.047UF
16V
10%
X7R
0402
COMMON
9<>
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBC_VREF1
FBC_VREF3
GND
GND
R72
511
0402
COMMON
R70
1.3K
COMMON
FBVDDQ
1%
1%
GND
FBC_CMD<4>
FBC_CMD<6>
FBC_CMD<5>
FBC_CMD<13>
FBC_CMD<22>
FBC_CMD<24>
FBC_CMD<0>
FBC_CMD<2>
R1
R611
0402
R610
0402
R604
0402
R606
0402
R635
0402
R629
0402
R631
0402
R639
0402
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
R71
511
0402
COMMON
9<>
C96
R2
.1UF
10V
X5R
0402
COMMON
R69
1.3K
04020402
COMMON
FBVDDQ
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511K + 1.18K)
FBVDDQ
R1
1%
C95
R2
1%
.1UF
10V
10%10%
X5R
0402
COMMON
GND
9<>
GND
Decoupling for FBC 0..31
FBVDDQ
C697
4.7UF
6.3V
10%
X5R
0805
COMMON
C831
4.7UF
6.3V
10%
X5R
0805
COMMON
C779
4.7UF
6.3V
10%
X5R
0805
COMMON
C694
4.7UF
6.3V
10%
X5R
0805
COMMON
C640
.01UF
25V
10%
X7R
0402
COMMON
C644
.022UF
16V
10%
X7R
0402
COMMON
C833
.1UF
10V
10%
X5R
0402
COMMON
C818
.1UF
10V
10%
X5R
0402
COMMON
C687
.1UF
10V
10%
X5R X7R
0402
COMMON
C650
.1UF
10V
10%
X5R
0402
COMMON
C842
4.7UF
6.3V
10%
X5R
0805
COMMON
C814
.1UF
10V
10%
X5R
0402
COMMON
GND
C674
.01UF
25V
10%
0402
COMMON
C639
.1UF
10V
10%
X5R
0402
COMMON
C815
.022UF
16V
10%
X7R
0402
COMMON
C646
.022UF
16V
10%
X7R
0402
COMMON
C651
4.7UF
6.3V
10%
X5R
0805
COMMON
C836
4.7UF
6.3V
10%
X5R
0805
COMMON
C643
.022UF
16V
10%
X7R
0402
COMMON
C647
4.7UF
6.3V
10%
X5R
0805
COMMON
C758
4.7UF
6.3V
10%
X5R
0805
COMMON
C638
4.7UF
6.3V
10%
X5R
0805
COMMON
C778
.01UF
25V
10%
X7R
0402
COMMON
C791
.1UF
10V
10%
X5R
0402
COMMON
C703
.022UF
16V
10%
X7R X5R
0402
COMMON
C636
4.7UF
6.3V
10%
X5R
0805
COMMON
C686
4.7UF
6.3V
10%
X5R
0805
COMMON
C649
.1UF
10V
10%
0402
COMMON
C770
.1UF
10V
10%
X5R
0402
COMMON
C789
.022UF
16V
10%
X7R
0402
COMMON
C641
.1UF
10V
10%
0402
COMMON
C777
.022UF
16V
10%
X7R
0402
COMMON
C782
.022UF
16V
10%
X7R
0402
COMMON
C830
.01UF
25V
10%
X7RX5R
0402
COMMON
C822
4.7UF
6.3V
10%
X5R
0805
COMMON
C785
4.7UF
6.3V
10%
X5R
0805
COMMON
GND
GND
GND
24
25
26
27
28
29
30
31
56
57
58
59
60
61
62
63
FBCD<24>
FBCD<25>
FBCD<26>
FBCD<27>
FBCD<28>
FBCD<29>
FBCD<30>
FBCD<31>
FBCDQM<3>
FBCDQS_RN<3>
FBCDQS_WP<3>
FBCD<56>
FBCD<57>
FBCD<58>
FBCD<59>
FBCD<60>
FBCD<61>
FBCD<62>
FBCD<63>
FBCDQM<7>
FBCDQS_RN<7>
FBCDQS_WP<7>
L10
M10
N11
R10
T11
R11
M11
T10
N10
P10
P11
E2
B2
G3
C2
C3
F2
B3
F3
E3
D3
D2
U7
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
U9
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
www.vinafix.vn
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
FBC Partition
600-10455-0002-001
design
LFarasati
7 OF 24
9-FEB-2006
OUT
OUTINININOUTININ
OUT
MIRRORNONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS
RAS
BA0
BA1
A7
A8/AP
A3
A11
A2
A1
A0
A9
A6
A5
A4
A10
RAS
CAS
A0
CS
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
CKE
CLK
CLK
NC/RFU
NC/RFU
NC/RFU
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
OUT
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
ININININOUTININ
MIRRORNONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS
RAS
BA0
BA1
A7
A8/AP
A3
A11
A2
A1
A0
A9
A6
A5
A4
A10
RAS
CAS
A0
CS
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
CKE
CLK
CLK
NC/RFU
NC/RFU
NC/RFU
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ4
DQ3
DQ2
DQ1
DQ5
DQ6
DQ7
DQM
BIBIBI
BI
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
Page8: FBD Partition
STUFF CAP FOR G71, 0R FOR G70
9>
9>
GND
4>
4> 9>
FBVDDQ
R719
0
5%
0402
NO STUFF
C897
.01UF
25V
10%
X7R
0402
COMMON
FBD_CLK0_TERM
R720
R723
40.2
40.2
0402
COMMON
1%
1%
0402
COMMON
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
9> 4>
CMD-Addr Mapping
144 136 ADDR
CMD15 CMD1 RAS*
CMD25 CMD10 CAS*
CMD9 CMD11 WE*
CMD8 CMD8 CS0*
CMD7 CMD7 BA2
CMD1 CMD19 A<0>
CMD3 CMD25 A<1>
CMD2 CMD22 0A<2>
CMD0 CMD24 0A<3>
CMD24 CMD0 0A<4>
CMD22 CMD2 0A<5>
CMD13 CMD4 1A<2>
CMD4 CMD6 1A<3>
CMD5 CMD5 1A<4>
CMD6 CMD13 1A<5>
CMD21 CMD21 A<6>
CMD23 CMD16 A<7>
CMD19 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD16 CMD9 A<11>
CMD10 CMD12 BA0
CMD18 CMD3 BA1
CMD11 CMD18 CKE
CMD12 CMD15 RST
FBD_CMD<26..0>
9<>
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
9<>
9>
9<
9>
4<>
4>
4<
4>
FBVDDQ
LB16
LB12
CHANGED
0603
CHANGED
0603
FBDD<63..0>
FBDDQM<7..0>
FBDDQS_RN<7..0>
FBDDQS_WP<7..0>
0
0
9<>
9<>
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
U2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
15
FBD_CMD<1>
FBD_CMD<10>
FBD_CMD<11>
FBD_CMD<8>
FBD_CMD<19>
FBD_CMD<25>
FBD_CMD<22>
FBD_CMD<24>
FBD_CMD<0>
FBD_CMD<2>
FBD_CMD<21>
FBD_CMD<16>
FBD_CMD<23>
FBD_CMD<20>
FBD_CMD<17>
FBD_CMD<9>
FBD_CMD<12>
FBD_CMD<3>
FBD_CMD<7>
FBD_CMD<18>
FBD_CLK0
FBD_CLK0*
SNN_FBD0_NC1
SNN_FBD0_NC2
GND
FBD_CMD<15>
A9
FBD_ZQ0 A4
GND
R710
10K
5%
0402
COMMON
GND
FBD_VDDA0
FBD_VDDA1
C29
.047UF
16V
10%
X7R
0402
COMMON
R711
10K
5%
0402
COMMON
GNDGND
C51
.047UF
16V
10%
X7R
0402
COMMON
R21
240
5%
0603
COMMON
K12
J12
K1
J1
GND
C11FBDD<0>
E11
F11
G10
B11
F10
C10
B10
E10
D10
D11
L10
R10
T10
N11
T11
M11
R11
N10
P10
P11
FBDDQM<0>
FBDDQM<1>
FBDDQM<2>
FBDDQM<3>
FBDDQM<4>
FBDDQM<5>
FBDDQM<6>
FBDDQM<7>
FBDDQS_RN<0>
FBDDQS_RN<1>
FBDDQS_RN<2>
FBDDQS_RN<3>
FBDDQS_RN<4>
FBDDQS_RN<5>
FBDDQS_RN<6>
FBDDQS_RN<7>
FBDDQS_WP<0>
FBDDQS_WP<1>
FBDDQS_WP<2>
FBDDQS_WP<3>
FBDDQS_WP<4>
FBDDQS_WP<5>
FBDDQS_WP<6>
FBDDQS_WP<7>
0
FBDD<1>
1
FBDD<2>
2
FBDD<3>
3
FBDD<4>
4
FBDD<5>
5
FBDD<6>
6
FBDD<7>
7
FBDDQM<0>
FBDDQS_RN<0>
FBDDQS_WP<0>
FBDD<32>
32
FBDD<33>
33
FBDD<34>
34
FBDD<35>
35
FBDD<36>
36
FBDD<37> M10
37
FBDD<38>
38
FBDD<39>
39
FBDDQM<4>
FBDDQS_RN<4>
FBDDQS_WP<4>
U2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
U4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
GND
GND
FBD_VREF0
FBD_VREF2
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQ
DDR3:
1.26V = 1.8V * 1.18K/(511 + 1.18K)
FBDD<8>
FBDD<9>
FBDD<10>
FBDD<11>
FBDD<12>
FBDD<13>
FBDD<14>
FBDD<15>
FBDDQM<1>
FBDDQS_RN<1>
FBDDQS_WP<1>
FBDD<40>
FBDD<41>
FBDD<42>
FBDD<43>
FBDD<44>
FBDD<45>
FBDD<46>
FBDD<47>
FBDDQM<5>
FBDDQS_RN<5>
FBDDQS_WP<5>
STUFF CAP FOR G71, 0R FOR G70
FBVDDQ
R702
0
5%
0402
9>
C866
.01UF
25V
10%
X7R
0402
COMMON
GND
4>
9>
4>
9>
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
NO STUFF
FBD_CLK1_TERM
R700
40.2
1%
0402
COMMON
FBVDDQ
R24
511
R1
1%
0402
COMMON
R26
1.3K
0402
COMMON
R2
1%
C50
.1UF
10V
10%
X5R
0402
COMMON
GND
U2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
N2
T2
R2
R3
T3
M2
L3
M3
N3
P3
P2
U4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
C10
F11
E11
B11
C11
G10
F10
B10
E10
D10
D11
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBDD<16>
FBDD<17>
FBDD<18>
FBDD<19>
FBDD<20>
FBDD<21>
FBDD<22>
FBDD<23>
FBDDQM<2>
FBDDQS_RN<2>
FBDDQS_WP<2>
FBDD<48>
FBDD<49>
FBDD<50>
FBDD<51>
FBDD<52>
FBDD<53>
FBDD<54>
FBDD<55>
FBDDQM<6>
FBDDQS_RN<6>
FBDDQS_WP<6>
9<>
R697
40.2
1%
0402
COMMON
R18
511
0402
COMMON
R20
1.3K
0402
COMMON
FBVDDQ
1%
1%
GND
CMD-Addr Mapping
144 136 ADDR
CMD15 CMD1 RAS*
CMD25 CMD10 CAS*
CMD9 CMD11 WE*
CMD8 CMD8 CS0*
CMD7 CMD7 BA2
CMD1 CMD19 A<0>
CMD3 CMD25 A<1>
CMD2 CMD22 0A<2>
CMD0 CMD24 0A<3>
CMD24 CMD0 0A<4>
CMD22 CMD2 0A<5>
CMD13 CMD4 1A<2>
CMD4 CMD6 1A<3>
CMD5 CMD5 1A<4>
CMD6 CMD13 1A<5>
CMD21 CMD21 A<6>
CMD23 CMD16 A<7>
CMD19 CMD23 A<8>
CMD20 CMD20 A<9>
CMD17 CMD17 A<10>
CMD16 CMD9 A<11>
CMD10 CMD12 BA0
CMD18 CMD3 BA1
CMD11 CMD18 CKE
CMD12 CMD15 RST
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
FBVDDQ
LB17
0603
LB19
0603
R1
C23
U2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
E2
F3
C3
F2
G3
B2
B3
C2
E3
D3
D2
U4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
R3
T3
R2
T2
N2
L3
M3
M2
N3
P3
P2
.1UF
10V
10%
X5R
0402
COMMON
R2
0
CHANGED
0
CHANGED
9<>
9<>
9<>
24
25
26
27
28
29
30
31
56
57
58
59
60
61
62
63
FBVDDQ
9<>
FBDD<24>
FBDD<25>
FBDD<26>
FBDD<27>
FBDD<28>
FBDD<29>
FBDD<30>
FBDD<31>
FBDDQM<3>
FBDDQS_RN<3>
FBDDQS_WP<3>
FBDD<56>
FBDD<57>
FBDD<58>
FBDD<59>
FBDD<60>
FBDD<61>
FBDD<62>
FBDD<63>
FBDDQM<7>
FBDDQS_RN<7>
FBDDQS_WP<7>
GND
7
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
12
1
11
GND
15
FBD_CMD<7>
FBD_CMD<8>
FBD_CMD<18>
FBD_CMD<10>
FBD_CMD<5>
FBD_CMD<13>
FBD_CMD<21>
FBD_CMD<20>
FBD_CMD<19>
FBD_CMD<25>
FBD_CMD<4>
FBD_CMD<9>
FBD_CMD<17>
FBD_CMD<6>
FBD_CMD<23>
FBD_CMD<16>
FBD_CMD<3>
FBD_CMD<12>
FBD_CMD<1>
FBD_CMD<11>
FBD_CLK1
FBD_CLK1*
SNN_FBD1_NC1
SNN_FBD1_NC2
FBD_CMD<15>
FBD_VDDA2
FBD_VDDA3
C64
.047UF
16V
10%
X7R
0402
COMMON
M10
T10
L10
M11
T11
R11
N11
R10
N10
P10
P11
B2
C3
C2
B3
E2
G3
F2
F3
E3
D3
D2
H11
K10
K11
H10
J11
J10
FBD_ZQ1 A4
R40
240
5%
0603
COMMON
GND
K12
C55
.047UF
16V
10%
X7R
0402
COMMON
J12
U2
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
U4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
U4
DDR3BGA136
PACK_TYPE=BGA136
VERSION=BGA136
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
K1
J1
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
GND
R31
511
0402
COMMON
FBVDDQ
1%
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
R1
FBD_CMD<4>
FBD_CMD<6>
FBD_CMD<5>
FBD_CMD<13>
FBD_CMD<22>
FBD_CMD<24>
FBD_CMD<0>
FBD_CMD<2>
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.18K/(511 + 1.18K)
R701
0402
R703
0402
R706
0402
R709
0402
R717
0402
R715
0402
R716
0402
R721
0402
FBVDDQ
R44
511
1%
0402
COMMON
FBVDDQ
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
R1
9<>
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBD_VREF1
FBD_VREF3
GND
R30
1.3K
R2
1%
0402 0402
COMMON
C56
.1UF
10V
10% 10%
X5R
0402
COMMON
GND
R43
1.3K
COMMON
R2
1%
GND
C71
.1UF
10V
X5R
0402
COMMON
Decoupling for FBD 0..31
FBVDDQ
C864
C855
C854
C863
C874
C867
C859
C876
4.7UF
6.3V
10%
X5R X5R
0805
COMMON
C888
4.7UF
6.3V
10%
X5R
0805
COMMON
C891
4.7UF
6.3V
10%
X5R
0805
COMMON
C871
4.7UF
6.3V
10%
X5R
0805
COMMON
C862
.1UF
10V
10%
0402
COMMON
C869
.022UF
16V
10%
X7R
0402
COMMON
C908
4.7UF
6.3V
10%
X5R
0805
COMMON
C896
.022UF
16V
10%
X7R
0402
COMMON
.1UF
10V
10%
X5R
0402
COMMON
C870
.1UF
10V
10%
X5R
0402
COMMON
C907
.1UF
10V
10%
X5R
0402
COMMON
C884
4.7UF
6.3V
10%
X5R
0805
COMMON
GND
.01UF
25V
10%
X7R
0402
COMMON
C872
.1UF
10V
10%
X5R
0402
COMMON
C883
.022UF
16V
10%
X7R
0402
COMMON
.022UF
16V
10%
X7R
0402
COMMON
C858
4.7UF
6.3V
10%
X5R
0805
COMMON
C865
4.7UF
6.3V
10%
X5R
0805
COMMON
.022UF
16V
10%
X7R X5R
0402
COMMON
C878
.01UF
25V
10%
X7R
0402
COMMON
C873
4.7UF
6.3V
10%
X5R
0805
COMMON
4.7UF
6.3V
10%
0805
COMMON
C851
4.7UF
6.3V
10%
X5R
0805
COMMON
C880
4.7UF
6.3V
10%
X5R
0805
COMMON
.022UF
16V
10%
X7R
0402
COMMON
C890
.1UF
10V
10%
X5R
0402
COMMON
C879
.022UF
16V
10%
X7R
0402
COMMON
.1UF
10V
10%
X5R
0402
COMMON
C903
4.7UF
6.3V
10%
X5R
0805
COMMON
C902
.1UF
10V
10%
X5R
0402
COMMON
9<>
C894
.01UF
25V
10%
X7R
0402
COMMON
C905
4.7UF
6.3V
10%
X5R
0805
COMMON
C901
.1UF
10V
10%
X5R
0402
COMMON
C853
.01UF
25V
10%
X7R
0402
COMMON
C904
.022UF
16V
10%
X7R
0402
COMMON
C887
.1UF
10V
10%
X5R
0402
COMMON
GND
GND
GND
www.vinafix.vn
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
FBD Partition
600-10455-0002-001
design
LFarasati
8 OF 24
9-FEB-2006
Page9: FrameBuffer Net Properties
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI
OUT
OUTINOUT
OUT
OUT
OUT
OUT
OUT
OUTBIOUTINOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIOUTINOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIIN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NET RULES for FrameBuffer A/B
5<>
5<>
5<>
5<>
5<
5<
5<
5<
5<
3<>
3>
3>
5>
3>
3>
5>
3>
3>
3<
3>
NET
FBA_CLK0
FBA_CLK0*
FBA_CLK0_TERM
FBA_CLK1
FBA_CLK1*
FBA_CLK1_TERM
FBA_CMD<26..0>
FBADQS_WP<7..0>
FBADQS_RN<7..0>
FBADQM<7..0>
FBAD<63..0>
NET
6<
3>
6<
3>
6>
6<
3>
6<
3>
6<>
6<>
6<>
6<>
6<
3<>
6>
3>
3>
3<
3>
FBB_CLK0
FBB_CLK0*
FBB_CLK0_TERM
FBB_CLK1
FBB_CLK1*
FBB_CLK1_TERM 1
FBB_CMD<26..0>
FBBDQS_WP<7..0>
FBBDQS_RN<7..0>
FBBDQM<7..0>
FBBD<63..0>
NET
3<>
3<>
3<>
3<>
3<>
3<>
3<>
3<>
FBCAL0_PD_VDDQ
FBCAL0_PU_GND
FBCAL0_TERM_GND
FBCAL1_PD_VDDQ
FBCAL1_PU_GND
FBCAL1_TERM_GND
FBA_DEBUG
FBB_DEBUG
NET VOLTAGE
3<>
3<>
3<>
3<>
5>
5>
5>
5>
5<
5<
5<
5<
5<
5<
6>
6>
6>
6>
6<
6<
6<
6<
6<
6<
FBAB_PLLVDD
FBAB_PLLAVDD
FBA_VREF0
FBA_VREF1
FBA_VREF2
FBA_VREF3
FBA_ZQ0
FBA_ZQ1
FBA_VDDA0
FBA_VDDA1
FBA_VDDA2
FBA_VDDA3
FBB_VREF0
FBB_VREF1
FBB_VREF2
FBB_VREF3
FBB_ZQ0
FBB_ZQ1
FBB_VDDA0
FBB_VDDA1
FBB_VDDA2
FBB_VDDA3
FB_VREF1
FB_VREF2
NV_CRITICAL
1
1
1
1
1
1
1
1
1
1
1
NV_CRITICAL
1
1
1
1
1
1
1
1
1
1
NV_CRITICAL
1
1
1
1
1
1
1
1
3.3V
1.2V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.8V
1.8V
1.8V
1.8V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.8V
1.8V
1.8V
1.8V
1.26V
1.26V
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
40OHM
80DIFF
80DIFF FBA_CLK1
40OHM
50OHM
50OHM
50OHM
50OHM
50OHM
FBA_CLK0
FBA_CLK0
FBA_CLK1
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
40OHM
80DIFF
80DIFF
40OHM
50OHM
50OHM
50OHM
50OHM
50OHM
NV_IMPEDANCE
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
DIFFPAIR
MAX_CURRENT MIN_WIDTH
0.04A
0.12A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL0.02A
12MIL0.02A
NET RULES for FrameBuffer C/D
7<>
8<>
7<
7<
7<
7<
7<
7<>
7<>
7<>
8<
8<
8<
8<
8<
8<>
8<>
8<>
4<>
4<>
4<>
4<>
4<>
4<>
7>
7>
7>
7>
7<
7<
7<
7<
7<
7<
8>
8>
8>
8>
8<
8<
8<
8<
8<
8<
4>
4>
7>
4>
4>
7>
4>
4>
4<
4>
4>
4>
8>
4>
4>
8>
4>
4>
4<
4>
NET
FBC_CLK0
FBC_CLK0*
FBC_CLK0_TERM
FBC_CLK1
FBC_CLK1*
FBC_CLK1_TERM
FBC_CMD<26..0>
FBCDQS_WP<7..0>
FBCDQS_RN<7..0>
FBCDQM<7..0>
FBCD<63..0>
NET
FBD_CLK0
FBD_CLK0*
FBD_CLK0_TERM
FBD_CLK1
FBD_CLK1*
FBD_CLK1_TERM 1
FBD_CMD<26..0>
FBDDQS_WP<7..0>
FBDDQS_RN<7..0>
FBDDQM<7..0>
FBDD<63..0>
FBC_DEBUG
FBD_DEBUG
NET VOLTAGE
FBCD_PLLVDD
FBCD_PLLAVDD
FBC_VREF0
FBC_VREF1
FBC_VREF2
FBC_VREF3
FBC_ZQ0
FBC_ZQ1
FBC_VDDA0
FBC_VDDA1
FBC_VDDA2
FBC_VDDA3
FBD_VREF0
FBD_VREF1
FBD_VREF2
FBD_VREF3
FBD_ZQ0
FBD_ZQ1
FBD_VDDA0
FBD_VDDA1
FBD_VDDA2
FBD_VDDA3
NV_CRITICAL
1
1
1
1
1
1
1
1
1
1
1
NV_CRITICAL
1
1
1
1
1
1
1
1
1
1
1
1
3.3V
1.2V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.8V
1.8V
1.8V
1.8V
1.26V
1.26V
1.26V
1.26V
1.26V
1.26V
1.8V
1.8V
1.8V
1.8V
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
40OHM
80DIFF
80DIFF
40OHM
50OHM
50OHM
50OHM
50OHM
50OHM
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
40OHM
80DIFF
80DIFF
40OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
MAX_CURRENT MIN_WIDTH
0.04A
0.12A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
FrameBuffer Net Properties
www.vinafix.vn
600-10455-0002-001
design
LFarasati
9 OF 24
9-FEB-2006
Page10: DACA Interface
OUT
OUT
OUT
OUT
OUT
OUT
OUT
11
15
6
10
1
5
SDA
ID0
SCL
HSYNC
VSYNC
GND_B
GND-G
GND-R
R
G
5V
ID2
GND
GND
B
8/24 DACA
DACA_VSYNC
DACA_HSYNC
I2CA_SCL
I2CA_SDA
DACA_RED
DACA_IDUMP
DACA_GREEN
DACA_BLUE
DACA_VDD
DACA_VREF
DACA_RSET
INININININININININININININININININININININ
IN
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
COMBINED DAC_VDD FOR DACS A/B/C
F3V3
220R@100MHz
LB506
COMMONBEAD_0603
C825
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
DAC_VDD
C810
.1UF
10V
10%
0402
COMMON
GND
DACA NET RULES
NET
DACA_RED
DACA_GREEN
DACA_BLUE
12<
12<
12<
10>
10>
10>
DACA_RED_DVI
DACA_GREEN_DVI
DACA_BLUE_DVI
DACA_HSYNC
DACA_VSYNC
DACA_HS_BUF
DACA_VS_BUF
DACA_HS_BUF_R
DACA_VS_BUF_R
10>
12<
10>
12<
10>
12<
10>
12<
DAC_VDD
DACA_HS_DVI
DACA_VS_DVI
DACA_I2C_SCL
DACA_I2C_SDA
DACA_I2C_SCL_R
DACA_I2C_SDA_R
DACA_I2C_SCL_DVI
DACA_I2C_SDA_DVI
DACA_VREF
DACA_RSET
DAC_VDD
NV_CRITICAL
1
1
1
1
1
1
2
2
2
2
2
2
2
2
VOLTAGENET
3.3V
DAC_VDD
C824
4.7UF
6.3V
10%
X5R
0603
COMMON
C823
4.7UF
6.3V
10%
X5R
0603
COMMON
U8
G71-N-A2
BGA1148
CHANGED
AK13
C757
.01UF
16V
10%
0402
COMMON
C751
.1UF
10V
10%
X5RX7RX5R
0402
COMMON
DACA_VREF
DACA_RSET
R623
1.21K
1%
0402
CHANGED
R625
137
1%
0402
COMMON
AK14
AH11
ECSetNV_IMPEDANCE
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
DAC_RGB_CSET
DAC_RGB_CSET
DAC_RGB_CSET
DAC_RGB_CSET
DAC_RGB_CSET
DAC_RGB_CSET
MIN_WIDTHMAX_CURRENT
0.25A
16MIL
T9
AJ11
AF14
AH13
AJ14
AH12
AJ13
GND
DACA_I2C_SCL
DACA_I2C_SDAU8
DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_GREEN
DACA_BLUE
5V
GND
5V
GND
C16
4.7UF
6.3V
10%
X5R
0603
COMMON
U507
74ACT08
8
74ACT_SO
COMMON
U507
74ACT08
6
74ACT_SO
COMMON
DACA_HS_BUF
DACA_VS_BUF
10
9
5V
C925
.1UF
10V
10%
X5R
0402
COMMON
GND
4
5
R616
154
1%
0402
CHANGED
GND
R615
143
1%
0402
CHANGED
GND
R617
150
1%
0402
COMMON
GND
5V
GND
Place near Sync Diode
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
DACA Interface
www.vinafix.vn
33
R13
COMMON
0402
5%
33
R14
COMMON
0402
5%
sync_buf bypass
R746
0402
5%
R747
0402
5%
sync_buf bypass
R727
0402
5%
R728
0402
5%
DACA_I2C_SCL_R
DACA_I2C_SDA_R
33
NO STUFF
DACA_HS_BUF_R
33
COMMON
33
NO STUFF
DACA_VS_BUF_R
33
COMMON
GND
GND
GND GND
R730
150
1%
0402
COMMON
R743
150
1%
0402
COMMON
150
1%
0402
COMMON
6
1
7
2
8
3
9
4
10
5
12< 10<
10< 12<
10< 12<
10< 12<
10>
10>
10<
10>
J2
CON_DSUB15HD
VGA_SLIM_DVIMTG
VGA_SLIM_DVIMTG
NO STUFF
12< 10<
12<
12<
10>
10>
12<
11
12
13
14
15
10<
10< 12< 10<
10>
10<
12<
SNN_DACA_ID0
180R@100MHz
LB5
CHANGED
BEAD_0603
1
R7
2.2K
5V
0402
COMMON5%2
1
R8
2.2K
0402
COMMON5%2
180R@100MHz
LB6
CHANGED
BEAD_0603
27nH
L4
COMMON
0402
5V
2
D4
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
5V
2
D1
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
C910
22PF
50V
5%
C0G
0402
NO STUFF
GND
C921
22PF
50V
5%
C0G
0402
NO STUFF
GND
C909R729
22PF
50V
5%
C0G
0402
NO STUFF
L3
0402
L502
L511
L501
COMMON
27nH
COMMON0402
COMMON0402
COMMON0402
27nH
27nH
27nH
GND
GND
GND
GND
GND
GND
GND
C7
22PF
50V
5%
C0G
0603
COMMON
C8
22PF
50V
5%
C0G
0603
COMMON
C10
27PF
50V
5%
C0G
0603
COMMON
C9
27PF
50V
5%
C0G
0603
COMMON
C915
4.7PF
50V
+/-0.25PF
COG
0402
COMMON
C936
4.7PF
50V
+/-0.25PF
COG
0402
COMMON
C914
4.7PF
50V
+/-0.25PF
COG
0402
COMMON
DACA_I2C_SCL_DVI
DACA_I2C_SDA_DVI
DACA_HS_DVI
DACA_VS_DVI
DACA_RED_DVI
DACA_GREEN_DVI
DACA_BLUE_DVI
DACA_RED_DVI
DACA_GREEN_DVI
DACA_BLUE_DVI
DDC_5V
SNN_DACA_ID2
GND
600-10455-0002-001
design
LFarasati
10 OF 24
9-FEB-2006
Page11: DACC Interface
OUT
OUT
OUT
OUT
OUT
OUT
OUT
11
15
6
10
1
5
SDA
ID0
SCL
HSYNC
VSYNC
GND_B
GND-G
GND-R
R
G
5V
ID2
GND
GND
B
10/24 DACC
DACC_VSYNC
DACC_HSYNC
I2CB_SCL
I2CB_SDA
DACC_IDUMP
DACC_BLUE
DACC_GREEN
DACC_RED
DACC_VDD
DACC_VREF
DACC_RSET
INININININININININININININININININININININ
IN
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
R731
0402
R12
0402
5%
5%
33
COMMON
33
COMMON
DACC_I2C_SCL_R
DACC_I2C_SDA_R
LB520
BEAD_0603
1
R739
2.2K
5V
0402
COMMON5%2
1
R11
2.2K
5%
0402
COMMON
2
BEAD_0603
180R@100MHz
LB4
CHANGED
180R@100MHz
CHANGED
C926
22PF
50V
5%
C0G
0603
COMMON
GND
C4
22PF
50V
5%
C0G
0603
COMMON
GND
DACC_I2C_SCL_DVI
DACC_I2C_SDA_DVI
12< 11<
11< 12<
sync_buf bypass
33
R744
NO STUFF
0402
5V
13
12
COMMON DAC_VDD FOR DAC A/B/C
DAC_VDD
DACC_VREF
DACC_RSET
R638
C811
.1UF
10V
10%
0402
COMMON
GND
C807
.01UF
16V
10%
0402
COMMON
C784
.1UF
10V
10%
X5RX7RX5R
0402
COMMON
1.4K
1%
0402
CHANGED
R634
137
1%
0402
COMMON
AH7
AK8
AH8
U8
G71-N-A2
BGA1148
CHANGED
R9
T8
AJ10
AJ7
AJ9
AH9
AH10
AK9
GND
DACC_I2C_SCL
DACC_I2C_SDA
DACC_HSYNC
DACC_VSYNC
DACC_RED
DACC_GREEN
DACC_BLUE
1
2
R627
150
1%
0402
COMMON
GND
R630
147
1%
0402
CHANGED
GND
U507
74ACT08
DACC_HS_BUF
11
74ACT_SO
COMMON
GND
5V
U507
74ACT08
DACC_VS_BUF
3
74ACT_SO
COMMON
GND
5%
33
R745
COMMON
0402
5%
sync_buf bypass
33
R725
NO STUFF
0402
5%
33
R726
COMMON
0402
5%
DACC_HS_BUF_R
DACC_VS_BUF_R
GND
GND
R741
150
1%
0402
COMMON
R742
150
1%
0402
COMMON
5V
2
D3
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
5V
2
D2
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
C919
22PF
50V
5%
C0G
0402
NO STUFF
GND
C920
22PF
50V
5%
C0G
0402
NO STUFF
GND
DACC NET RULES
NV_CRITICALNET
DACC_RED
DACC_GREEN
DACC_BLUE
12<
12<
11> 12<
11>
11>
DACC_RED_DVI
DACC_GREEN_DVI
DACC_BLUE_DVI
1
1
1
1
1
1
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
ECSetNV_IMPEDANCE
DAC_RGB_CSET
DAC_RGB_CSET
DAC_RGB_CSET
DAC_RGB_CSET
DAC_RGB_CSET
DAC_RGB_CSET
R620
154
1%
0402
CHANGED
GND
150
1%
0402
COMMON
GND GND
C918R740
22PF
50V
5%
C0G
0402
NO STUFF
L2
L1
0402
0402
L507
L508
L506
COMMON
COMMON
27nH
27nH
COMMON0402
COMMON0402
COMMON0402
27nH
27nH
27nH
C6
27PF
50V
5%
C0G
0603
COMMON
GND
C5
27PF
50V
5%
C0G
0603
COMMON
GND
C928
10PF
50V
5%
C0G
0402
CHANGED
GND
C929
10PF
50V
5%
C0G
0402
CHANGED
GND
C927
10PF
50V
5%
C0G
0402
CHANGED
GND
DACC_HS_DVI
DACC_VS_DVI
DACC_RED_DVI
DACC_GREEN_DVI
DACC_BLUE_DVI
DACC_RED_DVI
DACC_GREEN_DVI
DACC_BLUE_DVI
DDC_5V
SNN_DACC_ID2
11< 12<
11< 12<
11>
11>
11>
12< 11<
11< 12<
12< 11<
11>
12<
11>
11<
12<
11>
11<
12<
11<
J1
CON_DSUB15HD
VGA_SLIM_DVIMTG
VGA_SLIM_DVIMTG
NO STUFF
6
1
7
2
8
3
9
4
10
5
GND
11
12
13
14
15
SNN_DACC_ID0
DACC_HSYNC
DACC_VSYNC
DACC_HS_BUF
DACC_VS_BUF
DACC_HS_BUF_R
DACC_VS_BUF_R
11>
12<
11>
12<
11>
12<
11>
12<
DACC_HS_DVI
DACC_VS_DVI
DACC_I2C_SCL
DACC_I2C_SDA
DACC_I2C_SCL_R
DACC_I2C_SDA_R
DACC_I2C_SCL_DVI
DACC_I2C_SDA_DVI
DACC_VREF
DACC_RSET
2
2
2
2
2
2
2
2
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
5V
C17
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
Place near Synce Diode
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
DACC Interface
www.vinafix.vn
600-10455-0002-001
design
LFarasati
11 OF 24
9-FEB-2006
INININININININININ
IN
1917
81624
C5A
C1
C2
C3
C5
C4
SHLD13
SHLD24
SHIELD6
SHIELD7
SHIELD10
SHIELD9
SHIELD8
SHIELD5
SHIELD4
SHIELD3
SHIELD2
SHIELD1
SHLD05
TX0ÂTX0+
TX2-
TX1ÂTX1+
TX2+
TX3ÂTX3+
TX4-
TX5-
TX4+
TX5+
DDCC
DDCD
TXC-
SHLDC
GND
VDDC
TXC+
HPD
R
VSYNC
G
B
AGND1
AGND2
HSYNC
1917
81624
C5A
C1
C2
C3
C5
C4
SHLD13
SHLD24
SHIELD6
SHIELD7
SHIELD10
SHIELD9
SHIELD8
SHIELD5
SHIELD4
SHIELD3
SHIELD2
SHIELD1
SHLD05
TX0ÂTX0+
TX2-
TX1ÂTX1+
TX2+
TX3ÂTX3+
TX4-
TX5-
TX4+
TX5+
DDCC
DDCD
TXC-
SHLDC
GND
VDDC
TXC+
HPD
R
VSYNC
G
B
AGND1
AGND2
HSYNC
INININININININ
OUTINININININININOUT
12/24 IFPAB TMDS
IFPA_TXD0
IFPA_TXC
IFPA_TXC
IFPA_TXD0
IFPA_TXD1
IFPA_TXD1
IFPA_TXD3
IFPA_TXD3
IFPA_TXD2
IFPA_TXD2
IFPB_TXD7
IFPB_TXD7
IFPB_TXD4
IFPB_TXD6
IFPB_TXD6
IFPB_TXD5
IFPB_TXD5
IFPB_TXD4
IFPB_TXC
IFPB_TXC
IFPAB_RSET
IFPAB_PLLVDD
IFPAB_PLLGND
IFPA_IOVDD
IFPAB_VPROBE
IFPB_IOVDD
13/24 IFPCD TMDS
IFPC_TXD2
IFPC_TXC
IFPC_TXC
IFPC_TXD0
IFPC_TXD0
IFPC_TXD1
IFPC_TXD1
IFPC_TXD2
IFPD_TXD6
IFPD_TXD6
IFPD_TXD5
IFPD_TXC
IFPD_TXC
IFPD_TXD4
IFPD_TXD4
IFPD_TXD5
IFPCD_RSET
IFPCD_VPROBE
IFPCD_PLLGND
IFPC_IOVDD
IFPCD_PLLVDD
IFPD_IOVDD
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
U8
G71-N-A2
BGA1148
CHANGED
C809
.01UF
16V
X7R
0402
COMMON
C797
.01UF
16V
10%
X7R
0402
COMMON
AR6
AM7
AN6
AN7
AN8
SNN_IFPAB_VPROBE
IFPAB_RSET
IFPAB_PLLVDD
C804
.1UF
10V
10% 10%
X5R
0402
COMMON
IFPAB_IOVDD
C795
.1UF
10V
10%
X5R
0402
COMMON
AM6
C793
10V
10%
X5R
0402
COMMON
GND
C805
.01UF.1UF
16V
10%
X7R
0402
COMMON
NET RULES
NET
IFPAB_TXC*
AT9
IFPAB_TXC
AT8
IFPAB_TXD0*
AN4
IFPAB_TXD0
AN5
IFPAB_TXD1*
AT3
IFPAB_TXD1
AT4
IFPAB_TXD2*
AP4
IFPAB_TXD2
AP5
SNN_IFPAB_TXD3*
AR3
SNN_IFPAB_TXD3
AR4
SNN_IFPB_TXC*
AP1
SNN_IFPB_TXC
AR2
IFPAB_TXD4*
AP6
IFPAB_TXD4
AP7
IFPAB_TXD5*
AR7
IFPAB_TXD5
AR8
IFPAB_TXD6*
AT5
IFPAB_TXD6
AT6
SNN_IFPAB_TXD7*
AN2
SNN_IFPAB_TXD7
AP2
IFPAB_TXC
IFPAB_TXC
IFPAB_TXD0
IFPAB_TXD0
IFPAB_TXD1
IFPAB_TXD1
IFPAB_TXD2
IFPAB_TXD2
IFPAB_TXD4
IFPAB_TXD4
IFPAB_TXD5
IFPAB_TXD5
IFPAB_TXD6
IFPAB_TXD6
NV_IMPEDANCENV_CRITICALDIFFPAIR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
F3V3
A2V5
IFP_IOVDD
FOR G70 COMPATIBILITY
180R@100MHz
LB507
BEAD_0603
180R@100MHz
LB508
BEAD_0603
180R@100MHz
LB505
BEAD_0603
NO STUFF
CHANGED
CHANGED
1K
R633
COMMON
0402
5%
GND
C820
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C801
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
Page12: IFP A/B and C/D Interface
F3V3
16<
U8
G71-N-A2
AL6
AN3
AM4
AL4
AL5
BGA1148
CHANGED
FOR G70 COMPATIBILITY
180R@100MHz
F3V3
A2V5
IFP_IOVDD
LB512
BEAD_0603
180R@100MHz
LB515
BEAD_0603
180R@100MHz
LB517
BEAD_0603
NO STUFF
CHANGED
CHANGED
1K
R653
COMMON
0402
5%
GND
C846
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
C839
4.7UF
6.3V
10%
X5R
0603
COMMON
SNN_IFPCD_VPROBE
IFPCD_RSET
IFPCD_PLLVDD
C832
.1UF
10V
10%
X5R
0402
COMMON
IFPCD_IOVDD
C803
.1UF
10V
10%
X5R
0402
COMMON
C819
.01UF
16V
10%
X7R
0402
COMMON
C808
.01UF
16V
10%
X7R
0402
COMMON
GND
C834
.1UF
10V
10%
X5R
0402
COMMON
GND
C816
.01UF
16V
10%
X7R
0402
COMMON
AJ4
GPIO0_DVI_A_HPD
R10
10K
5%
0402
COMMON
GND
NET RULES
NET
IFPCD_TXC*
AJ6
IFPCD_TXC
AH6
IFPCD_TXD0*
AL2
IFPCD_TXD0
AL1
IFPCD_TXD1*
AJ1
IFPCD_TXD1
AK1
IFPCD_TXD2*
AL3
IFPCD_TXD2
AM3
SNN_IFPD_TXC*
AH5
SNN_IFPD_TXC
AH4
IFPCD_TXD4*
AK2
IFPCD_TXD4
AK3
IFPCD_TXD5*
AK4
IFPCD_TXD5
AK5
IFPCD_TXD6*
AM1
IFPCD_TXD6
AN1
16<
3
IFPC_TXC
IFPC_TXC
IFPCD_TXD0
IFPCD_TXD0
IFPCD_TXD1
IFPCD_TXD1
IFPCD_TXD2
IFPCD_TXD2
IFPCD_TXD4
IFPCD_TXD4
IFPCD_TXD5
IFPCD_TXD5
IFPCD_TXD6
IFPCD_TXD6
Hotplug Detection
GPIO1_DVI_C_HPD
GND
R6
0402
2
D6
BAV99
SOT23
100V
100MA
COMMON
1
GND
R9
10K
5%
0402
COMMON
www.vinafix.vn
DVI_A_HPD_R
5.1K
CHANGED
5%
F3V3
GND
NV_CRITICALDIFFPAIR
F3V3
2
D5
BAV99
3
SOT23
100V
100MA
COMMON
1
GND
C18
.1UF
16V
10%
X7R
0603
COMMON
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0402
BEAD_0603
C3
220PF
50V
5%
C0G
0402
COMMON
GND
180R@100MHz
LB2
COMMON
NV_IMPEDANCE
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
R5
CHANGED
5%
BEAD_0603 COMMON
DVI_C_HPD_R
5.1K
F3V3
C19
.1UF
16V
10%
X7R
0603
COMMON
GND
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
IFP A/B and C/D Interface
LB1
180R@100MHz
C2
220PF
50V
5%
C0G
0402
COMMON
GND
10>
10<
10>
10<
10>
10<
10>
10<
10< 10>
10>
10<
10>
10<
11>
11<
11>
11<
11>
11<
11>
11<
11>
11<
11>
11<
11>
11<
DDC_5V
C935
22PF
50V
5%
C0G
0402
CHANGED
GND
IFPAB_TXD0*
IFPAB_TXD0
IFPAB_TXD1*
IFPAB_TXD1
IFPAB_TXD2*
IFPAB_TXD2
IFPAB_TXD4*
IFPAB_TXD4
IFPAB_TXD5*
IFPAB_TXD5
IFPAB_TXD6*
IFPAB_TXD6
DACA_I2C_SCL_DVI
DACA_I2C_SDA_DVI
IFPAB_TXC*
IFPAB_TXC
DACA_VS_DVI
DVI_A_HPD_C
DACA_RED_DVI
DACA_GREEN_DVI
DACA_BLUE_DVI
DACA_HS_DVI
C937
22PF
50V
5%
C0G
0402
CHANGED
GND
IFPCD_TXD0*
IFPCD_TXD0
IFPCD_TXD1*
IFPCD_TXD1
IFPCD_TXD2*
IFPCD_TXD2
IFPCD_TXD4*
IFPCD_TXD4
IFPCD_TXD5*
IFPCD_TXD5
IFPCD_TXD6*
IFPCD_TXD6
DACC_I2C_SCL_DVI
DACC_I2C_SDA_DVI
IFPCD_TXC*
IFPCD_TXC
DACC_VS_DVI
DVI_C_HPD_C
DACC_RED_DVI
DACC_GREEN_DVI
DACC_BLUE_DVI
DACC_HS_DVI
DDC_5V
25
26
27
28
29
17
18
9
10
1
2
3
11
19
12
13
4
5
20
21
6
7
14
15
22
24
23
8
16
C1
C2
C3
C5
C5A
C4
30
31
32
33
34
GND
25
26
27
28
29
17
18
9
10
1
2
3
11
19
12
13
4
5
20
21
6
7
14
15
22
24
23
8
16
C1
C2
C3
C5
C5A
C4
30
31
32
33
34
GND
IFPABCD NET RULES
NET
IFPAB_RSET
IFPCD_RSET
DVI_A_HPD_C
DVI_A_HPD_R
DVI_C_HPD_C
DVI_C_HPD_R
NET
IFPAB_PLLVDD
IFPAB_IOVDD
IFPCD_PLLVDD
IFPCD_IOVDD
J5
DVI-I
DVI_I_(SLIM_)SHLD_MOLEX
DVI_I_SLIM_SHLD_M
COMMON
065-0011-000
IFP_IOVDD
C812
.01UF
16V
10%
X7R
0402
NO STUFF
IFP_IOVDD
C802
.01UF
16V
10%
X7R
0402
NO STUFF
J4
DVI-I
DVI_I_(SLIM_)SHLD_MOLEX
DVI_I_SLIM_SHLD_M
COMMON
065-0011-000
IFP_IOVDD
C79
.01UF
16V
10%
X7R
0402
NO STUFF
IFP_IOVDD
C76
.01UF
16V
10%
X7R
0402
NO STUFF
NV_CRITICAL
1
1
VOLTAGE
2.5V
3.3V
2.5V
3.3V
IFP_IOVDD
C829
.01UF
16V
10%
X7R
0402
NO STUFF
GND
C821
C796
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
NO STUFF
NO STUFF
GND
C837
C813
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
NO STUFF
NO STUFF
GND
IFP_IOVDD
C843
.01UF
16V
10%
X7R
0402
NO STUFF
GND
C78
C82
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
NO STUFF
NO STUFF
GND
C80
C75
.01UF
.01UF
16V
16V
10%
10%
X7R
X7R
0402
0402
NO STUFF
NO STUFF
GND
600-10455-0002-001
design
LFarasati
R643
0402
R663
0402
R659
0402
0402
R645
0402
0402
R644
0402
R662
0402
R55
0402
R53
0402
R57
0402
R50
0402
R48
0402
R59
0402
MAX_CURRENT
49.9
NO STUFF
1%
49.9
NO STUFF
1%
49.9
NO STUFF
1%
49.9R652
NO STUFF
1%
49.9
NO STUFF
1%
49.9R636
NO STUFF
1%
49.9
NO STUFF
1%
49.9
NO STUFF
1%
49.9
NO STUFF
1%
49.9
NO STUFF
1%
49.9
NO STUFF
1%
49.9
NO STUFF
1%
49.9
NO STUFF
1%
49.9
NO STUFF
1%
50OHM
50OHM
0.03A
0.15A
0.15A
R642
0402
R660
0402
R655
R650
0402
R640
0402
R632
0402
R641
0402
R661
0402
R56
0402
R54
0402
R58
0402
R51
0402
R49
0402
R60
0402
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
MIN_WIDTH
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
49.9
NO STUFF
DIFFPAIRNV_IMPEDANCE
16MIL
16MIL
16MIL0.03A
16MIL
IFPAB_TXC*
IFPAB_TXC
IFPAB_TXD0*
IFPAB_TXD0
IFPAB_TXD1*
IFPAB_TXD1
IFPAB_TXD2*0402
IFPAB_TXD2
IFPAB_TXD4*
IFPAB_TXD4
IFPAB_TXD5*
IFPAB_TXD5
IFPAB_TXD6*
IFPAB_TXD6
IFPCD_TXC*
IFPCD_TXC
IFPCD_TXD0*
IFPCD_TXD0
IFPCD_TXD1*
IFPCD_TXD1
IFPCD_TXD2*
IFPCD_TXD2
IFPCD_TXD4*
IFPCD_TXD4
IFPCD_TXD5*
IFPCD_TXD5
IFPCD_TXD6*
IFPCD_TXD6
12 OF 24
9-FEB-2006
Page13: DACB and Stereo Interface
ININININININININININININININININININININININININININBI
OUT
POLYSWITCH
IN
OUT
IN
out
in
out
out
in
5V+
Y/CVBS
SDA
C
GND
C/Pr
Pb out
SCL
GND
Y/CVBS
HDTV
YOUT
PBOUT
GND
COUT
SDA
RFU
X
GND
GND
SCL
GND
+5V
KEYED
OUT
IN
9/24 DACB (TVout)
DACB_RED
DACB_GREEN
DACB_BLUE
DACB_IDUMP
DACB_RSET
DACB_VREF
DACB_VDD
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
COMMON DAC_VDD FOR DAC A/B/C
Stereo 3D
DAC_VDD
Stereo 5V
F1
1A
1812
5V
NO STUFF
1
2
5V_POLY_STEREO
DNI FOR VIVO
LB3
BEAD_0805
LB10
BEAD_0805
NO STUFF
NO STUFF
Current = ~300mA
220R@100MHz
220R@100MHz
MDIN_GND2_STEREO5V
STEREO_5V
Internal Stereo Out/ I2S (Optional)
16<
16>
16<
16> 17>
16<
R735
150
1%
0402
COMMON
GND
R736
150
1%
0402
COMMON
GND
CVBSYIN_R
18
NO STUFF0402
5%
to DIN connector
82pF/270pF
ROM_SCLK
ROM_SI
ROM_SO
I2S Pin Mapping
1 ROM_SCLK (aclk)
2 GND
3 ROM_SI (i2ssd)
4 ROM_SO (i2ssw)
8.2PF
C923
50V
0603
COMMON
NPO
L504
COMMON
0603
C912
82PF
50V
5%
C0G
0402
COMMON
GND
8.2PF
C924
0603
COMMON
NPO
L505
COMMON
0603
C913
82PF
50V
5%
C0G
0402
COMMON
GND
L510
NO STUFF
0603
C917
270PF
50V
5%
C0G
0603
NO STUFF
GND
+/-0.5PF
0.56uH
+/-0.5PF50V
0.56uH
1.8uH
R16
0603
R19
0603
R22
0603
GND
GND
GND
0
NO STUFF
5%
0
NO STUFF
5%
0
NO STUFF
5%
MDIN_PBOUT_C
C933
82PF
50V
5%
C0G
0402
COMMON
MDIN_COUT_C
C934
82PF
50V
5%
C0G
0402
COMMON
C931
330PF
50V
5%
C0G
0603
NO STUFF
STEREO_5V
BUFFSTEREO_C
MDIN_CVBSYIN_C
DDC_5V
C15
.1UF
10V
10%
X5R
0402
NO STUFF
J3
CON_MINIDIN_7_REGAL
HDTV_POD
CHANGED
7
9
8
5
1
GNDGND
2X6 COMP OUT HDR
J7
HDR_2X6
MALE
2.00MM
0
N/A
KEY3
NO STUFF
1
5
7
9
11
C24
220PF
50V
5%
C0G
0603
NO STUFF
GNDGNDGND
12 1311
2
SNN_2X6HDR_RFU
4
6
8
10
12
GNDGND
ST_INT_GND
R17
0
5%
0603
NO STUFF
MDIN_SCL_C_STEREO
DDC_5V
10
4
6
3
2
STUFF 1UF CAP
WHEN STEREO
ELSE 0 OHM R
1
J8
HDR_1M4
2
MALE
3
2.0MM
N/A
4
NORM
NO STUFF
16MIL
ST_INT_SHLD
R23
0
5%
0603
NO STUFF
GND
I2CC_SCL_BUFFSTEREO_R
C11
220PF
50V
5%
C0G
0603
NO STUFF
GND
MDIN_SDA_C
MDIN_GND2_STEREO5V
MDIN_YOUT_C
MDIN_CIN_C
R4
0
5%
0603
COMMON
Rgnd_video
LB9
BEAD_0603
STUFF (3) FOR STEREO/VIVO
3
5V
2
D516
BAV99
SOT23
100V
100MA
NO STUFF
1
GND
LB8
BEAD_0603
180R@100MHz
NO STUFF
AA8
AB9
BUFFSTEREO_C
COUT
SVID_CHROM
CVBS_YOUT
SVID_LUM
CVBS_PBOUTAA9
COMPOSITE
R621
158
1%
0402
CHANGED
GND
R649
143
1%
0402
CHANGED
BUFFSTEREO
5V
GND
C906
.1UF
10V
10%
X5R
0402
NO STUFF
DNI FOR VIVO
R722
0402
5%
33
NO STUFF
U8
G71-N-A2
BGA1148
CHANGED
5V
R724
3.3K
5%
0402
5V
NO STUFF
5
16< 16>
STEREO
1
2
U506
SN74LVC1G08
4
SC70-5
NO STUFF
3
GND
Y9
DACB_VREF
GNDGND
DACB_RSET
R622
15.8K
1%
0402
CHANGED
R619
127
1%
0402
CHANGED
C826
.1UF
10V
10%
X5R
0402
COMMON
GND
C790
.1UF
10V
10%
X5R
0402
COMMON
C787
.01UF
16V
10%
X7R
0402
COMMON
C788
.1UF
10V
10%
X5R
0402
COMMON
Y8
Y11
W9
GND
GND
13< 14<
CVBSYIN
GND
R738
R733
56
5%
0402
NO STUFF
FILTER CIRCUIT
HDTV/SDTV
from codec
82pF/330pF
8.2pF/22pf
0.56uH/1.8uH
DACB & STEREO NET RULES
180R@100MHz
NO STUFF
COMMON
L503
C932
82PF
50V
5%
C0G
0402
COMMON
GND
L509
C930
330PF
50V
5%
C0G
0603
NO STUFF
GND
C922
0603
0603
13> 14<
13> 14<
8.2PF
50V0603
NPO
0.56uH
COMMON
1.8uH
NO STUFF
DDC_5V
GND
+/-0.5PF
C22
4.7UF
6.3V
10%
X5R
0603
NO STUFF
C911
82PF
50V
5%
C0G
0402
COMMON
GND
C916
270PF
50V
5%
C0G
0603
NO STUFF
GND
NET
COUT
MDIN_COUT_C
CVBS_YOUT
MDIN_YOUT_C
CVBS_PBOUT
MDIN_PBOUT_C
CVBSYIN
CVBSYIN_R
MDIN_CVBSYIN_C
CHROMAIN
CHROMAIN_R
MDIN_CIN_C
I2CC_SCL_BUFFSTEREO_R
MDIN_SCL_C_STEREO
BUFFSTEREO
BUFFSTEREO_C
MDIN_SDA_C
NET
5V_POLY_STEREO
STEREO_5V
MDIN_GND2_STEREO5V
ST_INT_GND
ST_INT_SHLD
DACB_VREF
DACB_RSET
MDIN_GND
DNI FOR STEREO
R15
0402
5%
LB7
BEAD_0603
C12
220PF
50V
5%
C0G
0603
NO STUFF
GND
GND
CHROMAIN_R
0
R734
150
1%
0402
COMMON
0402
NO STUFF
NO STUFF
5%
1
1
1
1
1
1
1
1
1
1
1
1
5.0V
5.0V
0.0V
0.0V
0.0V
0.0V
180R@100MHz
R626
150
1%
0402
COMMON
GND
18R737
NO STUFF
GND
R732
56
5%
0402
NO STUFF
I2CC_SCL
I2CC_SDA
CVBS_YOUT
CHROMAIN
75OHM
75OHM
75OHM
75OHM
75OHM
75OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
0.03A
0.03A
MIN_WIDTHMAX_CURRENTVOLTAGE
13< 14<
ECSetNV_IMPEDANCENV_CRITICAL
DACB_RGB_CSET
DACB_RGB_CSET
DACB_RGB_CSET
DACB_RGB_CSET
DACB_RGB_CSET
DACB_RGB_CSET
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
16MIL
23< 16< 16> 14<
23<> 16< 16<> 14<>
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
DACB and Stereo Interface
www.vinafix.vn
600-10455-0002-001
design
LFarasati
13 OF 24
9-FEB-2006
Page14: Video Capture (Philips SAA7115)
INININININININININININININININININININ
IN
X-Port
VDD
D-GND
7114H,7115HL (QFP100)
Video In
I-Port
AGND
VSSA0
VSSA1
VSSA2
VDDA1
VDDA2
VDDA0
TDO
TMS
TRST
TDI
TCK
TEST5
TEST4
TEST0
TEST3
TEST2
TEST1
RTCO
XPD0
RTS1
LLC2
RTS0
LLC
XPD1
XPD5
XPD4
XPD3
XPD2
XPD6
XCLK
XPD7
XDQ
XRH
XTRI
XRV
XRDY
VDD_XTAL
VDDDE1
VDDDE2
VDDDI1
VDDDI2
VDDDI3
VDDDI4
VDDDI5
VDDDI6
VDDDE4
VDDDE3
VSS_XTAL
VSSDE1
VSSDE2
VSSDE3
VSSDI1
VSSDE4
VSSDI2
VSSDI3
AI1D
AI21
AI12
AOUT
AI11
AI22
ASCLK
AMCLK
AI24
AI23
AI2D
ALRCLK
SCL
RES (CE)
SDA
XTALI
XTALO
XTOUT
AMXCLK
RES_OUT
IPD4
IPD3
IPD2
IPD1
IPD0
IPD5
IPD6
IPD7
HPD1
HPD0
HPD6
HPD5
HPD4
HPD3
HPD2
IDQ
ICLK
HPD7
IGPH
ITRI
ITRDY
IGPV
IGP0
IGP1
INININBIOUTINOUT
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
VIDEO CAPTURE
U3
SAA7115HL
15_QFP100
NO STUFF
7115_VDDA
SNN_7115_AOUT
.047UF
13<
13>
13>
13<
CVBSYIN
CHROMAIN
16<> 16< 23<>
16> 16< 23<
16>
17>
15<
13<>
13<
16<
15<
14<
I2CC_SDA
I2CC_SCL
BUFRST*
MIOBD<7..0>
VIPPCLK
C886
16V
0402
10%
X7R
NO STUFF
.047UF
C885
16V
0402
10%
X7R
NO STUFF
STUFF PULLUP for 7115
STUFF O Ohm for 7114
R39
0402
5%
0
NO STUFF
7115_VDD
R42
10K
5%
0402
NO STUFF
R38
0402
STUFF for 7115
C35
33PF
50V
5%
C0G
0603
NO STUFF
5%
4.7K
NO STUFF
CER_SMD
Y1
XTAL
24.576MHZ
+/-30PPM
NO STUFF
R707
0402
C33
.047UF
16V
10%
X7R
0402
NO STUFF
33
NO STUFF
5%
C63
.047UF
16V
10%
X7R
0402
NO STUFF
NO STUFF
C34
.047UF
16V
10%
X7R
0402
NO STUFF
TP507
C36
33PF
50V
5%
C0G
0603
NO STUFF
7115_A11
SNN_7115_A12
7115_A1D
7115_A21
SNN_7115_A22
SNN_7115_A23
SNN_7115_A24
7115_A2D
SNN_7115_AMCLK
SNN_7115_ALRCLK
SNN_7115_ASCLK
7115_XTOUT
7115_XOUT
7115_XIN
RESET_7114
SNN_RES_OUT
0
1
2
3
4
5
6
7
SNN_7115_HPD0
SNN_7115_HPD1
SNN_7115_HPD2
SNN_7115_HPD3
SNN_7115_HPD4
SNN_7115_HPD5
SNN_7115_HPD6
SNN_7115_HPD7
VIPPCLK_R
SNN_7115_IDQ
SNN_7115_IGPH
SNN_7115_IGPV
SNN_7115_ITRDY
RESET_7115
SNN_7115_IGP0
SNN_7115_IGP1
22
20
18
19
16
14
12
10
13
37
40
39
41
4
6
7
32
31
27
30
62
61
60
59
57
56
55
54
72
71
70
69
67
66
65
64
45
46
53
52
42
47
48
49
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Video Capture (Philips SAA7115)
www.vinafix.vn
23
17
11
21
24
15
9
2
99
3
97
98
44
73
74
77
78
79
36
34
35
28
29
90
89
87
86
85
84
82
81
94
95
92
91
96
80
8
1
25
51
75
33
43
58
68
83
93
5
26
50
76
100
38
63
88
7115_TDO
7115_TMS
7115_TDI
7115_TRST*
7115_TCK
SNN_7115_TEST0
SNN_7115_TEST1
SNN_7115_TEST2
SNN_7115_TEST3
SNN_7115_TEST4
SNN_7115_TEST5
7115_RTCO
SNN_7115_RTC0
SNN_7115_RTS1
SNN_7115_LLC
SNN_7115_LLC2
SNN_7115_XPD0
SNN_7115_XPD1
SNN_7115_XPD2
SNN_7115_XPD3
SNN_7115_XPD4
SNN_7115_XPD5
SNN_7115_XPD6
SNN_7115_XPD7
SNN_7115_XCLK
SNN_7115_XDQ
SNN_7115_XRH
SNN_7115_XRV
SNN_7115_XRDY
SNN_7115_XTRI
7115_VDDX
7115_VDDE
16V
10%
X7R
0402
NO STUFF
C889
2200PF
16V
10%
X7R
0402
NO STUFF
C54
2200PF
16V
10%
X7R
0402
NO STUFF
C68
2200PF
16V
10%
X7R
0402
NO STUFF
2200PF 2200PF2200PF
16V
10%
X7R
0402
NO STUFF
TP3
TP2
TP1
C37
C40C38C42
.1UF
10V
10V
16V
10%
X7R
0402
NO STUFF
NO STUFF
NO STUFF
NO STUFF
disable JTAG port
R27
1K
5%
0402
NO STUFF
Select I2C Address
R29
RTC0=0 -> 0x42/0x43
3.3K
RTC0=1 -> 0x40/0x41
5%
0402
NO STUFF
SAA 7115
R28
1K
5%
0402
NO STUFF
10%
X5R
0402
NO STUFF
10%
X5R
0402
NO STUFF
I2C ADDRESS 0X42
C893
.1UF
10V
10%
X5R
0402
NO STUFF
C60
2200PF
16V
10%
X7R
0402
NO STUFF
C70
2200PF
16V
10%
X7R
0402
NO STUFF
C65
2200PF
16V
10%
X7R
0402
NO STUFF
C57
2200PF
16V
10%
X7R
0402
NO STUFF
C66
2200PF
16V
10%
X7R
0402
NO STUFF
C43
2200PF
16V
10%
X7R
0402
NO STUFF
C39C41
.1UF.1UF
10V
10%
X5R
0402
NO STUFF
C67
2200PF
16V
10%
X7R
0402
NO STUFF
C47
2200PF
16V
10%
X7R
0402
NO STUFF
C31
4.7UF
6.3V
10%
X5R
0603
NO STUFF
LB13
C69
.1UF
10V
10%
X5R
0402
NO STUFF
C46
.1UF
10V
10%
0402
NO STUFF
14>
15<
SAA7115 NET RULES
600R@100MHZ
NO STUFFBEAD_0603
VIPPCLK_R
VIPPCLK
7115_A11
7115_A1D
7115_A2D
7115_A21
7115_XOUT
7115_XIN
RESET_7114
RESET_7115
7115_TRST*
7115_TCK
7115_RTCO
7115_TMS
7115_TDO
7115_TDI
7115_XTOUT
7115_VDDA
7115_VDDE
7115_VDDX
7115_VDD
C53
.1UF
10V
10%
X5R
0402
NO STUFF
C52
.1UF
10V
10%
X5RX5R
0402
NO STUFF
NET
NET
C32
4.7UF
6.3V
10%
X5R
0603
NO STUFF
C898
4.7UF
6.3V
10%
X5R
0603
NO STUFF
C45
4.7UF
6.3V
10%
X5R
0603
NO STUFF
C72
.1UF
10V
10%
X5R
0402
NO STUFF
1
1
2
2
2
2
1
1
2
2
2
2
2
VOLTAGE MIN_WIDTHMAX_CURRENT
3.3V
3.3V
3.3V
LB519
LB15
600R@100MHZ
NO STUFFBEAD_0603
600R@100MHZ
NO STUFFBEAD_0603
600-10455-0002-001
design
LFarasati
50OHM
DIFFPAIRNV_IMPEDANCENV_CRITICAL
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
0.09A 16MIL
0.08A
0.01A
C899
4.7UF
6.3V
10%
X5R
0603
NO STUFF
C44
4.7UF
6.3V
10%
X5R
0603
NO STUFF
7115_VDD
16MIL
16MIL
14 OF 24
9-FEB-2006
Page15: Multi-use IO(MIO) Interface
INBIIN
MIOD<11>
MIOD<10>
MIOD<9>
MIOD<8>
MIOD<7>
MIOD<6>
MIOD<5>
MIOD<4>
MIOD<3>
MIOD<2>
MIOD<1>
MIOD<0>
MIOCLK
MIODE
MIOVSYNC
MIOHSYNC
SWAP_RDY
GND
GND
GND
GND
GND
GND
RSVD
RSVD
RSVD
14/24 MIOA
MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8
MIOAD9
MIOAD10
MIOAD11
MIOA_DE
MIOA_CLKIN
MIOA_CTL3
MIOA_VSYNC
MIOA_HSYNC
MIOA_CLKOUT
MIOA_CLKOUT
MIOACAL_PD_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOA_VREF
MIOA_VDDQ
MIOACAL_PU_GND
IN
IN
15/24 MIOB
MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11
MIOBD12
MIOBD13
MIOBD14
MIOBD15
MIOBD16
MIOBD17
MIOBD18
MIOBD19
MIOBD20
MIOBD21
MIOBD22
MIOBD23
MIOB_DE
MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT
MIOB_HSYNC
MIOB_VSYNC
MIOB_CTL3
MIOBCAL_PD_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VREF
MIOBCAL_PU_GND
INININININININININININININININININ
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
MIO Feature Connector
MIOAD<11..0>
U8
A2V5
220R@100MHz
LB513
CHANGED
BEAD_0805
.1UF .01UF .01UF.01UF4.7UF
6.3V
10%
X5R
0603
COMMON
GND
10V
10%
X5R
0402
16V
10%
X7R
0402
COMMONCOMMON
16V
10%
X7R
COMMON
C771C759C798C752C850
16V
10%
X7R
04020402
COMMON
F3V3
220R@100MHz
LB514
BEAD_0805
CHANGED
C849
1UF
6.3V
10%
X7R
0603
COMMON
GND
C772
.1UF
10V
10%
X5R
0402
COMMON
C753
.01UF
16V
10%
X7R
0402
COMMON
C768
.01UF
16V
10%
X7R
0402
COMMON
MIO NET RULES
MIOAD<11..0>
MIOA_CLKIN
MIOA_CLKOUT
MIOA_DE
MIOA_HSYNC
MIOA_VSYNC
MIOBD<11..0>
MIOB_CLKIN
MIOB_HSYNC
MIOA_VDDQ
MIOA_VREF
MIOACAL_PD_VDDQ
MIOACAL_PU_GND
MIOB_VDDQ
MIOB_VREF
MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND
15<
17>
15<
17>
14>
15<
NV_CRITICALNET
2
2
2
2
2
2
2
2
VOLTAGENET
2.5V
1.65V
2.5V
0.0V
3.3V
1.65V
3.3V
0.0V
NV_IMPEDANCE
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
MAX_CURRENT
0.80A 16MIL
0.03A 12MIL
DIFFPAIR
MIN_WIDTH
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
MIOA_VDDQ
R654
R651
GND
MIOB_VDDQ
R656
R658
GND
GND
0402
0402
GND
0402
0402
C844
.1UF
10V
10%
X5R
0402
COMMON
49.9
COMMON
1%
49.9
COMMON
1%
C841 R666
.1UF
10V
10%
X5R
0402
COMMON
49.9
COMMON
1%
49.9
COMMON
1%
R676
1K
1%
0402
COMMON
MIOA_VREF
R675
1K
1%
0402
COMMON
MIOACAL_PD_VDDQ
MIOACAL_PU_GND
R667
1K
1%
0402
COMMON
MIOB_VREF
1K
1%
0402
COMMON
MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND
G71-N-A2
BGA1148
CHANGED
U11
V11
W11
T12
U12
AA4
Y7
V7
V6
V5
U7
Y3
W1
W2
Y4
W5
W6
W3
V3
V2
U4
AA2
Y1
AA5
Y5
AA7
U8
G71-N-A2
BGA1148
CHANGED
AE11
AE12
AF12
AE13
AF13
AG2
AG1
AF1
AE6
AG7
AF9
AF8
AE9
AE7
AD8
AD9
AC8
AD7
AD5
AC5
AD4
AF4
AE2
AE1
AE3
AF3
AH2
AH1
AH3
AJ3
AG9
AG8
AF7
AD3
AG3
AG4
AF5
AE5
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Multi-use IO(MIO) Interface
www.vinafix.vn
MIOA_DEW7
MIOA_CLKIN
MIOA_CLKOUT
SNN_MIOA_CLKOUT*
MIOA_HSYNC
MIOA_VSYNC
SNN_MIOA_CTL3
SNN_MIOBD12
SNN_MIOBD13
SNN_MIOBD14
SNN_MIOBD15
SNN_MIOBD16
SNN_MIOBD17
SNN_MIOBD18
SNN_MIOBD19
SNN_MIOBD20
SNN_MIOBD21
SNN_MIOBD22
SNN_MIOBD23
SNN_MIOB_DE
MIOB_CLKIN
SNN_MIOB_CLKOUT
SNN_MIOB_CLKOUT*
MIOB_HSYNC
VIPPCLKAG5
SNN_MIOB_CTL3
10
11
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
MIOBD<11..0>
VIP0
VIP1
VIP2
VIP3
VIP4
VIP5
VIP6
VIP7
STRAPS
STRAPS
STRAPS
STRAPS
SNN_MIOA_RSVD0
SNN_MIOA_RSVD1
SNN_MIOA_RSVD2
R646
0402
R657
0402
TP4
5%
NO STUFF
5%
10K
COMMON
10K
COMMON
GND
14<
GND
14>
GND
B7
B11
A3
A7
A11
B5
A9
A13
15< 17>
14>
CN1
CON_MIO_26_EDGE
NONPHY
COMMON
A12
B12
A10
B10B3
B9
A8
A6
B6
A5
A4
B4
A2
B2
A1
B13
B8
B1
MIOAD<11..0>
MIOA_HSYNC
MIOA_VSYNC
MIOA_DE
MIOA_CLKOUT
SWAPRDY_A
17> 15< 17> 15<
11
10
9
8
7
6
5
4
3
2
1
0
16> 16<
15< 15<
600-10455-0002-001
design
LFarasati
15 OF 24
9-FEB-2006
INININININININININININININININININININININININININININININININ
VCC
GND
HOLD
WP
CS
SI
SCK
SO
OUT
BI
VCC
VCC
GND
GND
SCL
SDA
NC
SDA
OUTINOUT
17/24 I2C
I2CC_SDA
I2CC_SCL
I2CH_SDA
I2CH_SCL
OUT
OUT
OUT
24/24 MISC
BUFRST
ROM_SO
ROM_SI
ROM_SCLK
ROMCS
STEREO
CLAMP
TESTMODE
SWAPRDY_A
SPDIF
RFU
RFU
RFU
RFU
RFU
RFU
ININOUT
OUTINOUT
IN
18/24 GPIO
GPIO<12>
GPIO<11>
GPIO<10>
GPIO<9>
GPIO<7>
GPIO<8>
GPIO<6>
GPIO<4>
GPIO<5>
GPIO<3>
GPIO<2>
GPIO<1>
GPIO<0>
11/24 PLLVDD
VID_PLLVDD
VID_PLLAVDD
VID_PLLGND
PLLVDD
PLLAVDD
PLLGND
16/24 XTAL
XTALOUTBUFF
XTALOUT
XTALSSIN
XTALIN
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
Page16: MISC: GPIO, I2C, ROM, HDCP, HDMI and XTAL
GPIO
U8
G71-N-A2
BGA1148
CHANGED
GPIO0_DVI_A_HPD
N3
GPIO1_DVI_C_HPD
U3
GPIO2_FAN_CTRL
T4
SNN_GPIO3
R2
N1
SNN_GPIO4
GPIO5_VSEL0
T3
GPIO6_VSEL1
T5
SNN_GPIO7
P1
GPIO8_GPU_SLOW*
M2
SNN_GPIO9
N2
SNN_GPIO10
R1
SNN_GPIO11
R3
GPIO12_EXT12V_PRSNT
P3
12>
16<
16<
16<
16<
16< 12>
20<
20<
23>
20>
23< 16<
GPIO Assignment Table
I/O Function
GPIO
0
2
3
4
5
6
7
8
9
11
12
IN
IN1
OUT
N/A
N/A
OUT
OUT
N/A
IN
N/A
N/A10
N/A
IN
DVI HOTPLUG DET A
DVI HOTPLUG DET C
PWM FAN CONTROL
VOLTAGE SELECT 0
VOLTAGE SELECT 1
GPU_SLOW*
EXT_12V DETECT
PLLVDD/VID_PLLVDD
AB11VID_PLLVDD
AB12
AA12
AC11
AC12
AD12
U8
G71-N-A2
BGA1148
CHANGED
F3V3
A2V5
F3V3
A2V5
Place near Input
Ferrite bead of PLLVDD
PEX_VDD
180R@100MHz
LB518
BEAD_0603
180R@100MHz
LB516
BEAD_0603
FOR G70 COMPATIBILITY
180R@100MHz
LB509
BEAD_0603
180R@100MHz
LB511
BEAD_0603
C847
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
180R@100MHz
LB510
BEAD_0603 CHANGED
C845
4.7UF
6.3V
10%
X5R
0603
COMMON
NO STUFF
COMMON
NO STUFF
COMMON
C774
C848
.1UF
4.7UF
10V
6.3V
10%
10%
X5R
X5R
0402
0603
COMMON
COMMON
GND
C792
C840
.1UF
4.7UF
10V
6.3V
10%
10%
X5R
X5R
0402
0603
COMMON
COMMON
GND
C767
C827
.1UF
4.7UF
10V
6.3V
10%
10%
X5R
X5R
0402
0603
COMMON
COMMON
C799
.01UF
16V
10%
X7R
0402
COMMON
C783
.01UF
16V
10%
X7R
0402
COMMON
C756
.01UF
16V
10%
X7R
0402
COMMON
PLLVDD
PLLAVDD
GND
I2CC / I2CH(+ HDCP ROM)
F3V3
I2CC_SCL
I2CC_SDA
U8
G71-N-A2
BGA1148
CHANGED
P8
I2CC_SCL_R
P9
I2CC_SDA_R
U9
I2CH_SCL
V9
I2CH_SDA
ROM / MISC
INPUT FROM SPDIF HEADER
SPDIF
SNN_GPU_AC9 AC9
SNN_GPU_AB7
SNN_GPU_AB6
SNN_GPU_AC7
SNN_GPU_AB5
AB1
AC3SNN_GPU_AC3
AB7
AB6
AC7
AB5
U8
G71-N-A2
BGA1148
CHANGED
R664
0402
R665
0402
5%
5%
F3V3
33
COMMON
33
COMMON
R705
10K
5%
0402
NO STUFF
GND
(BUFRST/STEREO/SWAPRDY/TESTMODE)
ROM_CS*
AC4
ROM_SI
AB2
ROM_SO
AA3
ROM_SCLK
AA1
BUFRST*
U5
STEREO
Y12
SWAPRDY_A
N9
RF12 IS NC FOR G71
5V_CLAMPR12
TESTMODEV1
R669
2.2K
5%
0402
COMMON
R704
10K
5%
0402
NO STUFF
F3V3
R668
2.2K
5%
0402
COMMON
I2CH_SCL
I2CH_SDA
R61
10K
5%
0402
COMMON
GND GND
6
5
3
2SNN_CRYPT
13<
13>
13<
16<
14<
16<
13<
16<
13<
13<>
C754
.1UF
10V
10%
X5R
0402
NO STUFF
14< 16<
U504
AT88SC0808C
SO8
NO STUFF
16<
16<
F3V3
17>
F3V3
R33
1K
1%
0402
COMMON
0402
DO NOT PLACE NEAR GPU
5%
16< 14<>
R41
10K
5%
0402
COMMON
100R624
NO STUFF
16> 23<
13<
14<
13<>
14<>
16<>
23<>
13< 16>
17>
13>
16<
13< 16>
14<
16>
13<
16>
15<>
23<
23<>
F3V3
8
7
4
1
C861
.1UF
10V
10%
X5R
0402
NO STUFF
GND
7
3
1
5
2
6
16< 15<>
5V CLAMP FOR G70 COMPATIBILITY
5V
U5
SST25VF512
SO8
SO8
COMMON
16>
12>
16<
12>
16<
16>
20<
16>
20<
16<
23>
16>
23<
16<
20>
23<
F3V3
8
C58
.1UF
10V
10%
X5R
4
0402
COMMON
GND
MISC NET RULES
NET
I2CC_SCL
I2CC_SDA
I2CC_SCL_R
I2CC_SDA_R
I2CH_SCL
I2CH_SDA
ROM_CS*
ROM_SI
ROM_SO
ROM_SCLK
BUFRST*
STEREO
SWAPRDY_A
TESTMODE
GPIO0_DVI_A_HPD
GPIO1_DVI_C_HPD
GPIO5_VSEL0
GPIO6_VSEL1
GPIO8_GPU_SLOW*
GPIO2_FAN_CTRL
GPIO12_EXT12V_PRSNT
XTALSSIN
XTALIN
XTALOUT
XTALOUTBUFF
SPDIF_IN
SPDIF
NET
VID_PLLVDD
PLLVDD
PLLAVDD
5V_CLAMP
NV_CRITICAL NV_IMPEDANCE DIFFPAIR
1
1
1
2.5V
2.5V
1.2V
5V
50OHM
50OHM
50OHM
0.03A
0.03A
MIN_WIDTHMAX_CURRENTVOLTAGE
12MIL
12MIL
10MIL
16MIL
XTAL
C84
18PF
50V
5%
C0G
0402
COMMON
AD2
AD1
U8
G71-N-A2
BGA1148
CHANGED
XTAL_4PIN_HOSONIC
Y2XTALIN
+/-10 PPM
H10SSMD
COMMON
XTALOUTBUFFAB3
AC1
XTALOUT27 MHZ
C83
18PF
50V
5%
C0G
0402
COMMON
GND
R63
330
5%
0402
COMMON
GND
XTALSSIN
R62
10K
5%
0402
COMMON
GND
GND
SPDIF INPUT FOR HDMI (OPTIONAL)
NO STUFF FOR G70
SPDF-IN 2-PIN HEADER
HDR_1M2_FAN
MALE
2.5MM
NORM
NO STUFF
J6
0
SPDIF_IN1
2
R3
76.8
GND
1%
0402
NO STUFF
GND
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
GPIO, I2C, ROM, HDMI, and XTAL
0402
.1UF
C1
10V
10%
X5R
NO STUFF
www.vinafix.vn
FBVDDQ
R1
21K
1%
0402
NO STUFF
Need 400mV Here
R2
5.9K
1%
0402
NO STUFF
GND
TO PIN AB1 ON G71 GPU
SPDIF
600-10455-0002-001
design
LFarasati
16 OF 24
9-FEB-2006
Page17: Strapping Configuration
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
OUT
OUT
OUT
MIOAD<11..0>
MIOBD<12..0>
MIOAD<1>
1
MIOBD<0>
0
MIOBD<1>
1
MIOBD<8>
8
MIOBD<9>
9
15<
15<
14>
MIOAD<2>
2
MIOBD<11>
11
16< 13<
16>
ROM_SI
MIOBD<10>
10
A2V5 F3V3
HW STRAP Hi
R708
2.2K
0402
NO STUFF
5%
R47
10K
0402
COMMON
5%
R687
10K
0402
COMMON
5%
R699
10K
0402
COMMON
5%
R684
10K
0402
NO STUFF
5%
R681
2.2K
0402
NO STUFF
5%
R34
10K
0402
COMMON
5%
HW STRAP Hi
R680 10K
04025%COMMON
10K
NO STUFF
10K
NO STUFF
10K
NO STUFF
10K
COMMON
10K
10K
COMMON
2.2K
NO STUFF
MIOAD<1>
MIOBD<0>
MIOBD<1>
MIOBD<8>
MIOBD<9>
MIOAD<2>
MIOBD<11>
ROM_SI
MIOBD<10>
PC Strap
R45
0402
5%
R686
0402
5%
R698
0402
5%
R685
0402
5%
PC Strap
R696
04025%COMMON
R682
0402
5%
Strap overide for Scalability Connector
R35
0402
5%
Standardized Straps
SUBVENDOR
ROMTYPE[1:0]
PCI_AD
BUS_TYPE
RAMCFG[3:0]
USER[0]
DEVID[3]
BOOT_0_STRAP_0
G71
00: PCI_AD_SWAP
01: SUB_VENDOR
*
02: RAM_CFG_0
03: RAM_CFG_1*
*
04: RAM_CFG_2
* 05: RAM_CFG_3
06: CRYSTAL_0
07: TV_MODE_0
08: TV_MODE_1
09: AGP4x/8x
10: AGP_SBA
11: AGP_FASTWR
12: PCI_DEVID_0
13: PCI_DEVID_1
14: BUS_TYPE
15: FP_IFACE
*
16: USER_0
17: USER_1
18: USER_2
19: USER_3
20: PCI_DEVID_2
* 21: PCI_DEVID_3
22: CRYSTAL_1
23: FB_0
24: FB_1
25: BR
26: BR_128M
27: BR_AGP
28: BR_IO
* 29: ROM_TYPE_0
30: ROM_TYPE_1
31: STRAP_0_OVERWRITE
AND MASK
1 -> HARDWARE STRAP
0 -> BIOS STRAP
OR MASK
1 -> DESIRED=1 ANDMASK=0
SKU#
(256Mb)
0000
DESIRED
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
AND MASK
OR MASK
0 0 0
01
01
1 00
1
1
0
01
1
0
0 0
00
0 0
0
1 0
0
0 0
00
0 0
0
0
0
0
0
0
110
1 0
0
1 1
0
0
0 00
0
0
0
0
0
0
0 11 1
01
0 0
0
DESIRED
1
0
000
0
10
0
000
0
001
0
0
0
00
0
0
00
0
0
00
0
(256Mb)
xxxx
AND MASK
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
100
0
OR MASK
0
0
001
011
0
0
1
0
0
000
0
0
0
0
000
0
0
0
0
1
0
00
0
0
0
000
01
0
G71 Strap Mapping
NV_STRAP_0
----------------------------------------ÂBIT FUNCTION NORMAL PIN (RTL Name)
HW Default
----------------------------------------Â0 PCI_AD `NV_PEXTDEV_BOOT_0_STRAP_PCI_AD_NORMAL
1
1 SUB_VENDOR MIOAD1 (Ccira_data[1])
2 RAMCFG[0] MIOBD0 (Ccirb_data[0])
3 RAMCFG[1] MIOBD1 (Ccirb_data[1])
4 RAMCFG[2] MIOBD8 (Ccirb_data[8])
5 RAMCFG[3] MIOBD9 (Ccirb_data[9])
0
6 CRYSTAL[0] MIOBD2 (Ccirb_data[2])
1
7 TVMODE[0] MIOAD7 (Ccira_data[7])
0
8 TVMODE[1] MIOAD10 (Ccira_data[10])
9 AGP_4X `NV_PEXTDEV_BOOT_0_STRAP_AGP_4X_DISABLED
10 AGP_SBA `NV_PEXTDEV_BOOT_0_STRAP_AGP_SBA_DISABLED
11 AGP_FASTWR `NV_PEXTDEV_BOOT_0_STRAP_AGP_FASTWR_DISABLED
0
12 PCI_DEVID[0] MIOBD4 (Ccirb_data[4])
0
13 PCI_DEVID[1] MIOBD5 (Ccirb_data[5])
14 AGP `NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI
15 FP_IFACE `NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT
16 USER[0] MIOAD2 (Ccira_data[2])
17 USER[1] MIOAD3 (Ccira_data[3])
18 USER[2] MIOAD4 (Ccira_data[4])
19 USER[3] MIOAD5 (Ccira_data[5])
0
20 PCI_DEVID[2] MIOBD3 (Ccirb_data[3])
0
21 PCI_DEVID32[1] MIOBD11 (Ccirb_data[11])
22 CRYSTAL[1] MIOBD6 (Ccirb_data[6])
23 FB[0] 0
24 FB[1] 1
1
25 BR ROM_SI (Rom_si)
26 BR_128M `NV_PEXTDEV_BOOT_0_STRAP_BR_REG_128M_DISABLED
27 BR_AGP `NV_PEXTDEV_BOOT_0_STRAP_BR_AGP_DEV_DISABLED
28 BR_IO `NV_PEXTDEV_BOOT_0_STRAP_BR_IO_DEV_DISABLED
1
29 ROMTYPE[0] MIOBD10 (Ccirb_data[10])
0
30 ROMTYPE[1] 0
NV_STRAP_1
----------------------------------------ÂBIT FUNCTION NORMAL PIN (RTL Name)
----------------------------------------Â0 1394 `NV_PEXTDEV_BOOT_3_STRAP_1_1394_DISABLED
1 1394_PHY `NV_PEXTDEV_BOOT_3_STRAP_1_1394_PHY_DISABLED
2 1394_PHY_PWRCLASS[0] 0
3 1394_PHY_PWRCLASS[1] 0
4 VGA_DEVICE `NV_PEXTDEV_BOOT_3_STRAP_1_VGA_DEVICE_ENABLED
5 MEM_LSB_SWAP `NV_PEXTDEV_BOOT_3_STRAP_1_MEM_LSB_SWAP_DISABLED
6 BR_LAST_DEV `NV_PEXTDEV_BOOT_3_STRAP_1_BR_LAST_DEV_DISABLED
7 BR_BAR1_BCASTONLY `NV_PEXTDEV_BOOT_3_STRAP_1_BR_BAR1_BCASTONLY_ENABLED
8 SUBSYSTEM_USER `NV_PEXTDEV_BOOT_3_STRAP_1_SUBSYSTEM_USER_DISABLED
9 BOARD `NV_PEXTDEV_BOOT_3_STRAP_1_BOARD_0
1
10 FPB_IFACE MIOBD12 (Ccirb_data[12])
0
11 PEX_PLL_EN_TERM100 MIOAD0 (Ccira_data[0])
0
12 3GIO_PADCFG_LUT_ADR[0] MIOAD6 (Ccira_data[6])
0
13 3GIO_PADCFG_LUT_ADR[1] MIOAD8 (Ccira_data[8])
0
14 3GIO_PADCFG_LUT_ADR[2] MIOAD9 (Ccira_data[9])
*HW has Internal 10K Strap, need 1K to overide
SUB_VENDOR[0]
RAM_CFG[3:0]
CRYSTAL[1:0]
TVMODE[1:0]
PCI_DEVID[3:0]
USER[3:0]
FB[1:0]
ROM_TYPE[1:0]
BR
FPB_IFACE
PEX_PLL_EN_TERM100
3GIO_PADCFG_LUT_ADR[2:0]
STRAP_OVERWITE
0 - NO_BIOS
1 - READ FROM BIOS (DESIRED)
0000 RESERVED
0001 8PCS 16Mx32 Infineon DDR3
0010 8PCS 16Mx32 Hynix DDR3
0011 8PCS 16Mx32 Samsung DDR3
0100 N/A
0101 8PCS 8Mx32 Infineon DDR3
0110 8PCS 8Mx32 Hynix DDR3
0111 8PCS 8Mx32 Samsung DDR3
1000 N/A
1001 4PCS 16Mx32 Infineon DDR3
1010 4PCS 16Mx32 Hynix DDR3
1011 4PCS 16Mx32 Samsung DDR3
1100 N/A
1101 4PCS 8Mx32 Infineon DDR3
1110 4PCS 8Mx32 Hynix DDR3
1111 4PCS 8Mx32 Samsung DDR3
00 - 13.5 MHz
01 - 14.31818 MHz
10 - 27.000 MHz (DESIRED)
11 - UNKNOWN
00 - SECAM
01 - NTSC (DESIRED)
10 - PAL
11 - CRT
0000 = G71 = 0x000
1100 =
0000 - USER STRAP
00 - 64MEG (DESIRED)
01 - 128MEG
10 - 256MEG
11 - 512MEG
00 - PARALLEL (NOT SUPPORTED)
01 - SERIAL AT25F (DESIRED)
10 - SERIAL SST45VF/LF
11 - RFU
0 - ENABLE
1 - DISABLED (Default)
0 - 12Bit
1 - 24bit (Default)
0 - ENABLED (Internal 100ohm Term)
1 - DISABLED
000 = DEFAULT
0 - DISABLED (DESIRED)
1 - ENABLED
BOOT_3_STRAP_1
00: 1394
01: 1394_PHY
02: 1394_PHY_PWRCLASS[0]
03: 1394_PHY_PWRCLASS[1]
MIOBD<12>
12
MIOAD<0>
0
MIOAD<6>
6
MIOAD<8>
8
MIOAD<9>
9
HW STRAP Low
R694
04025%COMMON
*NOTE: Mobile Designs must provide the 3GPIO Strap Options
*NOTE: Mobile Designs must provide the 3GPIO Strap Options
*NOTE: Mobile Designs must provide the 3GPIO Strap Options
GND
10K
MIOAD<0>
R695
2.2K
04025%NO STUFF
04: VGA_DEVICE
05: MEM_LSB_SWAP
06: BR_LAST_DEV
07: BR_BAR1_BCASTONLY
08: SUBSYSTEM_USER
09: BOARD
10: FPB_IFACE
11: PEX_PLL_EN_TERM100
12: 3GIO_PADCFG_LUT_ADR[0]
13: 3GIO_PADCFG_LUT_ADR[1]
14: 3GIO_PADCFG_LUT_ADR[2]
31: STRAP_1_OVERWRITE
www.vinafix.vn
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 00
0 000
0
0
00
0
0
0
0
0
0
0
0
0
000
0 00
01
0
0 0
00
0
0
0
0
0
0
0
0
000
0
000
0
0
0
0
0
0
000
00
0
0
0
0
0
0
0
0
0
00
0
0
1
0
0
0
0
0
0
0
0
00
00
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Strapping Configuration
600-10455-0002-001
design
LFarasati
17 OF 24
9-FEB-2006
Page18: Power/GND and Decoupling
22/24 GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
OUT
OUT
20/24 VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD_SENSE
GND_SENSE
6/24 FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
21/24
VDD33
NC
NC
NC
NC
NC
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
7/24 VTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
IN
IN
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
VDD33
U8
G71-N-A2
BGA1148
CHANGED
N11
22<
22<
FBVTT
18>
18>
U8
G71-N-A2
BGA1148
CHANGED
P11
R11
N12
AH15
AJ16
AK16
AJ17
AK17
T2
AE21
AF23
AP23
AJ26
M12
M13
M15
M16
M17
M20
M21
M22
AE22
AE23
M24
AE24
M25
N25
R25
T25
U25
Y25
AA25
AB25
AD25
AE25
NVVDD_SENSE_GPU
NVVDD_GND_SENSE_GPU
SNN_GPU_T2
SNN_GPU_AE21
SNN_GPU_AF23
SNN_GPU_AP23
SNN_GPU_AJ26
C666
1UF
6.3V
10%
X5R
0402
COMMON
F3V3
FBVDDQ
GND
C755
.1UF
10V
10%
X5R
0402
COMMON
C776
.1UF
10V
10%
X5R
0402
COMMON
GND
C741
.47UF
6.3V
10%
X5R
0402
COMMON
C786
1UF
6.3V
10%
X7R
COMMON
C679
4.7UF
6.3V
10%
X5R
0603
COMMON
C672
.1UF
10V
10%
X5R
0402
COMMON
C744
1UF
6.3V
10%
X5R
0402
COMMON
C732
1UF
6.3V
10%
X5R
04020603
COMMON
C707
1UF
6.3V
10%
X5R
0402
COMMON
NV_IMPEDANCE DIFFPAIRNET NV_CRITICAL
C769
.47UF
6.3V
10%
X5R
0402
COMMON
GND
GND
GND
GND
GND
GND
GND
NVVDD
NVVDD
Place near BGA
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Power/GND and Decoupling
FBVDDQ
FBVDDQ
Place near BGA
C763
.022UF
16V
10%
X7R
0402
COMMON
C719
.022UF
16V 16V 10V 10V
10%
X7R
GND
GND
0402
COMMON
C718
.022UF
16V
10%
X7R
0402
COMMON
C735
.022UF
16V
10%
X7R
0402
COMMON
C745
.022UF
16V
10%
X7R
0402
COMMON
C764
.022UF
16V
10%
X7R
0402
COMMON
C653
.022UF
16V
X7R
0402
C659
.022UF
16V
10%
X7R
0402
COMMON
C700
.022UF
10%
X7R
0402
COMMON
C698
.022UF
16V
10%
X7R
0402
COMMON
C708
.022UF
16V
10%
X7R
0402
COMMON
C730
.022UF
16V
10%
X7R
0402
COMMON
C731
.022UF
16V
10%
X7R
0402
COMMON
C665
.1UF
10V
10%
X5R
0402
COMMON
C668
.1UF
10%
X5R
0402
COMMON
C663
.1UF
10V
10%
X5R
0402
COMMON
C682
.1UF
10V
10%
X5R
0402
COMMON
C676
.1UF
10V
10%
X5R
0402
COMMON
C669
.1UF
10V
10%
X5R
0402
COMMON
C688
.1UF
10V
10%10%
X5R
0402
COMMONCOMMON
C664
.1UF
10V
10%
X5R
0402
COMMON
C658
.1UF
10%
X5R
0402
COMMON
C670
.1UF
10V
10%
X5R
0402
COMMON
C684
.1UF
10V
10%
X5R
0402
COMMON
C671
.1UF
10V
10%
X5R
0402
COMMON
C717
.1UF
10V
10%
X5R
0402
COMMON
www.vinafix.vn
C749
1UF
6.3V
10%
X5R
0402
COMMON
C737
1UF
6.3V
10% 10% 10% 10%
X5R
0402
COMMON
C733
1UF
6.3V
10%
X5R
0402
COMMON
C734
1UF
6.3V
10%
X5R
0402
COMMON
C746
1UF
6.3V
10%
X5R
0402
COMMON
C736
1UF
6.3V
10%
X5R
0402
COMMON
C748
1UF
6.3V
10%
X5R X5RX5R X5R
0402
COMMON
C699
4.7UF
6.3V
10%
X5R
0603
COMMON
C727
.047UF
6.3V
10%
X5R
0402
COMMON
C726
.047UF
6.3V
X5R
0402
COMMON
C725
.047UF
6.3V
10%
X5R
0402
COMMON
C724
.047UF
6.3V
10%
X5R
0402
COMMON
C723
.047UF
6.3V
10%
X5R
0402
COMMON
C722
.047UF
6.3V
10%
X5R
0402
COMMON
C721
.047UF
6.3V
10%
0402
COMMON
C705
.047UF
6.3V
10%
X5R
0402
COMMON
C740
4.7UF
6.3V
10%
X5R
0603
COMMON
C712
.1UF
10V
10%
X5R
0402
COMMON
C711
.1UF
10V
X5R
0402
COMMON
C685
.1UF
10V
10%
X5R
0402
COMMON
C675
.1UF
10V
10%
X5R
0402
COMMON
C690
.1UF
10V
10%
X5R
0402
COMMON
C709
.1UF
10V
10%
X5R
0402
COMMON
C710
.1UF
10V
10%
0402
COMMON
C706
.047UF
6.3V
10%
X5R
0402
COMMON
C720
4.7UF
6.3V
10%
X5R
0603
COMMON
C691
.1UF
10V
10%
X5R
0402
COMMON
C683
.1UF
10V
X5R
0402
COMMON
C677
.1UF
10V
10%
X5R
0402
COMMON
C728
.1UF
10V
10%
X5R
0402
COMMON
C692
.047UF
6.3V
10%
X5R
0402
COMMON
C750
.1UF
10V
10%
X5R
0402
COMMON
C738
.1UF
10V
10%
0402
COMMON
U8
U8
G71-N-A2
BGA1148
CHANGED
R14
V14
W14
AB14
P15
R15
T15
V15
W15
AA15
AB15
GND
GND
GND
GND
GND
GND
GND
GND
GND
AC15
R16
T16
V16
W16
AA16
AB16
P18
R18
T18
V18
W18
AA18
AB18
AC18
P19
R19
T19
V19
W19
AA19
AB19
AC19
R21
T21
V21
W21
AA21
AB21
R22
T22
V22
W22
AA22
AB22
AC22
R23
V23
W23
AB23
P23
NVVDD
NVVDD_SENSE_GPUP22
NVVDD_GND_SENSE_GPU
FBVDDQ
L12
L13
J14
L14
J15
L15
J17
L17
J18
L18
J19
L19
J20
L20
J22
L22
J23
L23
L24
AF24
L25
M26
N26
P26
R26
U26
V26
W26
Y26
AB26
AC26
AD26
AE26
AF26
K28
U28
V28
W28
Y28
AA28
AD28
AE28
L29
AA29
U8
G71-N-A2
BGA1148
CHANGED
22<
18<
22<
18<
GND
G71-N-A2
BGA1148
CHANGED
M19
U19
Y19
AE19
AJ19
AL19
AT19
B20
P20
R20
T20
U20
V20
W20
AA20
AB20
AC20
AP20
F21
L21
P21
U21
Y21
AC21
AF21
AR21
D22
H22
U22
Y22
AF22
AK22
AT22
B23
M23
T23
U23
Y23
AA23
AC23
F24
AL24
AP24
D25
H25
P25
V25
W25
AC25
AF25
AJ25
AN25
B26
L26
T26
AA26
AR26
F27
AJ27
AL27
B29
E29
M29
R29
V29
W29
AB29
AG29
AM29
AR29
G30
AK30
K31
N31
T31
AA31
AD31
AG31
B32
E32
H32
AJ32
AM32
AR32
M33
R33
V33
W33
AB33
AE33
B35
E35
H35
L35
P35
U35
Y35
AC35
AF35
AJ35
AM35
AR35
AH14
600-10455-0002-001
design
LFarasati
B2
E2
H2
L2
P2
U2
Y2
AC2
AF2
AJ2
AM2
AP3
M4
R4
V4Y20
W4
AB4
AE4
B5
E5
H5
AJ5
AM5
AR5
K6
N6
T6
AA6
AD6
AG6
AT7
B8
E8
H8
M8
R8
V8
W8
AB8
AE8
AJ8
AM8
AP8
F10
AT10
B11
M11
T11
AA11
AD11
AF11
AK11
AP11
D12
P12
V12
W12
AJ12
AR12
F13
AL13
AT13
B14
H14
M14
P14
T14
U14
Y14
AA14
AC14
AE14
AP14
D15
H15
U15
Y15
AJ15
AR15
F16
L16
P16
U16
Y16
AC16
AF16
AL16
AT16
B17
P17
R17
T17
U17
V17
W17
Y17
AA17
AB17
AC17
AP17
D18
H18
M18
U18
Y18
AE18
AJ18
AR18
D19
H19
18 OF 24
9-FEB-2006
GND
INININ
IN
OUT
TAB
GND/ADJ
IN
D
S
G
C
E
B
POLYSWITCH
OUT
TAB
GND/ADJ
IN
OUT
TAB
GND/ADJ
IN
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
Page19: Power Supply I: A2V5, DDC5V, SAA7115, TMDS Supplies
F3V3 Supply
F3V3 = 3.3V @ 2.5A
0R FOR BYPASS
0805
L5
7_6x7_6
0
CHANGED
1uH
NO STUFF
C30
4.7UF
6.3V
10%
X5R
0603
NO STUFF
GND GND
ALTERNATES
C21
1000UF
NO STUFF
20%
6.3V
ALE
1.34A@105C
0.021
TH_D80P35
LB11
3V3
ALTERNATES
C48
100UF
NO STUFF
+/-20%
10V
ALE
0.14A@85C
N/A
TH_D50P20
GND
GND
C49
100UF
NO STUFF
20%
25V
ALE
0.3A
0.34R@105C
SMD_D60
GND
C900
4.7UF
6.3V
10%
X5R
0603
NO STUFF
CONTINUOUS_CURRENT=5.28A
DC_RESISTANCE=0.012R
GND
F3V3
C20
1000UF
NO STUFF
20%
6.3V
ALE
0.45A@105C
0.17R
SMD_D80
A2V5 Supply
SAA7115_VDD Supply
ADD MIN 100MM^2 COPPER AROUND THIS FOOTRPINT FOR HEAT DISSIPATION
EXT_12V
Worst Case Pdiss for 300mA
Res: 68.25R * 0.1A ^ 2 = 0.6825W
LDO: (12.96V-(0.3A*21.53R)-3.14)*0.3A=1W
RthetaJA for LDO must be < 70 C/W
R98
R97
GND
R96
68
5%
2512
NO STUFF
C133
1UF
16V
10%
X7R
0805
NO STUFF
68
5%
2512
NO STUFF
68
5%
2512
NO STUFF
12V_IN_R
GND
3
C132
.1UF
16V
10%
X7R
0603
NO STUFF
U14
AP2317S-3.3
FIXED 3.3V
GOI,IGOI,TO263
TO263
NO STUFF
LAYOUT NOTE:
2
4
1
7115_VDD = 3.3V @0.3A
F3V3
LB14
220R@100MHz
NO STUFF
BEAD_0603
C131
C116
4.7UF
.1UF
6.3V
16V
10%
10%
X5R
X7R
0805
0603
NO STUFF
NO STUFF
GND
GND
BYPASS TO F3V3
POWER NET RULES
NETF3V3 NET RULES
3.3V
3.3V
3.3V
5.0V 16MIL
2.5V 1.0A
C119
47UF
NO STUFF
+/-20%
16V
ALE
0.099A@85C
7.06R
TH_D50P20
Place in same location as SMD
GND
ALTERNATES
7115_VDD
C128
47UF
NO STUFF
20%
6.3V
ALE
0.15A@105C
0.76R
SMD_D50
F3V3
7115_VDD
IFP_IOVDD NET RULES
IFP_IOVDD
5V and DDC5V NET RULES
5V
DDC_5V
A2V5 NET RULES
A2V5
F3V3
7115_VDD
7115_VDD_ADJ
12V_IN_R
IFP_IOVDD
IFP_IOVDD_EN
IFP_IOVDD_EN*
5V
DDC_5V
A2V5
2.5A
0.3A
1.2A
0.1A5.0V
0.1A
MIN_WIDTHMAX_CURRENTVOLTAGE
16MIL
12MIL
10MIL
12MIL
16MIL
10MIL
10MIL
16MIL
16MIL
R94
121
Radj1
1%
0603
Radj2
C77
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
NO STUFF
R95
1K
1%
0603
NO STUFF
GND
F3V3
BYPASS TO F3V3
LB20
220R@100MHz
NO STUFF
BEAD_0805
C73
22UF
6.3V
20%
X5R
0805
COMMON
IFP_IOVDD
Current Draw
Single Link: I=0.28A
Dual Link/2x Single Link: I=0.56A
Single Link + Dual Link: I=0.84A
Dual Link + Dual Link: I=1.12A
U1
F3V3
C27
4.7UF
6.3V
10%
X5R
0603
COMMON
C28
.47UF
10V
10%
X5R
0603
COMMON
GNDGND
AZ2940D-2.5
FIXED 2.5V
IGO,IGOI
COMBINED_IGO
CHANGED
1
4
2
GND GND
3
C26
.47UF
10V
10%
X5R
0603
COMMON
GND
5V and DDC5V Supply
LAYOUT NOTE:
ADD MIN 200MM^2 COPPER AROUND THIS DPAK FOR HEAT DISSIPATION
12V
C882
4.7UF
25V
10%
X5R
1206
COMMON
GNDGND
C877
.1UF
16V
10%
X7R
0603
COMMON
U505
AZ7805DE1
VR=5V
IGO,IGOI
COMBINED_IGO
COMMON
1
GND GND
2
DDC5V = 5V @200mA
3
C875
.1UF
10V
10%
4
X5R
0402
COMMON
A2V5 = 2.5V @ 1A
C25
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
5V
C881
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
ALTERNATES
C13
47UF
NO STUFF
+/-20%
16V
ALE
0.099A@85C
7.06R
TH_D50P20
F501
200mA
1206
COMMON
21
DDC_5V
GND
GND
C14
47UF
COMMON
20%
6.3V
ALE
0.15A@105C
0.76R
SMD_D50
C938
220PF
50V
5%
C0G
0603
COMMON
A2V5
Stuffing Option for Adj LDO
TMDS IOVDD Backdrive Prevention
1G1D1S
R46
0402
1
2.2K
COMMON
5%
F3V3
IFP_IOVDD_EN
R37
309
1%
0402
CHANGED
1B1C1E
R36
100
1%
0402
CHANGED
IFP_IOVDD_EN*
3
Q1
MMBT2222A
1
SOT23_1B1C1E
COMMON
2
7115_VDD_ADJ
C134
.1UF
Cadj
16V
10%
X7R
0603
NO STUFF
GND
F3V3
FET Options:
1. VISHAY Si2305DS - NVPN: 300-0015-000
2. AOS AO3415 - NVPN: 300-0071-000 *default
3. ROHM RTR030P02 - NO NVPN
3
Q2
RTR030P02
SOT23_1G1D1S
CHANGED
2
MAX_VOLTAGE=-20V
CONTINUOUS_CURRENT=-3A@25C
R_DS_ON=0.125R MAX
MAX_CURRENT=-12A
MAX_WATTAGE=1W@25C
V_BE_GS=+/-12V
GND
GNDGND
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Power Supply I: A2V5, DDC5V, SAA7115, TMDS Supplies
www.vinafix.vn
600-10455-0002-001
design
LFarasati
19 OF 24
9-FEB-2006
D
SGS
D
G
OUT
OUT
OUT
OUT
OUT
S
D
G
S
D
G
S
D
G
IN
IN
PRSNT*
GND
12V
12V
12V
GND
INININININININININININININININININININININININ
IN
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
Page20: Power Supply II: PEX Input Filters, External 12V Power, NVVDD VID Control
Internal & External 12V Input Filters
12V Input Selection for NVVDD
INPUT FILTER FOR INTERNAL 12V
EXT_12V
6
3
EXT12V_PRSNT*
C135
4.7UF
16V
20%
X7R
1206
COMMON
GND
C136
.1UF
16V
10%
X7R
0603
COMMON
5
2
4
1
GND
J11
HDR_2M3
MALE
4.2MM
90
PCIEPWR
COMMON
12V
GND
C139
47UF
NO STUFF
+/-20%
16V
ALE
0.099A@85C
7.06R
TH_D50P20
GND
C138
100UF
COMMON
20%
25V
ALE
0.3A
0.34R@105C
SMD_D60
DC_RESISTANCE=0.012R
L11
COMMON7_6x7_6
MAX_CURRENT=8.0A
1uH
INPUT FILTER FOR EXTERNAL 12V
EXT_12V
GND
C140
47UF
NO STUFF
+/-20%
16V
ALE
0.099A@85C
7.06R
TH_D50P20
GND
C141
100UF
COMMON
20%
25V
ALE
0.3A
0.34R@105C
SMD_D60
DC_RESISTANCE=0.012R
L10
COMMON7_6x7_6
MAX_CURRENT=8.0A
1uH
Source FBVDDQ Switcher
Source NVVDD Switcher
INT_12V_IN
EXT_12V_IN
16<
23<
GPIO12_EXT12V_PRSNT
EXT12V_PRSNT*
Input from EXT PWR CON
0 = EXT_12V Connected
1 = EXT_12V Disconnected
NVVDD VID CONTROL
D509
BAT54C
25V
200MA
SOT23
NO STUFF
3
VOL_1
D512
BAT54C
25V
200MA
SOT23
1G1D1S
3
Q517
1
MIN_LINE_WIDTHMAX_CURRENT
50MIL
50MIL
50MIL
16<
16>
16>
16<
GPIO5_VSEL0
GPIO6_VSEL1
EXT_12V
INT_12V_IN
EXT_12V_IN
EXT_12V
INT_12V_IN
VOLTAGENET
12V
12V
12VEXT_12V_IN
5.5A
8A
8A
R569
0402
R581
0402
NV_CRITICALNET
20>
22<>
20>
22<>
20>
22<>
20>
22<>
NVVDD_VID1
NVVDD_VID2
NVVDD_VID3
NVVDD_VID4
VOL_1
VID1_VOL1
VID2_VOL1
VID3_VOL1
VID4_VOL1
VOL_2
VID1_VOL2
VID2_VOL2
VID3_VOL2
VID4_VOL2
VOL_DEF
VID1_VOL_DEF
VID2_VOL_DEF
VID3_VOL_DEF
VID4_VOL_DEF
GATE_DEF
GATE_DEF_R
12V_SELECT
EXT12V_PRSNT*
EXT12V_PRSNT_G*
NV_IMPEDANCE DIFFPAIR
12
D514
BAT54A
30V
200MA
F3V3
R588
10K
5%
0402
COMMON
GATE_DEF
SOT23
NO STUFF
3
D513
BAT54A
30V
200MA
SOT23
NO STUFF
SNN_GATE_NC
1
3
R580
0402
5%
GATE_DEF_R
2
0
COMMON
Default selection for NVVDD_VID[4..1]
www.vinafix.vn
2
10K
NO STUFF
5%
GND
1G1D1S
3
Q516
1
2
10K
NO STUFF
5%
GND
1G1D1S
1
10K
R570
NO STUFF
0402
5%
additional PDbridge diode
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Power Supply II: PEX Input Filters, External 12V Power, NVVDD VID Control
NO STUFF
3
RHK003N06
SOT23_1G1D1S
NO STUFF
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.3A@25C
R_DS_ON=1.5R
MAX_CURRENT=1.2A
MAX_WATTAGE=0.2W@25C
V_BE_GS=+/-20V
D508
BAT54C
25V
200MA
SOT23
NO STUFF
3
VOL_2
D511
BAT54C
25V
200MA
SOT23
NO STUFF
3
RHK003N06
SOT23_1G1D1S
NO STUFF
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.3A@25C
R_DS_ON=1.5R
MAX_CURRENT=1.2A
MAX_WATTAGE=0.2W@25C
V_BE_GS=+/-20V
D507
BAT54C
25V
200MA
SOT23
COMMON
3
VOL_DEF
D510
BAT54C
25V
200MA
SOT23
COMMON
3
3
Q515
RHK003N06
SOT23_1G1D1S
2
COMMON
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.3A@25C
R_DS_ON=1.5R
MAX_CURRENT=1.2A
MAX_WATTAGE=0.2W@25C
V_BE_GS=+/-20V
GND
2
1
2
1
2
1
2
1
2
1
2
1
Voltage1
VID1_VOL1
0
R547
NO STUFF
0402
5%
0
R549
NO STUFF
0402
5%
VID2_VOL1
VID3_VOL1
0
R553
NO STUFF
0402
5%
0
R558
NO STUFF
0402
5%
VID4_VOL1
Voltage2
VID1_VOL2
0
R546
NO STUFF
0402
5%
0
R551
NO STUFF
0402
5%
VID2_VOL2
VID3_VOL2
0
R555
NO STUFF
0402
5%
0
R572
NO STUFF
0402
5%
VID4_VOL2
Default
VID1_VOL_DEF
0
R548
NO STUFF
0402
5%
0
R550
NO STUFF
0402
5%
VID2_VOL_DEF
VID3_VOL_DEF
0
R554
NO STUFF
0402
5%
0
R559
COMMON
0402
5%
VID4_VOL_DEF
INT_12V_IN
R535
2.2K
D515
BAV99
SOT23
100V
100MA
COMMON
5%
0402
COMMON
C537 R543
1000PF
16V
10%
X7R
0402
COMMON
GND
EXT12V_PRSNT_G*
R537
0603
20K
5%
0402
COMMON
1G1D1S
GND
1K
COMMON
1%
GND
22<> 20<
22<> 20<
22<> 20<
22<> 20<
F3V3
2
3
1
GND
NVVDD_VID1
NVVDD_VID2
NVVDD_VID3
NVVDD_VID4
NVVDD Voltage Select
NVVDD range 0.8V-1.55V
Regulator: ISL6568
Control via NV_GPIOs NV_VSEL[2..0] :
VID NVVDD
4 3 2 1 Vout
1 1 1 1 0.80V
1 1 1 0 0.85V
1 1 0 1 0.90V
1 1 0 0 0.95V
1 0 1 1 1.00V
1 0 1 0 1.05V
1 0 0 1 1.10V
1 0 0 0 1.15V
0 1 1 1 1.20V
0 1 1 0 1.25V
0 1 0 1 1.30V
0 1 0 0 1.35V
0 0 1 1 1.40V
0 0 1 0 1.45V
0 0 0 1 1.50V
0 0 0 0 1.55V
Note: ISL6568 Controller can support
AMD HAMMER VID codes and
Intel VRM9/10 VID codes
The above uses AMD Hammer VID codes
=> Default
=> Voltage1
=> Voltage2
R544
0402
1
C533
.1UF
16V
10%
X7R
0603
COMMON
27K
COMMON
5%
=> Default
=> Voltage1
=> Voltage2
Q513
RHK003N06
SOT23_1G1D1S
COMMON
INT_12V_IN
R545
2.2K
5%
0402
COMMON
12V_SELECT
3
2
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.3A@25C
R_DS_ON=1.5R
MAX_CURRENT=1.2A
MAX_WATTAGE=0.2W@25C
V_BE_GS=+/-20V
GND
G70G71
1G4D1S
FET Options:
6
1. RSQ030P03 - 300-0084-000 *
5
1. AO6405 - 300-0083-000
2
1. SI3457DV - 300-0009-000
1
Q514
RSQ030P03
TSOP6_1G4D1S
3
COMMON
4
MAX_VOLTAGE=-30V
CONTINUOUS_CURRENT=-3A@25C
R_DS_ON=0.090R
MAX_CURRENT=-12A
MAX_WATTAGE=1.25W@25C
V_BE_GS=+/-20V
EXT_12V_IN
Bypass External Connector
N/A
N/A
N/A
EXT_12V_IN
0
NO STUFF
0
NO STUFF
0
NO STUFF
INT_12V_IN
R100
R101
1206
R99
1206
1206
STUFF WHEN EXT PWR CONN NOT STUFFED
600-10455-0002-001
design
LFarasati
20 OF 24
9-FEB-2006
INININININININININININININININININ
IN
S
D
G
S
D
G
UGATE
VCC12
PVCC5
BOOT
PHASE
LGATE
SW_FB
COMP
LDO_FB
FS_DIS
LDO_DR
VCC5
GND
PGNDSD
G
S
D
G
S
D
G
IN
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
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Page21: Power Supply III: FBVDDQ & PEX_VDD
FBVDDQ and PEX_VDD NET RULES
NET
1.8V 14A
5V
5V
14A1.8V
FBVDDQ NET RULES
FBVDDQ
FBVDDQ
FBVDDQ_VCC5
FBVDDQ_PVCC5
FBVDDQ_FS_DIS
NVVDD_PGOOD_EN*
FBVDDQ_BOOT
FBVDDQ_UGATE
FBVDDQ_UGATE_R
FBVDDQ_LGATE
FBVDDQ_LGATE_AC
FBVDDQ_SNUB
FBVDDQ_PHASE
FBVDDQ_COMP
FBVDDQ_COMP_RC
FBVDDQ_FB
FBVDDQ_FB_RC
MIN_WIDTHMAX_CURRENTVOLTAGE
16MIL
12MIL
12MIL
10MIL
10MIL
12MIL
16MIL
16MIL
16MIL
16MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
PEX = 1.2V @2A
PEX_VDD
C118
100UF
NO STUFF
+/-20%
10V
ALE
0.14A@85C
N/A
TH_D50P20 SMD_D60
Place in same location as SMD
GND
22< 22>
C122
100UF
COMMON
20%
25V
ALE
0.3A
0.34R@105C
GND
C108
22UF
6.3V
20%
X5R
0805
COMMON
F3V3
C114
4.7UF
6.3V
10%
X5R
0603
COMMON
R504
1K
5%
0402
COMMON
1G1D1S
1.2V 16MIL2A
12MIL
12MIL
12MIL
FBVDDQ
INT_12V_IN
PEX_VDD
PEX_VDD NET RULES
PEX_VDD
PEX_LDO_DR
PEX_LDO_RC
PEX_LDO_FB
Input Ripple = ~5.5A
C143
180UF
CHANGED
20%
16V
ALE
4.36A@105C
0.016R
COMBI_7343_D80
GND GND
2.2
R507
COMMON
0402
5%
SNN_FBVDDQ_LG_ACDRIVE
3
2
100V
100MA
SOT23
BAV99
D501
NO STUFF
0
50V
0603
5%
X7R
CHANGED
R2
4.22K
R532
COMMON
0402
1%
TP501
TESTPOINT2
SCHMOO
NO STUFF
1
TP506
TESTPOINT2
SCHMOO
NO STUFF
1
GND
*Default - No Stuff
FBVDDQ_UGATE_R
FBVDDQ_LGATE_AC
470
R501
NO STUFF
0402
5%
.022UFC523
16V0603
10%
X7R
COMMON
FBVDDQ
PLACE WITHIN 2cm AREA
C503
10UF
16V
20%
X5R
1206
NO STUFF
GND
GND
FBVDDQ_FB_RC
TP502
TESTPOINT2
SCHMOO
NO STUFF
1
C504
10UF
16V
20%
X5R
1206
NO STUFF
LFPAK
4
LFPAK
4
R533
FBVDDQ_FB
Place near Drain of Top Mosfet
GND
5
Q502
AO4420
SO8_1G4D3S
CHANGED
1
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=13.7A@25C,9.7A@70C
2
R_DS_ON=0.012R MAX
MAX_CURRENT=60A
3
MAX_WATTAGE=3.1W@25C,2W@70C
V_BE_GS=12V
5
Q501
AO4410
SO8_1G4D3S
CHANGED
1
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=18A@25C,15A@70C
2
R_DS_ON=0.0062R MAX
MAX_CURRENT=80A
3
MAX_WATTAGE=3@25C,2.1W@70C
V_BE_GS=12V
GND
R3C3
10
COMMON0402
5%
TP504
TESTPOINT2
SCHMOO
NO STUFF
1
C502
4.7UF
16V
20%
X7R
1206
COMMON
FET Options:
1. TOP - BSC059N03S, BOT - BSC032N03S
2. TOP - RLA130N03, BOT - RQA180N03
3. TOP - AOS4420, BOT - AOS4410
Output Inductor Options:
Vishay - 131-0025-000 3.0mOhm, 27A
Vishay - 131-0028-000 4.1mOhm, 23A
Delta - 131-0091-000 2.6mOhm, 27A *default
CONTINUOUS_CURRENT=27A
DC_RESISTANCE=0.0026R MAX
SMD_138x127
R502
2.2
5%
D502
1
RSX201L-30
SMA
30V
2A
2
COMMON
OUTPUT VOLTAGE
FBVDDQ
R526
1.5K
Rtop
1%
0603
CHANGED
R530
1K
Rbot
1%
0603
COMMON
GND
FBVDDQ = VREF * (1 + Rtop/Rbot)
FBVDDQ = 0.8V * (1 + 1.24K/1K) = 1.8V
FBVDDQ = 0.8V * (1 + 1.50K/1K) = 2.0V
TP503
TESTPOINT2
SCHMOO
NO STUFF
1
GND
0805
COMMON
FBVDDQ_SNUB
C505
820PF
50V
5%
C0G
0603
COMMON
GND
1.5uH
L9
COMMON
FBVDDQ = 1.8V - 2.0V @14A
Est. Eff = 85%
C535
C536
47UF
47UF
6.3V
6.3V
20%
20%
X5R
X5R
1206
1206
NO STUFF
NO STUFF
*Default - No Stuff
C126
1200UF
COMMON
+/-20%
4V
OSCON
5.44A@105C
0.012R
COMBI_7343D80D1001812
DC/DC calculator Rev 1.1
You need to enter values in the yellow fields.
Results will be shown in the blue fields.
Output current Iout 14.00 A
Output voltage Vout 1.8 V
Input voltage Vin 12.00 V
Loss less duty cycle DC 0.15
Switching frequency f 600 kHz
Inductance L 1.500 uH
Ripple current through the inductor Iripple 1.700 A
Maximum inductor current ILMax 14.850 A
Input
Input capacitor ripple current IRMS 5.303 A
Output
Output capacitor total ESR 12.00 mOhm
Output capacitor total capacitance Cout 1200.0 uF
Output ripple voltage deltaVout 20.577 mV
ALTERNATES
Place in the same location as SMD
GND
FBVDDQ
C125
1000UF
NO STUFF
+/-20%
4V
OSCON
5.04A@45C
0.012R
COMBI_TH_D80_D100
C1
.1UF
16V
10%
X7R
COMMON
2200PF
50V
10%
X7R
COMMON
C2
C144
180UF
CHANGED
20%
16V
ALE
4.36A@105C
0.016R
COMBI_7343_D80
GND
Place close to PVCC5 pin
C508
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
.1UF
C515
16V
0603
10%
X7R
COMMON
1
C501
0R default
FBVDDQ_COMP_RC
T3FQCOMP Spreadsheet
For PM=70deg, BW=100KHz, R1=1.24K
C1=102 nF, C2=3.61 nF, C3=33.9 nF
R2=4.13K, R3=11
Place close to MOSFET
C538
10UF
6.3V
20%
X5R
0805
COMMON
GND
COMBI_MONO_1G2D1S
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=10A@25C
R_DS_ON=0.028@10V
MAX_CURRENT=30A
MAX_WATTAGE=60W@25C
V_BE_GS=+/-20V
R528
C115
.047UF
16V
10%
X7R
0402
COMMON
GND
C107
22UF
6.3V
20%
X5R
0805
COMMON
GND
12V
3
Q505
RHK003N06
SOT23_1G1D1S
1NVVDD_PGOOD
COMMON
2
GND
1K
1%
0603
COMMON
R529
2K
1%
0603
COMMON
GND
Vout = 0.8V * (1 + Rtop/Rbot)
1.2V = 0.8V * (1 + 1K/2K)
STUFFING OPTION FOR G70
NVVDD->FBVDDQ Sequencing
R505
10K
5%
0402
COMMON
NVVDD_PGOOD_EN*
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.3A@25C
R_DS_ON=1.5R
MAX_CURRENT=1.2A
MAX_WATTAGE=0.2W@25C
V_BE_GS=+/-20V
FET Alternates:
IRFR3303PBF - 300-0043-000
IRLR3714 - 300-0016-000
AOD408 - 300-0059-000
AOD420 - 300-0082-000 *default
AOD420
CHANGED
4
2
Q3
3
Use large D2Pak Pad for up to 2W of Disipation
1G2D1S
1
Rtop
Rbot
1G1D1S
3
Q509
RHK003N06
SOT23_1G1D1S
1
COMMON
2
GND
Place close to VCC5 pin
R524
2.7K
5%
0402
COMMON
PEX_LDO_RC
C521
1000PF
16V
10%
X7R
0402
COMMON
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.3A@25C
R_DS_ON=1.5R
MAX_CURRENT=1.2A
MAX_WATTAGE=0.2W@25C
V_BE_GS=+/-20V
R508
10
5%
0805
COMMON
C512
.47UF
16V
10%
X7R
0603
COMMON
GND
FBVDDQ_VCC5
PEX_LDO_DR
PEX_LDO_FB
FBVDDQ_FS_DIS
R521
47.5K
1%
0402
COMMON
GND
FREQ_SET = 47.5K for 600khz
U501
ISL6549CB_600KHZ
VR_SW=0.8V, VR_LD=0.8V
SO14
SO14
COMMON
9
5
6
2
12
7
JEDEC_TYPE=SO14_I335X150
GND
Place close to VCC12 pin
12V
C516
1UF
16V
10%
X5R
0603
COMMON
GND
8
FBVDDQ_PVCC5
10
FBVDDQ_BOOT
1
FBVDDQ_UGATE
14
FBVDDQ_PHASE
13
FBVDDQ_LGATE
11
FBVDDQ_FB
4
FBVDDQ_COMP
3
Compensation for FBVDDQ
C525
0603
C524
0603
Shmoo TestPoints
TP505
TESTPOINT2
SCHMOO
NO STUFF
1
PEX_VDD
PLACE WITHIN 2cm AREA
PEX_LDO_FB
www.vinafix.vn
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Power Supply III: FBVDDQ and PEX1V2
600-10455-0002-001
design
LFarasati
21 OF 24
9-FEB-2006
Page22: Power Supply IV: NVVDD
INININININININININININININININININININININININININININININININININININ
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
IN
IN
2 Phase PWM
PVCC
BOOT1
UGATE1
PHASE1
ISEN1
LGATE1
PHASE2
BOOT2
UGATE2
ISEN2
LGATE2
ISUM
ICOMP
VID12_5
VDIFF
FB
COMP
VCC
REF
FS
OFS
ENLL
PGOOD
VID4
VID2
VID1
VID3
VID0
OCSET
IREF
RGND
VSEN
GND
BIBIBIBIOUTININ
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
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NVVDD NET RULES
EXT_12V_IN
C120
330UF
NO STUFF
20%
16V
ALE
5.05A/105C
0.014R
COMBI_TH_D80_D100
GND
ALTERNATES
Compensation
Place Compensation Components Close to IC
C513
0603
C517
0603
Cc
C1
.047UF
50V
10%
X7R
COMMON
.01UF
25V
10%
X7R
NO STUFF
NVVDD_COMP_RC
C3
C511
0603
NVVDD_FB_RC
Rfb
R512
0603
100PF
50V
5%
C0G
CHANGED
1%
For AMD Hammer Code
5K Res to +5V on VID12.5 Pin
A2V5
* Power sequencing Option
for G70 Compatibility
NVVDD_SENSE_GPU
18>
18<
18>
18<
NVVDD_GND_SENSE_GPU
R541
1K
1%
0402
NO STUFF
R538
2.21K
1%
0603
COMMON
GND
ENABLE:
ENLL has a 0.66V
precision threshold
0402
5%
R585
0402
5%
Rc
R514
0603
1%
Change C3 to 100pF if
1200uF OSCONs are stuffed
on output & C1/R3 NOSTUFF
R3
33.2
R510
NO STUFF
0603
1%
1K
COMMON
Vofs =
(0.5*Rfb)/Rofs
Open = No Offset
INT_12V_IN
R540
22.1K
1%
0603
COMMON
NVVDD
R517
0
5%
0402
NO STUFF
0R586
COMMON
0
COMMON
R513
0
5%
0402
NO STUFF
GND
5.9K
COMMON
5V
GND
GND
R519
0
5%
0402
COMMON
R516
0603
GND
20<
20<
20<
20<
22<
C527
1000PF
50V
10%
X7R
0603
NO STUFF
R523
0603
C519
1%
R515
0603
21<
Switching Freq = 300KHz/channel
5V
R511
0
5%
0603
COMMON
NVVDD_VCC
C518
Cf1
1UF
16V
10%
X5R
0603
COMMON
GND
NVVDD_COMP
NVVDD_FB
NVVDD_VDIFF
Rofs
NVVDD_OFS
10K
NO STUFF
0402
5%
NVVDD_FS
86.6K
COMMON
4.99K
COMMON
20>
20>
20>
20>
1%
NVVDD_REF
.022UF
50V
10%
X7R
COMMON
NVVDD_VID12_5
NVVDD_VID0
NVVDD_VID1
NVVDD_VID2
NVVDD_VID3
NVVDD_VID4
NVVDD_PGOOD
NVVDD_ENLL
NVVDD_SENSE_ISL
NVVDD_GND_SENSE_ISL
NVVDD_OCSET
GND
R520
3.57K
1%
0402
COMMON
Place Rcomp, Ccomp, Rs
near thier respective pins
on the ISL6568
DROOP
Input Ripple = ~ 7.5A
C121
330UF
COMMON
+/-20%
16V
OSCON
4.72A@105C
0.016R
COMBI_7343_D80_D100
GND
U502
ISL6568CRZ
DYNAMIC VID(0.8V..1.85V)
QFN32
QFN32
COMMON
4
5
6
7
3
29
2
1
32
31
30
21
22
28
20
9
8
13
10
TP
NVVDD_ICOMP
NVVDD_ISUM
Rcomp
66.5K
R518
COMMON
0402
C522
0603
1%
Ccomp
.01UF
25V
10%
X7R
COMMON
R525
R522
C526
.01UF
25V
10%
X7R
0603
COMMON
C142
330UF
NO STUFF
20%
16V
ALE
5.05A/105C
0.014R
COMBI_TH_D80_D100
GND
ALTERNATES
*Note: SMD OSCONs are $0.06 extra per cap.
NVVDD_PVCC
C534
4.7UF
16V
10%
X7R
1206
COMMON
GND
15
NVVDD_BOOT1
24
NVVDD_UGATE1
25
NVVDD_PHASE1
23
NVVDD_ISEN1
26
NVVDD_LGATE1
27
NVVDD_BOOT2
18
NVVDD_UGATE2
17
NVVDD_PHASE2
19
NVVDD_ISEN2
16
NVVDD_LGATE2
14
12
11
0402
Rs1
Rs2
1%
1%
82.5K
COMMON
82.5K
COMMON0402
NVVDD_PHASE1
NVVDD_PHASE2
C137
1
330UF
COMMON
+/-20%
2
16V
OSCON
4.72A@105C
0.016R
COMBI_7343_D80_D100
GND
NVVDD
0
R536
COMMON
0603
5%
C_BOOT1
.1UF
C528
25V
0603
10%
X7R
COMMON
2.2
R531
COMMON
0402
5%
R_ISEN1
1.8K
R527
COMMON
0603
5%
Place near ISEN1 Pin
Place near ISEN2 Pin
SNN_NVVDD_LG1_ACDRIVE
3
NVVDD_LG1_AC
2
1
100V
SOT23
100MA
BAV99
D505
NO STUFF
0R Default
0
C514
50V
0603
5%
X7R
CHANGED
Stuff cap to improve Cgs/Cgd ratio!
R_ISEN2
1.8KR539
COMMON
0603
5%
22<
22<
Stuff cap to improve Cgs/Cgd ratio!
C520
16V
20%
X5R
1206
NO STUFF
*Default = No Stuff
R509
470
5%
0402
NO STUFF
GND
C_BOOT2
C531
R542
0402
1
BAV99
D504
0R Default
C506
0603
www.vinafix.vn
C529
10UF10UF
16V
20%
X5R
1206
NO STUFF
GNDGND
LFPAK
4NVVDD_UG1_RG
LFPAK
4
.1UF
25V0603
10%
X7R
COMMON
5%
SNN_NVVDD_LG2_ACDRIVE
3
100V
SOT23
0
50V
5%
X7R
CHANGED
2.2
COMMON
100MA
NO STUFF
NVVDD_UG2_RG
2
Place near Drain of Top Mosfet
C510
4.7UF
16V
20%
X7R
1206
COMMON
GND
5
Q507
AOL1432
LFPAK
CHANGED
1
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=12A@25C
2
R_DS_ON=12mOHM MAX
MAX_CURRENT=44A
3
MAX_WATTAGE=2.1W@25C
V_BE_GS=+/-20V
5
Q506
AOL1408
LFPAK
CHANGED
1
2
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=85A
3
R_DS_ON=5.2mOHM
MAX_CURRENT=85A@25C
MAX_WATTAGE=2.1W@25C
V_BE_GS=+/-20V
GND
LFPAK
4
LFPAK
4
LFPAK
4
LFPAK
NVVDD_LG2_AC
R503
470
5%
0402
NO STUFF
GND
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Power Supply IV: NVVDD
4
Notes: LFPAK Footprint allows S08 alternates
FET Options:
1. TOP - AO4422 (SO8), BOT - 2XAO4410
2. TOP - RLA130N03(SO8), BOT - 2xRQA200N03
3. TOP - BSC059N03S, BOT - BSC032N03S *default
4. TOP - RQW160N03, BOT - 2 x RQW180N03
5. TOP - AOL1418, BOT - 2 x AOL1408
6. TOP - RJK0305DPB, BOT - 2 x RJK0304DPB
5
Q512
BSC059N03S
LFPAK
NO STUFF
1
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A
2
R_DS_ON=5.5mR
MAX_CURRENT=200A
3
MAX_WATTAGE=2.8W
V_BE_GS=+/-20V
5
Q511
BSC032N03S
LFPAK
NO STUFF
1
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A
2
R_DS_ON=3.2mR
MAX_CURRENT=200A
3
MAX_WATTAGE=2.8W
V_BE_GS=+/-20V
EXT_12V_IN
Place near Drain of Top Mosfet
C509
4.7UF
16V
20%
X7R
1206
COMMON
GND
5
Q508
AOL1432
LFPAK
CHANGED
1
MAX_VOLTAGE=25V
CONTINUOUS_CURRENT=12A@25C
2
R_DS_ON=12mOHM MAX
MAX_CURRENT=44A
3
MAX_WATTAGE=2.1W@25C
V_BE_GS=+/-20V
5
Q504
BSC032N03S
LFPAK
NO STUFF
1
2
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A
3
R_DS_ON=3.2mR
MAX_CURRENT=200A
MAX_WATTAGE=2.8W
V_BE_GS=+/-20V
GND
LFPAK
LFPAK
D506
1
RSX201L-30
SMA
30V
2A
2
COMMON
GND
4
4
Output Inductor Options:
1. Delta HCH1378-1R0NV - 131-0014-000
2. Vishay IHLP5050EZER1R0 - 131-0003-000
CONTINUOUS_CURRENT=32A
DC_RESISTANCE=0.0015 MAX
SMD_590x530
R506
1
5%
0805
COMMON
NVVDD_SNUB1
C507
1500PF
50V
10%
X7R
0603
COMMON
GND
Place near Low Side Mosfet
Notes: LFPAK Footprint allows S08 alternates
FET Options:
1. TOP - AO4422 (SO8), BOT - 2 X AO4430
2. TOP - RLA130N03(SO8), BOT - 2 x RQA200N03
3. TOP - BSC059N03S, BOT - 2 x BSC032N03S *default
4. TOP - RQW160N03, BOT - 2 x RQW180N03
5. TOP - AOL1418, BOT - 2 x AOL1408
6. TOP - RJK0305DPB, BOT - 2 x RJK0304DPB
5
Q503
BSC059N03S
LFPAK
NO STUFF
1
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A
2
R_DS_ON=5.5mR
MAX_CURRENT=200A
3
MAX_WATTAGE=2.8W
V_BE_GS=+/-20V
5
Q510
AOL1408
LFPAK
CHANGED
1
MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=85A
2
R_DS_ON=5.2mOHM
MAX_CURRENT=85A@25C
3
MAX_WATTAGE=2.1W@25C
V_BE_GS=+/-20V
1uH
L7
COMMON
6.3V
20%
X5R
1206
NO STUFF
GND
Output Inductor Options:
1. Delta HCH1378-1R0NV - 131-0014-000
2. Vishay IHLP5050EZER1R0 - 131-0003-000
D503
1
RSX201L-30
SMA
30V
2A
2
COMMON
NVVDD = 1.0V..1.2V (30..45A)
C541C532
47UF47UF
6.3V
20%
X5R
1206
NO STUFF
CONTINUOUS_CURRENT=32A
DC_RESISTANCE=0.0015 MAX
L8
SMD_590x530
R534
1
5%
0805
COMMON
NVVDD_SNUB2
C530
1500PF
50V
10%
X7R
0603
COMMON
GNDGND
Place near Low Side Mosfet
NET
NVVDD
22<
22<
NVVDD
NVVDD_PVCC
NVVDD_VCC
NVVDD_BOOT1
NVVDD_UGATE1
NVVDD_UG1_RG
NVVDD_PHASE1
NVVDD_LGATE1
NVVDD_LG1_AC
NVVDD_BOOT2
NVVDD_UGATE2
NVVDD_UG2_RG
NVVDD_PHASE2
NVVDD_LGATE2
NVVDD_LG2_AC
NVVDD_ISEN1
NVVDD_ISEN2
NVVDD_SNUB1
NVVDD_SNUB2
NVVDD_COMP
NVVDD_FB
NVVDD_COMP_RC
NVVDD_FB_RC
NVVDD_VDIFF
NVVDD_ISUM
NVVDD_ICOMP
NVVDD_OCSET
NVVDD_REF
NET
NVVDD_VID0
NVVDD_VID12_5
21< 22>
C130
1200UF
COMMON
+/-20%
4V
OSCON
5.44A@105C
0.012R
COMBI_7343D80D1001812
GND
C129
1000UF
NO STUFF
+/-20%
4V
OSCON
5.04A@45C
0.012R
COMBI_TH_D80_D100
GND
NVVDD_PGOOD
NVVDD_ENLL
NVVDD_OFS
NVVDD_FS
NVVDD_SENSE_ISL
NVVDD_GND_SENSE_ISL
Place in same location as SMD
1uH
COMMON
C546
47UF
6.3V
20%
X5R
1206
NO STUFF
Place on Bottom
*Default = No Stuff
GND
C547
47UF
6.3V
20%
X5R
1206
COMMON
1.2V
12V
5V
C124
1200UF
COMMON
+/-20%
4V
OSCON
5.44A@105C
0.012R
COMBI_7343D80D1001812
GND
C117
1000UF
NO STUFF
+/-20%
4V
OSCON
5.04A@45C
0.012R
COMBI_TH_D80_D100
GND
C542
47UF
6.3V
20%
X5R
1206
NO STUFF
Place on Bottom
C539
47UF
6.3V
20%
X5R
1206
COMMON
design
LFarasati
C123
1200UF
COMMON
+/-20%
4V
OSCON
5.44A@105C
0.012R
COMBI_7343D80D1001812
GND
C127
1000UF
NO STUFF
+/-20%
4V
OSCON
5.04A@45C
0.012R
COMBI_TH_D80_D100
GND
600-10455-0002-001
50A
0.003A
0.02A
25A
25A
ALTERNATESALTERNATESALTERNATES
MIN_WIDTHMAX_CURRENTVOLTAGE
DIFFPAIRNV_IMPEDANCENV_CRITICAL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
20MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
10MIL
NVVDD
22 OF 24
9-FEB-2006
FAN
+12V
GND
S
D
G
S
D
G
S
D
G
IN
OUT
IN
VDD
THERM
ALERT
GND
D+
D-
SDA
SCL
BI
19/24 THERMAL
THERMDN (CATHODE)
THERMDP (ANODE)
INININININININININININ
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
Page23: Thermal Diode, Fan Control
EXTERNAL THERMAL DIODE
U8
G71-N-A2
BGA1148
CHANGED
THERMDN
D- Connects to CATHODE
D+ Connects to ANODE
T1
THERMDP
U1
16< 16<> 14<>
THERM_ALERT*
16< 20>
16< 20>
GPIO12_EXT12V_PRSNT
THERM_ALERT*
GPIO12_EXT12V_PRSNT
C81
2200PF
50V
10%
X7R
0402
NO STUFF
14<
16> 16<
Bypass for AND Gate
1
2
13<
13<>
F3V3
GND
R679
R677
0402
0402
5
3
U503
SN74LVC1G08
4
SC70-5
NO STUFF
0
NO STUFF
5%
0
COMMON
5%
I2CC_SCL
I2CC_SDA 7
F3V3
C852
.1UF
10V
10%
X5R
0402
NO STUFF
Place near AND Gate
GND
GPIO8_GPU_SLOW_R*
2
3
8
U6
LM99CIMM
SO8_122MIL
NO STUFF
0402
1%
1
THERM_THERM*
4
THERM_ALERT*
6
5
1KR678
NO STUFF
F3V3
GND
GND
C74
.1UF
10V
10%
X5R
0402
NO STUFF
GPIO8_GPU_SLOW*
F3V3
R52
2.2K 2.2K
5%
0402
NO STUFF
F3V3
R683
5%
0402
NO STUFF
16<
FAN CONTROL
GPIO2_FAN_CTRL
FAN=OFF
FAN=ON
THERM_THERM*
12V
4-WIRE FAN CONNECTOR
1
2
3
4
GND
1
2
2-WIRE FAN CONNECTOR
J10
HDR_1M4
MALE
2.0MM
N/A
NORM
NO STUFF
J9
HDR_1M2_FAN
MALE
2.5MM
0
NORM
COMMON
GND
1
GPIO9_FAN_CTRL_R
C895
1UF
16V
20%
X7R
0805
COMMON
Q520
AO3414
SOT23_1G1D1S
COMMON
12V
D517
1
BAT43
SOD323
40V
400MA
2
COMMON
FAN_PWM_C
3
2
GND
MAX_VOLTAGE=20V
CONTINUOUS_CURRENT=3.2A@70C
R_DS_ON=0.063@2.5V
MAX_CURRENT=15A
MAX_WATTAGE=0.9W@70C
V_BE_GS=8V
22uH
L6
SMD_4_5X4_0MM
R25
0603
Inductor Bypass for PWM Mode
Alternate: RTR040N03 - 300-0097-000
5%
COMMON
0
NO STUFF
SNN_4PINFAN_PIN2
C61
.1UF
16V
10%
X7R
COMMON
FAN_PWM_D
C59
4.7UF
16V
20%
X7R
12060603
COMMON
33
R32
NO STUFF
0402
5%
F3V3
R712
1K
1%
0402
NO STUFF
1G1D1S
1
R713
1K
1%
0402
COMMON
GND
1G1D1S
1
R718
1K
1%
0402
COMMON
3
Q519
RHK003N06
SOT23_1G1D1S
COMMON
2
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.3A@25C
R_DS_ON=1.5R
MAX_CURRENT=1.2A
MAX_WATTAGE=0.2W@25C
V_BE_GS=+/-20V
FAN_PWM_T
3
Q518
RHK003N06
SOT23_1G1D1S
NO STUFF
2
MAX_VOLTAGE=60V
CONTINUOUS_CURRENT=0.3A@25C
R_DS_ON=1.5R
MAX_CURRENT=1.2A
MAX_WATTAGE=0.2W@25C
V_BE_GS=+/-20V
GND
FAN_PWM_B
R714
0
5%
0402
COMMON
GND
1G1D1S
THERM FAN CTRL BYPASS
NET
FAN_PWM_B
FAN_PWM_C
FAN_PWM_D
FAN_PWM_T
THERM_THERM*
23>
THERM_ALERT*
GPIO8_GPU_SLOW_R*
NET
THERMDN
THERMDP
NV_IMPEDANCENV_CRITICAL
DIFFPAIR
MIN_WIDTH
10MIL
10MIL
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Thermal Diode, Fan Control
www.vinafix.vn
600-10455-0002-001
design
LFarasati
23 OF 24
9-FEB-2006
1
5
4
3
2
F G H
PAGE
DATE
SANTA CLARA, CA 95050, USA
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
NV_PN
ID
NAME
ED
ASSEMBLY
PAGE DETAIL
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
B C
2
A
1
3
4
5
E GD F HCA B
MECH. MOUNTING TOP
Page24: Mechanical: Bracket/Thermal Solution
Brackets:
151-10001-0006-000 DVI,DVI,MDIN (text - 1-South, 2-North)
151-10001-0006-002 DVI,DB15,MDIN
Connector Screws Bracket Screw
MEC1
BKT1
DVI3152_DVI1552_MDIN490_TEXT_1_2_TAB
ATX_1X_TOP
COMMON
1
GND
HEX_JACK_SCREW
STD
COMMON
MEC4
HEX_JACK_SCREW
STD
COMMON
MEC3
HEX_JACK_SCREW
STD
COMMON
MEC2
HEX_JACK_SCREW
STD
COMMON
MEC5
PH_4_40X.1875_SCREW
STD
COMMON
new LF screw --155-0001-000.
ROHS screw --154-0003-700.
Stiffener for WS SKUs
MEC6
STF_7800_SINGLE
GND-2PL
NO STUFF
1
2
GND
Heatsink
MEC8
TM34E_BLANK
GND-6PL
COMMON
MEC7
TM38E
GND-9PL
1
2
3
4
5
6
GND
NO STUFF
1
2
3
4
5
6
7
8
9
BGA Socket
MEC9
BGA_SOCKET
GND-4PL
NO STUFF
1
2
3
4
GND
GND
G71-GS - 256MB-8Mx32 GDDR3, DVI-I-DL + DVI-I-DL + HDTV, 450/700 MHz for Dell HMGA
Mechanical: Bracket/Thermal Solution
www.vinafix.vn
600-10455-0002-001
design
LFarasati
24 OF 24
9-FEB-2006
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