Power Sequence Circuit to ensure SMPS_EN is released after
+12V_BUS and +3.3V_BUS are both in regulation.
Pull-up may or may not be required on SMPS_EN signal depending
on SMPS design.
AA
8
7
6
Node 1 When +12V ramps above min Vbe, SMPS_EN will be helt low
When +3.3V gets close to regulation, one of the two
Node 2
conditions of releasing SMPS_EN is active
Target ~ 900mV when +3.3 at min regulation (worse case)
Typical trigger when +3.3V ramps above 2.2V (650mV)
Node 3 When +12V gets close to regulation, one of the two
conditions of releasing SMPS_EN is active
Target ~ 1.25V when +12 at min regulation (worse case)
Typical trigger when +12V ramps above 10V (1.1V)
5
www.vinafix.vn
4
ATI Technologies Inc.
ATI Technologies Inc.
ATI Technologies Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Canada, L3T 7X6
Canada, L3T 7X6
Canada, L3T 7X6
(905) 882-2600
(905) 882-2600
(905) 882-2600
Title
Title
Title
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
C
C
C
Date:Sheet
Date:Sheet
3
Date:Sheet
2
105-A67700-00A
105-A67700-00A
105-A67700-00A
SYMBOL LEGEND
DNI
DO NOT
INSTALL
#
ACTIVE
LOW
DIGITAL
GROUND
ANALOG
GROUND
119Tuesday, December 20, 2005
119Tuesday, December 20, 2005
119Tuesday, December 20, 2005
1
1
1
1
of
of
of
Page 2
5
DD
4
3
2
1
NOTE: some of the PCIE testpoints will
be available trought via on traces.
PETp0_GFXRp0[1]
PETn0_GFXRn0[1]
PETp1_GFXRp1[1]
PETn1_GFXRn1[1]
PETp2_GFXRp2[1]
PETn2_GFXRn2[1]
PETp3_GFXRp3[1]
PETn3_GFXRn3[1]
PETp4_GFXRp4[1]
PETn4_GFXRn4[1]
PETp5_GFXRp5[1]
PETn5_GFXRn5[1]
PETp6_GFXRp6[1]
CC
BB
PETn6_GFXRn6[1]
PETp7_GFXRp7[1]
PETn7_GFXRn7[1]
PETp8_GFXRp8[1]
PETp9_GFXRp9[1]
PETn9_GFXRn9[1]
PETp10_GFXRp10[1]
PETn10_GFXRn10[1]
PETp11_GFXRp11[1]
PETn11_GFXRn11[1]
PETp12_GFXRp12[1]
PETn12_GFXRn12[1]
PETp13_GFXRp13[1]
PETn13_GFXRn13[1]
PETp14_GFXRp14[1]
PETn14_GFXRn14[1]
PETp15_GFXRp15[1]
PETn15_GFXRn15[1]
PCIE_REFCLKP[1]
PCIE_REFCLKN[1]
DNIDNI
R13
R13
51R
51R
402402
PERST#_buf[1]
R14
R14
51R
51R
For Tektronix LA only
Place close
to ASIC
TP11TP11
TP12TP12
TP13TP13
TP14TP14
TP19TP19
TP20TP20
TP21TP21
TP22TP22
TP27TP27
TP28TP28
R11
R11
4.7K
4.7K
402
TP7TP7
TP8TP8
TP9TP9
TP10TP10
TP15TP15
TP16TP16
TP17TP17
TP18TP18
TP23TP23
TP24TP24
TP25TP25
TP26TP26
+3.3V
DNI
AJ31
AH31
AH30
AG30
AG32
AF32
AF31
AE31
AE30
AD30
AD32
AC32
AC31
AB31
AB30
AA30
AA32
AL28
AK28
AG24
AA24
AF24
Y32
Y31
W31
W30
V30
V32
U32
U31
T31
T30
R30
R32
P32
P31
N31
U1A
U1A
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
Clock
Clock
PCIE_REFCLKP
PCIE_REFCLKN
PERSTB
PCIE_TEST
NC
RV530 unfused A11
RV530 unfused A11
PART 1 OF 7
PART 1 OF 7
P
P
C
C
I
I
-
E
E
X
X
P
P
R
R
E
E
S
S
S
S
I
I
N
N
T
T
E
E
R
R
F
F
A
A
C
C
E
E
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
Calibration
Calibration
PCIE_CALRN
PCIE_CALRP
PCIE_CALI
AK27
AJ27
AJ25
AH25
AH28
AG28
AG27
AF27
AF25
AE25
AE28
AD28
AD27
AC27
AC25
AB25
AB28
AA28
AA27
Y27
Y25
W25
W28
V28
V27
U27
U25
T25
T28
R28
R27
P27
AE24
AD24
AB24
GFXTp0_PERp0 [1]
GFXTn0_PERn0 [1]
GFXTp1_PERp1 [1]
GFXTn1_PERn1 [1]
GFXTp2_PERp2 [1]
GFXTn2_PERn2 [1]
GFXTp3_PERp3 [1]
GFXTn3_PERn3 [1]
GFXTp4_PERp4 [1]
GFXTn4_PERn4 [1]
GFXTp5_PERp5 [1]
GFXTn5_PERn5 [1]
GFXTp6_PERp6 [1]
GFXTn6_PERn6 [1]
GFXTp7_PERp7 [1]
GFXTn7_PERn7 [1]
GFXTp8_PERp8 [1]
GFXTn8_PERn8 [1]PETn8_GFXRn8[1]
GFXTp9_PERp9 [1]
GFXTn9_PERn9 [1]
GFXTp10_PERp10 [1]
GFXTn10_PERn10 [1]
GFXTp11_PERp11 [1]
GFXTn11_PERn11 [1]
GFXTp12_PERp12 [1]
GFXTn12_PERn12 [1]
GFXTp13_PERp13 [1]
GFXTn13_PERn13 [1]
GFXTp14_PERp14 [1]
GFXTn14_PERn14 [1]
GFXTp15_PERp15 [1]
GFXTn15_PERn15 [1]
402
R82.0KR82.0K
402
R9562RR9562R
R101.47KR101.47K
+PCIE
402
AA
ATI Technologies Inc.
ATI Technologies Inc.
ATI Technologies Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Canada, L3T 7X6
Canada, L3T 7X6
Canada, L3T 7X6
(905) 882-2600
(905) 882-2600
(905) 882-2600
Title
Title
Title
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
C
C
C
Date:Sheet
Date:Sheet
5
4
www.vinafix.vn
3
2
Date:Sheet
105-A67700-00A
105-A67700-00A
105-A67700-00A
1
1
1
1
of
of
of
219Friday, December 16, 2005
219Friday, December 16, 2005
219Friday, December 16, 2005
Page 3
5
DD
+T2PVDD
C227
C227
C226
NS15NS_VIA NS15NS_VIA
12
CC
I2C DEVICE ADDRESS' ON DDC3
DEVICE
LM63
BB
EC82 15PFEC82 15PF
EC83 15PFEC83 15PF
+T2XVDDR
C225
C225
NS19NS_VIA NS19NS_VIA
10uF
10uF
1uF_6.3V
12
GND_T2XVSSR
ADDRESS
x100 1100
EY82
EY82
27_MHZ
27_MHZ
21
Change to 10ppm/10ppm p/n 5028270000G
1uF_6.3V
TESTEN[1]
+3.3V
C224
C224
1uF_6.3V
1uF_6.3V
R33
R33
4.7K
4.7K
402402
+3.3V
+3.3V
R841MR84
1M
GND_T2PVSS
C223
C223
R34
R34
4.7K
4.7K
MR2410KDNIMR2410KDNI
R2410KR2410K
Overlap Footprints
R25499RR25499R
R26499RR26499R
XTALIN
XTALOUT
1uF_6.3V
1uF_6.3V
C222
C222
1uF_6.3V
1uF_6.3V
C226
1uF_6.3V
1uF_6.3V
C221
C221
1uF_6.3V
1uF_6.3V
CRT1DDCDATA[13]
CRT1DDCCLK[13]
CRT2DDCDATA[14]
CRT2DDCCLK[14]
4
U1B
U1B
AL18
T2XCM
AM18
T2XCP
AK19
T2X0M
AL19
T2X0P
AL20
T2X1M
AM20
T2X1P
AL21
T2X2M
AM21
T2X2P
AK18
T2X3M
AJ18
T2X3P
AH18
T2X4M
AG18
T2X4P
AJ20
T2X5M
AK20
T2X5P
AE19
T2PVDD
AE18
T2PVSS
AF20
T2XVDDR_1
AE20
T2XVDDR_2
AF19
T2XVDDR_3
AC21
T2XVDDR_4
AC22
T2XVDDR_5
AD22
T2XVDDR_6
AE21
T2XVDDR_7
AD21
T2XVDDR_8
AE22
T2XVDDR_9
AF22
T2XVSSR_1
AF17
T2XVSSR_2
AF21
T2XVSSR_3
AK17
T2XVSSR_4
AJ19
T2XVSSR_5
AF18
T2XVSSR_6
AH17
T2XVSSR_7
AG17
T2XVSSR_8
AG19
T2XVSSR_9
AH19
T2XVSSR_10
AH22
DDC1DATA
AH23
DDC1CLK
AH13
DDC2DATA
AG13
DDC2CLK
AE12
DDC3DATA
AF12
DDC3CLK
TESTEN
VREFG
XTALIN
XTALOUT
AF11
AE13
AF13
AG12
AH12
AG14
AG22
AL26
AM26
AC8
HPD1
SDA
SCL
DPLUS
DMINUS
PLLTEST
TESTEN
VREFG
XTALIN
XTALOUT
RV530 unfused A11
RV530 unfused A11
HPD1[14]
Integrated
Integrated
TMDS2
TMDS2
Monitor
Monitor
Interface
Interface
MMI2C
MMI2C
Thermal
Thermal
Diode
Diode
Test
Test
XTAL
XTAL
PART 2 OF 7
PART 2 OF 7
V
V
I
I
D
D
E
E
O
O
&
&
M
M
U
U
L
L
T
T
I
I
M
M
E
E
D
D
I
I
A
A
Integrated
Integrated
TMDS
TMDS
TXVDDR_1
TXVDDR_2
TXVDDR_3
TXVDDR_4
TXVSSR_1
TXVSSR_2
TXVSSR_3
TXVSSR_4
TXVSSR_5
DAC / CRT
DAC / CRT
DAC2 (TV/CRT2)
DAC2 (TV/CRT2)
A2VSSN_1
A2VSSN_2
NC_A2VDDQ
TXCM
TXCP
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TX3M
TX3P
TX4M
TX4P
TX5M
TX5P
TPVDD
TPVSS
HSYNC
VSYNC
RSET
AVDD_1
AVDD_2
AVSSQ
AVSSN_1
AVSSN_2
VDD1DI
VSS1DI
H2SYNC
V2SYNC
COMP
R2SET
A2VDD_1
A2VDD_2
A2VSSQ
VDD2DI
VSS2DI
AL9
AM9
AK10
AL10
AL11
AM11
AL12
AM12
AK9
AJ9
AK11
AJ11
AK12
AJ12
AM8
AL8
AJ6
AK6
AL6
AM6
AJ7
AK7
AL7
AM7
AK8
AK24
R
AM24
G
AL24
B
AJ23
AJ22
AL22
AL25
AM25
AK23
AK25
AJ24
AM23
AL23
AK15
R2
AM15
G2
AL15
B2
AF15
AG15
AJ15
Y
AJ13
C
AH15
AK14
AM16
AL16
AM17
AL17
AK13
AJ16
AJ17
AL14
3
C246
C246
C247
C247
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
+TXVDDR
C249
C249
C250
C250
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
A_R_DAC1 [13]
A_G_DAC1 [13]
A_B_DAC1 [13]
A_HSYNC_DAC1 [1,7,13]
A_VSYNC_DAC1 [7,13]
RSET
R31499R
R31499R
+AVDD
GND_AVSSQ
+VDD1DI
R2SETGND_A2VSSQ
R32715RR32715R
+A2VDD
C56
C56
10nF
10nF
+VDD2DI
C59
C59
10nF
10nF
GND_AVSSQ
RESISTOR, 499R 1% 1/16W EIA(0402)
RESISTOR, 499R 1% 1/16W EIA(0402)
C62
C62
C63
C63
100nF
100nF
10nF
10nF
C54
C54
C53
C53
100nF
100nF
10nF
10nF
A_R_DAC2 [14]
A_G_DAC2 [14]
A_B_DAC2 [14]
A_HSYNC_DAC2 [7,14]
A_VSYNC_DAC2 [7,14]
DAC2_Y[15]
DAC2_C[15]
DAC2_COMP [15]
C58
C58
C57
C57
100nF
100nF
1uF_6.3V
1uF_6.3V
C60
C60
1uF_6.3V
1uF_6.3V
C251
C251
10uF
10uF
+TPVDD
C64
C64
1uF_6.3V
1uF_6.3V
C55
C55
1uF_6.3V
1uF_6.3V
NS14 NS_VIANS14 NS_VIA
GND_TPVSS
NS13 NS_VIANS13 NS_VIA
GND_TXVSSR
NS8 NS_VIANS8 NS_VIA
NS9 NS_VIANS9 NS_VIA
NS10 NS_VIANS10 NS_VIA
Place close to ASIC
12
12
NS5 NS_VIANS5 NS_VIA
GND_AVSSQ
NS6 NS_VIANS6 NS_VIA
GND_AVSSN
NS7 NS_VIANS7 NS_VIA
GND_VSS1DI
GND_A2VSSN
GND_A2VSSQ
GND_VSS2DI
2
R136182RR136182R
R132182RR132182R
R133182RR133182R
R134182RR134182R
R135182RR135182R
R131182RR131182R
R130182R
R130182R
LF RESISTOR 324R 1% 1/16W EIA(0402)
LF RESISTOR 324R 1% 1/16W EIA(0402)
12
12
12
12
12
12
TjXCM[14]
TjXCP[14]
TjX0M[14]
TjX0P[14]
TjX1M[14]
TjX1P[14]
TjX2M[14]
TjX2P[14]
TjX3M[14]
TjX3P[14]
TjX4M[14]
TjX4P[14]
TjX5M[14]
TjX5P[14]
1
AA
ATI Technologies Inc.
ATI Technologies Inc.
Place R_RTCLK close to XTAL so the
main clock line has shortest stub
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)
GPIO(3:2) - Miscellaneous PCI-Express Modes
00: Halt impedance calibration before transmitter is enabled and enable receiver detection (Default
setting for Desktop)
01: Allow impedance calibration to continue on in the background AFTER transmitter has
been enabled and enable receive detection.
10: Bypass common-mode detection & receiver detection and halt impedance calibration before TX_EN.
11: Short-circuit internal loopback and halt impedance calibration before TX_EN and enable
receiver detection.
GPIO(4) - DEBUG_ACCESS: 0 for normal operation, 1 for debug mode
GPIO(6:5) - PLL_IBIAS_RD (Reduced mirror bias setting for PHY PLL)
Provide 4 different IBIAS settings - Set to 00 for R520
GPIO(8) - FORCE_COMPLIANCE: 0 for Normal operation, 1 for Force into Compliance Mode
GPIO(9,13:11) - ROMIDCFG[3..0]
1001 - 1M AT25F1024 ROM (Atmel)
1010 - 1M AT45DB011 ROM (Atmel)
1011 - 1M M25P10 ROM (ST)
1100 - 512K M25P05 ROM (ST) (ATI default)
1101 - 1M SST45LF010 ROM (SST), 1M W45B512 ROM (WinBond), 512K W45B012 ROM (WinBond)
1110 - 1M SST25VF010 ROM (SST), 512K SST25VF512 ROM (SST)
1111 - 1M NX25F011B ROM (NexFlash)
VSYNC - VIP_DEVICE
0: Slave VIP host port devices present (use if Theater is populated)
1: No slave VIP host port devices reporting presence during reset (use for configurations without video-in)
HSYNC - DWNGRD
This straps allow a Workstation bonded part to be downgraded to a normal part on a board. This
allow inventory management to better balance demand.
0 - Device remain a Workstation grade part
1 - Part is downgraded to a Normal part
H2SYNC, V2SYNC, GENERICC - Star Memory System repair mode
000 - Default
00 : RESERVED
01 : SAMSUNG
TV OUT STANDARD (Jumper position overwrite resistor settings)
0 - PAL TVO (Jumper position 2-3)
1 - NTSC TVO (Jumper position 1-2)
Data from display
Monitor ID bit 2
Open
+5V
50mA min
1A max
1.5A
J2001
J2001
1
R
2
G
3
B
11
MS0
DDC2_MONID0
12
MS1
DDC2_MONID1(SDA)
4
MS2
DDC2_MONID2
15
MS3
DDC2_MONID3(SCL)
9
NC
13
HS
14
VS
5
VSS
6
VSS#6
7
VSS#7
8
VSS#8
10
VSS#10
16
CASE
17
CASE#17
Connector_DB15_Female_VGA_Blue
Connector_DB15_Female_VGA_Blue
DDC2B or
DDC2AB Host
DDC2B+ Host
Monitor ID bit 0
Monitor ID bit 0
SDA
SDA
Monitor ID bit 2
Monitor ID bit 2
SCL
SCL
+5V
+5V
50mA min
300mA min
1A max
1A max
+5V_VESA2
C2010
C2010
68pF
68pF
DNI
DNI
DB15 pin
Standard VGA
Monitor ID bit 0
11
Monitor ID bit 1
12
Monitor ID bit 2
4
Monitor ID bit 3
15
N/C
9
Mechanical Key
Hardware
Support
NoYesYesNoYes
Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997
DDC1/2 Display
Optional
SDA
Optional
SCL
Optional
+5V_VESA2
SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane
BB
+3.3V
Q1021
Q1021
MMBT3904
MMBT3904
HPD1[3]
AA
8
7
6
5
R10240RR1024
0R
These resistors can be
placed close to the ASIC so
single net is needed
23
R1023
R1023
10K
10K
4
10K
10K
1
R1022
R1022
TjX2M[3]
TjX2P[3]
TjX4M[3]
TjX4P[3]
DDCCLK_DAC2_R
DDCDATA_DAC2_R
A_VSYNC_DAC2_R
TjX1M[3]
TjX1P[3]
TjX3M[3]
TjX3P[3]
HPD_DVI
TjX0M[3]
TjX0P[3]
TjX5M[3]
TjX5P[3]
TjXCP[3]
TjXCM[3]
A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F
A_HSYNC_DAC2_R
ATI Technologies Inc.
ATI Technologies Inc.
ATI Technologies Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Canada, L3T 7X6
Canada, L3T 7X6
Canada, L3T 7X6
(905) 882-2600
(905) 882-2600
(905) 882-2600
Title
Title
Title
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
Custom
Custom
Custom
Date:Sheet
Date:Sheet
3
Date:Sheet
2
J1001
J1001
25
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26
CASE#26
27
CASE#27
28
CASE#28
29
CASE#29
30
CASE#30
DVI CONNECTOR
DVI CONNECTOR
105-A67700-00A
105-A67700-00A
105-A67700-00A
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402
L3001 470nH_250mAL3001 470nH_250mA
C3001
C3001
47pF_50V
47pF_50V
L3002 470nH_250mAL3002 470nH_250mA
C3002
C3002
47pF_50V
47pF_50V
L3003 470nH_250mAL3003 470nH_250mA
C3003
C3003
47pF_50V
47pF_50V
DAC2_Y[3]
R3001
R3001
75R
75R
DAC2_C[3]
R3002
+3.3V
R3008
R3008
10K
10K
402
R3002
75R
75R
R3003
R3003
75R
75R
R30090RR30090R
DAC2_Y_F
DAC2_C_F
DAC2_COMP_F
DD
DAC2_COMP[3]
STV/HDTV#_OUT_DET[7]
CC
DAC2_Y_F
C3004
C3004
47pF_50V
47pF_50V
DAC2_C_F
C3005
C3005
47pF_50V
47pF_50V
DAC2_COMP_F
C3006
C3006
47pF_50V
47pF_50V
Place near connector
0R leaves footprint for Ferrite
Beads if req'd for EMI
TV Out
J3201
PIN6
J3201
6
HDTV_OUT_DET#
3
Y-OUT
4
C-OUT
7
Comp-out
5
Comp-in
1
GND
2
GND#2
11
Luma-in
12
Chroma-in
8
CASE
9
CASE#9
10
CASE#10
GA1042C219-019F
GA1042C219-019F
The 7-pin MiniDIN footprint allows one of the two MiniDINs:
- 7-pin Svideo/Composite MiniDIN P/N 6071001500G
- 4-pin Svideo MiniDIN P/N 6070001000G
7 pin N56-07F0021-F02
9 pin N56-09F0031-F02
BB
AA
ATI Technologies Inc.
ATI Technologies Inc.
ATI Technologies Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Canada, L3T 7X6
Canada, L3T 7X6
Canada, L3T 7X6
(905) 882-2600
(905) 882-2600
(905) 882-2600
Title
Title
Title
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
C
C
C
Date:Sheet
Date:Sheet
8
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105-A67700-00A
105-A67700-00A
105-A67700-00A
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DD
+12V_BUS
B31
B31
Bead
Bead
JU1JU1
1
2
JUl2
DUAL FOOTPRINT
JUl1
C4008
C4008
100nF
100nF
402
603
X7R
5%
CC
H2
H2
7120022000G
7120022000G
MJU1
MJU1
1
2
3
Header_1X3
Header_1X3
BB
AA
ATI Technologies Inc.
ATI Technologies Inc.
ATI Technologies Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Canada, L3T 7X6
Canada, L3T 7X6
Canada, L3T 7X6
(905) 882-2600
(905) 882-2600
(905) 882-2600
Title
Title
Title
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
C
C
C
Date:Sheet
Date:Sheet
8
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105-A67700-00A
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DD
4
MT1
MT1
MT_Hole_0.136_in.
MT_Hole_0.136_in.
3
2
1
FM1
FM1
SW_FB
REF1
REF1
PCB
PCB
109-A67731-00A
109-A67731-00A
CC
BB
SW_FB
1
FM2
FM2
SW_FB
SW_FB
1
FM3
FM3
SW_FB
SW_FB
1
FM4
FM4
SW_FB
SW_FB
1
FM5
FM5
SW_FB
SW_FB
1
FM6
FM6
SW_FB
SW_FB
1
X_PIN1*2
X_PIN1*2
X_PIN1*2
X_PIN1*2
X_PIN1*2
X_PIN1*2
JI1
JI1
JI2
JI2
JI3
JI3
+MVDDQ
+MVDDQ
+MVDDQ
X_PIN1*2
X_PIN1*2
X_PIN1*2
X_PIN1*2
X_PIN1*2
X_PIN1*2
JI4
JI4
JI5
JI5
JI6
JI6
AA
<Variant Name>
<Variant Name>
<Variant Name>
5
4
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2
ATI Technologies Inc.
ATI Technologies Inc.
ATI Technologies Inc.
1 Commerce Valley Drive East
1 Commerce Valley Drive East
1 Commerce Valley Drive East
Markham, Ontario
Markham, Ontario
Markham, Ontario
Canada, L3T 7X6
Canada, L3T 7X6
Canada, L3T 7X6
(905) 882-2600
(905) 882-2600
(905) 882-2600
Title
Title
Title
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
MS-V050 RV515 TSOP
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
C
C
C
Date:Sheet
Date:Sheet
Date:Sheet
105-A67700-00A
105-A67700-00A
105-A67700-00A
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<Variant Name>
<Variant Name>
<Variant Name>
Title
Title
Title
4
3
2
Date:Schematic No.
Date:Schematic No.
Date:Schematic No.
1
RV515/530 ATX VGA DVI VIVO 256/512MB TSOP
RV515/530 ATX VGA DVI VIVO 256/512MB TSOP
RV515/530 ATX VGA DVI VIVO 256/512MB TSOP
REVISION HISTORY
REVISION HISTORY
REVISION HISTORY
DD
Sch
Sch
Sch
Rev
Rev
Rev
CC
PCB
PCB
PCB
Rev
Rev
Rev
0
00A
Date
Date
Date
07/27/05
REVISION DESCRIPTION
REVISION DESCRIPTION
REVISION DESCRIPTION
DERIVE FROM A66606/29/05
(pg 01) Correct clock circuitry to support RT
(pg 08) Swap R603 and R604 to match layout for documentation purposes
(pg 09) Swap R703 and R704 to match layout for documentation purposes
(pg 10) Add MVDD linear regulator option
(pg 11) Add R986, R987, R988; replace redundant power sequence circuit with +5V_EN and MVDD_EN
(pg 11) Add MR911, R918 for +MPVDD for no-tracking option
(pg 16) Change C3103 to 603 footprint, change RT to power from 3.3V_BUS to avoid leakage, remove redundant RT clock resistors