MSI MS-V043 Schematic 11

8

7

6

5

4

3

2

1

+12V_BUS

C1

CAP CER 10UF 20% 16V X5R

10UF

(1206)1.8MM H MAX

+12V_BUS

+12V_BUS

C2

D D

+3.3V_BUS

+3.3V_BUS

C C

B B

C3

150nF_16V

150nF_16V

LF CAP CER 150NF 10% 16V X7R (0603)

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

C4
10uF

+3.3V_BUS

C6

C5

1uF_6.3V

1uF_6.3V

LF CAP CER 1U F 10% 6.3V X5R (0402)

Place these caps last,
ideally as close to the bu s
connector as possibl e

DNI

R6 0R
R5 0R

A_HSYNC_DAC1(3,7,14)

PETp10_GFXRp10(2)
PETn10_GFXRn10(2)

PETp11_GFXRp11(2)
PETn11_GFXRn11(2)

PETp12_GFXRp12(2)
PETn12_GFXRn12(2)

PETp13_GFXRp13(2)
PETn13_GFXRn13(2)

PETp14_GFXRp14(2)
PETn14_GFXRn14(2)

PETp15_GFXRp15(2)
PETn15_GFXRn15(2)

R4 0R

TP6

TP5

PETn0_GFXRn0(2)

PETp1_GFXRp1(2)
PETn1_GFXRn1(2)

PETp2_GFXRp2(2)
PETn2_GFXRn2(2)

PETp3_GFXRp3(2)
PETn3_GFXRn3(2)

PETp4_GFXRp4(2)
PETn4_GFXRn4(2)

PETp5_GFXRp5(2)
PETn5_GFXRn5(2)

PETp6_GFXRp6(2)
PETn6_GFXRn6(2)

PETp7_GFXRp7(2)
PETn7_GFXRn7(2)

PETp8_GFXRp8(2)
PETn8_GFXRn8(2)

PETp9_GFXRp9(2)
PETn9_GFXRn9(2)

PRESENCE

PCI-EXPRESS EDGE CONNECTOR

+12V_BUS+3.3V_BUS +3.3V_BUS+12V_BUS

TESTEN_GND
JTAG_TRST#

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

+12V#B1
+12V#B2
+12V#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1

3.3Vaux
WAKE#

RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82

Mechanical Key

x16 PCIe

PRSNT1#A1

+12V#A2
+12V#A3
GND#A4

JTAG2
JTAG3
JTAG4
JTAG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12
REFCLK+
REFCLK­GND#A15

PERp0
PERn0

GND#A18

RSVD#A19

GND#A20

PERp1

PERn1
GND#A23
GND#A24

PERp2

PERn2
GND#A27
GND#A28

PERp3

PERn3
GND#A31

RSVD#A32
RSVD#A33

GND#A34

PERp4

PERn4
GND#A37
GND#A38

PERp5

PERn5
GND#A41
GND#A42

PERp6

PERn6
GND#A45
GND#A46

PERp7

PERn7
GND#A49

RSVD#A50

GND#A51

PERp8

PERn8
GND#A54
GND#A55

PERp9

PERn9
GND#A58
GND#A59

PERp10

PERn10
GND#A62
GND#A63

PERp11

PERn11
GND#A66
GND#A67

PERp12

PERn12
GND#A70
GND#A71

PERp13

PERn13
GND#A74
GND#A75

PERp14

PERn14
GND#A78
GND#A79

PERp15

PERn15
GND#A82

MPCIE1

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

PERp0
PERn0

PERp1
PERn1

PERp2
PERn2

PERp3
PERn3

PERp4
PERn4

PERp5
PERn5

PERp6
PERn6

PERp7
PERn7

PERp8
PERn8

PERp9
PERn9

PERp10
PERn10

PERp11
PERn11

PERp12
PERn12

PERp13
PERn13

PERp14
PERn14

PERp15
PERn15

PRESENCE

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

R2 0R

C7
100nF

C9
100nF

C11
100nF

C13
100nF

C15
100nF

C17
100nF

C19
100nF

C21
100nF

C23
100nF

C25
100nF

C27
100nF

C29
100nF

C31
100nF

C33
100nF

C35
100nF

C37
100nF

DNI

PERST#

C8
100nF

C10
100nF

C12
100nF

C14
100nF

C16
100nF

C18
100nF

C20
100nF

C22
100nF

C24
100nF

C26
100nF

C28
100nF

C30
100nF

C32
100nF

C34
100nF

C36
100nF

C38
100nF

8 1
7 2
6 3
5 4

R1 0R

TP1

RP1AEXB28VR000X
RP1BEXB28VR000X
RP1CEXB28VR000X
RP1DEXB28VR000X

PCIE_REFCLKP (2)
PCIE_REFCLKN (2)PETp0_GFXRp0(2)

GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)

GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)

GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)

GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)

GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)

GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)

GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)

GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)

GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)

GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)

GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)

GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)

GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)

GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)

GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)

GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)

TP4

TP3

TP2

A_VSYNC_DAC1 (3,7,14)

CRT1DDCDATA (3,14)
CRT3DDCCLK (3,13,17)TESTEN(3)
CRT1DDCCLK (3,14)

+3.3V

CAP, CERAMIC 100NF 10% 10V X5R EIA (0402)

C39
100nF

53

1

4

2

U5
NC7SZ08P5X_NL

R_RST

R3 0R

Place R_RST in U_RST

PERST#_buf (2, 13,16)

POWER SEQ UENCING

+12V_BUS+3.3V_BUS +12V_BUS

SMPS_EN1 SMPS_EN2

R45

4.7K

402

Node 1

R41
475R

402
1%

A A

R42
200R

402
1%

R43

1.62K

402
1%

VMON2

Node 3

VMON1

Node 2

R44
200R

402
1%

8

5%

Q41

1

MMBT3904

2 3

Q42

1

MMBT3904

2 3

Q43

1

MMBT3904

2 3

R46
0R

402

DNI

5mA

7

SMPS_EN1 (8) SMPS_EN2 (9)

Q44

1

C43
100nF

MMBT3904

2 3

C44
100nF

6

Power Sequence Circuit to ensure SMPS_EN is released after
+12V_BUS and +3.3V_BUS are both in regulation.
Pull-up may or may not be required on SMPS_EN signal depending
on SMPS design.

Node 1 When +12V ramps above min Vbe, SMPS_EN will be helt low

When +3.3V gets close to regulation, one of the two

Node 2

conditions of releasing SMPS_EN is active
Target ~ 900mV when +3.3 at min regulation (worse case)

Typical trigger when +3.3V ramps above 2.2V (650mV)

Node 3 When +12V gets close to regulation, one of the two

conditions of releasing SMPS_EN is active
Target ~ 1.25V when +12 at min regulation (worse case)

Typical trigger when +12V ramps above 10V (1.1V)

5

www.vinafix.vn

4

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docum e n t N u mb er Re v

C

3

Date: Sheet

2

105-A671xx-00

SYMBOL LEGEND

DNI

DO NOT
INSTALL

#

ACTIVE
LOW

DIGITAL
GROUND

ANALOG
GROUND

120Saturday, O ctober 08, 2005

1

2

of

5

D D

4

3

2

1

NOTE: some of the PCIE testpoints will
be available trought via on traces.

PETp0_GFXRp0(1)
PETn0_GFXRn0(1)

PETp1_GFXRp1(1)
PETn1_GFXRn1(1)

PETp2_GFXRp2(1)
PETn2_GFXRn2(1)

PETp3_GFXRp3(1)
PETn3_GFXRn3(1)

PETp4_GFXRp4(1)
PETn4_GFXRn4(1)

PETp5_GFXRp5(1)
PETn5_GFXRn5(1)

PETp6_GFXRp6(1)

C C

B B

PETn6_GFXRn6(1)

PETp7_GFXRp7(1)
PETn7_GFXRn7(1)

PETp8_GFXRp8(1)

PETp9_GFXRp9(1)
PETn9_GFXRn9(1)

PETp10_GFXRp10(1)
PETn10_GFXRn10(1)

PETp11_GFXRp11(1)
PETn11_GFXRn11(1)

PETp12_GFXRp12(1)
PETn12_GFXRn12(1)

PETp13_GFXRp13(1)
PETn13_GFXRn13(1)

PETp14_GFXRp14(1)
PETn14_GFXRn14(1)

PETp15_GFXRp15(1)
PETn15_GFXRn15(1)

PCIE_REFCLKP(1)
PCIE_REFCLKN(1)

DNI DNI

R13
51R

402 402

PERST#_buf(1,13,16)

R14
51R

For Tektronix LA only

Place close
to ASIC

TP11

TP12

TP13

TP14

TP19

TP20

TP21

TP27

TP28

R11

4.7K

402

TP7

TP8

TP9

TP10

TP15

TP16

TP17

TP18

TP23TP22

TP24

TP25

TP26

+3.3V

DNI

U1A

AJ31

PCIE_RX0P

AH31

PCIE_RX0N

AH30

PCIE_RX1P

AG30

PCIE_RX1N

AG32

PCIE_RX2P

AF32

PCIE_RX2N

AF31

PCIE_RX3P

AE31

PCIE_RX3N

AE30

PCIE_RX4P

AD30

PCIE_RX4N

AD32

PCIE_RX5P

AC32

PCIE_RX5N

AC31

PCIE_RX6P

AB31

PCIE_RX6N

AB30

PCIE_RX7P

AA30

PCIE_RX7N

AA32

PCIE_RX8P

Y32

PCIE_RX8N

Y31

PCIE_RX9P

W31

PCIE_RX9N

W30

PCIE_RX10P

V30

PCIE_RX10N

V32

PCIE_RX11P

U32

PCIE_RX11N

U31

PCIE_RX12P

T31

PCIE_RX12N

T30

PCIE_RX13P

R30

PCIE_RX13N

R32

PCIE_RX14P

P32

PCIE_RX14N

P31

PCIE_RX15P

N31

PCIE_RX15N

AL28

PCIE_REFCLKP

AK28

PCIE_REFCLKN

AG24

PERSTB

AA24

PCIE_TEST

AF24

NC

RV530 Unfused LF A11

Clock

PART 1 OF 7

P
C
I

­E
X
P
R
E
S
S

I
N
T
E
R
F
A
C
E

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

Calibration

PCIE_CALRN
PCIE_CALRP

PCIE_CALI

AK27
AJ27

AJ25
AH25

AH28
AG28

AG27
AF27

AF25
AE25

AE28
AD28

AD27
AC27

AC25
AB25

AB28
AA28

AA27
Y27

Y25
W25

W28
V28

V27
U27

U25
T25

T28
R28

R27
P27

AE24
AD24

AB24

GFXTp0_PERp0 (1)
GFXTn0_PERn0 (1)

GFXTp1_PERp1 (1)
GFXTn1_PERn1 (1)

GFXTp2_PERp2 (1)
GFXTn2_PERn2 (1)

GFXTp3_PERp3 (1)
GFXTn3_PERn3 (1)

GFXTp4_PERp4 (1)
GFXTn4_PERn4 (1)

GFXTp5_PERp5 (1)
GFXTn5_PERn5 (1)

GFXTp6_PERp6 (1)
GFXTn6_PERn6 (1)

GFXTp7_PERp7 (1)
GFXTn7_PERn7 (1)

GFXTp8_PERp8 (1)
GFXTn8_PERn8 (1)PETn8_GFXRn8(1)

GFXTp9_PERp9 (1)
GFXTn9_PERn9 (1)

GFXTp10_PERp10 (1)
GFXTn10_PERn10 (1)

GFXTp11_PERp11 (1)
GFXTn11_PERn11 (1)

GFXTp12_PERp12 (1)
GFXTn12_PERn12 (1)

GFXTp13_PERp13 (1)
GFXTn13_PERn13 (1)

GFXTp14_PERp14 (1)
GFXTn14_PERn14 (1)

GFXTp15_PERp15 (1)
GFXTn15_PERn15 (1)

+PCIE

402

R82.0K

402

R9562R

402

R101.47K

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docum e n t N u mb er Re v

C

5

4

www.vinafix.vn

3

2

Date: Sheet

105-A671xx-00

1

2

of

220Saturday, O ctober 08, 2005

5

4

3

2

1

D D

C C

I2C DEVICE ADDRESS' ON DDC3

DEVICE
LM63

B B

Place close to ASIC

T2XCM(13)
T2XCP(13)

T2X0M(13)

T2X0P(13)

T2X1M(13)

T2X1P(13)

T2X2M(13)

T2X2P(13)

T2X3M(15)

T2X3P(15)

T2X4M(15)

T2X4P(15)

T2X5M(15)

T2X5P(15)

LF RESIST OR 324R 1% 1/ 16W EIA (0402)

+T2XVDDR

C225

NS19NS_VIA

10uF

1 2

GND_T2XVSSR

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

ADDRESS
x100 1100

CRT3DDCDATA(13,17)

CRT3DDCCLK(1,13,17)

TESTEN(1)

402

R101 324R

R102 324R

R103 324R

R104 324R

R105 324R

R106 324R

R107 324R

NS15NS_VIA

1 2

C224

1uF_6.3V

+3.3V

+T2PVDD

1uF_6.3V

R33

4.7K

402 402

+3.3V

+3.3V

C227

1uF_6.3V

GND_T2PVSS

C223

C222

1uF_6.3V

CRT1DDCDATA(1,14)

R34

CRT2DDCDATA(15)

4.7K

MR24 10K
R24 10K

Overlap Footprints

R25 499R
R26 499R

CRT1DDCCLK(1,14)

CRT2DDCCLK(15)

C226

1uF_6.3V

C221

1uF_6.3V

GPU_DPLUS(17)
GPU_DMINUS(17)

HPD1(14)

T2XCM
T2XCP

T2X0M
T2X0P

T2X1M
T2X1P

T2X2M
T2X2P

T2X3M
T2X3P

T2X4M
T2X4P

T2X5M
T2X5P

TP30

TESTEN

VREFG

XTALIN
XTALOUT

U1B

AL18

T2XCM

AM18

T2XCP

AK19

T2X0M

AL19

T2X0P

AL20

T2X1M

AM20

T2X1P

AL21

T2X2M

AM21

T2X2P

AK18

T2X3M

AJ18

T2X3P

AH18

T2X4M

AG18

T2X4P

AJ20

T2X5M

AK20

T2X5P

AE19

T2PVDD

AE18

T2PVSS

AF20

T2XVDDR_1

AE20

T2XVDDR_2

AF19

T2XVDDR_3

AC21

T2XVDDR_4

AC22

T2XVDDR_5

AD22

T2XVDDR_6

AE21

T2XVDDR_7

AD21

T2XVDDR_8

AE22

T2XVDDR_9

AF22

T2XVSSR_1

AF17

T2XVSSR_2

AF21

T2XVSSR_3

AK17

T2XVSSR_4

AJ19

T2XVSSR_5

AF18

T2XVSSR_6

AH17

T2XVSSR_7

AG17

T2XVSSR_8

AG19

T2XVSSR_9

AH19

T2XVSSR_10

AH22

DDC1DATA

AH23

DDC1CLK

AH13

DDC2DATA

AG13

DDC2CLK

AE12

DDC3DATA

AF12

DDC3CLK

AF11

HPD1

AE13

SDA

AF13

SCL

AG12

DPLUS

AH12

DMINUS

AG14

PLLTEST

AG22

TESTEN

AC8

VREFG

AL26

XTALIN

AM26

XTALOUT

RV530 Unfused LF A11

Integrated
TMDS2

Monitor
Interfa ce

MMI2C

Thermal
Diode

Test

XTAL

PART 2 OF 7

V
I
D
E
O

&

M
U
L
T
I
M
E
D
I
A

Integrated
TMDS

TXVDDR_1
TXVDDR_2
TXVDDR_3
TXVDDR_4

TXVSSR_1
TXVSSR_2
TXVSSR_3
TXVSSR_4
TXVSSR_5

DAC / CRT

DAC2 (TV/CRT2)

A2VSSN_1
A2VSSN_2

NC_A2VDDQ

TXCM
TXCP

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TX3M

TX3P

TX4M

TX4P

TX5M

TX5P
TPVDD
TPVSS

HSYNC

VSYNC

RSET

AVDD_1
AVDD_2

AVSSQ

AVSSN_1
AVSSN_2

VDD1DI
VSS1DI

H2SYNC

V2SYNC

COMP

R2SET

A2VDD_1
A2VDD_2

A2VSSQ

VDD2DI
VSS2DI

AL9
AM9

AK10
AL10

AL11
AM11

AL12
AM12

AK9
AJ9

AK11
AJ11

AK12
AJ12

AM8
AL8
AJ6

AK6
AL6
AM6

AJ7
AK7
AL7
AM7
AK8

AK24

R

AM24

G

AL24

B

AJ23
AJ22

RSET

AL22

+AVDD

AL25
AM25

GND_AVSSQ

AK23
AK25
AJ24

+VDD1DI

AM23
AL23

AK15

R2

AM15

G2

AL15

B2

AF15
AG15

AJ15

Y

AJ13

C

AH15

R2SET GND_A2VSSQ

AK14

+A2VDD

AM16
AL16

C56

AM17

10nF

AL17

AK13

+VDD2DI

AJ16

C59

AJ17

10nF

AL14

C246

C247

1uF_6.3V

1uF_6.3V

+TXVDDR

C250

C249

1uF_6.3V

1uF_6.3V

A_R_DAC1 (14)
A_G_DAC1 (14)
A_B_DAC1 (14)

A_HSYNC_DAC1 (1,7,14)
A_VSYNC_DAC1 (1,7,14)

R31 499R

R32 715R

GND_AVSSQ

RESISTOR, 499R 1% 1/16W E IA(0402)

C62

C63
100nF

10nF

10V X5R

10V X7R

402 10%

402 10%

C54

C53

100nF

10nF

A_R_DAC2 (15)
A_G_DAC2 (15)
A_B_DAC2 (15)

A_HSYNC_DAC2 (7,15)
A_VSYNC_DAC2 (7,15)

DAC2_Y (16)
DAC2_C (16)
DAC2_COMP (16)

C57

C58

100nF

1uF_6.3V

C60
1uF_6.3V

+TPVDD

NS14 NS_VIA

12

GND_TPVSS

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

C251

NS13 NS_VIA

10uF

GND_TXVSSR

C64
1uF_6.3V

6.3V X5R
402 10%

C55
1uF_6.3V

12

NS5 NS_VIA

GND_AVSSQ

NS6 NS_VIA

GND_AVSSN

NS7 NS_VIA

GND_VSS1DI

NS8 NS_VIA

GND_A2VSSN

NS9 NS_VIA

GND_A2VSSQ

NS10 NS_VIA

GND_VSS2DI

Place close to ASIC

TjXCM
TjXCP

TjX0M
TjX0P

TjX1M
TjX1P

TjX2M
TjX2P

TjX3M
TjX3P

TjX4M
TjX4P

TjX5M
TjX5P

12

12

12

12

12

12

R136 324R

R132 324R

R133 324R

R134 324R

R135 324R

R131 324R

R130 324R

LF RESIST OR 324R 1% 1/ 16W EIA (0402)

TjXCM ( 14)
TjXCP (14)

TjX0M (14)
TjX0P (14)

TjX1M (14)
TjX1P (14)

TjX2M (14)
TjX2P (14)

TjX3M (14)
TjX3P (14)

TjX4M (14)
TjX4P (14)

TjX5M (14)
TjX5P (14)

XTALIN_S

MR81 82R

R81 82R

R82

51.1R

R83 0R

MR83 0R

XTALIN

C82

Y82

22pF

27_MHZ

XTALOUT

4

www.vinafix.vn

CRYSTA L 27MHZ 30P PM F UND H C49SMT

2 1

Change to 10ppm/10ppm p/n 5028270000G

C83
22pF

XTALIN_S

XTALOUT_S

3

R_RTCLK

R85 0R
MR85 0R

R84
1M

MR86 0R
R86 330R

Place R_RTCLK close to XTAL so the
main clock line has shortest stub

XTALIN

XTALOUT

RTXTALIN (16)

RTXTALOUT (16)

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docu m en t N u m be r Re v

Custom

2

Date: Sheet

105-A671xx-00

1

2

of

320Saturday , O ctober 08, 2005

RTCLK(16)

+3.3V

A A

C81
1uF_6.3V

4
2

XTAL

Y81

VCC
GND

27.000MHz

5

OUT

E/D

XTAL_EN

3
1

5

+MVDD

C306
1uF_6.3V

C316
1uF_6.3V

C329
1uF_6.3V

C231
1uF_6.3V

C242
1uF_6.3V

C237
1uF_6.3V

+PVDD

C69
10nF

C307
1uF_6.3V

C317
1uF_6.3V

C330
1uF_6.3V

C301
1uF_6.3V

C311

D D

C C

+1.8V +3.3V

1uF_6.3V

C321
1uF_6.3V

C341
10uF

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

B57 1 2 0R_300m A
MB57 1 20R_300mA

1uF_6.3V

C312
1uF_6.3V

C322
1uF_6.3V

C342
10uF

1uF_6.3V

C313
1uF_6.3V

C326
1uF_6.3V

C343
10uF

+MVDD

C303

C302

Possible alt ernate 5150005600G

B B

NS12 NS_VIA

1 2

GND_PVSS +PCIE

C305

C304

1uF_6.3V

1uF_6.3V

C314

C315

1uF_6.3V

1uF_6.3V

C327

C328

1uF_6.3V

1uF_6.3V

C344

C345

10uF

10uF

Possible alt ernate 5150005600G

B54 120R_300mA
B55 120R_300mA

NS16 NS_VIA

12

GND_VSSRH0

+3.3V

C241
1uF_6.3V

C236
1uF_6.3V

C308
1uF_6.3V

C318
1uF_6.3V

C232
1uF_6.3V

NS17 N S_VIA

12

GND_VSSRH1

C243
1uF_6.3V

C238
1uF_6.3V

C70
100nF

4

C309
1uF_6.3V

C319
1uF_6.3V

C233
1uF_6.3V

C244
1uF_6.3V

CAP CER 10UF 10%

6.3V X5R (0805)1.4MM
MAX THICK

C239
1uF_6.3V

C71
1uF_6.3V

C310
1uF_6.3V

C320
1uF_6.3V

C245
10uF

C234
1uF_6.3V

+PVDD

GND_PVSS

U1E

C1

VDDR1_1

J1

VDDR1_2

M1

VDDR1_3

R1

VDDR1_4

V1

VDDR1_5

AA1

VDDR1_6

A3

VDDR1_7

P9

VDDR1_8

J10

VDDR1_9

N9

VDDR1_10

P10

VDDR1_11

A9

VDDR1_12

Y10

VDDR1_13

P8

VDDR1_14

R9

VDDR1_15

Y9

VDDR1_16

J11

VDDR1_17

A21

VDDR1_18

M10

VDDR1_20

N10

VDDR1_21

Y8

VDDR1_22

J18

VDDR1_23

J19

VDDR1_24

K21

VDDR1_25

A12

VDDR1_26

H13

VDDR1_27

A15

VDDR1_28

J20

VDDR1_29

J13

VDDR1_30

K11

VDDR1_31

K19

VDDR1_32

A18

VDDR1_33

L23

VDDR1_34

K20

VDDR1_35

K24

VDDR1_36

L24

VDDR1_37

H19

VDDR1_38

A24

VDDR1_39

K13

VDDR1_40

J32

VDDR1_41

A30

VDDR1_42

C32

VDDR1_43

F32

VDDR1_45

L32

VDDR1_46

A27

VDDRH0

F1

VDDRH1

A28

VSSRH0

E1

VSSRH1

AB9

VDDR3_1

AB10

VDDR3_2

AA9

VDDR3_3

AC19

VDDR3_4

AD18

VDDR3_5

AC20

VDDR3_6

AD19

VDDR3_7

AD20

VDDR3_8

AJ5

VDDR4_1

AM5

VDDR4_2

AL5

VDDR4_3

AK5

VDDR4_4

AE2

VDDR5_1

AE3

VDDR5_2

AE4

VDDR5_3

AE5

VDDR5_4

AJ14

PVDD

AH14

PVSS

RV530 Unfused LF A11

Clock

Memory I/O

I/O

PART 5 OF 7

P
O
W
E
R

Memory

Selected PLL's

3

PCIE_PVSS

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23

BBP_4
BBP_3
BBP_2
BBP_1

VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4
VDDCI_6
VDDCI_7
VDDCI_8

VDD25_1
VDD25_2
VDD25_3
VDD25_4
VDD25_5
VDD25_6

MPVDD

MPVSS

VDDPLL

V23
N23
P23
U23

W23

N29
N28
N27
N26
N25

AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27

AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18
V18
P18
P19
R19
W19
AD11

AC14
M23
V10
K18

W10
T14
W17
P16
T23
K14
U19

AC13
AC16
AC18
L10
K22
AA10

A6

A5

AC15

+VDDC

+MPVDD

GND_MPVSS

+VDDPLL

C214
1uF_6.3V

C202

C201

1uF_6.3V

1uF_6.3V

C191

C192

1uF_6.3V

1uF_6.3V

C162

C161

1uF_6.3V

1uF_6.3V

C172

C171

1uF_6.3V

1uF_6.3V

C211
1uF_6.3V

C206
1uF_6.3V

C67

1uF_6.3V

B56

C215
1uF_6.3V

120R_300mA

Possible alt ernate 5150005600G

PCIE_PVDD_12_1
PCIE_PVDD_12_2
PCIE_PVDD_12_3
PCIE_PVDD_12_4

PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4
PCIE_VDDR_12_5

PCIE_VDDR_12_6
PCIE_VDDR_12_7
PCIE_VDDR_12_8

PCIE_VDDR_12_9
PCIE_VDDR_12_10
PCIE_VDDR_12_11
PCIE_VDDR_12_12
PCIE_VDDR_12_13

PCI-Express

PCIE_VDDR_12_14

Core

I/0

I/O Internal

100nF

C203
1uF_6.3V

C193
1uF_6.3V

C163
1uF_6.3V

C173
1uF_6.3V

C66

+PCIE

C212
1uF_6.3V

C207
1uF_6.3V

10nF

2

C204
1uF_6.3V

GND_PCIE_PVSS

C194
1uF_6.3V

C164
1uF_6.3V

C174
1uF_6.3V

+VDDC

C208
1uF_6.3V

C65

22uF_16V

NS18 NS_VIA

C195
1uF_6.3V

C165
1uF_6.3V

C175
1uF_6.3V

C213
10uF

C209
1uF_6.3V

+MPVDD

C68

12

C196
1uF_6.3V

C166
1uF_6.3V

C177
1uF_6.3V

C197
1uF_6.3V

C167
1uF_6.3V

C178
1uF_6.3V

+VDDC_CT

C210
10uF

NS11NS_VIA

GND_MPVSS

1

+PCIE

C198
1uF_6.3V

C168
1uF_6.3V

C179
1uF_6.3V

12

C200

C199

10uF

10uF

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

C169

C170

1uF_6.3V

1uF_6.3V

C180
1uF_6.3V

C181
10uF

C183

C182

10uF

10uF

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

C184
10uF

+VDDC

C185
10uF

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docum e n t N u mb er Re v

C

5

4

www.vinafix.vn

3

2

Date: Sheet

105-A671xx-00

1

2

of

420Saturday, O ctober 08, 2005

5

4

3

2

1

+MVDD

+MVDD

R161
100R

R162
100R

R163
100R

R164
100R

M_MDA[63..0](12)

MVREFD_0

C351
100nF

MVREFS_0

C353
100nF

M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
M_MDA5
M_MDA6
M_MDA7
M_MDA8

M_MDA9
M_MDA10
M_MDA11
M_MDA12
M_MDA13
M_MDA14
M_MDA15
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
M_MDA21
M_MDA22
M_MDA23
M_MDA24
M_MDA25
M_MDA26
M_MDA27
M_MDA28
M_MDA29
M_MDA30
M_MDA31
M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA63

C352
10nF

C354
10nF

U1C

M31

DQA_0

M30

DQA_1

L31

DQA_2

L30

DQA_3

H30

DQA_4

G31

DQA_5

G30

DQA_6

F31

DQA_7

M27

DQA_8

M29

DQA_9

L28

DQA_10

L27

DQA_11

J27

DQA_12

H29

DQA_13

G29

DQA_14

G27

DQA_15

M26

DQA_16

L26

DQA_17

M25

DQA_18

L25

DQA_19

J25

DQA_20

G28

DQA_21

H27

DQA_22

H26

DQA_23

F26

DQA_24

G26

DQA_25

H25

DQA_26

H24

DQA_27

H23

DQA_28

H22

DQA_29

J23

DQA_30

J22

DQA_31

E23

DQA_32

D22

DQA_33

D23

DQA_34

E22

DQA_35

E20

DQA_36

F20

DQA_37

D19

DQA_38

D18

DQA_39

B19

DQA_40

B18

DQA_41

C17

DQA_42

B17

DQA_43

C14

DQA_44

B14

DQA_45

C13

DQA_46

B13

DQA_47

D17

DQA_48

E18

DQA_49

E17

DQA_50

F17

DQA_51

E15

DQA_52

E14

DQA_53

F14

DQA_54

D13

DQA_55

H18

DQA_56

H17

DQA_57

G18

DQA_58

G17

DQA_59

G15

DQA_60

G14

DQA_61

H14

DQA_62

J14

DQA_63

C31

MVREFD_0

C30

MVREFS_0

RV530 Unfused LF A11

Part 3 of 7

MEMORY INTERFACE A

DDR1 DDR2 DDR3

bidir. differential strobe

Not usedbidir. strobe

For DDR2

write stroberead strobe

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15

DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

QSA_0

QSA_1

QSA_2

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B

ODTA0

ODTA1

CLKA0
CLKA0b

CKEA0
RASA0b
CASA0b

WEA0b

CSA0b_0
CSA0b_1

CLKA1
CLKA1b

CKEA1
RASA1b
CASA1b

WEA1b

CSA1b_0
CSA1b_1

M_MAA0

D26

M_MAA1

F28

M_MAA2

D28

M_MAA3

D25

M_MAA4

E24

M_MAA5

E26

M_MAA6

D27

M_MAA7

F25

M_MAA8

C26

M_MAA9

B26

M_MAA10

D29

M_MAA11

B27

M_MAA12

E27

M_MAA13

E29

M_MAA14

B25

M_MAA15

C25

M_DQMA#0

H31

M_DQMA#1

J29

M_DQMA#2

J26

M_DQMA#3

G23

M_DQMA#4

E21

M_DQMA#5

B15

M_DQMA#6

D14

M_DQMA#7

J17

M_QSA0

J31

M_QSA1

K29

M_QSA2

K25

M_QSA3

F23

M_QSA4

D20

M_QSA5

B16

M_QSA6

D16

M_QSA7

H15

M_QSA#0

K31

M_QSA#1

K28

M_QSA#2

K26

M_QSA#3

G24

M_QSA#4

D21

M_QSA#5

C16

M_QSA#6

D15

M_QSA#7

J15
F29

D24

D31

CLKA0 (12)

E31

CLKA#0 (12)

B30

CKEA0 (12)

B28

RASA#0 (12)

C29

CASA#0 (12)

B31

WEA#0 (12)

B29

CSA#0_0 (12)

C28

B20

CLKA1 (12)

C19

CLKA#1 (12)

C22

CKEA1 (12)

B24

RASA#1 (12)

B22

CASA#1 (12)

B21

WEA#1 (12)

B23

CSA#1_0 (12)

C23

+MVDD

+MVDD

R165
100R

R166
100R

R167
100R

R168
100R

M_MAA[15..0] (12)

M_DQMA#[7..0] (12)

M_QSA[7..0] (12)

M_QSA#[7..0] (12)

MVREFD_1

C355
100nF

MVREFS_1

C357
100nF

C356
10nF

C358
10nF

D D

C C

B B

M_MDB[63..0](12)

U1D

M_MDB0

B12

M_MDB1
M_MDB2
M_MDB3
M_MDB4
M_MDB5
M_MDB6
M_MDB7
M_MDB8
M_MDB9

M_MDB10
M_MDB11
M_MDB12
M_MDB13
M_MDB14
M_MDB15
M_MDB16
M_MDB17
M_MDB18
M_MDB19
M_MDB20
M_MDB21
M_MDB22
M_MDB23
M_MDB24
M_MDB25
M_MDB26
M_MDB27
M_MDB28
M_MDB29
M_MDB30
M_MDB31
M_MDB32
M_MDB33
M_MDB34
M_MDB35
M_MDB36
M_MDB37
M_MDB38
M_MDB39
M_MDB40
M_MDB41
M_MDB42
M_MDB43
M_MDB44
M_MDB45
M_MDB46
M_MDB47
M_MDB48
M_MDB49
M_MDB50
M_MDB51
M_MDB52
M_MDB53
M_MDB54
M_MDB55
M_MDB56
M_MDB57
M_MDB58
M_MDB59
M_MDB60
M_MDB61
M_MDB62
M_MDB63

DRAM_RST(12)

R171

4.7K

R170

4.7K

R172

4.7K

RESISTOR, 4.7K 5% 1/16W E IA( 0402)

DQB_0

C12

DQB_1

B11

DQB_2

C11

DQB_3

C8

DQB_4

B7

DQB_5

C7

DQB_6

B6

DQB_7

F12

DQB_8

D12

DQB_9

E11

DQB_10

F11

DQB_11

F9

DQB_12

D8

DQB_13

D7

DQB_14

F7

DQB_15

G12

DQB_16

G11

DQB_17

H12

DQB_18

H11

DQB_19

H9

DQB_20

E7

DQB_21

F8

DQB_22

G8

DQB_23

G6

DQB_24

G7

DQB_25

H8

DQB_26

J8

DQB_27

K8

DQB_28

L8

DQB_29

K9

DQB_30

L9

DQB_31

K5

DQB_32

L4

DQB_33

K4

DQB_34

L5

DQB_35

N5

DQB_36

N6

DQB_37

P4

DQB_38

R4

DQB_39

P2

DQB_40

R2

DQB_41

T3

DQB_42

T2

DQB_43

W3

DQB_44

W2

DQB_45

Y3

DQB_46

Y2

DQB_47

T4

DQB_48

R5

DQB_49

T5

DQB_50

T6

DQB_51

V5

DQB_52

W5

DQB_53

W6

DQB_54

Y4

DQB_55

R8

DQB_56

T8

DQB_57

R7

DQB_58

T7

DQB_59

V7

DQB_60

W7

DQB_61

W8

DQB_62

W9

DQB_63

B3

MVREFD_1

C3

MVREFS_1

AA3

DRAM_RST

AA5

TEST_MCLK

AA2

TEST_YCLK

AA7

MEMTEST

RV530 Unfused LF A11
R169
243R

LF RES EIA( 0402) 243R 1% 1/ 16W

Part 4 of 7

MEMORY INTERFACE B

DDR1 DDR2 DDR3

read strobe

Not used bidir. strobe

bidir. differential strobe

write strobe

For DDR2

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8

MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15

DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7

QSB_0

QSB_1

QSB_2

QSB_3

QSB_4

QSB_5

QSB_6

QSB_7

QSB_0B
QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B

ODTB0

ODTB1

CLKB0
CLKB0b

CKEB0
RASB0b
CASB0b

WEB0b

CSB0b_0
CSB0b_1

CLKB1
CLKB1b

CKEB1
RASB1b
CASB1b

WEB1b

CSB1b_0
CSB1b_1

M_MAB0

G4

M_MAB1

E6

M_MAB2

E4

M_MAB3

H4

M_MAB4

J5

M_MAB5

G5

M_MAB6

F4

M_MAB7

H6

M_MAB8

G3

M_MAB9

G2

M_MAB10

D4

M_MAB11

F2

M_MAB12

F5

M_MAB13

D5

M_MAB14

H2

M_MAB15

H3

M_DQMB#0

B8

M_DQMB#1

D9

M_DQMB#2

G9

M_DQMB#3

K7

M_DQMB#4

M5

M_DQMB#5

V2

M_DQMB#6

W4

M_DQMB#7

T9

M_QSB0

B9

M_QSB1

D10

M_QSB2

H10

M_QSB3

K6

M_QSB4

N4

M_QSB5

U2

M_QSB6

U4

M_QSB7

V8

M_QSB#0

B10

M_QSB#1

E10

M_QSB#2

G10

M_QSB#3

J7

M_QSB#4

M4

M_QSB#5

U3

M_QSB#6

V4

M_QSB#7

V9
D6

J4

B4

CLKB0 (12)

B5

CLKB#0 (12)

C2

CKEB0 (12)

E2

RASB#0 (12)

D3

CASB#0 (12)

B2

WEB#0 (12)

D2

CSB#0_0 (12)

E3

N2

CLKB1 (12)

P3

CLKB#1 (12)

L3

CKEB1 (12)

J2

RASB#1 (12)

L2

CASB#1 (12)

M2

WEB#1 (12)

K2

CSB#1_0 (12)

K3

M_MAB[15..0] (12)

M_DQMB#[7..0] (12)

M_QSB[7..0] (12)

M_QSB#[7..0] (12)

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docum e n t N u mb er Re v

C

5

4

www.vinafix.vn

3

2

Date: Sheet

105-A671xx-00

1

2

of

520Saturday, O ctober 08, 2005

5

4

3

2

1

U1F

AH27

PCIE_VSS_1

AC23

PCIE_VSS_2

AL27

PCIE_VSS_3

R23

PCIE_VSS_4

P25

PCIE_VSS_5

R25

PCIE_VSS_6

T26

PCIE_VSS_7

AB26
AC26
AD25
AE26
AF26
AD26
AG25
AH26
AC28

AH29
AF28

AC29
AB27

AJ26
AJ32

AK29

AA29
AB29
AD29
AE29
AF29
AG29

AJ29
AK26
AK30
AG26

AF30
AC30

AA31
AD31

AK32

AJ28

AJ30
AK31
AA23
AG31

AB23

AC24
AH24

AA25
AA26
AE27

AD10

AF14

AG11
AG16

U26

W26

Y26

Y28
U28
P28

V29

W27

V26

P26
P29
R29
T29
U29

W29

Y29

N30
R31

V31
P30

U30

Y30

N24

P24
R24
T24
U24
V24

W24

Y24

V25
R26
T27

AD7

AE8
AL1

AM2

K10
T10

E12

AC9
AD8

F10

AA4

B1
H1
L1
P1
U1
Y1

A2

E8
H5

M8

C5
J3

L6
M6
P6

V3
R3

C6
C9
F6
H7
J6

PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
PCIE_VSS_33
PCIE_VSS_34
PCIE_VSS_35
PCIE_VSS_36
PCIE_VSS_37
PCIE_VSS_38
PCIE_VSS_39
PCIE_VSS_40
PCIE_VSS_41
PCIE_VSS_42
PCIE_VSS_43
PCIE_VSS_44
PCIE_VSS_45
PCIE_VSS_46
PCIE_VSS_47
PCIE_VSS_48
PCIE_VSS_49
PCIE_VSS_50
PCIE_VSS_51
PCIE_VSS_52
PCIE_VSS_53
PCIE_VSS_54
PCIE_VSS_55
PCIE_VSS_56
PCIE_VSS_57
PCIE_VSS_58
PCIE_VSS_59
PCIE_VSS_60
PCIE_VSS_61
PCIE_VSS_62
PCIE_VSS_63
PCIE_VSS_64
PCIE_VSS_65
PCIE_VSS_66

PCIE_VSS_69
PCIE_VSS_70
PCIE_VSS_71
PCIE_VSS_72
PCIE_VSS_73
PCIE_VSS_74
PCIE_VSS_75
PCIE_VSS_76
PCIE_VSS_77
PCIE_VSS_78
PCIE_VSS_79
PCIE_VSS_80
PCIE_VSS_81
PCIE_VSS_82
PCIE_VSS_83
PCIE_VSS_84

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37

D D

C C

B B

A A

Part 6 of 7

CORE GND

AD16

VSS_45

AA6

VSS_44

P7

VSS_43

P5

VSS_42

M3

VSS_41

M9

VSS_40

L7

VSS_39

M7

VSS_38

AD17

VSS_47

AH11

VSS_48

A8

VSS_49

U7

VSS_50

C10

VSS_51

E9

VSS_52

F3

VSS_53

J9

VSS_54

N7

VSS_55

N3

VSS_56

Y5

VSS_57

AM13

VSS_58

AC10

VSS_59

Y6

VSS_60

U6

VSS_61

E5

VSS_62

AL13

VSS_63

A11

VSS_64

U8

VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151

VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_163
VSS_164
VSS_165

U9
U10
R6
AD6
V6
AD14
AD13
D11
J12
K12
A13
F13
E13
F15
K16
J21
H16
T15
V17
C15
C4
U14
P15
A16
E16
G13
G16
P17
R16
R14
W16
C18
F16
W18
U18
AE16
AE17
A19
H32
F19
G19
N8
Y7
T19
V19
G21
C21
F21
AE14
AK16
U5
F22
F18
K30
C24
F24
M24
A25
D30
E25
G25
G20
G22
F27
E28
H21
C27
E32
H28
J30
K17
K27
M32
A22
C20
E19
H20
J24
M28
J28
J16
F30

L29
A31
B32
E30
AE15
AG23
AD9
AF16
AH10
AJ10
AD15
AH16

PCI-Express GND

Y23

BBN_4

K15

BBN_3

R10

BBN_2

AC17

BBN_1

RV530 Unfused LF A11

5

4

www.vinafix.vn

3

VEFUSE

K23

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docum e n t N u mb er Re v

C

Date: Sheet

105-A671xx-00

1

of

620Saturday, O ctober 08, 2005

2

5

4

3

2

1

U1G

PART 7 OF 7

VID_[7..0](16)

D D

DVPCLK_R(13)

DVP_CNT L_R_[ 2.. 0](13)

DVPDATA_R_[11..0](13)

DVPDATA

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15

C C

DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

ALTERNATE USE

-

-

-

-

-

-

-

-

-

-

-

-

-

­STV/HDTV#_O UT_DET (INPUT)

­TESTOUT(0) (OUTPUT)
TESTOUT(1) (OUTPUT)
TESTOUT(2) (OUTPUT)
TESTOUT(3) (OUTPUT)
TESTOUT(4) (OUTPUT)
TESTOUT(5) (OUTPUT)
TESTOUT(6) (OUTPUT)
TESTOUT(7) (OUTPUT)

DEBUG BUS

No testpoint means the net
can be accessed from a pad
somewhere else

DVPDATA_16

TP31

DVPDATA_17

TP32 35mil

DVPDATA_18

TP33

DVPDATA_19

TP34 35mil

DVPDATA_20

TP35

DVPDATA_21

TP36

DVPDATA_22

TP37

DVPDATA_23

TP38 35mil

DVP_CNT L_R_[2..0]

DVPDATA_R_[11..0]

STV/HDTV#_OUT_DET(16)

DVPCLK_R

DVP_CNTL_R_0
DVP_CNTL_R_1
DVP_CNTL_R_2

DVPDATA_R_0
DVPDATA_R_1
DVPDATA_R_2
DVPDATA_R_3
DVPDATA_R_4
DVPDATA_R_5
DVPDATA_R_6
DVPDATA_R_7
DVPDATA_R_8
DVPDATA_R_9
DVPDATA_R_10
DVPDATA_R_11

DVPDATA_14

RP5004A 22R

RP5004B 22R
RP5004C 22R
RP5004D 22R

RP5001A 22R
RP5001B 22R
RP5001C 22R
RP5001D 22R
RP5002B 22R
RP5002A 22R
RP5002D 22R
RP5002C 22R
RP5003B 22R
RP5003A 22R
RP5003C 22R
RP5003D 22R

VID_0

AF10
AG10

AE10

AH9

AJ8

AH8
AG9
AH7
AG8

AF7

AE9

AG7

AF9

AG1

AF2
AF1
AF3

AG2
AG3
AH2
AH3

AJ2
AJ1

AK2
AK1
AK3

AL2
AL3

AM3
AE6
AF4
AF5
AG4

AJ3

AH4

AJ4

AG5
AH5
AF6
AE7
AG6

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7

VPCLK0

VHAD_0
VHAD_1

VPHCTL

VIPCLK

DVPCLK

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

VIP
Capture

VIP
Host

Zoom Video Port

VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7

VPCLK0(16)

VHAD_0(16)
VHAD_1(16)

VPHCTL(16)

VIPCLK(16)

DVPCLK

18

DVP_CNTL_0

27

DVP_CNTL_1

36

DVP_CNTL_2

45

DVPDATA_0

81

DVPDATA_1

72

DVPDATA_2

63

DVPDATA_3

54

DVPDATA_4

72

DVPDATA_5

81

DVPDATA_6

54

DVPDATA_7

63

DVPDATA_8

72

DVPDATA_9

81

DVPDATA_10

63

DVPDATA_11

54

GPIO_0
GPIO_1

General

GPIO_2

Purpose

GPIO_3

I/O

GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8

GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17

GENERICA
GENERICB
GENERICC
GENERICD

DVALID

PSYNC
ROMCSb

VARY_BL

No Connect

NC_DVOVMODE_0
NC_DVOVMODE_1

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7

NC_22

AD4
AD2
AD1
AD3
AC1
AC2
AC3
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7

AK22
AF23
AE23
AD23

AH6
AF8

AC7

AD12
AE11
AJ21
AK21
AH21
AG21
AG20
AH20
AB6

AK4
AL4

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9

GENERICA
GENERICB
GENERICC

DVALID
PSYNC

ROMCSb

RST#_Ext-TMDS (13)
GPIO_8 (15)
GPIO_9 (14)

DEBUG BUS

No testpoint means the net
can be accessed from a pad
somewhere else

GPIO_10
GPIO_11
GPIO_12
GPIO_13

HPD2 ( 13,15)
GPIO_15 (10)
ThermINT (17)

GENERICA (14)
GENERICB (14)
GENERICC (15)

GPIO PIN STRAP ALTERNATE USE

GPIO_0 YES V I DB_0 (OUTPUT)
GPIO_1 YES V I DB_1 (OUTPUT)
GPIO_2 YES V I DB_2 (OUTPUT)
GPIO_3 YES V I DB_3 (OUTPUT)
GPIO_4 YES V I DB_4 (OUTPUT)
GPIO_5 YES V I DB_5 (OUTPUT)
GPIO_6 YES LDAC (OUTPUT)
GPIO_7 NO PAL/NTSC TV (INPUT)/Ext-TMDS Reset# (OUTPUT)
GPIO_8 YES ­GPIO_9 YES F L OW_CNTL_EN (OUTPUT)
GPIO_10 NO TESTOUT(8) (OUTPUT)
GPIO_11 YES TESTOUT(9) (OUTPUT)
GPIO_12 YES TESTOUT(10) (OUTPUT)
GPIO_13 YES TESTOUT(11 (OUTPUT))
GPIO_14 NO HPD_DVI1 (HPD2) (INPUT)
GPIO_15 NO VIDA#/B (OUTPUT)
GPIO_16 NO 12VEXT_DETECT (INPUT)
GPIO_17 NO T_INT#(INPUT) & 12VEXT_DETECT# (INPUT)

RV530 Unfused LF A11

PIN BASED STRAPS

+3.3V

GPIO_0

GPIO_1

GPIO_3

B B

GPIO_2

GPIO_4

GPIO_6
GPIO_5

GPIO_8

GPIO_9
GPIO_13
GPIO_12
GPIO_11

A_VSYNC_DAC1(1,3,14)

A_HSYNC_DAC1(1,3,14)

A_VSYNC_DAC2(3,15)

A A

A_HSYNC_DAC2(3,15)

DVALID(15)

A_VSYNC_DAC1

A_HSYNC_DAC1

A_VSYNC_DAC2
A_HSYNC_DAC2

GENERICC

DVALID
PSYNC

GPIO_7

5

4

R51 10K

R52 10K

DNI

R53 10K

DNI

R54 10K

DNI

R55 10K

DNI

R56 10K
R57 10K

DNI

R58 10K

R59 10K
R60 10K

DNI

R61 10K

DNI

R62 10K

DNI

R63 10K MR63 10K

R64 10K

DNI

R65 10K

DNI

R66 10K

DNI

R67 10K

DNI

R68 10K

DNI

R69 10K

R70 10K

P2
PLUG

MR51 10K

MR52 10K

MR53 10K
MR54 10K

MR55 10K

MR56 10K
MR57 10K

MR58 10K

MR59 10K
MR60 10K
MR61 10K
MR62 10K

MR64 10K

MR65 10K
MR66 10K
MR67 10K

MR68 10K
MR69 10K

MR70 10K
NR70 1K

123

www.vinafix.vn

JU2
Header_3_Pin_1X3

DNI

GPIO(0) - TX _ P WRS _ E N B ( T ransmitter Po w er Savings Enable)

0: 50% Tx output swing for mobile mode
1: full Tx ou t put swing (De f a ult setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)

DNI

0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)

GPIO(3:2) - Mi s ce l laneous PCI-Express Modes

00: Halt impedance calibration before transmitter is enabled and enable receiver detection (Default
setting for Desktop)
01: Allow impedance calibration to continue on in the background AFTER transmitter ha s
been enabled an d en able receive detection.
10: Bypass common - mo de detection & receiver detection and halt impedance calibration before TX_EN.
11: Short-circuit internal loopback and halt impedance calibration before TX_EN and enable
receiver detection.

GPIO(4) - DEBUG_ACCESS: 0 for normal operation, 1 for debug mode

GPIO(6:5) - PLL_IBIAS_RD (Reduced mirror bias setting for PHY PLL)

DNI

Provide 4 dif f erent IBI AS s e t t i n g s - S e t t o 0 0 f o r R520

GPIO(8) - FORCE_COMPLIANCE: 0 for Normal operation, 1 for Force into Compliance Mode

DNI

GPIO(9,13:11) - ROMIDCFG[3..0]

1001 - 1M AT25F1024 ROM (Atmel)
1010 - 1M AT45DB011 ROM (Atmel)

DNI

1011 - 1M M25P10 ROM (ST)
1100 - 512K M25P05 ROM (ST) (ATI default)
1101 - 1M SST45LF010 ROM (SST), 1M W45B512 ROM ( WinBond), 512K W45B012 ROM (WinBond)
1110 - 1M SST25VF010 ROM (SST), 512K SST25VF512 ROM (SST)
1111 - 1M NX25F011B ROM (NexFlash)

VSYNC - VIP_DEVICE

0: Slave VIP host port devices present (use if Theater is populated)
1: No slave VIP host port devices reporting presence during res et (use for configurations without video-in)

HSYNC - DWNGRD

DNI

This straps allow a Workstation bonded part to be downgraded to a normal part on a board. This
allow inventory mana ge men t t o better balance demand.
0 - Device remain a Workstation grade part
1 - Part is downgraded to a Normal part

H2SYNC, V2S YNC, GENERIC C - S t a r Memory System repair mode

000 - Default

MEMORY CONFIG

DVALID: 0 = 4 bank memo ry , 1 = 8 bank memory
PSYNC: 0 = 1 ra n k o f memory, 1 = 2 ranks of memory

TV OUT STANDARD (Jumper position overwrite resistor settings)

0 - PAL TVO (Ju mp er position 2-3)
1 - NTSC TVO (Jumper position 1-2)

3

ATI Feature I

ATI Board Feature I

ATI PCIE FEATURE I

ATI PCIE FEATURE II

ATI Feature II

ATI Board Feature II

ATI PCIE FEATURE III

+3.3V

R35
10K

GPIO_8
GPIO_9
GPIO_10
ROMCSb

2

+3.3V

R36
10K

MR36
10K

+3.3V

Title
Size Docum e n t N u mb er Re v

C

Date: Sheet

U2

D
C
S
HOLD
W
VCC

VSS

M25P05-AVNM6P

105-A671xx-00

2

Q

BIOS1

BIOS

4

113-XXXXXX-XXX

VIDEO BIOS
FIRMWARE

of

1

720Saturday, O ctober 08, 2005

5
6
1
7
3
8

C51
100nF

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

2

8

7

6

5

4

3

2

1

VDDC-PWM1

BST

GH

GND

GL

Vcc

VCC

PVCC

LGATE

PGND

BOOT
UGATE
PHASE

+PW_VDDC_M
VDDC_EN
VDDC_FB

+VDDC_B

R609 1K

+VDDC_B

10
9
3
2

+VDDC_VCC

1

14
13
12
11
10
9
8

R608 20K

+12V_BUS_F1

402

+PW_VDDC_LGD

+PW_VDDC_HGD

+12V_BUS_F1

+VDDC_B

C603

0.22uF

+PW_VDDC_LGD

+PW_VDDC_HGD

C604

0.22uF

402

+PW_VDDC_M

+PW_VDDC_LGD

+PW_VDDC_HGD

+PW_VDDC_M

+PW_VDDC_HGD

SMPS_EN1 (1)

+PW_VDDC_M

+PW_VDDC_LGD

+PW_VDDC_HGDR +PW_VDDC_LGDR

MQ601

+VDDC_S +VDDC_S

Thermal

Pad

9

4 5
3

6

2

7

1

8

FDS7096N3

+PW_VDDC_M

R621 0R

R622 0R

+PW_VDDC_HGDR

402

+PW_VDDC_LGDR

402

MQ603

Thermal

Pad

4 5
3
2
1

FDS7096N3

9

6
7
8

VDDC_SS

VDDC_FB

+VDDC_S

R624
221K

VDDC_COMP
VDDC_FB

1% 1%

R602 30.1K
C602 1nF
R603 2.37K

R604 0R

R623 0R

D D

+VDDC_S

C601
22nF

603

C C

VDDC_FB

VDDC_COMP
+12V_BUS_F1

VDDC_UVIN

R625
100K

402402

+3.3V_BUS

402

VDDC_RT

402

VDDC_OCS

X7R 10V

402

VDDC_SS
VDDC_COMP_U601

+PW_VDDC_HGD

+VDDC_B

+PW_VDDC_LGD

VDDC_COMP_U104

VDDC_COMP_U601

+PW_VDDC_M

R601 10K

2

3
1

2

3
1

U602

7

SS

4

Vfb

5

COMP

6

UVIN

8

SWN

SP6132CU

SIPEX SP6132A p/n 2480054700G

402

VDDC_EN

VDDC-PWM2

U601

1

RT

2

OCSET

3

SS

4

COMP

5

FB

6

EN

7

GND

ISL6522CB

INTERSIL ISL6522/ISL6535
RICHTEK RT9232/RT9232A
ANPEC APW7062A
ANPEC APW7062B

VDDC-PWM3

U603

8

UGATE

PS

7

OPS

GND

6

BOOT

FB

5

LGATE4VCC

RT9214CS

RICHTEK RT9214
INTERSIL ISL6545

VDDC-PWM4

U604

8

UGATE

PS

7

OPS

GND

6

BOOT

FB

5

LGATE4VCC

RT9214CS

Q601

QH

4 5
3
2
1

BSC119N03SG
Q603

4 5
3
2
1

BSC119N03SG
Q602

QL

4 5
3
2
1

BSC119N03SG
Q604

4 5
3
2
1

BSC119N03SG

MQ602

4 5
3
2
1

FDS7096N3

Thermal

Pad

Thermal

Pad

Thermal

Pad

Thermal

Pad

Thermal

Pad

+VDDC_S

9

6
7
8

9

6
7
8

9

6
7
8

9

6

Place Rs and Cs across QL

7
8

RC snubber values shown
are for reference only,
tuning is required

9

6
7
8

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

C616

C615

10UF

10UF

L601
R68UH

ML601

1.71uH_14A

1 2

NL601 2.2uH_13A

1 2

R619

R620

33MOHM

33MOHM

Rs

1210

1210

1%

1%

C608
10nF_25V

Cs

402
X7R
25V

MULTI FOOTPRINT

MQ604

Thermal

Pad

FDS7096N3

9

6
7
8

4 5
3
2
1

C617
10UF

1206

MULTI FOOTPRINT

VDDC_FB(10)

C619
10UF

VDDC_FB

C620
10UF

1206 1206120612061206

C621
10UF

1206

R1

R611
1K

402
1%

R4

R610

2.0K

402
1%

C622
10UF

C613

2.2nF_50V

R613

49.9R

Place R1 and
R4 close to
PWM and
routed with
separate
20mil trace to
the ASIC

***

***

***

C618
150nF_16V

603

**

MC623
22uF_16V

**

ALT ALT

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

***

C625
470uF_10V

***

TH TH

CAP AE 470UF 20% 10V 10x12 .5MM LOW ESR

+12V_BUS

B601
60R

***

+VDDC

**

MC624

C623
10uF

DUAL FOOTPRINT DUAL FOOTPRINT

***

MC625
470uF

***

ALT
POLY

DUAL FOOTPRINT

LF CAP, AL/POLY, 470UF 6.3V, LOW ESR, 8MM DIA, SMT

22uF_16V

**

***

C626
470uF_10V

***

DUAL FOOTPRINT

C624
10uF

CAP CER 10UF 10%

6.3V X5R (0805)1.4MM
MAX THICK

+VDDC

***

MC626
470uF

***

ALT
POLY

ANPEC APW7061A

B B

This symbol is used for 103 SMPS p/n.

VDDC1

402

VDDC_EN

R614 0R

VDDC_COMP

RV410SOCKET

Regulator for VDDC (ASIC Core)

Vout = 1V ~ 1.3V

COMPENSAT IO N CIRCUIT FILTERED +12V_BUS BOOT CI RCUIT

MR606
0R

402 402

21

D601
SD103AWS

R605
0R

16V

+5V+12V_BUS

402

R606
0R

C606
150nF_16V

+PW_VDDC_M

+VDDC_VCC

+VDDC_B

Part

Vout

0.8V Ref 1.2V

1.25V

1.00K 1%

1.00K 1% 1.78K 1%

R2R1

2.00K 1%

1.3V 1.00K 1% 1.6K 1%

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Document Number Rev

Custom

5

4

3

Date: Sheet

2

105-A671xx-00

2

of

820Saturday, October 08, 2005

1

+12V_BUS

R615
0R

402

VDDC_COMP

C612

C611

33pF

10nF

10V

603

A A

402

R612

8.06K

402
1%

50V
10%

NPOX7R

10%

402

VDDC_FB

7

R616 0R
R617

0R

402

8

+12V_BUS_F1

+12V_BUS

R607

2.2R

C607
100nF

MD601
BAT54S

603
X7R
5%

C605
100nF

603
X7R
5%

6

www.vinafix.vn

8

7

6

5

4

3

2

1

Thermal

Pad

9

6
7
8

Thermal

Pad

9

6
7
8

MQ702

Thermal

Pad

4 5
3
2
1

FDS7096N3

+MVDDC_S

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

Rs

R719
33MOHM

1210
1%

C708
10nF_25V

402
X7R
25V

Place Rs and Cs across QL

MVDDC_FB

9

6
7
8

*** ***

C715

C716

10UF

10UF

*** ***

L701 2.2uH_13A

1 2

Cs

MULTI FOOTPRINT

C718

C717

150nF_16V

10UF

1206

603

C713

2.2nF_50V

R713

49.9R

R1

R711

1.78K

402
1%

Place R1 and

R4

R4 close to
PWM and

R710

routed with

1.3K

separate

402

20mil trace to

1%

the ASIC

RC snubber values shown
are for reference only,
tuning is required

+12V_BUS

B701
60R

***

+MVDD

***

C725
470uF_10V

***

DUAL FOOTPRINT

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

***

MC725
470uF_6.3V

***

ALT
POLY

*** ***

C723
100uF_6.3V

1210 1210

*** ***

C724
100uF_6.3V

Q701

QH

MVDDC-PWM1

U702

MVDDC_EN
MVDDC_FB
+PW_MVDDC_M

R701 10K

1

HSD

ILIM

DH

2

COMP

DL

3

FB

GND

9

LX

10

BST

PGND

MAX1954EUB

MAXIM MAX1954
MAXIM MAX1954A

MVDDC_EN

402

MVDDC-PWM2

U701

1

RT

2

OCSET

3

SS

4

COMP

5

FB

6

EN

7

GND

ISL6522CB

INTERSIL ISL6522
RICHTEK RT9232A
ANPEC APW7062A
ANPEC APW7062B

+MVDDC_S

603

R718

1%

301K

C709

D D

C C

C710
470pF_50V

402
X7R

+MVDDC_S

MVDDC_COMP

C701
22nF

603

47pF_50V

402
NPO
5%

R702 30.1K

402

C702 1nF
R703 2.37K

402

R704 0R

402

+MVDDC_B

+3.3V_BUS

MVDDC_RT

402
X7R10V

MVDDC_OCS
MVDDC_SS
MVDDC_COMP_U1049
MVDDC_FB

+PW_MVDDC_HGD

8

+PW_MVDDC_LGD

6
5

+MVDDC_VCC

IN

4

7

SMPS_EN2 (1)

PVCC

LGATE

PGND

BOOT
UGATE
PHASE

+12V_BUS_F2

C704

+MVDDC_B

0.22uF

+PW_MVDDC_LGD

+PW_MVDDC_HGD
+PW_MVDDC_M

14

VCC

13
12
11
10
9
8

MVDDC-PWM3

+PW_MVDDC_HGD

+MVDDC_B

+PW_MVDDC_LGD

U703

2

3
1

8

UGATE

PS

7

OPS

GND

6

BOOT

FB

5

LGATE4VCC

RT9214CS

RICHTEK RT9214
INTERSIL ISL6545

+PW_MVDDC_M
MVDDC_EN
MVDDC_FB

R708 20K

+12V_BUS_F2

C703

0.22uF

402

+PW_MVDDC_HGD

+PW_MVDDC_M

+PW_MVDDC_LGD

+PW_MVDDC_HGDR

MQ701

Thermal

Pad

4 5
3
2
1

FDS7096N3

+PW_MVDDC_M

+MVDDC_S

9

6
7
8

R721 0R

R722 0R

+PW_MVDDC_HGDR

402

+PW_MVDDC_LGDR

402

4 5
3
2
1

BSC119N03SG

Q702

QL

4 5
3
2
1

BSC119N03SG

+PW_MVDDC_LGDR

MVDDC-PWM4

B B

MVDDC_FB

MVDDC_COMP
+12V_BUS_F2

R723 0R

MVDDC_COMP_U204

402

2

3
1

U704

RT9214CS

UGATE

GND
BOOT
LGATE4VCC

8

PS

7

OPS

+MVDDC_B

6

FB

R709 1K

5

+PW_MVDDC_LGD

+PW_MVDDC_HGD

+PW_MVDDC_M

402

ANPEC APW7061A

R714 0R

402

MVDDC_EN MVDDC_ COMP

This symbol is used for 103 SMPS p/n.

MVDD1

RV410SOCKET

Regulator for MVDD

Vout = 1.8V ~ 2.85V

COMPENSAT IO N CIRCUIT FILTERED +12V_BUS BOOT C I RCUIT

MR706
0R

402 402

21

D701
SD103AWS

R705
0R

16V

+5V+12V_BUS

R706
0R

C706
150nF_16V

402

+MVDDC_VCC

+MVDDC_B

+PW_MVDDC_M

5

4

3

+12V_BUS

R715
0R

402402

A A

C711
10nF

402

10V
10%

R712

4.99K

402
1%

C712
33pF

603

50V

NPOX7R

10%

R716 0R
R717

0R

402

8

MVDDC_COMP

MVDDC_FB

402

+12V_BUS_F2

7

+12V_BUS

R707

2.2R

C707
100nF

MD701
BAT54S

603
X7R
5%

C705
100nF

603
X7R
5%

6

Part R2R1

0.8V Ref

Vout

1.9V

2.0V 1.69K 1.1K

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Document Number Rev

Custom

Date: Sheet

2

1.78K 1.3K

1.78K 1.21K

105-A671xx-00

2

of

920Saturday, October 08, 2005

1

www.vinafix.vn

8

7

6

5

4

3

2

1

Option for Dynamic VDDC

+5V

D D

GPIO15 LO = LED "OFF" AND 1 .2V VDDC
GPIO15 HI = LED "ON" AND 1.0V VDDC

GPIO_15(7)

R696 1K

R695

R694

10K

10K

402

402

DNI

+3.3V

C C

402

Regulator for +MVDDQ
Vout = 1.85V ~ 2.65V
Iout = 1.7A MAX
P_QMVDD = 2.5W MAX

2 1

D699
LED

**

MC981
22uF_16V

**

ALT

C699
100nF

2 4

3 5

C981
10uF

VDDC_FB(8)

Install a 0 Ohm resistor for
Rx for regular operation

R697 0R

DNI

U699
NC7SZ04M5

C983
1uF_6.3V

LF CAP CER 1UF 10% 6.3V X5R (0402)

+MVDD

4

Rm1

**

C982

MC982
22uF_16V

**

ALT

Rm2

10uF

R699
301R

402

VCORE_PLAY

R698
75R

Rx

402

+3.3V

MVDD_EN(11)

Q951
FQD20N06TM

12A 60V
Rds(on) = 0.15R MAX

QMVDD

1

3 2

C985
10uF

R954

CAP, TANTALUM 10UF 20% 6.3V A CASE

562R

402
1%

R6 = (R5 x Vr e f) / (Vout - Vref)

R955
1K

603
1%

32

MVDD_G

MVDD_FB

2N7002E
Q699

1

C986
100nF

Place Big Copper Area Under QMVDD
pin 2 and 4 for Heat Dissipation.

+12V_BUS

R956
470R

1/4W
1206

5%

3 2

C984
150nF_16V

LF CAP CER 150NF 10% 16V X7R (0603)

REG951
AS432S

4

1

NC

1

NC

2

5 3

MREG951
SC431LC5SK-1

Voltage Req.

2.85V

2.55V 316022R100G22.1R

2.5V

Rm1 Rm2

0R 3150000000 DNI
681R 3160681000G 953R 3240953000

562R1.9V min, 1. 94V nom. 1K

1.1K

3240110100G

3160681000G681R2.0V min

1.1K 3240110100G

2.5V Ref.

2.5V Ref.

1.24V Ref.2.1V min

1.24V Ref.

1.24V Ref.3160562000G 3160100100G

DUAL FOOTPRINT

CAP CER 10UF 10% 6.3V X5R

B B

A A

8

7

(0805)1.4MM MAX THICK

+2.5V +2.5V

R908
0R

402
1%

Q905

1

MMBT3904

2 3

R909
249R

402
1%

3 2

REG905
AS432S

1

DUAL FOOTPRINT

R906
604R

1%

R907

1.37K

1%

6

R905
10R

805, 1/10W

Rt1

402

4

NC

1

NC

2

MREG905

Rt2

5 3

402

SC431LC5SK-1

D905

1.8V

2 1

+1.8V

C906

C905

100nF

10uF

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Document Number Rev

Custom

5

4

3

Date: Sheet

2

105-A671xx-00

2

of

10 20Saturday, October 08, 2005

1

www.vinafix.vn

8

+3.3V_BUS

+2.5V_REF

4
1
2

5V_EN

8

C901
10uF

+2.5V

+12V_BUS

3
2

R913
1K

1%

DNI

5
6

R923
1K

1%

10

9

R933
1K

1%

12
13

R943
1K

1%

+

-

+

-

R922 1K

+

-

R932 1K

+

-

R942 1K

B901
120R_300mA

ALT

Possible alternate
5150005600G

Place caps very
close to power pin

C903

C902

100nF

100nF

603

603

X7R

X7R

411

R910 0R

1

U901A
LM324M

C917
10nF

R912 0R

R920 0R

7

C929

U901B

10nF

LM324M

1%

Req = 120.7R
Use 845R, 1206, 1/4W

8

C939

U901C

10nF

LM324M

1%

Req = 120.7R
Use 845R, 1206, 1/4W

14

C949

U901D

10nF

LM324M

1%

R901
33R

402

REG901

TL431C

D D

+2.5V_REF

+VDDC

C C

B B

A A

+2.5V_REF

+2.5V_REF

+2.5V_REF

NC
NC

5 3

MR911 1K

R911 1K

R918 1K

R921 1K

R931 1K

R941 1K

7

Alt regulator for +MPVDD
Vout = 1.2V (not tracking to VDDC)
Iout = 10mA MAX

+3.3V

3 2

R915
75R

REG911
AS432S

+MPVDD

R916
681R

1%

1

R917

1.5K

1%

+VDDC

B911
120R_300mA

ALT

Possible al te r na t e 5150005600G

Rt1

402

Rt2

402

4

NC

1

NC

2

5 3

MREG911
SC431LC5SK-1

GND_MPVSS

1.61V 432R

1.69V

1.718V

1.75V

+3.3V

C916

+MPVDD

1/4 W

10uF

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

C911
10uF

Q911

1

MMBT3904

200mA, SOT-23

2 3

CMPT3904: 40V 200mA

R914

4.99R

~ 2.5V Drop MAX
200mW MAX

R924 40.2R

270mW MAX for 60mA

Q921

1

R930 0R

R925 0R

1

1

2 3

7

MMBT3904

200mA, SOT-23

2 3

CMPT3904: 40V 200mA

R934
845R

Q931
MMBT3904

200mA, SOT-23

2 3

CMPT3904: 40V 200mA

R944

R945

845R

845R

Q941
MMBT3904

200mA, SOT-23
CMPT3904: 40V 200mA

R935
845R

C921
10uF

R946
845R

R936
845R

+5V

C922
100nF

R937
845R

+5V_VESA

Multi-footprint

C931
10uF

R947
845R

+5V_VESA2

Multi-footprint

C941
10uF

R948
845R

R938
845R

R949
845R

MC941

4.7uF

R939
845R

MC931

4.7uF

6

Rt1

32404320001.52V 432R
3160432000 3160215100

3240432000
3240432000432R

562R

3240562000
3160604000604R
3160604000 604R1.8V

+12V_BUS

C928

C927

100nF

100nF

603

603
16V 16V
X7R X7R

+5V

5V
60mA MAX

C938

R940

100nF

845R

603

16V 16V

X7R X7R

C948

R950

100nF

845R

603

16V 16V

X7R X7R

+2.5V +AVDD +A2VDD

B921
120R_300mA

Possible al te r na t e 5150005600G

6

Rt2

2.15K

1.5K

3230015200

1.5K 3160150100
3240121100

1.21K

32300152001.5K

1.5K 3160150100

32300152001.5K

1.5K 3160150100

31601371001.37K

C926
10UF

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

+12V_BUS

C937

C936

100nF

10UF

603

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

+12V_BUS

C946

C947

10UF

100nF

603

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

B922
120R_300mA

5

Optional regulator for +PCIE
Vout = 1.2V ~1.25V
Iout = 1.2A MAX

+PCIE_SOURCE

+3.3V +2.5V

+3.3V +VDDC_CT

+VDDC

R981
0R

402
1%

R982

2.0K

402
1%
DNI

+VDD1DI +VDD2DI +PVDD

B923
120R_300mA

B924
120R_300mA

5

+5V

C957

C958

10uF

1uF_6.3V

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

Optional regulator for +2.5V
Vout = 2.5V
Iout = 600mA MAX

+5V

C967

C968

10uF

1uF_6.3V

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

Optional Regulator for +VDDC_CT
Vout = 2.5V ~ 2.85V
Iout = 100mA MAX

+5V

C977

C978

10uF

1uF_6.3V

CAP CER 10UF 10% 6.3V X5R
(0805)1.4MM MAX THICK

+12V_BUS

R983

5.1K

402
5%

Q991

1

MMBT3904

2 3

B925
120R_300mA

U951_VCNTL
U951_VIN

C956
10uF

U961_VCNTL
U961_VIN

C966
10uF

U971_VCNTL
U971_VIN

C976
10uF

R986 5.1K

4

+3.3V

MR971
1K

1

402
5%

B926
120R_300mA

4

+2.5V_REF

+2.5V_REF

+5V

5V_EN

2 3

R951

1.07K

U951_REFEN

R952

C954

1K

1uF_6.3V

R961

1.07K

U961_REFEN

R962
1K

C964

DNI

1uF_6.3V

R971

4.75K

U971_REFEN

R972

C974

6.34K

1uF_6.3V

Q992

R987 5.1K

MMBT3904

402
5%

+TPVDD +TXVDDR

B927
120R_300mA

3

+VDDC +PCIE

RP951A EXB28VR000X
RP951B EXB28VR000X
RP951C EXB28VR000X
RP951D EXB28VR000X

+PCIE

U951_VOUT

R953
1K

+MVDD

R963
1K

+MVDD +VDDC_CT

R973
1K

MVDD_EN (10)

Q993

1

MMBT3904

2 3

+T2PVDD +T2XVDDR

B928
120R_300mA

C952

C953

10uF

22uF_16V

CAP CER 10UF 10%

6.3V X5R (0805)1.4MM
MAX THICK

RP961A EXB28VR000X
RP961B EXB28VR000X
RP961C EXB28VR000X
RP961D EXB28VR000X

U961_VOUT

CAP CER 10UF 10%

6.3V X5R (0805)1.4MM
MAX THICK

RP971A EXB28VR000X
RP971B EXB28VR000X
RP971C EXB28VR000X
RP971D EXB28VR000X

U971_VOUT

CAP CER 10UF 10%

6.3V X5R (0805)1.4MM
MAX THICK

+12V_BUS

R988 5.1K

1

402
5%

B929
120R_300mA

3

2

8 1
7 2
6 3
5 4

U951_VIN
U951_REFEN U951_VCNTL

U951_VOUT

C951
10uF

8 1
7 2
6 3
5 4

U961_VIN
U961_REFEN

U961_VOUT

C961
10uF

8 1
7 2
6 3
5 4

U971_VIN
U971_REFEN

U971_VOUT

C971
10uF

+3.3V_BUS +PCIE_SOURCE

R984
10K

Q995_G

Q994
MMBT3904

2 3

B930
120R_300mA

U951

1

VIN

NC#8

2

GND

NC#7

3

VREF

VCNTL

VOUT4NC

THM

APL5331

Supported footprint:
RT9173C/RT9199A/RT9199
APL5331

+2.5V

U961

1

VIN

NC#8

2

GND

NC#7

3

VREF

VCNTL

VOUT4NC

THM

APL5331

Supported footprint:
RT9173C/RT9199A/RT9199
APL5331

RP972A EXB28VR000X
RP972B EXB28VR000X
RP972C EXB28VR000X
RP972D EXB28VR000X

U971

1

VIN

NC#8

2

GND

NC#7

3

VREF

VCNTL

VOUT4NC

THM

APL5331

Supported footprint:
RT9173C/RT9199A/RT9199
APL5331

C992
10uf

1206
Y5V

6.3V

C991
100nF

402
X5R
10V

Q995
IRF7413PBF

678

4 5

RT9199 p/n 2480054800G (480mR RdsON Max)
RT9199A (300mR RdsON Max)
RT9173C (250mR RdsON Max)
APL5331 p/n 2480054200G (350mR MAX for 2A)

8
7
6
5
9

8
7

U961_VCNTL

6
5
9

8 1
7 2
6 3
5 4

8
7
6
5
9

123

Title
Size Document Number Rev
Date: Sheet

2

+2.5V

U971_VCNTL

+3.3V

R992

R991

B992
60R

ALT

R985
100K

4.7R

Req ~= 0.78R
Vdrop_max = 0.95V @ 1.2A
+PCIE_SOURCE ~= 2.35V
For 1.2A, each resistor (250mW

rated) dissipates 0.2A or 190mW

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

C

R993

4.7R

4.7R

1/4W 1/4W 1/4W 1/4W 1/4W1/4W

105-A671xx-00

R994

4.7R

1

R996

R995

4.7R

4.7R

2

of

11 20Saturday, October 08, 2005

1

www.vinafix.vn

M_MDA[63..0](5) M_MDB[63..0](5)

D D

RASA#0(5)

+MVDD

R219

2.37K

R220

5.49K

+MVDD

R221

2.37K

R222

5.49K

+MVDD

+MVDD

CKEA0(5)
CSA#0_0(5)
WEA#0(5)
RASA#0(5)
CASA#0(5)

CLKA1(5)
CLKA#1(5)

CKEA1(5)
CSA#1_0(5)
WEA#1(5)
RASA#1(5)
CASA#1(5)

C401
1uF_6.3V

C412
1uF_6.3V

C423
1uF_6.3V

C428
1uF_6.3V

CLKA0(5)
CLKA#0(5)

CASA#0(5)
CKEA0(5)

CSA#0_0(5)
WEA#0(5)
CLKA#0(5)

CLKA0(5)

M_QSA2
M_QSA3
M_QSA1
M_QSA0

M_QSA#2
M_QSA#3
M_QSA#1
M_QSA#0

M_DQMA#2
M_DQMA#3
M_DQMA#1
M_DQMA#0

DRAM_RST(5)

R218 243R

C438
1uF_6.3V

C440
1uF_6.3V

R201 60.4R
R202 60.4R

R203 121R
R204 121R
R205 121R
R206 121R
R217 121R

R251 60.4R
R252 60.4R

R253 121R
R254 121R
R255 121R
R256 121R
R257 121R

C403

C402

1uF_6.3V

1uF_6.3V

C414

C413

1uF_6.3V

1uF_6.3V

C424

C425

1uF_6.3V

1uF_6.3V

C429

C430

1uF_6.3V

1uF_6.3V

C C

B B

A A

5

U201

M_MDA22

T3

DQ31 | DQ23

M_MDA23

T2

DQ30 | DQ22

M_MDA20

R3

M_MDA21

R2

M_MDA18

M3

M_MDA19

N2

M_MDA16

L3

M_MDA17

M2

M_MDA31

T10

M_MDA29

T11

M_MDA30

R10

M_MDA28

R11

M_MDA26

M10

M_MDA27

N11

M_MDA24

L10

M_MDA25

M11

M_MDA14

G10

M_MDA15

F11

M_MDA13

F10

M_MDA12

E11

M_MDA10

C10

M_MDA11

C11

M_MDA9

B10

M_MDA8

B11

M_MDA7

G3

M_MDA6

F2

M_MDA5

F3

M_MDA4

E2

M_MDA3

C3

M_MDA0

C2

M_MDA2

B3

M_MDA1

B2

H10

M_MAA14 M_MAA14

G9

M_MAA15 M_MAA15

G4

M_MAA7

L4

M_MAA8

K2

M_MAA3

M9

M_MAA10

K11

M_MAA11

L9

M_MAA2

K10

M_MAA1

H11

M_MAA0

K9

M_MAA9

M4

M_MAA6

K3

M_MAA5

H2

M_MAA4

K4
F9
H9

M_MAA13 M_MAA13

H3
F4
H4

J10
J11

P3

P10

D10

D3
P2

P11

D11

D2
N3

N10

E10

E3
V9
A4

H1

C439
1uF_6.3V

H12

136BALL-GDDR3

C441
1uF_6.3V

+MVDD +MVDD

+MVDD

C404

C405

1uF_6.3V

1uF_6.3V

C415

C416

1uF_6.3V

1uF_6.3V

C427

C426

1uF_6.3V

1uF_6.3V

C432

C431

1uF_6.3V

1uF_6.3V

5

VDDQ#A12
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4
VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1
VSSQ#T4
VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

GND | VDD

M_MAA[15..0](5) M_MAB[15..0](5)

C406

C407

1uF_6.3V

1uF_6.3V

C418

C417

1uF_6.3V

1uF_6.3V

+MVDD

C433
10uF

+MVDD

A1

VDDQ

A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

+MVDD

A2

VDD

A11
F1
F12
M1
M12
V2
V11

B1

VSSQ

B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3

VSS

A10
G1
G12
L1
L12
V3
V10

K1

VDDA

K12

J12
J1

VSSA

J3

RFU2

J2

RFU1

V4

RFU0

A9

MF

C408
1uF_6.3V

C419
1uF_6.3V

+MVDD +MVDD

C434
10uF

+MVDD

B201
B202

220R_200mA
220R_200mA

C443

C442

1uF_6.3V

1uF_6.3V

C410
1uF_6.3V

C421
1uF_6.3V

C436
10uF

TP201
22mil

C411
1uF_6.3V

C422
1uF_6.3V

C437
10uF

R259

2.37K

R260

5.49K

R261

2.37K

R262

5.49K

+MVDD

+MVDD

M_QSA[7..0](5)

M_QSA#[7..0](5)

+MVDD

+MVDD

C451
1uF_6.3V

C462
1uF_6.3V

C473
1uF_6.3V

C478
1uF_6.3V

R223
0R

R224
0R

+MVDD +MVDD +MVDD +MVDD

M_MAA15
M_MAA14
M_MAA13
M_MAA12
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

C409
1uF_6.3V

C420
1uF_6.3V

C435
10uF

M_MDA61
M_MDA62
M_MDA60
M_MDA63
M_MDA58
M_MDA59
M_MDA56
M_MDA57
M_MDA54
M_MDA55
M_MDA52
M_MDA53
M_MDA49
M_MDA51
M_MDA48
M_MDA50
M_MDA39
M_MDA38
M_MDA37
M_MDA36
M_MDA34
M_MDA35
M_MDA33
M_MDA32
M_MDA47
M_MDA46
M_MDA45
M_MDA44
M_MDA40
M_MDA41
M_MDA43
M_MDA42

RASA#1(5)

M_MAA7
M_MAA8
M_MAA3
M_MAA10
M_MAA11
M_MAA2
M_MAA1
M_MAA0
M_MAA9
M_MAA6
M_MAA5
M_MAA4

CASA#1(5)
CKEA1(5)

CSA#1_0(5)
WEA#1(5)
CLKA#1(5)

CLKA1(5)

M_QSA7
M_QSA6
M_QSA4
M_QSA5

M_QSA#7
M_QSA#6
M_QSA#4
M_QSA#5

M_DQMA#7
M_DQMA#6
M_DQMA#4
M_DQMA#5

DRAM_RST(5)

R258 243R

C488
1uF_6.3V

C490
1uF_6.3V

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7

M_QSA#0
M_QSA#1
M_QSA#2
M_QSA#3
M_QSA#4
M_QSA#5
M_QSA#6
M_QSA#7

C452
1uF_6.3V

C463
1uF_6.3V

C474
1uF_6.3V

C479
1uF_6.3V

4

C489
1uF_6.3V

C491
1uF_6.3V

C453
1uF_6.3V

C464
1uF_6.3V

C475
1uF_6.3V

C480
1uF_6.3V

4

U202

T3
T2

R3
R2
M3
N2

L3

M2
T10
T11

R10
R11
M10
N11

L10

M11
G10

F11
F10
E11

C10
C11

B10
B11

G3

F2
F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10

H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4

J10
J11

P3

P10

D10

D3

P2

P11

D11

D2
N3

N10

E10

E3

V9

A4

H1

H12

136BALL-GDDR3

C454
1uF_6.3V

C465
1uF_6.3V

C476
1uF_6.3V

C481
1uF_6.3V

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

M_DQMA#[7..0](5)

C455
1uF_6.3V

C466
1uF_6.3V

C477
1uF_6.3V

C482
1uF_6.3V

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4

VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1

VSSQ#P4

VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

GND | VDD

C456
1uF_6.3V

C467
1uF_6.3V

+MVDD

3

+MVDD

A1

VDDQ

A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

+MVDD

A2

VDD

A11
F1
F12
M1
M12
V2
V11

B1

VSSQ

B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3

VSS

A10
G1
G12
L1

VSS#L1

L12
V3

VDDA

VSSA

RFU2
RFU1
RFU0

MF

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

C457
1uF_6.3V

C468
1uF_6.3V

C483
10uF

V10

K1
K12

J12
J1

J3
J2
V4

A9

C458
1uF_6.3V

C469
1uF_6.3V

C484
10uF

C492
1uF_6.3V

B251
B252

220R_200mA
220R_200mA

C493
1uF_6.3V

R263
0R

R264
0R

C459
1uF_6.3V

C470
1uF_6.3V

C485
10uF

C460
1uF_6.3V

C471
1uF_6.3V

C486
10uF

+MVDD

www.vinafix.vn

+MVDD

R309

2.37K

R310

5.49K

+MVDD

R311

2.37K

R312

5.49K

C461
1uF_6.3V

C472
1uF_6.3V

C487
10uF

RASB#0(5)

CASB#0(5)
CKEB0(5)

CSB#0_0(5)
WEB#0(5)
CLKB#0(5)

CLKB0(5)

DRAM_RST(5)

R308 243R

C538
1uF_6.3V

C540
1uF_6.3V

CLKB0(5)
CLKB#0(5)

CKEB0(5)
CSB#0_0(5)
WEB#0(5)
RASB#0(5)
CASB#0(5)

CLKB1(5)
CLKB#1(5)

CKEB1(5)
CSB#1_0(5)
WEB#1(5)
RASB#1(5)
CASB#1(5)

+MVDD

C501
1uF_6.3V

C512
1uF_6.3V

+MVDD

C523
1uF_6.3V

C528
1uF_6.3V

3

M_QSB2
M_QSB3
M_QSB1
M_QSB0

M_QSB#2
M_QSB#3
M_QSB#1
M_QSB#0

M_DQMB#2
M_DQMB#3
M_DQMB#1
M_DQMB#0

M_MDB22
M_MDB23
M_MDB20
M_MDB21
M_MDB18
M_MDB19
M_MDB16
M_MDB17
M_MDB31
M_MDB30
M_MDB29

R10

M_MDB28

R11

M_MDB26

M10

M_MDB27

N11

M_MDB25
M_MDB24

M11

M_MDB14

G10

M_MDB15
M_MDB13
M_MDB12
M_MDB10

C10

M_MDB11

C11

M_MDB9
M_MDB8
M_MDB7
M_MDB6
M_MDB5
M_MDB4
M_MDB3
M_MDB0
M_MDB2
M_MDB1

H10

M_MAB14
M_MAB15

M_MAB7
M_MAB8
M_MAB3
M_MAB10
M_MAB11
M_MAB2
M_MAB1

H11

M_MAB0
M_MAB9
M_MAB6
M_MAB5
M_MAB4

M_MAB13

D10

D11

N10

C539
1uF_6.3V

H12

C541
1uF_6.3V

R301 60.4R
R302 60.4R

R303 121R
R304 121R
R305 121R
R306 121R
R307 121R

R351 60.4R
R352 60.4R

R353 121R
R354 121R
R355 121R
R356 121R
R357 121R

C502
1uF_6.3V

C513
1uF_6.3V

C524
1uF_6.3V

C529
1uF_6.3V

U301

T3

DQ31 | DQ23

T2

DQ30 | DQ22

R3

DQ29 | DQ21

R2

DQ28 | DQ20

M3

DQ27 | DQ19

N2

DQ26 | DQ18

L3

DQ25 | DQ17

M2

DQ24 | DQ16

T10

DQ23 | DQ31

T11

DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26

L10

DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7

F11

DQ14 | DQ6

F10

DQ13 | DQ5

E11

DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2

B10

DQ9 | DQ1

B11

DQ8 | DQ0

G3

DQ7 | DQ15

F2

DQ6 | DQ14

F3

DQ5 | DQ13

E2

DQ4 | DQ12

C3

DQ3 | DQ11

C2

DQ2 | DQ10

B3

DQ1 | DQ9

B2

DQ0 | DQ8

BA2 | RAS

G9

BA1 | BA0

G4

BA0 | BA1

L4

A11 | A7

K2

A10 | A8

M9

A9 | A3

K11

A8/AP | A10

L9

A7 | A11

K10

A6 | A2
A5 | A1

K9

A4 | A0

M4

A3 | A9

K3

A2 | A6

H2

A1 | A5

K4

A0 | A4

F9

CS | CAS

H9

WE | CKE

H3

RAS | BA2

F4

CAS | CS

H4

CKE | WE

J10

CK

J11

CK

P3

RDQS3 | RDQS2

P10

RDQS2 | RDQS3
RDQS1 | RDQS0

D3

RDQS0 | RDQS1

P2

WDQS3 | WDQS2

P11

WDQS2 | WDQS3
WDQS1 | WDQS0

D2

WDQS0 | WDQS1

N3

DM3 | DM2
DM2 | DM3

E10

DM1 | DM0

E3

DM0 | DM1

V9

RESET

A4

ZQ

H1

VREF
VREF#H12

136BALL-GDDR3

C503
1uF_6.3V

C514
1uF_6.3V

C525
1uF_6.3V

C530
1uF_6.3V

+MVDD

C504
1uF_6.3V

C515
1uF_6.3V

C526
1uF_6.3V

C531
1uF_6.3V

VDDQ#A12

VDDQ#C12

VDDQ#E12

VDDQ#N12

VDDQ#R12
VDDQ#V12

VSSQ#B12

VSSQ#D12
VSSQ#G11

VSSQ#L11

VSSQ#P12

VSSQ#T12

VDDA#K12

VSSA#J12

C505
1uF_6.3V

C516
1uF_6.3V

C527
1uF_6.3V

C532
1uF_6.3V

VDDQ

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#V1

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ
VSSQ#B4
VSSQ#B9

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#G2

VSSQ#L2

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#T1
VSSQ#T4
VSSQ#T9

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VSSA

RFU2
RFU1
RFU0

GND | VDD

C506
1uF_6.3V

C517

1uF_6.3V

VDD

VSS

MF

+MVDD

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

C507
1uF_6.3V

C518
1uF_6.3V

C533
10uF

+MVDD

+MVDD

C542
1uF_6.3V

C508
1uF_6.3V

C519
1uF_6.3V

C534
10uF

2

U302

M_MDB61

T3

DQ31 | DQ23

M_MDB62

T2

DQ30 | DQ22

M_MDB60

R3

DQ29 | DQ21

M_MDB63

R2

DQ28 | DQ20

M_MDB58

M3

DQ27 | DQ19

M_MDB59

N2

DQ26 | DQ18

M_MDB56

L3

DQ25 | DQ17

M_MDB57

M2

DQ24 | DQ16

M_MDB54

T10

DQ23 | DQ31

M_MDB55

T11

DQ22 | DQ30

M_MDB52

R10

DQ21 | DQ29

M_MDB53

R11

DQ20 | DQ28

M_MDB49

M10

DQ19 | DQ27

M_MDB51

N11

DQ18 | DQ26

M_MDB48

L10

DQ17 | DQ25

M_MDB50

M11

DQ16 | DQ24

M_MDB39

G10

DQ15 | DQ7

M_MDB38

F11

DQ14 | DQ6

M_MDB37

F10

DQ13 | DQ5

M_MDB36

E11

DQ12 | DQ4

M_MDB34

C10

DQ11 | DQ3

M_MDB35

C11

DQ10 | DQ2

M_MDB33

B10

DQ9 | DQ1

M_MDB32

B11

DQ8 | DQ0

M_MDB47

G3

DQ7 | DQ15

M_MDB46

F2

DQ6 | DQ14

M_MDB45

F3

DQ5 | DQ13

M_MDB44

E2

DQ4 | DQ12

M_MDB40

C3

DQ3 | DQ11

M_MDB41

C2

DQ2 | DQ10

M_MDB43

B3

DQ1 | DQ9

M_MDB42

B2

DQ0 | DQ8

M_MAB14
M_MAB15

M_MAB7
M_MAB8
M_MAB3
M_MAB10
M_MAB11
M_MAB2
M_MAB1
M_MAB0
M_MAB9
M_MAB6
M_MAB5
M_MAB4

M_MAB13

M_QSB7
M_QSB6
M_QSB4
M_QSB5

M_QSB#7
M_QSB#6
M_QSB#4
M_QSB#5

M_DQMB#7
M_DQMB#6
M_DQMB#4
M_DQMB#5

C589
1uF_6.3V

C591
1uF_6.3V

C551
1uF_6.3V

C562
1uF_6.3V

C573
1uF_6.3V

C578
1uF_6.3V

H10

G9
G4

M9

K11
K10

H11

M4
H2

H9
H3

H4
J10

J11

P10
D10

D3

P11
D11

D2

N3
N10
E10

H1
H12

C552
1uF_6.3V

C563
1uF_6.3V

C574
1uF_6.3V

C579
1uF_6.3V

BA2 | RAS
BA1 | BA0
BA0 | BA1

L4

A11 | A7

K2

A10 | A8
A9 | A3
A8/AP | A10

L9

A7 | A11
A6 | A2
A5 | A1

K9

A4 | A0
A3 | A9

K3

A2 | A6
A1 | A5

K4

A0 | A4

F9

CS | CAS
WE | CKE
RAS | BA2

F4

CAS | CS
CKE | WE
CK

CK

P3

RDQS3 | RDQS2
RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

P2

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0

E3

DM0 | DM1

V9

RESET

A4

ZQ

VREF
VREF#H12

136BALL-GDDR3

C553
1uF_6.3V

C564
1uF_6.3V

C575
1uF_6.3V

C580
1uF_6.3V

RASB#1(5)

CASB#1(5)
CKEB1(5)

CSB#1_0(5)

C511
1uF_6.3V

C522
1uF_6.3V

R358 243R

C588
1uF_6.3V

C590
1uF_6.3V

C537
10uF

WEB#1(5)
CLKB#1(5)

CLKB1(5)

DRAM_RST(5)

+MVDD

+MVDD

+MVDD +MVDD

B301
B302

220R_200mA
220R_200mA

C543
1uF_6.3V

M_MAB15
M_MAB14
M_MAB13
M_MAB12
M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0

C509
1uF_6.3V

C520
1uF_6.3V

+MVDD

C535
10uF

TP301
22mil

C510
1uF_6.3V

C521
1uF_6.3V

R359

2.37K

R360

5.49K

R361

2.37K

R362

5.49K

+MVDD

+MVDD

C536
10uF

2

R313
0R

R314
0R

VDDQ

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ
VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1
VSSQ#T4
VSSQ#T9

VSSQ#T12

VSS

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VDDA#K12

VSSA#J12

VSSA

RFU2

RFU1

RFU0

MF

GND | VDD

M_QSB[7..0](5)

M_QSB#[7..0](5)

M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7

M_QSB#0
M_QSB#1
M_QSB#2
M_QSB#3
M_QSB#4
M_QSB#5
M_QSB#6
M_QSB#7

C554
1uF_6.3V

C565
1uF_6.3V

C576
1uF_6.3V

C581
1uF_6.3V

Title
Size Docum e n t N u mb er Re v
Date: Sheet

C556

C555

1uF_6.3V

1uF_6.3V

C566

C567

1uF_6.3V

1uF_6.3V

C577
1uF_6.3V

C582
1uF_6.3V

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

C

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

C592
1uF_6.3V

J12
J1

J3
J2
V4

A9

C557
1uF_6.3V

C568
1uF_6.3V

+MVDD

C583
10uF

105-A671xx-00

+MVDD

+MVDD

1

B351
B352

R363
0R

R364
0R

M_DQMB#[7..0](5)

C558
1uF_6.3V

C569
1uF_6.3V

C584
10uF

1

220R_200mA
220R_200mA

C593
1uF_6.3V

C559
1uF_6.3V

C570
1uF_6.3V

+MVDD

C585
10uF

M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7

C560
1uF_6.3V

C571
1uF_6.3V

12 20Saturday, O ctober 08, 2005

C586
10uF

C561
1uF_6.3V

C572
1uF_6.3V

of

C587
10uF

2

5

D D

TFP513

DVPDATA_R_0
DVPDATA_R_1
DVPDATA_R_2
DVPDATA_R_3
DVPDATA_R_4
DVPDATA_R_5
DVPDATA_R_6
DVPDATA_R_7
DVPDATA_R_8
DVPDATA_R_9
DVPDATA_R_10
DVPDATA_R_11

C C

DVP_CNTL_R_0
DVP_CNTL_R_1
DVP_CNTL_R_2

DVPCLK_R

MSEN_TMDS
HPD_ExtTMDS

I2C_RST
CRT3DDCDATA

CRT3DDCCLK

B B

63
62
61
60
59
58
55
54
53
52
51
50
47
46
45
44
43
42
41
40
39
38
37
36

6
4

5
2

57
56

11

9

13
14

15

17
20
26
32

65
66
67
68
69
70
71
72
73
74
75
76
77

U5002A

TFP513PAP

U5002B

TFP513PAP

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23

DK3
HSYNC

VSYNC
DE

IDCK+
IDCK-

MSEN
EDGE/HTPLG

ISEL/RST#
DSEL/SDA

BSEL/SCL

PGND
TGND20
TGND26
TGND32

GND_TH
GND_TH#66
GND_TH#67
GND_TH#68
GND_TH#69
GND_TH#70
GND_TH#71
GND_TH#72
GND_TH#73
GND_TH#74
GND_TH#75
GND_TH#76
GND_TH#77

PART 1 OF 2

PART 2 OF 2

THERMAL PAD

TX0+

TX1+

TX2+

TXC+

TVDD23
TVDD29

RESERVED34

VREF

TFADJ

PVDD

DVDD1
DVDD12
DVDD33

DGND16

RESERVED35

DGND64
DGND48

GND_TH#89
GND_TH#88
GND_TH#87
GND_TH#86
GND_TH#85
GND_TH#84
GND_TH#83
GND_TH#82
GND_TH#81
GND_TH#80
GND_TH#79
GND_TH#78

TX0-

TX1-

TX2-

TXC-

RDA
RCL

NC

PD#

24
25

27
28

30
31

21
22

+AVCC_TMDS
23
29

Ext-TMDS_PIN7

7

Ext-TMDS_PIN8

8
34

3
19

18
49

1
12
33

10
16
35
64
48

89
88
87
86
85
84
83
82
81
80
79
78

4

TX0M_DVI2
TX0P_DVI2

TX1M_DVI2
TX1P_DVI2

TX2M_DVI2
TX2P_DVI2

TXCM_DVI2
TXCP_DVI2

R5019

4.7K

402 402

RDA RCL

+VREF_TMDS

EXT_SWING

+PVCC1_TMDS
+PVCC2_TMDS

PD#

+3.3V_BUS

+3.3V_BUS

RST#_Ext-TMDS(7)
PERST#_buf(1,2,16)

12bit, Dual Edge DVO

DVPDATA_R_[11..0](7)

DVP_CNTL_R_[2..0](7)

DVPCLK_R(7)

R5020

4.7K

HPD2(7,15)

HPD_ExtTMDS(15)

DVPDATA_R_[11..0]

DVP_CNTL_R_[2..0]

+3.3V_BUS

R5001 5.1K
R5002 0R
MR5002 0R

CRT3DDCDATA(3,17)
CRT3DDCCLK(1,3,17)

R5006
10K

1
2

MR5007 0R

R5007 0R

+3.3V_BUS+3.3V_BUS

53

+-U5003

DVPDATA_R_0
DVPDATA_R_1
DVPDATA_R_2
DVPDATA_R_3
DVPDATA_R_4
DVPDATA_R_5
DVPDATA_R_6
DVPDATA_R_7
DVPDATA_R_8
DVPDATA_R_9
DVPDATA_R_10
DVPDATA_R_11

DVP_CNTL_R_0
DVP_CNTL_R_1
DVP_CNTL_R_2

DVPCLK_R

402

MSEN_TMDS

402
402

HPD_ExtTMDS
I2C_RST

4

TC7SZ08FU

402

402

3

I2C_RST

+PVCC1_TMDS

SiI170B

U5001

63
62
61
60
59
58
55
54
53
52
51
50
47
46
45
44
43
42
41
40
39
38
37
36

6
4

5
2

57
56

11

9

13
14

15

17
20
26
32

PCA9554BS

C5014

1uF_6.3V

402

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23

CTL3
HSYNC

VSYNC
DE

IDICK+
IDCK-

MSEN
HTPLG

ISEL/RST#
SDAS

SCLS

PGND1
AGND20
AGND26
AGND32

C5015
1uF_6.3V

402

6.3V
X5R

2

R5011 0R

T2X0M(3)

R5012 0R

T2X0P(3) TX0P_DVI2 (15)

R5013 0R

T2X1M(3)

R5014 0R

T2X1P(3)

R5015 0R

T2X2M(3)

R5016 0R

T2X2P(3)

R5017 0R

T2XCM(3)

R5018 0R

T2XCP(3)

AVCC23
AVCC29

RESERVED

EXT_SWING

DGND16
DGND35
DGND64

C5016

10uf

1206
Y5V

6.3V

TX0-

TX0+

TX1-

TX1+

TX2-

TX2+

TXC-

TXC+

NC7
NC8

VREF

PVCC1
PVCC2

VCC1
VCC12
VCC33

PD#

PGND2

+PVCC2_TMDS

24
25

27
28

30
31

21
22

23
29

7
8
34

3
19

18
49

1
12
33

10
16
35
64
48

C5017

1uF_6.3V

402

Ext-TMDS_PIN7
Ext-TMDS_PIN8

PD#

+3.3V_BUS

C5018
1uF_6.3V

402

6.3V
X5R

TX0M_DVI2
TX0P_DVI2

TX1M_DVI2
TX1P_DVI2

TX2M_DVI2
TX2P_DVI2

TXCM_DVI2
TXCP_DVI2

+VREF_TMDS

EXT_SWING

+PVCC1_TMDS
+PVCC2_TMDS

R5003
1K

R5004
1K

+AVCC_TMDS

MB5002

B5002

MB5003

B5003

C5019

10uf

1206
Y5V

6.3V

C5007

1uF_6.3V

C5008
1uF_6.3V

402

6.3V
X5R

C5001

1uF_6.3V

200R

200R

ALT: 0R

200R

200R

ALT: 0R

R5021 301R

R5022 301R

R5023 301R

R5024 301R

C5009
1uF_6.3V

1uF_6.3V

402 402

6.3V
X5R

C5002
1uF_6.3V

402 402402 402

6.3V
X5R

+3.3V_BUS

402

402

402 402

C5010

C5003

1uF_6.3V

+PVCC2_TMDS Filters

TX0M_DVI2 (15)

TX1M_DVI2 (15)
TX1P_DVI2 (15)

TX2M_DVI2 (15)
TX2P_DVI2 (15)

TXCM_DVI2 (15)
TXCP_DVI2 (15)

C5021 100nF

40240 2

C5022 100nF

402

C5023 100nF

402

C5024 100nF

C5011
1uF_6.3V

402402

6.3V
X5R

R_Ext-Swing

R5005 680R

C5004
1uF_6.3V

6.3V
X5R

+PVCC_TMDS

R5028
680R

402

R5029

2.0K

402

C5012

C5013

1uF_6.3V

10uf

402 1206

6.3V

Y5V

X5R

6.3V

+3.3V_BUS

C5005

10uf

1206
Y5V

6.3V

+PVCC_TMDS

3.3V

+12V_BUS

4

NC

1

NC

2

B5001

C5006
10uf

1206
Y5V

6.3V

R5025
470R

1206 1206

TL431C

5 3

R5026
470R

REG5025

200R

ALT: 0R

R5027
470R

1206

+3.3V_BUS

1

1206 1/4W each
Req = 157R
I = 55mA

+VDDR4

C5039

R5039

100nF

1K

402

402

1%

6.3V
X5R

C5040
100nF

402

6.3V

STUFFING OPTIONS

A A

SiI170B

NOTE:
1 - Other components are to be installed.
2 - Components marked as DNI should not be installed. They should only be installed if default board
settings are to be changed in which case other components may have to be adjusted accordingly.

SiI170B, +PVCC2_TMDS Filters
R_Ext-Swing =

505R <= R_Ext-Swing <= 515R

5

MUST NOT INSTALLMUST INSTALLEXT TMDS TX TO BE USED

TFP513

SiI170BTFP513, RDA, RCLTFP513

CAN BE REMOVED

RDA, RCL

(Optional) +PVCC2_TMDS Filters

4

3

2

X5R

+VREF_TMDS

R5040
1K

402
1%

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Document Number Rev

Custom

Date: Sheet

105-A671xx-00

1

2

of

13 20Saturday, October 08, 2005

www.vinafix.vn

8

D D

A_R_DAC1(3)
A_G_DAC1(3)
A_B_DAC1(3)

R1001 75R
R1002 75R
R1003 75R

RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane

C1004

3.3pF

402

7

L1001 47nH
L1002 47nH
L1003 47nH

C1005

C1006

3.3pF

3.3pF

402 402 402

C1001

8.0pF

A_R_DAC1_M
A_G_DAC1_M
A_B_DAC1_M

C1002

8.0pF

C1003

8.0pF

402402 402

6

L1004 47nH
L1005 47nH
L1006 47nH

5

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F

DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R

A_VSYNC_DAC1_R

4

+3.3V +12V_BUS

D1001

4

CH2

CH3

5

Vn

Vp

6

CH1

CH4

CM1213-04

C1008

C1009

C1007

5pF

5pF

5pF

L1008

L1007

L1009

82nH

82nH

82nH

805805805

3

3
2
1

4
5
6

D1002

CH3
Vp
CH4

CM1213-04

3

CH2

2

Vn

1

CH1

2

C1010
68pF

603603 603 603

+5V_VESA

MJ1001

1

R

2

G

3

B

11

MS0

12

MS1

4

MS2

15

MS3

9

NC

13

HS

14

VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8

10

VSS#10

16

CASE

17

CASE#17

G3179C219-005

1

DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)

+3.3V

R1004

4.7K

C C

B B

CRT1DDCDATA(1,3)

CRT1DDCCLK(1,3)

GENERICA(7)

A_HSYNC_DAC1(1,3,7)

A_VSYNC_DAC1(1,3,7)

GPIO_9(7)

GENERICB(7)

C1999 100nF

R1999 1K

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

402

+3.3V +5V

R1007

4.7K

402 402

+5V

14

2 3

1

7

4

5 6

MR1999
1K

U1999A
SN74HCT125D

SN74HCT125D
U1999B

A_HSYNC_DAC1_B

A_VSYNC_DAC1_B

1

32

BSH111
Q1001

1

32

BSH111
Q1002

R1014 2.0K

R1015 2.0K

+5V

R1005

6.8K

402

DDCDATA_DAC1_5V DDCDATA_DAC1_R

R1008

6.8K

402

DDCCLK_DAC1_5V

R1012 1K
C1012 2.0pF

R1013 1K
C1013 2.0pF

R1006 33R

R1009 33R

R1010

R1011

402

402

33R

402

33R

DDCCLK_DAC1_R

A_HSYNC_DAC1_R

A_VSYNC_DAC1_R

DB15 pin

Standard VGA
Monitor ID bit 0

11

Monitor ID bit 1

12

Monitor ID bit 2

4

Monitor ID bit 3

15

N/C

9

Mechanical Key
Hardware
Support

No Yes Yes No Yes

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA

25

TjX2M(3)
TjX2P(3)

TjX4M(3)
TjX4P(3)

DDCCLK_DAC1_R
DDCDATA_DAC1_R
A_VSYNC_DAC1_R

TjX1M(3)

+3.3V

Q1021

MMBT3904

HPD1(3)

2 3

R1023
10K

1

R1022 10K

TjX1P(3)
TjX3M(3)

TjX3P(3)

HPD_DVI1

TjX0M(3)
TjX0P(3)

TjX5M(3)
TjX5P(3)

TjXCP(3)
TjXCM(3)

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F
A_HSYNC_DAC1_R

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C1
C2
C3
C4
C5
C6

26
27
28
29
30

DDC1 Host
Monitor ID bit 0

Data from display
Monitor ID bit 2
Open
+5V
50mA min
1A max

J1001

CASE
TMDS Data2-

TMDS Data2+
TMDS Data2/4 Shield
TMDS Data4­TMDS Data4+
DDC Clock
DDC Data
Analog VSYNC
TMDS Data1­TMDS Data1+
TMDS Data1/3 Shield
TMDS Data3­TMDS Data3+
+5V Power
GND (for +5V)
Hot Plug Detect
TMDS Data0­TMDS Data0+
TMDS Data0/5 Shield
TMDS Data5­TMDS Data5+
TMDS Clock Shield
TMDS Clock+
TMDS Clock-

Analog Red
Analog Green
Analog Blue
Analog HYNC
Analog GND
Analog GND#C6

CASE#26
CASE#27
CASE#28
CASE#29
CASE#30

DVI CONNECTOR

DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max

DDC2AB Host
Monitor ID bit 0

SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max

DDC1/2 Display
Optional

SDA
Optional
SCL

Optional

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Document Number Rev

Custom

8

7

6

5

4

3

Date: Sheet

2

105-A671xx-00

2

of

14 20Saturday, October 08, 2005

1

www.vinafix.vn

8

7

6

5

4

3

2

1

+3.3V +12V_BUS

D2001

4

CH3

5

Vp

6

CH4

CM1213-04

C2001

8.0pF

8.0pF

C2017
100nF

C2016
100nF

A_R_DAC2_M
A_G_DAC2_M
A_B_DAC2_M

C2003

8.0pF

402402 402

D D

C C

B B

A_R_DAC2(3)
A_G_DAC2(3)
A_B_DAC2(3)

C2004

R2001 75R C2002
R2002 75R
R2003 75R

402

RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane

CRT2DDCDATA(3)

CRT2DDCCLK(3)

DVALID(7)

HPD2(7,13)

A_HSYNC_DAC2(3,7)

A_VSYNC_DAC2(3,7)

GPIO_8(7)

GENERICC(7)

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

R2000 1K

C2005

3.3pF

3.3pF

+3.3V

R2004

4.7K

402

+3.3V +5V

R2007

4.7K

402 402

GPIO_8

9 8

U1999C
SN74HCT125D

10
13

SN74HCT125D
U1999D

12 11

MR2000
1K

GPIO_8

R2017 0R

L2001 47nH
L2002 47nH
L2003 47nH

C2006

3.3pF

402 402 402

+5V

1

1

+3.3V

1

5

3

R2016 0R

A_HSYNC_DAC2_B

A_VSYNC_DAC2_B

3

1

5

32

BSH111
Q2001

32

BSH111
Q2002

24

U2016
74HCT1G126GW

R2014 2.0K

R2015 2.0K

24

U2017
74HCT1G126GW

R2005

6.8K

402

DDCDATA_DAC2_5V DDCDATA_DAC2_R

R2008

6.8K

402

DDCCLK_DAC2_5V

R2012 1K
C2012 2.0pF

R2013 1K
C2013 2.0pF

+3.3V

R2006 33R

R2009 33R

R2010

R2011

L2004 47nH
L2005 47nH
L2006 47nH

402

DDCCLK_DAC2_R

402

A_HSYNC_DAC2_R

33R

402

A_VSYNC_DAC2_R

33R

HPD_ExtTMDS(13)

A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F

DDCDATA_DAC2_R
DDCCLK_DAC2_R
A_HSYNC_DAC2_R

A_VSYNC_DAC2_R

MMBT3904

Q2021

C2007
5pF

L2007
82nH

TX3M_DVI2(3)
TX3P_DVI2(3)

TX4M_DVI2(3)
TX4P_DVI2(3)

TX5M_DVI2(3)
TX5P_DVI2(3)

+3.3V

R2022 10K

1

2 3

R2023
10K

C2008
5pF

L2008
82nH

T2X3M (3)
T2X3P (3)

T2X4M (3)
T2X4P (3)

T2X5M (3)
T2X5P (3)

CH2

CH1

C2009
5pF

L2009
82nH

805805805

3
2

Vn

1

D2002

4

CH3

5

Vp

6

CH4

CM1213-04

TX2M_DVI2(13)
TX2P_DVI2(13)

TX4M_DVI2(3)
TX4P_DVI2(3)

TX1M_DVI2(13)
TX1P_DVI2(13)

TX3M_DVI2(3)
TX3P_DVI2(3)

TX0M_DVI2(13)
TX0P_DVI2(13)

TX5M_DVI2(3)
TX5P_DVI2(3)

TXCP_DVI2(13)
TXCM_DVI2(13)

CH2

Vn

CH1

DDCCLK_DAC2_R
DDCDATA_DAC2_R
A_VSYNC_DAC2_R

HPD_DVI2

A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F
A_HSYNC_DAC2_R

3
2
1

+5V_VESA2

11
12

15
13

14

C2010
68pF

603603 603 603

DB15 pin

Standard VGA
Monitor ID bit 0

11

Monitor ID bit 1

12

Monitor ID bit 2

4

Monitor ID bit 3

15

N/C

9

Mechanical Key
Hardware
Support

No Yes Yes No Yes

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA2

DDC1 Host
Monitor ID bit 0

Data from display
Monitor ID bit 2
Open
+5V
50mA min
1A max

J2001

25

CASE

1

TMDS Data2-

2

TMDS Data2+

3

TMDS Data2/4 Shield

4

TMDS Data4-

5

TMDS Data4+

6

DDC Clock

7

DDC Data

8

Analog VSYNC

9

TMDS Data1-

10

TMDS Data1+

11

TMDS Data1/3 Shield

12

TMDS Data3-

13

TMDS Data3+

14

+5V Power

15

GND (for +5V)

16

Hot Plug Detect

17

TMDS Data0-

18

TMDS Data0+

19

TMDS Data0/5 Shield

20

TMDS Data5-

21

TMDS Data5+

22

TMDS Clock Shield

23

TMDS Clock+

24

TMDS Clock-

C1

Analog Red

C2

Analog Green

C3

Analog Blue

C4

Analog HYNC

C5

Analog GND

C6

Analog GND#C6

26

CASE#26

27

CASE#27

28

CASE#28

29

CASE#29

30

CASE#30

DVI CONNECTOR

10
16
17

MJ2001

1

R

2

G

3

B
MS0
MS1

4

MS2
MS3

9

NC
HS
VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8
VSS#10
CASE
CASE#17

G3179C219-005

DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max

DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)

DDC2AB Host
Monitor ID bit 0

SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max

DDC1/2 Display
Optional

SDA
Optional
SCL

Optional

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Document Number Rev

Custom

8

7

6

5

4

3

Date: Sheet

2

105-A671xx-00

2

of

15 20Saturday, October 08, 2005

1

www.vinafix.vn

8

+RTAVDD
Vout = 3.3V
Iout = 125mA MAX, 80mA RMS

REG3101
LM1117MPX-ADJNOPB

+RTAVDD

12

IN3OUT

10R

402

C3221
100nF

402

C3103
150nF_16V

D D

603

CompIn_R

LumaIn_R

C C

ChromaIn_R

L3221

3.3uH_50mA

C3222

22uF_16V

B B

2
4

CASE

ADJ

1

R3102
200R

1%

402

L3202 3.3u H _50mA

1 2

1206

L3201 3.3u H _50mA

1 2

1206

L3203 3.3u H _50mA

1 2

1206

RTXTALIN(3)

PERST#_buf(1,2,13)

R3101
121R

1%

C3206

R3206

330pF_50V

75R

402

402

C3204

R3204

330pF_50V

75R

402

402

C3205

R3205

330pF_50V

75R

402

402

As close as possible to
pin 56 of Rage Theater

C3101
10uF

7

+RTAVDD+12V_BUS

C3102
10uF

+RTAVDD

12

L3223

3.3uH_50mA

C3224

22uF_16V

12

L3225

R3225

10R

3.3uH_50mA

402

C3226

GND_VIN

C3225
100nF

402

C3209 100nF

C1105
68nF_25V

C1106

22nF

12

NS3201 NS_VIA
C3207 2.2uF_16V
C3208 2.2uF_16V

22uF_16V

R3223
10R

402

VADCFILTERVADCFILTER

C3223
100nF

402

VADCFILTER
VADCFILTER

R3221

4.7K

402
5%

6

47
49
48

66
60

61
33

34
35
36
37
38
39
40
27
28

58
59
57

56
55

43
45
44
46

50
51
52
53
54

69
70
73
74
67
68

VAGCVDD
VAGCVSS#49
VAGCVSS

VDACVDD
VDACBVSS

VDACJVSS
VIND0

VIND1
VIND2
VIND3
VIND4
VIND5
VIND6
VIND7
VINGATEA
VINGATEB

CF
CR
VAGCCAP

VIDEOGNDSENSE
VCLAMPCAP

VADCDVDD
VADCAVDD
VADCDVSS
VADCAVSS

COMP0
COMP1
COMP2
YF_COMP3
YR_COMP4

XTALIN
XTALOUT
TESTEN
RESETB
PLLVDD
PLLVSS

18

VSSC

26

VSSC#26

VSSC#77

77

83

71

81

29

VDDR1VDDC

VDDR#71

VDDR#81

VDDR#29

VSSR#2

VSSC#100

VSSC#83

VSSR#12

2

12

100

C3231
1uF_6.3V

25

99

76

VDDC#76

VSSR

VSSR#72

VSSR#3030VSSR#32

82

72

90

C3232
1uF_6.3V

41

31

VDDC#99

VDDR#31

CLKOUT0_GPIO0
CLKOUT1_GPIO1
CLKOUT2_GPIO2

VSSR#90

42

32

5

C3233
1uF_6.3V

U3201

SAD0
SAD1
SAD2

VDDC#41

SAD3
SAD4
SAD5
SAD6
SAD7

DS_VIPCLK

AS_HCTL

SRDY_IRQB

HAD0
HAD1

ADO
ADIO

BITCLK

SPDIF

BYTCLK

SYNC

Y_RED

C_GREEN

COMP_BLUE

RSET

GPIO3
GPIO4
GPIO5
GPIO6

PDATA0
PDATA1
PDATA2
PDATA3
PDATA4
PDATA5
PDATA6
PDATA7

PCLK

VSSC#42

Rage Theater 1 A43 LF

C3234

C3235

1uF_6.3V

1uF_6.3V

402 402 402 402 402402 402 402

91
92
93
94
95
96
97
98

RP3223C EXB28V330JX

88

RP3223A EXB28V330JX

87

R3228 47K

86

RP3223B EXB28V330JX

84

RP3223D EXB28V330JX

85
15

SDA

16

SCL

22
24
23

WS

21

19
89

75
62
63
64

R3321 383R

65

78
79
20
13
14
17
80

4
5
6
7
8
9
10
11
3

5%

R3322

C3236
1uF_6.3V

402
1%

8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4

Please close to RT

4

+3.3V_BUS

C3237

C3238

1uF_6.3V

1uF_6.3V

5%

63
81

5%

72
54

33R

+3.3V_BUS

R3325

4.7K
R3324
10K

402
1%

VID_0

RP3221AEXB28V330JX

VID_1

RP3221BEXB28V330JX

VID_2

RP3221CEXB28V330JX

VID_3

RP3221DEXB28V330JX

VID_4

RP3222AEXB28V330JX

VID_5

RP3222BEXB28V330JX

VID_6

RP3222CEXB28V330JX

VID_7

RP3222DEXB28V330JX

5%

R3326
10K

402402
1%5%

VIPCLK (7)

VPHCTL (7)
VHAD_0 (7)

VHAD_1 (7)

RTCLK (3)

VID_[7..0] (7)

VPCLK0 (7)

3

CompIn_R

LumaIn_R
ChromaIn_R

DAC2_COMP(3)RTXTALOUT(3)

2

PIN6
DAC2_Y_DIN

DAC2_C_DIN

C3202
330pF_50V

C3001
47pF_50V

C3002
47pF_50V

C3003
47pF_50V

DAC2_COMP_DIN

C3201
330pF_50V

L3001 4 70nH_250mA

L3002 4 70nH_250mA

L3003 4 70nH_250mAR3222

R3001
75R

R3002
75R

R3003
75R

CompIn

LumaIn
ChromaIn

R3203 0R

R3201 0R
R3202 0R

DAC2_Y(3)

DAC2_C(3)

J3201

6
3

4
7
5

1
2

11
12

8
9

10

GA1042C219-019F

Overlap with Rpin5

C3203
330pF_50V

C3004
47pF_50V

C3005
47pF_50V

C3006
47pF_50V

HDTV_OUT_DET#
Y-OUT

C-OUT
Comp-out
Comp-in

GND
GND#2

Luma-in
Chroma-in

CASE
CASE#9
CASE#10

1

DAC2_Y_F

DAC2_C_F

DAC2_COMP_F

Place near connector
0R leaves footprint fo r Ferrite
Beads if req'd for EMI

DAC2_C_F
DAC2_COMP_F

A A

8

7

6

5

www.vinafix.vn

4

R3004 0R
R3005 0R
R3006 0R

3

STV/HDTV#_OUT_DET(7)

402
402
402

DAC2_Y_DINDAC2_Y_F
DAC2_C_DIN
DAC2_COMP_DIN

+3.3V

R3008
10K

402

R3009 0R

402

C3007
82pF

The 7-pin Min i DIN footprint all ows one of the two MiniDINs:

- 7-pin Svideo/Composite MiniDIN P/N 6071001500G

- 4-pin Svideo MiniDIN P/N 6070001000G

C3009

C3008

82pF

82pF

402402 402

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docum e n t N u mb er Re v

C

Date: Sheet

2

TV Out

J3001

PIN6

6

HDTV_OUT_DET#

3

Y-OUT

4

C-OUT

7

Comp_out

CompIn

5

SYNC

1

GND

R3007

2

GND#2

0R

8

Rpin5

CASE

9

CASE#9

10

CASE#10

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

105-A671xx-00

of

16 20Saturday, O ctober 08, 2005

1

2

8

7

6

5

4

3

2

1

+3.3V

CAP CER 10UF 10% 6.3V X5R

INTERFACE INFO: SMBUS SLAVE
Clock: Min 10kHz - Max 100kHz
7 bit address: 100 1100

SCL_R
SDA_R
Tach

C4005
56pF_50V

402

NPO

402

(0805)1.4MM MAX THICK

C4006
56pF_50V

402

NPO

MMBT3906

Q4002

23

1

R4010 0R

C4007
1uF

805
16V

Y5V

R4004

R4003

10K

10K

D D

R4017
10K

Q4001
MMBT3904

2 3

R4001 100R
R4002 100R
R4015 0R

+12V_BUS

R4006

2.61K

402
1%

R4007
1K

402
1%

402

402

Rx can overlap QxQxRx

R4008 100K

CRT3DDCCLK(1,3,13)

CRT3DDCDATA(3,13)

PWM

H1

C C

B B

SUPERSET HEATSINK

COOLING SOLUTION GENERIC KEEP-OUT

H2

LOW PROFILE HS

PWM

R4005
0R

402

1

R4009
100K

402 402

1

2 3

DNI

+3.3V

C4001

10uF

U4001

8

SMBCLK

7

SMBDAT

6

ALERT
GND5PWM

LM63CIMAX

R4011
100K

Q4003
MMBT3904

R4012 10K

R4013

1.47K

402

C4002

1uF_6.3V

402 402

6.3V
X5R

VDD

1

402

C4003

100pF_50V

D+

D-

32

50V
NPO

1
2
3
4

Q4004

MJD45H11

PWM

+12V_BUS

C4004

2.2nF_50V

402
50V
X7R

B4001
26R_600mA

R4014
0R

402

DNI

GPU_DPLUS

GPU_DMINUS

C4008
1uF

805
16V

Y5V

Tach

GPU_ DPLUS (3)

GPU_DMINUS (3)ThermINT(7)

JU4001

1
2

MJU4001

1
2
3

Header_1X3

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docum e n t N u mb er Re v

C

8

7

6

5

www.vinafix.vn

4

3

Date: Sheet

2

105-A671xx-00

2

of

17 20Saturday, O ctober 08, 2005

1

5

DVI/VGA SCREWS

ASSY-SCREW1

SCREW

JACKSCREW

ASSY
7020000800

ASSY-SCREW3

SCREW

JACKSCREW

D D

ASSY
7020000800

C C

ASSY-SCREW2

SCREW

JACKSCREW

ASSY
7020000800

ASSY-SCREW4

SCREW

JACKSCREW

ASSY
7020000800

ASSY-SCREW5

SCREW

PAN_HEAD

7020001700

4

MT1
MT_Hole_0.136_in.

DNI DNI

DNI

SK1

RV410SOCKET
PCB1

RV410SOCKET

MT2
MT_Hole_0.136_in_6VI A

3

2

1

B B

A A

<Variant Name>

5

4

www.vinafix.vn

3

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docum e n t N u mb er Re v

C

Date: Sheet

105-A671xx-00

1

of

18 20Saturday, O ctober 08, 2005

2

<Variant

Name>

5

Title

4

3

2

1

Date:Schematic No.

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

REVISION HISTORY

D D

Sch
Rev

C C

PCB

Rev

0

00A

1 00B

200

Date

05/07/20

09/ 1 4/0 5 Added crossfire slave requirements

10/03 /05 Production Release

Design based o n A676-00B and memory of A675-00B
(pg 01) Delete redundant SMPS_EN circuits
(pg 03) Remove TMDS joins and add TMDS2 terminations
(pg 04) Add 1.8V option f or VDDR4 and VDDR5
(pg 05) Add additional separate MVREF, QS# and address; remove ODT for DDR2
(pg 07) Add DVO port and GPIO7 for ext TMDS reset
(pg 11) Change power sequence circuit for +5V and add 1.8V power supply
(pg 12) Add me mory based on A675-00B
(pg 13) Add ext TMDS HDCP support
(pg 14) Remove HPD2 option
(pg 15) Add 2nd DVI connector
(pg 16) Remove C3241, C3242, C3243, C3244 and C3245.
Remove +MVDDC/+MVDDQ reference, use only +MVDD

REVISION DESCRIPTION

105-A671xx-00

Saturday, October 08, 2005

Rev

2

B B

A A

5

4

www.vinafix.vn

3

2

1

5

4

3

2

1

MEMORY CHANNEL A

D D

DDR3 8M/16Mx32

MEM A

MEM B

Dual-Link LVTM

POWER
REGULATION

From +12V

VDDC, MVDD

From +12V LINEAR:

+5V, +5V_VESA,

C C

+5V_VESA2, RageTheater

From +12V DIRECT:

FAN

From +3.3V LINEAR:

VDDC_CT, MPVDD, PVDD,
TPVDD, T2PVDD, TXVDDR,
T2XVDDR, AVDD, A2VDD,
VDD1DI, VDD2DI,
PCIE, VDDR3, VDDR4,
VDDR5, VDDRH

MVDD

FAN

Straps

BIOS

Speed control
& temperature
sense

INTERRUPT

Temp. Sensing

GPIO

ROM

DDC3
GPIO17

D+/D-

RV5XX

GPIO14

DAC2

CRT

H/V2Sync

DDC2

TVO

XTALIN/OUT

MPP
VIP

DAC1

XTAL

CRT

H/VSync

DDC1

POWER DELIVERY

+PCIE_SOURCE

B B

+3.3V

3.3V_BUS
delayed circuit

+12V_BUS

Dual-Link TMDS

HPD1

PCI-Express

MEMORY CHANNEL B

DDR3 8M/16Mx32

TMDS matching

Oscillator

TMDS matching

External TMDS

RBG Filters

TVO Filters

XTALIN/OUT
CLKOUT

RageTheater

RBG Filters

HPD

TVO/VIVO

HPD

DVI-I

&

Slim-VGA

CONN

CONN

DVI-I

&

Slim-VGA

CONN

SMPS Enable
Circuit

+3.3V_BUS
+12V_BUS

PCI-Express Bus

RV5XX DDR3-136 FH 6-Layer

REV 0

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

RV530/RV515 256MB DDR3-136 Dual 2xDVI VIVO FH

Size Docum e n t N u mb er Re v

C

5

4

www.vinafix.vn

3

2

Date: Sheet

105-A671xx-00

1

2

of

20 20Saturday, O ctober 08, 2005