5
4
3
2
1
D D
V038-10
MEMORY CHANNEL A
DDRII Interface
MA[14..0]
CASA#
RASA#
CLOCK
C C
GPIO16 XTALIN XTALOUT ZV_LCDDATA18:19
STRAPS
BIOS
WEA#
ROMCS#
QSA[7..0]
CS0A#MDA[63..0]
DQMA[0..7]
CLKA01CKEA
CLKA01#
VGA
MEM A MEM B
Slim
DAC1
TMDS
R G B HSY VSY DDC1DATA DDC1CLK
TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
PRIMARY CRT
LOGIC
INTEG TMDS FILTERS
VGA
DVI-D
DVI-I
ROM
B B
POWER
REGULATION
VDDC VDDC_CT MVDDC MVDDQ VTT
PVDD TPVDD MPVDD
A2VDD Vref
RV280
DAC2
MUX
TVOUT
CONN
AGP
PAR
CBE3..0
GNT#
CLK
SBA[7..0]
AD_STB1#
CPUCLK
TRDY#
INTR
ST2..0
WBF#
AD_STB0
AD31..0
IRDY#
FRAME#
+5V_BUS+3.3V_BUS
+12V_BUS
+VDDQ_BUS
A A
AGPREF
AD_STB1
AGP B US
1X/2X/4X/8X
STOP#
DEVSEL#
DBI_HI
SB_STB
AD_STB0#
REQ#
RESET#
DBI_LO
SB_STB#
RBF#
MS-V038 ATI 9250
Size Document Number Rev
B
Date: Sheet of
5
4
www.vinafix.vn
3
2
Thursday, Sep t emb er 22, 2005
115
1
10
8
7
6
5
4
3
2
1
+VDDQ_BUS
AGP_ST1
AGP_SBA1
AGP_SBA3
AGP_SBA5
AGP_SBA7
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_C/BE#3
AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_C/BE#0
AGP_AD4
AGP_AD2
AGP_AD0
R91
1K
GND_RSETGND_R2SET
+VDDQ_BUS
1
C6
1uF / 0603
Biggest footprint
AGP_TYPEDET#
AGP_GC_8X_DET#
32
2N7002E
Q10
R92 147R
MAGP1
A1
12V
A2
TYPEDET#
A3
GC_DET#/RESERVED
A4
USB-
A5
GND
A6
INTA#
A7
RST#
A8
GNT#
A9
VCC3.3
A10
ST1
A11
MB_DET#/RESERVED
A12
DBI_HI/PIPE#
A13
GND#A13
A14
WBF#
A15
SBA1
A16
VCC3.3#A16
A17
SBA3
A18
SB_STB#
A19
GND#A19
A20
SBA5
A21
SBA7
A22
KEY
A23
KEY#A23
A24
KEY#A24
A25
KEY#A25
A26
AD30
A27
AD28
A28
VCC3.3#A28
A29
AD26
A30
AD24
A31
GND#A31
A32
AD_STB1#
A33
C/BE3#
A34
VDDQ
A35
AD22
A36
AD20
A37
GND#A37
A38
AD18
A39
AD16
A40
VDDQ#A40
A41
FRAME#
A42
KEY#A42
A43
KEY#A43
A44
KEY#A44
A45
KEY#A45
A46
TRDY#
A47
STOP#
A48
PME#
A49
GND#A49
A50
PAR
A51
AD15
A52
VDDQ#A52
A53
AD13
A54
AD11
A55
GND#A55
A56
AD9
A57
C/BE0#
A58
VDDQ#A58
A59
AD_STB0#
A60
AD6
A61
GND#A61
A62
AD4
A63
AD2
A64
VDDQ#A64
A65
AD0
A66
VREFGC
UNIVERSAL_AGP_BUS
R_AGP8X must be 1%
resistor to provide
350mV +/- 5% on Vref
R_AGP8X
R93
332R
R94
100R
+5V_BUS +3.3V_BUS
C2
C5
47uF_6.3V
>=6.3V
DNI
B1
OVRCNT#
B2
5.0V
B3
5.0V#B3
B4
USB+
B5
GND#B5
B6
INTB#
B7
CLK
B8
REQ#
B9
VCC3.3#B9
B10
ST0
B11
ST2
B12
RBF#
B13
GND#B13
SBA0
VCC3.3#B16
SBA2
SB_STB
GND#B19
SBA4
SBA6
KEY#B22
KEY#B23
KEY#B24
KEY#B25
AD31
AD29
VCC3.3#B28
AD27
AD25
GND#B31
AD_STB1
AD23
VDDQ#B34
AD21
AD19
GND#B37
AD17
C/BE2#
VDDQ#B40
IRDY#
KEY#B42
KEY#B43
KEY#B44
KEY#B45
DEVSEL#
VDDQ#B47
PERR#
GND#B49
SERR#
C/BE1#
VDDQ#B52
AD14
AD12
GND#B55
AD10
VDDQ#B58
AD_STB0
GND#B61
VDDQ#B64
VREFCG
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
AD8
B58
B59
B60
AD7
B61
B62
AD5
B63
AD3
B64
B65
AD1
B66
DBI_LO/RESERVED
AGP_VREFGC TEST
C19
10nF
C8
470uF_10V
AGP_ST0
AGP_ST2
AGP_SBA0
AGP_SBA2
AGP_SBA4
AGP_SBA6
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25
AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17
AGP_C/BE#2
AGP_C/BE#1
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
AGP_AD7AGP_AD6
AGP_AD5
AGP_AD3
AGP_AD1
AGP_AGPREF
22uF_10V
AGP_SBA[7..0]
AGP_ST[2..0]
AGP_C/BE#[3..0]
AGP_AD[31..0]
R86 0R
AGP_SBA[7..0] [3 ]
AGP_ST[2..0] [3]
AGP_C/BE#[3..0] [3]
AGP_AD[31..0] [3]
AGP_AGP/PCICLK [ 3 ]
AGP_REQ# [3]
AGP_RBF# [3]
AGP_DBI_LO [3]
AGP_SB_STB [3]
AGP_AD_STB1 [3]
AGP_IRDY# [3]
AGP_DEVSEL# [3]
AGP_AD_STB0 [3]
AGP_AGPREF
AGP_VREFGC
TEST
+VDDQ_BUS
32
1
R84 0R
R85 0R
+VDDQ_BUS
32
1
R88 137R
Q9
2N7002E
R89 75.0R
R_AGP8X must be 1%
resistor to provide
350mV +/- 5% on Vref
2N7002E
Q11
R95 147R
1%
1%
R_AGP8X
AGP_AGPTEST
Keep stubs short
R96
332R
R97
100R
C21
10nF
AGP_AGPTEST [3 ]
AGP_AGPREFCG [3 ]
GND_CHASSISGND_A2VSSNGND_A2VSSQGND_AVSSN
+12V_BUS
C10 place at the AGP connector
C10
D D
AGP_INTR#[3]
AGP_GNT#[3]
AGP_WBF#[3]
AGP_SB_STB#[3]
AGP_MB_8X_DET#[3]
AGP_DBI_HI[3]
AGP_RESET#[3]
C C
B B
A A
AGP_RESET#
180R
AGP_AD_STB1#[3]
AGP_FRAME#[3]
AGP_TRDY#[3]
AGP_STOP#[3]
AGP_PAR[3]
AGP_AD_STB0#[3]
AGP_MB_8X_DET#
10uF_20V
DNI
R83 0R
+5V_BUS
C11
100nF
X7R
3
AGP_TYPEDET#
AGP_GC_8X_DET#
+3.3V_BUS
R90
47K
R19
0R
R81
0R
147
13
12
U6D
SN74ACT86D
1
2
For retail, 1K ohm
pull-down causes
AMD system detects
AGP2X only
+12V, TYPEDET#
short protection
for OEM (1KR)
11
TEST
R3
100R
U6A
R4
SN74ACT86D
COMMON
UNIVERSAL VREFGC CIRCUIT (2X, 4X, 8X)
Size D o c u m ent Num ber Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
MS-V038 ATI 9250
Thursday, September 22, 2005
of
215
1
10
www.vinafix.vn
8
AGP_AD[31..0]
D D
AGP_C/BE#[3..0][2]
AGP_AGP/PCICLK[2]
C C
B B
AGP_SB_STB[2]
AGP_ST[2..0][2]
AGP_AGPREFCG[2]
AGP_AGPTEST[2]
AGP_C/BE#[3..0]
A_B/COMP_DAC2[12]
C20
100nF
2 1
A_R/C_DAC2[12]
A_G/Y_DAC2[12]
AGP_ST[2..0]
Y2
27_MHZ
R36 0R
AGP_SBA[7..0]
AGP_SB_STB#[2]
AGP_AD_STB0#[2]
AGP_AD_STB1#[2]
AGP_MB_8X_DET#[2]
AGP_DBI_HI[2]
AGP_DBI_LO[2]
OSC_IN
C1205 22pF
R1115
1M
C1206 22pF
AGP_RESET#[2]
AGP_REQ#[2]
AGP_GNT#[2]
AGP_PAR[2]
AGP_STOP#[2]
AGP_DEVSEL#[2]
AGP_TRDY#[2]
AGP_IRDY#[2]
AGP_FRAME#[2]
AGP_INTR#[2]
AGP_WBF#[2]
AGP_RBF#[2]
AGP_AD_STB0[2]
AGP_AD_STB1[2]
AGP_SBA[7..0][2]
A_HSYNC_DAC2[13]
A_VSYNC_DAC2[13]
AGP_ST0
AGP_ST1
AGP_ST2
GND_R2SET
+3.3V_BUS
7
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
R40 715R
R1198 4.7K DNI
R1199 4.7K DNI
6
U1A
K27
AD0
L26
AD1
L25
AD2
L27
AD3
M25
AD4
M26
AD5
N26
AD6
N25
AD7
R26
AD8
R25
AD9
T26
AD10
T25
AD11
U26
AD12
U25
AD13
U27
AD14
V26
AD15
M28
AD16
N29
AD17
N28
AD18
P29
AD19
P28
AD20
R29
AD21
R28
AD22
T28
AD23
V29
AD24
V28
AD25
W29
AD26
W28
AD27
Y29
AD28
Y28
AD29
AA29
AD30
AA28
AD31
P27
C/BEb0
V25
C/BEb1
M29
C/BEb2
T29
C/BEb3
AF29
PCICLK
AG30
RSTb
AE29
REQb
AG28
GNTb
J29
PAR
J28
STOPb
K29
DEVSELb
K28
TRDYb
L29
IRDYb
L28
FRAMEb
AF28
INTAb
AF27
WBFb
AJ26
NC19
AH25
NC18
AC29
RBFb
P25
AD_STBF0
U29
AD_STBF1
AB26
SB_STBF
AE27
SBA0
AD26
SBA1
AC25
SBA2
AC26
SBA3
AA25
SBA4
AA26
SBA5
Y25
SBA6
Y26
SBA7/IDSEL
AD28
ST0
AD29
ST1
AC28
ST2
AB25
SB_STBS
P26
AD_STBS0
U28
AD_STBS1
H29
AGPREF
H28
AGPTEST
AG27
AGP8X_DETb
AB28
DBI_HI
AB29
DBI_LO
AJ21
R2SET
AJ22
C_R
AK22
Y_G
AK21
COMP_B
AG25
H2SYNC
AF25
V2SYNC
AF23
CRT2DDCCLK
AG24
CRT2DDCDAT
AG29
NC34
AH29
NC33
AJ28
XTALIN
AJ29
AH26
AJ27
XTALOUT
TESTEN
STEREOSYNC
RV280
STEREOSYNC
TESTEN
R33
1K
Part 1 of 5
EXT TMDS / GPIO / ROM
PCI/AGPAGP2XCLK
NCSTMDSDAC1
AGP4X/8X
SSC DAC2
STEREOSYNC [8]
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
ROMCSb
DVOMODE
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
NC35
NC27
NC36
NC28
NC37
NC29
NC39
NC31
NC38
NC30
NC22
NC13
NC23
NC14
NC24
NC15
NC26
NC17
NC25
NC16
DPLUS
DMINUS
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DVIDDCCLK
DVIDDCDATA
HSYNC
VSYNC
RSET
VGADDCDATA
VGADDCCLK
AUXWIN
AJ5
AK4
AJ4
AF4
AG4
AH4
AK3
AJ3
AH3
AG3
AF3
AJ2
AH2
AG2
AF2
AH1
AG1
AH5
AE10
AF5
AE6
AF6
AE7
AG6
AF7
AG8
AF8
AE8
AE9
AF9
AG9
VID/DVO12
AK7
VID/DVO13
AJ7
VID/DVO14
AH8
VID/DVO15
AJ8
AH9
AJ9
AK9
AH10
AK10
AJ10
AH11
AJ11
AK6
AJ6
AH6
AH7
AE15
AF15
AE16
AF16
AG15
AH15
AH16
AH17
AF17
AG17
AJ17
AH18
AK18
AJ18
AG19
AH19
AJ16
AK16
AH20
AJ20
AF11
NC7
AE12
NC8
AF10
AE11
AJ13
AH13
AJ14
AH14
AJ15
AK15
AK12
AK13
AF13
AE13
AF12
HPD
AK25
R
AJ25
G
AK24
B
AH28
AH27
R39 499R
AJ23
AG26
AF26
AUXWIN
AE25
GND_RSET
5
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
ROMCS#
DVOMODE
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VSYNC
VGADDCDATA
VGADDCCLK
R63 4.7K
GPIO[13..0]
R986
10K
24bit-SDR-DVO
DC_Strap1 [8]
DC_Strap2 [8]
DC_Strap3 [8]
DC_Strap4 [8]
TMDS_TX0N [13]
TMDS_TX0P [13]
TMDS_TX1N [13]
TMDS_TX1P [13]
TMDS_TX2N [13]
TMDS_TX2P [13]
TMDS_TXCN [13]
TMDS_TXCP [13]
DVIDDCCLK [13]
DVIDDCDATA [13]
HPD [13]
+3.3V_BUS
4
GPIO[13..0] [8]AGP_AD[31..0][2]
Mem_Strap2 [8]
Mem_Strap1 [8]
Mem_Strap0 [8]
A_R_DAC1 [11]
A_G_DAC1 [11]
A_B_DAC1 [11]
A_HSYNC_DAC1 [11 ]
A_VSYNC_DAC1 [11]
CRT1DDCDATA [11]
CRT1DDCCLK [11]
RSET
R2SET
3
THE VALUES OF R SET AND R2SET SHOW N IN THE TABLE MAY BE
APPROXIMATE VALUES ONLY (SUITABLE FOR PROTOTYPING)
BEFORE GOING INTO PRODUCTION,CONTACT YOUR ATI
499R
REPRESENTATIVE FOR THE RSET/R2SET VALUES QUALIFIED FOR
MASS PRODUCTION
715R
LCDDATA16 [ 8 ]
LCDDATA17 [ 8 ]
PAL/NTSC [8]
DC_Strap5 [8,12]
LCDDATA20 [ 8 ]
SERIAL EEPROM BIOS
+3.3V_BUS
R21
GPIO9
GPIO10
ROMCS#
10K
+3.3V_BUS
C80
100nF
X7R
2
U11
5
D
6
C
1
S
7
HOLD
3
W
8
VCC
M25P05-VMN6T
1
2
Q
4
VSS
GPIO8
Drop-in without strap change
A A
8
7
6
5
4
3
Pm25LV512-25SC P/N2280002900
Size D o c u m ent Num ber Rev
Custom
Date: Sheet
2
MS-V038 ATI 9250
Thursday, September 22, 2005
of
315
1
10
www.vinafix.vn
5
D D
4
3
2
1
MEMORY CHANNEL A
QSA[7..0][10]
DQMA#[7..0][10]
MAA[14..0][10]
MDA[63..0][10]
C C
B B
A A
QSA[7..0]
DQMA#[7..0]
MAA[14..0]
MDA[63..0]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
U1B
G29
DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63
Part 2 of 5
ELPIDA
DQMAb0
DQMAb1
DQMAb2
DQMAb3
DQMAb4
DQMAb5
DQMAb6
DQMAb7
MEMORY INTERFACE A
CLKA0b
CLKA1b
CLKAFB
G30
F28
F30
E29
D28
D29
D30
K25
K26
J25
J26
G28
G25
G26
G27
C29
B29
B28
C27
C26
B26
C25
B25
E26
F25
E25
F24
E23
D22
F22
E22
C17
B17
C16
B16
C14
B14
C13
B13
E18
F17
E17
D16
F15
E15
F14
E14
A13
C12
A12
B12
C10
B10
C9
B9
E13
F12
E12
F11
E10
F9
E9
F8
RV280
AA10
AA11
AA12
AA13
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASAb
CASAb
WEAb
CSAb0
CSAb1
CKEA
CLKA0
CLKA1
VREF
DIMA0
DIMA1
MAA0
B24
AA0
MAA1
A24
AA1
MAA2
B23
AA2
MAA3
C23
AA3
MAA4
B21
AA4
MAA5
F21
AA5
MAA6
E21
AA6
MAA7
F20
AA7
MAA8
E20
AA8
MAA9
C21
AA9
MAA10
B22
MAA11
C22
MAA12
A25
MAA13
C24
DQMA#0
E28
DQMA#1
H26
DQMA#2
A27
DQMA#3
E24
DQMA#4
B15
DQMA#5
E16
DQMA#6
C11
DQMA#7
E11
QSA0
F29
QSA1
H25
QSA2
B27
QSA3
F23
QSA4
C15
QSA5
F16
QSA6
B11
QSA7
F10
RASA#
A19
CASA#
C18
WEA#
F18
CSA#0
E19
F19
CKEA
B19
CLKA0
C20
CLKA#0
B20
CLKA1
B18
CLKA#1
A18
C19
+VREF
B8
F26
F13
RASA# [10 ]
CASA# [10 ]
WEA# [10]
CSA#0 [10]
MAA14
CKEA [9,10]
CLKA0 [9,10]
CLKA#0 [9,10]
CLKA1 [9,10]
CLKA#1 [9,10]
Vref Voltage
+MVDDQ
R265
Re6
499R
+VREF
R268
Re7
499R
Place close to ASIC ball
Use localized Vref on the memory page
MEMORY CHANNEL B
U1C
B6
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63
Part 3 of 5
ELPIDA
MEMORY INTERFACE B
DQMBb0
DQMBb1
DQMBb2
DQMBb3
DQMBb4
DQMBb5
DQMBb6
DQMBb7
MEMVMODE
MEMVMODE1
MEMTEST
C6
B5
C5
B2
C3
C2
D2
E8
E7
D4
D3
F6
F3
F5
G6
D1
E2
F2
F1
G2
H3
H2
J3
G4
H6
H5
J6
K5
K4
L6
L5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA3
AB2
AB3
AC2
AD1
AD3
AE1
AE2
U6
U5
U3
V6
W5
W4
Y6
Y5
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
RV280
AB10
AB11
AB12
AB13
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASBb
CASBb
WEBb
CSBb0
CSBb1
CKEB
CLKB0
CLKB0b
CLKB1
CLKB1b
CLKBFB
DIMB0
DIMB1
J2
AB0
K3
AB1
K2
AB2
L3
AB3
L2
AB4
M3
AB5
M2
AB6
N5
AB7
M1
AB8
M5
AB9
N3
P2
P6
P5
A4
E3
G3
J5
W2
AC3
W6
AC6
B4
E5
G1
K6
W1
AD2
V5
AC5
R2
T5
T6
R5
R6
R3
N1
N2
T2
T3
P3
DNI
2.5V (DDR)
1.8V (DDR)
3.3V (SDR)
+VDDC_CT
Default
B7
C7
G5
AE3
C8
R55
47R
R51 4.7K
R52 4.7K
R54
R53
4.7K
4.7K
DNI
MEMVMODE[1:0] MEMORY IO VOLTAGE
0 1
1 0
1 1
Size D o c u m ent Num ber Rev
Custom
5
4
3
2
Date: Sheet
MS-V038 ATI 9250
Thursday, September 22, 2005
1
415
10
of
www.vinafix.vn
5
U1D
P18
VDDC#P18
P19
VDDC#P19
U12
VDDC#U12
U13
VDDC#U13
U14
VDDC#U14
U17
VDDC#U17
U18
+VDDC_CT
VDDC#U18
U19
VDDC#U19
V12
VDDC#V12
V13
VDDC#V13
V14
VDDC#V14
V17
VDDC#V17
V18
VDDC#V18
V19
VDDC#V19
W12
VDDC#W12
W13
VDDC#W13
W14
VDDC#W14
W17
VDDC#W17
W18
VDDC#W18
W19
VDDC#W19
H10
VDDR1#H10
H13
VDDR1#H13
H15
VDDR1#H15
H17
VDDR1#H17
H19
VDDR1#H19
H22
VDDR1#H22
J1
VDDR1#J1
J23
VDDR1#J23
J24
VDDR1#J24
J27
VDDR1#J27
J4
VDDR1#J4
J7
VDDR1#J7
J8
VDDR1#J8
L8
VDDR1#L8
M4
VDDR1#M4
N4
VDDR1#N4
N7
VDDR1#N7
N8
VDDR1#N8
R1
VDDR1#R1
R4
VDDR1#R4
T4
VDDR1#T4
T7
VDDR1#T7
T8
VDDR1#T8
E27
VDDR1#E27
F4
VDDR1#F4
G10
VDDR1#G10
G13
VDDR1#G13
G15
VDDR1#G15
G22
VDDR1#G22
G7
VDDR1#G7
Y23
VDDC18
L23
VDDC18#L23
H20
VDDC18#H20
H11
VDDC18#H11
P8
VDDC18#P8
Y8
VDDC18#Y8
AC11
VDDC18#AC11
AC20
VDDC18#AC20
AK19
NC
AE19
VDDC18#AE19
AE20
VDDC18#AE20
AF20
NC#AF20
AG20
NC#AG20
AJ19
NC#AJ19
AF18
NC#AF18
AF19
NC#AF19
AE18
NC#AE18
AE17
NC#AE17
AJ12
TPVDD
AH12
TPVSS
AF14
TXVDDR
AE14
TXVDDR#AE14
AG14
TXVSSR
AG13
TXVSSR#AG13
AG12
TXVSSR#AG12
AF21
A2VDD
AF22
A2VDD#AF22
AH21
A2VDDQ
AF24
AVDD
AE23
AVDD#AE23
AE21
A2VSSN
AE22
A2VSSN#AE22
AG22
A2VSSDI
AH22
A2VSSQ
RV280
GND_A2VSSQ
+A2VDD
Matching
Ground
2.5V
AVSSN
(Noisy)
AVSSQ
DAC2 VDD
(1) A2VDD regulated source
and A2VSSN return path routed
with at least 15 mil trace and
not longer than 1.5 inch.
AVSSN with single via to GND
at the regulator.
(2) Sourced from VDD thru bead
instead of the regulator
D D
+MVDDQ
C C
C56
100nF
X7R
+TPVDD
C57
C58
4.7uF
>=6.3V
Ceramic
+A2VDDQ
GND_A2VSSQ
100nF
X7R
C60
C64
100nF
X7R
Board power
and ground
option(s)
C59
4.7uF
DNI
>=6.3V
Ceramic
Pin Names
Voltage
Usage
C77
100pF
100nF
X7R
X7R
DNI
DNI
+AVDD
C68
C67
100nF
4.7uF
X7R
GND_AVSSN
GND_A2VSSN
+AVDD
1.8V
DAC1 VDD A2VSSQ
(80mA)
DAC1 Band Gap Ref.
AVDD sourc ed fr om VDDC_CT
thru bead at least 15 mil trace
and not longer than 1.5 inch.
AVSSN and AVSSQ with single
via to GND close to the pin.
>=6.3V
+VDDC_CT
C62
100nF
X7R
GND_A2VSSN
Ceramic
0R on B16
B16 200R
C61
4.7uF
C63
4.7uF
>=6.3V
Ceramic
5
B B
+A2VDD
L2
1.8uH
A A
4
Part 4 of 5
Memory I/O Power
(1.8V/2.5V/3.3V)
I/O POWER
I/O level shift power
(1.8V)
Ext. TMDS/
DVO Power
GPIO & Ext.
TMDS I/O Power
(1.8V)
TMDS PLL TMDS I/O
(1.8V)
Analog Display Power,
see table below
Matching
Ground
A2VSSN
(Noisy)
(120mA)
4
VDDC
VDDC#AC15
VDDC#AC17
VDDC#AD13
VDDC#AD15
VDDC#M12
VDDC#M13
VDDC#M14
VDDC#M17
VDDC#M18
VDDC#M19
VDDC#N12
VDDC#N13
VDDC#N14
VDDC#N17
VDDC#N18
VDDC#N19
VDDC#P12
VDDC#P13
VDDC#P14
VDDC#P17
VDDR1
VDDR1#A21
VDDR1#AA7
VDDR1#AA8
VDDR1#D11
VDDR1#D14
VDDR1#D17
VDDR1#D8
VDDR1#V4
VDDR1#A28
VDDR1#A3
VDDR1#A9
VDDR1#AA1
VDDR1#AA4
VDDR1#AD4
VDDR1#B1
VDDR1#B30
VDDR1#D10
VDDR1#D19
VDDR1#D20
VDDR1#D23
VDDR1#D26
VDDR1#D6
VDDR1#V7
VDDR1#V8
VDDRH0
VDDRH1
VSSRH0
VSSRH1
VDDRH0 - CH A Clock Power
VDDRH1 - CH B Clock PowerAGP Bus I/O Power
(VDDR1)
MPVDD
MPVSS
PVDD
PVSS
PLL MPLL
VDDR4
VDDR4#AC9
VDDR4#AD10
VDDR4#AD9
VDDR4#AG10
(1.8V/3.3V)
VDDR3
VDDR3#AC22
VDDR3#AC21
VDDR3#AD21
VDDR3#AC19
VDDR3#AD19
VDDR3#AD7
VDDR3#AC8
(3.3V)
VDDP
VDDP#AA24
VDDP#AB27
VDDP#AB30
VDDP#AC23
VDDP#AD27
VDDP#AE30
VDDP#AH30
VDDP#J30
VDDP#M23
VDDP#M24
VDDP#N27
VDDP#N30
VDDP#P23
VDDP#T23
VDDP#T24
(1.5V/3.3V) (1.8V) (1.8V)
VDDP#T27
VDDP#T30
VDDP#V23
VDDP#V24
VDDP#W27
VDDP#W30
VDDP#Y27
AVDDDI
A2VDDDI
AVSSQ
AVSSDI
AVSSN#AD24
AVSSN
+A2VDDQ
1.8V
DAC2 Band Gap Ref.
Source from AVDD thru bead.
A2VSSQ with sigle via to GND
close to the pin.
AC13
AC15
AC17
AD13
AD15
M12
M13
M14
M17
M18
M19
N12
N13
N14
N17
N18
N19
P12
P13
P14
P17
A15
A21
AA7
AA8
D11
D14
D17
D8
V4
A28
A3
A9
AA1
AA4
AD4
B1
B30
D10
D19
D20
D23
D26
D6
V7
V8
G19
N6
G18
M6
A7
A6
AK27
AK28
AC10
AC9
AD10
AD9
AG10
AD22
AC22
AC21
AD21
AC19
AD19
AD7
AC8
AA23
AA24
AB27
AB30
AC23
AD27
AE30
AH30
J30
M23
M24
N27
N30
P23
T23
T24
T27
T30
V23
V24
W27
W30
Y27
AH24
AH23
AJ24
AG23
AD24
AE24
+VDDC
+MVDDQ
+3.3V_BUS
GND_AVSSN
Matching
Ground
(Quiet)
C51
100nF
X7R
C53
100nF
X7R
+VDDQ_BUS
C65
100nF
X7R
+AVDDDI
+A2VDDDI
1.8V
Digital Power for
DAC1 and DAC2
Source fro m VDDC_CT
thru bead
+VDDC
CP9A
8 1
10nF
B17 200R
C66
4.7uF
>=6.3V
Ceramic
CP9B
7 2
10nF
+MPVDD
+PVDD
Matching
Ground
AVSSDI
A2VSSDI
(Digital)(Quiet)
CP9C
6 3
10nF
C52
4.7uF
>=6.3V
Ceramic
C54
4.7uF
>=6.3V
Ceramic
+VDDC_CT
3
CP3A
CP9D
CP3B
8 1
5 4
7 2
10nF
10nF
10nF
+VDDC
+3.3V_BUS
+MVDDQ +MVDDQ
+MVDDQ
+VDDC_CT
CP4A
CP3C
CP3D
CP4B
8 1
6 3
5 4
7 2
10nF
10nF
10nF
10nF
C26
100nF
X7R X7R X7R X7R X7R
CP1A
8 1
10nF
CP5A
8 1
10nF
C32
100nF
X7R X7R X7R X7R
CP1C
6 3
10nF
C45
100nF
X7R
C28
C27
100nF
100nF
C44
100nF
CP1B
7 2
10nF
CP5B
CP5C
CP5D
7 2
6 3
5 4
10nF
10nF
10nF
C34
C33
100nF
100nF
C83
CP1D
100nF
5 4
10nF
X7R
C46
C47
100nF
100nF
X7R X7R X7R X7R
Distributed around
+VDDQ_BUS plane
3
C48
100nF
CP4C
6 3
10nF
C29
100nF
CP6A
8 1
10nF
C35
100nF
CP4D
5 4
10nF
CP6B
7 2
10nF
C49
100nF
C30
100nF
CP6C
6 3
10nF
CP2A
8 1
10nF
CP2B
CP2C
7 2
6 3
10nF
10nF
C38
CP6D
10uf
5 4
10nF
PLACE DIRECTLY
UNDERNEATH CHANNEL
A & B SECTION OF ASIC.
+3.3V_BUS
D30
2.4V
2 1
CP2D
5 4
10nF
C39
10uf
+VDDQ_BUS+VDDQ_BUS
CP8A
8 1
10nF
2
+VDDC
C23
10uf
At the corner of VDDC plane
CP8B
CP8C
7 2
6 3
10nF
10nF
2
CP8D
5 4
10nF
1
U1E
F27
VSS#F27
F7
G12
G16
G21
G24
G9
H12
H14
H16
H18
H21
H23
H27
H4
H8
H9
K1
K23
K24
K30
K7
K8
L4
M15
M16
M27
M30
M7
M8
N15
N16
N23
N24
P15
P16
P4
R12
R13
R14
R15
R16
R17
R18
R19
R23
R24
R27
R30
R7
R8
T1
T12
T13
T14
T15
T16
T17
T18
T19
W23
W24
W25
W26
W7
W8
Y4
RV280
Part 5 of 5
VSS#F7
VSS#G12
VSS#G16
VSS#G21
VSS#G24
VSS#G9
VSS#H12
VSS#H14
VSS#H16
VSS#H18
VSS#H21
VSS#H23
VSS#H27
VSS#H4
VSS#H8
VSS#H9
VSS#K1
VSS#K23
VSS#K24
VSS#K30
VSS#K7
VSS#K8
VSS#L4
VSS#M15
VSS#M16
VSS#M27
VSS#M30
VSS#M7
VSS#M8
VSS#N15
VSS#N16
VSS#N23
VSS#N24
VSS#P15
VSS#P16
VSS#P4
VSS#R12
VSS#R13
VSS#R14
VSS#R15
VSS#R16
VSS#R17
VSS#R18
VSS#R19
VSS#R23
VSS#R24
VSS#R27
VSS#R30
VSS#R7
VSS#R8
VSS#T1
VSS#T12
VSS#T13
VSS#T14
VSS#T15
VSS#T16
VSS#T17
VSS#T18
VSS#T19
VSS#W23
VSS#W24
VSS#W25
VSS#W26
VSS#W7
VSS#W8
VSS#Y4
CORE GND
Size D o c u m ent Num ber Rev
Custom
Thursday, September 22, 2005
Date: Sheet
U15
VSS#U15
U16
VSS#U16
U23
VSS#U23
U4
VSS#U4
U8
VSS#U8
V15
VSS#V15
A10
VSS
A16
VSS#A16
A2
VSS#A2
A22
VSS#A22
A29
VSS#A29
AA27
VSS#AA27
AA30
VSS#AA30
AB1
VSS#AB1
AB23
VSS#AB23
AB24
VSS#AB24
AB4
VSS#AB4
AB7
VSS#AB7
AB8
VSS#AB8
AC12
VSS#AC12
AC14
VSS#AC14
AC16
VSS#AC16
AC18
VSS#AC18
AC27
VSS#AC27
AC4
VSS#AC4
AD12
VSS#AD12
AD16
VSS#AD16
AD18
VSS#AD18
AD25
VSS#AD25
AD30
VSS#AD30
AE26
VSS#AE26
AE28
VSS#AE28
AG11
VSS#AG11
AG16
VSS#AG16
AG18
VSS#AG18
AG21
VSS#AG21
AG5
VSS#AG5
AG7
VSS#AG7
AJ1
VSS#AJ1
AJ30
VSS#AJ30
AK2
VSS#AK2
AK29
VSS#AK29
B3
VSS#B3
C1
VSS#C1
C28
VSS#C28
C30
VSS#C30
C4
VSS#C4
D12
VSS#D12
D13
VSS#D13
D15
VSS#D15
D18
VSS#D18
D21
VSS#D21
D24
VSS#D24
D25
VSS#D25
D27
VSS#D27
D5
VSS#D5
D7
VSS#D7
D9
VSS#D9
E4
VSS#E4
E6
VSS#E6
V16
VSS#V16
V27
VSS#V27
V30
VSS#V30
W15
VSS#W15
W16
VSS#W16
MS-V038 ATI 9250
1
10
of
515
www.vinafix.vn
8
+12V_BUS
R1593
2R2
1
D20
BAT54SLT1
3
2
D D
C3
0.1uF
R1592
2R2
MU31
1
BOOT
PHASE
2
UGATE
3
GND
LGATE4VCC
APW7120
R1618
2R2
+12V_BUS
CORE REGULATOR VDDC
APW7120 Application Circuit
R1594
0R
8
7
OPS
6
FB
5
C143
0.1uF
R500
19K
R501
1.2K
7
DS
Q23
N-APM2512N TO-252
(TO-252)
G
G
C1688
100nF
DS
Q21
(TO-252)
N-APM2512N TO-252
R1686
1.2K
R502
200RF
L100
Dip 1.6uH
C1532
1.0uF
6
C117
C116
10uF
10uF
C1149
10uF
C1146
10uF
C616
470UF
C1323
820uF_6.3V
+VDDC
C1321
820uF_6.3V
5
+3.3V_BUS
B18
Chock 1.2u
4
3
2
1
+VDDC=1.6V
C C
B B
VDDC=0.8 * [ 1+ ( R1686 / R501 )]
A A
Size D o c u m ent Num ber Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
MS-V038 ATI 9250
Thursday, September 22, 2005
of
615
1
10
www.vinafix.vn
8
7
6
5
4
3
2
1
+3.3V_BUS
R124
15R
C109
10uF_6.3V
EREG9
D D
APL431BAC_SOT23
2
3 1
DNI
R812
100R
1%
R813
100R
1%
2.5V_REF1
R1
1.25V_REF2
R2
1.25V_REF2
R101 1K
402
R103
2.15K
Rx2
1.25V_REF2
C C
Alt. regulator for +1.8V
Vout = 1.8V
Iout = 500mA MAX
2.5V_REF1
R109 1K
402
R111
1K
R105 1.00K
5
6
+12V_BUS
411
U81A
3
+
2
-
LM324M
R102 432R
U81B
+
-
LM324M
R110 619R
10
9
R107
3.32K
Place caps very
close to power pin
603
X7R
5%
R130
1
Rx1
7
U81C
+
-
LM324M
C12
100nF
603
X7R
5%
0R
CMPT3904: 40V 200mA
MMBT2222: 40V 600mA
R131
0R
R127 120R
8
R106 0R
+3.3V_BUS
Q31
1
MMBT2222ALT1
2 3
N-APM3023N_TO252
+3.3V_BUS
1
2 3
+3.3V_BUS
DS
Q33
G
Q103
MMBT2222ALT1
+1.8V
C123
10uf
L9
0ohm
G
+VDDC_CT
DS
Q34
N-APM3023N_TO252
ALT
C316
10uF
+A2VDD
C124
100nF
C302
10uF_6.3V
ALT
C315
10uF
C9
10uF / 10V
C314
10uF
1.8V
150mA MAX
C13
10uF / 10V
+MVDDC
C401
470uF_10V
2.0V
C339
10uf
C1
10uF/10V
C340
10uf
+MVDDQ +MVDDC
B B
CASE
+1.8V
2
4
R296
C308
1.50K
10uF_6.3V
1%
+MPVDD
402
+1.8V
+AVDD +A2VDDQ
L8
1.8uH
+PVDD +TPVDD
L11
1.8uH
L6
1.8uH
L3
1.8uH
L12
1.8uH
+3.3V_BUS
C4
10u / 1206
MREG36
LT1117CST
IN3OUT
ADJ
1
R295
681R
1%
I31-0111719-A35
I31-0111719-N03
I31-0111719-A30
A A
8
7
6
C400
10uF_6.3V
+MPVDD: 10mA MAX
+PVDD: 25mA MAX
5
+TPVDD: 50mA MAX
Size D o c u m ent Num ber Rev
Custom
4
3
Date: Sheet
2
MS-V038 ATI 9250
Thursday, September 22, 2005
of
715
1
10
www.vinafix.vn
8
GPIO[13..0]
GPIO[13..0][3]
D D
C C
LCDDATA16[3]
LCDDATA17[3]
LCDDATA20[3]
STEREOSYNC[3]
Mem_Strap0[3]
Mem_Strap1[3]
Mem_Strap2[3]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO11
GPIO12
GPIO13
GPIO9
GPIO8
GPIO4
GPIO5
GPIO6
GPIO7
7
STRAP G
STRAP H
STRAP J
STRAP K
STRAP L
STRAP M
STRAP N
STRAP O
STRAP A
STRAP D
STRAP E
STRAP F
STRAP B
STRAP R
STRAP S
STRAP T
STRAP P
R201 10K DNI
R202 10K
R203 10K DNI
R204 10K
R205 10K DNI
R206 10K
R207 10K DNI
R208 10K
R209 10K
R210 10K
R211 10K
R212 10K COMMON
R213 10K COMMON
R214 10K
R215 10K
R216 10K DNI
R217 10K DNI
R218 10K
R219 10K DNI
R220 10K
R221 10K DNI
R222 10K
R223 10K DNI
R224 10K
R225 10K DNI
R226 10K
R227 10K DNI
R228 10K COMMON
R229 10K COMMON
R230 10K DNI
R231 10K
R232 10K DNI
R233 10K DNI
R234 10K
R235 10K DNI
R236 10K
R237 10K DNI
R238 10K
R239 10K DNI
R240 10K
DNI
DNI
DNI
6
+3.3V_BUS
STRAPS
AGPFBSKEW(1:0)
X1CLK_SKWE(1:0)
ROMIDCFG(3:0)
ID_DISABLE
BUSCFG(2:0)
VGA_DISABLE
MULTIFUNC(1:0)
VIP_DEVICE
STRAP P
LOW
HIGH
PIN
GPIO(1:0)
GPIO(3:2)
GPIO(9,13:11)
GPIO(8)
GPIO(6:4)
GPIO(7)
LCDDATA(17:16)
LCDDATA(20)
STRAP T
INTERRUPT
ENABLED (DEFAULT)
DISABLED
5
4
OPTION STRAPS
DESCRIPTION
AGP 1x clock feedback phase adjustment wrt refclk(cpuclk)
00 - refclk slightly earlier then feedback
01 - refclk 1 tap earlier then feedback
10 - refclk 1 t ap later then feedback
11 - refclk 2 t aps earlier then feedback clock
Clock phase adjustment between x1 clk and x2clk
00 - 0 tap delay
01 - 1 tap delay
10 - 2 taps delay
11 - 3 taps delay
If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type
0000 - No ROM, CHG_ID=0
0001 - No ROM, CHG_ID=1
0100 - reserved
0110 - reserved
1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P05/10 ROM (ST), chip IDis from ROM
1100 - Reserved
1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM
0 - Normal operation
1 - Shuts the chip down by not responding to any config cycles
In a system w i th two graphics chips, one on the motherboard,
the other on add-in card, the strap can be used to disable one of the two throught a jumper.
Controls bus type , CL K PL L select, and IDSEL
000 - 1.5V BUS -> AGP 4x, PLL clk, IDSEL=AD16
000 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
001 - 1.5V BUS -> AGP 4x, PLL clk, IDSEL=AD17
001 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
010 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
010 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
011 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
011 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
100 - PCI 66MHz, PLL clk
101 - PCI 33MHz, 3.3v, REF clk
110 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD16
110 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD16
111 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD17
111 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD17
Note that for AGP configurations GPIO(4) acts as the IDSEL strap.
For PCI it acts as the PLL bypass (33 or 66MHz) strap.
0 - VGA controller capabillity enabled.
1 - The device will not be recognized as the systemis VGA controller.
Multi-function device select
00 - single function device.
01 - two function device. No AGP in either function
10 - two function device. AGP only in function 0
11 - two function device. AGP in both functions
If BUSCFG pin bas ed s tra ps ar e s et t o P CI, t he n AGP will not be enabled in any function.
See AGP func t io n table below for detail on AGP ability claims.
Indicates if any slave VIP host devices drove this in low during reset.
0 - Slave VIP hos t po rt devices present
1 - No slave VIP ho s t port devices reporting presence during reset
3
DEFAULT
00
(internal pull-down)
00
(internal pull-down)
1100
0
(internal pull-down)
000
(internal pull-down)
0
10
0
2
1
B B
STRAPS
DC_STRAP1 LCDDATA12
Daughter Card Straps
DC_Strap2 [3]
+3.3V_BUS
PAL/NTSC [3]
6
+3.3V_BUS
R582 10K
R578 10K R580 10K
R574 10K
DC_Strap5[3,12]
DC_Strap3[3] DC_Strap4 [3]
DC_Strap1[3]
A A
R575 10K
R579 10K
R583 10K
8
R584 10K
R576 10K
R577 10K
R581 10K
R585 10K
7
DC_STRAP2 LCDDATA13
DC_STRAP4 LCDDATA15 DAC2 ConfigurationDC_STRAP5 LCDDATA19
DC_STRAP6 LCDDATA18 TVO Standard Default (Resistor pull-up and switch short to GND)
5
PIN
00
01
1
11
0
4
DESCRIPTION
Internal TMDS Enabled
0 - Disabled
1 - Enabled
Video Capture Enabled
0 - Disabled
1 - Enabled
DAC2 Off
DAC2 On as CRT
DAC2 On as TVOUT
DAC2 On as TVOUT and CRT
0 - PAL (on board resistor pull-down and switch closed)
1 -NTSC (on board resistor pull-up)
3
Size D o c u m ent Num ber Rev
Custom
Date: Sheet
2
MS-V038 ATI 9250
Thursday, September 22, 2005
of
815
1
10
www.vinafix.vn
5
4
3
2
1
CLKA#0[4,10]
CLKA0[4,10]
CLKA#1[4,10]
CLKA1[4,10]
CKEA[4,10]
R243
10K
R250 56R
R251 56R
R252 56R
R253 56R
C300
10nF
C301
10nF
D D
C C
B B
A A
Size D o c u m ent Num ber Rev
Custom
5
4
3
2
Date: Sheet
MS-V038 ATI 9250
Thursday, September 22, 2005
1
915
10
of
www.vinafix.vn
8
DQMA#[7..0]
DQMA#[7..0][4]
D D
MDA[63..0][4]
MAA[14..0][4]
C C
MDA[63..0]
MAA[14..0]
VREF_A0
+MVDDQ
R300
4.99K
R301
4.99K
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
CLKA#0[4,9]
CLKA0[4,9]
CKEA[4,9]
CSA#0[4]
WEA#[4]
RASA#[4]
CASA#[4]
QSA[7..0][4]
MAA12
MAA13
MAA14
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
DQMA#0
DQMA#1
ODTA0
QSA0 QSA2 QSA6
R320 10R
QSA1 QSA5
R321 10R
VREF_U20
C281
100nF
U20
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HY5PS561621F-25
7
QSA[7..0]
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
6
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
QSA3
U21
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HY5PS561621F-25
MDA11
B9
MDA15
B1
MDA12
D9
MDA14
D1
MDA13
D3
MDA8
D7
MDA10
C2
DQ9
MDA9
C8
DQ8
MDA3
F9
DQ7
MDA4
F1
DQ6
MDA0
H9
DQ5
MDA7
H1
DQ4
MDA6
H3
DQ3
MDA1
H7
DQ2
MDA5
G2
DQ1
MDA2
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
B300
220R
C200
100nF
+MVDDQ
B308
220R
DNI
C206
1uF
+MVDDC
VREF_A0
+MVDDQ
R322 10R
R323 10R
R302
4.99K
VREF_U21
R303
4.99K
C282
100nF
MAA12
MAA13
MAA14
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
CLKA#0
CLKA0
CKEA
CSA#0
WEA#
CASA#
DQMA#3
ODTA0
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
5
MDA27
B9
MDA26
B1
MDA29
D9
MDA25
D1
MDA24
D3
MDA28
D7
MDA31
C2
DQ9
MDA30
C8
DQ8
MDA20
F9
DQ7
MDA19
F1
DQ6
MDA23
H9
DQ5
MDA16
H1
DQ4
MDA17
H3
DQ3
MDA22
H7
DQ2
MDA18
G2
DQ1
MDA21
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
B301
220R
C210
100nF
+MVDDQ
B309
220R
DNI
C216
1uF
+MVDDC
VREF_A1
+MVDDQ
R304
4.99K
R305
4.99K
4
QSA4
U22
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HY5PS561621F-25
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
B9
B1
D9
D1
D3
D7
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
MAA12
MAA13
MAA14
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
CLKA#1[4,9]
CLKA1[4,9]
CKEA
CSA#0
WEA#
RASA#
CASA#
DQMA#4 DQMA#6DQMA#2
DQMA#5 DQMA#7
ODTA1
R324 10R
R325 10R
VREF_U22
C283
100nF
MDA43
MDA44
MDA40
MDA46
MDA47
MDA42
MDA45
MDA41
MDA35
MDA36
MDA32
MDA39
MDA38
MDA33
MDA37
MDA34
B302
220R
C226
100nF
3
+MVDDQ
B310
220R
DNI
C236
1uF
+MVDDC
VREF_A1
+MVDDQ
R326 10R
R327 10R
R306
4.99K
VREF_U23
R307
4.99K
C284
100nF
MAA12
MAA13
MAA14
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
CLKA#1
CLKA1
CKEA
CSA#0
WEA#
RASA#RASA#
CASA#
ODTA1
QSA7
2
U23
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
WEK3VDDQ10
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HY5PS561621F-25
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
1
MDA60
B9
MDA59
B1
MDA63
D9
MDA56
D1
MDA57
D3
MDA62
D7
MDA58
C2
DQ9
MDA61
C8
DQ8
MDA52
F9
DQ7
MDA51
F1
DQ6
MDA54
H9
DQ5
MDA48
H1
DQ4
MDA49
H3
DQ3
MDA55
H7
DQ2
MDA50
G2
DQ1
MDA53
G8
DQ0
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
B303
220R
C246
100nF
+MVDDQ
B311
220R
DNI
C256
1uF
+MVDDC
B B
+MVDDQ +MVDDQ
R312
4.99K
VREF_A0 VREF_A1
R313
4.99K
MS-V038 ATI 9250
Custom
Thursday, September 22, 2005
2
R314
4.99K
R315
4.99K
10 15
10
of
1
ODTA0
+MVDDQ
3
R308
4.99K
+MVDDC
C208
100nF
402
C223
100nF
402
C228
100nF
C209
100nF
C224
C225
100nF
100nF
402
C229
100nF
402
402
C207
100nF
402
+MVDDQ
C222
A A
C221
100nF
100nF
402
402 402
+MVDDC +MVDDC
C227
100nF
402
8
+MVDDQ
C231
100nF
402402
+MVDDC
7
C217
100nF
402
C232
100nF
C237
100nF
402
C218
100nF
C233
100nF
402
C238
100nF
C219
100nF
402
402402
C234
C235
100nF
100nF
402
402
Put 1 1uF cap per power pin of memory
C204
100nF
402
C205
100nF
402
+MVDDQ
C211
100nF
402
C212
100nF
100nF
402
402
5
100nF
402402
C215
100nF
402
4
C214
C213
+MVDDQ
C239
100nF
402
402
C201
100nF
6
C202
100nF
402
C203
100nF
402
ODTA1
+MVDDQ
R310
4.99K
Size D o c u m ent Num ber Rev
Date: Sheet
www.vinafix.vn
8
D D
7
6
5
4
3
2
1
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
PRIMARY CRT
Place close to ASIC
CRT1_R
CRT1_G
CRT1_B
CRT_DDCDATA
CRT_DDCCLK
C408
3.3pF
6
8
B7 82nH
B9 82nH
B11 82nH
C412
3.3pF
+3.3V_BUS
R419
4.7K
+3.3V_BUS
R420
4.7K
A_HSYNC_DAC1_B
A_VSYNC_DAC1_B
1
32
BSN20
Q3
1
32
BSN20
Q4
R885
R884
A_R_DAC1[3]
A_G_DAC1[3]
A_B_DAC1[3]
R1259
75.0R
R1260
75.0R
C404
3.3pF
DNI DNI DNI DNI DNI DNI
CRT1DDCDATA[3]
CRT1DDCCLK[3]
5
4
U6B
SN74ACT86D
10
9
U6C
SN74ACT86D
R1258
75.0R
C C
B B
A_HSYNC_DAC1[3]
A_VSYNC_DAC1[3]
C413
5pF
C409
5pF
+5V_BUS
R401
6.8k
+5V_BUS
R398
6.8k
C405
5pF
R522
51R
51R
B8 82nH
B10 82nH
B12 82nH
33R
33R
R523
A_HSYNC_DAC1_R
A_VSYNC_DAC1_RA_VSYNC_DAC1_R
+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V_BUS+5V_BUS
BAT54SLT1
BAT54SLT1
D3
DNI
3
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
2
1
BAT54SLT1
2
1
DNI
2
D1
3
1
C414
5pF
B15
82nH
DNI DNI DNI
GND_CHASSIS
D2
DNI
3
BAT54SLT1
DNI
C410
5pF
B14
82nH
C406
5pF
B13
82nH
D4
+5V_BUS +5V_BUS
BAT54SLT1
2
DNI
3
1
C415
D5
10pF
BAT54SLT1
2
DNI
3
1
C416
10pF
Place close to CONNECTOR
CRT1_R
CRT1_G
CRT1_B
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
CRT_DDCDATA
CRT_DDCCLK
D8
3
C417
10pF
BAT54SLT1
2
DNI
1
C419
10pF
14 Pin VGA Header
2
D9
3
1
J1
1
2
3
4
5
6
7 14
+5V_BUS
F1
750mA
Resettable fuse
C402
68pF
8
9
10
11
12
13
5V_DVI [13]
GND_CHASSIS
11
12
15
13
14
10
16
17
1
2
3
4
9
5
6
7
8
J4
R
G
B
MS0
MS1
MS2
MS3
NC
HS
VS
VSS
VSS#6
VSS#7
VSS#8
VSS#10
CASE
CASE#17
Slim VGA
A A
Size D o c u m ent Num ber Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
MS-V038 ATI 9250
Thursday, September 22, 2005
11 15
1
10
of
www.vinafix.vn
8
7
6
5
4
3
2
1
Place close to ASIC
D D
C C
Pr
A_R/C_DAC2[3]
Y
A_G/Y_DAC2[3]
A_B/COMP_DAC2[3]
Pb
+3.3V_BUS
R586
10K
DC_Strap5[3,8]
402
U96
1
SEL
2
1A0
3
1A1
5
1B0
6
1B1
11
1C0
1C1101D0
15
E
PI5V330
A_R/C_DAC2
A_G/Y_DAC2
A_B/COMP_DAC2
VCC
YA
YB
YC
YD
1D1
GND
A_R_DAC2
A_G_DAC2
+5V_BUS
C155
100nF
402
16
4
7
9
12
13
14
8
A_B_DAC2
A_C_DAC2
A_Y_DAC2
A_COMP_DAC2
B30 82nH
B32 82nH
B34 82nH
R1001
75.0R
R1002
75.0R
C297
C298
3.3pF
3.3pF
DNI DNIDNI
C299
3.3pF
R1000
75.0R
Pr
Y
Pb
Place close to ASIC
B31 82nH
B33 82nH
B35 82nH
C305
C304
C303
5pF
5pF
5pF
R_DAC2 [13]
G_DAC2 [13]
B_DAC2 [1 3 ]
Pr
A_R/C_DAC2
Y
A_G/Y_DAC2
Pb
A_B/COMP_DAC2
B B
A A
MUX BYPASS
Place Resistors close to ASIC.
A_Y_DAC2
A_C_DAC2
A_COMP_DAC2
R1257
75.0R
R1256
75.0R
R1255
75.0R
R9280R
402
R9290R
402
R9300R
402
R9700R
402
R9710R
402
R9720R
402
A_R_DAC2
A_G_DAC2
A_B_DAC2
A_C_DAC2
A_Y_DAC2
A_COMP_DAC2
L20 1 .8uH
C550
82pF
L21 1 .8uH
C552
82pF
L22 1 .8uH
C554
82pF
Pr
Y
Pb
Pr
Y
Pb
C551
82pF
C553
82pF
C555
82pF
Place near connector
0R leaves footprint for Ferrite
Beads if req'd for EMI
A_C_DAC2_F A_C_DAC2_DIN
A_Y_DAC2_DINA_Y_DAC2_F
A_COMP_DAC2_DINA_COMP_DAC2_F PIN7
TV Out (SVHS)
GND_CHASSIS
J6
6
+12V
3
Y-OUT
4
C-OUT
7
Comp_out
PIN5
5
SYNC
1
GND
2
GND#2
8
CASE
9
CASE#9
10
CASE#10
Connector_DIN_Miniature_Circular_7_Pin
GND_CHASSIS
Size D o c u m ent Num ber Rev
Custom
8
7
6
5
4
3
Date: Sheet
MS-V038 ATI 9250
Thursday, September 22, 2005
2
of
12 15
10
1
www.vinafix.vn
5
TMDS_TX2N[3]
D D
TMDS_TX2P[3]
TMDS_TX1N[3]
TMDS_TX1P[3]
TMDS_TX0N[3]
TMDS_TX0P[3]
TMDS_TXCP[3]
TMDS_TXCN[3]
+3.3V_BUS
1
R416
C C
DVIDDCDATA[3]
DVIDDCCLK[3]
A_HSYNC_DAC2[3]
4.7K
+3.3V_BUS +5V_BUS
R417
4.7K
1
+5V_BUS
147
1
2
32
BSN20
Q5
32
BSN20
Q6
C900
100nF
X7R
SN74ACT86D
U7A
3
+5V_BUS
R400
6.8k
R399
6.8k
R601
330R
402
R602
330R
402
R603
330R
402
R604
330R
402
DDCDATA_DAC1_5V DDCDATA_DVI-I_R
DDCCLK_DAC1_5V
R901
R520
R521
4
33R
33R
51R
DDCCLK_DVI-I_R
3
5V_DVI[11]
R_DAC2[12]
G_DAC2[12]
B_DAC2[12]
+5V_BUS +3.3V_BUS +3.3V_BUS
2
D10
3
1
2
CASE
TMDS Data2-
TMDS Data2+
TMDS Data2/4 Shield
TMDS Data4TMDS Data4+
DDC Clock
DDC Data
Analog VSYNC
TMDS Data1TMDS Data1+
TMDS Data1/3 Shield
TMDS Data3TMDS Data3+
+5V Power
GND (for +5V)
Hot Plug Detect
TMDS Data0TMDS Data0+
TMDS Data0/5 Shield
TMDS Data5TMDS Data5+
TMDS Clock Shield
TMDS Clock+
TMDS Clock-
Analog Red
Analog Green
Analog Blue
Analog HYNC
Analog GND
Analog GND#C6
CASE#M2
M4
CASE#M3
CASE#M2
M3
J2
M1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C1
Pr
C2
Y
C3
Pb
C4
C5
C6
M2
2
2
D11
3
1
D12
3
1
DNI
DVI_A/D
1
PRIMARY DVI-I CONNECTOR
GND_CHASSIS
+3.3V_BUS
+5V_BUS
2
D13
3
2
D14
3
1
1
5
6
B B
A_VSYNC_DAC2[3]
A A
4
U7B
SN74ACT86D
10
13
12
5
8
9
U7C
SN74ACT86D
11
U7D
SN74ACT86D
R900
51R
+3.3V_BUS
R605
R606
20K
20K
402
2 3
CMPT3904
402
1
Q28
1
2 3
3
HPD[3]
D121
2.5V
DNI
2 1
4
Q27
CMPT3904
R609
100K
402 402
R608 20K
R607 20K
402
Size D o c u m ent Num ber Rev
Custom
2
Date: Sheet
MS-V038 ATI 9250
Thursday, September 22, 2005
1
13 15
10
of
www.vinafix.vn
5
4
3
2
1
CRT SCREWS
ASSY1
SCREW
JACKSCREW
ASSY
D D
C C
ASSY2
1
1
1
1
SCREW
JACKSCREW
ASSY
FM1
SW_FB
FM2
SW_FB
FM3
SW_FB
FM4
SW_FB
CABLE
D-sub Cable
Heatsink
MH101
PCB
STD
COMMON
SCREW-1
MEC_SCREW
STD
COMMON
SCREW-2
MEC_SCREW
STD
COMMON
SCREW-3
MEC_SCREW
STD
COMMON
SCREW-4
MEC_SCREW
PCB
PCB
BRACKET
BRACKET
BRACKET
HEATSINK
FM5
SW_FB
1
FM6
SW_FB
1
FM7
SW_FB
1
FM8
SW_FB
1
D-Sub Cable
+12V_BUS
C901
100nF
603
X7R
5%
B40
Bead
J200
1
2
F ST SHR IRT
COMMON
B2B_XHA2_5MM_O
B B
A A
Size D o c u m ent Num ber Rev
Custom
5
4
3
2
Date: Sheet
MS-V038 ATI 9250
Thursday, September 22, 2005
1
14 15
10
of
www.vinafix.vn
<Variant Name>
5
4
3
2
1
Title
RV280 LP AGP8x 128MB 16Mx16 DDR
D D
Sch
Rev
0
1 00B
C C
200
Date
03/25/03 Based on 105-A062xx-00 schematic
00A
04/01/03 (pg5) Replace VDDC 470uF with thru-hole
04/10/03 (pg6) Remove C1, C17 and C1034
05/14/03
05/30/03 (pg9) Replace a 2-pin with a 3-pin jumper for NTSC/PAL section.
(pg2) Add pull-up on CS# for flashrom
(pg5) Replace swiching VDDC regulator with Op-Amp regulator circuit
(pg5) Add Op-Amp regulator circuit for low-cost design
(pg6) Add Op-Amp regulator circuit for low-cost design
(pg6) Remove C317 Thru-hole Alum. Cap for MVDDC
(pg6) Add +3.3V_BUS directly to +MVDDC option
(pg11) Modify VO connector filter chassis ground connections
(pg6) Add thru-hole 470uF on +MVDDC for option
(pg5) Remove Q811 and Q814
(pg6) Add C805 10uF tant. cap on +MPVDD
(pg6) Add R112 to bypass opamp for +MVDDC
(pg6) Remove diodes (D10 and D11) and resistors (R111, R1261, R1262, R1263 and R1264) for +MVDDC
(pg5, 6) Add R104 to drive +MVDDC from alternate shunt reference
(pg7) Add jumper J1 for PAL TVO default
(Layout) Add silscreen for switch and jumper
(Layout) Corr ect M iniDIN J6 footprint
(Layout) Correct diode clearance for manufacturing request
(Layout) Move sticker location
(pg5) Add R812, R813 and R815 for +MVDDC voltage adjustment
(Layout) Change footprint of P/N4238010600
REVISION HISTORY
REVISION DESCRIPTION
105-A165XX-00
Date:Schematic No.
Thursday, September 22, 2005
Rev
10
3 0A 07/15/05 Redesign form 8999-1A schematic
B B
A A
5
4
www.vinafix.vn
3
2
1
Loading...