MSI MS-V033 Schematic 10

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

NV41/42/G70-P317, 256bit, 4M/8Mx32bit DDR3

Page Overview

Page1: Overview
Page2: PCI Express 1.0
Page3: MEMORY: GPU Partition A/B
Page4: MEMORY: GPU Partition C/D
Page5: FrameBuffer: Partition A 8Mx32 BGA144 DDR3
Page6: FrameBuffer: Partition A Decoupling
Page7: FrameBuffer: Partition B 8Mx32 BGA144 DDR3
Page8: FrameBuffer: Partition B Decoupling
Page9: FrameBuffer: Partition C 8Mx32 BGA144 DDR3
Page10: FrameBuffer: Partition C Decoupling
Page11: FrameBuffer: Partition D 8Mx32 BGA144 DDR3
Page12: FrameBuffer: Partition D Decoupling
Page13: DACA Interface
Page14: DACC Interface
Page15: IFP A/B and C/D Interface
Page16: DACB Interface/Framelock
Page17: Video Capture (Philips 7115)
Page18: Multi-use IO(MIO) Interface
Page19: PEX: Zero Delay Buffer
Page20: MISC: GPIO, I2C, THERMAL, BIOS, XTAL
Page21: Strapping Configuration
Page22: Power/GND and Decoupling
Page23: Power Supply I: TMDS/MIOA/DACB Alternate Supplies
Page24: Power Supply II: 5V and A3V3
Page25: Power Supply III: FBVDDQ and PEX_VDD
Page26: Power Supply IV: External 12V + NVVDD VID Control
Page27: Power Supply V: NVVDD
Page28: Mechanical: Bracket/Thermal Solution

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Overview

www.vinafix.vn

600-10317-0002-100

design
John Lam

1 OF 28

31-MAY-2005

J501

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIOUT

OUT

IN

23/24 JTAG

JTAG_TRST

JTAG_TDO

JTAG_TMS

JTAG_TCLK

JTAG_TDI

KEY

TRST*

GND

TCK

TMS
TDI
VCC
TDO

1/24 PCI EXPRESS

PEX_IOVDD

PEX_IOVDD

PEX_IOVDD

PEX_IOVDD
PEX_IOVDD

PEX_IOVDD

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_PLLAVDD

RFU

RFU

PEX_PLLDGND

PEX_PLLDVDD

PEX_PLLAGND

PEX_TEST_PLL_CLK_OUT
PEX_TEST_PLL_CLK_OUT

PEX_TX0

PEX_RST

PEX_REFCLK
PEX_REFCLK

PEX_TX0

PEX_TX2

PEX_RX2

PEX_TX3

PEX_RX1

PEX_RX0

PEX_TX1

PEX_RX1

PEX_TX2

PEX_RX2

PEX_RX0

PEX_TX1

PEX_RX3

PEX_RX3

PEX_TX3

PEX_TX7

PEX_RX6

PEX_TX4

PEX_RX6

PEX_TX6

PEX_RX5

PEX_TX5

PEX_TX5

PEX_RX4

PEX_RX5

PEX_TX6

PEX_RX4

PEX_TX4

PEX_TX7

PEX_RX7

PEX_TX9

PEX_TX10

PEX_RX8

PEX_TX9

PEX_RX9

PEX_TX8

PEX_RX10

PEX_RX8

PEX_RX9

PEX_TX10

PEX_TX8

PEX_RX7

PEX_TX11

PEX_RX13
PEX_RX13

PEX_RX11

PEX_TX12

PEX_RX10

PEX_TX11

PEX_RX11

PEX_TX12

PEX_RX12
PEX_RX12

PEX_TX13
PEX_TX13

PEX_TX14

PEX_RX15

PEX_TX14

PEX_RX14
PEX_RX14

PEX_RX15

PEX_TX15

PEX_TX15

ININOUT

OUT

END OF X4

END OF X1

END OF X16

END OF X8

TCLK JTAG2

TDI JTAG3
TDO JTAG4
TMS JTAG5

WAKE

SMDAT

SMCLK

PERST

REFCLK

PERP0
PERN0

REFCLK

PETP0

PERN1

PERP1

PETN0

PERP2

PETN1

PETP1

PETP2

PETN3

PETP3

PERN3

PETN2

PERN2

PERP3

PETP4

PERP5

PETN4

PERN4

PERP4

PERN5

PETP5
PETN5

PERP6
PERN6

PETP6
PETN6

PERP7
PERN7

PETP7
PETN7

PERP8

PETP8
PETN8

PERN8

PERP9
PERN9

PETP9
PETN9

PERP10
PERN10

PETP10
PETN10

PERP11

PERN12

PERP12

PETN11

PETP11

PERN11

PETN13

PETP12
PETN12

PERN13

PETP13

PERP13

PERP14

PETN15

PETP15

PERN15

PERP15

PERN14

PETN14

PETP14

TRST* JTAG1+12V

+12V/RSVD

+3V3AUX

+12V

+12V

+12V

+3V3
+3V3
+3V3

PRSNT2

PRSNT1

GND

GND

RSVD

GND
GND
GND

GND

GND

GND
GND

PRSNT2
RSVD

RSVD

GND
GND

RSVD

GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

PRSNT2
RSVD

GND

GND

GND
GND

GND
GND

GND
GND

GND

GND
GND
GND

GND

GND

GND

PRSNT2

GND

RSVD

RSVD

GND

GND

GND

GND
GND
GND
GND
GND
GND

GND
GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND
GND

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

HDR_2F4

FEMALE

NV_SOURCE_POWER_NET=TRUE

12 V

5.5A

C43

C42

4.7UF

4.7UF

16V

16V

20%

20%

X7R

X7R

1206

1206

COMMON

COMMON

NV_SOURCE_POWER_NET=TRUE

3.3 V

3A

C47

C54

.1UF

4.7UF

16V

6.3V
10%

10%

X7R

X5R

0402

0603

COMMON

COMMON

20MIL

C45
.1UF

16V
10%
X7R
0402
COMMON

20MIL

SNN_3V3AUX

PRSNT*

SNN_PE_PRSNT2_A

SNN_PE_RSVD2

CN2

CON_X16
COMMON

CON_PCIEXP_X16_EDGE

B1
B2
A2
A3
B3

B8
A9

A10

B10

A1

B17

B12

B4
A4

B7
A12
B13
A15
B16
B18
A18

2 PCI Express 1.0

12V

GND

3V3

GND

SNN_PE_PRSNT2_B
SNN_PE_RSVD3
SNN_PE_RSVD4
SNN_PE_RSVD5

SNN_PE_PRSNT2_C
SNN_PE_RSVD6

PRSNT*
SNN_PE_RSVD7
SNN_PE_RSVD8

GND

B31
A19
B30
A32

A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32

B48

GND

A33

A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49

GND

B81
A50
B82

A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82

GND

PEX JTAG

A

PEX_TRST*

B9

PEX_TCLK

A5

PEX_TDI

A6
A7
A8

B5
B6

B11

A11

A13
A14

A16
A17

B14
B15

A21
A22

B19
B20

A25
A26

B23
B24

A29
A30

B27
B28

A35
A36

B33
B34

A39
A40

B37
B38

A43
A44

B41
B42

A47
A48

B45
B46

A52
A53

B50
B51

A56
A57

B54
B55

A60
A61

B58
B59

A64
A65

B62
B63

A68
A69

B66
B67

A72
A73

B70
B71

A76
A77

B74
B75

A80
A81

B78
B79

PEX_TDO
PEX_TMS

SNN_PEX_SMCLK
SNN_PEX_SMDAT

SNN_PEX_WAKE*

PEX_RST*
PEX_REFCLK
PEX_REFCLK*

PEX_TXX0
PEX_TXX0*

PEX_RX0
PEX_RX0*

PEX_TXX1
PEX_TXX1*

PEX_RX1
PEX_RX1*

PEX_TXX2
PEX_TXX2*

PEX_RX2
PEX_RX2*

PEX_TXX3
PEX_TXX3*

PEX_RX3
PEX_RX3*

PEX_TXX4
PEX_TXX4*

PEX_RX4
PEX_RX4*

PEX_TXX5
PEX_TXX5*

PEX_RX5
PEX_RX5*

PEX_TXX6
PEX_TXX6*

PEX_RX6
PEX_RX6*

PEX_TXX7
PEX_TXX7*

PEX_RX7
PEX_RX7*

PEX_TXX8
PEX_TXX8*

PEX_RX8
PEX_RX8*

PEX_TXX9
PEX_TXX9*

PEX_RX9
PEX_RX9*

PEX_TXX10
PEX_TXX10*

PEX_RX10
PEX_RX10*

PEX_TXX11
PEX_TXX11*

PEX_RX11
PEX_RX11*

PEX_TXX12
PEX_TXX12*

PEX_RX12
PEX_RX12*

PEX_TXX13
PEX_TXX13*

PEX_RX13
PEX_RX13*

PEX_TXX14
PEX_TXX14*

PEX_RX14
PEX_RX14*

PEX_TXX15
PEX_TXX15*

PEX_RX15
PEX_RX15*

A = Default STUFF for no PEX JTAG
B = STUFF for Compliance board

C1016

COMMON

C1004

COMMON

C991

COMMON

C985

COMMON

C967

COMMON

C950

COMMON

C931

COMMON

C907

COMMON

COMMON

C853

COMMON

C818

COMMON

C788

COMMON

C751

COMMON

C729

COMMON

C722

COMMON

C720

COMMON

0

R715

COMMON

0402

5%

2<> 19<
2<> 19<

2<>

19>

2<>

19>

.1UF

C1011

10V

0402

10%

0402

X5R

.1UF

0402 10V .1UFC1002

10%

0402

X5R

.1UF

C989

10V

0402

10%

0402

X5R

.1UF

C974

10V

0402

10%

0402

X5R

.1UF

C965

10V

0402

10%

0402

X5R

.1UF

C945

10V

0402

10%

0402

X5R

.1UF

C920

10V

0402

10%

0402

X5R

.1UF

10V

0402

10%

0402

X5R

.1UFC885

C876

10V

0402

10%

0402

X5R

.1UF

C840

10V

0402

10%

0402

X5R

.1UF

C815

10V

0402

10%

0402

X5R

.1UF

C780

10V

0402

10%

0402

X5R X5R

.1UF

10V

0402

10%

0402

X5R

.1UF

10V

0402

10%

0402

X5R

.1UF

C721

10V

0402

10%

0402

X5R

.1UF

C716

10V

0402

10%

0402

X5R

.1UF

10V

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UFC896

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UFC744

10V

.1UFC725

10V

.1UF

10V

.1UF

10V

0402X4

0402X4

0402X4

0402X4

R710

0402

RP1

0.05R_MAX

RP1

0.05R_MAX

RP1

0.05R_MAX

RP1

0.05R_MAX

PEX_REFCLK_OUT
PEX_REFCLK_OUT*

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%

10%
X5R

10%
X5R

10%
X5R

10%
X5R

B

0

NO STUFF

5%

0

5

4

NO STUFF

0

6

3

NO STUFF

0

7

2

NO STUFF

0

8

1

NO STUFF

PEX_TX0
PEX_TX0*

COMMON

PEX_TX1
PEX_TX1* AN11

COMMON

PEX_TX2
PEX_TX2*

COMMON

PEX_TX3
PEX_TX3*

COMMON

PEX_TX4

COMMON

PEX_TX5
PEX_TX5*

COMMON

PEX_TX6
PEX_TX6*

COMMON

PEX_TX7
PEX_TX7*

COMMON

PEX_TX8 AM16
PEX_TX8*

COMMON

PEX_TX9
PEX_TX9*

COMMON

PEX_TX10
PEX_TX10*

COMMON

PEX_TX11
PEX_TX11*

COMMON

PEX_TX12
PEX_TX12*

COMMON

PEX_TX13
PEX_TX13*

COMMON

PEX_TX14
PEX_TX14*

COMMON

PEX_TX15
PEX_TX15*

COMMON

AR9

AK10
AL10

AM11
AM10

AP9

AP10

AN10

AR10
AR11

AN12
AM12

AT11
AT12

AL12
AK12

AP12
AP13

AM14
AM13PEX_TX4*

AR13
AR14

AN13
AN14

AT14
AT15

AN15
AM15

AP15
AP16

AL15
AK15

AR16
AR17

AN16

AT17
AT18

AN17
AN18

AP18
AP19

AM18
AM17

AR19
AR20

AL18
AK18

AT20
AT21

AM19
AN19

AP21
AP22

AN20
AN21

AR22
AR23

AM21
AM20

AT23
AT24

AL21
AK21

AR24
AR25

U9
GF-7800-GT-A2

BGA1148
CHANGED

1.274MM
0

3V3

KEY6_JTAG_SMALL
NO STUFF

1
3
5
7

2
4

8

www.vinafix.vn

3V3

R716

R702

R701
10K

5%
0402
COMMONGND

AH21
AJ21
AH22
AJ22
AH23
AJ23

AH16
AF17
AH17
AF18
AH18

AF19
AH19
AE20
AF20
AH20

AJ20

AM9
AN9

AK19

AK20

AE15

180

10K

5%

5%

0402

0402

COMMON

COMMON

R703
10K

5%
0402
COMMON

GND

JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*

R717
270

5%
0402
COMMON

80MIL

C806
.1UF

10V
10%
X5R
0402
COMMON

80MIL

C816

10V
10%
X5R
0402
COMMON

C817
.1UF

10V
10%
X5R
0402
COMMON

PEX_TEST_PLL_CLK_OUT Termination = 200ohm

PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*

PEXCAL_PD_VDDQ

PEXCAL_PD_GND

12MIL

AF15

AE17

AE16

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
PCI Express 1.0

JTAG

AK6
AL8
AL7
AK7
AL9

C799
.1UF

10V
10%
X5R
0402
COMMON

C839
.1UF.1UF

10V
10%
X5R
0402
COMMON

C838
.1UF

10V
10%
X5R
0402
COMMON

R638
200

1%
0402
COMMON

RFU - NOT USED for NV41

49.9

R625

NO STUFF

0402

1%

49.9

R624

NO STUFF

0402

1%

Components will be no stuff

C860

C858

1UF

.1UF

6.3V

10V

10%

10%

X5R

X5R

0402

0402
COMMON COMMON

C841

C855

1UF

.1UF

6.3V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

U9
GF-7800-GT-A2

BGA1148
CHANGED

C798
1UF

6.3V
10%
X5R
0402
COMMON

C819
1UF

6.3V
10%
X5R
0402
COMMON

C836
1UF

6.3V
10%
X5R
0402
COMMON

PEX_PLLVDD

C78

4.7UF

6.3V
10%
X5R
0603
COMMON

C80

4.7UF

6.3V
10%
X5R
0603
COMMON

C754

C743

4.7UF

1UF

6.3V

6.3V
10%

10%

X5R

X5R

0603

0402

COMMON

COMMON

C76

C851
1UF 4.7UF

6.3V

6.3V
10%

10%

X5R

X5R

0603

0402

COMMON

COMMON

C805
1UF

6.3V

10%
X5R
0402
COMMON

GND

LB13

GND

GND

PEX_VDD

COMMONBEAD_0603

C746
10UF

6.3V
20%
X5R
0805
COMMON

GND

C77
10UF

6.3V
20%
X5R
0805
COMMON

220R@100MHz

GND

3GIO NET RULES

NET

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT

PEX_VDD

PEX_VDD

PEX_REFCLK
PEX_REFCLK*

PEX_REFCLK_OUT
PEX_REFCLK_OUT*

PEX_TXX0
PEX_TXX0*
PEX_TXX1
PEX_TXX1*
PEX_TXX2
PEX_TXX2*
PEX_TXX3
PEX_TXX3*
PEX_TXX4
PEX_TXX4*
PEX_TXX5
PEX_TXX5*
PEX_TXX6
PEX_TXX6*
PEX_TXX7
PEX_TXX7*
PEX_TXX8
PEX_TXX8*
PEX_TXX9
PEX_TXX9*
PEX_TXX10
PEX_TXX10*
PEX_TXX11
PEX_TXX11*
PEX_TXX12
PEX_TXX12*
PEX_TXX13
PEX_TXX13*
PEX_TXX14
PEX_TXX14*
PEX_TXX15
PEX_TXX15*

PEX_RX0
PEX_RX0*
PEX_RX1
PEX_RX1*
PEX_RX2
PEX_RX2*
PEX_RX3
PEX_RX3*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_RX14
PEX_RX14*
PEX_RX15
PEX_RX15*

PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*

PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*

100DIFF
100DIFF
100DIFF
100DIFF

100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF

100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF

100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF

100DIFF
100DIFF

Matching Rule of Thumb

4 inch from Top of Gold Fingers to GPU

PEX_VDD

C79

4.7UF

6.3V
10%
X5R
0603
COMMON

*2 inch Lane to Lane Skew

*No real Skew rule, but reducing the skew will minimize latency

NET

PEX_PLLVDD

VOLTAGE

1.2 V

600-10317-0002-100

design
John Lam

DIFFPAIRCRITICALIMPEDANCE

PEX_REFCLK_OUT
PEX_REFCLK_OUT
PEX_REFCLK_OUT
PEX_REFCLK_OUT

PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15

PEX_RX0
PEX_RX0
PEX_RX1
PEX_RX1
PEX_RX2
PEX_RX2
PEX_RX3
PEX_RX3
PEX_RX4
PEX_RX4
PEX_RX5
PEX_RX5
PEX_RX6
PEX_RX6
PEX_RX7
PEX_RX7
PEX_RX8
PEX_RX8
PEX_RX9
PEX_RX9
PEX_RX10
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_RX12
PEX_RX13
PEX_RX13
PEX_RX14
PEX_RX14
PEX_RX15
PEX_RX15

PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15

2 OF 28

31-MAY-2005

2>
19<

19<
2<
19>

19>

3 FrameBuffer: GPU Partition A/B

OUTINININOUT

OUT

OUT

OUT

3/24 MEM_B

FBB_CMD6

FBB_CMD4
FBB_CMD5

FBB_CMD3

FBB_CMD1
FBB_CMD2

FBB_CMD0

FBB_CMD7

FBB_CMD26

FBB_CMD24
FBB_CMD25

FBB_CMD23

FBB_CMD21
FBB_CMD22

FBB_CMD19
FBB_CMD20

FBB_CMD18

FBB_CMD17

FBB_CMD16

FBB_CMD14
FBB_CMD15

FBB_CMD13

FBB_CMD12

FBB_CMD11

FBB_CMD9

FBB_CMD10

FBB_CMD8

FBB_CLK1

FBB_CLK0
FBB_CLK0
FBB_CLK1

RFU
RFU

FBB_DEBUG

FBB_REFCLK

FBCAL1_PD_VDDQ

FBB_REFCLK

FBCAL1_TERM_GND

FBCAL1_PU_GND

FBB_PLLAVDD

FBB_PLLVDD

FBB_PLLGND

FBBD6

FBBD4
FBBD5

FBBD3

FBBD2

FBBD1

FBBD0

FBBD7

FBBD27

FBBD26

FBBD25

FBBD24

FBBD23

FBBD22

FBBD21

FBBD19
FBBD20

FBBD17

FBBD16

FBBD15

FBBD13

FBBD12

FBBD11

FBBD9
FBBD10

FBBD8

FBBD14

FBBD18

FBBD47

FBBD46

FBBD45

FBBD44

FBBD42
FBBD43

FBBD41

FBBD40

FBBD39

FBBD37
FBBD38

FBBD36

FBBD35

FBBD34

FBBD32
FBBD33

FBBD31

FBBD30

FBBD29

FBBD28

FBBD48

FBBDQM2

FBBDQM1

FBBDQM0

FBBD62
FBBD63

FBBD60
FBBD61

FBBD59

FBBD57
FBBD58

FBBD55
FBBD56

FBBD54

FBBD53

FBBD52

FBBD50
FBBD51

FBBD49

FBBDQS_WP2

FBBDQS_WP1

FBBDQS_WP0

FBBDQS_RN7

FBBDQS_RN4
FBBDQS_RN5
FBBDQS_RN6

FBBDQS_RN3

FBBDQS_RN2

FBBDQS_RN1

FBBDQS_RN0

FBBDQM7

FBBDQM6

FBBDQM4
FBBDQM5

FBBDQM3

FBBDQS_WP3

FB_VREF2

FBBDQS_WP7

FBBDQS_WP6

FBBDQS_WP5

FBBDQS_WP4

OUT

OUTBIIN

OUT

OUT

OUT

OUT

OUTBIOUTINOUT

2/24 MEM_A

FBA_CMD0

FBA_CMD2

FBA_CMD1

FBA_CMD3

FBA_CMD5

FBA_CMD4

FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD10

FBA_CMD9

FBA_CMD11
FBA_CMD12
FBA_CMD13

FBA_CMD15

FBA_CMD14

FBA_CMD16
FBA_CMD17
FBA_CMD18

FBA_CMD20

FBA_CMD19

FBA_CMD22

FBA_CMD21

FBA_CMD23

FBA_CMD25

FBA_CMD24

FBA_CMD26

FBA_CLK1

FBA_CLK1

FBA_CLK0

FBA_CLK0

RFU
RFU

FBA_DEBUG

FBA_REFCLK

FBA_PLLAVDD

FBA_REFCLK

FBA_PLLVDD

FBCAL0_TERM_GND

FBCAL0_PU_GND

FBCAL0_PD_VDDQ

FBA_PLLGND

FBAD0
FBAD1
FBAD2
FBAD3

FBAD5

FBAD4

FBAD6
FBAD7
FBAD8

FBAD10

FBAD9

FBAD11

FBAD13

FBAD12

FBAD14
FBAD15
FBAD16
FBAD17
FBAD18

FBAD20

FBAD19

FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27

FBAD40

FBAD46
FBAD47

FBAD28
FBAD29
FBAD30
FBAD31

FBAD33

FBAD32

FBAD34
FBAD35
FBAD36

FBAD38

FBAD37

FBAD39

FBAD41

FBAD43

FBAD42

FBAD44
FBAD45

FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54

FBAD56

FBAD55

FBAD57
FBAD58

FBAD61

FBAD63

FBAD62

FBADQM0
FBADQM1
FBADQM2

FBAD60

FBAD59

FBADQM3

FBADQM5

FBADQM4

FBADQM6
FBADQM7

FBADQS_RN1

FBADQS_RN0

FBADQS_RN2
FBADQS_RN3

FBADQS_RN6

FBADQS_RN5

FBADQS_RN4

FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4

FBADQS_WP6

FBADQS_WP5

FBADQS_WP7

FB_VREF1

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

NET RULES

NET

FBA_PLLVDD
FBB_PLL_VDD
FBAB_PLLAVDD

VOLTAGE

3.3 V

3.3 V

1.4 V

U9
GF-7800-GT-A2

BGA1148

5<>
5<>
5<>

5<>

FBAD<63..0>
FBADQM<7..0>
FBADQS_RN<7..0>
FBADQS_WP<7..0>

FBVDDQ

R608
511

1%
0402
COMMON

R606

1.18K

1%
0402
COMMON

GND

C730
.1UF

10V
10%
X5R
0402
COMMON

GND

VREF = 0.70 * FBVDDQDDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

FB_VREF1

FBAD<0>
FBAD<1>
FBAD<2>
FBAD<3>
FBAD<4>
FBAD<5>
FBAD<6>
FBAD<7>
FBAD<8>
FBAD<9>
FBAD<10>
FBAD<11>
FBAD<12>
FBAD<13>
FBAD<14>
FBAD<15>
FBAD<16>
FBAD<17>
FBAD<18>
FBAD<19>
FBAD<20>
FBAD<21>
FBAD<22>
FBAD<23>
FBAD<24>
FBAD<25>
FBAD<26> AG35
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30>
FBAD<31>
FBAD<32>
FBAD<33>
FBAD<34>
FBAD<35>
FBAD<36>
FBAD<37>
FBAD<38>
FBAD<39>
FBAD<40>
FBAD<41>
FBAD<42>
FBAD<43>
FBAD<44>
FBAD<45>
FBAD<46>
FBAD<47>
FBAD<48>
FBAD<49>
FBAD<50>
FBAD<51>
FBAD<52>
FBAD<53>
FBAD<54>
FBAD<55>
FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<60>
FBAD<61>
FBAD<62>
FBAD<63>

FBADQM<0>
FBADQM<1> AM33
FBADQM<2>
FBADQM<3>
FBADQM<4>
FBADQM<5>
FBADQM<6>
FBADQM<7>

FBADQS_RN<0>
FBADQS_RN<1>
FBADQS_RN<2>
FBADQS_RN<3>
FBADQS_RN<4>
FBADQS_RN<5>
FBADQS_RN<6>
FBADQS_RN<7>

FBADQS_WP<0>
FBADQS_WP<1>
FBADQS_WP<2>
FBADQS_WP<3>
FBADQS_WP<4>
FBADQS_WP<5>
FBADQS_WP<6>
FBADQS_WP<7>

AH35
AH36
AH34
AJ34
AK36
AJ36
AK34
AL34
AH32
AK33
AJ33
AH33
AL33
AN32
AN33
AN31
AE32
AF30
AF32
AE30
AE31
AC30
AC32
AD30
AG36
AG34

AF36
AD36
AD34
AD35
AE34
AP36
AN35
AM34
AP35
AP34
AP33
AT34
AR34
AM22
AM25
AN26
AN24
AK24
AL22
AK23
AM23
AT32
AT33
AR33
AP31
AR30
AT30
AP30
AT29
AP26
AP27
AT25
AP25
AR28
AP28
AT28
AP29

AK35

AF33
AF34
AN34
AM24
AP32
AR27

AL35
AK32
AG33
AE36
AM36
AN22
AR31
AT27

AL36
AL32
AG32
AE35
AN36
AN23
AT31
AT26

J29

CHANGED

CALIBRATION PIN

FB_CALx_PD_VDDQ

FB_CALx_PU_GND

FB_CALx_TERM_GND

VREF RATIO

DDR3

60

40

40

0.7 FBVDDQ

AK28
AK29
AN30
AM27
AN28
AL29
AM30
AJ31
AK31
AH31
AK25
AM26
AL31
AN29
AK27
AK26
AN27
AL25
AJ30
AM31
AH30
AL30
AH29
AL28
AH28
AM28

AH27
AJ29
AJ28

AJ24

AH25

AF28
AG28

J28

H28

H29

AF29

AD29

AE29

GND

FBA_CMD<0>
FBA_CMD<1>
FBA_CMD<2>
FBA_CMD<3>
FBA_CMD<4>
FBA_CMD<5>
FBA_CMD<6>
FBA_CMD7
FBA_CMD<8>
FBA_CMD<9>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<12>
FBA_CMD<13>
FBA_CMD<14>
FBA_CMD<15>
FBA_CMD<16>
FBA_CMD<17>
FBA_CMD<18>
FBA_CMD<19>
FBA_CMD<20>
FBA_CMD<21>
FBA_CMD<22>
FBA_CMD<23>
FBA_CMD<24>
FBA_CMD<25>
SNN_FBA_CMD26AG30

FBA_CLK0AH26
FBA_CLK0*
FBA_CLK1
FBA_CLK1*

SNN_FBA_RFU0
SNN_FBA_RFU1AH24

FBA_DEBUG

SNN_FBA_REFCLK
SNN_FBA_REFCLK*

FBCAL0_PD_VDDQ

FBCAL0_PU_GND

FBCAL0_TERM_GND

12MIL

FBA_PLLVDD

12MIL

FBAB_PLLAVDD

NO STUFF

GND

GND

TP512

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

.01UF

16V
10%
X7R
0402
COMMON

C742
.01UF

16V
10%
X7R
0402
COMMON

0
1
2
3
4
5
6

8
9

NO STUFF

FBA_CMD<0..26>

TP511

5<
5<
5<
5<

60.4

R613

COMMON

0402

1%

40.2

R610

COMMON

0402

1%

69.8

R605

CHANGED

0402

1%

.1UF

10V
10%
X5R
0402
COMMON

GND

C750
.1UF

10V
10%
X5R
0402
COMMON

GND GND

144BGA CMD Mapping

CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21
CMD22

CMD24
CMD25
CMD26

GND

ADDRCMD
A<3>
A<0>
A<2>
A<1>
A<3>
A<4>
A<5>
CS1* *not used
CS0*
WE*
BA0
CKE
RESET
A<2>
A<12>
RAS*
A<11>
A<10
BA1
A<8>
A<9>
A<6>
A<5>
A<7>CMD23
A<4>
CAS*
A<13> *not used

180R@100MHz

LB502

BEAD_0603

C723C734 C752

4.7UF

6.3V
10%
X5R
0603
COMMON

180R@100MHz

LB501

BEAD_0603

C719

4.7UF

6.3V
10%
X5R
0603
COMMON

5<

COMMON

GND

COMMON

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
MEMORY: GPU Partition A/B

GND

C713

4.7UF

6.3V
10%
X5R
0603
COMMON

C715

4.7UF

6.3V
10%
X5R
0603
COMMON

FBVDDQ

A3V3

NVVDD

7<>
7<>
7<>

7<>

www.vinafix.vn

FBBD<63..0>
FBBDQM<7..0>
FBBDQS_RN<7..0>
FBBDQS_WP<7..0>

C753
.1UF

10V
10%
X5R
0402
COMMON

GND

VREF = 0.70 * FBVDDQDDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBVDDQ

GND

R615
511

1%
0402
COMMON

R614

1.18K

1%
0402
COMMON

0
1
2
3
4
5
6
7

FB_VREF2

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

FBBD<0>
FBBD<1>
FBBD<2>
FBBD<3>
FBBD<4>
FBBD<5>
FBBD<6>
FBBD<7>
FBBD<8>
FBBD<9>
FBBD<10>
FBBD<11>
FBBD<12>
FBBD<13>
FBBD<14>
FBBD<15>
FBBD<16>
FBBD<17>
FBBD<18>
FBBD<19>
FBBD<20>
FBBD<21>
FBBD<22>
FBBD<23>
FBBD<24>
FBBD<25>
FBBD<26>
FBBD<27>
FBBD<28>
FBBD<29>
FBBD<30>
FBBD<31>
FBBD<32>
FBBD<33>
FBBD<34>
FBBD<35>
FBBD<36>
FBBD<37>
FBBD<38>
FBBD<39>
FBBD<40>
FBBD<41>
FBBD<42>
FBBD<43>
FBBD<44>
FBBD<45>
FBBD<46>
FBBD<47>
FBBD<48>
FBBD<49>
FBBD<50>
FBBD<51>
FBBD<52>
FBBD<53>
FBBD<54>
FBBD<55>
FBBD<56>
FBBD<57>
FBBD<58>
FBBD<59>
FBBD<60>
FBBD<61>
FBBD<62>
FBBD<63>

FBBDQM<0>
FBBDQM<1>
FBBDQM<2>
FBBDQM<3>
FBBDQM<4>
FBBDQM<5>
FBBDQM<6>
FBBDQM<7>

FBBDQS_RN<0>
FBBDQS_RN<1>
FBBDQS_RN<2>
FBBDQS_RN<3>
FBBDQS_RN<4>
FBBDQS_RN<5>
FBBDQS_RN<6>
FBBDQS_RN<7>

FBBDQS_WP<0>
FBBDQS_WP<1>
FBBDQS_WP<2>
FBBDQS_WP<3>
FBBDQS_WP<4>
FBBDQS_WP<5>
FBBDQS_WP<6>
FBBDQS_WP<7>

U9
GF-7800-GT-A2

BGA1148
CHANGED

G36
G35
H36
H34
J35
J34
K34 T30
K35
J31
K32
J30
H30
L32
K30
M31
L30
G31
J32
J33
F33
H31
E33
F31
F32
F35
G34
F36
F34
C35
D34
C36
D35
N35
M34
L34
N36
P36
P34
R36
R34

AC33

Y33

Y30
AB30
AA32
AD32
AD33
AA33

T36

R35

T34

U36

W35

U34

V34

W36
AC36
AA36
AC34
AB34
AA35

Y34

Y36

W34

J36

M32

H33

E34

N34

Y32

T35
AA34

L36

K33

G32

E36

M36
AB32

V35
AB35

K36

L33

G33

D36

M35
AB31

V36
AB36

J27

FBB_CMD<0>

P33

FBB_CMD<1>

N33

FBB_CMD<2>

R31

FBB_CMD<3>

U33

FBB_CMD<4>

V30

FBB_CMD<5>

T33

FBB_CMD<6>
SNN_FBB_CMD7

N32

FBB_CMD<8>

R32

FBB_CMD<9>

P32

FBB_CMD<10>

U32

FBB_CMD<11>

U30

FBB_CMD<12>

P30

FBB_CMD<13>

V31

FBB_CMD<14>

T28

FBB_CMD<15>

W30

FBB_CMD<16>

V32

FBB_CMD<17>

T32

FBB_CMD<18>

N30

FBB_CMD<19>

P28

FBB_CMD<20>

P29

FBB_CMD<21>

U29

FBB_CMD<22>

N28

FBB_CMD<23>

R30

FBB_CMD<24>

M30

FBB_CMD<25>

T29

SNN_FBB_CMD26

N29

FBB_CLK0

M28

FBB_CLK0*

L28

FBB_CLK1

W31

FBB_CLK1*

W32

SNN_FBB_RFU0

R28

SNN_FBB_RFU1K29

FBB_DEBUG

C34

SNN_FBB_REFCLK

AA30

SNN_FBB_REFCLK*

Y29

H27

H26

J26

AB28

AC29

FBCAL1_PD_VDDQ

FBCAL1_PU_GND

FBCAL1_TERM_GND

12MIL

FBB_PLL_VDD

FBAB_PLLAVDD

NO STUFF

AC28

GND

GND

FBB_CMD<0..26>

0
1
2
3
4
5
6

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

7<
7<
7<
7<

TP510

60.4

R616

COMMON

0402

1%

40.2

R618

COMMON

0402

1%

69.8

R619

CHANGED

0402

1%

180R@100MHz

LB503

.01UF

16V
10%
X7R
0402
COMMON

.1UF

10V
10%
X5R
0402
COMMON

GND

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

600-10317-0002-100

design
John Lam

7<

COMMONBEAD_0603

GND

C714C724C749 C758

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

3 OF 28

31-MAY-2005

FBVDDQ

A3V3

4 FrameBuffer: GPU Partition C/D

OUTINININOUT

OUT

OUT

OUT

5/24 MEM_D

FBD_CMD6

FBD_CMD4
FBD_CMD5

FBD_CMD3

FBD_CMD2

FBD_CMD1

FBD_CMD0

FBD_CMD7

FBD_CMD26

FBD_CMD24
FBD_CMD25

FBD_CMD21
FBD_CMD22
FBD_CMD23

FBD_CMD20

FBD_CMD19

FBD_CMD18

FBD_CMD17

FBD_CMD16

FBD_CMD15

FBD_CMD14

FBD_CMD13

FBD_CMD12

FBD_CMD11

FBD_CMD9

FBD_CMD10

FBD_CMD8

FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1

RFU
RFU

FBD_REFCLK

FBD_DEBUG

FBD_PLLVDD

FBD_PLLAVDD

FBD_REFCLK

FBD_PLLGND

FBDD6

FBDD5

FBDD4

FBDD3

FBDD2

FBDD1

FBDD0

FBDD7

FBDD27

FBDD26

FBDD24

FBDD23

FBDD22

FBDD19
FBDD20

FBDD18

FBDD17

FBDD16

FBDD14
FBDD15

FBDD13

FBDD12

FBDD11

FBDD9
FBDD10

FBDD8

FBDD25

FBDD21

FBDD47

FBDD46

FBDD45

FBDD44

FBDD43

FBDD42

FBDD39

FBDD41

FBDD40

FBDD37
FBDD38

FBDD35
FBDD36

FBDD34

FBDD32
FBDD33

FBDD31

FBDD30

FBDD29

FBDD28

FBDD48

FBDDQM2

FBDDQM1

FBDDQM0

FBDD63

FBDD62

FBDD60
FBDD61

FBDD59

FBDD58

FBDD57

FBDD55
FBDD56

FBDD54

FBDD53

FBDD52

FBDD51

FBDD50

FBDD49

FBDDQS_WP2

FBDDQS_WP1

FBDDQS_WP0

FBDDQS_RN7

FBDDQS_RN4
FBDDQS_RN5
FBDDQS_RN6

FBDDQS_RN3

FBDDQS_RN2

FBDDQS_RN1

FBDDQS_RN0

FBDDQM7

FBDDQM6

FBDDQM4
FBDDQM5

FBDDQM3

FBDDQS_WP3

FBDDQS_WP7

FBDDQS_WP6

FBDDQS_WP5

FBDDQS_WP4

OUT

OUTBIIN

OUT

OUT

OUT

OUT

OUTBIOUTINOUT

4/24 MEM_C

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20

FBC_CMD23

FBC_CMD22

FBC_CMD21

FBC_CMD25

FBC_CMD24

FBC_CMD26

FBC_CLK1

FBC_CLK0

FBC_CLK1

FBC_CLK0

RFU
RFU

FBC_DEBUG

FBC_REFCLK
FBC_REFCLK

FBC_PLLAVDD

FBC_PLLVDD

FBC_PLLGND

FBCD0

FBCD2

FBCD4

FBCD6

FBCD1

FBCD3

FBCD5

FBCD7

FBCD10
FBCD11

FBCD18

FBCD21

FBCD24

FBCD12

FBCD17

FBCD15

FBCD14

FBCD8
FBCD9

FBCD13

FBCD20

FBCD23

FBCD22

FBCD25
FBCD26
FBCD27

FBCD19

FBCD16

FBCD31

FBCD34

FBCD36

FBCD38

FBCD28

FBCD30

FBCD29

FBCD32

FBCD37

FBCD40
FBCD41

FBCD39

FBCD42
FBCD43
FBCD44

FBCD46

FBCD45

FBCD47

FBCD35

FBCD33

FBCD48

FBCD52

FBCD49
FBCD50
FBCD51

FBCD54

FBCD53

FBCD56

FBCD55

FBCD59

FBCD58

FBCD57

FBCD60
FBCD61

FBCD63

FBCD62

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3

FBCDQM5

FBCDQM4

FBCDQM6
FBCDQM7

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3

FBCDQS_RN6

FBCDQS_RN5

FBCDQS_RN4

FBCDQS_RN7

FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

NET RULES

NET

FBC_PLLVDD
FBD_PLLVDD
FBCD_AVDD

VOLTAGE

3.3 V

3.3 V

1.4 V

U9
GF-7800-GT-A2

BGA1148

9<>
9<>
9<>

9<>

FBCD<63..0>
FBCDQM<7..0>
FBCDQS_RN<7..0>
FBCDQS_WP<7..0>

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

FBCD<0>
FBCD<1>
FBCD<2>
FBCD<3>
FBCD<4>
FBCD<5>
FBCD<6>
FBCD<7>
FBCD<8>
FBCD<9>
FBCD<10>
FBCD<11>
FBCD<12>
FBCD<13>
FBCD<14>
FBCD<15>
FBCD<16>
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>
FBCD<24>
FBCD<25>
FBCD<26>
FBCD<27>
FBCD<28>
FBCD<29>
FBCD<30>
FBCD<31>
FBCD<32>
FBCD<33>
FBCD<34>
FBCD<35>
FBCD<36>
FBCD<37>
FBCD<38>
FBCD<39>
FBCD<40>
FBCD<41>
FBCD<42>
FBCD<43>
FBCD<44>
FBCD<45>
FBCD<46>
FBCD<47>
FBCD<48>
FBCD<49>
FBCD<50>
FBCD<51>
FBCD<52>
FBCD<53>
FBCD<54>
FBCD<55>
FBCD<56>
FBCD<57>
FBCD<58>
FBCD<59>
FBCD<60>
FBCD<61>
FBCD<62>
FBCD<63>

FBCDQM<0>
FBCDQM<1> C20
FBCDQM<2>
FBCDQM<3>
FBCDQM<4>
FBCDQM<5>
FBCDQM<6>
FBCDQM<7>

FBCDQS_RN<0>
FBCDQS_RN<1>
FBCDQS_RN<2>
FBCDQS_RN<3>
FBCDQS_RN<4>
FBCDQS_RN<5>
FBCDQS_RN<6>
FBCDQS_RN<7>

FBCDQS_WP<0>
FBCDQS_WP<1>
FBCDQS_WP<2>
FBCDQS_WP<3>
FBCDQS_WP<4>
FBCDQS_WP<5>
FBCDQS_WP<6>
FBCDQS_WP<7>

C18
C17
A17
B16
C14
A16
C15
A14
A18
A19
B19
B18
B21
C19
B22
C21
E15
D16
D17
G16
E16
E14
G13
D13
A22
C22
C23
A23
A24
C24
C25
B24
C28
B27
C27
B28
C29
A29
B30
A30
E31
E28
D28
F29
F30
D33
D32
D31
G27
F25
G26
D26
G29
G28
E27
F28
A34
C32
B34
C33
C31
B31
A31
C30

C16

G14
C26
A28
D29
D27
B33

B15
A21
D14
B25
A27
E30
E25
A33

A15
A20
E13
A25
A26
D30
E26
A32

CHANGED

F18
H20
E18
E20
D23
G24
D24
G23
D20
E22
J21
E21
G20
F22
H21
E17
E19
D21
E23
F19
E24
G21
G19
G25
G18
G22

H17
J16
J24
H23

H24
J25

H16

F15
G15

H13

J12

J13

GND

FBC_CMD<0>
FBC_CMD<1>
FBC_CMD<2>
FBC_CMD<3>
FBC_CMD<4>
FBC_CMD<5>
FBC_CMD<6>
FBC_CMD7
FBC_CMD<8>
FBC_CMD<9>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<12>
FBC_CMD<13>
FBC_CMD<14>
FBC_CMD<15>
FBC_CMD<16>
FBC_CMD<17>
FBC_CMD<18>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<21>
FBC_CMD<22>
FBC_CMD<23>
FBC_CMD<24>
FBC_CMD<25>
SNN_FBC_CMD26G17

FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*

SNN_FBC_RFU0
SNN_FBC_RFU1

SNN_FBC_DEBUG

SNN_FBC_REFCLK
SNN_FBC_REFCLK*

12MIL

FBC_PLLVDD

12MIL

FBCD_PLLAVDD

FBC_CMD<0..26>

0
1
2
3
4
5
6

TP513

8
9

10

NO STUFF

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

9<
9<
9<
9<

Unable to fit testpoint

.01UF

16V
10%
X7R
0402
COMMON

C877
.01UF

16V
10%
X7R
0402
COMMON

GND

GND

GND

.1UF

10V
10%
X5R
0402
COMMON

C890
.1UF

10V
10%
X5R
0402
COMMON

9<

144BGA CMD Mapping

ADDRCMD
A<3>

CMD0

A<0>

CMD1

A<2>

CMD2

A<1>

CMD3

A<3>

CMD4

A<4>

CMD5

A<5>

CMD6

CS1* *not used

CMD7

CS0*

CMD8

WE*

CMD9

BA0

CMD10

CKE

CMD11

RESET

CMD12

A<2>

CMD13

A<12>

CMD14

RAS*

CMD15

A<11>

CMD16

A<10

CMD17

BA1

CMD18

A<8>

CMD19

A<9>

CMD20

A<6>

CMD21

A<5>

CMD22

A<7>

CMD23

A<4>

CMD24

CAS*

CMD25

A<13> *not used

CMD26

180R@100MHz

LB504

COMMONBEAD_0603

C868C873C874

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

180R@100MHz

LB505

COMMON

BEAD_0603

C892

4.7UF

6.3V
10%
X5R
0603
COMMON

GNDGND

GND

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
MEMORY: GPU Partition C/D

A3V3

C850

4.7UF

6.3V
10%
X5R
0603
COMMON

NVVDD

C911

4.7UF

6.3V
10%
X5R
0603
COMMON

11<>
11<>
11<>

11<>

www.vinafix.vn

FBDD<63..0>
FBDDQM<7..0>
FBDDQS_RN<7..0>
FBDDQS_WP<7..0>

U9
GF-7800-GT-A2

BGA1148
CHANGED

FBD_CMD<0>

FBDD<0>

0

FBDD<1>

1

FBDD<2>

2

FBDD<3>

3

FBDD<4>

4

FBDD<5>

5

FBDD<6>

6

FBDD<7>

7

FBDD<8>

8

FBDD<9>

9

FBDD<10>

10

FBDD<11>

11

FBDD<12>

12

FBDD<13>

13

FBDD<14>

14

FBDD<15>

15

FBDD<16>

16

FBDD<17>

17

FBDD<18>

18

FBDD<19>

19

FBDD<20>

20

FBDD<21>

21

FBDD<22>

22

FBDD<23>

23

FBDD<24>

24

FBDD<25>

25

FBDD<26>

26

FBDD<27>

27

FBDD<28>

28

FBDD<29>

29

FBDD<30>

30

FBDD<31>

31

FBDD<32>

32

FBDD<33>

33

FBDD<34>

34

FBDD<35>

35

FBDD<36>

36

FBDD<37>

37

FBDD<38>

38

FBDD<39>

39

FBDD<40>

40

FBDD<41>

41

FBDD<42>

42

FBDD<43>

43

FBDD<44>

44

FBDD<45>

45

FBDD<46>

46

FBDD<47>

47

FBDD<48>

48

FBDD<49>

49

FBDD<50>

50

FBDD<51>

51

FBDD<52>

52

FBDD<53>

53

FBDD<54>

54

FBDD<55>

55

FBDD<56>

56

FBDD<57>

57

FBDD<58>

58

FBDD<59>

59

FBDD<60>

60

FBDD<61>

61

FBDD<62>

62

FBDD<63>

63

FBDDQM<0>

0

FBDDQM<1>

1

FBDDQM<2>

2

FBDDQM<3>

3

FBDDQM<4>

4

FBDDQM<5>

5

FBDDQM<6>

6

FBDDQM<7>

7

FBDDQS_RN<0>

0

FBDDQS_RN<1>

1

FBDDQS_RN<2>

2

FBDDQS_RN<3>

3

FBDDQS_RN<4>

4

FBDDQS_RN<5>

5

FBDDQS_RN<6>

6

FBDDQS_RN<7>

7

FBDDQS_WP<0>

0

FBDDQS_WP<1>

1

FBDDQS_WP<2>

2

FBDDQS_WP<3>

3

FBDDQS_WP<4>

4

FBDDQS_WP<5>

5

FBDDQS_WP<6>

6

FBDDQS_WP<7>

7

H3
J3
J1
J2
M3
K3
L3 F8
M1
H1
G3
G1
G2
F3
E1
D1
D2
P4
N7
M7
N5
P5
R7
T7
P7
C1
C5
C2
B4
A3
B3
C4
C3
A8
C6
C7
A7
C8
C9
A9
B9

E12

E9

F9
G10
D10
G12
F12
D11

F4

E4

D4

D5

D8

E7

D7

D9
B13
C11
A13
C13
A11
A10
B10
C10

K2

E3

N4

D3

B7
G11

F5
C12

K1

F2

R6

A4

B6
E10

E6
A12

L1

F1

R5

A5

A6
E11

D6
B12

M6
G5
L7
K5
J10
G8

G6
H6
F6
K8
L5
H4
G4
K9
L4
K4
K7
G7
J4
F7
J5
J6
H7
L8
J7
M5

L9
M9
J9
J8

H10
L11

N8

G9
H9

H11

J11

H12

GND

FBD_CMD<1>
FBD_CMD<2>
FBD_CMD<3>
FBD_CMD<4>
FBD_CMD<5>
FBD_CMD<6>
FBD_CMD7
FBD_CMD<8>
FBD_CMD<9>
FBD_CMD<10>
FBD_CMD<11>
FBD_CMD<12>
FBD_CMD<13>
FBD_CMD<14>
FBD_CMD<15>
FBD_CMD<16>
FBD_CMD<17>
FBD_CMD<18>
FBD_CMD<19>
FBD_CMD<20>
FBD_CMD<21>
FBD_CMD<22>
FBD_CMD<23>
FBD_CMD<24>
FBD_CMD<25>
SNN_FBD_CMD26

FBD_CLK0
FBD_CLK0*
FBD_CLK1
FBD_CLK1*

SNN_FBD_RFU0
SNN_FBD_RFU1

FBD_DEBUG

SNN_FBD_REFCLK
SNN_FBD_REFCLK*

12MIL

FBD_PLLVDD

FBCD_PLLAVDD

NO STUFF

GND

0
1
2
3
4
5
6

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

TP6

.01UF

16V
10%
X7R
0402
COMMON

FBD_CMD<0..26>

TP515

NO STUFF

11<
11<
11<
11<

180R@100MHz

LB506

C900C901 C933 C946
.1UF

10V
10%
X5R
0402
COMMON

GND

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

11<

COMMONBEAD_0603

A3V3

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

600-10317-0002-100

design
John Lam

4 OF 28

31-MAY-2005

CS0

INININININBIBIBIBI

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

IN

IN

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

INININ

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

BI

BIBIBI

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBA_CMD<13>
FBA_CMD<4>
FBA_CMD<5>
FBA_CMD<6>

FBA_CLK1
FBA_CLK1*

GND

FBA_CMD<15>
FBA_CMD<25>
FBA_CMD<9>
FBA_CMD<8>

FBA_CMD<1>
FBA_CMD<3>

FBA_CMD<21>
FBA_CMD<23>
FBA_CMD<19>
FBA_CMD<20>
FBA_CMD<17>
FBA_CMD<16>
FBA_CMD<14>

FBA_CMD<10>
FBA_CMD<18>

SNN_FBA1_BA2

FBA_CMD<11>

SNN_FBA1_NC1
SNN_FBA1_NC2
SNN_FBA1_NC3

FBA_CMD<12>

FBA_ZQ1

R561
243

1%
0603
COMMON

B10

C13
E13
D12
D13

C12
B12
B13

D13
E13
C13
D12

B10FBAD<55>

C12
B12
B13

GND

B9
B8
C9

C9
B9
B8

U13

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U14

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

5 FrameBuffer: Partition A 8Mx32 BGA144 DDR3

3> 5<

CKE

R87
10K

5%
0402
COMMON

GND

RESET

R86
10K

5%
0402
COMMON

GND

ZQ = 6x desired outputDDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

144BGA CMD Mapping

CMD ADDR

RAS*CMD15
CAS*

CMD25

WE*

CMD9

CKE

CMD11

RESET

CMD12

CS0*

CMD8

CS1**notused

CMD7

A<0>

CMD1

A<1>

CMD3

A<2>

CMD2
CMD0
CMD24
CMD22

CMD13
CMD4
CMD5
CMD6

CMD21
CMD23 A<7>
CMD19
CMD20
CMD17
CMD16
CMD14
CMD10
CMD18

A<3>
A<4>
A<5>

A<2>
A<3>
A<4>
A<5>

A<6>

A<8>
A<9>
A<10
A<11>
A<12>
BA0
BA1

Low Sub-Partition

Hi Sub-Partition

FBA_CMD<25..0>

Low Sub-Partition

3>

5<

3>

5<

5<>

5<>

5<>

5<>

3<>

15
25
9
8

1
3
2
0
24
22
21
23
19
20
17
16
14

10
18

11

12

3>

3<

3>

A-CS0-LOW-32bit

U13

DDR3BGA144
PACK_TYPE=BGA144
VERSION=BGA144
CHANGED

M10

L12
M12
N12
N13
N11FBA_CMD<19>
M11

N10

E12

GND

FBAD<63..0>

FBADQM<7..0>

FBADQS_RN<7..0>

FBADQS_WP<7..0>

M5
N6
N9

N2
N3
M3
L3

M4
N4

N5

L6

M7
N7
N8

E3

M8

M6

M9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VREF:
M2 - DATA
M13 - ADDR

FBADQM<0>

0

FBADQM<1>

1

FBADQM<2>

2

FBADQM<3>

3

FBADQM<4>

4

FBADQM<5>

5

FBADQM<6>

6

FBADQM<7>

7

FBADQS_RN<0>

0

FBADQS_RN<1>

1

FBADQS_RN<2>

2

FBADQS_RN<3>

3

FBADQS_RN<4>

4

FBADQS_RN<5>

5

FBADQS_RN<6>

6

FBADQS_RN<7>

7

FBADQS_WP<0>

0

FBADQS_WP<1>

1

FBADQS_WP<2>

2

FBADQS_WP<3>

3

FBADQS_WP<4>

4

FBADQS_WP<5>

5

FBADQS_WP<6>

6

FBADQS_WP<7>

7

FBA_CMD<15>
FBA_CMD<25>
FBA_CMD<9>
FBA_CMD<8>

CS0

FBA_CMD<1>

FBA_CMD<3>
FBA_CMD<2>
FBA_CMD<0>
FBA_CMD<24>
FBA_CMD<22>

FBA_CMD<21>

FBA_CMD<23>

FBA_CMD<20>

FBA_CMD<17>

FBA_CMD<16>

FBA_CMD<14>

FBA_CMD<10>

FBA_CMD<18>

SNN_FBA0_BA2

FBA_CMD<11>

FBA_CLK0
FBA_CLK0*

SNN_FBA0_NC1
SNN_FBA0_NC2
SNN_FBA0_NC3

FBA_CMD<12>

FBA_ZQ0

R566

243

1%

0603

COMMON

GND

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4L9
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

GND

12MIL

FBA_VREF_DATA0
FBA_VREF_ADDR0

VREF = 0.70 * FBVDDQ

DDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBAD<0>

0

FBAD<1>

1

FBAD<2>

2

FBAD<3>

3

FBAD<4>

4

FBAD<5>

5

FBAD<6>

6

FBAD<7>

7

FBADQM<0>
FBADQS_RN<0>
FBADQS_WP<0>

FBAD<32>

32

FBAD<33>

33

FBAD<34>

34

FBAD<35>

35

FBAD<36>

36

FBAD<37>

37

FBAD<38>

38

FBAD<39>

39

FBADQM<4>
FBADQS_RN<4>
FBADQS_WP<4>

FBA Partition

Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBA_CMD<25..0>

FBVDDQ

R89
511

1%

0402

COMMON

1.3K

1%

0402

CHANGED

GND

12MIL

B6
C6
B5
B7
C2
D3
E2
D2

C3
B3
B2

K12
L13
F13
J13
K13
F12
G12
G13

J12
H12
H13

2

0

24

22

13

4

5

6

R1

C84R88
.1UF

R2

10V
10%
X5R
0402
COMMON

U13

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U14

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

FBA_CMD<2>

FBA_CMD<0>

FBA_CMD<24>

FBA_CMD<22>

FBA_CMD<13>

FBA_CMD<4>

FBA_CMD<5>

FBA_CMD<6>

FBA_CLK0

FBA_CLK0*

FBA_CLK1

FBA_CLK1*

CHANGED

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

FBVDDQ

R572

511

1%

0402

COMMON

R571

1.3K

1%

0402

GND

FBAD<8>

8

FBAD<9>

9

FBAD<10>

10

FBAD<11>

11

FBAD<12>

12

FBAD<13>

13

FBAD<14>

14

FBAD<15>

15

FBADQM<1>

FBADQS_WP<1>

FBAD<40>

40

FBAD<41>

41

FBAD<42>

42

FBAD<43>

43

FBAD<44> L2

44

FBAD<45>

45

FBAD<46>

46

FBAD<47>

47

FBADQM<5>
FBADQS_RN<5>
FBADQS_WP<5>

R573

121

0402

1%

R575

121

0402

1%

R582

121

0402

1%

R579

121

0402

1%

R570

121

0402

1%

R580

121

0402

1%

R557

121

0402

1%

R556

121

0402

1%

R565

60.4

0402

1%

R564

60.4

0402

1%

R568

60.4

0402

1%

R567

60.4

0402

1%

ZQ = 6x desired output

DDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

R1

C583
.1UF

R2

10V
10%
X5R
0402
COMMON

FBVDDQ

G2
G3
F2
F3
J2
K2
K3
L2

J3
H3FBADQS_RN<1>
H2

J2
F3
F2
G2

K2
K3
G3

J3
H3
H2

FBA_CMD<25..0>

Hi Sub-Partition

3>

5<

3>

5<

U13

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U14

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition A 8Mx32 BGA144 DDR3

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

15
25
9
8

1
3
13
4
5
6
21
23
19
20
17
16
14

10
18

11

FBAD<16>
FBAD<17>
FBAD<18>
FBAD<19>
FBAD<20>
FBAD<21>
FBAD<22>
FBAD<23>

FBADQM<2>
FBADQS_RN<2>
FBADQS_WP<2>

FBAD<48>
FBAD<49>
FBAD<50>
FBAD<51>
FBAD<52>
FBAD<53>
FBAD<54>

FBADQM<6>
FBADQS_RN<6>
FBADQS_WP<6>

www.vinafix.vn

A-CS0-HI-32bit

U14

DDR3BGA144
PACK_TYPE=BGA144
VERSION=BGA144
CHANGED

M5
N6
N9

M10

N2
N3
M3

L3
L12
M12
N12
N13
N11
M11

M4

N4

L9

N5
N10

L6

M7

N7

N8

E3
E12

M8

M6

M9

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

FBAD<24>
FBAD<25>
FBAD<26>
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30>
FBAD<31>

FBADQM<3>
FBADQS_RN<3>
FBADQS_WP<3>

FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<60>
FBAD<61>
FBAD<62>
FBAD<63>

FBADQM<7>
FBADQS_RN<7>
FBADQS_WP<7>

NET RULES

NET

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

DDR3:

G13
F12
F13
G12
K13
K12
L13
J13

J12
H12
H13

GND

12MIL

FBA_VREF_DATA1
FBA_VREF_ADDR1

VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

U13

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U14

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

D3
C2
E2
D2
B5
B7
B6
C6

C3
B3
B2

3>

5<

3>

5<

3>

5<

3>

5<

3>

5<

3<>

5<>

3>

5<>

3<

5<>

3>

5<>

FBVDDQ

R562

511

R1

1%

0402

COMMON

R563 C580

1.3K

R2

1%

0402

CHANGED

GND

12MIL

FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
FBA_CMD<25..0>

FBAD<63..0>
FBADQM<7..0>

FBADQS_RN<7..0>
FBADQS_WP<7..0>

.1UF

10V
10%
X5R
0402
COMMON

FBVDDQ

R552

511

1%

0402

COMMON

R549

1.3K

1%

0402

CHANGED

NVVDD

Reference Plane Transition Cap

C640
22UF

6.3V
20%
X5R
0805

R1

R2

GND

C1074
120PF

50V
5%
C0G
0402
COMMONCOMMON

100DIFF
100DIFF
100DIFF
100DIFF
40OHM

40OHM
40OHM

40OHM
40OHM

C562
.1UF

10V
10%
X5R
0402
COMMON

C1006
120PF

50V
5%
C0G
0402
COMMON

GND

600-10317-0002-100

design
John Lam

DIFFPAIRCRITICALIMPEDANCE

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

5 OF 28

31-MAY-2005

1
1
1
1
1

1
1

1
1

6 FrameBuffer: Partition A Decoupling

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBVDDQ

FBVDDQ

Decoupling for FBA 0..31 Decoupling for FBA 32..63

C556

C564

1UF

6.3V
10%
X5R
0603
COMMON

C685

1UF

6.3V
10%
X5R
0603
COMMON

C601

1UF

6.3V
10%
X5R
0603
COMMON

C680

1UF

6.3V
10%
X5R
0603
COMMON

C557

1UF

6.3V
10%
X5R
0603
COMMON

C578 C586

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C677

C608

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C602

C645

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C674

C667

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C567

C572

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

.01UF

16V
10%
X7R
0402
COMMON

C630

.01UF

16V
10%
X7R
0402
COMMON

C603

.01UF

16V
10%
X7R
0402
COMMON

C623

.01UF

16V
10%
X7R
0402
COMMON

C649

.01UF

16V
10%
X7R
0402
COMMON

C591 C594

.01UF .01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C632

C589

.01UF

.01UF

16V

16V

10%

10%
X7RX7R

0402

0402

COMMON

COMMON

C609

C611

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C625

C641

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C650

C655

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C617

.01UF

16V
10%
X7R
0402
COMMON

C642

.01UF

16V
10%
X7R
0402
COMMON

C607

120PF

50V
5%
C0G
0402
COMMON

C628

120PF

50V
5%
C0G
0402
COMMON

C596

120PF

50V
5%
C0G
0402
COMMON

C656

120PF

50V
5%
C0G
0402
COMMON

GND

GND

GND

GND

C553 C565 C571

1UF .1UF .1UF

6.3V

10V
10%
X5R
0402
COMMON

C566

10V
10%

0402
COMMON

C579

.1UF

10V
10%
X5R
0402
COMMON

C605

.1UF

10V
10%
X5R
0402
COMMON

C675

.1UF

10V
10%
X5R
0402
COMMON

10V
10%
X5R
0402
COMMON

C646

.1UF

10V
10%
X5R
0402
COMMON

C668

.1UF

10V
10%
X5R
0402
COMMON

C585

.1UF

10V
10%
X5R
0402
COMMON

C587

.1UF

10V
10%
X5R
0402
COMMON

10%
X5R
0603
COMMON

C563

1UF .1UF

6.3V
10%
X5R X5R
0603
COMMON

C568

1UF

6.3V
10%
X5R
0603
COMMON

C606

1UF

6.3V
10%
X5R
0603
COMMON

C681

1UF

6.3V
10%
X5R
0603
COMMON

C588 C593 C592

.01UF .01UF.01UF

16V

16V
10%
X7R
0402
COMMON

C633

.01UF

16V
10%
X7R
0402
COMMON

C610

.01UF

16V
10%
X7R
0402
COMMON

C626

.01UF

16V
10%
X7R
0402
COMMON

C653

.01UF

16V
10%
X7R
0402
COMMON

16V
10%
X7R
0402
COMMON

C618

.01UF

16V
10%
X7R
0402
COMMON

C643

.01UF

16V
10%
X7R
0402
COMMON

C654

.01UF

16V
10%
X7R
0402
COMMON

10%
X7R
0402
COMMON

C631

.01UF

16V
10%
X7R
0402
COMMON

C604

.01UF

16V
10%
X7R
0402
COMMON

C612

.01UF

16V
10%
X7R
0402
COMMON

C652

.01UF

16V
10%
X7R
0402
COMMON

C619

.01UF

16V
10%
X7R
0402
COMMON

C644

.01UF

16V
10%
X7R
0402
COMMON

C590

120PF

50V
5%
C0G
0402
COMMON

C629

120PF

50V
5%
C0G
0402
COMMON

C651

120PF

50V
5%
C0G
0402
COMMON

C597

120PF

50V
5%
C0G
0402
COMMON

GND

GND

GND

GND

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition A Decoupling

www.vinafix.vn

GND

600-10317-0002-100

design
John Lam

6 OF 28

31-MAY-2005

CS0

INININININBIBIBIBI

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

IN

IN

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

INININ

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

BI

BIBIBI

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBB_CMD<13>
FBB_CMD<4>
FBB_CMD<5>
FBB_CMD<6>

FBB_CLK1
FBB_CLK1*

GND

FBB_CMD<15>
FBB_CMD<25>
FBB_CMD<9>
FBB_CMD<8>

FBB_CMD<3>

FBB_CMD<21>
FBB_CMD<23>
FBB_CMD<19>
FBB_CMD<20>
FBB_CMD<17>
FBB_CMD<16>
FBB_CMD<14>

FBB_CMD<10>
FBB_CMD<18>

SNN_FBB1_BA2

FBB_CMD<11>

SNN_FBB1_NC1
SNN_FBB1_NC2
SNN_FBB1_NC3

FBB_CMD<12>

FBB_ZQ1

R589
243

1%
0603
COMMON

D12
B10

C13
D13
E13

C12
B12
B13

C13
E13
D13
D12

B10FBBD<53>

C12
B12
B13

GND

C9
B9

B8

C9

B9
B8

U11

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U12

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

7 FrameBuffer: Partition B 8Mx32 BGA144 DDR3

3> 7<

CKE

R85
10K

5%
0402
COMMON

GND

RESET

R84
10K

5%
0402
COMMON

GND

ZQ = 6x desired outputDDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

144BGA CMD Mapping

ADDRCMD

CMD15 RAS*

CAS*

CMD25

WE*

CMD9

CKE

CMD11

RESET

CMD12

CS0*

CMD8

CS1* *notused

CMD7

A<0>

CMD1

A<1>

CMD3

A<2>

CMD2
CMD0
CMD24
CMD22

CMD13
CMD4
CMD5
CMD6

CMD21

CMD19
CMD20
CMD17
CMD16
CMD14
CMD10
CMD18

A<3>
A<4>
A<5>

A<2>

A<4>
A<5>

A<6>
A<7>CMD23
A<8>
A<9>
A<10
A<11>
A<12>
BA0
BA1

Low Sub-Partition

Hi Sub-Partition

FBB_CMD<25..0>

Low Sub-Partition

3>

7<

3>

7<

7<>

7<>

7<>

7<>

3<>

15
25
9
8

1
3
2
0
24
22
21
23
19
20
17
16
14

10
18

11

12

3>

3<

3>

A-CS0-LOW-32bit

U11

DDR3BGA144
BGA144
VERSION=BGA144
CHANGED

M10

L12
M12
N12
N13
N11
M11

N10

E12

GND

FBBD<63..0>

FBBDQM<7..0>

FBBDQS_RN<7..0>

FBBDQS_WP<7..0>

M5
N6
N9

N2
N3
M3
L3

M4
N4

N5

L6

M7
N7
N8

E3

M8

M6

M9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VREF:

M13 - ADDR

FBBDQM<0>

0

FBBDQM<1>

1

FBBDQM<2>

2

FBBDQM<3>

3

FBBDQM<4>

4

FBBDQM<5>

5

FBBDQM<6>

6

FBBDQM<7>

7

FBBDQS_RN<0>

0

FBBDQS_RN<1>

1

FBBDQS_RN<2>

2

FBBDQS_RN<3>

3

FBBDQS_RN<4>

4

FBBDQS_RN<5>

5

FBBDQS_RN<6>

6

FBBDQS_RN<7>

7

FBBDQS_WP<0>

0

FBBDQS_WP<1>

1

FBBDQS_WP<2>

2

FBBDQS_WP<3>

3

FBBDQS_WP<4>

4

FBBDQS_WP<5>

5

FBBDQS_WP<6>

6

FBBDQS_WP<7>

7

FBB_CMD<15>
FBB_CMD<25>
FBB_CMD<9>
FBB_CMD<8>

CS0

FBB_CMD<1>

FBB_CMD<3>
FBB_CMD<2>
FBB_CMD<0>
FBB_CMD<24>
FBB_CMD<22>

FBB_CMD<21>

FBB_CMD<23>

FBB_CMD<19>

FBB_CMD<20>

FBB_CMD<17>

FBB_CMD<16>

FBB_CMD<14>

FBB_CMD<10>

FBB_CMD<18>

SNN_FBB0_BA2

FBB_CMD<11>

FBB_CLK0
FBB_CLK0*

SNN_FBB0_NC1
SNN_FBB0_NC2
SNN_FBB0_NC3

FBB_CMD<12>

FBB_ZQ0

R600

243

1%

0603

COMMON

GND

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4L9
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

GND

12MIL

FBB_VREF_DATA0
FBB_VREF_ADDR0

VREF = 0.70 * FBVDDQ

DDR3:M2 - DATA

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBBD<0>

0

FBBD<1>

1

FBBD<2>

2

FBBD<3>

3

FBBD<4>

4

FBBD<5>

5

FBBD<6>

6

FBBD<7>

7

FBBDQM<0>
FBBDQS_RN<0>
FBBDQS_WP<0>

FBBD<32>

32

FBBD<33>

33

FBBD<34>

34

FBBD<35>

35

FBBD<36>

36

FBBD<37>

37

FBBD<38>

38

FBBD<39>

39

FBBDQM<4>
FBBDQS_RN<4>
FBBDQS_WP<4>

FBB Partition

Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBB_CMD<25..0>

FBVDDQ

R82
511

1%

0402

COMMON

1.3K

1%

0402

CHANGED

GND

12MIL

B6
B7
C6
C2
D3
B5
D2
E2

C3
B3
B2

G12
J13
K13
K12
G13
L13
F13
F12

J12
H12
H13

2

0

24

22

13

4

5

6

R1

C82R83
.1UF

R2

10V
10%
X5R
0402
COMMON

U11

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U12

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

FBB_CMD<2>

FBB_CMD<0>

FBB_CMD<24>

FBB_CMD<22>

FBB_CMD<13>

FBB_CMD<4>

FBB_CMD<5>

FBB_CMD<6>

FBB_CLK0

FBB_CLK0*

FBB_CLK1

FBB_CLK1*

CHANGED

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

FBVDDQ

R603

511

1%

0402

COMMON

R601

1.3K

1%

0402

GND

FBBD<8>

8

FBBD<9>

9

FBBD<10>

10

FBBD<11>

11

FBBD<12>

12

FBBD<13>

13

FBBD<14>

14

FBBD<15>

15

FBBDQM<1>

FBBDQS_WP<1>

FBBD<40>

40

FBBD<41>

41

FBBD<42>

42

FBBD<43>

43

FBBD<44> G3

44

FBBD<45>

45

FBBD<46>

46

FBBD<47>

47

FBBDQM<5>

FBBDQS_WP<5>

R596

121

0402

1%

R597

121

0402

1%

R604

121

0402

1%

R602

121

0402

1%

R581

121

0402

1%

R576

121

0402

1%

R590

121

0402

1%

R592

121

0402

1%

R598

60.4

0402

1%

R599

60.4

0402

1%

R583

60.4

0402

1%

R587

60.4

0402

1%

ZQ = 6x desired output

DDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

R1

C687
.1UF

R2

10V
10%
X5R
0402
COMMON

FBVDDQ

F3
J2
F2
G2
K3
G3
L2
K2

J3
H3FBBDQS_RN<1>
H2

K3
F2
F3
J2

K2
L2
G2

J3
H3FBBDQS_RN<5>
H2

FBB_CMD<25..0>

Hi Sub-Partition

3>

7<

3>

7<

U11

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U12

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition B 8Mx32 BGA144 DDR3

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

15
25
9
8

1
3
13
4
5
6
21
23
19
20
17
16
14

10
18

11

FBBD<16>
FBBD<17>
FBBD<18>
FBBD<19>
FBBD<20>
FBBD<21>
FBBD<22>
FBBD<23>

FBBDQM<2>
FBBDQS_RN<2>
FBBDQS_WP<2>

FBBD<48>
FBBD<49>
FBBD<50>
FBBD<51>
FBBD<52>

FBBD<54>
FBBD<55>

FBBDQM<6>
FBBDQS_RN<6>
FBBDQS_WP<6>

www.vinafix.vn

A-CS0-HI-32bit

U12

DDR3BGA144
PACK_TYPE=BGA144
VERSION=BGA144
CHANGED

M5
N6
N9

M10

N2FBB_CMD<1>
N3
M3

L3
L12
M12
N12
N13
N11
M11

M4

N4

L9

N5
N10

L6

M7

N7

N8

E3
E12

M8

M6

M9

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

FBBD<24>
FBBD<25>
FBBD<26>
FBBD<27>
FBBD<28>
FBBD<29>
FBBD<30>
FBBD<31>

FBBDQM<3>
FBBDQS_RN<3>
FBBDQS_WP<3>

FBBD<56>
FBBD<57>
FBBD<58>
FBBD<59>
FBBD<60>
FBBD<61>
FBBD<62>
FBBD<63>

FBBDQM<7>
FBBDQS_RN<7>
FBBDQS_WP<7>

NET RULES

NET

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

DDR3:

F13
F12
G12
G13
L13
K13
K12
J13

J12
H12
H13

GND

12MIL

FBB_VREF_DATA1
FBB_VREF_ADDR1

VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

U11

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U12

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

E2
D3
D2
C2
C6
B6
B5
B7

C3
B3
B2

12MIL

R574

511

0402

COMMON

R558

1.3K

0402

CHANGED

7<>

FBVDDQ

1%

1%

GND

7<
7<
7<
7<
7<

7<>

7<>
7<>

3>
3>
3>
3>
3>

3<>

3>

3<
3>

R1

R2

FBB_CLK0
FBB_CLK0*
FBB_CLK1
FBB_CLK1*
FBB_CMD<25..0>

FBBD<63..0>
FBBDQM<7..0>

FBBDQS_RN<7..0>
FBBDQS_WP<7..0>

C574
.1UF

10V
10%
X5R
0402
COMMON

FBVDDQ

R591

511

1%

0402

COMMON

R584

1.3K

1%

0402

CHANGED

NVVDD

Reference Plane Transition Cap

C575
22UF

6.3V
20%
X5R
0805

R1

R2

GND

C648
120PF

50V
5%
C0G
0402
COMMONCOMMON

100DIFF
100DIFF
100DIFF
100DIFF
40OHM

40OHM
40OHM

40OHM
40OHM

C599
.1UF

10V
10%
X5R
0402
COMMON

C963
120PF

50V
5%
C0G
0402
COMMON

GND

600-10317-0002-100

design
John Lam

DIFFPAIRCRITICALIMPEDANCE

FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1

7 OF 28

31-MAY-2005

1
1
1
1
1

1
1

1
1

8 FrameBuffer: Partition B Decoupling

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBVDDQ

Decoupling for FBB 0..31

C659

C661

1UF

6.3V
10%
X5R
0603
COMMON

C672

1UF

6.3V
10%
X5R
0603
COMMON

C700

1UF

6.3V
10%
X5R
0603
COMMON

C711

1UF

6.3V
10%
X5R
0603
COMMON

C710

1UF

6.3V
10%
X5R
0603
COMMON

C683 C676

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C678

C689

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C664

C688

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C701

C708

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C709

C695

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C679 C682 C684

.01UF

.01UF .01UF .01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C686

C690

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R X7R

0402

0402

COMMON

COMMON

C692

C693

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C698

C699

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C703

C705

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

16V
10%
X7R
0402
COMMON

C691

.01UF

16V
10%

0402
COMMON

C697

.01UF

16V
10%
X7R
0402
COMMON

C702

.01UF

16V
10%
X7R
0402
COMMON

C706

.01UF

16V
10%
X7R
0402
COMMON

16V
10%
X7R
0402
COMMON

C704

.01UF

16V
10%
X7R
0402
COMMON

C670

120PF

50V
5%
C0G
0402
COMMON

C696

120PF

50V
5%
C0G
0402
COMMON

C694

120PF

50V
5%
C0G
0402
COMMON

C707

120PF

50V
5%
C0G
0402
COMMON

GND

GND

GND

GND

FBVDDQ

Decoupling for FBB 32..63

C613 C637 C658

1UF .1UF .1UF

6.3V
10%
X5R
0603
COMMON

C576

1UF

6.3V
10%
X5R X5R
0603
COMMON

C569

1UF

6.3V
10%
X5R
0603
COMMON

C581

1UF

6.3V
10%
X5R
0603
COMMON

C669

1UF

6.3V
10%
X5R
0603
COMMON

10V
10%
X5R
0402
COMMON

C582

.1UF

10V
10%

0402
COMMON

C573

.1UF

10V
10%
X5R
0402
COMMON

C584

.1UF

10V
10%
X5R
0402
COMMON

C665

.1UF

10V
10%
X5R
0402
COMMON

10V
10%
X5R
0402
COMMON

C673

.1UF

10V
10%
X5R
0402
COMMON

C577

.1UF

10V
10%
X5R
0402
COMMON

C570

.1UF

10V
10%
X5R
0402
COMMON

C662

.1UF

10V
10%
X5R
0402
COMMON

C598 C616 C614

.01UF .01UF

16V
10%
X7R
0402
COMMON

C615

.01UF

16V
10%
X7R
0402
COMMON

C624

.01UF

16V
10%
X7R
0402
COMMON

C636

.01UF

16V
10%
X7R
0402
COMMON

C663

.01UF

16V
10%
X7R
0402
COMMON

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C600

C620

.01UF

.01UF

16V

16V

10%

10%
X7R X7R
0402 0402
COMMON

COMMON

C634

.01UF

16V
10%
X7R
0402
COMMON

C638

C647

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C660

C657

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C622 C595

120PF.01UF

16V

50V

10%

5%

X7R

C0G

0402

0402

COMMON

COMMON

C627

120PF

50V
5%
C0G
0402
COMMON

C635

120PF

50V
5%
C0G
0402
COMMON

C639

C666

.01UF

120PF

16V

50V

10%

5%

X7R

C0G

0402

0402

COMMON

COMMON

GND

GND

GND

GND

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition B Decoupling

www.vinafix.vn

GND

600-10317-0002-100

design
John Lam

8 OF 28

31-MAY-2005

CS0

INININININBIBIBIBI

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

IN

IN

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

INININ

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

BI

BIBIBI

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBC_CMD<13>
FBC_CMD<4>
FBC_CMD<5>
FBC_CMD<6>

FBC_CLK1
FBC_CLK1*

GND

FBC_CMD<15>
FBC_CMD<25>
FBC_CMD<9>
FBC_CMD<8>

FBC_CMD<1>
FBC_CMD<3>

FBC_CMD<21>
FBC_CMD<23>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<17>
FBC_CMD<16>
FBC_CMD<14>

FBC_CMD<10>
FBC_CMD<18>

SNN_FBC1_BA2

FBC_CMD<11>

SNN_FBC1_NC1
SNN_FBC1_NC2
SNN_FBC1_NC3

FBC_CMD<12>

FBC_ZQ1

R621
243

1%
0603
COMMON

B10
C13

D12
D13

E13

C12
B12
B13

G12
L13
K13
J13FBCD<51>
G13
F13
K12
F12

J12
H12
H13

GND

C9
B8

B9

U8

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U10

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

9 FrameBuffer: Partition C 8Mx32 BGA144 DDR3

4> 9<

CKE

R79
10K

5%
0402
COMMON

GND

RESET

R627
10K

5%
0402
COMMON

GND

ZQ = 6x desired outputDDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

144BGA CMD Mapping

ADDRCMD
RAS*CMD15
CAS*

CMD25

WE*

CMD9

CKE

CMD11

RESET

CMD12

CS0*

CMD8

CS1* *notused

CMD7

A<0>

CMD1

A<1>

CMD3

A<2>

CMD2
CMD0
CMD24
CMD22

CMD13
CMD4
CMD5
CMD6

CMD21

CMD20
CMD17
CMD16
CMD14
CMD10
CMD18

A<3>
A<4>
A<5>

A<2>
A<3>
A<4>
A<5>

A<6>
A<7>CMD23
A<8>CMD19
A<9>
A<10
A<11>
A<12>
BA0
BA1

Low Sub-Partition

Hi Sub-Partition

FBC_CMD<25..0>

Low Sub-Partition

4>

9<

4>

9<

9<>

9<>

9<>

9<>

4<>

15
25
9
8

1
3
2
0
24
22
21
23
19
20
17
16
14

10
18

11

12

4>

4<

4>

A-CS0-LOW-32bit

U8

DDR3BGA144
BGA144
VERSION=BGA144
CHANGED

M10

L12
M12
N12
N13
N11
M11

N10

E12

GND

FBCD<63..0>

FBCDQM<7..0>

FBCDQS_RN<7..0>

FBCDQS_WP<7..0>

M5
N6
N9

N2
N3
M3
L3

M4
N4

N5

L6

M7
N7
N8

E3

M8

M6

M9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VREF:
M2 - DATA
M13 - ADDR

FBCDQM<0>

0

FBCDQM<1>

1

FBCDQM<2>

2

FBCDQM<3>

3

FBCDQM<4>

4

FBCDQM<5>

5

FBCDQM<6>

6

FBCDQM<7>

7

FBCDQS_RN<0>

0

FBCDQS_RN<1>

1

FBCDQS_RN<2>

2

FBCDQS_RN<3>

3

FBCDQS_RN<4>

4

FBCDQS_RN<5>

5

FBCDQS_RN<6>

6

FBCDQS_RN<7>

7

FBCDQS_WP<0>

0

FBCDQS_WP<1>

1

FBCDQS_WP<2>

2

FBCDQS_WP<3>

3

FBCDQS_WP<4>

4

FBCDQS_WP<5>

5

FBCDQS_WP<6>

6

FBCDQS_WP<7>

7

FBC_CMD<15>
FBC_CMD<25>
FBC_CMD<9>
FBC_CMD<8>

CS0

FBC_CMD<1>

FBC_CMD<3>
FBC_CMD<2>
FBC_CMD<0>
FBC_CMD<24>
FBC_CMD<22>

FBC_CMD<21>

FBC_CMD<23>

FBC_CMD<19>

FBC_CMD<20>

FBC_CMD<17>

FBC_CMD<16>

FBC_CMD<14>

FBC_CMD<10>

FBC_CMD<18>

SNN_FBC0_BA2

FBC_CMD<11>

FBC_CLK0
FBC_CLK0*

SNN_FBC0_NC1
SNN_FBC0_NC2
SNN_FBC0_NC3

FBC_CMD<12>

FBC_ZQ0

R644

243

1%

0603

COMMON

GND

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4L9
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

GND

12MIL

FBC_VREF_DATA0
FBC_VREF_ADDR0

VREF = 0.70 * FBVDDQ

DDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBCD<0>

0

FBCD<1>

1

FBCD<2>

2

FBCD<3>

3

FBCD<4>

4

FBCD<5>

5

FBCD<6>

6

FBCD<7>

7

FBCDQM<0>
FBCDQS_RN<0>
FBCDQS_WP<0>

FBCD<32>

32

FBCD<33>

33

FBCD<34>

34

FBCD<35>

35

FBCD<36>

36

FBCD<37>

37

FBCD<38>

38

FBCD<39>

39

FBCDQM<4>
FBCDQS_RN<4>
FBCDQS_WP<4>

FBC Partition

Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBC_CMD<25..0>

FBVDDQ

R77
511

1%

0402

COMMON

1.3K

1%

0402

CHANGED

GND

12MIL

F12
F13
G12
G13
K13
J13
K12
L13

J12
H12
H13

B10
E13
D13
D12
C13

C9
B8
B9

C12
B12
B13

2

0

24

22

13

4

5

6

R1

C75R78
.1UF

R2

10V
10%
X5R
0402
COMMON

U8

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U10

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

FBC_CMD<2>

FBC_CMD<0>

FBC_CMD<24>

FBC_CMD<22>

FBC_CMD<13>

FBC_CMD<4>

FBC_CMD<5>

FBC_CMD<6>

FBC_CLK0

FBC_CLK0*

FBC_CLK1

FBC_CLK1*

CHANGED

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

FBVDDQ

R663

511

1%

0402

COMMON

R655

1.3K

1%

0402

GND

FBCD<8>

8

FBCD<9>

9

FBCD<10>

10

FBCD<11>

11

FBCD<12>

12

FBCD<13>

13

FBCD<14>

14

FBCD<15>

15

FBCDQM<1>

FBCDQS_WP<1>

FBCD<40>

40

FBCD<41>

41

FBCD<42>

42

FBCD<43>

43

FBCD<44> L2

44

FBCD<45>

45

FBCD<46>

46

FBCD<47>

47

FBCDQM<5>

FBCDQS_WP<5>

R630

121

0402

1%

R632

121

0402

1%

R660

121

0402

1%

R659

121

0402

1%

R612

121

0402

1%

R607

121

0402

1%

R622

121

0402

1%

R623

121

0402

1%

R636

60.4

0402

1%

R639

60.4

0402

1%

R617

60.4

0402

1%

R620

60.4

0402

1%

ZQ = 6x desired output

DDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

R1

C947
.1UF

R2

10V
10%
X5R
0402
COMMON

FBVDDQ

B7
B6
C6
B5
D3
C2
E2
D2

C3
B3FBCDQS_RN<1>
B2

G3
F2
F3
K2

K3
J2
G2

J3
H3FBCDQS_RN<5>
H2

FBC_CMD<25..0>

Hi Sub-Partition

4>

9<

4>

9<

U8

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U10

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition C 8Mx32 BGA144 DDR3

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

15
25
9
8

1
3
13
4
5
6
21
23
19
20
17
16
14

10
18

11

FBCD<16>
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>

FBCDQM<2>
FBCDQS_RN<2>
FBCDQS_WP<2>

FBCD<48>
FBCD<49>
FBCD<50>

FBCD<52>
FBCD<53>
FBCD<54>
FBCD<55>

FBCDQM<6>
FBCDQS_RN<6>
FBCDQS_WP<6>

www.vinafix.vn

A-CS0-HI-32bit

U10

DDR3BGA144
PACK_TYPE=BGA144
VERSION=BGA144
CHANGED

M5
N6
N9

M10

N2
N3
M3

L3
L12
M12
N12
N13
N11
M11

M4

N4

L9

N5
N10

L6

M7

N7

N8

E3
E12

M8

M6

M9

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

FBCD<24>
FBCD<25>
FBCD<26>
FBCD<27>
FBCD<28>
FBCD<29>
FBCD<30>
FBCD<31>

FBCDQM<3>
FBCDQS_RN<3>
FBCDQS_WP<3>

FBCD<56>
FBCD<57>
FBCD<58>
FBCD<59>
FBCD<60>
FBCD<61>
FBCD<62>
FBCD<63>

FBCDQM<7>
FBCDQS_RN<7>
FBCDQS_WP<7>

NET RULES

IMPEDANCENET

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

GND

12MIL

FBC_VREF_DATA1

VREF = 0.70 * FBVDDQDDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

U8

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

F3
F2
L2
G3
G2
K2
K3
J2

J3
H3
H2

U10

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

D2
C2
D3
E2
B5
B6
B7
C6

C3
B3
B2

12MILFBC_VREF_ADDR1

R609

511

0402

COMMON

R611

1.3K

0402

CHANGED

9<>

FBVDDQ

1%

1%

GND

9<
9<
9<
9<
9<

9<>

9<>
9<>

4>
4>
4>
4>
4>

4<>

4>

4<
4>

R1

R2

FBC_CLK0
FBC_CLK0*
FBC_CLK1

FBC_CMD<25..0>

FBCD<63..0>
FBCDQM<7..0>

FBCDQS_RN<7..0>
FBCDQS_WP<7..0>

C745
.1UF

10V
10%
X5R
0402

R81

COMMON

511

0402

COMMON

R80

1.3K

0402

CHANGED

NVVDD

Reference Plane Transition Cap

C728
22UF

6.3V
20%
X5R
0805

FBVDDQ

1%

1%

R1

R2

GND

C671
120PF

50V
5%
C0G
0402
COMMONCOMMON

100DIFF
100DIFF
100DIFF
100DIFFFBC_CLK1*
40OHM

40OHM
40OHM

40OHM
40OHM

C81
.1UF

10V
10%
X5R
0402
COMMON

C621
120PF

50V
5%
C0G
0402
COMMON

GND

600-10317-0002-100

design
John Lam

DIFFPAIRCRITICAL

FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1

9 OF 28

31-MAY-2005

1
1
1
1
1

1
1

1
1

10 FrameBuffer: Partition C Decoupling

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBVDDQ

FBVDDQ

Decoupling for FBC 0..31 Decoupling for FBC 32..63

C905

C906

1UF

6.3V
10%
X5R
0603
COMMON

C952

1UF

6.3V
10%
X5R
0603
COMMON

C969

1UF

6.3V
10%
X5R
0603
COMMON

C928

1UF

6.3V
10%
X5R
0603
COMMON

C849

1UF

6.3V
10%
X5R
0603
COMMON

C865 C904

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C953

C954

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C968

C866

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C927

C926

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C848

C864

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

.01UF

16V
10%
X7R
0402
COMMON

C897

.01UF

16V
10%
X7R
0402
COMMON

C941

.01UF

16V
10%
X7R
0402
COMMON

C923

.01UF

16V
10%
X7R
0402
COMMON

C925

.01UF

16V
10%
X7R
0402
COMMON

C914 C930

.01UF .01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C898

C899

.01UF

.01UF

16V

16V

10%

10%
X7R X7R
0402

0402
COMMON

COMMON

C942

C943

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C924

C912

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C915

C909

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C893

120PF

50V
5%
C0G
0402
COMMON

C940

120PF

50V
5%
C0G
0402
COMMON

C936

C957

.01UF

120PF

16V

50V

10%

5%

X7R

C0G

0402

0402

COMMON COMMON

C895

C888

.01UF

120PF

16V

50V

10%

5%

X7R

C0G

0402

0402

COMMON

COMMON

GND

GND

GND

GND

C775 C774 C820

.1UF1UF .1UF

6.3V

10V
10%
X5R
0402
COMMON

C736

.1UF

10V
10%

0402
COMMON

C726

.1UF

10V
10%
X5R
0402
COMMON

C761

.1UF

10V
10%
X5R
0402
COMMON

C717

.1UF

10V
10%
X5R
0402
COMMON

10V
10%
X5R
0402
COMMON

C821

.1UF

10V
10%
X5R
0402
COMMON

C732

.1UF

10V
10%
X5R
0402
COMMON

C760

.1UF

10V
10%
X5R
0402
COMMON

C822

.1UF

10V
10%
X5R
0402
COMMON

10%
X5R
0603
COMMON

C735

1UF

6.3V
10%
X5R X5R
0603
COMMON

C727

1UF

6.3V
10%
X5R
0603
COMMON

C762

1UF

6.3V
10%
X5R
0603
COMMON

C718

1UF

6.3V
10%
X5R
0603
COMMON

C755 C773 C787

.01UF .01UF

16V
10%
X7R
0402
COMMON

C740

.01UF

16V
10%
X7R
0402
COMMON

C772

.01UF

16V
10%
X7R
0402
COMMON

C790

.01UF

16V
10%
X7R
0402
COMMON

C794

.01UF

16V
10%
X7R
0402
COMMON

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C739

C738

.01UF

.01UF

16V

16V

10%

10%
X7RX7R

0402

0402

COMMON COMMON

C765

C764

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C791

C792

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C781

C771

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C759

.01UF

16V
10%
X7R
0402
COMMON

C737

120PF

50V
5%
C0G
0402
COMMON

C800

120PF

50V
5%
C0G
0402
COMMON

C801

120PF

50V
5%
C0G
0402
COMMON

C747

120PF

50V
5%
C0G
0402
COMMON

GND

GND

GND

GND

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition C Decoupling

www.vinafix.vn

GND

600-10317-0002-100

design
John Lam

10 OF 28

31-MAY-2005

CS0

INININININBIBIBIBI

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

IN

IN

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

INININ

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

BI

BIBIBI

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBD_CMD<13>
FBD_CMD<4>
FBD_CMD<5>
FBD_CMD<6>

FBD_CLK1
FBD_CLK1*

GND

FBD_CMD<15>
FBD_CMD<25>
FBD_CMD<9>
FBD_CMD<8>

FBD_CMD<1>
FBD_CMD<3>

FBD_CMD<21>
FBD_CMD<23>
FBD_CMD<19>
FBD_CMD<20>
FBD_CMD<17>
FBD_CMD<16>
FBD_CMD<14>

FBD_CMD<10>
FBD_CMD<18>

SNN_FBD1_BA2

FBD_CMD<11>

SNN_FBD1_NC1
SNN_FBD1_NC2
SNN_FBD1_NC3

FBD_CMD<12>

FBD_ZQ1

R706
243

1%
0603
COMMON

J13
K12
F12
G12
F13
K13
L13
G13

J12
H12
H13

L13
K13
K12
J13

G13
G12
F12

J12
H12
H13

GND

U2

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U4

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

11 FrameBuffer: Partition D 8Mx32 BGA144 DDR3

4> 11<

CKE

R721
10K

5%
0402
COMMON

GND

RESET

R27
10K

5%
0402
COMMON

GND

ZQ = 6x desired outputDDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

144BGA CMD Mapping

CMD ADDR
CMD15 RAS*

CAS*

CMD25

WE*

CMD9

CKE

CMD11

RESET

CMD12

CS0*

CMD8

CS1* *notused

CMD7

A<0>

CMD1

A<1>

CMD3

A<2>

CMD2
CMD0
CMD24
CMD22

CMD13
CMD4
CMD5
CMD6

CMD21
CMD23 A<7>
CMD19
CMD20
CMD17
CMD16
CMD14
CMD10
CMD18

A<3>
A<4>
A<5>

A<2>

A<4>
A<5>

A<6>

A<8>
A<9>
A<10
A<11>
A<12>
BA0
BA1

Low Sub-Partition

Hi Sub-Partition

FBD_CMD<25..0>

Low Sub-Partition

4>

11<

4>

11<

11<>

11<>

11<>

11<>

4<>

15
25
9
8

1
3
2
0
24
22
21
23
19
20
17
16
14

10
18

11

12

4>

4<

4>

A-CS0-LOW-32bit

U2

DDR3BGA144
BGA144
VERSION=BGA144
CHANGED

M10

L12
M12
N12
N13
N11FBD_CMD<19>
M11

N10

E12

M5
N6
N9

N2
N3
M3
L3

M4
N4

N5

L6

M7
N7
N8

E3

M8

FBD_CMD<15>
FBD_CMD<25>
FBD_CMD<9>
FBD_CMD<8>

CS0

FBD_CMD<1>

FBD_CMD<3>
FBD_CMD<2>
FBD_CMD<0>
FBD_CMD<24>
FBD_CMD<22>

FBD_CMD<21>

FBD_CMD<23>

FBD_CMD<20>

FBD_CMD<17>

FBD_CMD<16>

FBD_CMD<14>

FBD_CMD<10>

FBD_CMD<18>

SNN_FBD0_BA2

FBD_CMD<11>

FBD_CLK0
FBD_CLK0*

SNN_FBD0_NC1
SNN_FBD0_NC2
SNN_FBD0_NC3

M6FBD_CMD<12>

GND

FBDD<63..0>

FBDDQM<7..0>

FBDDQS_RN<7..0>

FBDDQS_WP<7..0>

M9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VREF:
M2 - DATA
M13 - ADDR

FBDDQM<0>

0

FBDDQM<1>

1

FBDDQM<2>

2

FBDDQM<3>

3

FBDDQM<4>

4

FBDDQM<5>

5

FBDDQM<6>

6

FBDDQM<7>

7

FBDDQS_RN<0>

0

FBDDQS_RN<1>

1

FBDDQS_RN<2>

2

FBDDQS_RN<3>

3

FBDDQS_RN<4>

4

FBDDQS_RN<5>

5

FBDDQS_RN<6>

6

FBDDQS_RN<7>

7

FBDDQS_WP<0>

0

FBDDQS_WP<1>

1

FBDDQS_WP<2>

2

FBDDQS_WP<3>

3

FBDDQS_WP<4>

4

FBDDQS_WP<5>

5

FBDDQS_WP<6>

6

FBDDQS_WP<7>

7

GND

FBD_ZQ0

R727

243

1%

0603

COMMON

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4L9
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

GND

12MIL

FBD_VREF_DATA0
FBD_VREF_ADDR0

VREF = 0.70 * FBVDDQ

DDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBDD<0>

0

FBDD<1>

1

FBDD<2>

2

FBDD<3>

3

FBDD<4>

4

FBDD<5>

5

FBDD<6>

6

FBDD<7>

7

FBDDQM<0>
FBDDQS_RN<0>
FBDDQS_WP<0>

FBDD<32>

32

FBDD<33>

33

FBDD<34>

34

FBDD<35>

35

FBDD<36>

36

FBDD<37>

37

FBDD<38>

38

FBDD<39>

39

FBDDQM<4>
FBDDQS_RN<4>
FBDDQS_WP<4>

FBD Partition

Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBD_CMD<25..0>

FBVDDQ

R25
511

1%

0402

COMMON

1.3K

1%

0402

CHANGED

GND

12MIL

C9
B8

B9
B10
D12
C13
E13
D13

C12
B12
B13

B10
D13
E13
C13
D12

B8

B9

C9

C12
B12
B13

2

0

24

22

13

4

5

6

R1

C39R24
.1UF

R2

10V
10%
X5R
0402
COMMON

U2

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U4

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

FBD_CMD<2>

FBD_CMD<0>

FBD_CMD<24>

FBD_CMD<22>

FBD_CMD<13>

FBD_CMD<4>

FBD_CMD<5>

FBD_CMD<6>

FBD_CLK0

FBD_CLK0*

FBD_CLK1

FBD_CLK1*

CHANGED

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

FBVDDQ

R736

511

1%

0402

COMMON

R730

1.3K

1%

0402

GND

FBDD<8>

8

FBDD<9>

9

FBDD<10>

10

FBDD<11>

11

FBDD<12>

12

FBDD<13>

13

FBDD<14>

14

FBDD<15>

15

FBDDQM<1>

FBDDQS_WP<1>

FBDD<40>

40

FBDD<41>

41

FBDD<42>

42

FBDD<43>

43

FBDD<44> C6

44

FBDD<45>

45

FBDD<46>

46

FBDD<47>

47

FBDDQM<5>
FBDDQS_RN<5>
FBDDQS_WP<5>

R718

121

0402

1%

R719

121

0402

1%

R729

121

0402

1%

R733

121

0402

1%

R696

121

0402

1%

R694

121

0402

1%

R711

121

0402

1%

R713

121

0402

1%

R723

60.4

0402

1%

R725

60.4

0402

1%

R700

60.4

0402

1%

R704

60.4

0402

1%

ZQ = 6x desired output

DDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

R1

C1091
.1UF

R2

10V
10%
X5R
0402
COMMON

FBVDDQ

C6
B6
B5
B7
D3
D2
E2
C2

C3
B3FBDDQS_RN<1>
B2

D2
B5
B7
B6

C2
D3
E2

C3
B3
B2

FBD_CMD<25..0>

Hi Sub-Partition

4>

11<

4>

11<

U2

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U4

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition D 8Mx32 BGA144 DDR3

15
25
9
8

1
3
13
4
5
6
21
23
19
20
17
16
14

10
18

11

FBDD<16>

16

FBDD<17>

17

FBDD<18>

18

FBDD<19>

19

FBDD<20>

20

FBDD<21>

21

FBDD<22>

22

FBDD<23>

23

FBDDQM<2>
FBDDQS_RN<2>
FBDDQS_WP<2>

FBDD<48>

48

FBDD<49>

49

FBDD<50>

50

FBDD<51>

51

FBDD<52> F13

52

FBDD<53>

53

FBDD<54>

54

FBDD<55>

55

FBDDQM<6>
FBDDQS_RN<6>
FBDDQS_WP<6>

www.vinafix.vn

A-CS0-HI-32bit

U4

DDR3BGA144
PACK_TYPE=BGA144
VERSION=BGA144
CHANGED

M5
N6
N9

M10

N2
N3
M3

L3
L12
M12
N12
N13
N11
M11

M4

N4

L9

N5
N10

L6

M7

N7

N8

E3
E12

M8

M6

M9

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

FBDD<24>
FBDD<25>
FBDD<26>
FBDD<27>
FBDD<28>
FBDD<29>
FBDD<30>
FBDD<31>

FBDDQM<3>
FBDDQS_RN<3>
FBDDQS_WP<3>

FBDD<56>
FBDD<57>
FBDD<58>
FBDD<59>
FBDD<60>
FBDD<61>
FBDD<62>
FBDD<63>

FBDDQM<7>
FBDDQS_RN<7>
FBDDQS_WP<7>

NET RULES

IMPEDANCENET

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

DDR3:

GND

FBD_VREF_DATA1
FBD_VREF_ADDR1

VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

U2

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

G2
F3
F2
L2
K3
J2
G3
K2

J3
H3
H2

U4

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

L2
J2
K2
K3
G3
G2
F2
F3

J3
H3
H2

R693

511

0402

COMMON

R691

1.3K

0402

CHANGED

11<>

11<>

11<>
11<>

FBVDDQ

1%

1%

11<

11<
11<
11<

GND

4>
4> 11<
4>
4>
4>

4<>

4>

4<
4>

R1

R2

FBD_CLK0
FBD_CLK0*
FBD_CLK1
FBD_CLK1*
FBD_CMD<25..0>

FBDD<63..0>
FBDDQM<7..0>

FBDDQS_RN<7..0>
FBDDQS_WP<7..0>

C1034
.1UF

10V
10%
X5R

R28

0402

511

COMMON

0402

COMMON

R29

1.3K

0402

CHANGED

NVVDD

Reference Plane Transition Cap

C1073
22UF

6.3V
20%
X5R
0805

FBVDDQ

1%

1%

R1

R2

GND

C712
120PF

50V
5%
C0G
0402
COMMONCOMMON

100DIFF
100DIFF
100DIFF
100DIFF
40OHM

40OHM
40OHM

40OHM
40OHM

C44
.1UF

10V
10%
X5R
0402
COMMON

C731
120PF

50V
5%
C0G
0402
COMMON

GND

600-10317-0002-100

design
John Lam

DIFFPAIRCRITICAL

FBD_CLK0
FBD_CLK01
FBD_CLK1
FBD_CLK1

11 OF 28

31-MAY-2005

1

1
1
1

1
1

1
1

12 FrameBuffer: Partition D Decoupling

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBVDDQ

FBVDDQ

Decoupling for FBD 0..31 Decoupling for FBD 32..63

C1092

C1089

1UF

6.3V
10%
X5R
0603
COMMON

C1098

1UF

6.3V
10%
X5R
0603
COMMON

C1090

1UF

6.3V
10%
X5R
0603
COMMON

C1052

1UF

6.3V
10%
X5R
0603
COMMON

C1024

1UF

6.3V
10%
X5R
0603
COMMON

C1068 C1082

.1UF

.1UF .01UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C1095

C1094

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C1088

C1062

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C1055

C1059

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C1031

C1049

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

16V
10%
X7R
0402
COMMON

C1069

.01UF

16V
10%
X7R
0402
COMMON

C1063

.01UF

16V
10%
X7R
0402
COMMON

C1081

.01UF

16V
10%
X7R
0402
COMMON

C1083

.01UF

16V
10%
X7R
0402
COMMON

C1077 C1085

.01UF .01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C1067

C1071

.01UF

.01UF

16V

16V

10%

10%
X7R X7R
0402

0402
COMMON

COMMON

C1060

C1056

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C1066

C1070

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C1086

C1080

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C1064

.01UF

16V
10%
X7R
0402
COMMON

C1075

.01UF

16V
10%
X7R
0402
COMMON

C1076

120PF

50V
5%
C0G
0402
COMMON

C1054

120PF

50V
5%
C0G
0402
COMMON

C1078

120PF

50V
5%
C0G
0402
COMMON

C1093

120PF

50V
5%
C0G
0402
COMMON

GND

GND

GND

GND

C1061 C1058

.1UF1UF

6.3V

10V

10%

10%

X5R

X5R

0603

0402

COMMON

COMMON

C1051

C1047

1UF

.1UF

6.3V

10V

10%

10%
X5RX5R

0603

0402

COMMON

COMMON

C1012

C1025

1UF

.1UF

6.3V

10V

10%

10%

X5R

X5R

0603

0402

COMMON

COMMON

C1001

C1005

1UF

.1UF

6.3V

10V

10%

10%

X5R

X5R

0603

0402

COMMON

COMMON

C1084

C1057

1UF

.1UF

6.3V

10V

10%

10%

X5R

X5R

0603

0402

COMMON

COMMON

C1045

.1UF

10V
10%
X5R
0402
COMMON

C1018

.01UF

16V
10%
X7R
0402
COMMON

C1009

.1UF

10V
10%
X5R
0402
COMMON

C1053

.1UF

10V
10%
X5R
0402
COMMON

C1044 C1043 C1041

.01UF.01UF

16V
10%
X7R
0402
COMMON

C1029

.01UF

16V
10%
X7R
0402
COMMON

C1014

.01UF

16V
10%
X7R
0402
COMMON

C1037

.01UF

16V
10%
X7R
0402
COMMON

C1015

.01UF

16V
10%
X7R
0402
COMMON

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C1013

C1035

.01UF

.01UF

16V

16V

10%

10%
X7R X7R
0402

0402
COMMON COMMON

C1019

C1027

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C1033

C1042

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C1020

C1026

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C1038

.01UF

16V
10%
X7R
0402
COMMON

C1030

.01UF

16V
10%
X7R
0402
COMMON

C1048

120PF

50V
5%
C0G
0402
COMMON

C1010

120PF

50V
5%
C0G
0402
COMMON

C1032

120PF

50V
5%
C0G
0402
COMMON

C1039

120PF

50V
5%
C0G
0402
COMMON

GND

GND

GND

GND

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition D Decoupling

www.vinafix.vn

GND

600-10317-0002-100

design
John Lam

12 OF 28

31-MAY-2005

13 DACA Interface

OUT

OUT

OUT

OUT

OUT

OUT

OUT

11

15

6

10

1

5

SDA

ID0

SCL

HSYNC

VSYNC

GND_B

GND-G

GND-R
R

G

5V
ID2

GND

GND

B

OUT

8/24 DACA

DACA_VSYNC

DACA_HSYNC

I2CA_SCL
I2CA_SDA

DACA_RED

DACA_IDUMP

DACA_GREEN

DACA_BLUE

DACA_VDD

DACA_VREF

DACA_RSET

INININININININININININININININININ

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

DACA_I2C_SCL_R

33

R11

COMMON

0402

5V

10

9

3.3V

16MIL

C956C961

10V
10%
X5R
0402
COMMON

DACA_VDD

C875
.01UF.1UF4.7UF4.7UF

16V
10%
X7R
0402
COMMON

AK13

AK14

AH11

U9
GF-7800-GT-A2

BGA1148
CHANGED

T9
U8

AJ11
AF14

AH13

AJ14

AH12

DACA_I2C_SCL
DACA_I2C_SDA

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

5V

C1138
.1UF

10V
10%
X5R
0402
COMMON

GND

4

5

C863
.1UF

10V
10%
X5R
0402
COMMON

180R@100MHz

COMMONBEAD_0603

DACA_VREF

DACA_RSET

R635

1.91K

1%
0402
CHANGED

6.3V
10%
X5R
0603
COMMON

R634
137

1%
0402
COMMON

A3V3

LB507

C972

6.3V
10%
X5R
0603
COMMON

GND

GND

AJ13

GND

5V

C1108

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

Place near Sync Diode

U510

74ACT08

DACA_HS_BUF

8

74ACT_SO
COMMON

GND

5V

U510

74ACT08

DACA_VS_BUF

6

74ACT_SO
COMMON

GND

R626
150

1%
0402
COMMON

GND

R629
150

1%
0402
COMMON

GND

R628
150

1%
0402
COMMON

5%

R14

0402

5%

sync_buf bypass

R764

0402

0402

sync_buf bypass

R747

0402

R748

0402

33

COMMON

5%

5%

5%

5%

33

NO STUFF

33R765

COMMON

33

NO STUFF

33

COMMON

DACA_I2C_SDA_R

NET RULES

NET

DACA_RED
DACA_GREEN
DACA_BLUE
DACA_RED_T
DACA_GREEN_T
DACA_BLUE_T
DACA_RED_DVI
DACA_GREEN_DVI
DACA_BLUE_DVI

DACA_HSYNC
DACA_VSYNC
DACA_HS_BUF
DACA_VS_BUF
DACA_HS_BUF_R
DACA_VS_BUF_R
DACA_HS_DVI
DACA_VS_DVI

13>
15<

15<

13>
15<

13>
15<

15<

1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

IMPEDANCECRITICAL

50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
75OHM
75OHM
75OHM

50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM

www.vinafix.vn

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
DACA Interface

DACA_HS_BUF_R

DACA_VS_BUF_R

GND

GND

GND

R755
150

1%
0402
COMMON

R756
150

1%
0402
COMMON

R754
150

1%
0402
COMMON

BEAD_0603

R7

2.2K

5%

5V

0402
COMMON12

1

R9

2.2K

5%
0402
COMMON2

180R@100MHz

LB4

COMMON

BEAD_0603

27nH

L3

COMMON

0603

5V

2

D3

BAV99

3

SOT23
100V
100MA
COMMON

1

GND

5V

2

D1

BAV99

3

SOT23
100V
100MA
COMMON

1

27nH

L2

COMMON

0603

C7
22PF

50V
5%
C0G
0603
COMMON

GND

C8
22PF

50V
5%
C0G
0603
COMMON

GND

C10
12PF

50V
5%
C0G
0603
COMMON

GND

C9
12PF

50V
5%
C0G
0603
COMMON

GND

180R@100MHz

LB3

COMMON

DACA_I2C_SCL_DVI

DACA_I2C_SDA_DVI

DACA_HS_DVI

DACA_VS_DVI

15<

15<

15< 13<

15< 13<

GND

0603

C1112
22PF

50V
5%
C0G
0402
NO STUFF

C1113
22PF

50V
5%
C0G
0402
NO STUFF

C1111
22PF

50V
5%
C0G
0402
NO STUFF

27nH

CHANGED

27nH

CHANGED0603

27nH

CHANGED0603

GND

DACA_GREEN_T

GND

DACA_BLUE_T

GND

C1123

4.7PF

50V
+/-0.25PF
C0G
0402
CHANGED

C1124

4.7PF

50V
+/-0.25PF
C0G
0402
CHANGED

C1122

4.7PF

50V
+/-0.25PF
C0G
0402
CHANGED

L514

cmfltr4_2012

L515

L512

360R@100mhz

COMMON

WIRE_WOUND

360R@100mhz

COMMONcmfltr4_2012

WIRE_WOUND

360R@100mhz

COMMONcmfltr4_2012

WIRE_WOUND

L502

GND

L503

GND

L501

GND

DACA_RED_T

DACA_RED_DVI

DACA_GREEN_DVI

DACA_BLUE_DVI

SNN_DACA_ID2

0V

DACA_RGB_GND

DDC_5V

GND

15< 13<
15< 13<
15< 13<

J2

CON_DSUB15HD
VGA_SLIM_DVIMTG
VGA_SLIM_DVIMTG
NO STUFF

6
1
7
2
8
3
9
4

10

5

11

12

13

14

15

SNN_DACA_ID0

15<

600-10317-0002-100

design
John Lam

13 OF 28

31-MAY-2005

14 DACC Interface

OUT

OUT

OUT

OUT

OUT

OUT

OUT

11

15

6

10

1

5

SDA

ID0

SCL

HSYNC

VSYNC

GND_B

GND-G

GND-R
R

G

5V
ID2

GND

GND

B

OUT

10/24 DACC

DACC_VSYNC

DACC_HSYNC

I2CB_SCL
I2CB_SDA

DACC_IDUMP

DACC_BLUE

DACC_GREEN

DACC_RED

DACC_VDD

DACC_VREF

DACC_RSET

INININININININININININININININININ

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

DACC_I2C_SCL_R

33

R10

COMMON

0402

5V

13

12

3.3V

16MIL

C971C982

10V
10%
X5R
0402
COMMON

DACC_VDD

C929
.01UF.1UF4.7UF4.7UF

16V
10%
X7R
0402
COMMON

U9
GF-7800-GT-A2

BGA1148
CHANGED

AH7

AK8

AH8

R9
T8

AJ10
AJ7

AJ9

AH9

AH10

DACC_I2C_SCL
DACC_I2C_SDA

DACC_HSYNC
DACC_VSYNC

DACC_RED

DACC_GREEN

DACC_BLUE

1

2

C908
.1UF

10V
10%
X5R
0402
COMMON

180R@100MHz

COMMONBEAD_0603

DACC_VREF

DACC_RSET

R643

1.91K

1%
0402
CHANGED

6.3V
10%
X5R
0603
COMMON

R637
137

1%
0402
COMMON

A3V3

LB516

C997

6.3V
10%
X5R
0603
COMMON

GND

GND

AK9

GND

5V

C1107

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

Place near Synce Diode

U510

74ACT08

DACC_HS_BUF

11

74ACT_SO
COMMON

GND

5V

U510

74ACT08

DACC_VS_BUF

3

74ACT_SO
COMMON

GND

R656
150

1%
0402
COMMON

GND

R649
150

1%
0402
COMMON

GND

R671
150

1%
0402
COMMON

5%

R12

0402

5%

sync_buf bypass

R1

0402

0402

sync_buf bypass

R745

0402

R746

0402

33

COMMON

5%

5%

5%

5%

33

NO STUFF

33R763

COMMON

33

NO STUFF

33

COMMON

DACC_I2C_SDA_R

NET RULES

NET

DACC_RED
DACC_GREEN
DACC_BLUE
DACC_RED_T
DACC_GREEN_T
DACC_BLUE_T
DACC_RED_DVI
DACC_GREEN_DVI
DACC_BLUE_DVI

DACC_HSYNC
DACC_VSYNC
DACC_HS_BUF
DACC_VS_BUF
DACC_HS_BUF_R
DACC_VS_BUF_R
DACC_HS_DVI
DACC_VS_DVI

14>
15<

15<

14>
15<

15<
14>
14>
15<

1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

IMPEDANCECRITICAL

50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
75OHM
75OHM
75OHM

50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM

www.vinafix.vn

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
DACC Interface

DACC_HS_BUF_R

DACC_VS_BUF_R

GND

GND

GND

R757
150

1%
0402
COMMON

R759
150

1%
0402
COMMON

R753
150

1%
0402
COMMON

BEAD_0603

R6

2.2K

5%

5V

0402
COMMON12

1

R8

2.2K

5%
0402
COMMON2

2

1

180R@100MHz

LB6

COMMON

BEAD_0603

27nH

L1

COMMON

0603

5V

2

D4

BAV99

3

SOT23
100V
100MA
COMMON

1

GND

5V

2

D6

BAV99

3

SOT23
100V
100MA
COMMON

1

27nH

L4

COMMON

0603

C3
22PF

50V
5%
C0G
0603
COMMON

GND

C4
22PF

50V
5%
C0G
0603
COMMON

GND

C6
12PF

50V
5%
C0G
0603
COMMON

GND

C5
12PF

50V
5%
C0G
0603
COMMON

GND

180R@100MHz

LB5

COMMON

DACC_I2C_SCL_DVI

DACC_I2C_SDA_DVI

DACC_HS_DVI

DACC_VS_DVI

15<

15<

15< 14<

15< 14<

GND

0603

C1114
22PF

50V
5%
C0G
0402
NO STUFF

C1116
22PF

50V
5%
C0G
0402
NO STUFF

C1115
22PF

50V
5%
C0G
0402
NO STUFF

27nH

CHANGED

27nH

CHANGED0603

27nH

CHANGED0603

GND

DACC_GREEN_T

GND

DACC_BLUE_T

GND

C1121

4.7PF

50V
+/-0.25PF
C0G
0402
CHANGED

C1126

4.7PF

50V
+/-0.25PF
C0G
0402
CHANGED

C1120

4.7PF

50V
+/-0.25PF
C0G
0402
CHANGED

L513

cmfltr4_2012

L516

L511

360R@100mhz

COMMON

WIRE_WOUND

360R@100mhz

COMMONcmfltr4_2012

WIRE_WOUND

360R@100mhz

COMMONcmfltr4_2012

WIRE_WOUND

L505

GND

L506

GND

L504

GND

DACC_RED_T

DACC_RED_DVI

DACC_GREEN_DVI

DACC_BLUE_DVI

SNN_DACC_ID2

0V

DACC_RGB_GND

DDC_5V

GND

15< 14<
15< 14<
15< 14<

J1

CON_DSUB15HD
VGA_SLIM_DVIMTG
VGA_SLIM_DVIMTG
NO STUFF

6
1
7
2
8
3
9
4

10

5

11

12

13

14

15

SNN_DACC_ID0

15<

600-10317-0002-100

design
John Lam

14 OF 28

31-MAY-2005

LB2

1917

81624

C5A

C1

C2

C3

C5

C4

SHLD13

SHLD24

SHIELD6
SHIELD7

SHIELD10

SHIELD9

SHIELD8

SHIELD5

SHIELD4

SHIELD3

SHIELD2

SHIELD1

SHLD05

TX0­TX0+

TX2-

TX1­TX1+

TX2+

TX3­TX3+
TX4-

TX5-

TX4+

TX5+
DDCC
DDCD

TXC-

SHLDC

GND

VDDC

TXC+

HPD

R

VSYNC

G
B
AGND1

AGND2
HSYNC

1917

81624

C5A

C1

C2

C3

C5

C4

SHLD13

SHLD24

SHIELD6
SHIELD7

SHIELD10

SHIELD9

SHIELD8

SHIELD5

SHIELD4

SHIELD3

SHIELD2

SHIELD1

SHLD05

TX0­TX0+

TX2-

TX1­TX1+

TX2+

TX3­TX3+
TX4-

TX5-

TX4+

TX5+
DDCC
DDCD

TXC-

SHLDC

GND

VDDC

TXC+

HPD

R

VSYNC

G
B
AGND1

AGND2
HSYNC

ININININININININOUTININININININININ

OUT

12/24 IFPAB TMDS

IFPA_TXD0

IFPA_TXC
IFPA_TXC

IFPA_TXD0

IFPA_TXD1
IFPA_TXD1

IFPA_TXD3
IFPA_TXD3

IFPA_TXD2

IFPA_TXD2

IFPB_TXD7
IFPB_TXD7

IFPB_TXD4

IFPB_TXD6

IFPB_TXD6

IFPB_TXD5
IFPB_TXD5

IFPB_TXD4

IFPB_TXC

IFPB_TXC

IFPAB_RSET

IFPAB_PLLVDD

IFPAB_PLLGND

IFPA_IOVDD

IFPAB_VPROBE

IFPB_IOVDD

13/24 IFPCD TMDS

IFPC_TXD2

IFPC_TXC

IFPC_TXC

IFPC_TXD0
IFPC_TXD0

IFPC_TXD1
IFPC_TXD1

IFPC_TXD2

IFPD_TXD6

IFPD_TXD6

IFPD_TXD5

IFPD_TXC

IFPD_TXC

IFPD_TXD4
IFPD_TXD4

IFPD_TXD5

IFPCD_RSET

IFPCD_VPROBE

IFPCD_PLLGND

IFPC_IOVDD

IFPCD_PLLVDD

IFPD_IOVDD

INININ

IN

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

LB1

COMMONBEAD_0603

COMMONBEAD_0603

U9
GF-7800-GT-A2

BGA1148
CHANGED

C938
.01UF

16V

X7R
0402
COMMON

C917
.01UF

16V
10%
X7R
0402
COMMON

C937
.01UF.1UF

16V
10%
X7R
0402
COMMON

C949
.01UF

16V
10%
X7R
0402
COMMON

C939
.01UF

16V
10%
X7R
0402
COMMON

C951
.01UF

16V
10%
X7R
0402
COMMON

AR6

AM7

AN6

AN7

AN8

AM6

U9
GF-7800-GT-A2

BGA1148
CHANGED

AL6

AN3

AM4

AL4

AL5

AJ4

SNN_IFPAB_VPROBE

IFPAB_RSET

1K

COMMON

IFPAB_PLLVDD

C935
.1UF

10V
10% 10%
X5R
0402
COMMON

16MIL

IFPAB_IOVDD

C922
.1UF

10V
10%
X5R
0402
COMMON

GND

C916

10V
10%
X5R
0402
COMMON

GND

SNN_IFPCD_VPROBE

IFPCD_RSET

1K

COMMON

16MIL

IFPCD_PLLVDD

C959
.1UF

10V
10%
X5R
0402
COMMON

16MIL

IFPCD_IOVDD

C934
.1UF

10V
10%
X5R
0402
COMMON

GND

C966
.1UF

10V
10%
X5R
0402
COMMON

GND

3.3 V16MIL

3.3 V

3.3 V

3.3 V

IMPEDANCECRITICALDIFFPAIR

100DIFF
100DIFF

100DIFF
100DIFF

NET RULES

NET

IFPAB_TXC*

AT9

IFPAB_TXC

AT8

IFPAB_TXD0*

AN4

IFPAB_TXD0

AN5

IFPAB_TXD1*

AT3

IFPAB_TXD1

AT4

IFPAB_TXD2*

AP4

IFPAB_TXD2

AP5

SNN_IFPAB_TXD3*

AR3

SNN_IFPAB_TXD3

AR4

SNN_IFPB_TXC*

AP1

SNN_IFPB_TXC

AR2

IFPAB_TXD4*

AP6

IFPAB_TXD4

AP7

IFPAB_TXD5*

AR7

IFPAB_TXD5

AR8

IFPAB_TXD6*

AT5

IFPAB_TXD6

AT6

SNN_IFPAB_TXD7*

AN2

SNN_IFPAB_TXD7

AP2

NET RULES

IFPCD_TXC*

AJ6

IFPCD_TXC

AH6

IFPCD_TXD0*

AL2

IFPCD_TXD0

AL1

IFPCD_TXD1*

AJ1

IFPCD_TXD1

AK1

IFPCD_TXD2*

AL3

IFPCD_TXD2

AM3

SNN_IFPD_TXC*

AH5

SNN_IFPD_TXC

AH4

IFPCD_TXD4*

AK2

IFPCD_TXD4

AK3

IFPCD_TXD5*

AK4

IFPCD_TXD5

AK5

IFPCD_TXD6*

AM1

IFPCD_TXD6

AN1

DIFFPAIRNET

IFPAB_TXC
IFPAB_TXC

IFPAB_TXD0
IFPAB_TXD0

IFPAB_TXD1
IFPAB_TXD1

IFPAB_TXD2
IFPAB_TXD2

IFPAB_TXD4
IFPAB_TXD4

IFPAB_TXD5
IFPAB_TXD5

IFPAB_TXD6
IFPAB_TXD6

20<

IFPCD_TXC
IFPCD_TXC

IFPCD_TXD0
IFPCD_TXD0

IFPCD_TXD1
IFPCD_TXD1

IFPCD_TXD2
IFPCD_TXD2

IFPCD_TXD4
IFPCD_TXD4

IFPCD_TXD5
IFPCD_TXD5

IFPCD_TXD6
IFPCD_TXD6

20<

IMPEDANCECRITICALDIFFPAIR

1
1

1
1

1
1

1
1

1
1

1
1

1
1

GPIO0_DVI_A_HPD

R15
10K

5%
0402
COMMON

GND

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

5V

R3

0402

2

D2

BAV99

3

SOT23
100V
100MA
COMMON

1

GND

DVI_A_HPD_R

1K

COMMON

1%

IMPEDANCECRITICAL

1
1

1
1

1
1

1
1

1
1

1
1

1
1

GPIO1_DVI_C_HPD

R13
10K

5%
0402
COMMON

GND

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

100DIFF
100DIFF

5V

0402

2

D5

BAV99

3

SOT23
100V
100MA
COMMON

1

GND

DVI_C_HPD_R

1K

R4

COMMON

1%

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
IFP A/B and C/D Interface

www.vinafix.vn

LB508

LB510

180R@100MHz

COMMONBEAD_0603

180R@100MHz

COMMONBEAD_0603

GND

C977

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

R642

0402

1%

C960

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

15 IFP A/B and C/D Interface

IFP_PLLVDD

IFP_IOVDD

IFP_PLLVDD

IFP_IOVDD

LB514

BEAD_0603

LB517

BEAD_0603

180R@100MHz

COMMON

180R@100MHz

COMMON

C983

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

R661

0402

1%

C988

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

GND

NET RULES

NET

IFPAB_TXC_DVI*
IFPAB_TXC_DVI

IFPCD_TXC_DVI*
IFPCD_TXC_DVI

IFPAB_TXC
IFPAB_TXC

IFPCD_TXC
IFPCD_TXC

1
1

1
1

180R@100MHz

C2
220PF

50V
5%
C0G
0402
COMMON

GND

LB14

LB15

14<

180R@100MHz

C1
220PF

50V
5%
C0G
0402
COMMON

GND

LB16

LB17

13> 13<

0402

0402

14>

14>

0402

13<

CHANGED

CHANGED

14<

13>
13>

CHANGED0402

CHANGED

13>

13<
13>
13>
13<
13>

13>
13<

14>
14>

0

0

14>

14>
14<
14>
14<

14>
14<

DDC_5V

C1132
4700PF

16V
10%
X7R
0402
COMMON

GND

IFPAB_TXD0*
IFPAB_TXD0
IFPAB_TXD1*
IFPAB_TXD1
IFPAB_TXD2*
IFPAB_TXD2

IFPAB_TXD4*
IFPAB_TXD4
IFPAB_TXD5*
IFPAB_TXD5
IFPAB_TXD6*
IFPAB_TXD6
DACA_I2C_SCL_DVI
DACA_I2C_SDA_DVI

0

0

IFPAB_TXC_DVI*

IFPAB_TXC_DVI
DACA_VS_DVI
DVI_A_HPD_C

DACA_RED_DVI
DACA_GREEN_DVI
DACA_BLUE_DVI
DACA_RGB_GND

DACA_HS_DVI

GND

IFPCD_TXD0*
IFPCD_TXD0
IFPCD_TXD1*
IFPCD_TXD1
IFPCD_TXD2*
IFPCD_TXD2

IFPCD_TXD4*
IFPCD_TXD4
IFPCD_TXD5*
IFPCD_TXD5
IFPCD_TXD6*
IFPCD_TXD6
DACC_I2C_SCL_DVI
DACC_I2C_SDA_DVI

IFPCD_TXC_DVI*
IFPCD_TXC_DVI

DACC_VS_DVI
DVI_C_HPD_C

DACC_RED_DVI
DACC_GREEN_DVI
DACC_BLUE_DVI
DACC_RGB_GND

DACC_HS_DVI

C1140
4700PF

16V
10%
X7R
0402
COMMON

DDC_5V

25
26
27
28
29

17
18

9

10

1
2

3
11
19
12
13

4

5
20
21

6

7
14
15
22
24
23

8
16

C1
C2
C3
C5

C5A

C4

30
31
32
33
34

GND

25
26
27
28
29

17
18

9
10

1

2

3
11
19
12
13

4

5
20
21

6

7
14
15
22
24
23

8
16

C1
C2
C3
C5

C5A

C4

30
31
32
33
34

GND

SOUTH

MIDDLE NORTH

J5
DVI-I

DVI_I_(SLIM_)SHLD_MOLEX
DVI_I
CHANGED

IFP_IOVDD

C948
.01UF

16V
10%
X7R
0402
COMMON

IFP_IOVDD

C944
.01UF

16V
10%
X7R
0402
COMMON

3V3

3V3 Plane Transition Caps

C1133
.1UF

16V
10%
X7R
0402
NO STUFF

J4
DVI-I

DVI_I_(SLIM_)SHLD_MOLEX
DVI_I
CHANGED

IFP_IOVDD

C67
.01UF

16V
10%
X7R
0402
COMMON

IFP_IOVDD

C65
.01UF

16V
10%
X7R
0402
COMMON

3V3

3V3 Plane Transition Caps

C1129
.1UF

16V
10%
X7R
0402
NO STUFF

C921
.01UF

16V
10%
X7R
0402
COMMON

C955
.01UF

16V
10%
X7R
0402
COMMON

C73
.01UF

16V
10%
X7R
0402
COMMON

C63
.01UF

16V
10%
X7R
0402
COMMON

IFP_IOVDD

GND

GND

GND

C1131
.1UF

16V
10%
X7R
0402
NO STUFF

IFP_IOVDD

GND

GND

GND

C1130
.1UF

16V
10%
X7R
0402
NO STUFF

C964
.01UF

16V
10%
X7R
0402
COMMON

C958
.01UF

16V
10%
X7R
0402
COMMON

C970
.01UF

16V
10%
X7R
0402
COMMON

C976
.01UF

16V
10%
X7R
0402
COMMON

C66
.01UF

16V
10%
X7R
0402
COMMON

C71
.01UF

16V
10%
X7R
0402
COMMON

R648

0402

1%

R672

0402

1%

R666

0402 COMMON

1%

R657

0402

1%

R646

04021%COMMON

R645

0402

1%

R651

0402

1%

C15
.1UF

16V
10%
X7R
0402
NO STUFF

R670

0402

1%

R67

0402

1%

R69

0402

1%

R71

0402

1%

R57

0402

1%

R73

0402

1%

R55

0402

1%

C11
.1UF

16V
10%
X7R
0402
NO STUFF

49.9

COMMON

49.9

COMMON

49.9

49.9

COMMON

49.9

49.9

COMMON

49.9

COMMON

49.9

COMMON

49.9

COMMON

49.9

COMMON

49.9

COMMON

49.9

COMMON

49.9

COMMON

49.9

COMMON

R647

0402

R667

0402

0402

R654

0402

0402

R641

0402

R652

0402

C1141
.1UF

16V
10%
X7R
0402
NO STUFF

R669

0402

R68

0402

R70

0402

R72

0402

R58

0402

R74

0402

R56

0402

C13
.1UF

16V
10%
X7R
0402
NO STUFF

IFPAB_TXC*
IFPAB_TXC

49.9

COMMON

1%

IFPAB_TXD0*
IFPAB_TXD0

49.9

IFPAB_TXD1*

COMMON

1%

1%

1%

1%

1%

1%

49.9R662

COMMON

49.9

COMMON

49.9R650

COMMON

49.9

COMMON

49.9

COMMON

IFPAB_TXD1
IFPAB_TXD2*
IFPAB_TXD2

IFPAB_TXD4*
IFPAB_TXD4
IFPAB_TXD5*
IFPAB_TXD5
IFPAB_TXD6*
IFPAB_TXD6

GND

C932
.1UF

16V
10%
X7R
0402
NO STUFF

IFPCD_TXC*
IFPCD_TXC

49.9

COMMON

1%

IFPCD_TXD0*
IFPCD_TXD0

49.9

IFPCD_TXD1*

COMMON

1%

1%

1%

49.9

COMMON

49.9

COMMON

IFPCD_TXD1
IFPCD_TXD2*
IFPCD_TXD2

IFPCD_TXD4*
IFPCD_TXD4

49.9

IFPCD_TXD5*

COMMON

1%

1%

1%

49.9

COMMON

49.9

COMMON

IFPCD_TXD5
IFPCD_TXD6*
IFPCD_TXD6

GND

C984
.1UF

16V
10%
X7R
0402
NO STUFF

600-10317-0002-100

design
John Lam

15 OF 28

31-MAY-2005

16 DACB Interface/Framelock

INBIOUT

INININININININININININ

IN

FRAMELOCK

GND
GND

12V

RST*
12V

GND

INTR

STER
SCK
SDA
VRST
SRDY
CLK
GPIO

INBIOUT

OUTBIOUT

out

in

out

out

in

5V+

Y/CVBS

SDA

C

GND

C/Pr

Pb out

SCL

GND

Y/CVBS

OUT

POLYSWITCH

9/24 DACB (TVout)

DACB_RED

DACB_GREEN

DACB_BLUE

DACB_IDUMP

DACB_RSET

DACB_VREF

DACB_VDD

IN

S

D

G

IN

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

16>

17<

16>

17<

NET RULES

NET

CVBS_YOUT
CVBS_PBOUT
MDIN_Cout_C
MDIN_Yout_C
MDIN_PBout_C

CVBSYIN

CHROMAIN

CVBSYIN_R

CHROMAIN_R
MDIN_CVBSYIN_C
MDIN_Cin_C

IMPEDANCECRITICAL

1COUT
1
1
1
1
1

1
1
1
1
1
1

50OHM
50OHM
50OHM
75OHM
75OHM
75OHM

50OHM
50OHM
50OHM
50OHM
75OHM
75OHM

20>

STEREO 5V

F1
1A

1812

5V

NO STUFF

16MIL

21

5V_POLY_STEREO

STEREO 3D

GND

180R@100MHz

COMMON

DACB_VREF

R690
10K

5%
0402
NO STUFF

STEREO

DACB_VDD

A3V3

GND

20>

LB509

BEAD_0603

C975

4.7UF

6.3V
10%
X5R
0603
COMMON

C913
.1UF

10V
10%
X5R
0402
COMMON

GND

GPIO11_DACB_RSET

5V

C962

4.7UF

6.3V
10%
X5R
0603
COMMON

DACB_RSET2

1G1D1S

R75

1.5K

1%
0402
NO STUFF

1

220R@100MHz

220R@100MHz

5V

5

1

2

3

GND

16MIL

DACB_VDD

C910
.01UF

16V
10%
X7R
0402
COMMON

R633

1.82K

1%
0402
NO STUFF

Current = ~300mA

5V

GND

U509

SN74AHCT1G08

4

SC70-5
NO STUFF

R631

64.9

1%
0402
CHANGED

GND

DNI FOR VIVO

LB8

BEAD_0805

LB9

BEAD_0805

To Framelock

5V

R749

3.3K

5%
0402
NO STUFF

3

Q517

BSS138
SOT23_1G1D1S
NO STUFF

2

NO STUFF

NO STUFF

C919
.1UF

10V
10%
X5R
0402
COMMON

DACB_RSET

R681
499

1%
0402
NO STUFF

MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V

FILTER VALUES

GND

HDTV/StandardTV

from codec

82pF/330pF

MDIN_GND2_STEREO5V

C1110
.1UF

10V
10%
X5R
0402
NO STUFF

BUFFSTEREO

U9
GF-7800-GT-A2

BGA1148
CHANGED

Y9

Y8

Y11

16MIL

16MIL

STEREO_5V

R743

R744

8.2pF/22pf

0.56uH/1.8uH

0402

0402

5%

5%

33

NO STUFF

33

NO STUFF

BUFFSTEREO_4pin

to DIN connector

82pF/270pF

Internal Stereo Out

STEREO_5V

R640
150

1%
0402
COMMON

BUFFSTEREO_C

C21
.1UF

10V
10%
X5R
0402
NO STUFF

R653
150

1%
0402
COMMON

16< 17<

AB9

AA9

W9

3

3

GND

LB523

BEAD_0603

5V

2

D515

BAV99
SOT23
100V
100MA
NO STUFF

1

GND

5V

2

D8

BAV99
SOT23
100V
100MA
NO STUFF

1

SVID_CHROM

COUTAA8

SVID_LUM

CVBS_YOUT

COMPOSITE

CVBS_PBOUT

NO STUFF

180R@100MHz

CVBS_PBOUT

/COMPOSITE

R668
150

1%
0402
COMMON

C35
220PF

50V
5%
C0G
0603
NO STUFF

CVBSYIN

ST_INT_GND

16MIL

R19
0

5%
0603

GNDGNDGND

R751

R750

56

5%
0402
COMMON

1
2
3
4

ST_INT_SHLD

16MIL

R23
0

5%
0603
NO STUFFNO STUFF

GND

R760
150

1%
0402
COMMON

R761
150

1%
0402
COMMON

18

COMMON0402

5%

Framelock

J7

HDR_1M4
MALE

2.0MM
N/A
NORM
NO STUFF

5V

Ind should be Stuff with 0ohm by default
Cap should be No-Stuff by default

CVBSYIN_R

2

D516

BAV99

3

SOT23
100V
100MA
COMMON

1

C1127

COMMON

L507

C1117
82PF

50V
5%
C0G
0402
COMMON

C1128

COMMON

L508

C1118
82PF

50V
5%
C0G
0402
COMMON

L509

C1119
270PF

50V
5%
C0G
0603
COMMON

0603

0603

8.2PF

50V
NPO

COMMON

8.2PF

50V0603
NPO

COMMON0603

COMMON0603

1

2STEREO

+/-0.5PF

0.56uH

+/-0.5PF

0.56uH

1.8uH

5V

GND

5

3

U508

SN74AHCT1G08

STEREO_FL_BUF

4

SC70-5
NO STUFF

MDIN_PBout_C

C1136
82PF

50V
5%
C0G
0402
COMMON

MDIN_Cout_C

C1137
82PF

50V
5%
C0G
0402
COMMON

C1134
330PF

50V
5%
C0G
0603
COMMON

33

R758

NO STUFF

0402

20>

5%

20<

18<>

5V

C1105
.1UF

10V
10%
X5R
0402
NO STUFF

GND

20<

J3

MINIDIN_10_VIVO
VIVO
CHANGED

7

9

8

5

1

MDIN_GND

R2
0

5%

MDIN_CVBSYIN_C

Rgnd

0603
COMMON

GND FOR STEREO

NOTE:
Rgnd can be used for EMI purposes.

STEREO_FL
I2CC_SCL
I2CC_SDA
GPIO4_VTG_RST

make 10k when header not stuffed

SWAPRDY_A

XTALSSIN

GND

I2CC_SCL_BUFFSTEREO_R

MDIN_SCL_C_STEREO

DDC_5V

C1143
4700PF

16V
10%
X7R
0402
COMMON

MDIN_SDA_C

MDIN_GND2_STEREO5V

10

4

MDIN_Yout_C

6

3

2

1312011

R5

Ind should be Stuff with 0ohm by default
Cap should be No-Stuff by default

5%

MDIN_Cin_C

0603
COMMON

Rgnd_video

STUFF 1UF CAP

WHEN STEREO
ELSE 0 OHM R

Place close to GPU

R752

0402

C1046
.047UF

16V
10%
X7R
0402
NO STUFF

FL_XTAL

R699
110

1%
0402
NO STUFF

C14
220PF

50V
5%
C0G
0603
COMMON

C1099
1000PF

16V
10%
X7R
0402
NO STUFF

GND

0

NO STUFF

5%

LB7

COMMON

BEAD_0603

STUFF (3) FOR STEREO/VIVO

LB525

BEAD_0603

C1135
220PF

50V
5%
C0G
0603
COMMON

C1139

COMMON

L510

C1142
82PF

50V
5%
C0G
0402
COMMON

L5

C12
330PF

50V
5%
C0G
0603
COMMON

180R@100MHz

180R@100MHz

COMMON

8.2PF

+/-0.5PF

50V0603
NPO

0.56uH

COMMON0603

1.8uH

COMMON0603

1
3
5
7

9
11
13

FRAMLOCK_CLKIN

C1125
82PF

50V
5%
C0G
0402
COMMON

C16
270PF

50V
5%
C0G
0603
COMMON

J6

HDR_2X7
FEMALE

2.54MM
0
NO
NORM
NO STUFF

GND

3

R740
10K

5%
0402
NO STUFF

5V

2

D7

BAV99
SOT23
100V
100MA
COMMON

1

Connector
SDI - Female 075-20000-0012-000
Framelock - Male

2
4
6

BUFRST*

8
10
12
14

GND

GPIO10_FL_INT
GPIO7_FL_IO

R741
10K

5%
0402
NO STUFF

DNI FOR STEREO

R17

0402

R762
150

1%
0402
COMMON

CHROMAIN_R

R16

0402

1.5A required for SDI

EXT_12V

20> 17<

C1109
.047UF

16V
10%
X7R
0402
NO STUFF

C1106
.1UF

16V
10%
X7R
0402
NO STUFF

20<>

20<

0

COMMON

5%

I2CC_SCL

I2CC_SDA

20> 17<

20<> 17<>

CVBS_YOUT

R18

56

5%
0402
COMMON

CHROMAIN

17< 16<

18

COMMON

5%

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
DACB Interface/Framelock

www.vinafix.vn

600-10317-0002-100

design
John Lam

16 OF 28

31-MAY-2005

17 Video Capture (Philips 7115)

INININININ

X-Port

VDD

D-GND

7114H,7115HL (QFP100)

Video In

I-Port

AGND
VSSA0
VSSA1
VSSA2

VDDA1
VDDA2

VDDA0

TDO
TMS

TRST

TDI

TCK

TEST5

TEST4

TEST0

TEST3

TEST2

TEST1

RTCO

XPD0

RTS1

LLC2

RTS0

LLC

XPD1

XPD5

XPD4

XPD3

XPD2

XPD6

XCLK

XPD7

XDQ
XRH

XTRI

XRV

XRDY

VDD_XTAL

VDDDE1
VDDDE2

VDDDI1
VDDDI2
VDDDI3
VDDDI4
VDDDI5
VDDDI6

VDDDE4

VDDDE3

VSS_XTAL

VSSDE1
VSSDE2
VSSDE3

VSSDI1

VSSDE4

VSSDI2
VSSDI3

AI1D

AI21

AI12

AOUT

AI11

AI22

ASCLK

AMCLK

AI24

AI23

AI2D

ALRCLK

SCL

RES (CE)

SDA

XTALI

XTALO

XTOUT

AMXCLK

RES_OUT

IPD4

IPD3

IPD2

IPD1

IPD0

IPD5
IPD6
IPD7

HPD1

HPD0

HPD6

HPD5

HPD4

HPD3

HPD2

IDQ

ICLK

HPD7

IGPH

ITRI

ITRDY

IGPV

IGP0
IGP1

ININOUTININBIOUT

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

17> 18<

17> 18< 21>

NET RULES

NET

7115_Xin

VIPPCLK
VIPPCLK_R

50OHM
50OHM

50OHMMIOBD<7..0>

CRITICALIMPEDANCE

17115_Xout
1

1
1

2

VIDEO CAPTURE

U1

SAA7115HL
15_QFP100
COMMON

3.3V

12MIL

7115_VDDA

SNN_7115_AOUT

NO STUFF

NO STUFF

7115_A11
SNN_7115_A12
7115_A1D

7115_A21
SNN_7115_A22
SNN_7115_A23
SNN_7115_A24
7115_A2D

SNN_7115_AMCLK
SNN_7115_ALRCLK
SNN_7115_ASCLK

TP_7115_24576
7115_Xout
7115_Xin

TP_RES_OUT

0
1
2
3
4
5
6
7

SNN_7115_HPD0
SNN_7115_HPD1
SNN_7115_HPD2
SNN_7115_HPD3
SNN_7115_HPD4
SNN_7115_HPD5
SNN_7115_HPD6
SNN_7115_HPD7

SNN_7115_IDQ
SNN_7115_IGPH
SNN_7115_IGPV
SNN_7115_ITRDY

SNN_7115_IGP0
SNN_7115_IGP1

.047UF

R726

0402

C1097

C1096

A3V3

0

NO STUFF

5%

R26

0402

5%

R724

0402

5%

STUFF for 7115

0402

0402

R728
10K

5%
0402
COMMON

4.7K

COMMON

33

COMMON

16V
10%
X7R
COMMON

.047UF

16V
10%
X7R
COMMON

C1087
.047UF

16V
10%
X7R
0402
COMMON

C17
33PF

50V
5%
C0G
0603
COMMON

CER_SMD

Y1

C23
.047UF

16V
10%
X7R
0402
COMMON

XTAL

24.576MHZ

+/-30PPM
COMMON

RESET_7114*

VIPPCLK_R

RESET_7115*

C22
.047UF

16V
10%
X7R
0402
COMMON

TP3

C18
33PF

50V
5%
C0G
0603
COMMON

TP517

16< 16>

16< 16>

CVBSYIN

CHROMAIN

STUFF Pullup for 7115
STUFF 0ohm for 7114

16<> 20<>

20> 16<

16<

20>

21> 18< 17<

17< 18<

I2CC_SDA
I2CC_SCL

BUFRST*

MIOBD<7..0>

VIPPCLK

22

20
18
19

16
14
12
10
13

37
40
39
41

4
6
7

32
31

27
30

62
61
60
59
57
56
55
54

72
71
70
69
67
66
65
64

45
46
53
52
42
47
48
49

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Video Capture (Philips 7115)

www.vinafix.vn

23
17
11

21
24
15
9

2

3
97
98

44
73
74
77
78
79

36
34
35
28
29

90
89
87
86
85
84
82
81

94
95
92
91
96
80

8
1
25
51
75
33
43
58
68
83
93

5
26
50
76
100
38
63
88

TP_7115_TDO
TP_7115_TMS99
TP_7115_TDI
7115_TRST*
7115_TCK

SNN_7115_TEST0
SNN_7115_TEST1
SNN_7115_TEST2
SNN_7115_TEST3
SNN_7115_TEST4
SNN_7115_TEST5

7115_RTCO
SNN_7115_RTC0
SNN_7115_RTS1
SNN_7115_LLC
SNN_7115_LLC2

SNN_7115_XPD0
SNN_7115_XPD1
SNN_7115_XPD2
SNN_7115_XPD3
SNN_7115_XPD4
SNN_7115_XPD5
SNN_7115_XPD6
SNN_7115_XPD7

SNN_7115_XCLK
SNN_7115_XDQ
SNN_7115_XRH
SNN_7115_XRV
SNN_7115_XRDY
SNN_7115_XTRI

3.3V

12MIL

7115_VDDX

3.3V

12MIL

7115_VDDE

C33
2200PF

16V
10%
X7R
0402
COMMON

C1100
2200PF

16V
10%
X7R
0402
COMMON

C38
2200PF

16V

X7R
0402
COMMON

C51
2200PF

16V
10%
X7R
0402
COMMON

NO STUFF

NO STUFF

NO STUFF

C27
2200PF

16V
10%
X7R
0402
COMMON

TP2
TP1
TP4

R22

3.3K

5%
0402
COMMON

C1101
.1UF

10V
10%
X5R
0402
COMMON

C41
2200PF

16V

X7R
0402
COMMON

C53
2200PF

16V
10%
X7R
0402
COMMON

C26

C31

.1UF2200PF

16V 10V

10%

10%

X5R

X7R

0402

0402

COMMON

COMMON

disable JTAG port

R20

R21

1K

1K

1%

1%

0402

0402

COMMON

COMMON

Select I2C Address
RTC0=0 -> 0x42/0x43
RTC0=1 -> 0x40/0x41

C48
2200PF

16V
10%10%10%
X7R
0402
COMMON

C36
2200PF

16V
10%
X7R
0402
COMMON

C32
.1UF

10V 10V
10%
X5R
0402
COMMON

C49
2200PF

16V

X7R
0402
COMMON

C34
2200PF

16V
10%
X7R
0402
COMMON

C28
.1UF

10%
X5R
0402
COMMON

C50
2200PF

16V

X7R
0402
COMMON

C25
2200PF

16V
10%
X7R
0402
COMMON

C20

4.7UF

6.3V
10%
X5R
0603
COMMON

LB10

BEAD_0603

180R@100MHz

COMMON

C52
.1UF

10V
10%10%10% 10%
X5R
0402
COMMON

C24
.1UF

10V
10%
X5R
0402
COMMON

C37
.1UF

10V

X5R
0402
COMMON

C40
.1UF

10V
10%
X5R
0402
COMMON

A3V3

C19

4.7UF

6.3V
10%
X5R
0603
COMMON

LB524

C1103

4.7UF

6.3V
10%
X5R
0603
COMMON

LB11

BEAD_0603

C30

4.7UF

6.3V
10%
X5R
0603
COMMON

C55
.1UF

10V
10%
X5R
0402
COMMON

180R@100MHz

COMMONBEAD_0603

180R@100MHz

COMMON

C1104

4.7UF

6.3V
10%
X5R
0603
COMMON

C29

4.7UF

6.3V
10%
X5R
0603
COMMON

A3V3

600-10317-0002-100

design
John Lam

17 OF 28

31-MAY-2005

18 Multi-use IO(MIO) Interface

INBIIN

MIOD<11>
MIOD<10>

MIOD<9>
MIOD<8>
MIOD<7>
MIOD<6>
MIOD<5>
MIOD<4>
MIOD<3>
MIOD<2>
MIOD<1>
MIOD<0>

MIOCLK

MIODE

MIOVSYNC

MIOHSYNC

SWAP_RDY

GND
GND
GND
GND
GND
GND

RSVD

RSVD

RSVD

IN

IN

14/24 MIOA

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8

MIOAD9
MIOAD10
MIOAD11

MIOA_DE

MIOA_CLKIN

MIOA_CTL3

MIOA_VSYNC

MIOA_HSYNC

MIOA_CLKOUT

MIOA_CLKOUT

MIOACAL_PD_VDDQ

MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ

MIOA_VREF

MIOA_VDDQ

MIOACAL_PU_GND

15/24 MIOB

MIOBD0

MIOBD1

MIOBD2

MIOBD3

MIOBD4

MIOBD5

MIOBD6

MIOBD7

MIOBD8

MIOBD9
MIOBD10
MIOBD11
MIOBD12
MIOBD13
MIOBD14
MIOBD15
MIOBD16
MIOBD17
MIOBD18
MIOBD19
MIOBD20
MIOBD21
MIOBD22
MIOBD23

MIOB_DE

MIOB_CLKIN

MIOB_CLKOUT
MIOB_CLKOUT

MIOB_HSYNC
MIOB_VSYNC

MIOB_CTL3

MIOBCAL_PD_VDDQ

MIOB_VDDQ

MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ

MIOB_VREF

MIOBCAL_PU_GND

INININININ

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

U9
GF-7800-GT-A2

BGA1148

U11
V11
W11
T12
U12

CHANGED

AA4
Y7
V7
V6
V5
U7
Y3
W1
W2
Y4
W5
W6

W3

MIOA_2V5

220R@100MHz

LB515

NV40 Test Data shows this interface requires Vref = 3/4VDDQ
*New: NV41 Uses CTT termination, which requires Vref = 1/2VDDQ

COMMONBEAD_0805

C987

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

C867
.1UF

10V
10%
X5R
0402
COMMON

C894
.01UF

16V
10%
X7R
0402
COMMON

C881
.01UF

16V
10%
X7R
0402
COMMON

C886
.01UF

16V
10%
X7R
0402
COMMON

16MIL

MIOA_VDDQ

3.3 V

C70
.1UF

10V
10%
X5R
0402
COMMON

R66
1K

1%
0402
COMMON

MIOA_VREF

R60
1K

1%
0402
COMMON

GND

MIOACAL_PD_VDDQ

49.9

R65

COMMON

0402

1%

MIOACAL_PU_GND

49.9

R59

COMMON

0402

1%

GND

V3

V2

W7

U4

AA2
Y1

AA5
Y5

AA7

MIOA_DE

MIOA_CLKIN

MIOA_CLKOUT
SNN_MIOA_CLKOUT*

MIOA_HSYNC
MIOA_VSYNC

SNN_MIOA_CTL3

MIO Feature Connector

MIOAD<11..0>

CN1
CON_MIO_26_EDGE

NONPHY
COMMON

0
1
2
3
4
5
6
7
8

9
10
11

SNN_MIOA_RSVD0
SNN_MIOA_RSVD1
SNN_MIOA_RSVD2

10K

R658

COMMON

0402

5%

GND

B3
B7

B11

A3
A7

A11

GND

B5
A9

A13

A12
B12
A10
B10
B9
A8
A6
B6
A5
A4
B4
A2

B2
A1

B8

MIOA_HSYNC
MIOA_VSYNC
MIOA_DEB13

MIOA_CLKOUT

SWAPRDY_AB1

MIOAD<11..0>

20> 16<>

18<

21> 18< 18<

21>

21>

11
10

9
8
7
6
5
4
3
2
1
0

18<
21>

U9

AE11
AE12
AF12
AE13
AF13

AG2

AG1

AF1MIOBCAL_PU_GND

GF-7800-GT-A2

BGA1148
CHANGED

AE6
AG7
AF9
AF8
AE9
AE7
AD8
AD9
AC8
AD7
AD5
AC5
AD4
AF4
AE2
AE1
AE3
AF3
AH2
AH1
AH3
AJ3
AG9
AG8

AF7

AD3

AG3
AG4

AF5
AG5

AE5

SNN_MIOBD12
SNN_MIOBD13
SNN_MIOBD14
SNN_MIOBD15
SNN_MIOBD16
SNN_MIOBD17
SNN_MIOBD18
SNN_MIOBD19
SNN_MIOBD20
SNN_MIOBD21
SNN_MIOBD22
SNN_MIOBD23

SNN_MIOB_DE

MIOB_CLKIN

SNN_MIOB_CLKOUT
SNN_MIOB_CLKOUT*

SNN_MIOB_HSYNC
VIPPCLK

SNN_MIOB_CTL3

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Multi-use IO(MIO) Interface

www.vinafix.vn

0
1
2
3
4
5
6
7
8

9
10
11

MIOBD<11..0>

VIP0
VIP1
VIP2
VIP3
VIP4
VIP5
VIP6
VIP7
STRAPS
STRAPS
STRAPS
STRAPS

220R@100MHz

3V3

A3V3

LB518

BEAD_0805

220R@100MHz

LB519

BEAD_0805

NO STUFF

COMMON

3.3 V

12MIL

C981
1UF

6.3V
10%
X5R
0603
COMMON

GND

C887
.1UF

10V
10%
X5R
0402
COMMON

C869
.01UF

16V
10%
X7R
0402 0402
COMMON

C883
.01UF

16V
10%
X7R

COMMON

MIOB_VDDQ

C74
.1UF

10V
10%
X5R
0402
COMMON

R62
1K

1%
0402
COMMON

MIOB_VREF

R64
1K

1%
0402
COMMON

GND

MIOBCAL_PD_VDDQ

49.9

18<

21>

21>

18<

NET RULES

MIOA_CLKOUT 50OHM

IMPEDANCENET

50OHMMIOA_HSYNC
50OHMMIOA_VSYNC
50OHMMIOA_DE
50OHMMIOAD<11..0>

CRITICAL

1
2
2
2
2

R76

COMMON

0402

1%

49.9

R665

COMMON

0402

1%

GND

GND

R664
10K

5%
0402
COMMON

VIPPCLK

21> 17> 17<

17> 17<

600-10317-0002-100

design
John Lam

18 OF 28

31-MAY-2005

19 PEX: Zero Delay Buffer

OUT

OUT

OUT

OUT

OUT

OUT

NC0
NC1

NC4

NC3

NC5
NC6

NC2

NC7

NC12

NC15

NC9

NC8

NC10

NC14

NC13

NC11

NC16
NC17
NC18
NC19
NC20
NC21
NC22

GND

CLK_OUT*

CLK_OUT

PAD_GND

VDD0
VDD1

CLK_IN
CLK_IN*

IREF

VDDA

IN

IN

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

NET RULES

NET

DIFFPAIRCRITICALIMPEDANCE

ICS9DB202_CLk_OUT
ICS9DB202_CLK_OUT*
ICS9DB202_CLk_OUT_R
ICS9DB202_CLK_OUT_R*

1100DIFF
1100DIFF
1100DIFF
1100DIFF

3V3

LB12

BEAD_0603

LB522

BEAD_0603

C1036
10UF

6.3V

X5R
0805
NO STUFF

180R@100MHz

NO STUFF

180R@100MHz

NO STUFF

GND

2<>

2>

2<>

2>

PEX_REFCLK
PEX_REFCLK*

C59
10UF

6.3V
20%
X5R
0805
NO STUFF

GND

C1023
10UF

6.3V
20%20% 10%
X5R
0805
NO STUFF

GND

GND

Place near ICS9DB

Pleace 0.047uF near pin

C60
.047UF

16V
10%
X7R
0402
NO STUFF

C58
.047UF

16V
10%
X7R
0402
NO STUFF

GND

C57
.047UF

16V

X7R
0402
NO STUFF

GND

R49

R45

49.9

49.9

1%

1%

0402

0402

NO STUFF

NO STUFF

GNDGND

12MIL
ICS9DB202_VDD

12MILGND
ICS9DB202_VDDA

R40
475

1%
0402
NO STUFF

U6
ICS9DB202-01

MLF32

MLF32
NO STUFF

13
20

3

4
5

1ICS9DB202_IREF

ICS9DB202_CLk_OUT

9

ICS9DB202_CLK_OUT*

10

SNN_ICS9DB202_NC0

2

SNN_ICS9DB202_NC1

6

SNN_ICS9DB202_NC2

7

SNN_ICS9DB202_NC3

8

SNN_ICS9DB202_NC4

11

SNN_ICS9DB202_NC5

12

SNN_ICS9DB202_NC6

14

SNN_ICS9DB202_NC7

15

SNN_ICS9DB202_NC8

16

SNN_ICS9DB202_NC9

17

SNN_ICS9DB202_NC10

18

SNN_ICS9DB202_NC11

19

SNN_ICS9DB202_NC12

21

SNN_ICS9DB202_NC13

22

SNN_ICS9DB202_NC14

23

SNN_ICS9DB202_NC15

24

SNN_ICS9DB202_NC16

25

SNN_ICS9DB202_NC17

26

SNN_ICS9DB202_NC18

28

SNN_ICS9DB202_NC19

29

SNN_ICS9DB202_NC20

30

SNN_ICS9DB202_NC21

31

SNN_ICS9DB202_NC22

32

27
33

0402

R53

0402

5%

5%

33R54

NO STUFF

33

NO STUFF

R676

49.9

1%
0402
NO STUFF

GND

Place near ICS9DB

GND

R677

49.9

1%
0402
NO STUFF

ICS9DB202_CLk_OUT_R

ICS9DB202_CLK_OUT_R*

10V

NO STUFF

10%

10V

NO STUFF

10%

Bypass Resistors

C69

.1UF

0402
X5R

C68

.1UF

0402
X5R

R687
0

5%
0402
COMMON

R686
0

5%
0402
COMMON

PEX_REFCLK_OUT

PEX_REFCLK_OUT*

2<>

2<

2< 2<>

ICS9DB202_CLK_OUT
ICS9DB202_CLK_OUT
ICS9DB202_CLK_OUT_R
ICS9DB202_CLK_OUT_R

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
PEX: Zero Delay Buffer

www.vinafix.vn

600-10317-0002-100

design
John Lam

19 OF 28

31-MAY-2005

20 MISC: GPIO, I2C, THERMAL, BIOS, XTAL

INININININ

FAN
+12V
GND

OUT

BI

VCC
VCC

GND

GND

SCL
SDA

NC

SDA

S

D

G

S

D

G

S

D

G

VCC

GND

HOLD
WP
CS

SI

SCK

SO

OUT

OUT

OUTININININ

OUT

OUT

17/24 I2C

I2CC_SDA

I2CC_SCL

I2CH_SDA

I2CH_SCL

19/24 THERMAL

THERMDN (CATHODE)

THERMDP (ANODE)

BIINOUT

24/24 MISC

ROMCS

ROM_SCLK

BUFRST

ROM_SI
ROM_SO

STEREO

TESTMODE

CLAMP

SWAPRDY_A

RFU

RFU
RFU
RFU

RFU

RFU
RFU

18/24 GPIO

GPIO<12>

GPIO<11>

GPIO<10>

GPIO<9>

GPIO<7>
GPIO<8>

GPIO<6>

GPIO<4>
GPIO<5>

GPIO<3>

GPIO<2>

GPIO<1>

GPIO<0>

IN

11/24 PLLVDD

VID_PLLVDD

VID_PLLAVDD

VID_PLLGND

PLLVDD

PLLAVDD

PLLGND

VDD

THERM
ALERT

GND

D+
D-

SDA

SCL

16/24 XTAL

XTALOUTBUFF

XTALOUT

XTALSSIN

XTALIN

IN

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

Thermal Diode

A3V3

R52

C64
.1UF

10V
10%
X5R
0402
NO STUFF

200

1%
0603
NO STUFF

12MIL
THERM_VDD

A3V3

THERM_THERM*
THERM_ALERT*

A3V3

R50

2.2K

5%

R51

2.2K

5%
04020402
NO STUFFNO STUFF

GND

GND

I2CC_SCL
I2CC_SDA

C72U7
2200PF

16V
10%
X7R
0402
NO STUFF

3.3 V

LM99CIMM

SO8_122MIL

NO STUFF

1

4
6

5

2
3

8
7

THERMDN

THERMDP

U9
GF-7800-GT-A2

BGA1148
CHANGED

T1

U1

D- Connects to CATHODE
D+ Connects to ANODE

I2CC / I2CH(+ HDCP ROM)

U9
GF-7800-GT-A2

BGA1148
CHANGED

I2CC_SCL_RP8

P9

I2CC_SDA_R

I2CH_SCL

U9

I2CH_SDA

V9

3V3

R734

2.2K

5%
0402
COMMON

3V3

0402

R47

0402

I2CC_SCL
I2CC_SDA

33R48

COMMON

5%

33

COMMON

5%

16>
20<

3V3

R737

2.2K

5%
0402

R692
10K

5%
0402
NO STUFF

GND

COMMON

R695
10K

5%
0402
NO STUFF

16<

16<>

17<

17<>

I2CH_SCL

I2CH_SDA

SNN_CRYPT

6

5
3

2

U507

AT88SC0808C
SO8
NO STUFF

3V3

8

C1050

7

.1UF

10V
10%

4

X5R

1

0402
NO STUFF

GND

NET RULES

IMPEDANCENET

XTALIN
XTALOUT
XTALSSIN

THERMDN
THERMDP

50OHM
50OHM
50OHM

50OHM
50OHM

CRITICAL

1
1
1

2
2

PLLVDD/VID_PLLVDD

*Option to source PLLVDD with 2.5V

A3V3MIOA_2V5

PLLVDD_SELECT

0

R800

COMMON

0402

5%

0

R801

NO STUFF

0402

5%

A3V3

C992

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

Place near Input Ferrite Bead of PLLVDD

180R@100MHz

LB512

BEAD_0603

180R@100MHz

LB513

COMMON

COMMONBEAD_0603

U9
GF-7800-GT-A2

BGA1148
CHANGED

3.3 V12MIL

AB11

AB12

C979

4.7UF

6.3V
10%
X5R
0603
COMMON

C889
.1UF

10V
10%
X5R
0402
COMMON

C902
.01UF

16V
10%
X7R
0402
COMMON

VID_PLLVDD

AA12

GND

C980

4.7UF

6.3V
10%
X5R
0603
COMMON

C918
.1UF

10V
10%
X5R
0402
COMMON

C903
.01UF

16V
10%
X7R
0402
COMMON

12MIL 3.3 V

PLLVDD

12MIL 1.4 V

PLLAVDD

AC11

AC12

AD12

NVVDD

180R@100MHz

LB511

COMMON

BEAD_0603

C995

4.7UF

6.3V
10%
X5R
0603
COMMON

XTAL

16>
20<

XTALSSIN

AD2

AD1

XTALIN

C62
18PF

50V
5%
C0G
0402
COMMON

GND

GND

U9
GF-7800-GT-A2

BGA1148
CHANGED

Y2

H10SSMD

C978

4.7UF

6.3V
10%
X5R
0603
COMMON

XTAL_4PIN

C882
.1UF

10V
10%
X5R
0402
COMMON

10 PPM 85C
COMMON

C872
.01UF

16V
10%
X7R
0402
COMMON

XTALOUT27 MHZ

AC1

GND

XTALOUTBUFFAB3

GND

C61 R63
18PF

50V
5%
C0G
0402
COMMON

2.2K

5%
0402
COMMON

GND

GPIO

U9
GF-7800-GT-A2

BGA1148
CHANGED

GPIO0_DVI_A_HPDN3
GPIO1_DVI_C_HPD

U3

TP_GPIO2

T4

TP_GPIO3

R2

GPIO4_VTG_RST

N1

GPIO5_VSEL0

T3

GPIO6_VSEL1

T5

GPIO7_FL_IO

P1

GPIO8_GPU_SLOW*

M2

GPIO9_FAN_CTRL

N2

GPIO10_FL_INT

R1

GPIO11_DACB_RSETR3

P3

5V

5

1

2

26>

THERM_ALERT*

GPIO12_EXT12V_PRSNT

ROM / MISC

U9
GF-7800-GT-A2

BGA1148
CHANGED

SNN_MISC0
SNN_MISC1

SNN_MISC2
SNN_MISC3
SNN_MISC4
SNN_MISC5
SNN_MISC6

AB1
AC3

AC9
AB7
AB6
AC7
AB5

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
MISC: GPIO, I2C, THERMAL, BIOS, XTAL

www.vinafix.vn

U5

SN74AHCT1G08

4

SC70-5
NO STUFF

3

GPIO8_GPU_SLOW_R*

GND

(BUFRST/STEREO/SWAPRDY/CLAMP/TESTMODE)

AC4

AB2
AA3
AA1

U5

Y12

N9

R12

V1

NO STUFF

NO STUFF

5V

GND

TP5

TP516

R41

0402

C56
.1UF

10V
10%
X5R
0402
NO STUFF

15>
15>

16>
26<
26<
16>

16<>

16<

1%

ROM_CS*

ROM_SI
ROM_SO
ROM_SCLK

BUFRST*

STEREO

SWAPRDY_A

18MIL

5V_CLAMP

TESTMODE

Bypass for AND Gate

1K

NO STUFF

5 V

R61
10K

5%
0402
COMMON

GND GND

GPIO Assignment Table

IN
IN
N/A
N/A
IN
OUT
OUT
IN
IN
OUT
I/O
OUT
I/O

GPIO12_EXT12V_PRSNT

0

COMMON

0

NO STUFF

R37
10K

5%
0402
COMMON

Function

DVI HOTPLUG DET A
DVI HOTPLUG DET C

VTG RESET (FL)
VOLTAGE SELECT 0
VOLTAGE SELECT 1
Framelock IO
GPU_SLOW*
PWM FAN
Framelock Int
DACB RSET
Detect Ext 12V

THERM_ALERT*

3V3

R689

0402

Place far away from GPU

GPIO I/O

0
1
2
3
4
5
6
7
8
9
10
11
12

R44

0402

5%

R46

0402

5%

3V3

21>

C871
.1UF

10V
10%
X5R
0402
COMMON

R722
10K

5%
0402
COMMON

5%

0

CHANGED

FAN CONTROL

12V

3V3

R735
1K

1%
0402
NO STUFF

1G1D1S

GPIO9_FAN_CTRL

THERM_THERM*

U3

AT25F1024A
SO8
SO8
COMMON

7
3
1

5
2
6

3V3

R30
10K

5%
0402
COMMON

5V

8

4

17< 16<
16<
16<> 18<>

1

R732
1K

1%
0402
COMMON

1G1D1S

GND

1

3V3

C46
.1UF

10V
10%
X5R
0402
COMMON

GND

R731
1K

1%
0402
COMMON

FAN_PWM_B

3

Q525

BSS138
SOT23_1G1D1S
COMMON

2

MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V

FAN_PWM_T

3

Q524

BSS138
SOT23_1G1D1S
COMMON

2

MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V

GND

1G1D1S

C1065
1UF

16V
20%
X7R
0805
COMMON

1

R738
0

5%
0402
NO STUFF

D9

1

BAT43
SOD323
40V
400MA

2

COMMON

L6

SMD_4_5X4_0MM

3

FAN_PWM_C

Q523

IRLML2502
SOT23_1G1D1S
COMMON

2

MAX_VOLTAGE=20V
CONTINUOUS_CURRENT=3.4A
R_DS_ON=0.08R
MAX_CURRENT=20A
MAX_WATTAGE=0.8W@70C
V_BE_GS=+/-12V

GND

22uH

COMMON

C1079
.1UF

16V
10%
X7R
0603
COMMON

FAN_PWM_D

C1072

4.7UF

16V
20%
X7R
1206
COMMON

1
2

J8

HDR_1M2_FAN_HI_TEMP
MALE

2.5MM
0
NORM
CHANGED

600-10317-0002-100

design
John Lam

20 OF 28

31-MAY-2005

21 Strapping Configuration

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

OUT

OUT

OUT

OUT

MIOAD<11..0>

MIOBD<12..0>

MIOAD<1>

1

MIOAD<2>

2

MIOAD<3>

3

MIOAD<4>

4

MIOAD<5>

5

MIOBD<2>

2

MIOAD<7>

7

MIOAD<10>

10

17>

18<

17<
18<

MIOBD<4>

4

MIOBD<5>

5

MIOBD<0>

0

MIOBD<1>

1

MIOBD<8>

8

MIOBD<9>

9

MIOBD<3>

3

18<

MIOA_HSYNC

MIOBD<6>

6

20<

ROM_SI

MIOBD<10>

10

MIOBD<11>

11

MIOA_2V5

HW STRAP Hi

R682

10K

0402

NO STUFF

5%

R34

10K

0402

COMMON

5%

R35

10K

0402

NO STUFF

5%

R43

10K

0402

COMMON

5%

R38

10K

0402

NO STUFF

5%

R33

10K

0402

NO STUFF

5%

HW STRAP Hi

R707 10K

0402

NO STUFF

5%

R708

2.2K

0402

NO STUFF

5%

10K

10K

NO STUFF

10K

COMMON

10K

NO STUFF

10K

COMMON

2.2K

NO STUFF

10K

MIOAD<1>

MIOAD<2>

MIOBD<0>

MIOBD<1>

MIOBD<8>

MIOBD<9>

ROM_SI

MIOBD<10>

MIOBD<11>

PC Strap

R720

04025%COMMON

R32

0402

5%

R36

0402

5%

R42

0402

5%

R39

0402

5%

Strap overide for Scalability Connector

R31

0402

5%
Check Polarity of signal, need to Disable Bridge
*Can this be a BIOS overide only?

HW STRAP Low

R709

04025%COMMON

Standardized Straps
SUBVENDOR
ROMTYPE[1:0]
PCI_AD
BUS_TYPE
RAMCFG[3:0]
USER[0]
DEVID[3]

A3V3

BOOT_0_STRAP_0

NV41-A01

*

*

00: PCI_AD_SWAP

01: SUB_VENDOR

02: RAM_CFG_0

03: RAM_CFG_1

04: RAM_CFG_2

05: RAM_CFG_3

06: CRYSTAL_0

07: TV_MODE_0

08: TV_MODE_1

09: AGP4x/8x

10: AGP_SBA

11: AGP_FASTWR

12: PCI_DEVID_0

13: PCI_DEVID_1

14: BUS_TYPE

15: FP_IFACE

16: USER_0

17: USER_1

18: USER_2

19: USER_3

20: PCI_DEVID_2

21: PCI_DEVID_3

22: CRYSTAL_1

23: FB_0

24: FB_1

25: BR

26: BR_128M

27: BR_AGP

28: BR_IO

29: ROM_TYPE_0

30: ROM_TYPE_1

31: STRAP_0_OVERWRITE

NV41-A02
NV42/G70

16: USER_0

*

17: USER_1

18: USER_2

19: USER_3

*

02: RAM_CFG_0

*

03: RAM_CFG_1

*

04: RAM_CFG_2

*

05: RAM_CFG_3

*

21: PCI_DEVID_3

AND MASK
1 -> HARDWARE STRAP
0 -> BIOS STRAP

OR MASK
1 -> DESIRED=1 ANDMASK=0

SKU#

0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0

0
0

(256Mb)

0000

DESIRED

AND MASK

0 00
1

1

1 00

0
0 00
1

0
0 0
0 0
0
0
1
1
1
0 0
0 00
0
0
0
0
11 0 1

0 0010

OR MASK

0 1
01 0
01

0

1

0 0

0 0

0
0 0
0 0

0
1
0

0 0
0
0

DESIRED

0
00
01

10
000
000

00
001
000

0

00
0
1

00

0
0

0

(256Mb)

xxxx

AND MASK

0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0

OR MASK

0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0

BOOT_3_STRAP_1

00: 1394

01: 1394_PHY

02: 1394_PHY_PWRCLASS[0]

03: 1394_PHY_PWRCLASS[1]

MIOBD<12>

12

MIOAD<0>

0

MIOAD<6>

6

MIOAD<8>

8

MIOAD<9>

9

HW STRAP Low

R680

04025%NO STUFF

*NOTE: Mobile Designs must provide the 3GPIO Strap Options
*NOTE: Mobile Designs must provide the 3GPIO Strap Options
*NOTE: Mobile Designs must provide the 3GPIO Strap Options

GND

10K

MIOAD<0>

R678

04025%NO STUFF

2.2K

04: VGA_DEVICE

05: MEM_LSB_SWAP

06: BR_LAST_DEV

07: BR_BAR1_BCASTONLY

08: SUBSYSTEM_USER

09: BOARD

10: FPB_IFACE

*

11: PEX_PLL_EN_TERM100

12: 3GIO_PADCFG_LUT_ADR[0]

13: 3GIO_PADCFG_LUT_ADR[1]

14: 3GIO_PADCFG_LUT_ADR[2]

31: STRAP_1_OVERWRITE

0

0 0 0

0

0 0

0

0

0

0 000
0
0

0 0 0
0
0
0
0
0
0
0

0
0

0
0
0 0 00

0 0 00

0

00000
00 0
0 01
0
0
000

0

0

0

0

0

0

0

0

0

0

000

0

0

0

0

00

0

0

0

0

0

000

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

NV41-A01 Strap Mapping

Last Checked Dec 19, 2003

NV_STRAP_0

----------------------------------------­BIT FUNCTION NORMAL PIN (RTL Name)

HW Default

----------------------------------------­0 PCI_AD `NV_PEXTDEV_BOOT_0_STRAP_PCI_AD_NORMAL

1

1 SUB_VENDOR MIOAD1 (Ccira_data[1])
2 RAMCFG[0] MIOAD2 (Ccira_data[2])
3 RAMCFG[1] MIOAD3 (Ccira_data[3])
4 RAMCFG[2] MIOAD4 (Ccira_data[4])
5 RAMCFG[3] MIOAD5 (Ccira_data[5])

0

6 CRYSTAL[0] MIOBD2 (Ccirb_data[2])

1

7 TVMODE[0] MIOAD7 (Ccira_data[7])

0

8 TVMODE[1] MIOAD10 (Ccira_data[10])
9 AGP_4X `NV_PEXTDEV_BOOT_0_STRAP_AGP_4X_DISABLED
10 AGP_SBA `NV_PEXTDEV_BOOT_0_STRAP_AGP_SBA_DISABLED
11 AGP_FASTWR `NV_PEXTDEV_BOOT_0_STRAP_AGP_FASTWR_DISABLED

0

12 PCI_DEVID[0] MIOBD4 (Ccirb_data[4])

0

13 PCI_DEVID[1] MIOBD5 (Ccirb_data[5])
14 AGP `NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI
15 FP_IFACE `NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT
16 Strap_user[0] MIOBD0 (Ccirb_data[0])
17 Strap_user[1] MIOBD1 (Ccirb_data[1])
18 Strap_user[2] MIOBD8 (Ccirb_data[8])
19 Strap_user[3] MIOBD9 (Ccirb_data[9])

0

20 PCI_DEVID[2] MIOBD3 (Ccirb_data[3])

0

21 PCI_DEVID[3] MIOA_HSYNC (ccira_hsync)
22 CRYSTAL[1] MIOBD6 (Ccirb_data[6])
23 FB[0] 0
24 FB[1] 1

1

25 BR ROM_SI (Rom_si)
26 BR_128M `NV_PEXTDEV_BOOT_0_STRAP_BR_REG_128M_DISABLED
27 BR_AGP `NV_PEXTDEV_BOOT_0_STRAP_BR_AGP_DEV_DISABLED
28 BR_IO `NV_PEXTDEV_BOOT_0_STRAP_BR_IO_DEV_DISABLED

1

29 ROMTYPE[0] MIOBD10 (Ccirb_data[10])

0

30 ROMTYPE[1] MIOBD11 (Ccirb_data[11])

NV_STRAP_1

----------------------------------------­BIT FUNCTION NORMAL PIN (RTL Name)

----------------------------------------­0 1394 `NV_PEXTDEV_BOOT_3_STRAP_1_1394_DISABLED
1 1394_PHY `NV_PEXTDEV_BOOT_3_STRAP_1_1394_PHY_DISABLED
2 1394_PHY_PWRCLASS[0] 0
3 1394_PHY_PWRCLASS[1] 0
4 VGA_DEVICE `NV_PEXTDEV_BOOT_3_STRAP_1_VGA_DEVICE_ENABLED
5 MEM_LSB_SWAP `NV_PEXTDEV_BOOT_3_STRAP_1_MEM_LSB_SWAP_DISABLED
6 BR_LAST_DEV `NV_PEXTDEV_BOOT_3_STRAP_1_BR_LAST_DEV_DISABLED
7 BR_BAR1_BCASTONLY `NV_PEXTDEV_BOOT_3_STRAP_1_BR_BAR1_BCASTONLY_ENABLED
8 SUBSYSTEM_USER `NV_PEXTDEV_BOOT_3_STRAP_1_SUBSYSTEM_USER_DISABLED
9 BOARD `NV_PEXTDEV_BOOT_3_STRAP_1_BOARD_0

1

10 FPB_IFACE MIOBD12 (Ccirb_data[12])

0

11 PEX_PLL_EN_TERM100 MIOAD0 (Ccira_data[0])

0

12 3GIO_PADCFG_LUT_ADR[0] MIOAD6 (Ccira_data[6])

0

13 3GIO_PADCFG_LUT_ADR[1] MIOAD8 (Ccira_data[8])

0

14 3GIO_PADCFG_LUT_ADR[2] MIOAD9 (Ccira_data[9])

*HW has Internal 10K Strap, need 1K to overide

NV41-A02 Strap Mapping

NV_STRAP_0

--------------------------------------------------------------------------­BIT FUNCTION NORMAL PIN (RTL Name)

--------------------------------------------------------------------------­0 PCI_AD `NV_PEXTDEV_BOOT_0_STRAP_PCI_AD_NORMAL
1 SUB_VENDOR MIOAD1 (Ccira_data[1])
2 RAMCFG[0] MIOBD0 (Ccirb_data[0])
3 RAMCFG[1] MIOBD1 (Ccirb_data[1])
4 RAMCFG[2] MIOBD8 (Ccirb_data[8])
5 RAMCFG[3] MIOBD9 (Ccirb_data[9])
6 CRYSTAL0 MIOBD2 (Ccirb_data[2])
7 TVMODE[0] MIOAD7 (Ccira_data[7])
8 TVMODE[1] MIOAD10 (Ccira_data[10])
9 AGP_4X `NV_PEXTDEV_BOOT_0_STRAP_AGP_4X_DISABLED
10 AGP_SBA `NV_PEXTDEV_BOOT_0_STRAP_AGP_SBA_DISABLED
11 AGP_FASTWR `NV_PEXTDEV_BOOT_0_STRAP_AGP_FASTWR_DISABLED
12 PCI_DEVID10[0] MIOBD4 (Ccirb_data[4])
13 PCI_DEVID10[1] MIOBD5 (Ccirb_data[5])
14 AGP `NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP
15 FP_IFACE `NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT
16 USER[0] MIOAD2 (Ccira_data[2])
17 USER[1] MIOAD3 (Ccira_data[3])
18 USER[2] MIOAD4 (Ccira_data[4])
19 USER[3] MIOAD5 (Ccira_data[5])
20 PCI_DEVID32[0] MIOBD3 (Ccirb_data[3])
21 PCI_DEVID32[1] MIOBD11 (Ccirb_data[11])
22 CRYSTAL1 MIOBD6 (Ccirb_data[6])
23 FB[0] 0
24 FB[1] 1
25 BR ROM_SI (Rom_si)
26 BR_128M `NV_PEXTDEV_BOOT_0_STRAP_BR_REG_128M_DISABLED
27 BR_AGP `NV_PEXTDEV_BOOT_0_STRAP_BR_AGP_DEV_DISABLED
28 BR_IO `NV_PEXTDEV_BOOT_0_STRAP_BR_IO_DEV_DISABLED
29 ROMTYPE[0] MIOBD10 (Ccirb_data[10])
30 ROMTYPE[1] 0

Updated May 19, 2004

SUB_VENDOR[0]

RAM_CFG[3:0]

CRYSTAL[1:0]

TVMODE[1:0]

PCI_DEVID[3:0]

USER[3:0]

FB[1:0]

ROM_TYPE[1:0]

BR

FPB_IFACE

PEX_PLL_EN_TERM100

3GIO_PADCFG_LUT_ADR[2:0]

STRAP_OVERWITE

0 - NO_BIOS
1 - READ FROM BIOS (DESIRED)

0000 N/A
0001 N/A
0010 N/A
0011 N/A
0100 N/A
0101 N/A
0110 N/A
0111 8PCS 8Mx32 SAMSUNG DDR3

00 - 13.5 MHz
01 - 14.31818 MHz
10 - 27.000 MHz (DESIRED)
11 - UNKNOWN

00 - SECAM
01 - NTSC (DESIRED)
10 - PAL
11 - CRT

0000 = NV41 = 0x000
1100 = NV41-U-A1 = 0x0C0

0000 - USER STRAP

00 - 64MEG (DESIRED)
01 - 128MEG
10 - 256MEG
11 - 512MEG

00 - PARALLEL (NOT SUPPORTED)
01 - SERIAL AT25F (DESIRED)
10 - SERIAL SST45VF/LF
11 - RFU

0 - ENABLE
1 - DISABLED (Default)

0 - 12Bit
1 - 24bit (Default)

0 - ENABLED (Internal 100ohm Term)
1 - DISABLED

000 = DEFAULT

0 - DISABLED (DESIRED)
1 - ENABLED

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Strapping Configuration

www.vinafix.vn

600-10317-0002-100

design
John Lam

21 OF 28

31-MAY-2005

22 Power/GND and Decoupling

22/24 GND

GND
GND

GND

GND

GND

GND

GND

GND

GND

GND
GND

GND

GND

GND

GND

GND
GND

GND

GND

GND

GND

GND

GND

GND

GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND
GND

GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND

GND

GND
GND

GND

GND

GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND

GND
GND

GND

GND
GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND

GND

GND
GND

GND

GND

GND

GND
GND

GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND

GND

GND

GND
GND

GND

GND

GND

GND
GND

GND

GND
GND

GND
GND

GND
GND

GND

GND

GND

GND

GND
GND

GND

GND

GND
GND

GND

GND

GND
GND

GND
GND

GND
GND

GND
GND

GND

GND

GND
GND

GND

GND

GND

GND
GND

GND

GND

GND

GND
GND

GND

GND

GND
GND
GND

GND

GND

GND

GND

GND

GND

GND
GND

GND

GND

GND
GND
GND

GND
GND
GND

GND
GND

GND

GND

GND
GND

GND

GND

GND

GND

GND

OUT

20/24 VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD
VDD

VDD

VDD
VDD

VDD

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD
VDD
VDD

VDD
VDD
VDD
VDD
VDD

VDD
VDD
VDD

VDD

VDD

VDD
VDD
VDD
VDD

VDD
VDD
VDD

VDD

VDD

VDD

VDD

VDD_SENSE
GND_SENSE

6/24 FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ
FBVDDQ

FBVDDQ
FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ
FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ
FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ
FBVDDQ
FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

21/24

VDD33

NC
NC

NC

NC
NC

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33
VDD33

7/24 VTT

FBVTT
FBVTT
FBVTT
FBVTT
FBVTT

FBVTT
FBVTT
FBVTT
FBVTT
FBVTT

FBVTT
FBVTT
FBVTT
FBVTT
FBVTT

FBVTT
FBVTT
FBVTT
FBVTT
FBVTT

FBVTT
FBVTT

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

VDD33

U9
GF-7800-GT-A2

BGA1148
CHANGED

FBVTT

U9
GF-7800-GT-A2

BGA1148
CHANGED

N11
P11
R11
N12
AH15

AJ16
AK16
AJ17
AK17

SNN_GPU_NC0

T2

SNN_GPU_NC1

AE21

SNN_GPU_NC2

AF23

SNN_GPU_NC3

AP23

SNN_GPU_NC4

AJ26

FBVTT is not supported in NV41
GPU ties this net to FBVDDQ

M12
M13
M15
M16
M17

M20
M21
M22
AE22
AE23

M24
AE24
M25
N25
R25

T25
U25
Y25
AA25
AB25

AD25
AE25

A3V3

FBVDDQ

C884
.047UF

6.3V
10%
X5R
0402
COMMON

C810
.1UF

10V
10%
X5R
0402
COMMON

C880
.1UF

10V
10%
X5R
0402
COMMON

GND

GND

GND

GND

C852
.047UF

6.3V
10%
X5R
0402
COMMON

C973
1UF

6.3V
10%
X5R
0603
COMMON

C782

4.7UF

6.3V
10%
X5R
0603
COMMON

C870
.1UF

10V
10%
X5R
0402
COMMON

C891
.1UF

10V
10%
X5R
0402
COMMON

C809
.022UF

16V
10%
X7R
0402
COMMON

C784
.1UF

10V
10%
X5R
0402
COMMON

FBVDDQ

FBVDDQ

Place near BGA

C783
.047UF

6.3V
10%
X5R
0402
COMMON

C757
.047UF

6.3V

X5R
0402
COMMON

C766
.047UF

6.3V
10%
X5R
0402
COMMON

C768
.047UF

6.3V
10%
X5R
0402
COMMON

C844
.047UF

6.3V
10%
X5R
0402
COMMON

C824
.047UF

6.3V
10%
X5R
0402
COMMON

C837

4.7UF

6.3V
10%

C770
.022UF

16V
10%
X7R
0402
COMMON

C748
.022UF

16V

X7R
0402
COMMON

C756
.022UF

16V
10%
X7R
0402
COMMON

C826
.022UF

16V
10%
X7R
0402
COMMON

C879
.022UF

16V
10%
X7R
0402
COMMON

C802
.022UF

16V
10%
X7R
0402
COMMON

C733

4.7UF

6.3V
10%

06030603
COMMONCOMMON

C793
.1UF

10V
10%
X5R
0402
COMMON

C786
.1UF

10V

X5R
0402
COMMON

C777
.1UF

10V
10%
X5R
0402
COMMON

C767
.1UF

10V
10%
X5R
0402
COMMON

C763
.1UF

10V
10%
X5R
0402
COMMON

C825
.1UF

10V
10%
X5R
0402
COMMON

NVVDD

NVVDD

Place near BGA

C878
.1UF

10V
10%
X5R
0402
COMMON

C856
.1UF

10V
10%10%10% 10%
X5R
0402
COMMON

C823
.1UF

10V
10%
X5R
0402
COMMON

C803
.1UF

10V
10%
X5R
0402
COMMON

C741
.1UF

10V
10%
X5R
0402
COMMON

C779
.047UF

6.3V
10%
X5R
0402
COMMON

C769
.1UF

10V
10%

0402
COMMON

GND

GND

GND

GND

GND

GND

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Power/GND and Decoupling

C828
1UF

6.3V
10%
X5R
0402
COMMON

C843
1UF

6.3V
10% 10%10%10%
X5R
0402
COMMON

C807
1UF

6.3V
10%
X5R
0402
COMMON

C832
1UF

6.3V
10%
X5R
0402
COMMON

C776
1UF

6.3V
10%
X5R
0402
COMMON

C812
1UF

6.3V
10%
X5R
0402
COMMON

C847
1UF

6.3V
10%

0402
COMMON

C804

4.7UF

6.3V
10%
X5R
0603
COMMON

www.vinafix.vn

C814
.047UF

6.3V
10%
X5R
0402
COMMON

C829
.047UF

6.3V

X5R
0402
COMMON

C811
.047UF

6.3V
10%
X5R
0402
COMMON

C833
.047UF

6.3V
10%
X5R
0402
COMMON

C778
.047UF

6.3V
10%
X5R
0402
COMMON

C862
.047UF

6.3V
10%
X5R
0402
COMMON

C846
.047UF

6.3V
10%

0402
COMMON

C808
.047UF

6.3V
10%
X5R
0402
COMMON

C827

4.7UF

6.3V
10%
X5R
0603
COMMON

C795
.1UF

10V
10%
X5R
0402
COMMON

C830
.1UF

10V

X5R
0402
COMMON

C831
.1UF

10V
10%
X5R
0402
COMMON

C834
.1UF

10V
10%
X5R
0402
COMMON

C845
.1UF

10V
10%
X5R
0402
COMMON

C796
.1UF

10V
10%
X5R
0402
COMMON

C861
.1UF

10V
10%
X5RX5R X5RX5R X5RX5RX5R
0402
COMMON

C797
.047UF

6.3V
10%
X5R
0402
COMMON

C854

4.7UF

6.3V
10%
X5R
0603
COMMON

C859
.1UF

10V
10%
X5R
0402
COMMON

C835
.1UF

10V

X5R
0402
COMMON

C785
.1UF

10V
10%
X5R
0402
COMMON

C789
.1UF

10V
10%
X5R
0402
COMMON

C842
.047UF

6.3V
10%
X5R
0402
COMMON

C857
.1UF

10V
10%
X5R
0402
COMMON

C813
.1UF

10V
10%

0402
COMMON

U9
U9
GF-7800-GT-A2

BGA1148
CHANGED

R14
V14
W14
AB14
P15

R15
T15
V15
W15
AA15

AB15

GND

GND

GND

GND

GND

GND

GND

GND

GND

AC15
R16
T16
V16

W16
AA16
AB16
P18
R18

T18
V18
W18
AA18
AB18

AC18
P19
R19
T19
V19

W19
AA19
AB19
AC19
R21

T21
V21
W21
AA21
AB21

R22
T22
V22
W22
AA22

AB22
AC22
R23
V23
W23
AB23

P22
P23

NVVDD

NVVDD_SENSE
TP_GND_SENSE

Testpoint if not used

FBVDDQ

L12
L13
J14
L14
J15

L15
J17
L17
J18
L18

J19
L19
J20
L20
J22

L22
J23
L23
L24

AF24

L25
M26
N26
P26
R26

U26
V26
W26
Y26

AB26

AC26
AD26
AE26
AF26

K28

U28
V28
W28
Y28

AA28

AD28
AE28

L29

AA29

50OHM

1

U9
GF-7800-GT-A2

BGA1148
CHANGED

27<

TP514

NO STUFF

GND

GF-7800-GT-A2

BGA1148

CHANGED

M19
U19

Y19
AE19
AJ19
AL19
AT19

B20

P20

R20

T20

U20

V20

W20

AA20
AB20
AC20
AP20

F21

L21

P21

U21

Y21
AC21
AF21
AR21

D22

H22

U22

Y22
AF22
AK22
AT22

B23

M23

T23

U23

Y23
AA23

AC23

F24
AL24
AP24

D25

H25

P25

V25

W25
AC25

AF25
AJ25
AN25

B26

L26

T26
AA26
AR26

F27
AJ27

AL27

B29

E29

M29

R29

V29

W29
AB29
AG29
AM29

AR29

G30
AK30

K31

N31

T31
AA31
AD31
AG31

B32

E32

H32
AJ32
AM32
AR32

M33

R33

V33

W33
AB33

AE33

B35

E35

H35

L35

P35

U35

Y35
AC35
AF35

AJ35
AM35
AR35
AH14

600-10317-0002-100

design
John Lam

B2
E2
H2
L2
P2
U2
Y2
AC2
AF2
AJ2

AM2
AP3
M4
R4
V4Y20
W4
AB4
AE4
B5
E5

H5
AJ5
AM5
AR5
K6
N6
T6
AA6
AD6
AG6

AT7
B8
E8
H8
M8
R8
V8
W8
AB8
AE8

AJ8
AM8
AP8
F10
AT10
B11
M11
T11
AA11
AD11

AF11
AK11
AP11
D12
P12
V12
W12
AJ12
AR12
F13

AL13
AT13
B14
H14
M14
P14
T14
U14
Y14
AA14

AC14
AE14
AP14
D15
H15
U15
Y15
AJ15
AR15
F16

L16
P16
U16
Y16
AC16
AF16
AL16
AT16
B17
P17

R17
T17
U17
V17
W17
Y17
AA17
AB17
AC17
AP17

D18
H18
M18
U18
Y18
AE18
AJ18
AR18
D19
H19

22 OF 28

31-MAY-2005

GND

23 Power Supply I: TMDS/MIOA/DACB Alternate Supplies

IN

POLYSWITCH

OUT

ADJ

GND

IN

EN

D

S

G

D

S

G

C

E

B

S

D

G

C

E

B

C

E

B

OUT

ADJ

GND

IN

EN

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

MIOA_VDDQ

R684
1K

1%
0402
CHANGED

431_CATHODE

1B1C1E

1

3V3

GND

Q521

MMBT2222A
SOT23_1B1C1E
NO STUFF

C1022
22UF

6.3V
20%
X5R
0805
COMMON

3

2

GND

125

6

1G4D1S

U505

SC431

ADJ_VR2.495

SOT23
SOT23

COMMON

TSOP6_1G4D1S

FDC637AN

Q519

3

2

3

GND

MAX_VOLTAGE=20V

R_DS_ON=0.024 at 4.5V

V_BE_GS=+/-8V

MAX_CURRENT=20A

CONTINUOUS_CURRENT=6.2A

MAX_WATTAGE=1.6W

4

COMMON

1

MIOA_2V5 = 2.5V @.8A

2.5V

C996
10UF

6.3V
20%
X5R
0805

Rtop

Rbot

NO STUFF

GND

R675
0

5%
0402
COMMON

431_ADJ

R673
1K

1%
0402
NO STUFF

16MIL

.8A

MIOA_2V5

C1028
100UF

COMMON
+/-20%

4.0V
POSCAP

1.4A

0.035R
SMD_3528

5V

C1017
.1UF

16V
10%
X7R
0603
COMMON

GND

5V

NVVDD

R714
1K

1%

1B1C1E

0402
NO STUFF

1

431_EN1

R712
3K

5%
0402
NO STUFF

GND

R705
3K

5%
0402
NO STUFF

431_EN2

3

Q522

MMBT2222A
SOT23_1B1C1E
NO STUFF

2

GND

Vout = Vref * (1+Rtop/Rbot)
Vout = 2.5V * (1+0R/NO STUFF) = 2.5V

DACB Supply

3V35V

U504

LX8211

ADJ_VR=1.175V

SOT23-5
SOT23-5
NO STUFF

1

3

C993

4.7UF

6.3V
10%
X5R
0603
NO STUFF

GND GND

C994
.047UF

16V
10%
X7R
0402
NO STUFF

Vout = VRef * (1+Rtop/Rbot)

3.31V = 1.175V * (1+1820/1000)

5

4

2

Rtop

R674

1.82K

1%
0402
NO STUFF

DACB_VDD_ADJ

R679
1K

1%
0603
NO STUFF
Rbot

GNDGND GND

3.3V

C990
.047UF

16V
10%
X7R
0402
NO STUFF

.12A

DACB_VDD

GND

C986

4.7UF

6.3V
10%
X5R
0603
NO STUFF

DDC_5V

5V

1

2

C1145

4.7UF

6.3V
10%
X5R
0603

GND

GND

F501
200mA

1206
COMMON

5V_POLY

LB526
220R@100MHz

COMMON
BEAD_0805
16MIL

C1144
220PF

50V
5%
C0G
0603
COMMONCOMMON

DDC_5V

GND

*E-DDC v1.1 spec requires only 50mA per connector
*Stereo requires 300mA per connector

.12A5V

16MIL

5V5V_POLY

16MIL

GND

0V

TMDS PLL Supply

C1008

4.7UF

6.3V
10%
X5R
0603
NO STUFF

3V3

U506

LX8211

ADJ_VR=1.175V

SOT23-5
SOT23-5

1

3

NO STUFF

5

4

2

C1007
.047UF

16V
10%
X7R
0402
NO STUFF

GND

IFP_PLL_ADJ

5V

GND

GNDGND

A3V3

Rtop

R683

1.82K

1%
0402
NO STUFF

R688
1K

1%
0603
NO STUFF
Rbot

LB520
220R@100MHz

COMMON
BEAD_0805

GND

16MIL

.12A3.3V

C1003
.047UF

16V
10%
X7R
0402
NO STUFF

IFP_PLLVDD

GND

C998

4.7UF

6.3V
10%
X5R
0603
COMMON

TMDS IOVDD Backdrive Prevention

A3V3 Source

A3V3 Enable

A3V3 = 2.8V, IFP_IOVDD_EN = 0.7V
A3V3 = 3.3V, IFP_IOVDD_EN = 1.1V

A3V3

R698

3.09K

1%
0402
COMMON

IFP_IOVDD_EN

R697
1K

1%
0402
COMMON

1B1C1E

1

IFP_IOVDD_EN_G

3

Q520

MMBT2222A
SOT23_1B1C1E
COMMON

2

GNDGND

R685

2.2K

5%
0402
COMMON

1G1D1S

A3V3

3

Q516
SI2305DS

SOT23_1G1D1S

1

COMMON

2

MAX_VOLTAGE=-8V
CONTINUOUS_CURRENT=-2.8A@70C
R_DS_ON=52mR
MAX_CURRENT=-6A
MAX_WATTAGE=0.8W@70C
V_BE_GS=+/-8V

GND

ALT: PEX 3V3 Source

3V3

220R@100MHz
LB521

BEAD_0805 NO STUFF

C1040

4.7UF

6.3V
10%
X5R
0603
NO STUFF

GND

1G1D1S

Current Draw

Single Link: I=0.28A
Dual Link/2x Single Link: I=0.56A
Single Link + Dual Link: I=0.84A
Dual Link + Dual Link: I=1.12A

C999

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

C1000
22UF

6.3V
20%
X5R
0805
COMMON

GND

3V3_IFP

C1021

4.7UF

6.3V
10%
X5R
0603
NO STUFF

1

1.2A3.3V

3

Q518
SI2305DS

SOT23_1G1D1S
NO STUFF

2

16MIL

MAX_VOLTAGE=-8V
CONTINUOUS_CURRENT=-2.8A@70C
R_DS_ON=52mR
MAX_CURRENT=-6A
MAX_WATTAGE=0.8W@70C
V_BE_GS=+/-8V

16MIL

1.2A3.3V

IFP_IOVDD

Vout = VRef * (1+Rtop/Rbot)

2.8V = 1.175V * (1+1400/1000)

3.31V = 1.175V * (1+1820/1000)

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Power Supply I: TMDS/MIOA/DACB Alternate Supplies

www.vinafix.vn

600-10317-0002-100

design
John Lam

23 OF 28

31-MAY-2005

24 Power Supply II: 5V and A3V3

OUT

TAB

GND/ADJ

IN

S

D

G

S

D

G

UGATE

VCC12
PVCC5

BOOT

PHASE

LGATE

SW_FB

COMP

LDO_FB

FS_DIS

LDO_DR

VCC5

GND

PGNDSD

G

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

Alternate 5V regulator

INT_12V_IN

Place near Switcher Output

U15

7805

IGO,IGOI

VR=5V

COMBINED_IGO
NO STUFF

1

C512
.1UF

5V

D506

2

MBRS340T3G

403-03
40V
4A@105C

1

APM3055L

MAX_VOLTAGE=30V

R_DS_ON=0.100R

MAX_CURRENT=30A

V_BE_GS=20V

R517

3.09K

1%
0603
COMMON

R516
1K

1%
0603
COMMON

COMMON

Rtop

Rbot

COMMON

16MIL
A3V3_VIN

1.3A

4
2

Q1

3

1G2D1S

1

GND

Place close to MOSFET

C552
10UF

6.3V
20%

R742
0

N/A
1206
NO STUFF

C524
.047UF

16V
10%
X7R
0402
COMMON

X5R
0805
COMMON

GND

COMBI_MONO_1G2D1S

CONTINUOUS_CURRENT=12A

MAX_WATTAGE=50W@25C

GND

OUTPUT VOLTAGE

Vout = 0.8V * (1 + Rtop/Rbot)
A3V3 = 0.8V * (1 + 3.09K/1K)

3V3

C1102
47UF

R739

6.3V

0

20%

N/A

X5R

1206

1206

NO STUFF

NO STUFF

1.7A

C91
100UF

COMMON
20%
16V
ALE

0.23@105C

0.44R
SMD_D60

16MIL

GND

C528

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

A3V3 @1.7A

A3V3

3.3V

C92
100UF

NO STUFF
+/-20%
10V
ALE

0.146A@85C

3.78R
TH_D50P20

Place in same location as SMD

GND

Alternates:
IRLR3714 - 300-0016-000
IRFR3303 - 300-0043-000
APM3055L - 300-0030-000

Place with 1inch Sq Area for Heat Disipation

C504

R514

2.7K

5%
0402
COMMON

6549_LDO_RC

C518
1000PF

16V
10%
X7R
0402
COMMON

.47UF

16V
10%
X7R
0603
COMMON

GND

R503
10

5%
0805
COMMON

U501

ISL6549CB_600KHZ

VR_SW=0.8V, VR_LD=0.8V

SO14
SO14
COMMON

5V

12MIL
6549_VCC5

12MIL
6549_LDO_DR

12MIL
6549_LDO_FB

6549_FS_DIS

9

5

6

2

12

R505

47.5K

1%
0402
COMMON

GND

7

GND

FREQ_SET = 47.5K for 600khz

8
10

1

14

13

11

4

3

12V

C513
1UF

16V
10%
X5R
0603
COMMON

GND

12MIL
6549_PVCC

12MIL
6549_BOOT

12MIL
6549_UGATE

12MIL
6549_PHASE

12MIL
6549_LGATE

12MIL
6549_FB

12MIL
6549_COMP

Compensation for 5V

C517

C516

0603

0603

INT_12V_IN

C108

1G2D1S

1G2D1S

4

2

R520

GND

0402

1UF

16V
10%
X5R
0603
COMMON

6
5

Q3

FDS6912A

SO8_DUAL_1G2D1S

COMMON

3

8
7

Q3

FDS6912A

SO8_DUAL_1G2D1S

COMMON

1

R3C1

10

COMMON

5%

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=6A
R_DS_ON=0.028R
MAX_CURRENT=20A
MAX_WATTAGE=1.6W@25C
V_BE_GS=20V

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=6A
R_DS_ON=0.028R
MAX_CURRENT=20A
MAX_WATTAGE=1.6W@25C
V_BE_GS=20V

GND

C501

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

5V

C2

.047UF

16V
10%
X7R
COMMON

1000PF

50V
10%
X7R
CHANGED

C3

.1UF

C514

16V

0603

10%
X7R
COMMON

12MIL
6549_COMP_RC

R504

0402

R519

0402

12MIL
6549_UGATE_R

2.2

COMMON

5%

C502
100PF

50V
5%
C0G
0603
NO STUFF

stuff option

GND

R4

5%

10K

COMMON

C515

0603

4700PF

16V
10%
X7R
COMMON

12MIL
6549_FB_RC

Only use this Alternate when A3V3 regulator is not Stuffed

Conditions for Linear 5V:
1- If all Analog 3.3V circuits are tested to +/-10% tolerance
2- 5V Linear will supply DDC 5V + Diode protection circuits
3- Must Not use when Stereo is an Option

Input Ripple = ~1A
Share with FBVDDQ Switcher

Place near Drain of TOP Mosfet

C509

4.7UF

16V
20%
X7R
1206
COMMON

GND

OUTPUT VOLTAGE

5V

GND

Vout = 0.8V * (1 + Rtop/Rbot)
5V = 0.8V * (1 + 6.34K/1.21K)

16V
10%
X7R
0603
NO STUFF

GND

2

GND

Use the same Input and Output Caps

Alternates:
Fairchild: FDS6912(A) - 300-0028-000

L11

7_6X7_6

12MIL

GND

R91

4.3

5%
0805
CHANGED

6549_SNUB

C99
820PF

50V
5%
C0G
0603
COMMON

R522

6.34K

1%
0603
COMMON

R523

1.21K

1%
0603
COMMON

D10

1

IR10MQ040N

SMA
40V

2.1A

2

COMMON

Rtop

Rbot

5V = 5V @200mA

3
4

COMMON

GND

4.7UH

C537
.1UF

16V
10%
X7R
0603
NO STUFF

C533
47UF

20%
X5R
1206 1206
NO STUFF

Default: No Stuff

GND

Shmoo TestPoints

TP502

TESTPOINT2

SCHMOO
NO STUFF

1

5V

PLACE WITHIN 2cm AREA

C532
47UF

6.3V6.3V
20%
X5R

NO STUFF

6549_FB

5V

C534
10UF

6.3V
20%
X5R
0805
COMMON

TP501

TESTPOINT2

SCHMOO
NO STUFF

1

5V @1.5A

5V

TP503

TESTPOINT2

SCHMOO

NO STUFF

1

GND

C98
150UF

COMMON
+/-20%

6.3V
POSCAP

1.5A@45C

0.045R
SMD_7343

16MIL

1.5A

5V

www.vinafix.vn

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Power Supply II: 5V and A3V3

600-10317-0002-100

design
John Lam

24 OF 28

31-MAY-2005

25 Power Supply III: FBVDDQ and PEX_VDD

S

D

G

S

D

G

UGATE

VCC12
PVCC5

BOOT

PHASE

LGATE

SW_FB

COMP

LDO_FB

FS_DIS

LDO_DR

VCC5

GND

PGNDSD

G

IN

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBVDDQ

D504

2

MBRS340T3G

403-03
40V
4A@105C

1

IRFR3303PBF

COMMON

MAX_VOLTAGE=30V

R_DS_ON=0.031R

MAX_CURRENT=120A

V_BE_GS=+/-20V

R538

1.5K

1%
0603
CHANGED

R539
2K

1%
0603
COMMON

Rtop

Rbot

27>

NO STUFF

16MIL

2.5A

PEX_VIN

4
2

Q2

3

Place close to MOSFET

C546
10UF

6.3V
20%
X5R
0805
COMMON

was PEX = 1.2V @2.5A
PEX = 1.4V @2.5A as of 12/15/2004

PEX_VDD

GND

2.5A

1.2V

C88
100UF

NO STUFF
+/-20%
10V
ALE

0.146A@85C

3.78R
TH_D50P20

Place in same location as SMD

C87
100UF

COMMON
20%
16V
ALE

0.23@105C

0.44R
SMD_D60

GND

C83
22UF

6.3V
20%
X5R
0805
COMMON

C85

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

GND

GND

COMBI_MONO_1G2D1S

CONTINUOUS_CURRENT=33A@25C, 21A@100C

MAX_WATTAGE=57W@25C

C86
.047UF

16V
10%
X7R
0402
COMMON

C561
22UF

6.3V
20%
X5R
0805
COMMON

GND

OUTPUT VOLTAGE

Vout = 0.8V * (1 + Rtop/Rbot)

1.2V = 0.8V * (1 + 1K/2K)

1.4V = 0.8V * (1 + 1.5K/2K)

Shmoo TestPoints

TP506

TESTPOINT2

SCHMOO
NO STUFF

1

PEX_VDD

PEX_LDO_FB

PLACE WITHIN 2cm AREA

TP505

TESTPOINT2

SCHMOO

1

TP508

TESTPOINT2

SCHMOO
NO STUFFNO STUFF

1

GND

Bypass Diode when FBVDDQ < 1.9V

R535

R547

0

0

N/A

N/A

1206

1206

COMMON

COMMON

Note: Look into dissipating heat into Resistors
Alternates:
IRFR3303PBF - 300-0043-000
IRLR3714 - 300-0016-000

Use large D2Pak Pad for up to 2W of Disipation

1G2D1S

1

Place close to VCC5 pin

C522

R90

0402

.47UF

16V
10%
X7R
0603
COMMON

GND

0

COMMON

5%

R531

2.7K

5%
0402
COMMON

12MIL
PEX_LDO_RC

C540
1000PF

16V
10%
X7R
0402
COMMON

NVVDD_SSEND

R518
10

5%
0805
COMMON

U502

ISL6549CB_600KHZ

VR_SW=0.8V, VR_LD=0.8V

SO14
SO14
COMMON

5V

12MIL
FBVDDQ_VCC5

12MIL
PEX_LDO_DR

12MIL
PEX_LDO_FB

FBVDDQ_FS_DIS

9

5

6

2

12

R528

47.5K

1%
0402
COMMON

GND

7

GND

FREQ_SET = 47.5K for 600khz

Place close to VCC12 pin

12V

GND

8

12MIL
FBVDDQ_PVCC5

10

12MIL
FBVDDQ_BOOT

1

12MIL
FBVDDQ_UGATE

14

12MIL
FBVDDQ_PHASE

13

12MIL
FBVDDQ_LGATE

11

12MIL
FBVDDQ_FB

4

12MIL
FBVDDQ_COMP

3

C106
180UF

COMMON
+/-20%
16V
OSCON

3.64A@105C

0.020R
COMBI_7343_D80

GND

Place close to PVCC5 pin

C529
1UF

16V
10%
X5R
0603
COMMON

5V

C519

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

.1UF

C526

16V

0603

10%
X7R
COMMON

Compensation for FBVDDQ

C2

12MIL
FBVDDQ_COMP_RC

.047UF

C543

16V

0603

10%
X7R
COMMON

2200PF

C542

50V

0603

10%
X7R
COMMON

C3

Input Ripple = ~7.5A

C107
180UF

COMMON
+/-20%
16V
OSCON

3.64A@105C

0.020R
COMBI_7343_D80

GND

2.2

R515

COMMON

0402

5%

R4

4.22K

R544

COMMON

0402

1%

12MIL
FBVDDQ_UGATE_R

C541

0603

GND

*Default - No Stuff

C508
100PF

50V
5%
C0G
0603
NO STUFF

stuff option

GND

12MIL
FBVDDQ_FB_RC

.022UF

16V
10%
X7R
COMMON

C505
10UF

16V
20%
X5R
1206
NO STUFF

LFPAK

LFPAK

GND

4

4

R543

0402

C506
10UF

16V
20%
X5R
1206
NO STUFF

R3C1

5%

INT_12V_IN

Place near Drain of Top Mosfet

C507

4.7UF

16V
20%
X7R
1206
COMMON

GND

5

Q504
IRF7821

SO8_1G4D3S
CHANGED

1

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=13.6A

2

R_DS_ON=.0091R
MAX_CURRENT=100A

3

MAX_WATTAGE=2.5@25C
V_BE_GS=+/- 20V

5

Q503
IRF7832

SO8_1G4D3S
CHANGED

1

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=20A

2

R_DS_ON=0.004R
MAX_CURRENT=160A

3

MAX_WATTAGE=2.5@25C
V_BE_GS=+/- 20V

GND

OUTPUT VOLTAGE

10

COMMON

FBVDDQ

R533

1.58K

1%
0603
COMMON

R540
1K

1%
0603
COMMON

D501

1

IR10MQ040N

SMA
40V

2.1A

2

COMMON

Rtop

Rbot

Output Inductor Options:
Vishay - 131-0025-000 3.0mOhm, 27A
Vishay - 131-0028-000 4.1mOhm, 23A *default

CONTINUOUS_CURRENT=23A

L10

SMD_590x530

R512

2.2

5%
0805
CHANGED

FBVDDQ_SNUB

12MIL

C510
820PF

50V
5%
C0G
0603
COMMON

GND

COMMON

1.5UH

FBVDDQ = 2.1V - 1.8V @16A

Est. Eff = 85%

16MIL

16A2.7V

C551

C550

47UF

47UF

6.3V6.3V
20%

20%

X5R

X5R

1206

1206

NO STUFF

NO STUFF

*Default - No Stuff

C93
1200UF

COMMON
+/-20%
4V
OSCON

5.44A@105C

0.012R
COMBI_7343D80D1001812

Place in the same location as SMD

C94
1000UF

NO STUFF
+/-20%
4V
OSCON

5.04A@45C

0.012R
COMBI_TH_D80_D100

GND

FBVDDQ

Shmoo TestPoints

FBVDDQ

PLACE WITHIN 2cm AREA

www.vinafix.vn

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Power Supply III: FBVDDQ and PEX_VDD

TP507

TESTPOINT2

SCHMOO
NO STUFF

1

FBVDDQ_FB

TP504

TESTPOINT2

SCHMOO
NO STUFF

1

GND

FBVDDQ = VREF * (1 + Rtop/Rbot)
FBVDDQ = 0.8V * (1 + 1.62K/1K) = 2.1V
FBVDDQ = 0.8V * (1 + 1.62K/1K) = 1.8V

TP509

TESTPOINT2

SCHMOO
NO STUFF

1

GND

600-10317-0002-100

design
John Lam

25 OF 28

31-MAY-2005

26 Power Supply IV: Extermal 12V Power + NVVDD VID Control

D

SGS

D

G

OUT

OUT

OUT

OUT

OUT

S

D

G

S

D

G

IN

IN

S

D

G

+12V

GND

GND

+5V

PRSNT*

GND
12V

12V

12V

GND

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

Internal & External 12V Input Filters

EXT_12V

SNN_EXT_5V_IN

EXT12V_PRSNT*

Place coincident with PCIEPWR_6P

1

2

3

4

6
3
5
2
4
1

GND

J9

HDR_2M3
MALE

4.2MM
90
PCIEPWR
CHANGED

J10

ATXPWR_4P
MALE

5.08MM
0
ATXPWR_VERT
NO STUFF

12V

GND

EXT_12V

GND

C103
47UF

NO STUFF
+/-20%
16V
ALE

0.099A@85C

7.06R
TH_D50P20

C104
47UF

NO STUFF
+/-20%
16V
ALE

0.099A@85C

7.06R
TH_D50P20

NV_SOURCE_POWER_NET=TRUE

INPUT FILTER FOR INTERNAL 12V

7_6X7_6

MAX_CURRENT=7.97A

Source FBVDDQ and 5V switchers

GND

C102
100UF

COMMON
20%
25V
ALE

0.280A@105C

0.34R
SMD_D60

12V

1uH

L12

COMMON

INPUT FILTER FOR EXTERNAL 12V

50MIL4.5A12V

C105
100UF

COMMON
20%
25V
ALE

0.280A@105C

0.34R
SMD_D60

GND

L9

7_6X7_6

MAX_CURRENT=7.97A

12V

1uH

COMMON

Source NVVDD switcher

Bypass External Connector

EXT_12V_IN

R507

1206

R508

1206

R506

1206

50MIL
8A

50MIL
8A

INT_12V_IN

0

NO STUFF

N/A

0

NO STUFF

N/A

0

NO STUFF

N/A

INT_12V_IN

EXT_12V_IN

12V Input Selection for NVVDD

INT_12V_IN

R501

2.2K

D502

BAV99
SOT23
100V
100MA
COMMON

5%
0402
COMMON

C511
1000PF

16V
10%
X7R
0402
COMMON

GND

EXT12V_PRSNT_G*

R502

0603

R509
20K

5%
0402
COMMON

GND

1K

COMMON

1%

20<

GPIO12_EXT12V_PRSNT

EXT12V_PRSNT*

0 = EXT_12V Connected
1 = EXT_12V Disconnected

5V

2

3

1

GND

1G1D1S

GND

R510

1

C503
.1UF

16V
10%
X7R
0603
COMMON

27K

COMMON0402

5%

INT_12V_IN

R511

2.2K

5%
0402
COMMON

12V_SELECT

3

Q501

BSS138
SOT23_1G1D1S
COMMON

2

MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V

GND

1G4D1S

6
5
2
1

Q502
SI3457DV

TSOP6_1G4D1S

3

COMMON

4

MAX_VOLTAGE=-30V
CONTINUOUS_CURRENT=-4A
R_DS_ON=0.075R
MAX_CURRENT=-20A
MAX_WATTAGE=1.6W@70
V_BE_GS=+/-25V

EXT_12V_IN

NVVDD VID CONTROL

Default selection for NVVDD_VID[4..1]

1G1D1S

3

Q515

1

2

10K

D514
BAT54A

30V
200MA
SOT23
COMMON

D513
BAT54A

30V
200MA
SOT23
COMMON

3

R593

0402

5%

R585

0402

R594

0402

SNN_GATE_NC

1

GATE_DEF_R

2

0

NO STUFF

COMMON

5%

GND

1G1D1S

3

Q514

1

2

10K

COMMON

5%

GND

1G1D1S

1

10K

R586

COMMON

0402

5%

additional PDbridge diode

20>
20>

GPIO5_VSEL0
GPIO6_VSEL1

A3V3

R595
10K

5%
0402
COMMON

GATE_DEF

132

3

VOL_1

3

BSS138
SOT23_1G1D1S
COMMON

MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V

3

VOL_2

3

BSS138
SOT23_1G1D1S
COMMON

MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V

3

VOL_DEF

3

3

Q513

BSS138
SOT23_1G1D1S
COMMON

2

MAX_VOLTAGE=50V
CONTINUOUS_CURRENT=0.22A@31C
R_DS_ON=3.5R
MAX_CURRENT=0.88A
MAX_WATTAGE=0.36W@25C
V_BE_GS=+/-20V

GND

D509
BAT54C

25V
200MA
SOT23
COMMON

D512
BAT54C

25V
200MA
SOT23
COMMON

D508
BAT54C

25V
200MA
SOT23
COMMON

D511
BAT54C

25V
200MA
SOT23
COMMON

D507
BAT54C

25V
200MA
SOT23
COMMON

D510
BAT54C

25V
200MA
SOT23
COMMON

Voltage1

VID1_VOL1

2

1

VID2_VOL1

VID3_VOL1

2

1

VID4_VOL1

Voltage2

VID1_VOL2

2

1

VID2_VOL2

VID3_VOL2

2

1

VID4_VOL2

Default

VID1_VOL_DEF

2

1

VID2_VOL_DEF

VID3_VOL_DEF

2

1

VID4_VOL_DEF

0

R550

NO STUFF

0402

5%

0

R553

COMMON

0402

5%

0

R559

NO STUFF

0402

5%

0

R577

COMMON

0402

5%

0

R548

04025%NO STUFF

0

R555

NO STUFF

0402

5%

0

R569

COMMON

0402

5%

0

R588

COMMON

0402

5%

0

R551

NO STUFF

0402

5%

0

R554

NO STUFF

0402

5%

0

R560

NO STUFF

0402

5%

0

R578

COMMON

0402

5%

NVVDD_VID1

NVVDD_VID2

NVVDD_VID3

NVVDD_VID4

27<>

27<>

27<>

27<>

NVVDD Voltage Select

NVVDD range 0.8V-1.55V

Regulator: ISL6563

Control via NV_GPIOs NV_VSEL[2..0] :
VID NVVDD
4 3 2 1 Vout
1 1 1 1 0.80V
1 1 1 0 0.85V
1 1 0 1 0.90V
1 1 0 0 0.95V
1 0 1 1 1.00V
1 0 1 0 1.05V
1 0 0 1 1.10V
1 0 0 0 1.15V
0 1 1 1 1.20V
0 1 1 0 1.25V
0 1 0 1 1.30V
0 1 0 0 1.35V
0 0 1 1 1.40V
0 0 1 0 1.45V
0 0 0 1 1.50V
0 0 0 0 1.55V

Note: ISL6563 Controller can support
AMD HAMMER VID codes and
Intel VRM9/10 VID codes
The above uses AMD Hammer VID codes

SKU Specific Codes

SKU

600-50317-0000
600-50317-0001

600-10317-0000

600-50317-0002

Default 0 1 0 0 1

Default
Voltage1
Voltage2

Default
Voltage1
Voltage2

VID
4 3 2 1 0

0 1 1 1 0
0 1 0 1 0
0 0 1 1 0

0 1 1 0 1
0 0 1 1 1
0 0 1 1 1

NVVDD
Vout

1.325V

1.200V

1.300V

1.400V

1.225V

1.375V

1.375V

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Power Supply IV: External 12V Power + NVVDD VID Control

www.vinafix.vn

600-10317-0002-100

design
John Lam

26 OF 28

31-MAY-2005

27 Power Supply V: NVVDD

S

D

G

S

D

G

S

D

G

S

D

G

S

D

G

S

D

G

S

D

G

S

D

G

BIBIBIBIOUT

2 Phase PWM

PVCC

BOOT1

LGATE1

PHASE1

UGATE1

BOOT2

UGATE2

PHASE2

LGATE2

GND(PAD)

DACSEL

VCC

ISEN

ENLL

OFS

SSEND

VRM10

COMP

VID4

VID3

VID2

VID1

VID0

FB

GND

IN

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

Input Ripple = ~ 8A

C100
180UF

COMMON
+/-20%
16V
OSCON

3.64A@105C

0.020R
COMBI_7343_D80

GND

C549
10UF

16V
20%
X5R
1206
NO STUFF

GND

*Default = No Stuff

GND

C97
180UF

COMMON
+/-20%
16V
OSCON

3.64A@105C

0.020R
COMBI_7343_D80

C101
180UF

COMMON
+/-20%
16V
OSCON

3.64A@105C

0.020R
COMBI_7343_D80

GND

EXT_12V_IN

C539
10UF

16V
20%
X5R
1206
NO STUFF

GND

Switching Freq = 230Khz/channel

5V

10

R521

COMMON

0805

12MIL
NVVDD_VCC

NVVDD_ISEN

NVVDD_SSEND

NVVDD_ENLL

NVVDD_OFS

TP_NVVDD_VRM10

NVVDD_VID0
NVVDD_VID1
NVVDD_VID2
NVVDD_VID3
NVVDD_VID4
NVVDD_DACSEL

NVVDD_COMP

NVVDD_FB

5%

U503

ISL6563CRZ_230KHZ

DYNAMIC VID(0.8V..1.85V)

MLFP24
MLFP24
COMMON

8

7 20

10

21

9

4
2

1
24
23
22

3

5

6

14
25

GND

C525
1UF

16V
10%
X5R
0603
COMMON

GND

1.5KR526

COMMON

0603

R542
0

0402
COMMON

26>
26>
26>
26>

GND

1%

R534
0

0402
COMMON

TP7

NO STUFF

25<

A3V3

R546
1K

1%
0402
COMMON

R545
1K

0402
COMMON

GND

ENABLE:
ENLL has a 0.6V
precision threshold

Rofs

R524
10K

5% 5%5%1%
0402
NO STUFF

GND

Vofs =
(R1*500)/Rofs
Open = No Offset

GND

Set VID0=LOW
to prevent
Shutdown state

R532

0805

0

COMMON

5%

12MIL
NVVDD_PVCC

16

12MIL
NVVDD_BOOT1

12MIL
NVVDD_UGATE1

19

12MIL
NVVDD_PHASE1

18

12MIL
NVVDD_LGATE1

17

11

GND

C547

R541

0402

C535

4.7UF

6.3V
10%
X5R
0603
COMMON

0402 10V

5%

.1UF

10%
X5R
COMMON

2.2

COMMON

12MIL
NVVDD_UGATE1_RG

LFPAK

4

LFPAK

4

12

13

15

Compensation

R1

NVVDD_SENSE

R525
240

5%
0402
COMMON

R4

C2

NVVDD_COMP

R529
510

5%
0402
COMMON

NVVDD_COMP_RC

C530
.1UF

50V
10%
X7R
0603
COMMON

22>

C3

C531
4700PF

50V
10%
X7R
0603
COMMON

NVVDD_FB

R3

C1

NVVDD

R537
100

5%
0402
COMMON

R530
33

5%
0402
COMMON

NVVDD_FB_RC

C536
.047UF

50V
10%
X7R
0603
COMMON

12MIL
NVVDD_BOOT2

12MIL
NVVDD_UGATE2

12MIL
NVVDD_PHASE2

12MIL
NVVDD_LGATE2

C527

0402

R527

0402

.1UF

10V
10%
X5R
COMMON

5%

2.2

COMMON

12MIL
NVVDD_UGATE2_RG

LFPAK

4

LFPAK

4

www.vinafix.vn

Place near Drain of Top Mosfet

C545

4.7UF

16V
20%
X7R

5

Q507

BSC059N03S

LFPAK
COMMON

1

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A

2

R_DS_ON=5.5mR
MAX_CURRENT=200A

3

MAX_WATTAGE=2.8W
V_BE_GS=+/-20V

5

Q510

BSC032N03S

LFPAK
COMMON

1
2

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A

3

R_DS_ON=3.2mR
MAX_CURRENT=200A
MAX_WATTAGE=2.8W
V_BE_GS=+/-20V

GND

1206
COMMON

GND

LFPAK

4

LFPAK

4

Notes: LFPAK Footprint allows S08 alternates
FET Options:

1. TOP - IRF7821, BOT - HAT2165H

2. TOP - IRF7821, BOT - 2xIRF7832

3. TOP - HAT2168H, BOT - HAT2165H

5

Q505

BSC059N03S

LFPAK
NO STUFF

1

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A

2

R_DS_ON=5.5mR
MAX_CURRENT=200A

3

MAX_WATTAGE=2.8W
V_BE_GS=+/-20V

5

Q506

BSC032N03S

LFPAK
COMMON

1

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A

2

R_DS_ON=3.2mR
MAX_CURRENT=200A

3

MAX_WATTAGE=2.8W
V_BE_GS=+/-20V

C521
1500PF

50V
10%
X7R
0603
NO STUFF

GND

Stuff cap if needed to improve Cgs/Cgd ratio!

EXT_12V_IN

Place near Drain of Top Mosfet

C538

4.7UF

16V

5

Q511

BSC059N03S

LFPAK
COMMON

1

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A

2

R_DS_ON=5.5mR
MAX_CURRENT=200A

3

MAX_WATTAGE=2.8W
V_BE_GS=+/-20V

5

Q509

BSC032N03S

LFPAK
COMMON

1
2

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A

3

R_DS_ON=3.2mR
MAX_CURRENT=200A
MAX_WATTAGE=2.8W
V_BE_GS=+/-20V

GND

20%
X7R
1206
COMMON

GND

LFPAK

4

LFPAK

4

Notes: LFPAK Footprint allows S08 alternates
FET Options:

1. TOP - IRF7821, BOT - HAT2165H

2. TOP - IRF7821, BOT - 2xIRF7832

3. TOP - HAT2168H, BOT - HAT2165H

5

Q512

BSC059N03S

LFPAK
NO STUFF

1

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A

2

R_DS_ON=5.5mR
MAX_CURRENT=200A

3

MAX_WATTAGE=2.8W
V_BE_GS=+/-20V

5

Q508

BSC032N03S

LFPAK
COMMON

1

MAX_VOLTAGE=30V
CONTINUOUS_CURRENT=50A

2

R_DS_ON=3.2mR
MAX_CURRENT=200A

3

MAX_WATTAGE=2.8W
V_BE_GS=+/-20V

C523
1500PF

50V
10%
X7R
0603
NO STUFF

GND

Stuff cap if needed to improve Cgs/Cgd ratio!

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Power Supply V: NVVDD

Need to revisit Output Inductor if NVVDD Current Falls well below 45A
1uH Inductor will have less output ripple voltage
Output Inductor Options:
Vishay - 131-0003-000 2.3 mOhm, 29A
Vishay - 131-0004-000 1.7 mOhm, 32A
Delta - 131-0014-000 1.5 mOhm, 32A

CONTINUOUS_CURRENT=29A

SMD_590X530

R513
1

5%
0805
COMMON

NVVDD_SNUB1

C520
1500PF

50V
10%
X7R
0603
COMMON

GND

Place near Low Side Mosfet

Output Inductor Options:
Vishay - 131-0003-000 2.3 mOhm, 29A
Vishay - 131-0004-000 1.7 mOhm, 32A
Delta - 131-0014-000 1.5 mOhm, 32A

CONTINUOUS_CURRENT=29A

SMD_590X530

R536
1

5%
0805
COMMON

NVVDD_SNUB2

C544
1500PF

50V
10%
X7R
0603
COMMON

GND

Place near Low Side Mosfet

L8

12MIL

L7

1UH

CHANGED

1UH

CHANGED

GND

GND

1

2

GND

1

2

GND

23A

D505

IR10MQ040N

SMA
40V

2.1A
COMMON

23A

D503

IR10MQ040N

SMA
40V

2.1A
COMMON

C559
47UF

6.3V
20%
X5R
1206
NO STUFF

Place on Bottom

47UF

6.3V
20%
X5R
1206
NO STUFF

Place on Bottom

*Default = No Stuff

NVVDD = 1.1V..1.4V (30..45A)

C558
47UF

6.3V
20%
X5R
1206
NO STUFF

C89
1200UF

COMMON
+/-20%
4V
OSCON

5.44A@105C

0.012R
COMBI_7343D80D1001812

GND

C95
1000UF

NO STUFF
+/-20%
4V
OSCON

5.04A@45C

0.012R
COMBI_TH_D80_D100

GND

Place in same location as SMD

47UF

6.3V
20%
X5R
1206
NO STUFF

47UF

6.3V
20%
X5R
1206
NO STUFF

Place on Bottom

C560C555C554 C548
47UF

6.3V
20%
X5R
1206
NO STUFF

C90
1200UF

COMMON
+/-20%
4V
OSCON

5.44A@105C

0.012R
COMBI_7343D80D1001812

GND

C96
1000UF

NO STUFF
+/-20%
4V
OSCON

5.04A@45C

0.012R
COMBI_TH_D80_D100

GND

600-10317-0002-100

design
John Lam

16MIL

45A

NVVDD

27 OF 28

31-MAY-2005

28 Mechanical: Bracket/Thermal Solution

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

MECH. MOUNTING TOP

Brackets:

151-10001-0006-000 DVI,DVI,MDIN (text - 1-South, 2-North)
151-10001-0006-001 DB15,DVI,MDIN
151-10001-0006-002 DVI,DB15,MDIN
151-10001-0006-003 DB15,DB15,MDIN (text - 1-South, 2-North)

Connector Screws Bracket Screw

MEC2

HEX_JACK_SCREW
STD
COMMON

MEC1

HEX_JACK_SCREW
STD
COMMON

MEC4

HEX_JACK_SCREW
STD
COMMON

MEC3

HEX_JACK_SCREW
STD
COMMON

BKT1

DVI3152_DVI1552_MDIN490_TEXT_1_2_TAB
ATX_1X_TOP
COMMON

1

GND

MEC5

PH_4_40X.1875_SCREW
STD
COMMON

LF screw --155-0001-000.
ROHS screw --154-0003-700

Heatsink

365-00000-0008-001 - TM30 Fansink + memory heatsink Interface material

ALLEGRO FOOTPRINT SYMBOLS

FAN_GPU_2_68X3_30_B
HEATSINK_GPU_2_35X2_72_B
HEATSINK_MEM_5_34X3_52_B

095-0013-000 - TM30 Fansink
095-0014-000 - TM30 Quadro Fansink
285-00006-0000-000 - Interface Material

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Mechanical: Bracket/Thermal Solution

www.vinafix.vn

600-10317-0002-100

design
John Lam

28 OF 28

31-MAY-2005