MSI MS-V033 Schematic 10

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

NV41/42/G70-P317, 256bit, 4M/8Mx32bit DDR3

Page Overview

Page1: Overview
Page2: PCI Express 1.0
Page3: MEMORY: GPU Partition A/B
Page4: MEMORY: GPU Partition C/D
Page5: FrameBuffer: Partition A 8Mx32 BGA144 DDR3
Page6: FrameBuffer: Partition A Decoupling
Page7: FrameBuffer: Partition B 8Mx32 BGA144 DDR3
Page8: FrameBuffer: Partition B Decoupling
Page9: FrameBuffer: Partition C 8Mx32 BGA144 DDR3
Page10: FrameBuffer: Partition C Decoupling
Page11: FrameBuffer: Partition D 8Mx32 BGA144 DDR3
Page12: FrameBuffer: Partition D Decoupling
Page13: DACA Interface
Page14: DACC Interface
Page15: IFP A/B and C/D Interface
Page16: DACB Interface/Framelock
Page17: Video Capture (Philips 7115)
Page18: Multi-use IO(MIO) Interface
Page19: PEX: Zero Delay Buffer
Page20: MISC: GPIO, I2C, THERMAL, BIOS, XTAL
Page21: Strapping Configuration
Page22: Power/GND and Decoupling
Page23: Power Supply I: TMDS/MIOA/DACB Alternate Supplies
Page24: Power Supply II: 5V and A3V3
Page25: Power Supply III: FBVDDQ and PEX_VDD
Page26: Power Supply IV: External 12V + NVVDD VID Control
Page27: Power Supply V: NVVDD
Page28: Mechanical: Bracket/Thermal Solution

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
Overview

www.vinafix.vn

600-10317-0002-100

design
John Lam

1 OF 28

31-MAY-2005

J501

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIOUT

OUT

IN

23/24 JTAG

JTAG_TRST

JTAG_TDO

JTAG_TMS

JTAG_TCLK

JTAG_TDI

KEY

TRST*

GND

TCK

TMS
TDI
VCC
TDO

1/24 PCI EXPRESS

PEX_IOVDD

PEX_IOVDD

PEX_IOVDD

PEX_IOVDD
PEX_IOVDD

PEX_IOVDD

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_PLLAVDD

RFU

RFU

PEX_PLLDGND

PEX_PLLDVDD

PEX_PLLAGND

PEX_TEST_PLL_CLK_OUT
PEX_TEST_PLL_CLK_OUT

PEX_TX0

PEX_RST

PEX_REFCLK
PEX_REFCLK

PEX_TX0

PEX_TX2

PEX_RX2

PEX_TX3

PEX_RX1

PEX_RX0

PEX_TX1

PEX_RX1

PEX_TX2

PEX_RX2

PEX_RX0

PEX_TX1

PEX_RX3

PEX_RX3

PEX_TX3

PEX_TX7

PEX_RX6

PEX_TX4

PEX_RX6

PEX_TX6

PEX_RX5

PEX_TX5

PEX_TX5

PEX_RX4

PEX_RX5

PEX_TX6

PEX_RX4

PEX_TX4

PEX_TX7

PEX_RX7

PEX_TX9

PEX_TX10

PEX_RX8

PEX_TX9

PEX_RX9

PEX_TX8

PEX_RX10

PEX_RX8

PEX_RX9

PEX_TX10

PEX_TX8

PEX_RX7

PEX_TX11

PEX_RX13
PEX_RX13

PEX_RX11

PEX_TX12

PEX_RX10

PEX_TX11

PEX_RX11

PEX_TX12

PEX_RX12
PEX_RX12

PEX_TX13
PEX_TX13

PEX_TX14

PEX_RX15

PEX_TX14

PEX_RX14
PEX_RX14

PEX_RX15

PEX_TX15

PEX_TX15

ININOUT

OUT

END OF X4

END OF X1

END OF X16

END OF X8

TCLK JTAG2

TDI JTAG3
TDO JTAG4
TMS JTAG5

WAKE

SMDAT

SMCLK

PERST

REFCLK

PERP0
PERN0

REFCLK

PETP0

PERN1

PERP1

PETN0

PERP2

PETN1

PETP1

PETP2

PETN3

PETP3

PERN3

PETN2

PERN2

PERP3

PETP4

PERP5

PETN4

PERN4

PERP4

PERN5

PETP5
PETN5

PERP6
PERN6

PETP6
PETN6

PERP7
PERN7

PETP7
PETN7

PERP8

PETP8
PETN8

PERN8

PERP9
PERN9

PETP9
PETN9

PERP10
PERN10

PETP10
PETN10

PERP11

PERN12

PERP12

PETN11

PETP11

PERN11

PETN13

PETP12
PETN12

PERN13

PETP13

PERP13

PERP14

PETN15

PETP15

PERN15

PERP15

PERN14

PETN14

PETP14

TRST* JTAG1+12V

+12V/RSVD

+3V3AUX

+12V

+12V

+12V

+3V3
+3V3
+3V3

PRSNT2

PRSNT1

GND

GND

RSVD

GND
GND
GND

GND

GND

GND
GND

PRSNT2
RSVD

RSVD

GND
GND

RSVD

GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

PRSNT2
RSVD

GND

GND

GND
GND

GND
GND

GND
GND

GND

GND
GND
GND

GND

GND

GND

PRSNT2

GND

RSVD

RSVD

GND

GND

GND

GND
GND
GND
GND
GND
GND

GND
GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND
GND

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

HDR_2F4

FEMALE

NV_SOURCE_POWER_NET=TRUE

12 V

5.5A

C43

C42

4.7UF

4.7UF

16V

16V

20%

20%

X7R

X7R

1206

1206

COMMON

COMMON

NV_SOURCE_POWER_NET=TRUE

3.3 V

3A

C47

C54

.1UF

4.7UF

16V

6.3V
10%

10%

X7R

X5R

0402

0603

COMMON

COMMON

20MIL

C45
.1UF

16V
10%
X7R
0402
COMMON

20MIL

SNN_3V3AUX

PRSNT*

SNN_PE_PRSNT2_A

SNN_PE_RSVD2

CN2

CON_X16
COMMON

CON_PCIEXP_X16_EDGE

B1
B2
A2
A3
B3

B8
A9

A10

B10

A1

B17

B12

B4
A4

B7
A12
B13
A15
B16
B18
A18

2 PCI Express 1.0

12V

GND

3V3

GND

SNN_PE_PRSNT2_B
SNN_PE_RSVD3
SNN_PE_RSVD4
SNN_PE_RSVD5

SNN_PE_PRSNT2_C
SNN_PE_RSVD6

PRSNT*
SNN_PE_RSVD7
SNN_PE_RSVD8

GND

B31
A19
B30
A32

A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32

B48

GND

A33

A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49

GND

B81
A50
B82

A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82

GND

PEX JTAG

A

PEX_TRST*

B9

PEX_TCLK

A5

PEX_TDI

A6
A7
A8

B5
B6

B11

A11

A13
A14

A16
A17

B14
B15

A21
A22

B19
B20

A25
A26

B23
B24

A29
A30

B27
B28

A35
A36

B33
B34

A39
A40

B37
B38

A43
A44

B41
B42

A47
A48

B45
B46

A52
A53

B50
B51

A56
A57

B54
B55

A60
A61

B58
B59

A64
A65

B62
B63

A68
A69

B66
B67

A72
A73

B70
B71

A76
A77

B74
B75

A80
A81

B78
B79

PEX_TDO
PEX_TMS

SNN_PEX_SMCLK
SNN_PEX_SMDAT

SNN_PEX_WAKE*

PEX_RST*
PEX_REFCLK
PEX_REFCLK*

PEX_TXX0
PEX_TXX0*

PEX_RX0
PEX_RX0*

PEX_TXX1
PEX_TXX1*

PEX_RX1
PEX_RX1*

PEX_TXX2
PEX_TXX2*

PEX_RX2
PEX_RX2*

PEX_TXX3
PEX_TXX3*

PEX_RX3
PEX_RX3*

PEX_TXX4
PEX_TXX4*

PEX_RX4
PEX_RX4*

PEX_TXX5
PEX_TXX5*

PEX_RX5
PEX_RX5*

PEX_TXX6
PEX_TXX6*

PEX_RX6
PEX_RX6*

PEX_TXX7
PEX_TXX7*

PEX_RX7
PEX_RX7*

PEX_TXX8
PEX_TXX8*

PEX_RX8
PEX_RX8*

PEX_TXX9
PEX_TXX9*

PEX_RX9
PEX_RX9*

PEX_TXX10
PEX_TXX10*

PEX_RX10
PEX_RX10*

PEX_TXX11
PEX_TXX11*

PEX_RX11
PEX_RX11*

PEX_TXX12
PEX_TXX12*

PEX_RX12
PEX_RX12*

PEX_TXX13
PEX_TXX13*

PEX_RX13
PEX_RX13*

PEX_TXX14
PEX_TXX14*

PEX_RX14
PEX_RX14*

PEX_TXX15
PEX_TXX15*

PEX_RX15
PEX_RX15*

A = Default STUFF for no PEX JTAG
B = STUFF for Compliance board

C1016

COMMON

C1004

COMMON

C991

COMMON

C985

COMMON

C967

COMMON

C950

COMMON

C931

COMMON

C907

COMMON

COMMON

C853

COMMON

C818

COMMON

C788

COMMON

C751

COMMON

C729

COMMON

C722

COMMON

C720

COMMON

0

R715

COMMON

0402

5%

2<> 19<
2<> 19<

2<>

19>

2<>

19>

.1UF

C1011

10V

0402

10%

0402

X5R

.1UF

0402 10V .1UFC1002

10%

0402

X5R

.1UF

C989

10V

0402

10%

0402

X5R

.1UF

C974

10V

0402

10%

0402

X5R

.1UF

C965

10V

0402

10%

0402

X5R

.1UF

C945

10V

0402

10%

0402

X5R

.1UF

C920

10V

0402

10%

0402

X5R

.1UF

10V

0402

10%

0402

X5R

.1UFC885

C876

10V

0402

10%

0402

X5R

.1UF

C840

10V

0402

10%

0402

X5R

.1UF

C815

10V

0402

10%

0402

X5R

.1UF

C780

10V

0402

10%

0402

X5R X5R

.1UF

10V

0402

10%

0402

X5R

.1UF

10V

0402

10%

0402

X5R

.1UF

C721

10V

0402

10%

0402

X5R

.1UF

C716

10V

0402

10%

0402

X5R

.1UF

10V

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UFC896

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UF

10V

.1UFC744

10V

.1UFC725

10V

.1UF

10V

.1UF

10V

0402X4

0402X4

0402X4

0402X4

R710

0402

RP1

0.05R_MAX

RP1

0.05R_MAX

RP1

0.05R_MAX

RP1

0.05R_MAX

PEX_REFCLK_OUT
PEX_REFCLK_OUT*

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%
X5R

10%

10%
X5R

10%
X5R

10%
X5R

10%
X5R

B

0

NO STUFF

5%

0

5

4

NO STUFF

0

6

3

NO STUFF

0

7

2

NO STUFF

0

8

1

NO STUFF

PEX_TX0
PEX_TX0*

COMMON

PEX_TX1
PEX_TX1* AN11

COMMON

PEX_TX2
PEX_TX2*

COMMON

PEX_TX3
PEX_TX3*

COMMON

PEX_TX4

COMMON

PEX_TX5
PEX_TX5*

COMMON

PEX_TX6
PEX_TX6*

COMMON

PEX_TX7
PEX_TX7*

COMMON

PEX_TX8 AM16
PEX_TX8*

COMMON

PEX_TX9
PEX_TX9*

COMMON

PEX_TX10
PEX_TX10*

COMMON

PEX_TX11
PEX_TX11*

COMMON

PEX_TX12
PEX_TX12*

COMMON

PEX_TX13
PEX_TX13*

COMMON

PEX_TX14
PEX_TX14*

COMMON

PEX_TX15
PEX_TX15*

COMMON

AR9

AK10
AL10

AM11
AM10

AP9

AP10

AN10

AR10
AR11

AN12
AM12

AT11
AT12

AL12
AK12

AP12
AP13

AM14
AM13PEX_TX4*

AR13
AR14

AN13
AN14

AT14
AT15

AN15
AM15

AP15
AP16

AL15
AK15

AR16
AR17

AN16

AT17
AT18

AN17
AN18

AP18
AP19

AM18
AM17

AR19
AR20

AL18
AK18

AT20
AT21

AM19
AN19

AP21
AP22

AN20
AN21

AR22
AR23

AM21
AM20

AT23
AT24

AL21
AK21

AR24
AR25

U9
GF-7800-GT-A2

BGA1148
CHANGED

1.274MM
0

3V3

KEY6_JTAG_SMALL
NO STUFF

1
3
5
7

2
4

8

www.vinafix.vn

3V3

R716

R702

R701
10K

5%
0402
COMMONGND

AH21
AJ21
AH22
AJ22
AH23
AJ23

AH16
AF17
AH17
AF18
AH18

AF19
AH19
AE20
AF20
AH20

AJ20

AM9
AN9

AK19

AK20

AE15

180

10K

5%

5%

0402

0402

COMMON

COMMON

R703
10K

5%
0402
COMMON

GND

JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*

R717
270

5%
0402
COMMON

80MIL

C806
.1UF

10V
10%
X5R
0402
COMMON

80MIL

C816

10V
10%
X5R
0402
COMMON

C817
.1UF

10V
10%
X5R
0402
COMMON

PEX_TEST_PLL_CLK_OUT Termination = 200ohm

PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*

PEXCAL_PD_VDDQ

PEXCAL_PD_GND

12MIL

AF15

AE17

AE16

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
PCI Express 1.0

JTAG

AK6
AL8
AL7
AK7
AL9

C799
.1UF

10V
10%
X5R
0402
COMMON

C839
.1UF.1UF

10V
10%
X5R
0402
COMMON

C838
.1UF

10V
10%
X5R
0402
COMMON

R638
200

1%
0402
COMMON

RFU - NOT USED for NV41

49.9

R625

NO STUFF

0402

1%

49.9

R624

NO STUFF

0402

1%

Components will be no stuff

C860

C858

1UF

.1UF

6.3V

10V

10%

10%

X5R

X5R

0402

0402
COMMON COMMON

C841

C855

1UF

.1UF

6.3V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

U9
GF-7800-GT-A2

BGA1148
CHANGED

C798
1UF

6.3V
10%
X5R
0402
COMMON

C819
1UF

6.3V
10%
X5R
0402
COMMON

C836
1UF

6.3V
10%
X5R
0402
COMMON

PEX_PLLVDD

C78

4.7UF

6.3V
10%
X5R
0603
COMMON

C80

4.7UF

6.3V
10%
X5R
0603
COMMON

C754

C743

4.7UF

1UF

6.3V

6.3V
10%

10%

X5R

X5R

0603

0402

COMMON

COMMON

C76

C851
1UF 4.7UF

6.3V

6.3V
10%

10%

X5R

X5R

0603

0402

COMMON

COMMON

C805
1UF

6.3V

10%
X5R
0402
COMMON

GND

LB13

GND

GND

PEX_VDD

COMMONBEAD_0603

C746
10UF

6.3V
20%
X5R
0805
COMMON

GND

C77
10UF

6.3V
20%
X5R
0805
COMMON

220R@100MHz

GND

3GIO NET RULES

NET

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT

PEX_VDD

PEX_VDD

PEX_REFCLK
PEX_REFCLK*

PEX_REFCLK_OUT
PEX_REFCLK_OUT*

PEX_TXX0
PEX_TXX0*
PEX_TXX1
PEX_TXX1*
PEX_TXX2
PEX_TXX2*
PEX_TXX3
PEX_TXX3*
PEX_TXX4
PEX_TXX4*
PEX_TXX5
PEX_TXX5*
PEX_TXX6
PEX_TXX6*
PEX_TXX7
PEX_TXX7*
PEX_TXX8
PEX_TXX8*
PEX_TXX9
PEX_TXX9*
PEX_TXX10
PEX_TXX10*
PEX_TXX11
PEX_TXX11*
PEX_TXX12
PEX_TXX12*
PEX_TXX13
PEX_TXX13*
PEX_TXX14
PEX_TXX14*
PEX_TXX15
PEX_TXX15*

PEX_RX0
PEX_RX0*
PEX_RX1
PEX_RX1*
PEX_RX2
PEX_RX2*
PEX_RX3
PEX_RX3*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_RX14
PEX_RX14*
PEX_RX15
PEX_RX15*

PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*

PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*

100DIFF
100DIFF
100DIFF
100DIFF

100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF

100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF

100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF

100DIFF
100DIFF

Matching Rule of Thumb

4 inch from Top of Gold Fingers to GPU

PEX_VDD

C79

4.7UF

6.3V
10%
X5R
0603
COMMON

*2 inch Lane to Lane Skew

*No real Skew rule, but reducing the skew will minimize latency

NET

PEX_PLLVDD

VOLTAGE

1.2 V

600-10317-0002-100

design
John Lam

DIFFPAIRCRITICALIMPEDANCE

PEX_REFCLK_OUT
PEX_REFCLK_OUT
PEX_REFCLK_OUT
PEX_REFCLK_OUT

PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15

PEX_RX0
PEX_RX0
PEX_RX1
PEX_RX1
PEX_RX2
PEX_RX2
PEX_RX3
PEX_RX3
PEX_RX4
PEX_RX4
PEX_RX5
PEX_RX5
PEX_RX6
PEX_RX6
PEX_RX7
PEX_RX7
PEX_RX8
PEX_RX8
PEX_RX9
PEX_RX9
PEX_RX10
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_RX12
PEX_RX13
PEX_RX13
PEX_RX14
PEX_RX14
PEX_RX15
PEX_RX15

PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15

2 OF 28

31-MAY-2005

2>
19<

19<
2<
19>

19>

3 FrameBuffer: GPU Partition A/B

OUTINININOUT

OUT

OUT

OUT

3/24 MEM_B

FBB_CMD6

FBB_CMD4
FBB_CMD5

FBB_CMD3

FBB_CMD1
FBB_CMD2

FBB_CMD0

FBB_CMD7

FBB_CMD26

FBB_CMD24
FBB_CMD25

FBB_CMD23

FBB_CMD21
FBB_CMD22

FBB_CMD19
FBB_CMD20

FBB_CMD18

FBB_CMD17

FBB_CMD16

FBB_CMD14
FBB_CMD15

FBB_CMD13

FBB_CMD12

FBB_CMD11

FBB_CMD9

FBB_CMD10

FBB_CMD8

FBB_CLK1

FBB_CLK0
FBB_CLK0
FBB_CLK1

RFU
RFU

FBB_DEBUG

FBB_REFCLK

FBCAL1_PD_VDDQ

FBB_REFCLK

FBCAL1_TERM_GND

FBCAL1_PU_GND

FBB_PLLAVDD

FBB_PLLVDD

FBB_PLLGND

FBBD6

FBBD4
FBBD5

FBBD3

FBBD2

FBBD1

FBBD0

FBBD7

FBBD27

FBBD26

FBBD25

FBBD24

FBBD23

FBBD22

FBBD21

FBBD19
FBBD20

FBBD17

FBBD16

FBBD15

FBBD13

FBBD12

FBBD11

FBBD9
FBBD10

FBBD8

FBBD14

FBBD18

FBBD47

FBBD46

FBBD45

FBBD44

FBBD42
FBBD43

FBBD41

FBBD40

FBBD39

FBBD37
FBBD38

FBBD36

FBBD35

FBBD34

FBBD32
FBBD33

FBBD31

FBBD30

FBBD29

FBBD28

FBBD48

FBBDQM2

FBBDQM1

FBBDQM0

FBBD62
FBBD63

FBBD60
FBBD61

FBBD59

FBBD57
FBBD58

FBBD55
FBBD56

FBBD54

FBBD53

FBBD52

FBBD50
FBBD51

FBBD49

FBBDQS_WP2

FBBDQS_WP1

FBBDQS_WP0

FBBDQS_RN7

FBBDQS_RN4
FBBDQS_RN5
FBBDQS_RN6

FBBDQS_RN3

FBBDQS_RN2

FBBDQS_RN1

FBBDQS_RN0

FBBDQM7

FBBDQM6

FBBDQM4
FBBDQM5

FBBDQM3

FBBDQS_WP3

FB_VREF2

FBBDQS_WP7

FBBDQS_WP6

FBBDQS_WP5

FBBDQS_WP4

OUT

OUTBIIN

OUT

OUT

OUT

OUT

OUTBIOUTINOUT

2/24 MEM_A

FBA_CMD0

FBA_CMD2

FBA_CMD1

FBA_CMD3

FBA_CMD5

FBA_CMD4

FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD10

FBA_CMD9

FBA_CMD11
FBA_CMD12
FBA_CMD13

FBA_CMD15

FBA_CMD14

FBA_CMD16
FBA_CMD17
FBA_CMD18

FBA_CMD20

FBA_CMD19

FBA_CMD22

FBA_CMD21

FBA_CMD23

FBA_CMD25

FBA_CMD24

FBA_CMD26

FBA_CLK1

FBA_CLK1

FBA_CLK0

FBA_CLK0

RFU
RFU

FBA_DEBUG

FBA_REFCLK

FBA_PLLAVDD

FBA_REFCLK

FBA_PLLVDD

FBCAL0_TERM_GND

FBCAL0_PU_GND

FBCAL0_PD_VDDQ

FBA_PLLGND

FBAD0
FBAD1
FBAD2
FBAD3

FBAD5

FBAD4

FBAD6
FBAD7
FBAD8

FBAD10

FBAD9

FBAD11

FBAD13

FBAD12

FBAD14
FBAD15
FBAD16
FBAD17
FBAD18

FBAD20

FBAD19

FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27

FBAD40

FBAD46
FBAD47

FBAD28
FBAD29
FBAD30
FBAD31

FBAD33

FBAD32

FBAD34
FBAD35
FBAD36

FBAD38

FBAD37

FBAD39

FBAD41

FBAD43

FBAD42

FBAD44
FBAD45

FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54

FBAD56

FBAD55

FBAD57
FBAD58

FBAD61

FBAD63

FBAD62

FBADQM0
FBADQM1
FBADQM2

FBAD60

FBAD59

FBADQM3

FBADQM5

FBADQM4

FBADQM6
FBADQM7

FBADQS_RN1

FBADQS_RN0

FBADQS_RN2
FBADQS_RN3

FBADQS_RN6

FBADQS_RN5

FBADQS_RN4

FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4

FBADQS_WP6

FBADQS_WP5

FBADQS_WP7

FB_VREF1

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

NET RULES

NET

FBA_PLLVDD
FBB_PLL_VDD
FBAB_PLLAVDD

VOLTAGE

3.3 V

3.3 V

1.4 V

U9
GF-7800-GT-A2

BGA1148

5<>
5<>
5<>

5<>

FBAD<63..0>
FBADQM<7..0>
FBADQS_RN<7..0>
FBADQS_WP<7..0>

FBVDDQ

R608
511

1%
0402
COMMON

R606

1.18K

1%
0402
COMMON

GND

C730
.1UF

10V
10%
X5R
0402
COMMON

GND

VREF = 0.70 * FBVDDQDDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

FB_VREF1

FBAD<0>
FBAD<1>
FBAD<2>
FBAD<3>
FBAD<4>
FBAD<5>
FBAD<6>
FBAD<7>
FBAD<8>
FBAD<9>
FBAD<10>
FBAD<11>
FBAD<12>
FBAD<13>
FBAD<14>
FBAD<15>
FBAD<16>
FBAD<17>
FBAD<18>
FBAD<19>
FBAD<20>
FBAD<21>
FBAD<22>
FBAD<23>
FBAD<24>
FBAD<25>
FBAD<26> AG35
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30>
FBAD<31>
FBAD<32>
FBAD<33>
FBAD<34>
FBAD<35>
FBAD<36>
FBAD<37>
FBAD<38>
FBAD<39>
FBAD<40>
FBAD<41>
FBAD<42>
FBAD<43>
FBAD<44>
FBAD<45>
FBAD<46>
FBAD<47>
FBAD<48>
FBAD<49>
FBAD<50>
FBAD<51>
FBAD<52>
FBAD<53>
FBAD<54>
FBAD<55>
FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<60>
FBAD<61>
FBAD<62>
FBAD<63>

FBADQM<0>
FBADQM<1> AM33
FBADQM<2>
FBADQM<3>
FBADQM<4>
FBADQM<5>
FBADQM<6>
FBADQM<7>

FBADQS_RN<0>
FBADQS_RN<1>
FBADQS_RN<2>
FBADQS_RN<3>
FBADQS_RN<4>
FBADQS_RN<5>
FBADQS_RN<6>
FBADQS_RN<7>

FBADQS_WP<0>
FBADQS_WP<1>
FBADQS_WP<2>
FBADQS_WP<3>
FBADQS_WP<4>
FBADQS_WP<5>
FBADQS_WP<6>
FBADQS_WP<7>

AH35
AH36
AH34
AJ34
AK36
AJ36
AK34
AL34
AH32
AK33
AJ33
AH33
AL33
AN32
AN33
AN31
AE32
AF30
AF32
AE30
AE31
AC30
AC32
AD30
AG36
AG34

AF36
AD36
AD34
AD35
AE34
AP36
AN35
AM34
AP35
AP34
AP33
AT34
AR34
AM22
AM25
AN26
AN24
AK24
AL22
AK23
AM23
AT32
AT33
AR33
AP31
AR30
AT30
AP30
AT29
AP26
AP27
AT25
AP25
AR28
AP28
AT28
AP29

AK35

AF33
AF34
AN34
AM24
AP32
AR27

AL35
AK32
AG33
AE36
AM36
AN22
AR31
AT27

AL36
AL32
AG32
AE35
AN36
AN23
AT31
AT26

J29

CHANGED

CALIBRATION PIN

FB_CALx_PD_VDDQ

FB_CALx_PU_GND

FB_CALx_TERM_GND

VREF RATIO

DDR3

60

40

40

0.7 FBVDDQ

AK28
AK29
AN30
AM27
AN28
AL29
AM30
AJ31
AK31
AH31
AK25
AM26
AL31
AN29
AK27
AK26
AN27
AL25
AJ30
AM31
AH30
AL30
AH29
AL28
AH28
AM28

AH27
AJ29
AJ28

AJ24

AH25

AF28
AG28

J28

H28

H29

AF29

AD29

AE29

GND

FBA_CMD<0>
FBA_CMD<1>
FBA_CMD<2>
FBA_CMD<3>
FBA_CMD<4>
FBA_CMD<5>
FBA_CMD<6>
FBA_CMD7
FBA_CMD<8>
FBA_CMD<9>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<12>
FBA_CMD<13>
FBA_CMD<14>
FBA_CMD<15>
FBA_CMD<16>
FBA_CMD<17>
FBA_CMD<18>
FBA_CMD<19>
FBA_CMD<20>
FBA_CMD<21>
FBA_CMD<22>
FBA_CMD<23>
FBA_CMD<24>
FBA_CMD<25>
SNN_FBA_CMD26AG30

FBA_CLK0AH26
FBA_CLK0*
FBA_CLK1
FBA_CLK1*

SNN_FBA_RFU0
SNN_FBA_RFU1AH24

FBA_DEBUG

SNN_FBA_REFCLK
SNN_FBA_REFCLK*

FBCAL0_PD_VDDQ

FBCAL0_PU_GND

FBCAL0_TERM_GND

12MIL

FBA_PLLVDD

12MIL

FBAB_PLLAVDD

NO STUFF

GND

GND

TP512

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

.01UF

16V
10%
X7R
0402
COMMON

C742
.01UF

16V
10%
X7R
0402
COMMON

0
1
2
3
4
5
6

8
9

NO STUFF

FBA_CMD<0..26>

TP511

5<
5<
5<
5<

60.4

R613

COMMON

0402

1%

40.2

R610

COMMON

0402

1%

69.8

R605

CHANGED

0402

1%

.1UF

10V
10%
X5R
0402
COMMON

GND

C750
.1UF

10V
10%
X5R
0402
COMMON

GND GND

144BGA CMD Mapping

CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21
CMD22

CMD24
CMD25
CMD26

GND

ADDRCMD
A<3>
A<0>
A<2>
A<1>
A<3>
A<4>
A<5>
CS1* *not used
CS0*
WE*
BA0
CKE
RESET
A<2>
A<12>
RAS*
A<11>
A<10
BA1
A<8>
A<9>
A<6>
A<5>
A<7>CMD23
A<4>
CAS*
A<13> *not used

180R@100MHz

LB502

BEAD_0603

C723C734 C752

4.7UF

6.3V
10%
X5R
0603
COMMON

180R@100MHz

LB501

BEAD_0603

C719

4.7UF

6.3V
10%
X5R
0603
COMMON

5<

COMMON

GND

COMMON

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
MEMORY: GPU Partition A/B

GND

C713

4.7UF

6.3V
10%
X5R
0603
COMMON

C715

4.7UF

6.3V
10%
X5R
0603
COMMON

FBVDDQ

A3V3

NVVDD

7<>
7<>
7<>

7<>

www.vinafix.vn

FBBD<63..0>
FBBDQM<7..0>
FBBDQS_RN<7..0>
FBBDQS_WP<7..0>

C753
.1UF

10V
10%
X5R
0402
COMMON

GND

VREF = 0.70 * FBVDDQDDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBVDDQ

GND

R615
511

1%
0402
COMMON

R614

1.18K

1%
0402
COMMON

0
1
2
3
4
5
6
7

FB_VREF2

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

FBBD<0>
FBBD<1>
FBBD<2>
FBBD<3>
FBBD<4>
FBBD<5>
FBBD<6>
FBBD<7>
FBBD<8>
FBBD<9>
FBBD<10>
FBBD<11>
FBBD<12>
FBBD<13>
FBBD<14>
FBBD<15>
FBBD<16>
FBBD<17>
FBBD<18>
FBBD<19>
FBBD<20>
FBBD<21>
FBBD<22>
FBBD<23>
FBBD<24>
FBBD<25>
FBBD<26>
FBBD<27>
FBBD<28>
FBBD<29>
FBBD<30>
FBBD<31>
FBBD<32>
FBBD<33>
FBBD<34>
FBBD<35>
FBBD<36>
FBBD<37>
FBBD<38>
FBBD<39>
FBBD<40>
FBBD<41>
FBBD<42>
FBBD<43>
FBBD<44>
FBBD<45>
FBBD<46>
FBBD<47>
FBBD<48>
FBBD<49>
FBBD<50>
FBBD<51>
FBBD<52>
FBBD<53>
FBBD<54>
FBBD<55>
FBBD<56>
FBBD<57>
FBBD<58>
FBBD<59>
FBBD<60>
FBBD<61>
FBBD<62>
FBBD<63>

FBBDQM<0>
FBBDQM<1>
FBBDQM<2>
FBBDQM<3>
FBBDQM<4>
FBBDQM<5>
FBBDQM<6>
FBBDQM<7>

FBBDQS_RN<0>
FBBDQS_RN<1>
FBBDQS_RN<2>
FBBDQS_RN<3>
FBBDQS_RN<4>
FBBDQS_RN<5>
FBBDQS_RN<6>
FBBDQS_RN<7>

FBBDQS_WP<0>
FBBDQS_WP<1>
FBBDQS_WP<2>
FBBDQS_WP<3>
FBBDQS_WP<4>
FBBDQS_WP<5>
FBBDQS_WP<6>
FBBDQS_WP<7>

U9
GF-7800-GT-A2

BGA1148
CHANGED

G36
G35
H36
H34
J35
J34
K34 T30
K35
J31
K32
J30
H30
L32
K30
M31
L30
G31
J32
J33
F33
H31
E33
F31
F32
F35
G34
F36
F34
C35
D34
C36
D35
N35
M34
L34
N36
P36
P34
R36
R34

AC33

Y33

Y30
AB30
AA32
AD32
AD33
AA33

T36

R35

T34

U36

W35

U34

V34

W36
AC36
AA36
AC34
AB34
AA35

Y34

Y36

W34

J36

M32

H33

E34

N34

Y32

T35
AA34

L36

K33

G32

E36

M36
AB32

V35
AB35

K36

L33

G33

D36

M35
AB31

V36
AB36

J27

FBB_CMD<0>

P33

FBB_CMD<1>

N33

FBB_CMD<2>

R31

FBB_CMD<3>

U33

FBB_CMD<4>

V30

FBB_CMD<5>

T33

FBB_CMD<6>
SNN_FBB_CMD7

N32

FBB_CMD<8>

R32

FBB_CMD<9>

P32

FBB_CMD<10>

U32

FBB_CMD<11>

U30

FBB_CMD<12>

P30

FBB_CMD<13>

V31

FBB_CMD<14>

T28

FBB_CMD<15>

W30

FBB_CMD<16>

V32

FBB_CMD<17>

T32

FBB_CMD<18>

N30

FBB_CMD<19>

P28

FBB_CMD<20>

P29

FBB_CMD<21>

U29

FBB_CMD<22>

N28

FBB_CMD<23>

R30

FBB_CMD<24>

M30

FBB_CMD<25>

T29

SNN_FBB_CMD26

N29

FBB_CLK0

M28

FBB_CLK0*

L28

FBB_CLK1

W31

FBB_CLK1*

W32

SNN_FBB_RFU0

R28

SNN_FBB_RFU1K29

FBB_DEBUG

C34

SNN_FBB_REFCLK

AA30

SNN_FBB_REFCLK*

Y29

H27

H26

J26

AB28

AC29

FBCAL1_PD_VDDQ

FBCAL1_PU_GND

FBCAL1_TERM_GND

12MIL

FBB_PLL_VDD

FBAB_PLLAVDD

NO STUFF

AC28

GND

GND

FBB_CMD<0..26>

0
1
2
3
4
5
6

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

7<
7<
7<
7<

TP510

60.4

R616

COMMON

0402

1%

40.2

R618

COMMON

0402

1%

69.8

R619

CHANGED

0402

1%

180R@100MHz

LB503

.01UF

16V
10%
X7R
0402
COMMON

.1UF

10V
10%
X5R
0402
COMMON

GND

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

600-10317-0002-100

design
John Lam

7<

COMMONBEAD_0603

GND

C714C724C749 C758

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

3 OF 28

31-MAY-2005

FBVDDQ

A3V3

4 FrameBuffer: GPU Partition C/D

OUTINININOUT

OUT

OUT

OUT

5/24 MEM_D

FBD_CMD6

FBD_CMD4
FBD_CMD5

FBD_CMD3

FBD_CMD2

FBD_CMD1

FBD_CMD0

FBD_CMD7

FBD_CMD26

FBD_CMD24
FBD_CMD25

FBD_CMD21
FBD_CMD22
FBD_CMD23

FBD_CMD20

FBD_CMD19

FBD_CMD18

FBD_CMD17

FBD_CMD16

FBD_CMD15

FBD_CMD14

FBD_CMD13

FBD_CMD12

FBD_CMD11

FBD_CMD9

FBD_CMD10

FBD_CMD8

FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1

RFU
RFU

FBD_REFCLK

FBD_DEBUG

FBD_PLLVDD

FBD_PLLAVDD

FBD_REFCLK

FBD_PLLGND

FBDD6

FBDD5

FBDD4

FBDD3

FBDD2

FBDD1

FBDD0

FBDD7

FBDD27

FBDD26

FBDD24

FBDD23

FBDD22

FBDD19
FBDD20

FBDD18

FBDD17

FBDD16

FBDD14
FBDD15

FBDD13

FBDD12

FBDD11

FBDD9
FBDD10

FBDD8

FBDD25

FBDD21

FBDD47

FBDD46

FBDD45

FBDD44

FBDD43

FBDD42

FBDD39

FBDD41

FBDD40

FBDD37
FBDD38

FBDD35
FBDD36

FBDD34

FBDD32
FBDD33

FBDD31

FBDD30

FBDD29

FBDD28

FBDD48

FBDDQM2

FBDDQM1

FBDDQM0

FBDD63

FBDD62

FBDD60
FBDD61

FBDD59

FBDD58

FBDD57

FBDD55
FBDD56

FBDD54

FBDD53

FBDD52

FBDD51

FBDD50

FBDD49

FBDDQS_WP2

FBDDQS_WP1

FBDDQS_WP0

FBDDQS_RN7

FBDDQS_RN4
FBDDQS_RN5
FBDDQS_RN6

FBDDQS_RN3

FBDDQS_RN2

FBDDQS_RN1

FBDDQS_RN0

FBDDQM7

FBDDQM6

FBDDQM4
FBDDQM5

FBDDQM3

FBDDQS_WP3

FBDDQS_WP7

FBDDQS_WP6

FBDDQS_WP5

FBDDQS_WP4

OUT

OUTBIIN

OUT

OUT

OUT

OUT

OUTBIOUTINOUT

4/24 MEM_C

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20

FBC_CMD23

FBC_CMD22

FBC_CMD21

FBC_CMD25

FBC_CMD24

FBC_CMD26

FBC_CLK1

FBC_CLK0

FBC_CLK1

FBC_CLK0

RFU
RFU

FBC_DEBUG

FBC_REFCLK
FBC_REFCLK

FBC_PLLAVDD

FBC_PLLVDD

FBC_PLLGND

FBCD0

FBCD2

FBCD4

FBCD6

FBCD1

FBCD3

FBCD5

FBCD7

FBCD10
FBCD11

FBCD18

FBCD21

FBCD24

FBCD12

FBCD17

FBCD15

FBCD14

FBCD8
FBCD9

FBCD13

FBCD20

FBCD23

FBCD22

FBCD25
FBCD26
FBCD27

FBCD19

FBCD16

FBCD31

FBCD34

FBCD36

FBCD38

FBCD28

FBCD30

FBCD29

FBCD32

FBCD37

FBCD40
FBCD41

FBCD39

FBCD42
FBCD43
FBCD44

FBCD46

FBCD45

FBCD47

FBCD35

FBCD33

FBCD48

FBCD52

FBCD49
FBCD50
FBCD51

FBCD54

FBCD53

FBCD56

FBCD55

FBCD59

FBCD58

FBCD57

FBCD60
FBCD61

FBCD63

FBCD62

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3

FBCDQM5

FBCDQM4

FBCDQM6
FBCDQM7

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3

FBCDQS_RN6

FBCDQS_RN5

FBCDQS_RN4

FBCDQS_RN7

FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

NET RULES

NET

FBC_PLLVDD
FBD_PLLVDD
FBCD_AVDD

VOLTAGE

3.3 V

3.3 V

1.4 V

U9
GF-7800-GT-A2

BGA1148

9<>
9<>
9<>

9<>

FBCD<63..0>
FBCDQM<7..0>
FBCDQS_RN<7..0>
FBCDQS_WP<7..0>

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

FBCD<0>
FBCD<1>
FBCD<2>
FBCD<3>
FBCD<4>
FBCD<5>
FBCD<6>
FBCD<7>
FBCD<8>
FBCD<9>
FBCD<10>
FBCD<11>
FBCD<12>
FBCD<13>
FBCD<14>
FBCD<15>
FBCD<16>
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>
FBCD<24>
FBCD<25>
FBCD<26>
FBCD<27>
FBCD<28>
FBCD<29>
FBCD<30>
FBCD<31>
FBCD<32>
FBCD<33>
FBCD<34>
FBCD<35>
FBCD<36>
FBCD<37>
FBCD<38>
FBCD<39>
FBCD<40>
FBCD<41>
FBCD<42>
FBCD<43>
FBCD<44>
FBCD<45>
FBCD<46>
FBCD<47>
FBCD<48>
FBCD<49>
FBCD<50>
FBCD<51>
FBCD<52>
FBCD<53>
FBCD<54>
FBCD<55>
FBCD<56>
FBCD<57>
FBCD<58>
FBCD<59>
FBCD<60>
FBCD<61>
FBCD<62>
FBCD<63>

FBCDQM<0>
FBCDQM<1> C20
FBCDQM<2>
FBCDQM<3>
FBCDQM<4>
FBCDQM<5>
FBCDQM<6>
FBCDQM<7>

FBCDQS_RN<0>
FBCDQS_RN<1>
FBCDQS_RN<2>
FBCDQS_RN<3>
FBCDQS_RN<4>
FBCDQS_RN<5>
FBCDQS_RN<6>
FBCDQS_RN<7>

FBCDQS_WP<0>
FBCDQS_WP<1>
FBCDQS_WP<2>
FBCDQS_WP<3>
FBCDQS_WP<4>
FBCDQS_WP<5>
FBCDQS_WP<6>
FBCDQS_WP<7>

C18
C17
A17
B16
C14
A16
C15
A14
A18
A19
B19
B18
B21
C19
B22
C21
E15
D16
D17
G16
E16
E14
G13
D13
A22
C22
C23
A23
A24
C24
C25
B24
C28
B27
C27
B28
C29
A29
B30
A30
E31
E28
D28
F29
F30
D33
D32
D31
G27
F25
G26
D26
G29
G28
E27
F28
A34
C32
B34
C33
C31
B31
A31
C30

C16

G14
C26
A28
D29
D27
B33

B15
A21
D14
B25
A27
E30
E25
A33

A15
A20
E13
A25
A26
D30
E26
A32

CHANGED

F18
H20
E18
E20
D23
G24
D24
G23
D20
E22
J21
E21
G20
F22
H21
E17
E19
D21
E23
F19
E24
G21
G19
G25
G18
G22

H17
J16
J24
H23

H24
J25

H16

F15
G15

H13

J12

J13

GND

FBC_CMD<0>
FBC_CMD<1>
FBC_CMD<2>
FBC_CMD<3>
FBC_CMD<4>
FBC_CMD<5>
FBC_CMD<6>
FBC_CMD7
FBC_CMD<8>
FBC_CMD<9>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<12>
FBC_CMD<13>
FBC_CMD<14>
FBC_CMD<15>
FBC_CMD<16>
FBC_CMD<17>
FBC_CMD<18>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<21>
FBC_CMD<22>
FBC_CMD<23>
FBC_CMD<24>
FBC_CMD<25>
SNN_FBC_CMD26G17

FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*

SNN_FBC_RFU0
SNN_FBC_RFU1

SNN_FBC_DEBUG

SNN_FBC_REFCLK
SNN_FBC_REFCLK*

12MIL

FBC_PLLVDD

12MIL

FBCD_PLLAVDD

FBC_CMD<0..26>

0
1
2
3
4
5
6

TP513

8
9

10

NO STUFF

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

9<
9<
9<
9<

Unable to fit testpoint

.01UF

16V
10%
X7R
0402
COMMON

C877
.01UF

16V
10%
X7R
0402
COMMON

GND

GND

GND

.1UF

10V
10%
X5R
0402
COMMON

C890
.1UF

10V
10%
X5R
0402
COMMON

9<

144BGA CMD Mapping

ADDRCMD
A<3>

CMD0

A<0>

CMD1

A<2>

CMD2

A<1>

CMD3

A<3>

CMD4

A<4>

CMD5

A<5>

CMD6

CS1* *not used

CMD7

CS0*

CMD8

WE*

CMD9

BA0

CMD10

CKE

CMD11

RESET

CMD12

A<2>

CMD13

A<12>

CMD14

RAS*

CMD15

A<11>

CMD16

A<10

CMD17

BA1

CMD18

A<8>

CMD19

A<9>

CMD20

A<6>

CMD21

A<5>

CMD22

A<7>

CMD23

A<4>

CMD24

CAS*

CMD25

A<13> *not used

CMD26

180R@100MHz

LB504

COMMONBEAD_0603

C868C873C874

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

180R@100MHz

LB505

COMMON

BEAD_0603

C892

4.7UF

6.3V
10%
X5R
0603
COMMON

GNDGND

GND

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
MEMORY: GPU Partition C/D

A3V3

C850

4.7UF

6.3V
10%
X5R
0603
COMMON

NVVDD

C911

4.7UF

6.3V
10%
X5R
0603
COMMON

11<>
11<>
11<>

11<>

www.vinafix.vn

FBDD<63..0>
FBDDQM<7..0>
FBDDQS_RN<7..0>
FBDDQS_WP<7..0>

U9
GF-7800-GT-A2

BGA1148
CHANGED

FBD_CMD<0>

FBDD<0>

0

FBDD<1>

1

FBDD<2>

2

FBDD<3>

3

FBDD<4>

4

FBDD<5>

5

FBDD<6>

6

FBDD<7>

7

FBDD<8>

8

FBDD<9>

9

FBDD<10>

10

FBDD<11>

11

FBDD<12>

12

FBDD<13>

13

FBDD<14>

14

FBDD<15>

15

FBDD<16>

16

FBDD<17>

17

FBDD<18>

18

FBDD<19>

19

FBDD<20>

20

FBDD<21>

21

FBDD<22>

22

FBDD<23>

23

FBDD<24>

24

FBDD<25>

25

FBDD<26>

26

FBDD<27>

27

FBDD<28>

28

FBDD<29>

29

FBDD<30>

30

FBDD<31>

31

FBDD<32>

32

FBDD<33>

33

FBDD<34>

34

FBDD<35>

35

FBDD<36>

36

FBDD<37>

37

FBDD<38>

38

FBDD<39>

39

FBDD<40>

40

FBDD<41>

41

FBDD<42>

42

FBDD<43>

43

FBDD<44>

44

FBDD<45>

45

FBDD<46>

46

FBDD<47>

47

FBDD<48>

48

FBDD<49>

49

FBDD<50>

50

FBDD<51>

51

FBDD<52>

52

FBDD<53>

53

FBDD<54>

54

FBDD<55>

55

FBDD<56>

56

FBDD<57>

57

FBDD<58>

58

FBDD<59>

59

FBDD<60>

60

FBDD<61>

61

FBDD<62>

62

FBDD<63>

63

FBDDQM<0>

0

FBDDQM<1>

1

FBDDQM<2>

2

FBDDQM<3>

3

FBDDQM<4>

4

FBDDQM<5>

5

FBDDQM<6>

6

FBDDQM<7>

7

FBDDQS_RN<0>

0

FBDDQS_RN<1>

1

FBDDQS_RN<2>

2

FBDDQS_RN<3>

3

FBDDQS_RN<4>

4

FBDDQS_RN<5>

5

FBDDQS_RN<6>

6

FBDDQS_RN<7>

7

FBDDQS_WP<0>

0

FBDDQS_WP<1>

1

FBDDQS_WP<2>

2

FBDDQS_WP<3>

3

FBDDQS_WP<4>

4

FBDDQS_WP<5>

5

FBDDQS_WP<6>

6

FBDDQS_WP<7>

7

H3
J3
J1
J2
M3
K3
L3 F8
M1
H1
G3
G1
G2
F3
E1
D1
D2
P4
N7
M7
N5
P5
R7
T7
P7
C1
C5
C2
B4
A3
B3
C4
C3
A8
C6
C7
A7
C8
C9
A9
B9

E12

E9

F9
G10
D10
G12
F12
D11

F4

E4

D4

D5

D8

E7

D7

D9
B13
C11
A13
C13
A11
A10
B10
C10

K2

E3

N4

D3

B7
G11

F5
C12

K1

F2

R6

A4

B6
E10

E6
A12

L1

F1

R5

A5

A6
E11

D6
B12

M6
G5
L7
K5
J10
G8

G6
H6
F6
K8
L5
H4
G4
K9
L4
K4
K7
G7
J4
F7
J5
J6
H7
L8
J7
M5

L9
M9
J9
J8

H10
L11

N8

G9
H9

H11

J11

H12

GND

FBD_CMD<1>
FBD_CMD<2>
FBD_CMD<3>
FBD_CMD<4>
FBD_CMD<5>
FBD_CMD<6>
FBD_CMD7
FBD_CMD<8>
FBD_CMD<9>
FBD_CMD<10>
FBD_CMD<11>
FBD_CMD<12>
FBD_CMD<13>
FBD_CMD<14>
FBD_CMD<15>
FBD_CMD<16>
FBD_CMD<17>
FBD_CMD<18>
FBD_CMD<19>
FBD_CMD<20>
FBD_CMD<21>
FBD_CMD<22>
FBD_CMD<23>
FBD_CMD<24>
FBD_CMD<25>
SNN_FBD_CMD26

FBD_CLK0
FBD_CLK0*
FBD_CLK1
FBD_CLK1*

SNN_FBD_RFU0
SNN_FBD_RFU1

FBD_DEBUG

SNN_FBD_REFCLK
SNN_FBD_REFCLK*

12MIL

FBD_PLLVDD

FBCD_PLLAVDD

NO STUFF

GND

0
1
2
3
4
5
6

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

TP6

.01UF

16V
10%
X7R
0402
COMMON

FBD_CMD<0..26>

TP515

NO STUFF

11<
11<
11<
11<

180R@100MHz

LB506

C900C901 C933 C946
.1UF

10V
10%
X5R
0402
COMMON

GND

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

11<

COMMONBEAD_0603

A3V3

4.7UF

6.3V
10%
X5R
0603
COMMON

GND

600-10317-0002-100

design
John Lam

4 OF 28

31-MAY-2005

CS0

INININININBIBIBIBI

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

IN

IN

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

INININ

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

BI

BIBIBI

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBA_CMD<13>
FBA_CMD<4>
FBA_CMD<5>
FBA_CMD<6>

FBA_CLK1
FBA_CLK1*

GND

FBA_CMD<15>
FBA_CMD<25>
FBA_CMD<9>
FBA_CMD<8>

FBA_CMD<1>
FBA_CMD<3>

FBA_CMD<21>
FBA_CMD<23>
FBA_CMD<19>
FBA_CMD<20>
FBA_CMD<17>
FBA_CMD<16>
FBA_CMD<14>

FBA_CMD<10>
FBA_CMD<18>

SNN_FBA1_BA2

FBA_CMD<11>

SNN_FBA1_NC1
SNN_FBA1_NC2
SNN_FBA1_NC3

FBA_CMD<12>

FBA_ZQ1

R561
243

1%
0603
COMMON

B10

C13
E13
D12
D13

C12
B12
B13

D13
E13
C13
D12

B10FBAD<55>

C12
B12
B13

GND

B9
B8
C9

C9
B9
B8

U13

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U14

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

5 FrameBuffer: Partition A 8Mx32 BGA144 DDR3

3> 5<

CKE

R87
10K

5%
0402
COMMON

GND

RESET

R86
10K

5%
0402
COMMON

GND

ZQ = 6x desired outputDDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

144BGA CMD Mapping

CMD ADDR

RAS*CMD15
CAS*

CMD25

WE*

CMD9

CKE

CMD11

RESET

CMD12

CS0*

CMD8

CS1**notused

CMD7

A<0>

CMD1

A<1>

CMD3

A<2>

CMD2
CMD0
CMD24
CMD22

CMD13
CMD4
CMD5
CMD6

CMD21
CMD23 A<7>
CMD19
CMD20
CMD17
CMD16
CMD14
CMD10
CMD18

A<3>
A<4>
A<5>

A<2>
A<3>
A<4>
A<5>

A<6>

A<8>
A<9>
A<10
A<11>
A<12>
BA0
BA1

Low Sub-Partition

Hi Sub-Partition

FBA_CMD<25..0>

Low Sub-Partition

3>

5<

3>

5<

5<>

5<>

5<>

5<>

3<>

15
25
9
8

1
3
2
0
24
22
21
23
19
20
17
16
14

10
18

11

12

3>

3<

3>

A-CS0-LOW-32bit

U13

DDR3BGA144
PACK_TYPE=BGA144
VERSION=BGA144
CHANGED

M10

L12
M12
N12
N13
N11FBA_CMD<19>
M11

N10

E12

GND

FBAD<63..0>

FBADQM<7..0>

FBADQS_RN<7..0>

FBADQS_WP<7..0>

M5
N6
N9

N2
N3
M3
L3

M4
N4

N5

L6

M7
N7
N8

E3

M8

M6

M9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VREF:
M2 - DATA
M13 - ADDR

FBADQM<0>

0

FBADQM<1>

1

FBADQM<2>

2

FBADQM<3>

3

FBADQM<4>

4

FBADQM<5>

5

FBADQM<6>

6

FBADQM<7>

7

FBADQS_RN<0>

0

FBADQS_RN<1>

1

FBADQS_RN<2>

2

FBADQS_RN<3>

3

FBADQS_RN<4>

4

FBADQS_RN<5>

5

FBADQS_RN<6>

6

FBADQS_RN<7>

7

FBADQS_WP<0>

0

FBADQS_WP<1>

1

FBADQS_WP<2>

2

FBADQS_WP<3>

3

FBADQS_WP<4>

4

FBADQS_WP<5>

5

FBADQS_WP<6>

6

FBADQS_WP<7>

7

FBA_CMD<15>
FBA_CMD<25>
FBA_CMD<9>
FBA_CMD<8>

CS0

FBA_CMD<1>

FBA_CMD<3>
FBA_CMD<2>
FBA_CMD<0>
FBA_CMD<24>
FBA_CMD<22>

FBA_CMD<21>

FBA_CMD<23>

FBA_CMD<20>

FBA_CMD<17>

FBA_CMD<16>

FBA_CMD<14>

FBA_CMD<10>

FBA_CMD<18>

SNN_FBA0_BA2

FBA_CMD<11>

FBA_CLK0
FBA_CLK0*

SNN_FBA0_NC1
SNN_FBA0_NC2
SNN_FBA0_NC3

FBA_CMD<12>

FBA_ZQ0

R566

243

1%

0603

COMMON

GND

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4L9
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

GND

12MIL

FBA_VREF_DATA0
FBA_VREF_ADDR0

VREF = 0.70 * FBVDDQ

DDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBAD<0>

0

FBAD<1>

1

FBAD<2>

2

FBAD<3>

3

FBAD<4>

4

FBAD<5>

5

FBAD<6>

6

FBAD<7>

7

FBADQM<0>
FBADQS_RN<0>
FBADQS_WP<0>

FBAD<32>

32

FBAD<33>

33

FBAD<34>

34

FBAD<35>

35

FBAD<36>

36

FBAD<37>

37

FBAD<38>

38

FBAD<39>

39

FBADQM<4>
FBADQS_RN<4>
FBADQS_WP<4>

FBA Partition

Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBA_CMD<25..0>

FBVDDQ

R89
511

1%

0402

COMMON

1.3K

1%

0402

CHANGED

GND

12MIL

B6
C6
B5
B7
C2
D3
E2
D2

C3
B3
B2

K12
L13
F13
J13
K13
F12
G12
G13

J12
H12
H13

2

0

24

22

13

4

5

6

R1

C84R88
.1UF

R2

10V
10%
X5R
0402
COMMON

U13

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U14

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

FBA_CMD<2>

FBA_CMD<0>

FBA_CMD<24>

FBA_CMD<22>

FBA_CMD<13>

FBA_CMD<4>

FBA_CMD<5>

FBA_CMD<6>

FBA_CLK0

FBA_CLK0*

FBA_CLK1

FBA_CLK1*

CHANGED

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

FBVDDQ

R572

511

1%

0402

COMMON

R571

1.3K

1%

0402

GND

FBAD<8>

8

FBAD<9>

9

FBAD<10>

10

FBAD<11>

11

FBAD<12>

12

FBAD<13>

13

FBAD<14>

14

FBAD<15>

15

FBADQM<1>

FBADQS_WP<1>

FBAD<40>

40

FBAD<41>

41

FBAD<42>

42

FBAD<43>

43

FBAD<44> L2

44

FBAD<45>

45

FBAD<46>

46

FBAD<47>

47

FBADQM<5>
FBADQS_RN<5>
FBADQS_WP<5>

R573

121

0402

1%

R575

121

0402

1%

R582

121

0402

1%

R579

121

0402

1%

R570

121

0402

1%

R580

121

0402

1%

R557

121

0402

1%

R556

121

0402

1%

R565

60.4

0402

1%

R564

60.4

0402

1%

R568

60.4

0402

1%

R567

60.4

0402

1%

ZQ = 6x desired output

DDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

R1

C583
.1UF

R2

10V
10%
X5R
0402
COMMON

FBVDDQ

G2
G3
F2
F3
J2
K2
K3
L2

J3
H3FBADQS_RN<1>
H2

J2
F3
F2
G2

K2
K3
G3

J3
H3
H2

FBA_CMD<25..0>

Hi Sub-Partition

3>

5<

3>

5<

U13

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U14

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition A 8Mx32 BGA144 DDR3

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

15
25
9
8

1
3
13
4
5
6
21
23
19
20
17
16
14

10
18

11

FBAD<16>
FBAD<17>
FBAD<18>
FBAD<19>
FBAD<20>
FBAD<21>
FBAD<22>
FBAD<23>

FBADQM<2>
FBADQS_RN<2>
FBADQS_WP<2>

FBAD<48>
FBAD<49>
FBAD<50>
FBAD<51>
FBAD<52>
FBAD<53>
FBAD<54>

FBADQM<6>
FBADQS_RN<6>
FBADQS_WP<6>

www.vinafix.vn

A-CS0-HI-32bit

U14

DDR3BGA144
PACK_TYPE=BGA144
VERSION=BGA144
CHANGED

M5
N6
N9

M10

N2
N3
M3

L3
L12
M12
N12
N13
N11
M11

M4

N4

L9

N5
N10

L6

M7

N7

N8

E3
E12

M8

M6

M9

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

FBAD<24>
FBAD<25>
FBAD<26>
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30>
FBAD<31>

FBADQM<3>
FBADQS_RN<3>
FBADQS_WP<3>

FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<60>
FBAD<61>
FBAD<62>
FBAD<63>

FBADQM<7>
FBADQS_RN<7>
FBADQS_WP<7>

NET RULES

NET

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

DDR3:

G13
F12
F13
G12
K13
K12
L13
J13

J12
H12
H13

GND

12MIL

FBA_VREF_DATA1
FBA_VREF_ADDR1

VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

U13

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U14

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

D3
C2
E2
D2
B5
B7
B6
C6

C3
B3
B2

3>

5<

3>

5<

3>

5<

3>

5<

3>

5<

3<>

5<>

3>

5<>

3<

5<>

3>

5<>

FBVDDQ

R562

511

R1

1%

0402

COMMON

R563 C580

1.3K

R2

1%

0402

CHANGED

GND

12MIL

FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
FBA_CMD<25..0>

FBAD<63..0>
FBADQM<7..0>

FBADQS_RN<7..0>
FBADQS_WP<7..0>

.1UF

10V
10%
X5R
0402
COMMON

FBVDDQ

R552

511

1%

0402

COMMON

R549

1.3K

1%

0402

CHANGED

NVVDD

Reference Plane Transition Cap

C640
22UF

6.3V
20%
X5R
0805

R1

R2

GND

C1074
120PF

50V
5%
C0G
0402
COMMONCOMMON

100DIFF
100DIFF
100DIFF
100DIFF
40OHM

40OHM
40OHM

40OHM
40OHM

C562
.1UF

10V
10%
X5R
0402
COMMON

C1006
120PF

50V
5%
C0G
0402
COMMON

GND

600-10317-0002-100

design
John Lam

DIFFPAIRCRITICALIMPEDANCE

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

5 OF 28

31-MAY-2005

1
1
1
1
1

1
1

1
1

6 FrameBuffer: Partition A Decoupling

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBVDDQ

FBVDDQ

Decoupling for FBA 0..31 Decoupling for FBA 32..63

C556

C564

1UF

6.3V
10%
X5R
0603
COMMON

C685

1UF

6.3V
10%
X5R
0603
COMMON

C601

1UF

6.3V
10%
X5R
0603
COMMON

C680

1UF

6.3V
10%
X5R
0603
COMMON

C557

1UF

6.3V
10%
X5R
0603
COMMON

C578 C586

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C677

C608

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C602

C645

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C674

C667

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C567

C572

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

.01UF

16V
10%
X7R
0402
COMMON

C630

.01UF

16V
10%
X7R
0402
COMMON

C603

.01UF

16V
10%
X7R
0402
COMMON

C623

.01UF

16V
10%
X7R
0402
COMMON

C649

.01UF

16V
10%
X7R
0402
COMMON

C591 C594

.01UF .01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C632

C589

.01UF

.01UF

16V

16V

10%

10%
X7RX7R

0402

0402

COMMON

COMMON

C609

C611

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C625

C641

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C650

C655

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C617

.01UF

16V
10%
X7R
0402
COMMON

C642

.01UF

16V
10%
X7R
0402
COMMON

C607

120PF

50V
5%
C0G
0402
COMMON

C628

120PF

50V
5%
C0G
0402
COMMON

C596

120PF

50V
5%
C0G
0402
COMMON

C656

120PF

50V
5%
C0G
0402
COMMON

GND

GND

GND

GND

C553 C565 C571

1UF .1UF .1UF

6.3V

10V
10%
X5R
0402
COMMON

C566

10V
10%

0402
COMMON

C579

.1UF

10V
10%
X5R
0402
COMMON

C605

.1UF

10V
10%
X5R
0402
COMMON

C675

.1UF

10V
10%
X5R
0402
COMMON

10V
10%
X5R
0402
COMMON

C646

.1UF

10V
10%
X5R
0402
COMMON

C668

.1UF

10V
10%
X5R
0402
COMMON

C585

.1UF

10V
10%
X5R
0402
COMMON

C587

.1UF

10V
10%
X5R
0402
COMMON

10%
X5R
0603
COMMON

C563

1UF .1UF

6.3V
10%
X5R X5R
0603
COMMON

C568

1UF

6.3V
10%
X5R
0603
COMMON

C606

1UF

6.3V
10%
X5R
0603
COMMON

C681

1UF

6.3V
10%
X5R
0603
COMMON

C588 C593 C592

.01UF .01UF.01UF

16V

16V
10%
X7R
0402
COMMON

C633

.01UF

16V
10%
X7R
0402
COMMON

C610

.01UF

16V
10%
X7R
0402
COMMON

C626

.01UF

16V
10%
X7R
0402
COMMON

C653

.01UF

16V
10%
X7R
0402
COMMON

16V
10%
X7R
0402
COMMON

C618

.01UF

16V
10%
X7R
0402
COMMON

C643

.01UF

16V
10%
X7R
0402
COMMON

C654

.01UF

16V
10%
X7R
0402
COMMON

10%
X7R
0402
COMMON

C631

.01UF

16V
10%
X7R
0402
COMMON

C604

.01UF

16V
10%
X7R
0402
COMMON

C612

.01UF

16V
10%
X7R
0402
COMMON

C652

.01UF

16V
10%
X7R
0402
COMMON

C619

.01UF

16V
10%
X7R
0402
COMMON

C644

.01UF

16V
10%
X7R
0402
COMMON

C590

120PF

50V
5%
C0G
0402
COMMON

C629

120PF

50V
5%
C0G
0402
COMMON

C651

120PF

50V
5%
C0G
0402
COMMON

C597

120PF

50V
5%
C0G
0402
COMMON

GND

GND

GND

GND

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition A Decoupling

www.vinafix.vn

GND

600-10317-0002-100

design
John Lam

6 OF 28

31-MAY-2005

CS0

INININININBIBIBIBI

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

IN

IN

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

INININ

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

BI

BIBIBI

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBB_CMD<13>
FBB_CMD<4>
FBB_CMD<5>
FBB_CMD<6>

FBB_CLK1
FBB_CLK1*

GND

FBB_CMD<15>
FBB_CMD<25>
FBB_CMD<9>
FBB_CMD<8>

FBB_CMD<3>

FBB_CMD<21>
FBB_CMD<23>
FBB_CMD<19>
FBB_CMD<20>
FBB_CMD<17>
FBB_CMD<16>
FBB_CMD<14>

FBB_CMD<10>
FBB_CMD<18>

SNN_FBB1_BA2

FBB_CMD<11>

SNN_FBB1_NC1
SNN_FBB1_NC2
SNN_FBB1_NC3

FBB_CMD<12>

FBB_ZQ1

R589
243

1%
0603
COMMON

D12
B10

C13
D13
E13

C12
B12
B13

C13
E13
D13
D12

B10FBBD<53>

C12
B12
B13

GND

C9
B9

B8

C9

B9
B8

U11

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U12

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

7 FrameBuffer: Partition B 8Mx32 BGA144 DDR3

3> 7<

CKE

R85
10K

5%
0402
COMMON

GND

RESET

R84
10K

5%
0402
COMMON

GND

ZQ = 6x desired outputDDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

144BGA CMD Mapping

ADDRCMD

CMD15 RAS*

CAS*

CMD25

WE*

CMD9

CKE

CMD11

RESET

CMD12

CS0*

CMD8

CS1* *notused

CMD7

A<0>

CMD1

A<1>

CMD3

A<2>

CMD2
CMD0
CMD24
CMD22

CMD13
CMD4
CMD5
CMD6

CMD21

CMD19
CMD20
CMD17
CMD16
CMD14
CMD10
CMD18

A<3>
A<4>
A<5>

A<2>

A<4>
A<5>

A<6>
A<7>CMD23
A<8>
A<9>
A<10
A<11>
A<12>
BA0
BA1

Low Sub-Partition

Hi Sub-Partition

FBB_CMD<25..0>

Low Sub-Partition

3>

7<

3>

7<

7<>

7<>

7<>

7<>

3<>

15
25
9
8

1
3
2
0
24
22
21
23
19
20
17
16
14

10
18

11

12

3>

3<

3>

A-CS0-LOW-32bit

U11

DDR3BGA144
BGA144
VERSION=BGA144
CHANGED

M10

L12
M12
N12
N13
N11
M11

N10

E12

GND

FBBD<63..0>

FBBDQM<7..0>

FBBDQS_RN<7..0>

FBBDQS_WP<7..0>

M5
N6
N9

N2
N3
M3
L3

M4
N4

N5

L6

M7
N7
N8

E3

M8

M6

M9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VREF:

M13 - ADDR

FBBDQM<0>

0

FBBDQM<1>

1

FBBDQM<2>

2

FBBDQM<3>

3

FBBDQM<4>

4

FBBDQM<5>

5

FBBDQM<6>

6

FBBDQM<7>

7

FBBDQS_RN<0>

0

FBBDQS_RN<1>

1

FBBDQS_RN<2>

2

FBBDQS_RN<3>

3

FBBDQS_RN<4>

4

FBBDQS_RN<5>

5

FBBDQS_RN<6>

6

FBBDQS_RN<7>

7

FBBDQS_WP<0>

0

FBBDQS_WP<1>

1

FBBDQS_WP<2>

2

FBBDQS_WP<3>

3

FBBDQS_WP<4>

4

FBBDQS_WP<5>

5

FBBDQS_WP<6>

6

FBBDQS_WP<7>

7

FBB_CMD<15>
FBB_CMD<25>
FBB_CMD<9>
FBB_CMD<8>

CS0

FBB_CMD<1>

FBB_CMD<3>
FBB_CMD<2>
FBB_CMD<0>
FBB_CMD<24>
FBB_CMD<22>

FBB_CMD<21>

FBB_CMD<23>

FBB_CMD<19>

FBB_CMD<20>

FBB_CMD<17>

FBB_CMD<16>

FBB_CMD<14>

FBB_CMD<10>

FBB_CMD<18>

SNN_FBB0_BA2

FBB_CMD<11>

FBB_CLK0
FBB_CLK0*

SNN_FBB0_NC1
SNN_FBB0_NC2
SNN_FBB0_NC3

FBB_CMD<12>

FBB_ZQ0

R600

243

1%

0603

COMMON

GND

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4L9
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

GND

12MIL

FBB_VREF_DATA0
FBB_VREF_ADDR0

VREF = 0.70 * FBVDDQ

DDR3:M2 - DATA

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBBD<0>

0

FBBD<1>

1

FBBD<2>

2

FBBD<3>

3

FBBD<4>

4

FBBD<5>

5

FBBD<6>

6

FBBD<7>

7

FBBDQM<0>
FBBDQS_RN<0>
FBBDQS_WP<0>

FBBD<32>

32

FBBD<33>

33

FBBD<34>

34

FBBD<35>

35

FBBD<36>

36

FBBD<37>

37

FBBD<38>

38

FBBD<39>

39

FBBDQM<4>
FBBDQS_RN<4>
FBBDQS_WP<4>

FBB Partition

Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBB_CMD<25..0>

FBVDDQ

R82
511

1%

0402

COMMON

1.3K

1%

0402

CHANGED

GND

12MIL

B6
B7
C6
C2
D3
B5
D2
E2

C3
B3
B2

G12
J13
K13
K12
G13
L13
F13
F12

J12
H12
H13

2

0

24

22

13

4

5

6

R1

C82R83
.1UF

R2

10V
10%
X5R
0402
COMMON

U11

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U12

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

FBB_CMD<2>

FBB_CMD<0>

FBB_CMD<24>

FBB_CMD<22>

FBB_CMD<13>

FBB_CMD<4>

FBB_CMD<5>

FBB_CMD<6>

FBB_CLK0

FBB_CLK0*

FBB_CLK1

FBB_CLK1*

CHANGED

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

FBVDDQ

R603

511

1%

0402

COMMON

R601

1.3K

1%

0402

GND

FBBD<8>

8

FBBD<9>

9

FBBD<10>

10

FBBD<11>

11

FBBD<12>

12

FBBD<13>

13

FBBD<14>

14

FBBD<15>

15

FBBDQM<1>

FBBDQS_WP<1>

FBBD<40>

40

FBBD<41>

41

FBBD<42>

42

FBBD<43>

43

FBBD<44> G3

44

FBBD<45>

45

FBBD<46>

46

FBBD<47>

47

FBBDQM<5>

FBBDQS_WP<5>

R596

121

0402

1%

R597

121

0402

1%

R604

121

0402

1%

R602

121

0402

1%

R581

121

0402

1%

R576

121

0402

1%

R590

121

0402

1%

R592

121

0402

1%

R598

60.4

0402

1%

R599

60.4

0402

1%

R583

60.4

0402

1%

R587

60.4

0402

1%

ZQ = 6x desired output

DDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

R1

C687
.1UF

R2

10V
10%
X5R
0402
COMMON

FBVDDQ

F3
J2
F2
G2
K3
G3
L2
K2

J3
H3FBBDQS_RN<1>
H2

K3
F2
F3
J2

K2
L2
G2

J3
H3FBBDQS_RN<5>
H2

FBB_CMD<25..0>

Hi Sub-Partition

3>

7<

3>

7<

U11

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U12

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition B 8Mx32 BGA144 DDR3

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

15
25
9
8

1
3
13
4
5
6
21
23
19
20
17
16
14

10
18

11

FBBD<16>
FBBD<17>
FBBD<18>
FBBD<19>
FBBD<20>
FBBD<21>
FBBD<22>
FBBD<23>

FBBDQM<2>
FBBDQS_RN<2>
FBBDQS_WP<2>

FBBD<48>
FBBD<49>
FBBD<50>
FBBD<51>
FBBD<52>

FBBD<54>
FBBD<55>

FBBDQM<6>
FBBDQS_RN<6>
FBBDQS_WP<6>

www.vinafix.vn

A-CS0-HI-32bit

U12

DDR3BGA144
PACK_TYPE=BGA144
VERSION=BGA144
CHANGED

M5
N6
N9

M10

N2FBB_CMD<1>
N3
M3

L3
L12
M12
N12
N13
N11
M11

M4

N4

L9

N5
N10

L6

M7

N7

N8

E3
E12

M8

M6

M9

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

FBBD<24>
FBBD<25>
FBBD<26>
FBBD<27>
FBBD<28>
FBBD<29>
FBBD<30>
FBBD<31>

FBBDQM<3>
FBBDQS_RN<3>
FBBDQS_WP<3>

FBBD<56>
FBBD<57>
FBBD<58>
FBBD<59>
FBBD<60>
FBBD<61>
FBBD<62>
FBBD<63>

FBBDQM<7>
FBBDQS_RN<7>
FBBDQS_WP<7>

NET RULES

NET

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

DDR3:

F13
F12
G12
G13
L13
K13
K12
J13

J12
H12
H13

GND

12MIL

FBB_VREF_DATA1
FBB_VREF_ADDR1

VREF = 0.70 * FBVDDQ

1.26V = 1.8V * 1.18K/(511 + 1.18K)

U11

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U12

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

E2
D3
D2
C2
C6
B6
B5
B7

C3
B3
B2

12MIL

R574

511

0402

COMMON

R558

1.3K

0402

CHANGED

7<>

FBVDDQ

1%

1%

GND

7<
7<
7<
7<
7<

7<>

7<>
7<>

3>
3>
3>
3>
3>

3<>

3>

3<
3>

R1

R2

FBB_CLK0
FBB_CLK0*
FBB_CLK1
FBB_CLK1*
FBB_CMD<25..0>

FBBD<63..0>
FBBDQM<7..0>

FBBDQS_RN<7..0>
FBBDQS_WP<7..0>

C574
.1UF

10V
10%
X5R
0402
COMMON

FBVDDQ

R591

511

1%

0402

COMMON

R584

1.3K

1%

0402

CHANGED

NVVDD

Reference Plane Transition Cap

C575
22UF

6.3V
20%
X5R
0805

R1

R2

GND

C648
120PF

50V
5%
C0G
0402
COMMONCOMMON

100DIFF
100DIFF
100DIFF
100DIFF
40OHM

40OHM
40OHM

40OHM
40OHM

C599
.1UF

10V
10%
X5R
0402
COMMON

C963
120PF

50V
5%
C0G
0402
COMMON

GND

600-10317-0002-100

design
John Lam

DIFFPAIRCRITICALIMPEDANCE

FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1

7 OF 28

31-MAY-2005

1
1
1
1
1

1
1

1
1

8 FrameBuffer: Partition B Decoupling

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBVDDQ

Decoupling for FBB 0..31

C659

C661

1UF

6.3V
10%
X5R
0603
COMMON

C672

1UF

6.3V
10%
X5R
0603
COMMON

C700

1UF

6.3V
10%
X5R
0603
COMMON

C711

1UF

6.3V
10%
X5R
0603
COMMON

C710

1UF

6.3V
10%
X5R
0603
COMMON

C683 C676

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C678

C689

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C664

C688

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C701

C708

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C709

C695

.1UF

.1UF

10V

10V

10%

10%

X5R

X5R

0402

0402

COMMON

COMMON

C679 C682 C684

.01UF

.01UF .01UF .01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C686

C690

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R X7R

0402

0402

COMMON

COMMON

C692

C693

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C698

C699

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C703

C705

.01UF

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

16V
10%
X7R
0402
COMMON

C691

.01UF

16V
10%

0402
COMMON

C697

.01UF

16V
10%
X7R
0402
COMMON

C702

.01UF

16V
10%
X7R
0402
COMMON

C706

.01UF

16V
10%
X7R
0402
COMMON

16V
10%
X7R
0402
COMMON

C704

.01UF

16V
10%
X7R
0402
COMMON

C670

120PF

50V
5%
C0G
0402
COMMON

C696

120PF

50V
5%
C0G
0402
COMMON

C694

120PF

50V
5%
C0G
0402
COMMON

C707

120PF

50V
5%
C0G
0402
COMMON

GND

GND

GND

GND

FBVDDQ

Decoupling for FBB 32..63

C613 C637 C658

1UF .1UF .1UF

6.3V
10%
X5R
0603
COMMON

C576

1UF

6.3V
10%
X5R X5R
0603
COMMON

C569

1UF

6.3V
10%
X5R
0603
COMMON

C581

1UF

6.3V
10%
X5R
0603
COMMON

C669

1UF

6.3V
10%
X5R
0603
COMMON

10V
10%
X5R
0402
COMMON

C582

.1UF

10V
10%

0402
COMMON

C573

.1UF

10V
10%
X5R
0402
COMMON

C584

.1UF

10V
10%
X5R
0402
COMMON

C665

.1UF

10V
10%
X5R
0402
COMMON

10V
10%
X5R
0402
COMMON

C673

.1UF

10V
10%
X5R
0402
COMMON

C577

.1UF

10V
10%
X5R
0402
COMMON

C570

.1UF

10V
10%
X5R
0402
COMMON

C662

.1UF

10V
10%
X5R
0402
COMMON

C598 C616 C614

.01UF .01UF

16V
10%
X7R
0402
COMMON

C615

.01UF

16V
10%
X7R
0402
COMMON

C624

.01UF

16V
10%
X7R
0402
COMMON

C636

.01UF

16V
10%
X7R
0402
COMMON

C663

.01UF

16V
10%
X7R
0402
COMMON

.01UF

16V

16V

10%

10%

X7R

X7R

0402

0402

COMMON

COMMON

C600

C620

.01UF

.01UF

16V

16V

10%

10%
X7R X7R
0402 0402
COMMON

COMMON

C634

.01UF

16V
10%
X7R
0402
COMMON

C638

C647

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C660

C657

.01UF

.01UF

16V

16V
10%

10%
X7R

X7R
0402

0402
COMMON

COMMON

C622 C595

120PF.01UF

16V

50V

10%

5%

X7R

C0G

0402

0402

COMMON

COMMON

C627

120PF

50V
5%
C0G
0402
COMMON

C635

120PF

50V
5%
C0G
0402
COMMON

C639

C666

.01UF

120PF

16V

50V

10%

5%

X7R

C0G

0402

0402

COMMON

COMMON

GND

GND

GND

GND

GND

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition B Decoupling

www.vinafix.vn

GND

600-10317-0002-100

design
John Lam

8 OF 28

31-MAY-2005

CS0

INININININBIBIBIBI

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

IN

IN

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

DQ7

DQSR
DQSW

DQM

DQ6

DQ5

DQ4

DQ3

DQ0
DQ1
DQ2

INININ

VDD

VDD

VDD

VDD

VDD
VDD

VDD
VDD

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ
VSSQ

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VREF
VREF

RAS
CAS
WE
CS

A0

A2
A3
A4
A5

A1

A10

BA<1>

BA<0>

NC/A<12>

A11

A8

A7

A6

A9

NC/BA<2>

CLK

CKE
CLK

NC/RFU

NC/RFU

NC/RFU

RESET

ZQ

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM
THERM

THERM

THERM

THERM

BI

BIBIBI

1

5

4

3

2

F G H

PAGE
DATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

ID
NAME

ED

ASSEMBLY
PAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

FBC_CMD<13>
FBC_CMD<4>
FBC_CMD<5>
FBC_CMD<6>

FBC_CLK1
FBC_CLK1*

GND

FBC_CMD<15>
FBC_CMD<25>
FBC_CMD<9>
FBC_CMD<8>

FBC_CMD<1>
FBC_CMD<3>

FBC_CMD<21>
FBC_CMD<23>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<17>
FBC_CMD<16>
FBC_CMD<14>

FBC_CMD<10>
FBC_CMD<18>

SNN_FBC1_BA2

FBC_CMD<11>

SNN_FBC1_NC1
SNN_FBC1_NC2
SNN_FBC1_NC3

FBC_CMD<12>

FBC_ZQ1

R621
243

1%
0603
COMMON

B10
C13

D12
D13

E13

C12
B12
B13

G12
L13
K13
J13FBCD<51>
G13
F13
K12
F12

J12
H12
H13

GND

C9
B8

B9

U8

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U10

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

9 FrameBuffer: Partition C 8Mx32 BGA144 DDR3

4> 9<

CKE

R79
10K

5%
0402
COMMON

GND

RESET

R627
10K

5%
0402
COMMON

GND

ZQ = 6x desired outputDDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

144BGA CMD Mapping

ADDRCMD
RAS*CMD15
CAS*

CMD25

WE*

CMD9

CKE

CMD11

RESET

CMD12

CS0*

CMD8

CS1* *notused

CMD7

A<0>

CMD1

A<1>

CMD3

A<2>

CMD2
CMD0
CMD24
CMD22

CMD13
CMD4
CMD5
CMD6

CMD21

CMD20
CMD17
CMD16
CMD14
CMD10
CMD18

A<3>
A<4>
A<5>

A<2>
A<3>
A<4>
A<5>

A<6>
A<7>CMD23
A<8>CMD19
A<9>
A<10
A<11>
A<12>
BA0
BA1

Low Sub-Partition

Hi Sub-Partition

FBC_CMD<25..0>

Low Sub-Partition

4>

9<

4>

9<

9<>

9<>

9<>

9<>

4<>

15
25
9
8

1
3
2
0
24
22
21
23
19
20
17
16
14

10
18

11

12

4>

4<

4>

A-CS0-LOW-32bit

U8

DDR3BGA144
BGA144
VERSION=BGA144
CHANGED

M10

L12
M12
N12
N13
N11
M11

N10

E12

GND

FBCD<63..0>

FBCDQM<7..0>

FBCDQS_RN<7..0>

FBCDQS_WP<7..0>

M5
N6
N9

N2
N3
M3
L3

M4
N4

N5

L6

M7
N7
N8

E3

M8

M6

M9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VREF:
M2 - DATA
M13 - ADDR

FBCDQM<0>

0

FBCDQM<1>

1

FBCDQM<2>

2

FBCDQM<3>

3

FBCDQM<4>

4

FBCDQM<5>

5

FBCDQM<6>

6

FBCDQM<7>

7

FBCDQS_RN<0>

0

FBCDQS_RN<1>

1

FBCDQS_RN<2>

2

FBCDQS_RN<3>

3

FBCDQS_RN<4>

4

FBCDQS_RN<5>

5

FBCDQS_RN<6>

6

FBCDQS_RN<7>

7

FBCDQS_WP<0>

0

FBCDQS_WP<1>

1

FBCDQS_WP<2>

2

FBCDQS_WP<3>

3

FBCDQS_WP<4>

4

FBCDQS_WP<5>

5

FBCDQS_WP<6>

6

FBCDQS_WP<7>

7

FBC_CMD<15>
FBC_CMD<25>
FBC_CMD<9>
FBC_CMD<8>

CS0

FBC_CMD<1>

FBC_CMD<3>
FBC_CMD<2>
FBC_CMD<0>
FBC_CMD<24>
FBC_CMD<22>

FBC_CMD<21>

FBC_CMD<23>

FBC_CMD<19>

FBC_CMD<20>

FBC_CMD<17>

FBC_CMD<16>

FBC_CMD<14>

FBC_CMD<10>

FBC_CMD<18>

SNN_FBC0_BA2

FBC_CMD<11>

FBC_CLK0
FBC_CLK0*

SNN_FBC0_NC1
SNN_FBC0_NC2
SNN_FBC0_NC3

FBC_CMD<12>

FBC_ZQ0

R644

243

1%

0603

COMMON

GND

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4L9
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

GND

12MIL

FBC_VREF_DATA0
FBC_VREF_ADDR0

VREF = 0.70 * FBVDDQ

DDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

FBCD<0>

0

FBCD<1>

1

FBCD<2>

2

FBCD<3>

3

FBCD<4>

4

FBCD<5>

5

FBCD<6>

6

FBCD<7>

7

FBCDQM<0>
FBCDQS_RN<0>
FBCDQS_WP<0>

FBCD<32>

32

FBCD<33>

33

FBCD<34>

34

FBCD<35>

35

FBCD<36>

36

FBCD<37>

37

FBCD<38>

38

FBCD<39>

39

FBCDQM<4>
FBCDQS_RN<4>
FBCDQS_WP<4>

FBC Partition

Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!

Minimize the stub length!!

FBC_CMD<25..0>

FBVDDQ

R77
511

1%

0402

COMMON

1.3K

1%

0402

CHANGED

GND

12MIL

F12
F13
G12
G13
K13
J13
K12
L13

J12
H12
H13

B10
E13
D13
D12
C13

C9
B8
B9

C12
B12
B13

2

0

24

22

13

4

5

6

R1

C75R78
.1UF

R2

10V
10%
X5R
0402
COMMON

U8

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U10

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

FBC_CMD<2>

FBC_CMD<0>

FBC_CMD<24>

FBC_CMD<22>

FBC_CMD<13>

FBC_CMD<4>

FBC_CMD<5>

FBC_CMD<6>

FBC_CLK0

FBC_CLK0*

FBC_CLK1

FBC_CLK1*

CHANGED

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

FBVDDQ

R663

511

1%

0402

COMMON

R655

1.3K

1%

0402

GND

FBCD<8>

8

FBCD<9>

9

FBCD<10>

10

FBCD<11>

11

FBCD<12>

12

FBCD<13>

13

FBCD<14>

14

FBCD<15>

15

FBCDQM<1>

FBCDQS_WP<1>

FBCD<40>

40

FBCD<41>

41

FBCD<42>

42

FBCD<43>

43

FBCD<44> L2

44

FBCD<45>

45

FBCD<46>

46

FBCD<47>

47

FBCDQM<5>

FBCDQS_WP<5>

R630

121

0402

1%

R632

121

0402

1%

R660

121

0402

1%

R659

121

0402

1%

R612

121

0402

1%

R607

121

0402

1%

R622

121

0402

1%

R623

121

0402

1%

R636

60.4

0402

1%

R639

60.4

0402

1%

R617

60.4

0402

1%

R620

60.4

0402

1%

ZQ = 6x desired output

DDR3:

impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm

R1

C947
.1UF

R2

10V
10%
X5R
0402
COMMON

FBVDDQ

B7
B6
C6
B5
D3
C2
E2
D2

C3
B3FBCDQS_RN<1>
B2

G3
F2
F3
K2

K3
J2
G2

J3
H3FBCDQS_RN<5>
H2

FBC_CMD<25..0>

Hi Sub-Partition

4>

9<

4>

9<

U8

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

U10

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

GF-7800-A2 - 256MB 8Mx32, DL-DVI + SL-DVI + HDTV/VIVO
FrameBuffer: Partition C 8Mx32 BGA144 DDR3

16
17
18
19
20
21
22
23

48
49
50
51
52
53
54
55

15
25
9
8

1
3
13
4
5
6
21
23
19
20
17
16
14

10
18

11

FBCD<16>
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>

FBCDQM<2>
FBCDQS_RN<2>
FBCDQS_WP<2>

FBCD<48>
FBCD<49>
FBCD<50>

FBCD<52>
FBCD<53>
FBCD<54>
FBCD<55>

FBCDQM<6>
FBCDQS_RN<6>
FBCDQS_WP<6>

www.vinafix.vn

A-CS0-HI-32bit

U10

DDR3BGA144
PACK_TYPE=BGA144
VERSION=BGA144
CHANGED

M5
N6
N9

M10

N2
N3
M3

L3
L12
M12
N12
N13
N11
M11

M4

N4

L9

N5
N10

L6

M7

N7

N8

E3
E12

M8

M6

M9

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

24
25
26
27
28
29
30
31

56
57
58
59
60
61
62
63

FBCD<24>
FBCD<25>
FBCD<26>
FBCD<27>
FBCD<28>
FBCD<29>
FBCD<30>
FBCD<31>

FBCDQM<3>
FBCDQS_RN<3>
FBCDQS_WP<3>

FBCD<56>
FBCD<57>
FBCD<58>
FBCD<59>
FBCD<60>
FBCD<61>
FBCD<62>
FBCD<63>

FBCDQM<7>
FBCDQS_RN<7>
FBCDQS_WP<7>

NET RULES

IMPEDANCENET

FBVDDQ

D7
D8
E4
E11
L4
L7
L8
L11

C4
C5
C7
C8
C10
C11
F4
F11
G4
G11
H4
H11
J4
J11
K4
K11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

M2
M13

VREF = FBVDDQ * R2/(R1 + R2)

GND

12MIL

FBC_VREF_DATA1

VREF = 0.70 * FBVDDQDDR3:

1.26V = 1.8V * 1.18K/(511 + 1.18K)

U8

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

F3
F2
L2
G3
G2
K2
K3
J2

J3
H3
H2

U10

DDR3BGA144
BGA144

VERSION=BGA144
CHANGED

D2
C2
D3
E2
B5
B6
B7
C6

C3
B3
B2

12MILFBC_VREF_ADDR1

R609

511

0402

COMMON

R611

1.3K

0402

CHANGED

9<>

FBVDDQ

1%

1%

GND

9<
9<
9<
9<
9<

9<>

9<>
9<>

4>
4>
4>
4>
4>

4<>

4>

4<
4>

R1

R2

FBC_CLK0
FBC_CLK0*
FBC_CLK1

FBC_CMD<25..0>

FBCD<63..0>
FBCDQM<7..0>

FBCDQS_RN<7..0>
FBCDQS_WP<7..0>

C745
.1UF

10V
10%
X5R
0402

R81

COMMON

511

0402

COMMON

R80

1.3K

0402

CHANGED

NVVDD

Reference Plane Transition Cap

C728
22UF

6.3V
20%
X5R
0805

FBVDDQ

1%

1%

R1

R2

GND

C671
120PF

50V
5%
C0G
0402
COMMONCOMMON

100DIFF
100DIFF
100DIFF
100DIFFFBC_CLK1*
40OHM

40OHM
40OHM

40OHM
40OHM

C81
.1UF

10V
10%
X5R
0402
COMMON

C621
120PF

50V
5%
C0G
0402
COMMON

GND

600-10317-0002-100

design
John Lam

DIFFPAIRCRITICAL

FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1

9 OF 28

31-MAY-2005

1
1
1
1
1

1
1

1
1