Page 1
<Variant Name>
8
Title
7
6
5
4
3
2
1
Date:Schematic No.
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
REVISION HISTORY
D D
Sch
Rev
C C
PCB
Rev
0 00A
Date
2005-01-07
REVISION DESCRIPTION
PRELIMINARY BASED ON 105-A53300-00A
105-A628XX-00A
Thursday, January 27, 2005
Rev
0
B B
A A
8
7
6
5
4
3
2
1
www.vinafix.vn
Page 2
+12V_BUS
C6
C5
100nF
10uF
6031210 603 603603
16V
16V 16V
X5R
X7R X7R
8
+3.3V_BUS
C7
C3
1.0uF
Y5V Y5V
C4
1.0uF
100nF
7
C8
100uF_16V
>=6.3V
6
+3.3V_BUS+3.3V_BUS
C2
47uF_16V
>=6.3V
DNI
PCI-EXPRESS EDGE CONNECTOR
5
4
3
2
GND_TPVSSGND_MPVSS
GND_PVSS GND_TXVSSR
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE
GND_A2VSSN
1
GND_AVSSQ GND_RSET
GND_A2VSSQ
GND_R2SETGND_AVSSN
D D
C C
B B
Place these capacitors close to the PCIE connector
PETp10_GFXRp10(2)
PETn10_GFXRn10(2)
PETp11_GFXRp11(2)
PETn11_GFXRn11(2)
PETp12_GFXRp12(2)
PETn12_GFXRn12(2)
PETp13_GFXRp13(2)
PETn13_GFXRn13(2)
PETp14_GFXRp14(2)
PETn14_GFXRn14(2)
PETp15_GFXRp15(2)
PETn15_GFXRn15(2)
+12V_BUS
+3.3V_BUS
MPCIE1
B1
+12V#B1
B2
+12V#B2
B3
RSVD#B3
B4
GND#B4
B5
SMCLK
B6
SMDAT
B7
GND#B7
B8
DNI
402
PRESENCE
JTAG_TRST#
PRESENT_NULL
PRESENT_NULL
PRESENT_NULL
TP28
TP30
TP32
TP34
TP36
TP38
TP40
TP42
TP44
TP46
TP48
TP50
TP52
TP54
TP56
TP58
R1008 0R
TP29
TP31
TP33
TP35
TP37
TP39
TP41
TP43
TP45
TP47
TP49
TP51
TP53
TP55
TP57
TP59
A_HSYNC_DAC1(2,10)
PETp0_GFXRp0(2)
PETn0_GFXRn0(2)
PETp1_GFXRp1(2)
PETn1_GFXRn1(2)
PETp2_GFXRp2(2)
PETn2_GFXRn2(2)
PETp3_GFXRp3(2)
PETn3_GFXRn3(2)
PETp4_GFXRp4(2)
PETn4_GFXRn4(2)
PETp5_GFXRp5(2)
PETn5_GFXRn5(2)
PETp6_GFXRp6(2)
PETn6_GFXRn6(2)
PETp7_GFXRp7(2)
PETn7_GFXRn7(2)
PETp8_GFXRp8(2)
PETn8_GFXRn8(2)
PETp9_GFXRp9(2)
PETn9_GFXRn9(2)
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
+3.3V#B8
JTAG1
3.3Vaux
WAKE#
RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82
x16 PCIe
Mechanical Key
PRSNT1#A1
+12V#A2
+12V#A3
GND#A4
+3.3V#A9
+3.3V#A10
PERST#
GND#A12
REFCLK+
REFCLK-
GND#A15
GND#A18
RSVD#A19
GND#A20
GND#A23
GND#A24
GND#A27
GND#A28
GND#A31
RSVD#A32
RSVD#A33
GND#A34
GND#A37
GND#A38
GND#A41
GND#A42
GND#A45
GND#A46
GND#A49
RSVD#A50
GND#A51
GND#A54
GND#A55
GND#A58
GND#A59
PERp10
PERn10
GND#A62
GND#A63
PERp11
PERn11
GND#A66
GND#A67
PERp12
PERn12
GND#A70
GND#A71
PERp13
PERn13
GND#A74
GND#A75
PERp14
PERn14
GND#A78
GND#A79
PERp15
PERn15
GND#A82
JTAG2
JTAG3
JTAG4
JTAG5
PERp0
PERn0
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PERp4
PERn4
PERp5
PERn5
PERp6
PERn6
PERp7
PERn7
PERp8
PERn8
PERp9
PERn9
+12V_BUS
+3.3V_BUS
PERp0
PERn0
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PERp4
PERn4
PERp5
PERn5
PERp6
PERn6
PERp7
PERn7
PERp8
PERn8
PERp9
PERn9
PERp10
PERn10
PERp11
PERn11
PERp12
PERn12
PERp13
PERn13
PERp14
PERn14
PERp15
PERn15
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
R12440R
402
PRESENCE
DNI
RP194A 0R
8 1
RP194B 0R
7 2
RP194C 0R
6 3
RP194D 0R
5 4
TP26
TP27
C607
C608
100nF
100nF
C617
C618
100nF
100nF
C626
C627
100nF
100nF
C631
C632
100nF
100nF
C611
C612
100nF
100nF
C622
C623
100nF
100nF
C621
C630
100nF
100nF
C605
C606
100nF
100nF
C615
C616
100nF
100nF
C624
C625
100nF
100nF
C633
C634
100nF
100nF
C609
100nF
C610
100nF
C619
C620
100nF
100nF
C628
C629
100nF
100nF
C603
C604
100nF
100nF
C613
C614
100nF
100nF
DNI
A_VSYNC_DAC1 (2,10)
DNI
CRT1DDCDATA (2,10)
DNI
SCL (2)
DNI
CRT1DDCCLK (2,10)
R701 1.50K
R702 1.50K
R703 1.50K
R704 1.50K
R705 1.50K
R706 1.50K
R707 1.50K
R708 1.50K
R709 1.50K
R710 1.50K
R711 1.50K
R712 1.50K
R713 1.50K
R714 1.50K
R715 1.50K
R716 1.50K
R717 1.50K
R718 1.50K
R719 1.50K
R720 1.50K
R721 1.50K
R722 1.50K
R723 1.50K
R724 1.50K
R725 1.50K
R726 1.50K
R727 1.50K
R728 1.50K
R729 1.50K
R730 1.50K
R731 1.50K
R732 1.50K
PCIE_REFCLKP (2)
PCIE_REFCLKN (2)
GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)
GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)
GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)
GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)
GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)
GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)
GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)
GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)
GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)
GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)
GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)
GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)
GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)
GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)
GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)
GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)
PERST#
+5V
C972
X5R
100nF
402
6.3V
53
1
2
4
U2
TC7SZ08FU
R3 100R
R4
180R
402
PERST#_buf (2)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
SYMBOL LEGEND
DO NOT
DNI
INSTALL
ACTIVE
#
LOW
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
C
8
7
6
5
4
3
Date: Sheet
2
105-A628XX-00A
DIGITAL
GROUND
ANALOG
GROUND
0
of
115Thursday, January 27, 2005
1
www.vinafix.vn
Page 3
5
4
3
2
1
U1A
TESTEN
AH30
PCIE_RX0P
AG30
PCIE_RX0N
AG29
PCIE_RX1P
AF29
PCIE_RX1N
AE29
PCIE_RX2P
AE30
PCIE_RX2N
AD30
PCIE_RX3P
AD29
PCIE_RX3N
AC29
PCIE_RX4P
AB29
PCIE_RX4N
AB30
PCIE_RX5P
AA30
PCIE_RX5N
AA29
PCIE_RX6P
Y29
PCIE_RX6N
W29
PCIE_RX7P
W30
PCIE_RX7N
V30
PCIE_RX8P
V29
PCIE_RX8N
U29
PCIE_RX9P
T29
PCIE_RX9N
T30
PCIE_RX10P
R30
PCIE_RX10N
R29
PCIE_RX11P
P29
PCIE_RX11N
N29
PCIE_RX12P
N30
PCIE_RX12N
M30
PCIE_RX13P
M29
PCIE_RX13N
L29
PCIE_RX14P
K29
PCIE_RX14N
K30
PCIE_RX15P
J30
PCIE_RX15N
AF26
PCIE_TX0P
AE26
PCIE_TX0N
AC25
PCIE_TX1P
AB25
PCIE_TX1N
AC27
PCIE_TX2P
AB27
PCIE_TX2N
AC26
PCIE_TX3P
AB26
PCIE_TX3N
Y25
PCIE_TX4P
W25
PCIE_TX4N
Y27
PCIE_TX5P
W27
PCIE_TX5N
Y26
PCIE_TX6P
W26
PCIE_TX6N
U25
PCIE_TX7P
T25
PCIE_TX7N
U27
PCIE_TX8P
T27
PCIE_TX8N
U26
PCIE_TX9P
T26
PCIE_TX9N
P25
PCIE_TX10P
N25
PCIE_TX10N
P27
PCIE_TX11P
N27
PCIE_TX11N
P26
PCIE_TX12P
N26
PCIE_TX12N
L25
PCIE_TX13P
K25
PCIE_TX13N
L27
PCIE_TX14P
K27
PCIE_TX14N
L26
PCIE_TX15P
K26
PCIE_TX15N
AF27
PCIE_REFCLKP
AE27
PCIE_REFCLKN
AC23
PCIE_CALRP
AB24
PCIE_CALRN
AB23
PCIE_CALI
402
AE25
PCIE_TEST
AD24
PWRGD_MASK
AD25
PWRGD
AH21
R2SET
AJ22
C_R_PR
AK21
Y_G
AK22
COMP_B_PB
AJ24
H2SYNC
AK24
V2SYNC
AG22
DDC3CLK
AG23
DDC3DATA
AJ23
NC#AJ23
AH24
NC#AH24
AH28
XTALIN
AJ29
XTALOUT
AH27
TESTEN
E8
TEST_YCLK
B6
TEST_MCLK
AF25
PLLTEST
AH25
STEREOSYNC
RV370GL
PCI Express
Part 1 of 6
DAC2CLK
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_PWRCNTL
GPIO_MEMSSIN
DVOVMODE
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVO / EXT TMDS / GPIOTMDSDAC1
DVPDATA_22
DVPDATA_23
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_3
VREFG
NC#AH15
NC#AH16
NC#AJ16
NC#AJ17
NC#AJ18
NC#AK18
NC#AJ20
NC#AJ21
NC#AK19
NC#AJ19
NC#AG16
NC#AG17
NC#AF16
NC#AF17
NC#AE18
NC#AE19
NC#AF19
NC#AF20
NC#AG19
NC#AG20
NC#AE12
NC#AG12
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DDC2CLK
DDC2DATA
HPD1
HSYNC
VSYNC
RSET
DDC1DATA
DDC1CLK
GPIO__AUXWIN
DPLUS
DMINUS
THERM
R
G
B
PETp0_GFXRp0(1)
PETn0_GFXRn0(1)
PETp1_GFXRp1(1)
PETn1_GFXRn1(1)
PETp2_GFXRp2(1)
PETn2_GFXRn2(1)
PETp3_GFXRp3(1)
D D
C C
+PCIE_VDDR
R1009 150R
R1010 100R
R1011 10K
GND_R2SET
R46
4.7K
2 1
Y1
27_MHZ
Placed & grounded close to ASIC
SCL(1)
C71 15PF
C72 15PF
+3.3V_BUS
402
402
R45
4.7K
402 402
B B
TP6
402
402
402
R40 715R
402
1%
OPTION 1: Crystal Circuit
+3.3V_BUS
MY1
4
VCC
C18
2
GND
100nF
402
A A
27.000MHz
R27
220R
3
OUT
1
E/D
+3.3V_BUS
R28
130R
PETn3_GFXRn3(1)
PETp4_GFXRp4(1)
PETn4_GFXRn4(1)
PETp5_GFXRp5(1)
PETn5_GFXRn5(1)
PETp6_GFXRp6(1)
PETn6_GFXRn6(1)
PETp7_GFXRp7(1)
PETn7_GFXRn7(1)
PETp8_GFXRp8(1)
PETn8_GFXRn8(1)
PETp9_GFXRp9(1)
PETn9_GFXRn9(1)
PETp10_GFXRp10(1)
PETn10_GFXRn10(1)
PETp11_GFXRp11(1)
PETn11_GFXRn11(1)
PETp12_GFXRp12(1)
PETn12_GFXRn12(1)
PETp13_GFXRp13(1)
PETn13_GFXRn13(1)
PETp14_GFXRp14(1)
PETn14_GFXRn14(1)
PETp15_GFXRp15(1)
PETn15_GFXRn15(1)
GFXTp0_PERp0(1)
GFXTn0_PERn0(1)
GFXTp1_PERp1(1)
GFXTn1_PERn1(1)
GFXTp2_PERp2(1)
GFXTn2_PERn2(1)
GFXTp3_PERp3(1)
GFXTn3_PERn3(1)
GFXTp4_PERp4(1)
GFXTn4_PERn4(1)
GFXTp5_PERp5(1)
GFXTn5_PERn5(1)
GFXTp6_PERp6(1)
GFXTn6_PERn6(1)
GFXTp7_PERp7(1)
GFXTn7_PERn7(1)
GFXTp8_PERp8(1)
GFXTn8_PERn8(1)
GFXTp9_PERp9(1)
GFXTn9_PERn9(1)
GFXTp10_PERp10(1)
GFXTn10_PERn10(1)
GFXTp11_PERp11(1)
GFXTn11_PERn11(1)
GFXTp12_PERp12(1)
GFXTn12_PERn12(1)
GFXTp13_PERp13(1)
GFXTn13_PERn13(1)
GFXTp14_PERp14(1)
GFXTn14_PERn14(1)
GFXTp15_PERp15(1)
GFXTn15_PERn15(1)
PCIE_REFCLKP(1)
PCIE_REFCLKN(1)
1%
1%
1%
A_B/COMP/Pb_DAC2(13)
R32
1.0M
402
R1089 10K
PERST#_buf(1)
A_R/C/Pr_DAC2(13)
A_G/L/Y_DAC2(13)
A_HSYNC_DAC2(11)
A_VSYNC_DAC2(11)
R33
1.0K
402
+3.3V_BUS
R44
10K
402
R29
0R
402
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
AE10
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AG4
AH15
AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20
AE12
AG12
AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12
AE13
AE14
AF12
AK27
AJ27
AJ26
AJ25
AK25
AH26
AG25
AF24
AG24
AF11
AE11
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
DVOMODE
VID/DVO14
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23
R43 10K
+3.3V_BUS
C16
100nF
402
X5R
6.3V
AUXWIN
Put large test points
TP11
TP12
R35
1.0K
402
R34
1.0K
402
+3.3V_BUS
402
GPIO[6..0]
GPIO[13..8]
Mem_Strap1 (9)
Mem_Strap0 (9)
R22 10K
R23 10K
Pull-up to 1.8V
12bit-DVO mode for SDR
Ext. TMDS 1.8V DVO I/O
SVHS/YPrPbb (13)
LCDDATA16 (9)
LCDDATA17 (9)
DEMUX_SEL-TVO/VGA# (13)
VHAD0 (9)
Both resistors and
capacitor close to ASIC
+3.3V_BUS
R65
4.7K
402
GPIO[6..0] (9)
GPIO[13..8] (9)
+VDDR4
402
402
TMDS_TX0N (12)
TMDS_TX0P (12)
TMDS_TX1N (12)
TMDS_TX1P (12)
TMDS_TX2N (12)
TMDS_TX2P (12)
TMDS_TXCN (12)
TMDS_TXCP (12)
DVIDDCCLK (11)
DVIDDCDATA (11)
HPD_IntTMDS (12)
A_R_DAC1 (10,11,13)
A_G_DAC1 (10,11,13)
A_B_DAC1 (10,11,13)
A_HSYNC_DAC1 (1,10)
A_VSYNC_DAC1 (1,10)
CRT1DDCDATA (1,10)
CRT1DDCCLK (1,10)
P1
PLUG
ALT
Header_3_Pin_1X3
R39 499R
BOUNDARY SCAN TEST ACCESS
A_HSYNC_DAC1
SCL
CRT1DDCDATA
CRT1DDCCLK
A_VSYNC_DAC1
TESTEN
DEBUG BUS ACCESS
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23
GPIO10
GPIO11
GPIO12
GPIO13
+VDDR4
JU2
R584
10K
402
1
2
3
R585
10K
ALT
402
GND_RSET
402
1%
TP7
Placed & grounded close to ASIC
TP1
TP2
TP3
TP4
TP5
TP8
TP17
TP19
TP20
TP21
TRST/
TDO
TDI
TMS
TCK
TESTOUT(0)
TESTOUT(1)
TESTOUT(2)
TESTOUT(3)
TESTOUT(4)
TESTOUT(5)
TESTOUT(6)
TESTOUT(7)
TESTOUT(8)
TESTOUT(9)
TESTOUT(10)
TESTOUT(11)
OPTION 2: Oscillator Circuit
Options can overlap in layout
<Variant Name>
5
4
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
Date: Sheet
105-A628XX-00A
1
215Thursday, January 27, 2005
of
0
www.vinafix.vn
Page 4
1
2
3
4
5
6
7
8
QSA[7..0](8)
DQMA#[7..0](8)
MAA[13..0](8)
MDA[63..0](8)
A A
B B
C C
QSA[7..0]
DQMA#[7..0]
MAA[13..0]
MDA[63..0]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
U1B
H28
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
Part 2 of 6
MEMORY INTERFACE
H29
J28
J29
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8
RV370GL
MEMORY CHANNEL A
U1C
D7
MAA0
E22
MAA_0
MAA1
B22
MAA_1
MAA2
B23
MAA_2
MAA3
B24
MAA_3
MAA4
C23
MAA_4
MAA5
C22
MAA_5
MAA6
F22
MAA_6
MAA7
F21
MAA_7
MAA8
C21
MAA_8
MAA9
A24
MAA_9
MAA10
C24
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7
CSAb_0
CSAb_1
CLKA0b
CLKA1b
MVREFD
MVREFS
DIMA_0
DIMA_1
A
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
RASAb
CASAb
WEAb
CKEA
CLKA0
CLKA1
MAA11
A25
MAA12
E21
MAA13
B20
C19
DQMA#0
J25
DQMA#1
F29
DQMA#2
E25
DQMA#3
A27
DQMA#4
F15
DQMA#5
C15
DQMA#6
C11
DQMA#7
E11
QSA0
J27
QSA1
F30
QSA2
F24
QSA3
B27
QSA4
E16
QSA5
B16
QSA6
B11
QSA7
F10
RASA#
A19
CASA#
E18
WEA#
E19
CSA#0
E20
CSA#1
F20
CKEA
B19
CLKA0
B21
CLKA#0
C20
CLKA1
C18
CLKA#1
A18
B7
B8
D30
B13
RASA# (8)
CASA# (8)
WEA# (8)
CSA#0 (8)
CSA#1 (8)
CKEA (8)
CLKA0 (7,8)
CLKA#0 (7,8)
CLKA1 (7,8)
CLKA#1 (7,8)
+MVDDQ
R58
100R
402
R59
C154
100R
100nF
402
402
X5R
6.3V
Placed close to ASIC
C153
100nF
402
X5R
6.3V
+MVDDQ
R56
100R
402
R57
100R
402
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
RV370GL
Part 3 of 6
MEMORY INTERFACE
B
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
MEMORY CHANNEL B
VDDR1 MEMVMODE_0 MEMVMODE_1
1.8V
2.5V
2.8V
GND
+VDDC_CT GND
+VDDC_CT +VDDC_CT
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
RASBb
CASBb
WEBb
CSBb_0
CSBb_1
CKEB
CLKB0
CLKB0b
CLKB1
CLKB1b
DIMB_0
DIMB_1
ROMCSb
MEMVMODE_0
MEMVMODE_1
MEMTEST
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2
E6
B2
J5
G3
W6
W2
AC6
AD2
F6
B3
K6
G1
V5
W1
AC5
AD1
R2
T5
T6
R5
R6
R3
N1
N2
T2
T3
E3
AA3
AF5
C6
C7
C8
+VDDC_CT
ROMCS# (9)
R51 4.7K
R52 4.7K
DNI
R54
R53
4.7K
4.7K
R55
47R
402
402 402
DNI
+VDDC_CT
402
402
D D
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
1
2
3
4
5
6
Date: Sheet
7
105-A628XX-00A
0
of
315Thursday, January 27, 2005
8
www.vinafix.vn
Page 5
5
+MVDDQ
D D
+MVDDQ
C38
10uf
+MVDDQ
C32
1uF
402 402 402
C C
B B
C35
C33
1uF
1uF
+TPVDD
GND_TPVSS
+1.8V
B11
+TXVDDR_PINS
200R
ALT:
0R
+1.8V
+1.8V
GND_TXVSSR
B14
+A2VDDQ
200R
ALT: 0R
GND_A2VSSQ
AVDD/A2VDDQ (1st & 2nd
DAC Band Gap) - 200mA
B13
+AVDD
200R
ALT: 0R
GND_AVSSN
C31
1uF
402 402402
C50
10uf
OPT
C59
4.7uF
C63
4.7uF
C67
4.7uF
C74
1uF
C43
2.2uF
ALT:
1uF
C60
1uF
402
C64
1uF
402
C68
1uF
402
C75
1uF
C58
2.2uF
ALT:
1uF
C81
1uF
402
C94
1uF
1uF
402402 402402
C73
1uF
402
+1.8V
B12
200R
ALT: 0R
1uF
GND_A2VSSN
+VDDOI_PINS
C66
4.7uF
1uF
+A2VDD
C62
1.0uF
603
C65
1uF
402
C97
C96
C95
+MVDDQ
AE15
AE16
AE17
AF15
AH19
AH13
AF13
AF14
AE20
AF21
AF23
AH23
AE23
AE22
AK28
K23
K24
L23
H10
H13
H15
H17
AA1
AA4
AA7
AA8
A15
A21
A28
B30
D26
D23
D20
D17
D14
D11
E27
G10
G13
G15
G19
G22
G27
H22
H19
AD4
F18
T7
R4
R1
N8
N7
M4
L8
J8
J7
J4
J1
T8
V4
V7
V8
A3
A9
B1
D8
D5
F4
G7
N4
N6
A7
U1D
RV370GL
4
VDDR1#T7
VDDR1#R4
VDDR1#R1
VDDR1#N8
VDDR1#N7
VDDR1#M4
VDDR1#L8
VDDR1#K23
VDDR1#K24
VDDR1#L23
VDDR1#J8
VDDR1#J7
VDDR1#J4
VDDR1#J1
VDDR1#H10
VDDR1#H13
VDDR1#H15
VDDR1#H17
VDDR1#T8
VDDR1#V4
VDDR1#V7
VDDR1#V8
VDDR1#AA1
VDDR1#AA4
VDDR1#AA7
VDDR1#AA8
VDDR1#A3
VDDR1#A9
VDDR1#A15
VDDR1#A21
VDDR1#A28
VDDR1#B1
VDDR1#B30
VDDR1#D26
VDDR1#D23
VDDR1#D20
VDDR1#D17
VDDR1#D14
VDDR1#D11
VDDR1#D8
VDDR1#D5
VDDR1#E27
VDDR1#F4
VDDR1#G7
VDDR1#G10
VDDR1#G13
VDDR1#G15
VDDR1#G19
VDDR1#G22
VDDR1#G27
VDDR1#H22
VDDR1#H19
VDDR1#AD4
VDDR1#N4
NC#AE15
NC#AE16
NC#AE17
NC#AF15
NC#AH19
TPVDD
TXVDDR#AF13
TXVDDR#AF14
VDDRH0
VDDRH1
A2VDD#AE20
A2VDD#AF21
A2VDDQ
AVDD
VDD1DI
VDD2DI
PVDD
MPVDD
Part 4 of 6
PCIE_VDDR_12#AG26
PCIE_VDDR_12#AG27
PCIE_VDDR_12#AG28
PCIE_VDDR_12#AJ30
PCIE_VDDR_12#AK29
PCIE_PVDD_12#N23
PCIE_PVDD_12#N24
PCIE_PVDD_12#P23
PCIE_PVDD_18#T23
PCIE_PVDD_18#U23
PCIE_PVDD_18#V23
PCIE_PVDD_18#W23
I/O POWER
VDDC#AC13
VDDC#AC15
VDDC#AC17
VDDC#AD13
VDDC#AD15
VDD15#H11
VDD15#H20
VDD15#M23
VDD15#P8
VDD15#Y23
VDD15#Y8
VDD15#AC11
VDD15#AC20
VDDR3#AC8
VDDR3#AC19
VDDR3#AC21
VDDR3#AC22
VDDR3#AD7
VDDR3#AD19
VDDR3#AD21
VDDR4#AC9
VDDR4#AC10
VDDR4#AD9
VDDR4#AD10
VDDR4#AG7
NC#D9
NC#D13
NC#D19
NC#D25
NC#E4
NC#T4
NC#AB4
NC#AF18
NC#AG15
NC#AG18
NC#AH17
NC#AH18
TPVSS
TXVSSR#AH14
TXVSSR#AG13
TXVSSR#AG14
VSSRH0
VSSRH1
A2VSSN#AH20
A2VSSN#AG21
A2VSSQ
AVSSN
AVSSQ
VSS1DI
VSS2DI
PVSS
MPVSS
AC13
AC15
AC17
AD13
AD15
H11
H20
M23
P8
Y23
Y8
AC11
AC20
AC8
AC19
AC21
AC22
AD7
AD19
AD21
AC9
AC10
AD9
AD10
AG7
D9
D13
D19
D25
E4
T4
AB4
AG26
AG27
AG28
AJ30
AK29
N23
N24
P23
T23
U23
V23
W23
AF18
AG15
AG18
AH17
AH18
AH12
AH14
AG13
AG14
F19
M6
AH20
AG21
AF22
AH22
AD22
AE24
AE21
AJ28
A6
+VDDC
+VDDC_CT
+3.3V_BUS
TP10
GND_TPVSS
GND_TXVSSR
GND_A2VSSN
GND_A2VSSQ
GND_AVSSN
GND_PVSS
GND_MPVSS
+VDDR4
C70
4.7uF
+PCIE_VDDR
+PCIE_PVDD_12
+PCIE_PVDD_18
GND_AVSSQ
+VDDC
C69
1uF
402
C20
1uF
+3.3V_BUS
TP9
3
C99
1.0uF
2
+VDDC
C24
10uf
+VDDC
C26
1uF
C86
+VDDC_CT
C40
1uF
C42
1uF
C56
1uF
1uF
C45
1uF
402 402 402 402402 402
C76
1uF
402 402
C78
1uF
402 402
C57
1uF
402 402
C87
C88
1uF
1uF
C47
C48
1uF
1uF
C77
1uF
C79
1uF
C61
1uF
C21
C22
1uF
1uF
402 402402
C98
1.0uF
C82
C23
1uF
1uF
402 402 402 402 402 402 402 402402 402 402 402 402
C37
1.0uF
C969
C968
1.0uF
1.0uF
603
603
C971
C970
1.0uF
1.0uF
603 603
C83
1uF
C44
1uF
C84
1uF
+3.3V_BUS
C39
1uF
402 402603 603 603
C41
1uF
402 402
C55
1uF
402 402
C85
1uF
C46
1uF
C28
C27
1uF
402 402 402 402402
C89
1uF
C49
1uF
C29
1uF
1uF
C90
C91
1uF
1uF
+VDDC
U1F
P17
VDDC#P17
P18
VDDC#P18
P19
VDDC#P19
U12
VDDC#U12
U13
AD12
AG11
VDDC#U13
U14
VDDC#U14
U17
VDDC#U17
U18
VDDC#U18
U19
VDDC#U19
V19
VDDC#V19
V18
VDDC#V18
V17
VDDC#V17
V14
VDDC#V14
V13
VDDC#V13
V12
VDDC#V12
N18
VDDC#N18
N17
VDDC#N17
N14
VDDC#N14
W17
VDDC#W17
W18
VDDC#W18
W12
VDDC#W12
W13
VDDC#W13
W14
VDDC#W14
N13
VDDC#N13
N19
VDDC#N19
M19
VDDC#M19
M18
VDDC#M18
M12
VDDC#M12
N12
VDDC#N12
M13
VDDC#M13
M14
VDDC#M14
P12
VDDC#P12
P13
VDDC#P13
RV370GL
U1E
A2
VSS#A2
A10
VSS#A10
A16
VSS#A16
A22
VSS#A22
A29
VSS#A29
C1
VSS#C1
C3
VSS#C3
C28
VSS#C28
C30
VSS#C30
D27
VSS#D27
D24
VSS#D24
D21
VSS#D21
D18
VSS#D18
D15
VSS#D15
D12
VSS#D12
D6
VSS#D6
D4
VSS#D4
D10
VSS#D10
F27
VSS#F27
G9
VSS#G9
G12
VSS#G12
G16
VSS#G16
G18
VSS#G18
G21
VSS#G21
G24
VSS#G24
H27
VSS#H27
H23
VSS#H23
H21
VSS#H21
H18
VSS#H18
H16
VSS#H16
H14
VSS#H14
H12
VSS#H12
H9
VSS#H9
H8
VSS#H8
H4
VSS#H4
J23
VSS#J23
J24
VSS#J24
VSS#AD12
AG5
VSS#AG5
AG9
VSS#AG9
VSS#AG11
R7
VSS#R7
P4
VSS#P4
M7
VSS#M7
M8
VSS#M8
L4
VSS#L4
K1
VSS#K1
K7
VSS#K7
K8
VSS#K8
R8
VSS#R8
T1
VSS#T1
W8
VSS#W8
W7
VSS#W7
U8
VSS#U8
U4
VSS#U4
Y4
VSS#Y4
RV370GL
C30
1uF
C93
C92
1uF
1uF
1
Part 6 of 6
VSS#M16
VSS#N16
VSS#N15
VSS#P15
VSS#P16
VSS#R18
VSS#R17
VSS#R16
VSS#R15
VSS#R14
VSS#R13
VSS#R12
VSS#T13
VSS#T14
VSS#T15
VSS#W15
VSS#V16
VSS#V15
VSS#U15
VSS#U16
VSS#T19
VSS#T18
VSS#T17
VSS#T16
CENTER ARRAY
VDDCI#W16
VDDCI#M15
VDDCI#R19
VDDCI#T12
VDDC#W19
VDDC#M17
VDDC#P14
Part 5 of 6
CORE GND
PCIE_VSS#AA23
PCIE_VSS#AA24
PCIE_VSS#AA25
PCIE_VSS#AA26
PCIE_VSS#AA27
PCIE_VSS#AA28
PCIE_VSS#AB28
PCIE_VSS#AC28
PCIE_VSS#AD26
PCIE_VSS#AD27
PCIE_VSS#AD28
PCIE_VSS#AE28
PCIE_VSS#AF28
PCIE_VSS#AH29
M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16
W16
M15
R19
T12
W19
M17
P14
VSS#AB8
VSS#AB7
VSS#AB1
VSS#AC4
VSS#AC12
VSS#AC14
VSS#AD16
VSS#AC16
VSS#AC18
VSS#AD18
VSS#AK2
VSS#AJ1
PCIE_VSS#K28
PCIE_VSS#L28
PCIE_VSS#M24
PCIE_VSS#M25
PCIE_VSS#M26
PCIE_VSS#M27
PCIE_VSS#M28
PCIE_VSS#N28
PCIE_VSS#P28
PCIE_VSS#R23
PCIE_VSS#R24
PCIE_VSS#R25
PCIE_VSS#R26
PCIE_VSS#R27
PCIE_VSS#R28
PCIE_VSS#T24
PCIE_VSS#T28
PCIE_VSS#U28
PCIE_VSS#V24
PCIE_VSS#V25
PCIE_VSS#V26
PCIE_VSS#V27
PCIE_VSS#V28
PCIE_VSS#W24
PCIE_VSS#W28
PCIE_VSS#Y28
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD18
AK2
AJ1
K28
L28
M24
M25
M26
M27
M28
N28
P28
R23
R24
R25
R26
R27
R28
T24
T28
U28
V24
V25
V26
V27
V28
W24
W28
Y28
AA23
AA24
AA25
AA26
AA27
AA28
AB28
AC28
AD26
AD27
AD28
AE28
AF28
AH29
+PVDD
C54
C53
4.7uF
1uF
A A
GND_MPVSS
5
GND_PVSS
+MPVDD
C52
4.7uF
402
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
C51
1uF
402
4
3
2
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
C
Date: Sheet
105-A628XX-00A
1
of
415Thursday, January 27, 2005
0
www.vinafix.vn
Page 6
8
7
6
5
4
3
2
1
Regulator for VDDC (ASIC Core)
VDDC-PWM1
U201
VDDC_EN
VDDC_FB
+PW_VDDC_M
R148 10K
1
HSD
ILIM
2
COMP
3
FB
GND
9
LX
10
BST
PGND
MAX1954EUB
MAXIM MAX1954
MAXIM MAX1954A
VDDC_EN
402
VDDC-PWM2
U202
1
RT
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
ISL6522CB
INTERSIL ISL6522
RICHTEK RT9232A
ANPEC APW7062A
ANPEC APW7062B
DH
DL
+VDDC_S
603
R147
1%
301K
C248
C249
470pF
47PF
402
402
X7R
+VDDC_S
NPO
5%
R149 30.1K
402
C1013 1nF
R150 2.37K
402
R336 0R
402
+VDDC_B
+3.3V_BUS
VDDC_RT
402
X7R10V
VDDC_OCS
VDDC_SS
VDDC_COMP_U202
VDDC_FB
D D
VDDC_COMP
C1015
22nf
603
C C
+PW_VDDC_HGD
8
+PW_VDDC_LGD
6
5
+VDDC_VCC
IN
4
7
+12V_BUS_F2
C1014
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
14
VCC
13
12
11
10
9
8
+VDDC_B
0.22uF
+PW_VDDC_LGD
+PW_VDDC_HGD
+PW_VDDC_M
+PW_VDDC_HGD
+PW_VDDC_M
+PW_VDDC_LGD
VDDC_FB
R140 0R
R141 0R
402
402
Q200
QH
4 5
3
2
1
FDS7096N3
Q201
QL
4 5
3
2
1
FDS7096N3
Fairchild FDS6680AS p/n 2020015300
Infineon BSO119N03S p/n 2020015600
Thermal
Pad
Thermal
Pad
9
6
7
8
9
6
7
8
+VDDC_S
*** ***
C1000
10uF
1210
*** ***
L200 2.2uH
1 2
R142
1.0R
805
Rs
1%
C1007
10nF
Cs
402
X7R
Place Rs and Cs across QL
C1001
10uF
1210 1206
C1002
1uF
R1
R20
1.0K
402
1%
R4
R21
1.78K
402
1%
C1003
150nF
603
C1006
100nF
R143
1.0K
Place R1 and
R4 close to
PWM and
routed with
separate
20mil trace to
the ASIC
+12V_BUS
B200
60R
***
+VDDC
***
C1005
470uF_10V
***
DUAL FOOTPRINT
0.8V Ref
R4 = (R1 x 0.8V) / (Vout1 - 0.8V)
***
MC1005
470uF
***
ALT
POLY
Vout = 1.2V ~ 1.3V
Part
0.8V Ref 1.2V
***
C1019
470uF_10V
***
Vout
1.25V
1.3V 1.00K 1%
***
MC1019
470uF
***
ALT
POLY
DUAL FOOTPRINT
1.00K 1%
ATI P/N 3240100100
1.00K 1%
ATI P/N 3240100100
ATI P/N 3240100100
R2R1
2.00K 1%
ATI P/N 3240200100
1.78K 1%
ATI P/N 3240178100
1.6K 1%
ATI P/N 3240162100
R137
10K
402
1%
R138
3.65K
402
1%
Note 3
+PCIE_VDDR
+PCIE_VDDR: 1.2V 1300mA MAX
C160
22uF_16V
+PCIE_PVDD_12
+PCIE_PVDD_12: 1.2V 100mA MAX
C310
22uF_16V
R132
4.7K
402
Note 1
Q108
1
CMPT3904
2 3
Q106
1
CMPT3904
2 3
5mA
4
R136
0R
402
DNI
+MPVDD: 10mA MAX
+PVDD: 25mA MAX
+TPVDD: 50mA MAX
+PCIE_PVDD_18
L4
1.8uH
ALT
5260002100
VDDC_EN
Q107
1
CMPT3904
2 3
Alt. Regulator for PCIE_PVDD_18
Vout = 1.82V
Iout = 500mA MAX
+3.3V_BUS
MREG36
LT1117CST
IN3OUT
CASE
ADJ
C163
1
10uf
1206
6.3V
Y5V
3
R297
49.9R
1%
Title
Size Document Number Rev
Custom
Date: Sheet
2
+PVDD +TPVDD+1.8V +MPVDD
L10
1.8uH
5260002100
Need at least a 10uF Tant.
output cap for stability
Min. Load Current: 10mA
L11
1.8uH
5260002100
L9
1.8uH
ALT: 0R ALT: 0R ALT: 0RALT: 0R
5260002100
Rails derived from +1.8V
+AVDD: 10mA MAX
+A2VDDQ: 20mA MAX
+VDDOI_PINS: 20mA MAX
+TXVDDR_PINS: 20mA MAX
+PCIE_PVDD_18
2
4
R296
110R
1%
C164
402
10uF_6.3V
Tant
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
105-A628XX-00A
1
0
of
515Thursday, January 27, 2005
VDDC-PWM3
+PW_VDDC_HGD
+VDDC_B
+PW_VDDC_LGD
VDDC_FB
B B
VDDC_COMP
+12V_BUS_F2
R335 0R
402
VDDC_COMP_U204
U203
2
UGATE
PS
OPS
3
GND
1
BOOT
FB
LGATE4VCC
RT9214CS
RICHTEK RT9214
INTERSIL ISL6545
VDDC-PWM4
U204
2
UGATE
PS
OPS
3
GND
1
BOOT
FB
LGATE4VCC
RT9214CS
8
7
6
5
8
7
6
5
+PW_VDDC_M
VDDC_EN
VDDC_FB
+VDDC_B
R332 1K
R152 20K
+12V_BUS_F2
C1018
0.22uF
402
402
+PW_VDDC_LGD
+PW_VDDC_HGD
+PW_VDDC_M
+VDDC
+VDDC
ANPEC APW7061
R333 0R
402
VDDC_EN VDDC_COMP
R1
0R
R2
0R
POWER SEQUENCING
+3.3V_BUS +12V_BUS+5V
R131
4.75K
402
1%
Note 2
COMPENSATION CIRCUIT FILTERED +12V_BUS BOOT CIRCUIT
MR310
0R
402 402
21
D2
RB501V-40
R146
0R
16V
+5V+12V_BUS
402
R310
0R
C1009
150nF
+PW_VDDC_M
+VDDC_VCC
+VDDC_B
+12V_BUS
R334
0R
402402
A A
C1017
10nF
10V
402
10%
R151
10K
402
1%
C1016
33pF
603
50V
10%
NPOX7R
R331 0R
MR331
0R
402
8
VDDC_COMP
VDDC_FB
402
+12V_BUS_F2
7
+12V_BUS
R144
2.2R
C1008
100nF
1
MD2
BAT54SLT1
3
603
X7R
5%
2
C1010
100nF
603
X7R
5%
6
R133
2K
402
1%
Power Sequence Circuit to ensure SMPS_EN is released after
+12V and +3.3V are both in regulation.
When +12V ramps above min Vbe, SMPS_EN will be helt lowNote 1
Note 2
When +3.3V gets closed to regulation, one of the two
conditions of releasing SMPS_EN is active
Target for 920mV when +3.3 at min regulation (worse case)
Typical trigger when +3.3V ramps above 2.2V (650mV)
Note 3
When +5V (derived from +12V) gets closed to regulation,
one of the two conditions of releasing SMPS_EN is active
Target for 1.2V when +5 at min regulation (worse case)
Typical trigger when +5V ramps above 3.2V (850mV)
5
www.vinafix.vn
Page 7
5
4
3
2
1
Place caps very
+12V_BUS
close to power pin
C13
C12
100nF
+3.3V_BUS
R811
33R
603
C800
REG9
D D
TL431CDBVR
5 3
0.8V
1.25V
1.5V
1.8V
1.84V
C C
1.5
1.55
1.6V
1.7V
1.8175V 681R
Voltage Req.
3.3V
2.7V
2.65V 301R
B B
2.61V 221R (402, 1%) (402, 1%)
2.55V 22.1R
2.5V 0R
10uF_6.3V
4
NC
1
NC
2
R1 R2Voltage Req.
150R
P/N 3160150000
100R
P/N 3160100000 402 P/N 3160100000 402
100R
54.9R
P/N 3240054900
49.9R 140R
P/N 3240049900
Rx1 for 1.25V Ref
432R
P/N 3240432000
(402, 1%)
P/N 3160475000
432R
P/N 3240432000
432R
P/N 3240432000
P/N 3240681000
P/N 3160681000 402
Ry1 for 2.5V Ref
1.07K
301R (402, 1%)
P/N 3160301000
(402, 1%) (402, 1%)
P/N 3160301000
316022R100G 4022.5V Ref
P/N 3230000000
P/N 3150000000 402
2.5V_REF2
R812
100R
R1
1%
402
1.25V_REF2
R813
100R
R2
1%
402
71.5R
402
P/N 324075R500
100R
150R
402P/N 3160100000
140R
P/N 3240140000
P/N 3240140000
Rx2 for 1.25V RefVoltage Req.
2.15K
P/N 3240215100
2K
(1%)475R
P/N 3160200100 (402)
P/N 3240200100 (603)
1.5K
P/N 3240150100
1.21K
P/N 3240121100
1.5K
603
P/N 3240150100
Ry2 for 2.5V Ref
3.32K
P/N 3240332100P/N 3240107100
3.32K
P/N 3240332100
4.99K
P/N 3160499100
4.99K
P/N 3160499100P/N 3160221000
1,1K
3240110100G 603
DNI
603
1.25V_REF2
R101 1K
3
402
2
R103
2K
603
Rx2
2.5V_REF2
MR105 1K
402
402P/N 3160150000
1.25V_REF2
2.5V_REF2
1%
R105 1K
1%
R109 1K
5
402
6
R107
1.1K
603
1%
Rx2
12
402
13
R111
1K
402
Rx2
2.5V_REF2
R113 1K
10
402
9
R115
1K
402
Rx2
Alt. regulator for +PVDD
Vout = 1.8V
Iout = 30mA MAX
A A
+PVDD
+3.3V_BUS +3.3V_BUS
R284
33R
R287
681R
1%
R290
1.5K
1%
Rt1
402
Rt2
4
1
2
5
NC
NC
GND_PVSS
5 3
MREG40
SC431LC5SK-1
REG40
AS432S
1
3 2
Alt regulator for +MPVDD
Vout = 1.8V
Iout = 10mA MAX
+MPVDD
R285
75R
3 2
REG32
AS432S
R288
Rt1
681R
402
1%
R291
1.5K
1%
4
NC
1
NC
2
Rt2
402402
GND_MPVSS
1
5 3
MREG32
SC431LC5SK-1
4
Alt. regulator for +TPVDD
Vout = 1.65V ~ 1.85V
Iout = 20mA MAX
603
X7R
411
U81A
+
1
-
LM324M
R102 475R
402
Rx1
U81B
+
7
-
LM324M
402
Rx1
R106 681R
MR106 22.1R
402
1%
Rx1
Req = 120.7R
Use 845R, 1206, 1/4W
U81D
+
14
-
LM324M
R110 1K
402
Rx1
U81C
+
8
-
LM324M
R114 1K
402
Rx1
R286
56R
REG39
AS432S
1
3 2
100nF
603
X7R
G_MVDDQ
+TPVDD+3.3V_BUS
R289
604R
1%
R292
1.37K
1%
+3.3V_BUS
1
+3.3V_BUS
1
+MVDD
1
1
Rt1
402
4
1
2
Rt2
402
Q31
CMPT3904
200mA, SOT-23
2 3
CMPT3904: 40V 200mA
MMBT2222: 40V 600mA
R108 0R
Q32
CMPT3904
200mA, SOT-23
2 3
CMPT3904: 40V 200mA
MMBT2222: 40V 600mA
R911
R912
845R
845R
Q33
CMPT3904
200mA, SOT-23
2 3
CMPT3904: 40V 200mA
MMBT2222: 40V 600mA
Assumed ~ 3V drops
R1044 110R
Q34
CMPT3904
200mA, SOT-23
2 3
CMPT3904: 40V 200mA
MMBT2222: 40V 600mA
MREG39
NC
SC431LC5SK-1
NC
5 3
GND_TPVSS
+VDDC_CT
1.5V ~ 1.55V
100mA MAX
180mW MAX
+VDDC_CT
C302
10uF_6.3V
Tant
G_MVDD
402
+TPVDD
C303
10uF_6.3V
Tant
R914
R915
R913
845R
845R
1/4 W
Alt. regulator for +VDDC_CT
Vout = 1.5V ~ 1.55V
Iout = 100mA MAX
3
845R
+5V
5V
25mA MAX
100mW MAX
R293
56R
REG33
AS432S
3 2
R916
845R
C901
10uF_6.3V
Tant
C9
10uF
16V
X5R
C315
10uF_6.3V
Tant
1
R917
845R
+VDDC_CT+3.3V_BUS
MC901
10uf
1206
16V
Y5V
C10
100nF
6031210
16V 16V
X7R X7R
C14
10uf
1206
6.3V
Y5V
R294
604R
1%
R295
1.37K
1%
Regulator for +MVDD (MVDDC, MVDDQ)
Vout = 2.5V
Iout <= 2A
+3.3V_BUS+MVDD_IN
R1264 0R
1/4W
1206
R1265 0R
1206
D5
1N5400
D4
1N5400
3A, 0.7~0.8V
C308
47uF_6.3V
DNI
Place Big Copper Area Under Q302
For Heat Dissipation.
C902
10uF
16V
X5R
+5V_VESA
+12V_BUS
C11
100nF
603
+5V
C15
1.0uF
603
10V
Y5V
Rt1
402
4
NC
1
NC
2
Rt2
5 3
402
These dummy resistors are
placed under the diode.
1/4W
21
DNI
21
DNI
C903
100nF
6031210
16V 16V
X7R X7R
R1260
0R
Use D4, D5 When +MVDDC/Q=1.8V
4
Q302
MTD3055V
32
C305
1
100nF
G_MVDD
+12V_BUS
C904
100nF
603
Option to tide on
board +5V from
+5V_VESA for cost
saving; if +5V_VESA is
402
overloaded or shorted,
board will not
function
R5
0R
MREG33
SC431LC5SK-1
R1261
0R
C306
100nF
DNI
R1263
R1262
0R
0R
+MVDDC+MVDD +MVDDQ
C307
470uF_10V
2
C300
470uF_10V
R903 0R
Alt. regulator for +A2VDD
Vout = 2.5V
Iout = 120mA MAX
+A2VDD+3.3V_BUS
REG35
1
VIN
3
SHDN
C139
1.0uF
603
X5R
Alt. regulator for +MVDD
Vout = 2.5V ~ 2.6V
Iout <= 2A MAX
G_MVDD
1
3 2
REG34
AS432S
+12V_BUS
C141
100nF
603
X7R
5%
BYPASS
GND
2.5V
2
GND_A2VSSN
4
NC
1
NC
2
5 3
VOUT
R950
750R
/.25W
MREG34
SC431LC5SK-1
5
4
Alt regulator for +5V_VESA
R901
1.0K
1%
4
NC
402
1
NC
R902
2
5 3
TL431CDBVR
Normal +5V regulated operation
If Iload > 55mA, +5V will drop
If Vout is shorted
1.61V 432R
1.69V
1.718V
1.75V
1.0K
1%
REG19
402
This circuit provide upto 55mA
Current across each Rx is 12V/845R = 14.2mA
Power dissipated by each Rx is 14.2mA x 12V = 171mW
Each Rx are rated 250mW (1/4W)
Derating 250mW by 70% is 175mW (1/4W)
Rt1
32404320001.52V 432R
3160432000 3160215100
3240432000
3240432000432R
3240562000
562R
3160604000604R
3160604000 604R1.8V
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
Date: Sheet
Rt2
2.15K
1.5K
1.5K 3160150100
1.21K
1.5K 3160150100
1.5K 3160150100
105-A628XX-00A
1
+A2VDD
C140
1uF
+MVDD
R959
1.0K
1%
402
R961
1.0K
1%
402
3230015200
3240121100
32300152001.5K
32300152001.5K
31601371001.37K
615Thursday, January 27, 2005
Rm1
Rm2
of
+MVDDC
L5
1.8uH
ALT: 0R
0
www.vinafix.vn
Page 8
5
4
3
2
1
MDA[63..0] M_MDA[63..0]
MDA[63..0](3,8)
MDA2 M_MDA2
D D
C C
QSA[7..0]
QSA[7..0](3,8)
MDA5 M_MDA5
MDA6 M_MDA6
MDA7 M_MDA7
MDA13 M_MDA13
MDA16 M_MDA16
MDA19 M_MDA19
MDA20 M_MDA20
MDA22 M_MDA22
MDA23 M_MDA23
MDA24 M_MDA24
MDA26 M_MDA26
MDA28 M_MDA28
MDA29 M_MDA29
MDA30 M_MDA30
MDA32 M_MDA32
MDA35 M_MDA35
MDA37 M_MDA37
MDA40 M_MDA40
MDA41 M_MDA41
MDA42 M_MDA42
MDA44 M_MDA44
MDA45 M_MDA45
MDA46 M_MDA46
MDA47 M_MDA47
MDA49 M_MDA49
MDA50 M_MDA50
MDA53 M_MDA53
MDA54 M_MDA54
MDA55 M_MDA55
MDA58 M_MDA58
MDA59 M_MDA59
MDA60 M_MDA60
MDA61 M_MDA61
MDA62 M_MDA62
MDA63 M_MDA63
QSA1 M_QSA1
QSA2 M_QSA2
QSA4 M_QSA4
QSA5 M_QSA5
QSA6 M_QSA6
QSA7 M_QSA7
M_MDA0MDA0
M_MDA1MDA1
M_MDA3MDA3
M_MDA4MDA4
M_MDA8MDA8
M_MDA9MDA9
M_MDA10MDA10
M_MDA11MDA11
M_MDA12MDA12
M_MDA14MDA14
M_MDA15MDA15
M_MDA17MDA17
M_MDA18MDA18
M_MDA21MDA21
M_MDA25MDA25
M_MDA27MDA27
M_MDA31MDA31
M_MDA33MDA33
M_MDA34MDA34
M_MDA36MDA36
M_MDA38MDA38
M_MDA39MDA39
M_MDA43MDA43
M_MDA48MDA48
M_MDA51MDA51
M_MDA52MDA52
M_MDA56MDA56
M_MDA57MDA57
M_QSA0QSA0
M_QSA3QSA3
M_QSA[7..0]
M_MDA[63..0] (3,8)
M_QSA[7..0] (3,8)
CLOCK
terminations
CLKA0(3,8)
CLKA#0(3,8)
CLKA1(3,8)
CLKA#1(3,8)
M_CLKA0 (3,8)
M_CLKA#0 (3,8)
M_CLKA1
M_CLKA1 (3,8)
M_CLKA#1 (3,8)
M_CLKA0
M_CLKA#0
M_CLKA#1
R797
56R
R798
56R
R799
56R
R800
56R
C778
10nF
C779
10nF
B B
A A
M_DQMA#[7..0](3,8)
M_MAA[13..0](3,8)
M_RASA#(3,8)
M_CASA#(3,8)
M_WEA#(3,8)
M_CSA#0(3,8)
M_CSA#1(3,8) CSA#1 (3,8)
M_CKEA(3,8)
5
M_DQMA#[7..0]
M_MAA[13..0]
M_DQMA#0 DQMA#0
M_DQMA#1 DQMA#1
M_DQMA#2 DQMA#2
M_DQMA#3 DQMA#3
M_DQMA#4 DQMA#4
M_DQMA#5 DQMA#5
M_DQMA#6 DQMA#6
M_DQMA#7 DQMA#7
M_MAA1 MAA1
M_MAA3 MAA3
M_MAA4 MAA4
M_MAA6 MAA6
M_MAA8 MAA8
M_MAA9 MAA9
M_MAA10 MAA10
M_MAA11 MAA11
M_RASA#
M_CASA#
M_WEA#
M_CSA#0
M_CSA#1
M_CKEA
MAA0M_MAA0
MAA2M_MAA2
MAA5M_MAA5
MAA7M_MAA7
MAA12M_MAA12
MAA13M_MAA13
RASA# (3,8)
CASA# (3,8)
WEA# (3,8)
CSA#0 (3,8)
CKEA (3,8)
4
DQMA#[7..0]
MAA[13..0]
DQMA#[7..0] (3,8)
MAA[13..0] (3,8)
<Variant Name>
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
Date: Sheet
105-A628XX-00A
1
of
715Thursday, January 27, 2005
0
www.vinafix.vn
Page 9
8
7
6
5
4
3
2
1
M_DQMA#[7..0](3)
D D
M_QSA[7..0](3)
C C
M_MAA[13..0](3)
B B
M_DQMA#[7..0]
M_QSA[7..0]
M_CLKA#0(3,7)
M_CLKA#1(3,7)
M_CLKA0(3,7)
M_CLKA1(3,7)
M_CKEA(3)
M_WEA#(3)
M_CASA#(3)
M_RASA#(3)
M_CSA#0(3)
M_CSA#1(3)
M_MAA[13..0]
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_CLKA0#
M_CLKA1#
M_CLKA0
M_CLKA1
M_CKEA
M_WEA#
M_CASA#0
M_RASA#0
M_CSA#0
M_CSA#1
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_CSA#1
M_CLKA#0
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_DQMA#2
M_DQMA#1
M_DQMA#3
M_DQMA#0
M_CLKA0
M_CKEA
M_MDA[63..0](3)
U29
M_MAA12
M3
BA0
M_MAA13
L4
BA1
M_MAA11
L6
A11
M_MAA10
K5
A10
M_MAA9
L7
A9
M_MAA8
M10
A8/AP
M_MAA7
M9
A7
M_MAA6
M8
A6
M_MAA5
L8
A5
M_MAA4
M7
A4
M_MAA3
M6
A3
M_MAA2
L5
A2
M_MAA1
M5
A1
M_MAA0
M4
A0
B3
NC
B10
NC#B10
G3
NC#G3
G10
NC#G10
K11
NC#K11
K12
NC#K12
L2
NC#L2
L3
NC#L3
M2
NC#M2
L12
MCL
M12
VREF
L9
RFU#L9
K8
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE
DQS3
DQS2
DQS1
DQS0
TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8
1MX32X4
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9
VDDQ#B11
VDDQ#D2
VDDQ#D11
VDDQ#E3
VDDQ#E10
VDDQ#F3
VDDQ#F10
VDDQ#H3
VDDQ#H10
VDDQ#J3
VDDQ#J10
VDD#C7
VDD#D3
VDD#D10
VDD#K3
VDD#K6
VDD#K7
VDD#K10
VSSQ#A10
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9
VSSQ#C10
VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9
L11
M1
L1
K1
K2
A11
G2
G11
A2
L10
M11
M_QSA2
A12
M_QSA1
G1
M_QSA3
G12
M_QSA0 M_QSA5
A1
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ
VSSQ
M_MDA16
A7
M_MDA17
B8
M_MDA18
A8
M_MDA19
A9
M_MDA20
B12
M_MDA21
C11
M_MDA22
C12
M_MDA23
D12
M_MDA8
J2
M_MDA13
J1
M_MDA14
H1
M_MDA12
H2
M_MDA15
F1
M_MDA11
F2
M_MDA9
E1
M_MDA10
E2
M_MDA25
E11
M_MDA24
E12
M_MDA28
F11
M_MDA27
F12
M_MDA30
H11
M_MDA31
H12
M_MDA26
J11
DQ9
M_MDA29
J12
DQ8
M_MDA3
D1
DQ7
M_MDA2
C1
DQ6
M_MDA0
C2
DQ5
M_MDA1
B1
DQ4
M_MDA4
A4
DQ3
M_MDA5
A5
DQ2
M_MDA6
B5
DQ1
M_MDA7
A6
DQ0
B2
B4
+MVDDQ +MVDDQ
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
VDD
VSS
+MVDDC +MVDDC
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
+VREF_U30+VREF_U29
M_MAA12
M_MAA13
M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0
M_CSA#1
M_CLKA#1
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_DQMA#6
M_DQMA#4
M_DQMA#7
M_DQMA#5
M_CLKA1
M_CKEA
M_QSA6
M_QSA4
M_QSA7
M3
M10
M9
M8
M7
M6
M5
M4
B10
G10
K11
K12
M2
L12
M12
L11
M1
A11
G11
L10
M11
A12
G12
L4
L6
K5
L7
L8
L5
B3
G3
L2
L3
L9
K8
L1
K1
K2
G2
A2
G1
A1
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8
U30
BA0
BA1
A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0
NC
NC#B10
NC#G3
NC#G10
NC#K11
NC#K12
NC#L2
NC#L3
NC#M2
MCL
VREF
RFU#L9
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE
DQS3
DQS2
DQS1
DQS0
TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8
1MX32X4
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9
VDDQ#B11
VDDQ#D2
VDDQ#D11
VDDQ#E3
VDDQ#E10
VDDQ#F3
VDDQ#F10
VDDQ#H3
VDDQ#H10
VDDQ#J3
VDDQ#J10
VDD#C7
VDD#D3
VDD#D10
VDD#K3
VDD#K6
VDD#K7
VDD#K10
VSSQ
VSSQ#A10
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9
VSSQ#C10
VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9
M_MDA48
A7
M_MDA49
B8
M_MDA50
A8
M_MDA51
A9
M_MDA55
B12
M_MDA52
C11
M_MDA54
C12
M_MDA53
D12
M_MDA33
J2
M_MDA32
J1
M_MDA35
H1
M_MDA34
H2
M_MDA37
F1
M_MDA36
F2
M_MDA39
E1
M_MDA38
E2
M_MDA56
E11
M_MDA57
E12
M_MDA58
F11
M_MDA59
F12
M_MDA60
H11
M_MDA61
H12
M_MDA62
J11
DQ9
M_MDA63
J12
DQ8
M_MDA41
D1
DQ7
M_MDA40
C1
DQ6
M_MDA47
C2
DQ5
M_MDA42
B1
DQ4
M_MDA46
A4
DQ3
M_MDA45
A5
DQ2
M_MDA43
B5
DQ1
M_MDA44
A6
DQ0
B2
B4
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
VDD
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
D4
VSS
D6
D7
D9
J5
J6
J7
J8
K4
K9
R60
C261
4.7K
100nF
402
402 402
X5R X5R
6.3V
+VREF_U29
C262
R61
100nF
4.7K
402
402
X5R
6.3V
Place these parts closed
to BGA1 reference
+MVDDQ+MVDDQ
C281
R62
100nF
4.7K
402
6.3V
+VREF_U30
R63
C282
4.7K
100nF
402
402
X5R
6.3V
Place these parts closed
to BGA2 reference
+MVDDQ
C204
C201
1uF
402
X5R X5R
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
+MVDDQ
C209
1uF
402 402 402402 402 402 402 402
X5R X5R X5R X5R X5R X5R X5RX5R
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
+MVDDC
C251
1uF
402 402 402402 402 402 402 402
X5R X5R X5R X5R X5R X5R X5RX5R
A A
8
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
Place these decoupling caps close to BGA1
Target each decoupling per associate power pin
C203
C202
1uF
1uF
X5R X5R X5R X5R X5R X5R
6.3V
C210
C211
1uF
1uF
C253
C252
1uF
1uF
7
C205
1uF
1uF
402 402402 402 402 402 402
C212
C213
1uF
1uF
C255
C254
1uF
1uF
C206
1uF
C214
1uF
C256
1uF
C207
1uF
C215
1uF
C257
1uF
C208
1uF
C216
1uF
6.3V
C258
1uF
6
+MVDDQ
C218
C217
1.0uF
1.0uF
603
603
Y5V
Y5V
10V
10V
+MVDDQ
C219
C220
1.0uF
1.0uF
603603
Y5V
Y5V
10V
10V
+MVDDC
C259
C260
1.0uF
1.0uF
603
603
Y5V
Y5V
10V
10V
Place these decoupling
caps close to BGA1
+MVDDQ
C222
C221
1uF
402 402 402402 402 402 402 402
X5R X5R X5R X5R X5R X5R X5RX5R
6.3V
+MVDDQ
C229
1uF
402 402 402402 402 402 402 402
X5R X5R X5R X5R X5R X5R X5RX5R
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
+MVDDC
C271
1uF
402 402 402402 402 402 402 402
X5R X5R X5R X5R X5R X5R X5RX5R
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
Place these decoupling caps close to BGA2
Target each decoupling per associate power pin
5
C223
1uF
1uF
6.3V 6.3V 6.3V
C230
C231
1uF
1uF
C273
C272
1uF
1uF
C224
1uF
C232
1uF
C274
1uF
C225
1uF
6.3V 6.3V
C233
1uF
C275
1uF
C227
C226
1uF
1uF
6.3V
C234
C235
1uF
1uF
C276
C277
1uF
1uF
4
C228
1uF
6.3V
C236
1uF
6.3V
C278
1uF
+MVDDQ
C237
C238
1.0uF
1.0uF
603
603
Y5V
Y5V
10V
10V
+MVDDQ
C239
C240
1.0uF
1.0uF
603603
Y5V
Y5V
10V
10V
+MVDDC
C280
C279
1.0uF
1.0uF
603
603
Y5V
Y5V
10V
10V
Place these decoupling
caps close to BGA2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
3
Date: Sheet
2
105-A628XX-00A
0
of
815Thursday, January 27, 2005
1
www.vinafix.vn
Page 10
8
7
6
5
4
3
2
1
GPIO0
OPTION STRAPS
+3.3V_BUS
D D
C C
Mem_Strap0(2)
Mem_Strap1(2)
B B
LCDDATA16(2)
LCDDATA17(2)
VHAD0(2)
A A
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO11
GPIO12
GPIO13
GPIO9
GPIO8
R201 10K
R202 10K
R203 10K
R204 10K
R205 10K
R206 10K
R207 10K
R208 10K
R219 10K
R220 10K
R221 10K
R222 10K
R223 10K
R224 10K
R209 10K
R210 10K
R211 10K
R212 10K
R213 10K
R214 10K
R215 10K
R216 10K
R217 10K
R218 10K
R235 10K
R236 10K
R237 10K
R238 10K
R227 10K
R228 10K
R229 10K
R230 10K
R231 10K
R232 10K
DESKTOP
MOBO
DESKTOP
MOBO
DNI
Tumwater
Grantsdale
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
+VDDR4
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
STRAPS
STRAP_B_PTX_PWRS_ENB
STRAP_B_PTX_DEEMPH_EN
PCIE_MODE(1:0)
STRAP_FORCE_COMPLIANCE
STRAP_B_PPLL_BW GPIO6
STRAP_DEBUG_ACCESS Strap to set the debug muxes to bring out DEBUG signals
ROMIDCFG(3:0)
STRAP P
INTERRUPT
LOW
ENABLED (DEFAULT)
DISABLED
HIGH
MEMORY TYPE STRAPS
Mem_Strap0 Mem_Strap1
SAM
00
INF
1
HYN
0
ELPIDA
11
GPIO[6..0]
GPIO[13..8]
0
1
GPIO[6..0] (2)
GPIO[13..8] (2)
DESCRIPTIONPIN
GPIO0
GPIO1
GPIO(3:2)
GPIO4
GPIO5
GPIO8
GPIO(9,13:11)
DVPDATA_20VIP_DEVICE Indicates if any slave VIP host devices drove this in low during reset.
(VHAD0 net)
Tansmitter Power Savings Enable
0: 50% Tx output swing for mobile mode
1: full Tx output swing
Transmitter De-emphasis Enable
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled
00: PCI Express 1.0A mode (Grantsdale)
01: Kyrene-compatible mode
10: PCI Express 1.0 mode (Tumwater)
11: PCI Express 1.0A mode and short-circuit internal loopback mode
(Rx connected directly to Tx of PHY)
Transmitter Extra Current
0: normal mode
1: extra current in Tx output stage - potential power savings for mobile mode
Force chip to go to Compliance state quickly for Tester purposes
0: normal operational mode
1: compliance mode
PLL Bandwidth
0: full PLL Bandwidth
1: reduced PLL bandwidth
even if registers are inaccessible.
If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type
0000 - No ROM, CHG_ID=0
0001 - No ROM, CHG_ID=1
0100 - reserved
0110 - reserved
1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P10 ROM (ST), chip IDis from ROM
1100 - Serial M25P05 ROM (ST), chip IDis from ROM
1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM
0 - Slave VIP host port devices present
1 - No slave VIP host port devices reporting presence during reset
GPIO8(2)
GPIO9(2)
GPIO10(2)
ROMCS#(3)
R91
10K
+3.3V_BUS
ASIC DEFAULT
0
0
00
0STRAP_B_PTX_IEXT
0
0
0
SERIAL EEPROM 512K
ROM_SO
SI/A16
SCK/WEb
CSb
HOLD1
+3.3V_BUS
C80
100nF
U11
5
D
6
C
1
S
7
HOLD
3
W
8
VCC
M25P05-AVMN6T
MU11
BIOS
113-A628xx-xxx
2
Q
4
VSS
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
105-A628XX-00A
0
of
915Thursday, January 27, 2005
1
www.vinafix.vn
Page 11
8
D D
7
6
5
4
3
2
1
Optional ESD/HotPlug Protection Diodes
BAT54SLT1
BAT54SLT1
2
D55
3
1
L51 47nH
L52 47nH
L53 47nH
C403
3.3pF
402 402 402
+5V
1
1
5
4
10
9
32
BSN20
Q51
32
BSN20
Q52
6
U6B
SN74ACT86D
8
U6C
SN74ACT86D
R405
6.8K
402
DDCDATA_DAC1_5V
R407
6.8K
402
DDCCLK_DAC1_5V
A_HSYNC_DAC1_B
A_VSYNC_DAC1_B
R401 75.0R
R402 75.0R
R403 75.0R
CRT1DDCDATA(1,2)
CRT1DDCCLK(1,2)
A_HSYNC_DAC1(1,2)
A_VSYNC_DAC1(1,2)
Pr
Y
Pb
C401
C402
3.3pF
3.3pF
402 402
402
+3.3V_BUS
R404
4.7K
402
+3.3V_BUS +5V
R406
4.7K
402 402
A_R_DAC1(2,11,13)
A_G_DAC1(2,11,13)
A_B_DAC1(2,11,13)
C C
RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane
B B
C404
8.0pF
L54 47nH
L55 47nH
L56 47nH
C406
C405
8.0pF
8.0pF
402
R415 33R
R416 33R
R413
R414
51R
51R
402
402
402
DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
Place close to the display connector
BAT54SLT1
2
D56
3
2
D57
3
1
1
C407
5pF
L60
82nH
+5V +5V+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V+5V
BAT54SLT1
BAT54SLT1
2
D51
3
1
C409
C408
5pF
5pF
L61
L62
82nH
82nH
805805805
BAT54SLT1
BAT54SLT1
2
D52
3
1
2
D53
3
2
D54
3
1
1
+5V_VESA
C441
68pF
603603 603 603
DB15 pin
Standard VGA
DDC1 Host
Monitor ID bit 0
11
12
4
15
9
Hardware
Support
Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997
Monitor ID bit 0
Monitor ID bit 1
Data from display
Monitor ID bit 2
Monitor ID bit 2
Monitor ID bit 3
Open
+5V
N/C
50mA min
Mechanical Key
1A max
No Yes Yes No Yes
J2
1
R
2
G
3
B
11
MS0
DDC2_MONID0
12
MS1
DDC2_MONID1(SDA)
4
MS2
DDC2_MONID2
15
MS3
DDC2_MONID3(SCL)
9
NC
13
HS
14
VS
5
VSS
6
VSS#6
7
VSS#7
8
VSS#8
10
VSS#10
16
CASE
17
CASE#17
Connector_DB15_Female_VGA_Blue
DDC2B or
DDC2AB Host
DDC2B+ Host
Monitor ID bit 0
Monitor ID bit 0
SDA
SDA
Monitor ID bit 2
Monitor ID bit 2
SCL
SCL
+5V
+5V
50mA min
300mA min
1A max
1A max
DDC1/2 Display
Optional
SDA
Optional
SCL
Optional
SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
105-A628XX-00A
0
of
10 15Thursday, January 27, 2005
1
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Page 12
8
7
6
5
4
3
2
1
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
+3.3V_BUS +3.3V_BUS +5V +5V+3.3V_BUS +5V+5V
BAT54SLT1
BAT54SLT1
D D
A_R_DVI-I (12)
A_G_DVI-I (12)
A_B_DVI-I (12)
C453
3.3pF
13
12
1
2
1
1
+5V
147
L71 47nH
L72 47nH
L73 47nH
R455
6.8K
402
DDCDATA_DAC2_5V
32
BSN20
Q71
R457
6.8K
DDCCLK_DAC2_5V
32
BSN20
Q72
A_HSYNC_DAC2_B
11
U6D
SN74ACT86D
SN74ACT86D
U6A
A_VSYNC_DAC2_B
3
A_R_DAC2(2,10,13)
A_G_DAC2(2,10,13)
A_B_DAC2(2,10,13)
C C
Pr
Y
Pb
R451 75.0R
R452 75.0R
R453 75.0R
402
RGB should be routed from the ASIC to the display connector without switching reference plane or running over split plane
DVIDDCDATA(2)
DVIDDCCLK(2)
A_HSYNC_DAC2(2)
A_VSYNC_DAC2(2)
C452
C451
3.3pF
3.3pF
+3.3V_BUS +5V
R454
4.7K
402
+3.3V_BUS +5V
R456
4.7K
402
C454
8.0pF
L74 47nH
L75 47nH
L76 47nH
C456
C455
8.0pF
8.0pF
402402
402402402 402
R465 33R
R466 33R
R463
R464
51R
51R
402
402402
402
402
DDCDATA_DAC2_R
DDCCLK_DAC2_R
A_HSYNC_DAC2_R
A_VSYNC_DAC2_R
A_R_DB15
A_G_DB15
A_B_DB15
DDCDATA_DVI-I_R (12)
DDCCLK_DVI-I_R (12)
A_HSYNC_DVI-I_R (12)
A_VSYNC_DVI-I_R (12)
D65
3
DDCDATA_DAC2_R
DDCCLK_DAC2_R
A_HSYNC_DAC2_R
A_VSYNC_DAC2_R
BAT54SLT1
2
2
D66
3
1
1
BAT54SLT1
BAT54SLT1
C459
5pF
L82
82nH
2
D61
3
2
D62
3
1
1
DNI
2
D67
3
1
C457
C458
5pF
5pF
L81
L80
82nH
82nH
BAT54SLT1
BAT54SLT1
2
2
D64
D63
3
3
1
1
C442
68pF
Close to
Connector
+5V_VESA2
6050003000 Old Slim-VGA connector
6052003000 New horizontally aligned Slim-VGA connector
MJ1
1
R
2
G
3
B
11
MS0
12
MS1
4
MS2
15
MS3
9
NC
13
HS
14
VS
5
VSS
6
VSS#6
7
VSS#7
8
VSS#8
10
VSS#10
16
CASE
17
CASE#17
SLIM VGA HT 6.27MM
DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)
Place close to CONNECTOR
DB15 pin
Standard VGA
DDC1 Host
Monitor ID bit 0
11
12
4
15
9
Hardware
Support
Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997
Monitor ID bit 0
Monitor ID bit 1
Data from display
Monitor ID bit 2
Monitor ID bit 2
Monitor ID bit 3
Open
+5V
N/C
50mA min
Mechanical Key
1A max
No Yes Yes No Yes
DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max
DDC2AB Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max
DDC1/2 Display
Optional
SDA
Optional
SCL
Optional
B B
+12V_BUS
Req = 120.8R
Use 845R, 1206, 1/4W
A A
8
R921
220R
7
R922
220R
R923
220R
R924
220R
R925
220R
REG20
TL431CDBVR
6
R953
220R
R954
220R
4
NC
1
NC
2
5 3
R918
1.0K
1%
402
R919
1.0K
1%
402
+5V_VESA2
Multi-footprint
C912
10uF_6.3V
MC912
4.7uF
5
Normal +5V regulated operation
This circuit provide upto 55mA
If Iload > 55mA, +5V will drop
If Vout is shorted
Current across each Rx is 12V/845R = 14.2mA
Power dissipated by each Rx is 14.2mA x 12V = 171mW
Each Rx are rated 250mW (1/4W)
Derating 250mW by 70% is 175mW (1/4W)
4
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
3
Date: Sheet
2
105-A628XX-00A
0
of
11 15Thursday, January 27, 2005
1
www.vinafix.vn
Page 13
5
4
3
2
1
PRIMARY DVI-I CONNECTOR
INSTALL TERMINATION RESISTORS CLOSE TO ASIC
R601 330R
D D
C C
TMDS_TX2N(2)
TMDS_TX2P(2)
TMDS_TX1N(2)
TMDS_TX1P(2)
TMDS_TX0N(2)
TMDS_TX0P(2)
TMDS_TXCP(2)
TMDS_TXCN(2)
DDCCLK_DVI-I_R(11)
DDCDATA_DVI-I_R(11)
402
R602 330R
402
R603 330R
402
R604 330R
402
DDCCLK_DVI-I
DDCDATA_DVI-I
A_VSYNC_DVI-I_R(11)
A_R_DVI-I(11)
A_G_DVI-I(11)
A_B_DVI-I(11)
Ra
R316 20K
Rc
A_HSYNC_DVI-I_R(11)
402
HPD_IntTMDS_DVI
LAYOUT NOTE: MAY REMOVE R605-R608 IF THERE'S NO SPACE!
+3.3V_BUS
R318
R317
20K
20K
Rb
CMPT3904
Q29
Qb
402
402 402
1
Q30
2 3
CMPT3904
1
2 3
Qa
R321
Rd
10K
402
HPD_IntTMDS(2)
HPD_IntTMDS
R326 0R
Re
+5V_VESA2
Pr
Y
Pb
C510
68pF
DNI
J1
25
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26
CASE#26
27
CASE#27
28
CASE#28
29
CASE#29
30
CASE#30
DVICONNECTOR
STUFFING OPTIONS
Hot-Plug Detect Circuit
Type A
B B
A A
5
Type B
NC High Z 0 (0V)
Connected 5V 1 (3.3V)
4
MUST INSTALL MUST NOT INSTALL
Ra, Rb, Rc,
Rd=0R, Qa, Qb
Ra=0R, Rc, Rd=10K,
Re, Qa
HPD_ExtTMDS_DVI
HPD_ExtTMDS
Type A
Re
Rb, Qb
HPD_ExtTMDS
Type B
0 (0V)
1 (3.3V)
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
C
3
2
Date: Sheet
105-A628XX-00A
1
0
of
12 15Thursday, January 27, 2005
www.vinafix.vn
Page 14
8
7
6
5
4
3
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1
From DAC2
R/C/Pr
D D
G/L/Y
B/COMP/Pb
C C
A_R/C/Pr_DAC2(2)
A_G/L/Y_DAC2(2)
A_B/COMP/Pb_DAC2(2)
+3.3V_BUS
R582
DEMUX_SEL-TVO/VGA#(2)
10K
A_R/C/Pr_DAC2
A_G/L/Y_DAC2
A_B/COMP/Pb_DAC2
DAC2 DeMux
U96
1
SEL
2
1A0
3
1A1
5
1B0
6
1B1
11
1C0
1C1101D0
15
E
PI5V330
To VGA Filters
A_R_DAC2
A_G_DAC2
+5V
C168
1uF
402
16
VCC
4
YA
7
YB
9
YC
12
YD
13
1D1
14
8
GND
A_B_DAC2
A_C/Pr_DAC2
A_L/Y_DAC2
A_COMP/Pb_DAC2
A_R_DAC2 (2,10,11)
A_G_DAC2 (2,10,11)
A_B_DAC2 (2,10,11)
To TVO filters
C/Pr
L/Y
COMP/Pb
R
G
B
DAC2 DeMux BYPASS
A_R_DAC2A_R/C/Pr_DAC2
R/C/Pr
G/L/Y
B/COMP/Pb
A_G/L/Y_DAC2
A_B/COMP/Pb_DAC2
R9280R
402402
R9290R
402
R9300R
402
R9700R
402
R9710R
402
R9720R
402
A_COMP/Pb_DAC2
A_G_DAC2
A_B_DAC2
A_C/Pr_DAC2
A_L/Y_DAC2
R/Pr
G/Y
B/Pb
C/Pr
L/Y
COMP/Pb
Place Resistors close to ASIC.
A_L/Y_DAC2
R504
75.0R
402
A_C/Pr_DAC2
R505
75.0R
402
B B
A_COMP/Pb_DAC2
R506
75.0R
402
L91
.47uH
C501
47PF
402 402
L92
.47uH
C503
47PF
L93
.47uH
C505
47PF
C502
47PF
C504
47PF
402402
C506
47PF
402402
A_L_DAC2_F
A_C_DAC2_F
A_COMP_DAC2_F
Place near connector
0R leaves footprint for Ferrite
Beads if req'd for EMI
402
R519 0R
R520 0R
R521 0R
A_L_DAC2_DIN
402
A_C_DAC2_DIN
402
A_COMP_DAC2_DIN
C507
82pF
C508
82pF
C509
82pF
402402 402
+3.3V_BUS
R578
10K
SVHS/YPrPbb(2)
R515
0R
402
R377 0R
TV Out (SVHS)
PIN6
402
6
3
4
PIN7
7
PIN5
5
1
2
8
9
10
J6
+12V
Y-OUT
C-OUT
Comp_out
SYNC
GND
GND#2
CASE
CASE#9
CASE#10
Connector_DIN_Miniature_Circular_7_Pin
The 7-pin MiniDIN footprint allows one of the two MiniDINs:
- 7-pin Svideo/Composite MiniDIN P/N 6071001500
- 4-pin Svideo MiniDIN P/N 6070001000
MJ6
PIN7
A A
8
7
6
5
4
Jack_Phono_RCA
1
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
3
Date: Sheet
2
105-A628XX-00A
0
of
13 15Thursday, January 27, 2005
1
www.vinafix.vn
Page 15
5
4
3
2
1
DVI/VGA SCREWS MISC. BOARD PARTS
ASSY1
SCREW
JACKSCREW
D D
C C
B B
ASSY2
ASSY15
ASSY16
SCREW
JACKSCREW
SCREW
JACKSCREW
SCREW
JACKSCREW
MT1
MT_Hole_0.136_in.
Bracket Screws
ASSY3
SCREW
PAN_HEAD
ASSY7
ANTISTATIC
BAG
6_X_11
9040000900
ASSY6
ANTISTATIC
BAG
6_X_11
9040000900
ASSY8
BLANK
LABEL
9050005900
ASSY9
2"_X_0.25"
9050004600
LABEL
ASSY5
ATI LOGO
LABEL
ATI_LOGO_LABEL
9110054500
ATX Brackets
ASSY14
BRACKET
DVI, DIN, VGA
8020037000
ASSY11
BRACKET
DVI, VGA
80200370A0
ASSY10
ATI LOGO
LABEL
ATI_LOGO_LABEL
9110054500
ASSY12
VGA, DIN, VGA
8020037100
ASSY13
80200371A0
BRACKET
BRACKET
+12V_BUS
H101
1
2
JU1
heatsink
7120005800
MH101
HEATSINK
7120002700
H100
HEATSINK
7120005100
Spring push-pin
MH100
HEATSINK
7120008000
ITW push-pin
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
105-A628XX-00A
1
0
of
14 15Thursday, January 27, 2005
www.vinafix.vn
Page 16
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4
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2
1
MEMORY CHANNEL A
D D
BGA 2/4Mx32 Memory
MEMORY TERMINATIONS A
VGA
DB15
CONN
MEM A
PRIMARY CRT
LOGIC
CLOCK
C C
DAC1
DVI-I CONN
TMDS
INTEGRATED TMDS
LOGIC
STRAPS
BIOS
ROM
BY PASS option
B B
POWER
REGULATION
RV370
AGP
DAC2
LCDDATA19
SEL
D
E
TVOUT Filters
M
VO
CONN
U
X
Secondary
CRT LOGIC
and/or VGA Slim
DB15 CONN
A A
PCI-Express
5
4
REFERENCE
DESIGN
THESE SCHEMATICS ARE
SUBJECT TO MODIFICATION
AND DESIGN IMPROVEMENTS.
PLEASE CONTACT ATI FIELD
APPLICATION ENGINEERING
BEFORE USING THE INFORMATION CONTAINED HEREIN.
3
RESTRICTION
NOTICE
THESE SCHEMATICS CONTAIN
INFORMATION WHICH IS PROPRIETARY
TO AND IS THE PROPERTY OF ATI, AND
MAY NOT BE USED, REPRODUCED OR
DISCLOSED IN ANY MANNER WITHOUT
EXPRESSED WRITTEN PERMISSION
FROM ATI.
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIE RV370 64-bit 32/64MB BGA DI-VO-V LS
Size Document Number Rev
B
2
Date: Sheet
105-A628XX-00A
1
of
15 15Thursday, January 27, 2005
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